[llvm] 8246715 - AMDGPU/GlobalISel: RegBankLegalize rules for add_min/max intrinsics (#192356)

[via llvm-commits]

Author: vangthao95
Date: 2026-04-16T08:44:45-07:00
New Revision: 82467159043f3007e41e81fb921c81beaa234a14

URL: https://github.com/llvm/llvm-project/commit/82467159043f3007e41e81fb921c81beaa234a14
DIFF: https://github.com/llvm/llvm-project/commit/82467159043f3007e41e81fb921c81beaa234a14.diff

LOG: AMDGPU/GlobalISel: RegBankLegalize rules for add_min/max intrinsics (#192356)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 8028a4cb7c878..8bd406764e64c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1621,6 +1621,18 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
            {{VgprB32},
             {IntrId, SgprB32_ReadFirstLane, SgprB32_ReadFirstLane, VgprB32}});
 
+  addRulesForIOpcs({amdgcn_add_max_i32, amdgcn_add_max_u32, amdgcn_add_min_i32,
+                    amdgcn_add_min_u32},
+                   Standard)
+      .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
+      .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
+
+  addRulesForIOpcs({amdgcn_pk_add_max_i16, amdgcn_pk_add_max_u16,
+                    amdgcn_pk_add_min_i16, amdgcn_pk_add_min_u16},
+                   Standard)
+      .Uni(V2S16, {{UniInVgprV2S16}, {IntrId, VgprV2S16, VgprV2S16, VgprV2S16}})
+      .Div(V2S16, {{VgprV2S16}, {IntrId, VgprV2S16, VgprV2S16, VgprV2S16}});
+
   addRulesForIOpcs({amdgcn_permlane16, amdgcn_permlanex16}, Standard)
       .Div(S32, {{Vgpr32},
                  {IntrId, Vgpr32, Vgpr32, SgprB32_ReadFirstLane,

diff  --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
index 99421d4a9b5c9..36d96dc738450 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250-GISEL %s
 
 declare i32 @llvm.amdgcn.add.min.i32(i32, i32, i32, i1)
 declare i32 @llvm.amdgcn.add.max.i32(i32, i32, i32, i1)