[llvm] [AMDGPU] Add llvm.amdgcn.s.prefetch.inst intrinsic (PR #192440)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 16 07:52:39 PDT 2026
================
@@ -0,0 +1,236 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,GFX12,GFX12-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,GFX1250,GFX1250-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,GFX1250,GFX1250-GISEL %s
+
+define amdgpu_ps void @prefetch_inst_sgpr_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) {
+; GFX12-LABEL: prefetch_inst_sgpr_base_sgpr_len:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: prefetch_inst_sgpr_base_sgpr_len:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
+; GFX1250-NEXT: s_endpgm
+ tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 %len)
+ ret void
+}
+
+define amdgpu_ps void @prefetch_inst_sgpr_imm_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) {
+; GFX12-LABEL: prefetch_inst_sgpr_imm_base_sgpr_len:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x200, s2, 0
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: prefetch_inst_sgpr_imm_base_sgpr_len:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x200, s2, 0
+; GFX1250-NEXT: s_endpgm
+ %gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
+ tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %gep, i32 %len)
+ ret void
+}
+
+define amdgpu_ps void @prefetch_inst_sgpr_base_imm_len(ptr addrspace(4) inreg %ptr) {
+; GFX12-LABEL: prefetch_inst_sgpr_base_imm_len:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: prefetch_inst_sgpr_base_imm_len:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
+; GFX1250-NEXT: s_endpgm
+ tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 31)
+ ret void
+}
+
+define amdgpu_ps void @prefetch_inst_sgpr_imm_base_imm_len(ptr addrspace(4) inreg %ptr) {
+; GFX12-LABEL: prefetch_inst_sgpr_imm_base_imm_len:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x200, null, 31
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: prefetch_inst_sgpr_imm_base_imm_len:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x200, null, 31
+; GFX1250-NEXT: s_endpgm
+ %gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
+ tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %gep, i32 31)
+ ret void
+}
+
+define amdgpu_ps void @prefetch_inst_vgpr_base_sgpr_len(ptr addrspace(4) %ptr, i32 inreg %len) {
+; GFX12-LABEL: prefetch_inst_vgpr_base_sgpr_len:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: prefetch_inst_vgpr_base_sgpr_len:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1250-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
+; GFX1250-NEXT: s_endpgm
+ tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 %len)
+ ret void
+}
+
+define amdgpu_ps void @prefetch_inst_vgpr_imm_base_sgpr_len(ptr addrspace(4) %ptr, i32 inreg %len) {
+; GFX12-SDAG-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-SDAG-NEXT: s_prefetch_inst s[2:3], 0x200, s0, 0
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x200, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
+; GFX12-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1250-SDAG-NEXT: s_prefetch_inst s[2:3], 0x200, s0, 0
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x200, v0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1250-GISEL-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
+; GFX1250-GISEL-NEXT: s_endpgm
+ %gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
+ tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %gep, i32 %len)
+ ret void
+}
+
+define amdgpu_ps void @prefetch_inst_sgpr_base_vgpr_len(ptr addrspace(4) inreg %ptr, i32 %len) {
+; GFX12-LABEL: prefetch_inst_sgpr_base_vgpr_len:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: prefetch_inst_sgpr_base_vgpr_len:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
+; GFX1250-NEXT: s_endpgm
+ tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 %len)
+ ret void
+}
+
+define amdgpu_ps void @prefetch_inst_sgpr_base_imm_len_global(ptr addrspace(1) inreg %ptr) {
+; GFX12-LABEL: prefetch_inst_sgpr_base_imm_len_global:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: prefetch_inst_sgpr_base_imm_len_global:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
+; GFX1250-NEXT: s_endpgm
+ tail call void @llvm.amdgcn.s.prefetch.inst.p1(ptr addrspace(1) %ptr, i32 31)
+ ret void
+}
+
+define amdgpu_ps void @prefetch_inst_sgpr_base_imm_len_flat(ptr inreg %ptr) {
+; GFX12-LABEL: prefetch_inst_sgpr_base_imm_len_flat:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: prefetch_inst_sgpr_base_imm_len_flat:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
+; GFX1250-NEXT: s_endpgm
+ tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr %ptr, i32 31)
+ ret void
+}
+
+define amdgpu_ps void @prefetch_inst_vgpr_base_imm_len(ptr addrspace(4) %ptr) {
+; GFX12-LABEL: prefetch_inst_vgpr_base_imm_len:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: prefetch_inst_vgpr_base_imm_len:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
+; GFX1250-NEXT: s_endpgm
+ tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 0)
+ ret void
+}
+
+define amdgpu_ps void @prefetch_inst_vgpr_base_vgpr_len(ptr addrspace(4) %ptr, i32 %len) {
+; GFX12-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
+; GFX12-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
+; GFX1250-GISEL-NEXT: s_endpgm
+ tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 %len)
+ ret void
+}
+
----------------
arsenm wrote:
Should make sure 0 and 1 work. Might also be worth testing a blockaddress use?
https://github.com/llvm/llvm-project/pull/192440
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