[llvm] [AArch64] Improve fixed vector lowering for cttz/ctlz when sve (PR #192427)

[Yashwant Singh via llvm-commits]

yashssh wrote:

I asked LLMs to create the benchmarks, that's how they look like 

```

static inline uint64x2_t ctlz_u64x2(uint64x2_t x){ return __builtin_elementwise_clzg(x); }

static void bench_u64x2(void) {
    volatile uint64x2_t seed =
        (uint64x2_t){1,16};

    uint64x2_t local_seed = seed;
    uint64x2_t x = local_seed;

    for (int i=0;i<WARMUP;i++){ x = ctlz_u64x2(x); x ^= local_seed; }

    uint64_t start = now_ns();

    for (int i=0;i<ITERS;i++){ x = ctlz_u64x2(x); x ^= local_seed; }

    uint64_t end = now_ns();

    sink ^= vgetq_lane_u64(x,0);
    printf("ctlz_u64x2: %.6f sec\n",(end-start)/1e9);
}

```
Ran before and after the patch

https://github.com/llvm/llvm-project/pull/192427