[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Sushant Gokhale via llvm-commits]

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@@ -0,0 +1,138 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 --aarch64-sve-vector-bits-min=256 -o - < %s | FileCheck %s
+
+define <vscale x 16 x i8> @zext_slt_test1(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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sushgokh wrote:

> I think @rj-jesus means the type of the overall pattern you're matching so varying that makes sense because it ensures the combine is using the correct type when creating the new zext.

Uptil now, I was writing the combine at very late just before isel. But if I write it early, as cited [here](https://github.com/llvm/llvm-project/pull/192405#pullrequestreview-4119061447),  then I suppose its irrelevant ?

https://github.com/llvm/llvm-project/pull/192405