[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Paul Walker via llvm-commits]

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@@ -0,0 +1,138 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 --aarch64-sve-vector-bits-min=256 -o - < %s | FileCheck %s
+
+define <vscale x 16 x i8> @zext_slt_test1(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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paulwalker-arm wrote:

I think @rj-jesus means the type of the overall pattern you're matching so varying that makes sense because it ensure the combine is using the correct types when creating the new zext.

https://github.com/llvm/llvm-project/pull/192405