[llvm] [llvm][RISCV] Handle miscompile of fma in zvfbfa codegen (PR #192412)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 16 02:09:08 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Brandon Wu (4vtomat)
<details>
<summary>Changes</summary>
---
Patch is 43.07 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/192412.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td (+14-10)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td (+3-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll (+40-40)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll (+40-40)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 4c558c4524c5b..9fdb7a19d9ce9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -691,6 +691,7 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name,
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_sameuser
@@ -700,7 +701,7 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name,
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector wti.RegClass:$rd)),
- (!cast<Instruction>(instruction_name#"_VV_"#suffix)
+ (!cast<Instruction>(instruction_name#alt#"_VV_"#suffix)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
@@ -712,7 +713,7 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name,
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector wti.RegClass:$rd)),
- (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
+ (!cast<Instruction>(instruction_name#alt#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
@@ -727,6 +728,7 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
@@ -735,7 +737,7 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue)),
(fneg wti.RegClass:$rd)),
- (!cast<Instruction>(instruction_name#"_VV_"#suffix)
+ (!cast<Instruction>(instruction_name#alt#"_VV_"#suffix)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
@@ -746,7 +748,7 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(fneg wti.RegClass:$rd)),
- (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
+ (!cast<Instruction>(instruction_name#alt#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
@@ -756,7 +758,7 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue)),
(fneg wti.RegClass:$rd)),
- (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
+ (!cast<Instruction>(instruction_name#alt#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
@@ -771,6 +773,7 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_sameuser
@@ -779,7 +782,7 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
(riscv_fpextend_vl_sameuser (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue)),
(fneg wti.RegClass:$rd)),
- (!cast<Instruction>(instruction_name#"_VV_"#suffix)
+ (!cast<Instruction>(instruction_name#alt#"_VV_"#suffix)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
@@ -789,7 +792,7 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue)),
(fneg wti.RegClass:$rd)),
- (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
+ (!cast<Instruction>(instruction_name#alt#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
@@ -804,6 +807,7 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
@@ -812,7 +816,7 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue)),
wti.RegClass:$rd),
- (!cast<Instruction>(instruction_name#"_VV_"#suffix)
+ (!cast<Instruction>(instruction_name#alt#"_VV_"#suffix)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
@@ -823,7 +827,7 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue)))),
wti.RegClass:$rd),
- (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
+ (!cast<Instruction>(instruction_name#alt#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
@@ -833,7 +837,7 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue)),
wti.RegClass:$rd),
- (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
+ (!cast<Instruction>(instruction_name#alt#"_V"#vti.ScalarSuffix#"_"#suffix)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 2a99492bc5596..9e3df3dc6c714 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -1876,13 +1876,14 @@ multiclass VPatWidenFPMulAccVL_VV_VF_RM<SDNode vop, string instruction_name,
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
+ defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", "");
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
def : Pat<(vop (vti.Vector vti.RegClass:$rs1),
(vti.Vector vti.RegClass:$rs2),
(wti.Vector wti.RegClass:$rd), (vti.Mask VMV0:$vm),
VLOpFrag),
- (!cast<Instruction>(instruction_name#"_VV_"#suffix#"_MASK")
+ (!cast<Instruction>(instruction_name#alt#"_VV_"#suffix#"_MASK")
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask VMV0:$vm),
// Value to indicate no rounding mode change in
@@ -1893,7 +1894,7 @@ multiclass VPatWidenFPMulAccVL_VV_VF_RM<SDNode vop, string instruction_name,
(vti.Vector vti.RegClass:$rs2),
(wti.Vector wti.RegClass:$rd), (vti.Mask VMV0:$vm),
VLOpFrag),
- (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix#"_MASK")
+ (!cast<Instruction>(instruction_name#alt#"_V"#vti.ScalarSuffix#"_"#suffix#"_MASK")
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask VMV0:$vm),
// Value to indicate no rounding mode change in
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
index c58520b640521..de4e5a9906158 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
@@ -2084,7 +2084,7 @@ define <1 x float> @vfwmaccbf16_vv_v1f32(<1 x float> %va, <1 x bfloat> %vb, <1 x
;
; ZVFBFA-LABEL: vfwmaccbf16_vv_v1f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwmacc.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <1 x bfloat> %vb to <1 x float>
@@ -2107,7 +2107,7 @@ define <1 x float> @vfwmaccbf16_vf_v1f32(<1 x float> %va, <1 x bfloat> %vb, bflo
;
; ZVFBFA-LABEL: vfwmaccbf16_vf_v1f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwmacc.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <1 x bfloat> poison, bfloat %c, i32 0
@@ -2130,7 +2130,7 @@ define <1 x float> @vfwnmaccbf16_vv_v1f32(<1 x float> %va, <1 x bfloat> %vb, <1
;
; ZVFBFA-LABEL: vfwnmaccbf16_vv_v1f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwnmacc.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <1 x bfloat> %vb to <1 x float>
@@ -2155,7 +2155,7 @@ define <1 x float> @vfwnmaccbf16_vf_v1f32(<1 x float> %va, <1 x bfloat> %vb, bfl
;
; ZVFBFA-LABEL: vfwnmaccbf16_vf_v1f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwnmacc.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <1 x bfloat> poison, bfloat %c, i32 0
@@ -2180,7 +2180,7 @@ define <1 x float> @vfwmsacbf16_vv_v1f32(<1 x float> %va, <1 x bfloat> %vb, <1 x
;
; ZVFBFA-LABEL: vfwmsacbf16_vv_v1f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwmsac.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <1 x bfloat> %vb to <1 x float>
@@ -2204,7 +2204,7 @@ define <1 x float> @vfwmsacbf16_vf_v1f32(<1 x float> %va, <1 x bfloat> %vb, bflo
;
; ZVFBFA-LABEL: vfwmsacbf16_vf_v1f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwmsac.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <1 x bfloat> poison, bfloat %c, i32 0
@@ -2228,7 +2228,7 @@ define <1 x float> @vfwnmsacbf16_vv_v1f32(<1 x float> %va, <1 x bfloat> %vb, <1
;
; ZVFBFA-LABEL: vfwnmsacbf16_vv_v1f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwnmsac.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <1 x bfloat> %vb to <1 x float>
@@ -2252,7 +2252,7 @@ define <1 x float> @vfwnmsacbf16_vf_v1f32(<1 x float> %va, <1 x bfloat> %vb, bfl
;
; ZVFBFA-LABEL: vfwnmsacbf16_vf_v1f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwnmsac.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <1 x bfloat> poison, bfloat %c, i32 0
@@ -2276,7 +2276,7 @@ define <2 x float> @vfwmaccbf16_vv_v2f32(<2 x float> %va, <2 x bfloat> %vb, <2 x
;
; ZVFBFA-LABEL: vfwmaccbf16_vv_v2f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwmacc.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <2 x bfloat> %vb to <2 x float>
@@ -2299,7 +2299,7 @@ define <2 x float> @vfwmaccbf16_vf_v2f32(<2 x float> %va, <2 x bfloat> %vb, bflo
;
; ZVFBFA-LABEL: vfwmaccbf16_vf_v2f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwmacc.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <2 x bfloat> poison, bfloat %c, i32 0
@@ -2322,7 +2322,7 @@ define <2 x float> @vfwnmaccbf16_vv_v2f32(<2 x float> %va, <2 x bfloat> %vb, <2
;
; ZVFBFA-LABEL: vfwnmaccbf16_vv_v2f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwnmacc.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <2 x bfloat> %vb to <2 x float>
@@ -2347,7 +2347,7 @@ define <2 x float> @vfwnmaccbf16_vf_v2f32(<2 x float> %va, <2 x bfloat> %vb, bfl
;
; ZVFBFA-LABEL: vfwnmaccbf16_vf_v2f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwnmacc.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <2 x bfloat> poison, bfloat %c, i32 0
@@ -2372,7 +2372,7 @@ define <2 x float> @vfwmsacbf16_vv_v2f32(<2 x float> %va, <2 x bfloat> %vb, <2 x
;
; ZVFBFA-LABEL: vfwmsacbf16_vv_v2f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwmsac.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <2 x bfloat> %vb to <2 x float>
@@ -2396,7 +2396,7 @@ define <2 x float> @vfwmsacbf16_vf_v2f32(<2 x float> %va, <2 x bfloat> %vb, bflo
;
; ZVFBFA-LABEL: vfwmsacbf16_vf_v2f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwmsac.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <2 x bfloat> poison, bfloat %c, i32 0
@@ -2420,7 +2420,7 @@ define <2 x float> @vfwnmsacbf16_vv_v2f32(<2 x float> %va, <2 x bfloat> %vb, <2
;
; ZVFBFA-LABEL: vfwnmsacbf16_vv_v2f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwnmsac.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <2 x bfloat> %vb to <2 x float>
@@ -2444,7 +2444,7 @@ define <2 x float> @vfwnmsacbf16_vf_v2f32(<2 x float> %va, <2 x bfloat> %vb, bfl
;
; ZVFBFA-LABEL: vfwnmsacbf16_vf_v2f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
; ZVFBFA-NEXT: vfwnmsac.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <2 x bfloat> poison, bfloat %c, i32 0
@@ -2468,7 +2468,7 @@ define <4 x float> @vfwmaccbf16_vv_v4f32(<4 x float> %va, <4 x bfloat> %vb, <4 x
;
; ZVFBFA-LABEL: vfwmaccbf16_vv_v4f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
; ZVFBFA-NEXT: vfwmacc.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <4 x bfloat> %vb to <4 x float>
@@ -2491,7 +2491,7 @@ define <4 x float> @vfwmaccbf16_vf_v4f32(<4 x float> %va, <4 x bfloat> %vb, bflo
;
; ZVFBFA-LABEL: vfwmaccbf16_vf_v4f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
; ZVFBFA-NEXT: vfwmacc.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <4 x bfloat> poison, bfloat %c, i32 0
@@ -2514,7 +2514,7 @@ define <4 x float> @vfwnmaccbf16_vv_v4f32(<4 x float> %va, <4 x bfloat> %vb, <4
;
; ZVFBFA-LABEL: vfwnmaccbf16_vv_v4f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
; ZVFBFA-NEXT: vfwnmacc.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <4 x bfloat> %vb to <4 x float>
@@ -2539,7 +2539,7 @@ define <4 x float> @vfwnmaccbf16_vf_v4f32(<4 x float> %va, <4 x bfloat> %vb, bfl
;
; ZVFBFA-LABEL: vfwnmaccbf16_vf_v4f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
; ZVFBFA-NEXT: vfwnmacc.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <4 x bfloat> poison, bfloat %c, i32 0
@@ -2564,7 +2564,7 @@ define <4 x float> @vfwmsacbf16_vv_v4f32(<4 x float> %va, <4 x bfloat> %vb, <4 x
;
; ZVFBFA-LABEL: vfwmsacbf16_vv_v4f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
; ZVFBFA-NEXT: vfwmsac.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <4 x bfloat> %vb to <4 x float>
@@ -2588,7 +2588,7 @@ define <4 x float> @vfwmsacbf16_vf_v4f32(<4 x float> %va, <4 x bfloat> %vb, bflo
;
; ZVFBFA-LABEL: vfwmsacbf16_vf_v4f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
; ZVFBFA-NEXT: vfwmsac.vf v8, fa0, v9
; ZVFBFA-NEXT: ret
%head = insertelement <4 x bfloat> poison, bfloat %c, i32 0
@@ -2612,7 +2612,7 @@ define <4 x float> @vfwnmsacbf16_vv_v4f32(<4 x float> %va, <4 x bfloat> %vb, <4
;
; ZVFBFA-LABEL: vfwnmsacbf16_vv_v4f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
; ZVFBFA-NEXT: vfwnmsac.vv v8, v9, v10
; ZVFBFA-NEXT: ret
%vd = fpext <4 x bfloat> %vb to <4 x float>
@@ -2636,7 +2636,7 @@ define <4 x float> @vfwnmsacbf16_vf_v4f32(<4 x float> %va, <4 x bfloat> %vb, bfl
;
; ZVFBFA-LABEL: vfwnmsacbf16_vf_v4f32:
; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+;...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/192412
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