[llvm] [AArch64][SelectionDAG][SVE] Fold following extend(icmp) patterns (PR #192052)

[Ricardo Jesus via llvm-commits]

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@@ -24422,6 +24437,105 @@ static SDValue performExtendCombine(SDNode *N,
                                     TargetLowering::DAGCombinerInfo &DCI,
                                     SelectionDAG &DAG,
                                     const AArch64Subtarget *Subtarget) {
+  // sext(icmp slt a, b) --> asr (shsub a, b), bitwidth-1
+  // sext(icmp ult a, b) --> asr (uhsub a, b), bitwidth-1
+  // zext(icmp slt a, b) --> lsr (shsub a, b), bitwidth-1
+  // zext(icmp ult a, b) --> lsr (uhsub a, b), bitwidth-1
+  // sext(icmp sgt a, b) --> asr (shsub b, a), bitwidth-1
+  // sext(icmp ugt a, b) --> asr (uhsub b, a), bitwidth-1
+  // zext(icmp sgt a, b) --> lsr (shsub b, a), bitwidth-1
+  // zext(icmp ugt a, b) --> lsr (uhsub b, a), bitwidth-1
+  SDValue Compare = N->getOperand(0);
+  SDLoc DL(N);
+  if (Compare.getOpcode() == AArch64ISD::SETCC_MERGE_ZERO &&
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rj-jesus wrote:

What I meant was, you need to check that the compare predicate is all-true. The new instructions may no longer zero the false lanes.

I think the combine isn't beneficial if the compare instruction isn't removed. Is making the compare one-use a problem for what you're trying to do?

https://github.com/llvm/llvm-project/pull/192052