[llvm] 3a754f4 - [LoongArch][NFC] Pre-commit tests for `vextrins` (#164065)

[via llvm-commits]

Author: ZhaoQi
Date: 2026-04-16T08:21:08Z
New Revision: 3a754f4b9e852fc9c765f1152dc9a11d93cb83b1

URL: https://github.com/llvm/llvm-project/commit/3a754f4b9e852fc9c765f1152dc9a11d93cb83b1
DIFF: https://github.com/llvm/llvm-project/commit/3a754f4b9e852fc9c765f1152dc9a11d93cb83b1.diff

LOG: [LoongArch][NFC] Pre-commit tests for `vextrins` (#164065)

Added: 
    llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vextrins.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vextrins.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vextrins.ll
new file mode 100644
index 0000000000000..a504067772e81
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vextrins.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx %s -o - | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
+
+;; vextrins.b
+define void @shufflevector_v16i8(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: shufflevector_v16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a1, 0
+; CHECK-NEXT:    vld $vr1, $a2, 0
+; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI0_0)
+; CHECK-NEXT:    vld $vr2, $a1, %pc_lo12(.LCPI0_0)
+; CHECK-NEXT:    vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT:    vst $vr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %va = load <16 x i8>, ptr %a
+  %vb = load <16 x i8>, ptr %b
+  %c = shufflevector <16 x i8> %va, <16 x i8> %vb, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 16>
+  store <16 x i8> %c, ptr %res
+  ret void
+}
+
+;; vextrins.h
+define void @shufflevector_v8i16(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: shufflevector_v8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a1, 0
+; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT:    vld $vr1, $a1, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT:    vshuf.h $vr1, $vr0, $vr0
+; CHECK-NEXT:    vst $vr1, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %va = load <8 x i16>, ptr %a
+  %vb = load <8 x i16>, ptr %b
+  %c = shufflevector <8 x i16> %va, <8 x i16> %vb, <8 x i32> <i32 0, i32 1, i32 2, i32 5, i32 4, i32 5, i32 6, i32 7>
+  store <8 x i16> %c, ptr %res
+  ret void
+}
+
+;; vextrins.w
+define void @shufflevector_v4i32(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: shufflevector_v4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a1, 0
+; CHECK-NEXT:    vld $vr1, $a2, 0
+; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI2_0)
+; CHECK-NEXT:    vld $vr2, $a1, %pc_lo12(.LCPI2_0)
+; CHECK-NEXT:    vshuf.w $vr2, $vr1, $vr0
+; CHECK-NEXT:    vst $vr2, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %va = load <4 x i32>, ptr %a
+  %vb = load <4 x i32>, ptr %b
+  %c = shufflevector <4 x i32> %va, <4 x i32> %vb, <4 x i32> <i32 3, i32 5, i32 6, i32 7>
+  store <4 x i32> %c, ptr %res
+  ret void
+}
+
+;; vextrins.w
+define void @shufflevector_v4f32(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: shufflevector_v4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a1, 0
+; CHECK-NEXT:    vld $vr1, $a2, 0
+; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT:    vld $vr2, $a1, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT:    vshuf.w $vr2, $vr1, $vr0
+; CHECK-NEXT:    vst $vr2, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %va = load <4 x float>, ptr %a
+  %vb = load <4 x float>, ptr %b
+  %c = shufflevector <4 x float> %va, <4 x float> %vb, <4 x i32> <i32 4, i32 5, i32 6, i32 2>
+  store <4 x float> %c, ptr %res
+  ret void
+}