[llvm] [AArch64][SelectionDAG][SVE] Fold following extend(icmp) patterns (PR #192052)

[Sushant Gokhale via llvm-commits]

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@@ -20941,6 +20941,22 @@ static SDValue performSVEAndCombine(SDNode *N,
   SDValue Src = N->getOperand(0);
   unsigned Opc = Src->getOpcode();
 
+  // and(splat(1), sext(setcc_merge_zero)) -> zext(setcc_merge_zero)
+  SDLoc DL(N);
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+  if (Op0.getOpcode() == ISD::SPLAT_VECTOR ||
+      Op1.getOpcode() == ISD::SPLAT_VECTOR) {
+    SDValue NonSplatOp = (Op0.getOpcode() == ISD::SPLAT_VECTOR ? Op1 : Op0);
+    SDValue SplatOp = (Op0.getOpcode() == ISD::SPLAT_VECTOR ? Op0 : Op1);
+    if (NonSplatOp.getOpcode() == ISD::SIGN_EXTEND) {
+      SDValue Compare = NonSplatOp.getOperand(0);
+      if (Compare.getOpcode() == AArch64ISD::SETCC_MERGE_ZERO) {
+        return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0), Compare);
+      }
+    }
+  }
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sushgokh wrote:

Considering the  zext patterns in this patch.

Type legalization happens on the `cmp` and `zext` is split into `and(splat(1), sext(setcc_merge_zero))`. So, before isel, what you see for `zext` is `and(splat(1), sext(setcc_merge_zero))`
So, the change does fold `and(...)` into `zext` again and thus acts as enabler for foldings in the current patch.

Also, not only its enabler for the current patch but producer better codegen.

I will split this patch and put this zext enabler in different patch. That should ease out things

https://github.com/llvm/llvm-project/pull/192052