[llvm] c87a60f - [RISCV] Replace Unsigned flag in generateInstSeqImpl with ShiftOpc. NFC (#192363)
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Wed Apr 15 19:46:41 PDT 2026
Author: Craig Topper
Date: 2026-04-15T19:46:37-07:00
New Revision: c87a60f617dd43d27a10a9dcf0349b2327568c3b
URL: https://github.com/llvm/llvm-project/commit/c87a60f617dd43d27a10a9dcf0349b2327568c3b
DIFF: https://github.com/llvm/llvm-project/commit/c87a60f617dd43d27a10a9dcf0349b2327568c3b.diff
LOG: [RISCV] Replace Unsigned flag in generateInstSeqImpl with ShiftOpc. NFC (#192363)
Changed ShiftAmount from int to unsigned.
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index f3443469f6364..26566e95b2bc5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -174,8 +174,8 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
int64_t Lo12 = SignExtend64<12>(Val);
Val = (uint64_t)Val - (uint64_t)Lo12;
- int ShiftAmount = 0;
- bool Unsigned = false;
+ unsigned ShiftAmount = 0;
+ unsigned ShiftOpc = RISCV::SLLI;
// Val might now be valid for LUI without needing a shift.
if (!isInt<32>(Val)) {
@@ -197,7 +197,7 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
// LUI, then shift left with SLLI.UW to clear the upper 32 set bits.
ShiftAmount -= 12;
Val = SignExtend64<32>((uint64_t)Val << 12);
- Unsigned = true;
+ ShiftOpc = RISCV::SLLI_UW;
}
}
@@ -207,7 +207,7 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
// Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with
// SLLI_UW.
Val = SignExtend64<32>((uint64_t)Val);
- Unsigned = true;
+ ShiftOpc = RISCV::SLLI_UW;
}
}
@@ -215,8 +215,7 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
// Skip shift if we were able to use LUI directly.
if (ShiftAmount) {
- unsigned Opc = Unsigned ? RISCV::SLLI_UW : RISCV::SLLI;
- Res.emplace_back(Opc, ShiftAmount);
+ Res.emplace_back(ShiftOpc, ShiftAmount);
}
if (Lo12)
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