[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for G_AMDGPU_S_BUFFER_PREFETCH (PR #191315)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 15 10:24:34 PDT 2026
https://github.com/vangthao95 updated https://github.com/llvm/llvm-project/pull/191315
>From b3c7190d5dbc2136cab6efbd450baa31f9012276 Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Thu, 9 Apr 2026 18:21:10 -0400
Subject: [PATCH 1/3] AMDGPU/GlobalISel: RegBankLegalize rules for
G_AMDGPU_S_BUFFER_PREFETCH
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 3 +
.../llvm.amdgcn.s.buffer.prefetch.data.ll | 110 +++++++++++++++---
2 files changed, 98 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 973f032e6ad6d..d69f1639b6065 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1401,6 +1401,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniS64, S32}, {{UniInVgprS64}, {Vgpr32}}})
.Any({{DivS64, S32}, {{Vgpr64}, {Vgpr32}}});
+ addRulesForGOpcs({G_AMDGPU_S_BUFFER_PREFETCH})
+ .Any({{}, {{}, {SgprV4S32_WF, Imm, Sgpr32_WF}}});
+
addRulesForGOpcs({G_FPEXT})
.Any({{DivS32, S16}, {{Vgpr32}, {Vgpr16}}})
.Any({{UniS64, S32}, {{UniInVgprS64}, {Vgpr32}}})
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
index dc33c4f0adf23..0652391291647 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,GISEL %s
declare void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) %rsrc, i32 %offset, i32 %len)
@@ -25,26 +25,106 @@ entry:
}
define amdgpu_ps void @buffer_prefetch_data_imm_offset_vgpr_len(ptr addrspace(8) inreg %rsrc, i32 %len) {
-; GCN-LABEL: buffer_prefetch_data_imm_offset_vgpr_len:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: v_readfirstlane_b32 s4, v0
-; GCN-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s4, 0
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: buffer_prefetch_data_imm_offset_vgpr_len:
+; SDAG: ; %bb.0: ; %entry
+; SDAG-NEXT: v_readfirstlane_b32 s4, v0
+; SDAG-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s4, 0
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: buffer_prefetch_data_imm_offset_vgpr_len:
+; GISEL: ; %bb.0: ; %entry
+; GISEL-NEXT: s_mov_b32 s4, exec_lo
+; GISEL-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
+; GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GISEL-NEXT: s_mov_b32 s4, exec_lo
+; GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GISEL-NEXT: v_cmpx_eq_u32_e64 s5, v0
+; GISEL-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s5, 0
+; GISEL-NEXT: ; implicit-def: $vgpr0
+; GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s4
+; GISEL-NEXT: s_cbranch_execnz .LBB2_1
+; GISEL-NEXT: ; %bb.2:
+; GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) inreg %rsrc, i32 128, i32 %len)
ret void
}
define amdgpu_ps void @buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len(ptr addrspace(8) %rsrc, i32 inreg %len) {
-; GCN-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: v_readfirstlane_b32 s4, v0
-; GCN-NEXT: v_readfirstlane_b32 s5, v1
-; GCN-NEXT: v_readfirstlane_b32 s6, v2
-; GCN-NEXT: v_readfirstlane_b32 s7, v3
-; GCN-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s0, 0
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len:
+; SDAG: ; %bb.0: ; %entry
+; SDAG-NEXT: v_readfirstlane_b32 s4, v0
+; SDAG-NEXT: v_readfirstlane_b32 s5, v1
+; SDAG-NEXT: v_readfirstlane_b32 s6, v2
+; SDAG-NEXT: v_readfirstlane_b32 s7, v3
+; SDAG-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s0, 0
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len:
+; GISEL: ; %bb.0: ; %entry
+; GISEL-NEXT: s_mov_b32 s1, exec_lo
+; GISEL-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1
+; GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GISEL-NEXT: v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
+; GISEL-NEXT: s_and_b32 s1, vcc_lo, s1
+; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-NEXT: s_and_saveexec_b32 s1, s1
+; GISEL-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s0, 0
+; GISEL-NEXT: ; implicit-def: $vgpr0
+; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s1
+; GISEL-NEXT: s_cbranch_execnz .LBB3_1
+; GISEL-NEXT: ; %bb.2:
+; GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) inreg %rsrc, i32 128, i32 %len)
ret void
}
+
+define amdgpu_ps void @buffer_prefetch_data_vgpr_rsrc_imm_offset_vgpr_len(ptr addrspace(8) %rsrc, i32 %len) {
+; SDAG-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_vgpr_len:
+; SDAG: ; %bb.0: ; %entry
+; SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; SDAG-NEXT: v_readfirstlane_b32 s1, v1
+; SDAG-NEXT: v_readfirstlane_b32 s2, v2
+; SDAG-NEXT: v_readfirstlane_b32 s3, v3
+; SDAG-NEXT: v_readfirstlane_b32 s4, v4
+; SDAG-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s4, 0
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_vgpr_len:
+; GISEL: ; %bb.0: ; %entry
+; GISEL-NEXT: s_mov_b32 s0, exec_lo
+; GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
+; GISEL-NEXT: v_cmp_eq_u32_e64 s1, s2, v4
+; GISEL-NEXT: s_and_b32 s0, vcc_lo, s0
+; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GISEL-NEXT: s_and_b32 s0, s0, s1
+; GISEL-NEXT: s_and_saveexec_b32 s0, s0
+; GISEL-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s2, 0
+; GISEL-NEXT: ; implicit-def: $vgpr0
+; GISEL-NEXT: ; implicit-def: $vgpr4
+; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GISEL-NEXT: s_cbranch_execnz .LBB4_1
+; GISEL-NEXT: ; %bb.2:
+; GISEL-NEXT: s_endpgm
+entry:
+ tail call void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) %rsrc, i32 128, i32 %len)
+ ret void
+}
>From 6bb134c8c0ad3a3115aede3c69585d37fc7ec93a Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Fri, 10 Apr 2026 12:20:28 -0400
Subject: [PATCH 2/3] Use readfirstlane instead of WF
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 6 +-
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 2 +-
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 1 +
.../llvm.amdgcn.s.buffer.prefetch.data.ll | 113 ++++--------------
4 files changed, 30 insertions(+), 92 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 7294166f5792d..4f25cbbfa69c2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1441,6 +1441,7 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
return LLT::fixed_vector(4, 16);
case SgprV4S32:
case SgprV4S32_WF:
+ case SgprV4S32_ReadFirstLane:
case VgprV4S32:
case UniInVgprV4S32:
return LLT::fixed_vector(4, 32);
@@ -1562,6 +1563,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case SgprV2S32:
case SgprV4S32:
case SgprV4S32_WF:
+ case SgprV4S32_ReadFirstLane:
case SgprB32:
case SgprB64:
case SgprB96:
@@ -1931,8 +1933,8 @@ bool RegBankLegalizeHelper::applyMappingSrc(
}
case SgprB32_M0:
case SgprB32_ReadFirstLane:
- case SgprB64_ReadFirstLane: {
- assert(Ty == getBTyFromID(MethodIDs[i], Ty));
+ case SgprB64_ReadFirstLane:
+ case SgprV4S32_ReadFirstLane: {
if (RB == SgprRB)
break;
assert(RB == VgprRB);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index d69f1639b6065..9d4a33eb2e6ba 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1402,7 +1402,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{DivS64, S32}, {{Vgpr64}, {Vgpr32}}});
addRulesForGOpcs({G_AMDGPU_S_BUFFER_PREFETCH})
- .Any({{}, {{}, {SgprV4S32_WF, Imm, Sgpr32_WF}}});
+ .Any({{}, {{}, {SgprV4S32_ReadFirstLane, Imm, SgprB32_ReadFirstLane}}});
addRulesForGOpcs({G_FPEXT})
.Any({{DivS32, S16}, {{Vgpr32}, {Vgpr16}}})
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index be9d472f29be4..3d282220d8611 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -245,6 +245,7 @@ enum RegBankLLTMappingApplyID {
// to move to SGPR.
SgprB32_ReadFirstLane,
SgprB64_ReadFirstLane,
+ SgprV4S32_ReadFirstLane,
// Src only modifiers: extends
Sgpr32AExt,
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
index 0652391291647..879a8facc7f32 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,SDAG %s
-; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GCN %s
declare void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) %rsrc, i32 %offset, i32 %len)
@@ -25,105 +25,40 @@ entry:
}
define amdgpu_ps void @buffer_prefetch_data_imm_offset_vgpr_len(ptr addrspace(8) inreg %rsrc, i32 %len) {
-; SDAG-LABEL: buffer_prefetch_data_imm_offset_vgpr_len:
-; SDAG: ; %bb.0: ; %entry
-; SDAG-NEXT: v_readfirstlane_b32 s4, v0
-; SDAG-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s4, 0
-; SDAG-NEXT: s_endpgm
-;
-; GISEL-LABEL: buffer_prefetch_data_imm_offset_vgpr_len:
-; GISEL: ; %bb.0: ; %entry
-; GISEL-NEXT: s_mov_b32 s4, exec_lo
-; GISEL-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
-; GISEL-NEXT: v_readfirstlane_b32 s5, v0
-; GISEL-NEXT: s_mov_b32 s4, exec_lo
-; GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GISEL-NEXT: v_cmpx_eq_u32_e64 s5, v0
-; GISEL-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s5, 0
-; GISEL-NEXT: ; implicit-def: $vgpr0
-; GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s4
-; GISEL-NEXT: s_cbranch_execnz .LBB2_1
-; GISEL-NEXT: ; %bb.2:
-; GISEL-NEXT: s_endpgm
+; GCN-LABEL: buffer_prefetch_data_imm_offset_vgpr_len:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: v_readfirstlane_b32 s4, v0
+; GCN-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s4, 0
+; GCN-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) inreg %rsrc, i32 128, i32 %len)
ret void
}
define amdgpu_ps void @buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len(ptr addrspace(8) %rsrc, i32 inreg %len) {
-; SDAG-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len:
-; SDAG: ; %bb.0: ; %entry
-; SDAG-NEXT: v_readfirstlane_b32 s4, v0
-; SDAG-NEXT: v_readfirstlane_b32 s5, v1
-; SDAG-NEXT: v_readfirstlane_b32 s6, v2
-; SDAG-NEXT: v_readfirstlane_b32 s7, v3
-; SDAG-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s0, 0
-; SDAG-NEXT: s_endpgm
-;
-; GISEL-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len:
-; GISEL: ; %bb.0: ; %entry
-; GISEL-NEXT: s_mov_b32 s1, exec_lo
-; GISEL-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1
-; GISEL-NEXT: v_readfirstlane_b32 s4, v0
-; GISEL-NEXT: v_readfirstlane_b32 s5, v1
-; GISEL-NEXT: v_readfirstlane_b32 s6, v2
-; GISEL-NEXT: v_readfirstlane_b32 s7, v3
-; GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GISEL-NEXT: v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
-; GISEL-NEXT: s_and_b32 s1, vcc_lo, s1
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: s_and_saveexec_b32 s1, s1
-; GISEL-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s0, 0
-; GISEL-NEXT: ; implicit-def: $vgpr0
-; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s1
-; GISEL-NEXT: s_cbranch_execnz .LBB3_1
-; GISEL-NEXT: ; %bb.2:
-; GISEL-NEXT: s_endpgm
+; GCN-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: v_readfirstlane_b32 s4, v0
+; GCN-NEXT: v_readfirstlane_b32 s5, v1
+; GCN-NEXT: v_readfirstlane_b32 s6, v2
+; GCN-NEXT: v_readfirstlane_b32 s7, v3
+; GCN-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s0, 0
+; GCN-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) inreg %rsrc, i32 128, i32 %len)
ret void
}
define amdgpu_ps void @buffer_prefetch_data_vgpr_rsrc_imm_offset_vgpr_len(ptr addrspace(8) %rsrc, i32 %len) {
-; SDAG-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_vgpr_len:
-; SDAG: ; %bb.0: ; %entry
-; SDAG-NEXT: v_readfirstlane_b32 s0, v0
-; SDAG-NEXT: v_readfirstlane_b32 s1, v1
-; SDAG-NEXT: v_readfirstlane_b32 s2, v2
-; SDAG-NEXT: v_readfirstlane_b32 s3, v3
-; SDAG-NEXT: v_readfirstlane_b32 s4, v4
-; SDAG-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s4, 0
-; SDAG-NEXT: s_endpgm
-;
-; GISEL-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_vgpr_len:
-; GISEL: ; %bb.0: ; %entry
-; GISEL-NEXT: s_mov_b32 s0, exec_lo
-; GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GISEL-NEXT: v_readfirstlane_b32 s4, v0
-; GISEL-NEXT: v_readfirstlane_b32 s5, v1
-; GISEL-NEXT: v_readfirstlane_b32 s6, v2
-; GISEL-NEXT: v_readfirstlane_b32 s7, v3
-; GISEL-NEXT: v_readfirstlane_b32 s2, v4
-; GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
-; GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GISEL-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s1, s2, v4
-; GISEL-NEXT: s_and_b32 s0, vcc_lo, s0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GISEL-NEXT: s_and_b32 s0, s0, s1
-; GISEL-NEXT: s_and_saveexec_b32 s0, s0
-; GISEL-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s2, 0
-; GISEL-NEXT: ; implicit-def: $vgpr0
-; GISEL-NEXT: ; implicit-def: $vgpr4
-; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
-; GISEL-NEXT: s_cbranch_execnz .LBB4_1
-; GISEL-NEXT: ; %bb.2:
-; GISEL-NEXT: s_endpgm
+; GCN-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_vgpr_len:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: v_readfirstlane_b32 s1, v1
+; GCN-NEXT: v_readfirstlane_b32 s2, v2
+; GCN-NEXT: v_readfirstlane_b32 s3, v3
+; GCN-NEXT: v_readfirstlane_b32 s4, v4
+; GCN-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s4, 0
+; GCN-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) %rsrc, i32 128, i32 %len)
ret void
>From e06c138324cc833d8c10bc8e4bbdbf68f072e771 Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Tue, 14 Apr 2026 13:17:00 -0400
Subject: [PATCH 3/3] Fix assert
---
.../Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 4f25cbbfa69c2..63a940ab5d29b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1933,8 +1933,18 @@ bool RegBankLegalizeHelper::applyMappingSrc(
}
case SgprB32_M0:
case SgprB32_ReadFirstLane:
- case SgprB64_ReadFirstLane:
+ case SgprB64_ReadFirstLane: {
+ assert(Ty == getBTyFromID(MethodIDs[i], Ty));
+ if (RB == SgprRB)
+ break;
+ assert(RB == VgprRB);
+ Register NewSGPR = MRI.createVirtualRegister({SgprRB, Ty});
+ buildReadFirstLane(B, NewSGPR, Op.getReg(), RBI);
+ Op.setReg(NewSGPR);
+ break;
+ }
case SgprV4S32_ReadFirstLane: {
+ assert(Ty == getTyFromID(MethodIDs[i]));
if (RB == SgprRB)
break;
assert(RB == VgprRB);
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