[llvm] [RISCV][llvm] Support [s|u]int_to_fp and fp_to_[s|u]int for zvfbfa (PR #192287)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 15 09:48:41 PDT 2026
https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/192287
None
>From b7cfa19b7e2b7c15e836017a9ac7cbe678bd2701 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 15 Apr 2026 09:35:06 -0700
Subject: [PATCH] [RISCV][llvm] Support [s|u]int_to_fp and fp_to_[s|u]int for
zvfbfa
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 22 +-
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 47 +-
.../Target/RISCV/RISCVInstrInfoVSDPatterns.td | 18 +-
.../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 27 +-
.../Target/RISCV/RISCVInstrInfoZvfofp8min.td | 9 -
.../CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll | 274 +++-
.../CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll | 542 +++++--
...fixed-vectors-vfptoi-constrained-sdnode.ll | 70 +-
...fixed-vectors-vitofp-constrained-sdnode.ll | 70 +-
.../RISCV/rvv/vfptoi-constrained-sdnode.ll | 116 +-
llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll | 1336 ++++++++++------
.../RISCV/rvv/vitofp-constrained-sdnode.ll | 116 +-
llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll | 1354 +++++++++++------
13 files changed, 2809 insertions(+), 1192 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1148b801530a0..91d807d98e86f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8044,11 +8044,16 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return lowerStrictFPExtendOrRoundLike(Op, DAG);
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
- if (Op.getValueType().isVector() &&
+ // Fall back to zvfbfmin for bf16 case if source type is wider than 8 bits.
+ if (SDValue Op1 = Op.getOperand(0);
+ Op.getValueType().isVector() &&
((Op.getValueType().getScalarType() == MVT::f16 &&
(Subtarget.hasVInstructionsF16Minimal() &&
!Subtarget.hasVInstructionsF16())) ||
- Op.getValueType().getScalarType() == MVT::bf16)) {
+ (Op.getValueType().getScalarType() == MVT::bf16 &&
+ (Subtarget.hasVInstructionsBF16Minimal() &&
+ (!Subtarget.hasVInstructionsBF16() ||
+ Op1.getValueType().getScalarSizeInBits() > 8))))) {
MVT NVT =
MVT::getVectorVT(MVT::f32, Op.getValueType().getVectorElementCount());
if (!isTypeLegal(NVT))
@@ -8063,12 +8068,17 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
[[fallthrough]];
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
+ // Fall back to zvfbfmin for bf16 case if destination type is wider than 8
+ // bits.
if (SDValue Op1 = Op.getOperand(0);
Op1.getValueType().isVector() &&
((Op1.getValueType().getScalarType() == MVT::f16 &&
(Subtarget.hasVInstructionsF16Minimal() &&
!Subtarget.hasVInstructionsF16())) ||
- Op1.getValueType().getScalarType() == MVT::bf16)) {
+ (Op1.getValueType().getScalarType() == MVT::bf16 &&
+ (Subtarget.hasVInstructionsBF16Minimal() &&
+ (!Subtarget.hasVInstructionsBF16() ||
+ Op.getValueType().getScalarSizeInBits() > 8))))) {
MVT NVT = MVT::getVectorVT(MVT::f32,
Op1.getValueType().getVectorElementCount());
if (!isTypeLegal(NVT))
@@ -8123,7 +8133,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return DAG.getNode(Op.getOpcode(), DL, VT, Ext);
}
// FP2Int
- assert(SrcEltVT == MVT::f16 && "Unexpected FP_TO_[US]INT lowering");
+ assert((SrcEltVT == MVT::f16 || SrcEltVT == MVT::bf16) &&
+ "Unexpected FP_TO_[US]INT lowering");
// Do one doubling fp_extend then complete the operation by converting
// to int.
MVT InterimFVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
@@ -8140,7 +8151,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
if (SrcEltSize > (2 * EltSize)) {
if (IsInt2FP) {
// One narrowing int_to_fp, then an fp_round.
- assert(EltVT == MVT::f16 && "Unexpected [US]_TO_FP lowering");
+ assert((EltVT == MVT::f16 || EltVT == MVT::bf16) &&
+ "Unexpected [US]_TO_FP lowering");
MVT InterimFVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
if (IsStrict) {
SDValue Int2FP = DAG.getNode(Op.getOpcode(), DL,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index a5b3b1d3f940b..9f041a9f00444 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -538,24 +538,35 @@ defset list<VTypeInfoToFraction> AllFractionableVF8IntVectors = {
def : VTypeInfoToFraction<VI64M8, VI8M1>;
}
-defset list<VTypeInfoToWide> AllWidenableIntToFloatVectors = {
- def : VTypeInfoToWide<VI8MF8, VF16MF4>;
- def : VTypeInfoToWide<VI8MF4, VF16MF2>;
- def : VTypeInfoToWide<VI8MF2, VF16M1>;
- def : VTypeInfoToWide<VI8M1, VF16M2>;
- def : VTypeInfoToWide<VI8M2, VF16M4>;
- def : VTypeInfoToWide<VI8M4, VF16M8>;
-
- def : VTypeInfoToWide<VI16MF4, VF32MF2>;
- def : VTypeInfoToWide<VI16MF2, VF32M1>;
- def : VTypeInfoToWide<VI16M1, VF32M2>;
- def : VTypeInfoToWide<VI16M2, VF32M4>;
- def : VTypeInfoToWide<VI16M4, VF32M8>;
-
- def : VTypeInfoToWide<VI32MF2, VF64M1>;
- def : VTypeInfoToWide<VI32M1, VF64M2>;
- def : VTypeInfoToWide<VI32M2, VF64M4>;
- def : VTypeInfoToWide<VI32M4, VF64M8>;
+defset list<VTypeInfoToWide> AllWidenableIntToFloatAndBF16Vectors = {
+ defset list<VTypeInfoToWide> AllWidenableIntToFloatVectors = {
+ def : VTypeInfoToWide<VI8MF8, VF16MF4>;
+ def : VTypeInfoToWide<VI8MF4, VF16MF2>;
+ def : VTypeInfoToWide<VI8MF2, VF16M1>;
+ def : VTypeInfoToWide<VI8M1, VF16M2>;
+ def : VTypeInfoToWide<VI8M2, VF16M4>;
+ def : VTypeInfoToWide<VI8M4, VF16M8>;
+
+ def : VTypeInfoToWide<VI16MF4, VF32MF2>;
+ def : VTypeInfoToWide<VI16MF2, VF32M1>;
+ def : VTypeInfoToWide<VI16M1, VF32M2>;
+ def : VTypeInfoToWide<VI16M2, VF32M4>;
+ def : VTypeInfoToWide<VI16M4, VF32M8>;
+
+ def : VTypeInfoToWide<VI32MF2, VF64M1>;
+ def : VTypeInfoToWide<VI32M1, VF64M2>;
+ def : VTypeInfoToWide<VI32M2, VF64M4>;
+ def : VTypeInfoToWide<VI32M4, VF64M8>;
+ }
+
+ defset list<VTypeInfoToWide> AllWidenableIntToBFloatVectors = {
+ def : VTypeInfoToWide<VI8MF8, VBF16MF4>;
+ def : VTypeInfoToWide<VI8MF4, VBF16MF2>;
+ def : VTypeInfoToWide<VI8MF2, VBF16M1>;
+ def : VTypeInfoToWide<VI8M1, VBF16M2>;
+ def : VTypeInfoToWide<VI8M2, VBF16M4>;
+ def : VTypeInfoToWide<VI8M4, VBF16M8>;
+ }
}
// This class holds the record of the RISCVVPseudoTable below.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 4c558c4524c5b..97d2e664db6b7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -416,13 +416,14 @@ multiclass VPatConvertFP2ISDNode_V<SDPatternOperator vop,
multiclass VPatWConvertI2FPSDNode_V<SDPatternOperator vop,
string instruction_name> {
- foreach vtiToWti = AllWidenableIntToFloatVectors in {
+ foreach vtiToWti = AllWidenableIntToFloatAndBF16Vectors in {
defvar ivti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
+ defvar alt = !if(!eq(fwti.Scalar, bf16), "_ALT", "");
let Predicates = !listconcat(GetVTypePredicates<ivti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
- (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_E"#ivti.SEW)
+ (!cast<Instruction>(instruction_name#alt#"_V_"#ivti.LMul.MX#"_E"#ivti.SEW)
(fwti.Vector (IMPLICIT_DEF)),
ivti.RegClass:$rs1,
ivti.AVL, ivti.Log2SEW, TA_MA)>;
@@ -463,13 +464,14 @@ multiclass VPatNConvertI2FPSDNode_W_RM<SDPatternOperator vop,
multiclass VPatNConvertFP2ISDNode_W<SDPatternOperator vop,
string instruction_name> {
- foreach vtiToWti = AllWidenableIntToFloatVectors in {
+ foreach vtiToWti = AllWidenableIntToFloatAndBF16Vectors in {
defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
+ defvar alt = !if(!eq(fwti.Scalar, bf16), "_ALT", "");
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1))),
- (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX)
+ (!cast<Instruction>(instruction_name#alt#"_W_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
fwti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
}
@@ -1508,12 +1510,12 @@ defm : VPatConvertI2FPSDNode_V_RM<any_uint_to_fp, "PseudoVFCVT_F_XU_V">;
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
defm : VPatWConvertFP2ISDNode_V<any_fp_to_sint, "PseudoVFWCVT_RTZ_X_F_V">;
defm : VPatWConvertFP2ISDNode_V<any_fp_to_uint, "PseudoVFWCVT_RTZ_XU_F_V">;
-defm : VPatWConvertI2FPSDNode_V<any_sint_to_fp, "PseudoVFWCVT_F_X_V">;
-defm : VPatWConvertI2FPSDNode_V<any_uint_to_fp, "PseudoVFWCVT_F_XU_V">;
+defm : VPatWConvertI2FPSDNode_V<any_sint_to_fp, "PseudoVFWCVT_F_X">;
+defm : VPatWConvertI2FPSDNode_V<any_uint_to_fp, "PseudoVFWCVT_F_XU">;
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
-defm : VPatNConvertFP2ISDNode_W<any_fp_to_sint, "PseudoVFNCVT_RTZ_X_F_W">;
-defm : VPatNConvertFP2ISDNode_W<any_fp_to_uint, "PseudoVFNCVT_RTZ_XU_F_W">;
+defm : VPatNConvertFP2ISDNode_W<any_fp_to_sint, "PseudoVFNCVT_RTZ_X_F">;
+defm : VPatNConvertFP2ISDNode_W<any_fp_to_uint, "PseudoVFNCVT_RTZ_XU_F">;
defm : VPatNConvertI2FPSDNode_W_RM<any_sint_to_fp, "PseudoVFNCVT_F_X_W">;
defm : VPatNConvertI2FPSDNode_W_RM<any_uint_to_fp, "PseudoVFNCVT_F_XU_W">;
foreach fvtiToFWti = AllWidenableFloatAndBF16Vectors in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 2a99492bc5596..56d817ea637d9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -1374,15 +1374,16 @@ multiclass VPatWConvertFP2I_RM_VL_V<SDNode vop, string instruction_name> {
multiclass VPatWConvertI2FPVL_V<SDPatternOperator vop,
string instruction_name> {
- foreach vtiToWti = AllWidenableIntToFloatVectors in {
+ foreach vtiToWti = AllWidenableIntToFloatAndBF16Vectors in {
defvar ivti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
+ defvar alt = !if(!eq(fwti.Scalar, bf16), "_ALT", "");
let Predicates = !listconcat(GetVTypePredicates<ivti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
(ivti.Mask VMV0:$vm),
VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_E"#ivti.SEW#"_MASK")
+ (!cast<Instruction>(instruction_name#alt#"_V_"#ivti.LMul.MX#"_E"#ivti.SEW#"_MASK")
(fwti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
(ivti.Mask VMV0:$vm),
GPR:$vl, ivti.Log2SEW, TA_MA)>;
@@ -1395,30 +1396,32 @@ multiclass VPatNConvertFP2IVL_W<SDPatternOperator vop,
string instruction_name> {
// Reuse the same list of types used in the widening nodes, but just swap the
// direction of types around so we're converting from Wti -> Vti
- foreach vtiToWti = AllWidenableIntToFloatVectors in {
+ foreach vtiToWti = AllWidenableIntToFloatAndBF16Vectors in {
defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
+ defvar alt = !if(!eq(fwti.Scalar, bf16), "_ALT", "");
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),
(fwti.Mask VMV0:$vm),
VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK")
+ (!cast<Instruction>(instruction_name#alt#"_W_"#vti.LMul.MX#"_MASK")
(vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
(fwti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;
}
}
multiclass VPatNConvertFP2I_RM_VL_W<SDNode vop, string instruction_name> {
- foreach vtiToWti = AllWidenableIntToFloatVectors in {
+ foreach vtiToWti = AllWidenableIntToFloatAndBF16Vectors in {
defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
+ defvar alt = !if(!eq(fwti.Scalar, bf16), "_ALT", "");
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),
(fwti.Mask VMV0:$vm), (XLenVT timm:$frm),
VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK")
+ (!cast<Instruction>(instruction_name#alt#"_W_"#vti.LMul.MX#"_MASK")
(vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
(fwti.Mask VMV0:$vm), timm:$frm, GPR:$vl, vti.Log2SEW, TA_MA)>;
}
@@ -2686,8 +2689,8 @@ defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_X_F_V">;
defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFWCVT_RTZ_XU_F_V">;
defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFWCVT_RTZ_X_F_V">;
-defm : VPatWConvertI2FPVL_V<any_riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">;
-defm : VPatWConvertI2FPVL_V<any_riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">;
+defm : VPatWConvertI2FPVL_V<any_riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU">;
+defm : VPatWConvertI2FPVL_V<any_riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X">;
foreach fvtiToFWti = AllWidenableFloatAndBF16Vectors in {
defvar fvti = fvtiToFWti.Vti;
@@ -2724,11 +2727,11 @@ foreach fvtiToFWti = AllWidenableFloatAndBF16Vectors in {
}
// 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
-defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
-defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_X_F_W">;
+defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_XU_F">;
+defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_X_F">;
-defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFNCVT_RTZ_XU_F_W">;
-defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFNCVT_RTZ_X_F_W">;
+defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFNCVT_RTZ_XU_F">;
+defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFNCVT_RTZ_X_F">;
defm : VPatNConvertI2FPVL_W_RM<any_riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">;
defm : VPatNConvertI2FPVL_W_RM<any_riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td
index 094fb31550637..bc2e4ab0aa8c9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td
@@ -30,15 +30,6 @@ let Predicates = [HasStdExtZvfofp8min], Constraints = "@earlyclobber $vd",
//===----------------------------------------------------------------------===//
defvar MxListQ = [V_MF8, V_MF4, V_MF2, V_M1, V_M2];
-defset list<VTypeInfoToWide> AllWidenableIntToBFloatVectors = {
- def : VTypeInfoToWide<VI8MF8, VBF16MF4>;
- def : VTypeInfoToWide<VI8MF4, VBF16MF2>;
- def : VTypeInfoToWide<VI8MF2, VBF16M1>;
- def : VTypeInfoToWide<VI8M1, VBF16M2>;
- def : VTypeInfoToWide<VI8M2, VBF16M4>;
- def : VTypeInfoToWide<VI8M4, VBF16M8>;
-}
-
defset list<VTypeInfoToWide> AllWidenableInt8ToFloat32Vectors = {
def : VTypeInfoToWide<VI8MF8, VF32MF2>;
def : VTypeInfoToWide<VI8MF4, VF32M1>;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
index e9357b629628c..350de6c52a775 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
@@ -1,8 +1,10 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32,ZVFBFMIN
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64,ZVFBFMIN
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32,ZVFBFMIN
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64,ZVFBFMIN
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+experimental-zvfbfa,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32,ZVFBFA
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+experimental-zvfbfa,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64,ZVFBFA
define void @fp2si_v2f32_v2i32(ptr %x, ptr %y) {
; CHECK-LABEL: fp2si_v2f32_v2i32:
@@ -419,15 +421,25 @@ define void @fp2ui_v8f32_v8i64(ptr %x, ptr %y) {
}
define void @fp2si_v2bf16_v2i64(ptr %x, ptr %y) {
-; CHECK-LABEL: fp2si_v2bf16_v2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
-; CHECK-NEXT: vse64.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: fp2si_v2bf16_v2i64:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vle16.v v8, (a0)
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.rtz.x.f.v v8, v9
+; ZVFBFMIN-NEXT: vse64.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: fp2si_v2bf16_v2i64:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vle16.v v8, (a0)
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.rtz.x.f.v v8, v9
+; ZVFBFA-NEXT: vse64.v v8, (a1)
+; ZVFBFA-NEXT: ret
%a = load <2 x bfloat>, ptr %x
%d = fptosi <2 x bfloat> %a to <2 x i64>
store <2 x i64> %d, ptr %y
@@ -435,15 +447,25 @@ define void @fp2si_v2bf16_v2i64(ptr %x, ptr %y) {
}
define void @fp2ui_v2bf16_v2i64(ptr %x, ptr %y) {
-; CHECK-LABEL: fp2ui_v2bf16_v2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
-; CHECK-NEXT: vse64.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: fp2ui_v2bf16_v2i64:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vle16.v v8, (a0)
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v9
+; ZVFBFMIN-NEXT: vse64.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: fp2ui_v2bf16_v2i64:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vle16.v v8, (a0)
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.rtz.xu.f.v v8, v9
+; ZVFBFA-NEXT: vse64.v v8, (a1)
+; ZVFBFA-NEXT: ret
%a = load <2 x bfloat>, ptr %x
%d = fptoui <2 x bfloat> %a to <2 x i64>
store <2 x i64> %d, ptr %y
@@ -451,48 +473,83 @@ define void @fp2ui_v2bf16_v2i64(ptr %x, ptr %y) {
}
define <2 x i1> @fp2si_v2bf16_v2i1(<2 x bfloat> %x) {
-; CHECK-LABEL: fp2si_v2bf16_v2i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: fp2si_v2bf16_v2i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: fp2si_v2bf16_v2i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v9, 0
+; ZVFBFA-NEXT: ret
%z = fptosi <2 x bfloat> %x to <2 x i1>
ret <2 x i1> %z
}
define <2 x i1> @fp2ui_v2bf16_v2i1(<2 x bfloat> %x) {
-; CHECK-LABEL: fp2ui_v2bf16_v2i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: fp2ui_v2bf16_v2i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: fp2ui_v2bf16_v2i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v9, 0
+; ZVFBFA-NEXT: ret
%z = fptoui <2 x bfloat> %x to <2 x i1>
ret <2 x i1> %z
}
define void @fp2si_v64bf16_v64i16(ptr %x, ptr %y) {
-; CHECK-LABEL: fp2si_v64bf16_v64i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vslidedown.vx v24, v8, a0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
-; CHECK-NEXT: vfncvt.rtz.x.f.w v24, v16
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v24, a0
-; CHECK-NEXT: vse16.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: fp2si_v64bf16_v64i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: li a2, 64
+; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vle16.v v8, (a0)
+; ZVFBFMIN-NEXT: li a0, 32
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vslidedown.vx v24, v8, a0
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v16
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v24, v16
+; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vslideup.vx v8, v24, a0
+; ZVFBFMIN-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: fp2si_v64bf16_v64i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a2, 64
+; ZVFBFA-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFA-NEXT: vle16.v v8, (a0)
+; ZVFBFA-NEXT: li a0, 32
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
+; ZVFBFA-NEXT: vslidedown.vx v24, v8, a0
+; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v8, v16
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v24, v16
+; ZVFBFA-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFA-NEXT: vslideup.vx v8, v24, a0
+; ZVFBFA-NEXT: vse16.v v8, (a1)
+; ZVFBFA-NEXT: ret
%a = load <64 x bfloat>, ptr %x
%d = fptosi <64 x bfloat> %a to <64 x i16>
store <64 x i16> %d, ptr %y
@@ -500,30 +557,101 @@ define void @fp2si_v64bf16_v64i16(ptr %x, ptr %y) {
}
define void @fp2ui_v64bf16_v64i16(ptr %x, ptr %y) {
-; CHECK-LABEL: fp2ui_v64bf16_v64i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vslidedown.vx v24, v8, a0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v24, v16
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v24, a0
-; CHECK-NEXT: vse16.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: fp2ui_v64bf16_v64i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: li a2, 64
+; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vle16.v v8, (a0)
+; ZVFBFMIN-NEXT: li a0, 32
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vslidedown.vx v24, v8, a0
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v16
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v24, v16
+; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vslideup.vx v8, v24, a0
+; ZVFBFMIN-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: fp2ui_v64bf16_v64i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a2, 64
+; ZVFBFA-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFA-NEXT: vle16.v v8, (a0)
+; ZVFBFA-NEXT: li a0, 32
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
+; ZVFBFA-NEXT: vslidedown.vx v24, v8, a0
+; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v8, v16
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v24, v16
+; ZVFBFA-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFA-NEXT: vslideup.vx v8, v24, a0
+; ZVFBFA-NEXT: vse16.v v8, (a1)
+; ZVFBFA-NEXT: ret
%a = load <64 x bfloat>, ptr %x
%d = fptoui <64 x bfloat> %a to <64 x i16>
store <64 x i16> %d, ptr %y
ret void
}
+define void @fp2si_v2bf16_v2i8(ptr %x, ptr %y) {
+; ZVFBFMIN-LABEL: fp2si_v2bf16_v2i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vle16.v v8, (a0)
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
+; ZVFBFMIN-NEXT: vse8.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: fp2si_v2bf16_v2i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vle16.v v8, (a0)
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFBFA-NEXT: vse8.v v9, (a1)
+; ZVFBFA-NEXT: ret
+ %a = load <2 x bfloat>, ptr %x
+ %d = fptosi <2 x bfloat> %a to <2 x i8>
+ store <2 x i8> %d, ptr %y
+ ret void
+}
+
+define void @fp2ui_v2bf16_v2i8(ptr %x, ptr %y) {
+; ZVFBFMIN-LABEL: fp2ui_v2bf16_v2i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vle16.v v8, (a0)
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
+; ZVFBFMIN-NEXT: vse8.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: fp2ui_v2bf16_v2i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vle16.v v8, (a0)
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; ZVFBFA-NEXT: vse8.v v9, (a1)
+; ZVFBFA-NEXT: ret
+ %a = load <2 x bfloat>, ptr %x
+ %d = fptoui <2 x bfloat> %a to <2 x i8>
+ store <2 x i8> %d, ptr %y
+ ret void
+}
+
define void @fp2si_v2f16_v2i64(ptr %x, ptr %y) {
; CHECK-LABEL: fp2si_v2f16_v2i64:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
index 613421d27fb83..516eefdd1a11f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
@@ -1,8 +1,10 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32,ZVFBFMIN
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64,ZVFBFMIN
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32,ZVFBFMIN
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64,ZVFBFMIN
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+experimental-zvfbfa,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32,ZVFBFA
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+experimental-zvfbfa,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64,ZVFBFA
define void @si2fp_v2i32_v2f32(ptr %x, ptr %y) {
; CHECK-LABEL: si2fp_v2i32_v2f32:
@@ -193,6 +195,38 @@ define <3 x float> @si2fp_v3i7_v3f32(<3 x i7> %x) {
; ZVFHMIN64-NEXT: vsext.vf2 v9, v8
; ZVFHMIN64-NEXT: vfwcvt.f.x.v v8, v9
; ZVFHMIN64-NEXT: ret
+; ZVFBFA32-LABEL: si2fp_v3i7_v3f32:
+; ZVFBFA32: # %bb.0:
+; ZVFBFA32-NEXT: lw a1, 0(a0)
+; ZVFBFA32-NEXT: lw a2, 4(a0)
+; ZVFBFA32-NEXT: lw a0, 8(a0)
+; ZVFBFA32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVFBFA32-NEXT: vmv.v.x v8, a1
+; ZVFBFA32-NEXT: vslide1down.vx v8, v8, a2
+; ZVFBFA32-NEXT: vslide1down.vx v8, v8, a0
+; ZVFBFA32-NEXT: vslidedown.vi v8, v8, 1
+; ZVFBFA32-NEXT: vadd.vv v8, v8, v8
+; ZVFBFA32-NEXT: vsra.vi v8, v8, 1
+; ZVFBFA32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFBFA32-NEXT: vsext.vf2 v9, v8
+; ZVFBFA32-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA32-NEXT: ret
+; ZVFBFA64-LABEL: si2fp_v3i7_v3f32:
+; ZVFBFA64: # %bb.0:
+; ZVFBFA64-NEXT: ld a1, 0(a0)
+; ZVFBFA64-NEXT: ld a2, 8(a0)
+; ZVFBFA64-NEXT: ld a0, 16(a0)
+; ZVFBFA64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVFBFA64-NEXT: vmv.v.x v8, a1
+; ZVFBFA64-NEXT: vslide1down.vx v8, v8, a2
+; ZVFBFA64-NEXT: vslide1down.vx v8, v8, a0
+; ZVFBFA64-NEXT: vslidedown.vi v8, v8, 1
+; ZVFBFA64-NEXT: vadd.vv v8, v8, v8
+; ZVFBFA64-NEXT: vsra.vi v8, v8, 1
+; ZVFBFA64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFBFA64-NEXT: vsext.vf2 v9, v8
+; ZVFBFA64-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA64-NEXT: ret
%z = sitofp <3 x i7> %x to <3 x float>
ret <3 x float> %z
}
@@ -266,6 +300,38 @@ define <3 x float> @ui2fp_v3i7_v3f32(<3 x i7> %x) {
; ZVFHMIN64-NEXT: vzext.vf2 v9, v8
; ZVFHMIN64-NEXT: vfwcvt.f.xu.v v8, v9
; ZVFHMIN64-NEXT: ret
+; ZVFBFA32-LABEL: ui2fp_v3i7_v3f32:
+; ZVFBFA32: # %bb.0:
+; ZVFBFA32-NEXT: lw a1, 0(a0)
+; ZVFBFA32-NEXT: lw a2, 4(a0)
+; ZVFBFA32-NEXT: lw a0, 8(a0)
+; ZVFBFA32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVFBFA32-NEXT: vmv.v.x v8, a1
+; ZVFBFA32-NEXT: vslide1down.vx v8, v8, a2
+; ZVFBFA32-NEXT: vslide1down.vx v8, v8, a0
+; ZVFBFA32-NEXT: vslidedown.vi v8, v8, 1
+; ZVFBFA32-NEXT: li a0, 127
+; ZVFBFA32-NEXT: vand.vx v8, v8, a0
+; ZVFBFA32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFBFA32-NEXT: vzext.vf2 v9, v8
+; ZVFBFA32-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA32-NEXT: ret
+; ZVFBFA64-LABEL: ui2fp_v3i7_v3f32:
+; ZVFBFA64: # %bb.0:
+; ZVFBFA64-NEXT: ld a1, 0(a0)
+; ZVFBFA64-NEXT: ld a2, 8(a0)
+; ZVFBFA64-NEXT: ld a0, 16(a0)
+; ZVFBFA64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVFBFA64-NEXT: vmv.v.x v8, a1
+; ZVFBFA64-NEXT: vslide1down.vx v8, v8, a2
+; ZVFBFA64-NEXT: vslide1down.vx v8, v8, a0
+; ZVFBFA64-NEXT: vslidedown.vi v8, v8, 1
+; ZVFBFA64-NEXT: li a0, 127
+; ZVFBFA64-NEXT: vand.vx v8, v8, a0
+; ZVFBFA64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFBFA64-NEXT: vzext.vf2 v9, v8
+; ZVFBFA64-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA64-NEXT: ret
%z = uitofp <3 x i7> %x to <3 x float>
ret <3 x float> %z
}
@@ -419,15 +485,25 @@ define <8 x double> @ui2fp_v8i1_v8f64(<8 x i1> %x) {
}
define void @si2fp_v2i64_v2bf16(ptr %x, ptr %y) {
-; CHECK-LABEL: si2fp_v2i64_v2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vfncvt.f.x.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: vse16.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: si2fp_v2i64_v2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vle64.v v8, (a0)
+; ZVFBFMIN-NEXT: vfncvt.f.x.w v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: si2fp_v2i64_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vle64.v v8, (a0)
+; ZVFBFA-NEXT: vfncvt.f.x.w v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: vse16.v v8, (a1)
+; ZVFBFA-NEXT: ret
%a = load <2 x i64>, ptr %x
%d = sitofp <2 x i64> %a to <2 x bfloat>
store <2 x bfloat> %d, ptr %y
@@ -435,15 +511,25 @@ define void @si2fp_v2i64_v2bf16(ptr %x, ptr %y) {
}
define void @ui2fp_v2i64_v2bf16(ptr %x, ptr %y) {
-; CHECK-LABEL: ui2fp_v2i64_v2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vfncvt.f.xu.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: vse16.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: ui2fp_v2i64_v2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vle64.v v8, (a0)
+; ZVFBFMIN-NEXT: vfncvt.f.xu.w v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: ui2fp_v2i64_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vle64.v v8, (a0)
+; ZVFBFA-NEXT: vfncvt.f.xu.w v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: vse16.v v8, (a1)
+; ZVFBFA-NEXT: ret
%a = load <2 x i64>, ptr %x
%d = uitofp <2 x i64> %a to <2 x bfloat>
store <2 x bfloat> %d, ptr %y
@@ -451,41 +537,67 @@ define void @ui2fp_v2i64_v2bf16(ptr %x, ptr %y) {
}
define <2 x bfloat> @si2fp_v2i1_v2bf16(<2 x i1> %x) {
-; CHECK-LABEL: si2fp_v2i1_v2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: si2fp_v2i1_v2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: si2fp_v2i1_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v9, v8, -1, v0
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: ret
%z = sitofp <2 x i1> %x to <2 x bfloat>
ret <2 x bfloat> %z
}
define <2 x bfloat> @ui2fp_v2i1_v2bf16(<2 x i1> %x) {
-; CHECK-LABEL: ui2fp_v2i1_v2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: ui2fp_v2i1_v2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: ui2fp_v2i1_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v9, v8, 1, v0
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: ret
%z = uitofp <2 x i1> %x to <2 x bfloat>
ret <2 x bfloat> %z
}
define void @si2fp_v8i64_v8bf16(ptr %x, ptr %y) {
-; CHECK-LABEL: si2fp_v8i64_v8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vfncvt.f.x.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: vse16.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: si2fp_v8i64_v8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vle64.v v8, (a0)
+; ZVFBFMIN-NEXT: vfncvt.f.x.w v12, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: si2fp_v8i64_v8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFBFA-NEXT: vle64.v v8, (a0)
+; ZVFBFA-NEXT: vfncvt.f.x.w v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v12
+; ZVFBFA-NEXT: vse16.v v8, (a1)
+; ZVFBFA-NEXT: ret
%a = load <8 x i64>, ptr %x
%d = sitofp <8 x i64> %a to <8 x bfloat>
store <8 x bfloat> %d, ptr %y
@@ -493,15 +605,25 @@ define void @si2fp_v8i64_v8bf16(ptr %x, ptr %y) {
}
define void @ui2fp_v8i64_v8bf16(ptr %x, ptr %y) {
-; CHECK-LABEL: ui2fp_v8i64_v8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vfncvt.f.xu.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: vse16.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: ui2fp_v8i64_v8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vle64.v v8, (a0)
+; ZVFBFMIN-NEXT: vfncvt.f.xu.w v12, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: ui2fp_v8i64_v8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFBFA-NEXT: vle64.v v8, (a0)
+; ZVFBFA-NEXT: vfncvt.f.xu.w v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v12
+; ZVFBFA-NEXT: vse16.v v8, (a1)
+; ZVFBFA-NEXT: ret
%a = load <8 x i64>, ptr %x
%d = uitofp <8 x i64> %a to <8 x bfloat>
store <8 x bfloat> %d, ptr %y
@@ -509,50 +631,87 @@ define void @ui2fp_v8i64_v8bf16(ptr %x, ptr %y) {
}
define <8 x bfloat> @si2fp_v8i1_v8bf16(<8 x i1> %x) {
-; CHECK-LABEL: si2fp_v8i1_v8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v10, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: si2fp_v8i1_v8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v10, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: si2fp_v8i1_v8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 8, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v9, v8, -1, v0
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: ret
%z = sitofp <8 x i1> %x to <8 x bfloat>
ret <8 x bfloat> %z
}
define <8 x bfloat> @ui2fp_v8i1_v8bf16(<8 x i1> %x) {
-; CHECK-LABEL: ui2fp_v8i1_v8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: ui2fp_v8i1_v8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v10, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: ui2fp_v8i1_v8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 8, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v9, v8, 1, v0
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: ret
%z = uitofp <8 x i1> %x to <8 x bfloat>
ret <8 x bfloat> %z
}
define void @si2fp_v64i16_v64bf16(ptr %x, ptr %y) {
-; CHECK-LABEL: si2fp_v64i16_v64bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvt.f.x.v v16, v8
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vslidedown.vx v24, v8, a0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: vfwcvt.f.x.v v16, v24
-; CHECK-NEXT: vfncvtbf16.f.f.w v24, v16
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v24, a0
-; CHECK-NEXT: vse16.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: si2fp_v64i16_v64bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: li a2, 64
+; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vle16.v v8, (a0)
+; ZVFBFMIN-NEXT: li a0, 32
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vslidedown.vx v24, v8, a0
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v24
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v24, v16
+; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vslideup.vx v8, v24, a0
+; ZVFBFMIN-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: si2fp_v64i16_v64bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a2, 64
+; ZVFBFA-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFA-NEXT: vle16.v v8, (a0)
+; ZVFBFA-NEXT: li a0, 32
+; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFA-NEXT: vslidedown.vx v24, v8, a0
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v16, v24
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v24, v16
+; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m8, ta, ma
+; ZVFBFA-NEXT: vslideup.vx v8, v24, a0
+; ZVFBFA-NEXT: vse16.v v8, (a1)
+; ZVFBFA-NEXT: ret
%a = load <64 x i16>, ptr %x
%d = sitofp <64 x i16> %a to <64 x bfloat>
store <64 x bfloat> %d, ptr %y
@@ -560,30 +719,195 @@ define void @si2fp_v64i16_v64bf16(ptr %x, ptr %y) {
}
define void @ui2fp_v64i16_v64bf16(ptr %x, ptr %y) {
-; CHECK-LABEL: ui2fp_v64i16_v64bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vslidedown.vx v24, v8, a0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v24
-; CHECK-NEXT: vfncvtbf16.f.f.w v24, v16
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v24, a0
-; CHECK-NEXT: vse16.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: ui2fp_v64i16_v64bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: li a2, 64
+; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vle16.v v8, (a0)
+; ZVFBFMIN-NEXT: li a0, 32
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vslidedown.vx v24, v8, a0
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v24
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v24, v16
+; ZVFBFMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vslideup.vx v8, v24, a0
+; ZVFBFMIN-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: ui2fp_v64i16_v64bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a2, 64
+; ZVFBFA-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFBFA-NEXT: vle16.v v8, (a0)
+; ZVFBFA-NEXT: li a0, 32
+; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFA-NEXT: vslidedown.vx v24, v8, a0
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v16, v24
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v24, v16
+; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m8, ta, ma
+; ZVFBFA-NEXT: vslideup.vx v8, v24, a0
+; ZVFBFA-NEXT: vse16.v v8, (a1)
+; ZVFBFA-NEXT: ret
%a = load <64 x i16>, ptr %x
%d = uitofp <64 x i16> %a to <64 x bfloat>
store <64 x bfloat> %d, ptr %y
ret void
}
+define void @si2fp_v2i8_v2bf16(ptr %x, ptr %y) {
+; ZVFBFMIN-LABEL: si2fp_v2i8_v2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vle8.v v8, (a0)
+; ZVFBFMIN-NEXT: vsext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v9, v8
+; ZVFBFMIN-NEXT: vse16.v v9, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: si2fp_v2i8_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vle8.v v8, (a0)
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vse16.v v9, (a1)
+; ZVFBFA-NEXT: ret
+ %a = load <2 x i8>, ptr %x
+ %d = sitofp <2 x i8> %a to <2 x bfloat>
+ store <2 x bfloat> %d, ptr %y
+ ret void
+}
+
+define void @ui2fp_v2i8_v2bf16(ptr %x, ptr %y) {
+; ZVFBFMIN-LABEL: ui2fp_v2i8_v2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vle8.v v8, (a0)
+; ZVFBFMIN-NEXT: vzext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v9, v8
+; ZVFBFMIN-NEXT: vse16.v v9, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: ui2fp_v2i8_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vle8.v v8, (a0)
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFA-NEXT: vse16.v v9, (a1)
+; ZVFBFA-NEXT: ret
+ %a = load <2 x i8>, ptr %x
+ %d = uitofp <2 x i8> %a to <2 x bfloat>
+ store <2 x bfloat> %d, ptr %y
+ ret void
+}
+
+define void @si2fp_v4i8_v4bf16(ptr %x, ptr %y) {
+; ZVFBFMIN-LABEL: si2fp_v4i8_v4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vle8.v v8, (a0)
+; ZVFBFMIN-NEXT: vsext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v9, v8
+; ZVFBFMIN-NEXT: vse16.v v9, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: si2fp_v4i8_v4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 4, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vle8.v v8, (a0)
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vse16.v v9, (a1)
+; ZVFBFA-NEXT: ret
+ %a = load <4 x i8>, ptr %x
+ %d = sitofp <4 x i8> %a to <4 x bfloat>
+ store <4 x bfloat> %d, ptr %y
+ ret void
+}
+
+define void @ui2fp_v4i8_v4bf16(ptr %x, ptr %y) {
+; ZVFBFMIN-LABEL: ui2fp_v4i8_v4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vle8.v v8, (a0)
+; ZVFBFMIN-NEXT: vzext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v9, v8
+; ZVFBFMIN-NEXT: vse16.v v9, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: ui2fp_v4i8_v4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 4, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vle8.v v8, (a0)
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFA-NEXT: vse16.v v9, (a1)
+; ZVFBFA-NEXT: ret
+ %a = load <4 x i8>, ptr %x
+ %d = uitofp <4 x i8> %a to <4 x bfloat>
+ store <4 x bfloat> %d, ptr %y
+ ret void
+}
+
+define void @si2fp_v8i8_v8bf16(ptr %x, ptr %y) {
+; ZVFBFMIN-LABEL: si2fp_v8i8_v8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vle8.v v8, (a0)
+; ZVFBFMIN-NEXT: vsext.vf2 v10, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v8, v10
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v10, v8
+; ZVFBFMIN-NEXT: vse16.v v10, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: si2fp_v8i8_v8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 8, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vle8.v v8, (a0)
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vse16.v v9, (a1)
+; ZVFBFA-NEXT: ret
+ %a = load <8 x i8>, ptr %x
+ %d = sitofp <8 x i8> %a to <8 x bfloat>
+ store <8 x bfloat> %d, ptr %y
+ ret void
+}
+
+define void @ui2fp_v8i8_v8bf16(ptr %x, ptr %y) {
+; ZVFBFMIN-LABEL: ui2fp_v8i8_v8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vle8.v v8, (a0)
+; ZVFBFMIN-NEXT: vzext.vf2 v10, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v8, v10
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v10, v8
+; ZVFBFMIN-NEXT: vse16.v v10, (a1)
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: ui2fp_v8i8_v8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 8, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vle8.v v8, (a0)
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFA-NEXT: vse16.v v9, (a1)
+; ZVFBFA-NEXT: ret
+ %a = load <8 x i8>, ptr %x
+ %d = uitofp <8 x i8> %a to <8 x bfloat>
+ store <8 x bfloat> %d, ptr %y
+ ret void
+}
+
define void @si2fp_v2i64_v2f16(ptr %x, ptr %y) {
; CHECK-LABEL: si2fp_v2i64_v2f16:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
index 77a67f1619dd0..abf6cd17fcf95 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+experimental-zvfbfa,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+experimental-zvfbfa,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <1 x i1> @vfptosi_v1f16_v1i1(<1 x half> %va) strictfp {
@@ -1657,3 +1657,69 @@ define <8 x i64> @vfptoui_v8f64_v8i64(<8 x double> %va) strictfp {
%evec = call <8 x i64> @llvm.experimental.constrained.fptoui.v8i64.v8f64(<8 x double> %va, metadata !"fpexcept.strict")
ret <8 x i64> %evec
}
+
+define <2 x i8> @vfptosi_v2bf16_v2i8(<2 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptosi_v2bf16_v2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <2 x i8> @llvm.experimental.constrained.fptosi.v2i8.v2bf16(<2 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <2 x i8> %evec
+}
+
+define <2 x i8> @vfptoui_v2bf16_v2i8(<2 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptoui_v2bf16_v2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <2 x i8> @llvm.experimental.constrained.fptoui.v2i8.v2bf16(<2 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <2 x i8> %evec
+}
+
+define <4 x i8> @vfptosi_v4bf16_v4i8(<4 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptosi_v4bf16_v4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8alt, mf4, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <4 x i8> @llvm.experimental.constrained.fptosi.v4i8.v4bf16(<4 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <4 x i8> %evec
+}
+
+define <4 x i8> @vfptoui_v4bf16_v4i8(<4 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptoui_v4bf16_v4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8alt, mf4, ta, ma
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <4 x i8> @llvm.experimental.constrained.fptoui.v4i8.v4bf16(<4 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <4 x i8> %evec
+}
+
+define <8 x i8> @vfptosi_v8bf16_v8i8(<8 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptosi_v8bf16_v8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8alt, mf2, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <8 x i8> @llvm.experimental.constrained.fptosi.v8i8.v8bf16(<8 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <8 x i8> %evec
+}
+
+define <8 x i8> @vfptoui_v8bf16_v8i8(<8 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptoui_v8bf16_v8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8alt, mf2, ta, ma
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <8 x i8> @llvm.experimental.constrained.fptoui.v8i8.v8bf16(<8 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <8 x i8> %evec
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
index c8aaa5107a78c..19043fc181555 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+experimental-zvfbfa,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+experimental-zvfbfa,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <1 x half> @vsitofp_v1i1_v1f16(<1 x i1> %va) strictfp {
@@ -1613,3 +1613,69 @@ define <8 x double> @vuitofp_v8i64_v8f64(<8 x i64> %va) strictfp {
%evec = call <8 x double> @llvm.experimental.constrained.uitofp.v8f64.v8i64(<8 x i64> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret <8 x double> %evec
}
+
+define <2 x bfloat> @vsitofp_v2i8_v2bf16(<2 x i8> %va) strictfp {
+; CHECK-LABEL: vsitofp_v2i8_v2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <2 x bfloat> @llvm.experimental.constrained.sitofp.v2bf16.v2i8(<2 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <2 x bfloat> %evec
+}
+
+define <2 x bfloat> @vuitofp_v2i8_v2bf16(<2 x i8> %va) strictfp {
+; CHECK-LABEL: vuitofp_v2i8_v2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8alt, mf8, ta, ma
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <2 x bfloat> @llvm.experimental.constrained.uitofp.v2bf16.v2i8(<2 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <2 x bfloat> %evec
+}
+
+define <4 x bfloat> @vsitofp_v4i8_v4bf16(<4 x i8> %va) strictfp {
+; CHECK-LABEL: vsitofp_v4i8_v4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8alt, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <4 x bfloat> @llvm.experimental.constrained.sitofp.v4bf16.v4i8(<4 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <4 x bfloat> %evec
+}
+
+define <4 x bfloat> @vuitofp_v4i8_v4bf16(<4 x i8> %va) strictfp {
+; CHECK-LABEL: vuitofp_v4i8_v4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8alt, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <4 x bfloat> @llvm.experimental.constrained.uitofp.v4bf16.v4i8(<4 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <4 x bfloat> %evec
+}
+
+define <8 x bfloat> @vsitofp_v8i8_v8bf16(<8 x i8> %va) strictfp {
+; CHECK-LABEL: vsitofp_v8i8_v8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8alt, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <8 x bfloat> @llvm.experimental.constrained.sitofp.v8bf16.v8i8(<8 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <8 x bfloat> %evec
+}
+
+define <8 x bfloat> @vuitofp_v8i8_v8bf16(<8 x i8> %va) strictfp {
+; CHECK-LABEL: vuitofp_v8i8_v8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8alt, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <8 x bfloat> @llvm.experimental.constrained.uitofp.v8bf16.v8i8(<8 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <8 x bfloat> %evec
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
index efcdc1e24b0b3..b5183137ace70 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+experimental-zvfbfa,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+experimental-zvfbfa,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i1> @vfptosi_nxv1f16_nxv1i1(<vscale x 1 x half> %va) strictfp {
@@ -1637,3 +1637,115 @@ define <vscale x 8 x i64> @vfptoui_nxv8f64_nxv8i64(<vscale x 8 x double> %va) st
%evec = call <vscale x 8 x i64> @llvm.experimental.constrained.fptoui.nxv8i64.nxv8f64(<vscale x 8 x double> %va, metadata !"fpexcept.strict")
ret <vscale x 8 x i64> %evec
}
+
+define <vscale x 1 x i1> @vfptosi_nxv1bf16_nxv1i1(<vscale x 1 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: ret
+ %evec = call <vscale x 1 x i1> @llvm.experimental.constrained.fptosi.nxv1i1.nxv1bf16(<vscale x 1 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <vscale x 1 x i1> %evec
+}
+
+define <vscale x 1 x i1> @vfptoui_nxv1bf16_nxv1i1(<vscale x 1 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: ret
+ %evec = call <vscale x 1 x i1> @llvm.experimental.constrained.fptoui.nxv1i1.nxv1bf16(<vscale x 1 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <vscale x 1 x i1> %evec
+}
+
+define <vscale x 1 x i8> @vfptosi_nxv1bf16_nxv1i8(<vscale x 1 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 1 x i8> @llvm.experimental.constrained.fptosi.nxv1i8.nxv1bf16(<vscale x 1 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <vscale x 1 x i8> %evec
+}
+
+define <vscale x 1 x i8> @vfptoui_nxv1bf16_nxv1i8(<vscale x 1 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 1 x i8> @llvm.experimental.constrained.fptoui.nxv1i8.nxv1bf16(<vscale x 1 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <vscale x 1 x i8> %evec
+}
+
+define <vscale x 2 x i8> @vfptosi_nxv2bf16_nxv2i8(<vscale x 2 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 2 x i8> @llvm.experimental.constrained.fptosi.nxv2i8.nxv2bf16(<vscale x 2 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <vscale x 2 x i8> %evec
+}
+
+define <vscale x 2 x i8> @vfptoui_nxv2bf16_nxv2i8(<vscale x 2 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 2 x i8> @llvm.experimental.constrained.fptoui.nxv2i8.nxv2bf16(<vscale x 2 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <vscale x 2 x i8> %evec
+}
+
+define <vscale x 4 x i8> @vfptosi_nxv4bf16_nxv4i8(<vscale x 4 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptosi_nxv4bf16_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 4 x i8> @llvm.experimental.constrained.fptosi.nxv4i8.nxv4bf16(<vscale x 4 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <vscale x 4 x i8> %evec
+}
+
+define <vscale x 4 x i8> @vfptoui_nxv4bf16_nxv4i8(<vscale x 4 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptoui_nxv4bf16_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 4 x i8> @llvm.experimental.constrained.fptoui.nxv4i8.nxv4bf16(<vscale x 4 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <vscale x 4 x i8> %evec
+}
+
+define <vscale x 8 x i8> @vfptosi_nxv8bf16_nxv8i8(<vscale x 8 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptosi_nxv8bf16_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %evec = call <vscale x 8 x i8> @llvm.experimental.constrained.fptosi.nxv8i8.nxv8bf16(<vscale x 8 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <vscale x 8 x i8> %evec
+}
+
+define <vscale x 8 x i8> @vfptoui_nxv8bf16_nxv8i8(<vscale x 8 x bfloat> %va) strictfp {
+; CHECK-LABEL: vfptoui_nxv8bf16_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %evec = call <vscale x 8 x i8> @llvm.experimental.constrained.fptoui.nxv8i8.nxv8bf16(<vscale x 8 x bfloat> %va, metadata !"fpexcept.strict")
+ ret <vscale x 8 x i8> %evec
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
index 45a6a4d95be02..2b8dad87b2af2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
@@ -1,715 +1,1151 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: --check-prefixes=CHECK,ZVFH,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: --check-prefixes=CHECK,ZVFH,ZVFBFMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: --check-prefixes=CHECK,ZVFHMIN,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: --check-prefixes=CHECK,ZVFHMIN,ZVFBFMIN
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+experimental-zvfbfa \
+; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
+; RUN: --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+experimental-zvfbfa \
+; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
+; RUN: --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
define <vscale x 1 x i1> @vfptosi_nxv1bf16_nxv1i1(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv1bf16_nxv1i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv1bf16_nxv1i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v9, 0
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i1>
ret <vscale x 1 x i1> %evec
}
define <vscale x 1 x i7> @vfptosi_nxv1bf16_nxv1i7(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i7:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv1bf16_nxv1i7:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv1bf16_nxv1i7:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i7>
ret <vscale x 1 x i7> %evec
}
define <vscale x 1 x i7> @vfptoui_nxv1bf16_nxv1i7(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i7:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv1bf16_nxv1i7:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv1bf16_nxv1i7:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i7>
ret <vscale x 1 x i7> %evec
}
define <vscale x 1 x i1> @vfptoui_nxv1bf16_nxv1i1(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv1bf16_nxv1i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv1bf16_nxv1i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v9, 0
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i1>
ret <vscale x 1 x i1> %evec
}
define <vscale x 1 x i8> @vfptosi_nxv1bf16_nxv1i8(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv1bf16_nxv1i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv1bf16_nxv1i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec
}
define <vscale x 1 x i8> @vfptoui_nxv1bf16_nxv1i8(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv1bf16_nxv1i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv1bf16_nxv1i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec
}
define <vscale x 1 x i16> @vfptosi_nxv1bf16_nxv1i16(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv1bf16_nxv1i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv1bf16_nxv1i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
}
define <vscale x 1 x i16> @vfptoui_nxv1bf16_nxv1i16(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv1bf16_nxv1i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv1bf16_nxv1i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
}
define <vscale x 1 x i32> @vfptosi_nxv1bf16_nxv1i32(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv1bf16_nxv1i32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.rtz.x.f.v v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv1bf16_nxv1i32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vfcvt.rtz.x.f.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
}
define <vscale x 1 x i32> @vfptoui_nxv1bf16_nxv1i32(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv1bf16_nxv1i32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv1bf16_nxv1i32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vfcvt.rtz.xu.f.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
}
define <vscale x 1 x i64> @vfptosi_nxv1bf16_nxv1i64(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv1bf16_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv1bf16_nxv1i64:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.rtz.x.f.v v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv1bf16_nxv1i64:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.rtz.x.f.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 1 x bfloat> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 1 x i64> @vfptoui_nxv1bf16_nxv1i64(<vscale x 1 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv1bf16_nxv1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv1bf16_nxv1i64:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv1bf16_nxv1i64:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.rtz.xu.f.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 1 x bfloat> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 2 x i1> @vfptosi_nxv2bf16_nxv2i1(<vscale x 2 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv2bf16_nxv2i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv2bf16_nxv2i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v9, 0
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i1>
ret <vscale x 2 x i1> %evec
}
define <vscale x 2 x i1> @vfptoui_nxv2bf16_nxv2i1(<vscale x 2 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv2bf16_nxv2i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv2bf16_nxv2i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v9, 0
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i1>
ret <vscale x 2 x i1> %evec
}
define <vscale x 2 x i8> @vfptosi_nxv2bf16_nxv2i8(<vscale x 2 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv2bf16_nxv2i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv2bf16_nxv2i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec
}
define <vscale x 2 x i8> @vfptoui_nxv2bf16_nxv2i8(<vscale x 2 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv2bf16_nxv2i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv2bf16_nxv2i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec
}
define <vscale x 2 x i16> @vfptosi_nxv2bf16_nxv2i16(<vscale x 2 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv2bf16_nxv2i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv2bf16_nxv2i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
}
define <vscale x 2 x i16> @vfptoui_nxv2bf16_nxv2i16(<vscale x 2 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv2bf16_nxv2i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv2bf16_nxv2i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
}
define <vscale x 2 x i32> @vfptosi_nxv2bf16_nxv2i32(<vscale x 2 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv2bf16_nxv2i32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.rtz.x.f.v v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv2bf16_nxv2i32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFA-NEXT: vfcvt.rtz.x.f.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
}
define <vscale x 2 x i32> @vfptoui_nxv2bf16_nxv2i32(<vscale x 2 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv2bf16_nxv2i32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv2bf16_nxv2i32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFA-NEXT: vfcvt.rtz.xu.f.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
}
define <vscale x 2 x i64> @vfptosi_nxv2bf16_nxv2i64(<vscale x 2 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv2bf16_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv2bf16_nxv2i64:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.rtz.x.f.v v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv2bf16_nxv2i64:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFA-NEXT: vfwcvt.rtz.x.f.v v8, v10
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 2 x bfloat> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 2 x i64> @vfptoui_nxv2bf16_nxv2i64(<vscale x 2 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv2bf16_nxv2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv2bf16_nxv2i64:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv2bf16_nxv2i64:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFA-NEXT: vfwcvt.rtz.xu.f.v v8, v10
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 2 x bfloat> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 4 x i1> @vfptosi_nxv4bf16_nxv4i1(<vscale x 4 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv4bf16_nxv4i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv4bf16_nxv4i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v10
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv4bf16_nxv4i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v9, 0
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 4 x bfloat> %va to <vscale x 4 x i1>
ret <vscale x 4 x i1> %evec
}
define <vscale x 4 x i1> @vfptoui_nxv4bf16_nxv4i1(<vscale x 4 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv4bf16_nxv4i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv4bf16_nxv4i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v10
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv4bf16_nxv4i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v9, 0
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 4 x bfloat> %va to <vscale x 4 x i1>
ret <vscale x 4 x i1> %evec
}
define <vscale x 4 x i8> @vfptosi_nxv4bf16_nxv4i8(<vscale x 4 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv4bf16_nxv4i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv4bf16_nxv4i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v10
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv4bf16_nxv4i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 4 x bfloat> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec
}
define <vscale x 4 x i8> @vfptoui_nxv4bf16_nxv4i8(<vscale x 4 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv4bf16_nxv4i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv4bf16_nxv4i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v10
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv4bf16_nxv4i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 4 x bfloat> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec
}
define <vscale x 4 x i16> @vfptosi_nxv4bf16_nxv4i16(<vscale x 4 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv4bf16_nxv4i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv4bf16_nxv4i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv4bf16_nxv4i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v8, v10
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 4 x bfloat> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
}
define <vscale x 4 x i16> @vfptoui_nxv4bf16_nxv4i16(<vscale x 4 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv4bf16_nxv4i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv4bf16_nxv4i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv4bf16_nxv4i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v8, v10
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 4 x bfloat> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
}
define <vscale x 4 x i32> @vfptosi_nxv4bf16_nxv4i32(<vscale x 4 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv4bf16_nxv4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv4bf16_nxv4i32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.rtz.x.f.v v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv4bf16_nxv4i32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFBFA-NEXT: vfcvt.rtz.x.f.v v8, v10
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 4 x bfloat> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
}
define <vscale x 4 x i32> @vfptoui_nxv4bf16_nxv4i32(<vscale x 4 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv4bf16_nxv4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv4bf16_nxv4i32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.rtz.xu.f.v v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv4bf16_nxv4i32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFBFA-NEXT: vfcvt.rtz.xu.f.v v8, v10
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 4 x bfloat> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
}
define <vscale x 4 x i64> @vfptosi_nxv4bf16_nxv4i64(<vscale x 4 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv4bf16_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv4bf16_nxv4i64:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.rtz.x.f.v v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv4bf16_nxv4i64:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.rtz.x.f.v v8, v12
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 4 x bfloat> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 4 x i64> @vfptoui_nxv4bf16_nxv4i64(<vscale x 4 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv4bf16_nxv4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv4bf16_nxv4i64:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv4bf16_nxv4i64:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.rtz.xu.f.v v8, v12
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 4 x bfloat> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 8 x i1> @vfptosi_nxv8bf16_nxv8i1(<vscale x 8 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv8bf16_nxv8i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv8bf16_nxv8i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v12
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv8bf16_nxv8i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v10, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v10, 0
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 8 x bfloat> %va to <vscale x 8 x i1>
ret <vscale x 8 x i1> %evec
}
define <vscale x 8 x i1> @vfptoui_nxv8bf16_nxv8i1(<vscale x 8 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv8bf16_nxv8i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv8bf16_nxv8i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v12
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv8bf16_nxv8i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v10, 0
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 8 x bfloat> %va to <vscale x 8 x i1>
ret <vscale x 8 x i1> %evec
}
define <vscale x 8 x i8> @vfptosi_nxv8bf16_nxv8i8(<vscale x 8 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv8bf16_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v10, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv8bf16_nxv8i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v10, v12
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v10, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv8bf16_nxv8i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v10, v8
+; ZVFBFA-NEXT: vmv.v.v v8, v10
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 8 x bfloat> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec
}
define <vscale x 8 x i8> @vfptoui_nxv8bf16_nxv8i8(<vscale x 8 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv8bf16_nxv8i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v10, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv8bf16_nxv8i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v10, v12
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v10, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv8bf16_nxv8i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; ZVFBFA-NEXT: vmv.v.v v8, v10
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 8 x bfloat> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec
}
define <vscale x 8 x i16> @vfptosi_nxv8bf16_nxv8i16(<vscale x 8 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv8bf16_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv8bf16_nxv8i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv8bf16_nxv8i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v8, v12
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 8 x bfloat> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
}
define <vscale x 8 x i16> @vfptoui_nxv8bf16_nxv8i16(<vscale x 8 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv8bf16_nxv8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv8bf16_nxv8i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv8bf16_nxv8i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v8, v12
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 8 x bfloat> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
}
define <vscale x 8 x i32> @vfptosi_nxv8bf16_nxv8i32(<vscale x 8 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv8bf16_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv8bf16_nxv8i32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.rtz.x.f.v v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv8bf16_nxv8i32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFBFA-NEXT: vfcvt.rtz.x.f.v v8, v12
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 8 x bfloat> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
}
define <vscale x 8 x i32> @vfptoui_nxv8bf16_nxv8i32(<vscale x 8 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv8bf16_nxv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv8bf16_nxv8i32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.rtz.xu.f.v v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv8bf16_nxv8i32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFBFA-NEXT: vfcvt.rtz.xu.f.v v8, v12
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 8 x bfloat> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
}
define <vscale x 8 x i64> @vfptosi_nxv8bf16_nxv8i64(<vscale x 8 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv8bf16_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv8bf16_nxv8i64:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.rtz.x.f.v v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv8bf16_nxv8i64:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.rtz.x.f.v v8, v16
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 8 x bfloat> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 8 x i64> @vfptoui_nxv8bf16_nxv8i64(<vscale x 8 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv8bf16_nxv8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv8bf16_nxv8i64:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv8bf16_nxv8i64:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.rtz.xu.f.v v8, v16
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 8 x bfloat> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 16 x i1> @vfptosi_nxv16bf16_nxv16i1(<vscale x 16 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv16bf16_nxv16i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv16bf16_nxv16i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v16
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv16bf16_nxv16i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v12, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v12, 0
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 16 x bfloat> %va to <vscale x 16 x i1>
ret <vscale x 16 x i1> %evec
}
define <vscale x 16 x i1> @vfptoui_nxv16bf16_nxv16i1(<vscale x 16 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv16bf16_nxv16i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv16bf16_nxv16i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v16
+; ZVFBFMIN-NEXT: vmsne.vi v0, v8, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv16bf16_nxv16i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v12, 0
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 16 x bfloat> %va to <vscale x 16 x i1>
ret <vscale x 16 x i1> %evec
}
define <vscale x 16 x i8> @vfptosi_nxv16bf16_nxv16i8(<vscale x 16 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv16bf16_nxv16i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv16bf16_nxv16i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v12, v16
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v12, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv16bf16_nxv16i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v12, v8
+; ZVFBFA-NEXT: vmv.v.v v8, v12
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 16 x bfloat> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %evec
}
define <vscale x 16 x i8> @vfptoui_nxv16bf16_nxv16i8(<vscale x 16 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv16bf16_nxv16i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv16bf16_nxv16i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v12, v16
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v12, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv16bf16_nxv16i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; ZVFBFA-NEXT: vmv.v.v v8, v12
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 16 x bfloat> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %evec
}
define <vscale x 16 x i16> @vfptosi_nxv16bf16_nxv16i16(<vscale x 16 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv16bf16_nxv16i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv16bf16_nxv16i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv16bf16_nxv16i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v8, v16
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 16 x bfloat> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
}
define <vscale x 16 x i16> @vfptoui_nxv16bf16_nxv16i16(<vscale x 16 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv16bf16_nxv16i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv16bf16_nxv16i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv16bf16_nxv16i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v8, v16
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 16 x bfloat> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
}
define <vscale x 16 x i32> @vfptosi_nxv16bf16_nxv16i32(<vscale x 16 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv16bf16_nxv16i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv16bf16_nxv16i32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.rtz.x.f.v v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv16bf16_nxv16i32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFBFA-NEXT: vfcvt.rtz.x.f.v v8, v16
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 16 x bfloat> %va to <vscale x 16 x i32>
ret <vscale x 16 x i32> %evec
}
define <vscale x 16 x i32> @vfptoui_nxv16bf16_nxv16i32(<vscale x 16 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv16bf16_nxv16i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv16bf16_nxv16i32:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.rtz.xu.f.v v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv16bf16_nxv16i32:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFBFA-NEXT: vfcvt.rtz.xu.f.v v8, v16
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 16 x bfloat> %va to <vscale x 16 x i32>
ret <vscale x 16 x i32> %evec
}
define <vscale x 32 x i1> @vfptosi_nxv32bf16_nxv32i1(<vscale x 32 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv32bf16_nxv32i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16
-; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v24
-; CHECK-NEXT: vmsne.vi v16, v8, 0
-; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v16, a0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv32bf16_nxv32i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: csrr a0, vlenb
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v12
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v8
+; ZVFBFMIN-NEXT: srli a0, a0, 2
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v16
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v12, v24
+; ZVFBFMIN-NEXT: vmsne.vi v16, v8, 0
+; ZVFBFMIN-NEXT: vmsne.vi v0, v12, 0
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; ZVFBFMIN-NEXT: vslideup.vx v0, v16, a0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv32bf16_nxv32i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v16, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v16, 0
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 32 x bfloat> %va to <vscale x 32 x i1>
ret <vscale x 32 x i1> %evec
}
define <vscale x 32 x i1> @vfptoui_nxv32bf16_nxv32i1(<vscale x 32 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv32bf16_nxv32i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v24
-; CHECK-NEXT: vmsne.vi v16, v8, 0
-; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v16, a0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv32bf16_nxv32i1:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: csrr a0, vlenb
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v12
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v8
+; ZVFBFMIN-NEXT: srli a0, a0, 2
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v16
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v12, v24
+; ZVFBFMIN-NEXT: vmsne.vi v16, v8, 0
+; ZVFBFMIN-NEXT: vmsne.vi v0, v12, 0
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; ZVFBFMIN-NEXT: vslideup.vx v0, v16, a0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv32bf16_nxv32i1:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; ZVFBFA-NEXT: vmsne.vi v0, v16, 0
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 32 x bfloat> %va to <vscale x 32 x i1>
ret <vscale x 32 x i1> %evec
}
define <vscale x 32 x i8> @vfptosi_nxv32bf16_nxv32i8(<vscale x 32 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv32bf16_nxv32i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
-; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v24
-; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v10, v12, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv32bf16_nxv32i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v12
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v12, v16
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v12, 0
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v12, v24
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v10, v12, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv32bf16_nxv32i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v16, v8
+; ZVFBFA-NEXT: vmv.v.v v8, v16
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 32 x bfloat> %va to <vscale x 32 x i8>
ret <vscale x 32 x i8> %evec
}
define <vscale x 32 x i8> @vfptoui_nxv32bf16_nxv32i8(<vscale x 32 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv32bf16_nxv32i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v24
-; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v10, v12, 0
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv32bf16_nxv32i8:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v12
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v12, v16
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v8, v12, 0
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v12, v24
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
+; ZVFBFMIN-NEXT: vnsrl.wi v10, v12, 0
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv32bf16_nxv32i8:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; ZVFBFA-NEXT: vmv.v.v v8, v16
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 32 x bfloat> %va to <vscale x 32 x i8>
ret <vscale x 32 x i8> %evec
}
define <vscale x 32 x i16> @vfptosi_nxv32bf16_nxv32i16(<vscale x 32 x bfloat> %va) {
-; CHECK-LABEL: vfptosi_nxv32bf16_nxv32i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12
-; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptosi_nxv32bf16_nxv32i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v8, v16
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v12
+; ZVFBFMIN-NEXT: vfncvt.rtz.x.f.w v12, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptosi_nxv32bf16_nxv32i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v8, v16
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.x.f.w v12, v16
+; ZVFBFA-NEXT: ret
%evec = fptosi <vscale x 32 x bfloat> %va to <vscale x 32 x i16>
ret <vscale x 32 x i16> %evec
}
define <vscale x 32 x i16> @vfptoui_nxv32bf16_nxv32i16(<vscale x 32 x bfloat> %va) {
-; CHECK-LABEL: vfptoui_nxv32bf16_nxv32i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vfptoui_nxv32bf16_nxv32i16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v8, v16
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v12
+; ZVFBFMIN-NEXT: vfncvt.rtz.xu.f.w v12, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vfptoui_nxv32bf16_nxv32i16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v8, v16
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.rtz.xu.f.w v12, v16
+; ZVFBFA-NEXT: ret
%evec = fptoui <vscale x 32 x bfloat> %va to <vscale x 32 x i16>
ret <vscale x 32 x i16> %evec
}
@@ -721,7 +1157,6 @@ define <vscale x 1 x i1> @vfptosi_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv1f16_nxv1i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -740,7 +1175,6 @@ define <vscale x 1 x i7> @vfptosi_nxv1f16_nxv1i7(<vscale x 1 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv1f16_nxv1i7:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -760,7 +1194,6 @@ define <vscale x 1 x i7> @vfptoui_nxv1f16_nxv1i7(<vscale x 1 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv1f16_nxv1i7:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -780,7 +1213,6 @@ define <vscale x 1 x i1> @vfptoui_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv1f16_nxv1i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -799,7 +1231,6 @@ define <vscale x 1 x i8> @vfptosi_nxv1f16_nxv1i8(<vscale x 1 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv1f16_nxv1i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -819,7 +1250,6 @@ define <vscale x 1 x i8> @vfptoui_nxv1f16_nxv1i8(<vscale x 1 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv1f16_nxv1i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -838,7 +1268,6 @@ define <vscale x 1 x i16> @vfptosi_nxv1f16_nxv1i16(<vscale x 1 x half> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv1f16_nxv1i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -855,7 +1284,6 @@ define <vscale x 1 x i16> @vfptoui_nxv1f16_nxv1i16(<vscale x 1 x half> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.rtz.xu.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv1f16_nxv1i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -873,7 +1301,6 @@ define <vscale x 1 x i32> @vfptosi_nxv1f16_nxv1i32(<vscale x 1 x half> %va) {
; ZVFH-NEXT: vfwcvt.rtz.x.f.v v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv1f16_nxv1i32:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -892,7 +1319,6 @@ define <vscale x 1 x i32> @vfptoui_nxv1f16_nxv1i32(<vscale x 1 x half> %va) {
; ZVFH-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv1f16_nxv1i32:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -935,7 +1361,6 @@ define <vscale x 2 x i1> @vfptosi_nxv2f16_nxv2i1(<vscale x 2 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv2f16_nxv2i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -954,7 +1379,6 @@ define <vscale x 2 x i1> @vfptoui_nxv2f16_nxv2i1(<vscale x 2 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv2f16_nxv2i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -973,7 +1397,6 @@ define <vscale x 2 x i8> @vfptosi_nxv2f16_nxv2i8(<vscale x 2 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv2f16_nxv2i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -993,7 +1416,6 @@ define <vscale x 2 x i8> @vfptoui_nxv2f16_nxv2i8(<vscale x 2 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv2f16_nxv2i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1012,7 +1434,6 @@ define <vscale x 2 x i16> @vfptosi_nxv2f16_nxv2i16(<vscale x 2 x half> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv2f16_nxv2i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1029,7 +1450,6 @@ define <vscale x 2 x i16> @vfptoui_nxv2f16_nxv2i16(<vscale x 2 x half> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.rtz.xu.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv2f16_nxv2i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1047,7 +1467,6 @@ define <vscale x 2 x i32> @vfptosi_nxv2f16_nxv2i32(<vscale x 2 x half> %va) {
; ZVFH-NEXT: vfwcvt.rtz.x.f.v v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv2f16_nxv2i32:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1066,7 +1485,6 @@ define <vscale x 2 x i32> @vfptoui_nxv2f16_nxv2i32(<vscale x 2 x half> %va) {
; ZVFH-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv2f16_nxv2i32:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1109,7 +1527,6 @@ define <vscale x 4 x i1> @vfptosi_nxv4f16_nxv4i1(<vscale x 4 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv4f16_nxv4i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1128,7 +1545,6 @@ define <vscale x 4 x i1> @vfptoui_nxv4f16_nxv4i1(<vscale x 4 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv4f16_nxv4i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1147,7 +1563,6 @@ define <vscale x 4 x i8> @vfptosi_nxv4f16_nxv4i8(<vscale x 4 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv4f16_nxv4i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1167,7 +1582,6 @@ define <vscale x 4 x i8> @vfptoui_nxv4f16_nxv4i8(<vscale x 4 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv4f16_nxv4i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1186,7 +1600,6 @@ define <vscale x 4 x i16> @vfptosi_nxv4f16_nxv4i16(<vscale x 4 x half> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv4f16_nxv4i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1203,7 +1616,6 @@ define <vscale x 4 x i16> @vfptoui_nxv4f16_nxv4i16(<vscale x 4 x half> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.rtz.xu.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv4f16_nxv4i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1221,7 +1633,6 @@ define <vscale x 4 x i32> @vfptosi_nxv4f16_nxv4i32(<vscale x 4 x half> %va) {
; ZVFH-NEXT: vmv1r.v v10, v8
; ZVFH-NEXT: vfwcvt.rtz.x.f.v v8, v10
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv4f16_nxv4i32:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1240,7 +1651,6 @@ define <vscale x 4 x i32> @vfptoui_nxv4f16_nxv4i32(<vscale x 4 x half> %va) {
; ZVFH-NEXT: vmv1r.v v10, v8
; ZVFH-NEXT: vfwcvt.rtz.xu.f.v v8, v10
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv4f16_nxv4i32:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1283,7 +1693,6 @@ define <vscale x 8 x i1> @vfptosi_nxv8f16_nxv8i1(<vscale x 8 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v10, v8
; ZVFH-NEXT: vmsne.vi v0, v10, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv8f16_nxv8i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1302,7 +1711,6 @@ define <vscale x 8 x i1> @vfptoui_nxv8f16_nxv8i1(<vscale x 8 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v10, v8
; ZVFH-NEXT: vmsne.vi v0, v10, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv8f16_nxv8i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1321,7 +1729,6 @@ define <vscale x 8 x i8> @vfptosi_nxv8f16_nxv8i8(<vscale x 8 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v10, v8
; ZVFH-NEXT: vmv.v.v v8, v10
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv8f16_nxv8i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1341,7 +1748,6 @@ define <vscale x 8 x i8> @vfptoui_nxv8f16_nxv8i8(<vscale x 8 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v10, v8
; ZVFH-NEXT: vmv.v.v v8, v10
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv8f16_nxv8i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1360,7 +1766,6 @@ define <vscale x 8 x i16> @vfptosi_nxv8f16_nxv8i16(<vscale x 8 x half> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv8f16_nxv8i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1377,7 +1782,6 @@ define <vscale x 8 x i16> @vfptoui_nxv8f16_nxv8i16(<vscale x 8 x half> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT: vfcvt.rtz.xu.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv8f16_nxv8i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1395,7 +1799,6 @@ define <vscale x 8 x i32> @vfptosi_nxv8f16_nxv8i32(<vscale x 8 x half> %va) {
; ZVFH-NEXT: vmv2r.v v12, v8
; ZVFH-NEXT: vfwcvt.rtz.x.f.v v8, v12
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv8f16_nxv8i32:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1414,7 +1817,6 @@ define <vscale x 8 x i32> @vfptoui_nxv8f16_nxv8i32(<vscale x 8 x half> %va) {
; ZVFH-NEXT: vmv2r.v v12, v8
; ZVFH-NEXT: vfwcvt.rtz.xu.f.v v8, v12
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv8f16_nxv8i32:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1457,7 +1859,6 @@ define <vscale x 16 x i1> @vfptosi_nxv16f16_nxv16i1(<vscale x 16 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v12, v8
; ZVFH-NEXT: vmsne.vi v0, v12, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv16f16_nxv16i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1476,7 +1877,6 @@ define <vscale x 16 x i1> @vfptoui_nxv16f16_nxv16i1(<vscale x 16 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v12, v8
; ZVFH-NEXT: vmsne.vi v0, v12, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv16f16_nxv16i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1495,7 +1895,6 @@ define <vscale x 16 x i8> @vfptosi_nxv16f16_nxv16i8(<vscale x 16 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v12, v8
; ZVFH-NEXT: vmv.v.v v8, v12
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv16f16_nxv16i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1515,7 +1914,6 @@ define <vscale x 16 x i8> @vfptoui_nxv16f16_nxv16i8(<vscale x 16 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v12, v8
; ZVFH-NEXT: vmv.v.v v8, v12
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv16f16_nxv16i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1534,7 +1932,6 @@ define <vscale x 16 x i16> @vfptosi_nxv16f16_nxv16i16(<vscale x 16 x half> %va)
; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv16f16_nxv16i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1551,7 +1948,6 @@ define <vscale x 16 x i16> @vfptoui_nxv16f16_nxv16i16(<vscale x 16 x half> %va)
; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFH-NEXT: vfcvt.rtz.xu.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv16f16_nxv16i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1569,7 +1965,6 @@ define <vscale x 16 x i32> @vfptosi_nxv16f16_nxv16i32(<vscale x 16 x half> %va)
; ZVFH-NEXT: vmv4r.v v16, v8
; ZVFH-NEXT: vfwcvt.rtz.x.f.v v8, v16
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv16f16_nxv16i32:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1588,7 +1983,6 @@ define <vscale x 16 x i32> @vfptoui_nxv16f16_nxv16i32(<vscale x 16 x half> %va)
; ZVFH-NEXT: vmv4r.v v16, v8
; ZVFH-NEXT: vfwcvt.rtz.xu.f.v v8, v16
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv16f16_nxv16i32:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1607,7 +2001,6 @@ define <vscale x 32 x i1> @vfptosi_nxv32f16_nxv32i1(<vscale x 32 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v16, v8
; ZVFH-NEXT: vmsne.vi v0, v16, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv32f16_nxv32i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -1633,7 +2026,6 @@ define <vscale x 32 x i1> @vfptoui_nxv32f16_nxv32i1(<vscale x 32 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v16, v8
; ZVFH-NEXT: vmsne.vi v0, v16, 0
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv32f16_nxv32i1:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -1659,7 +2051,6 @@ define <vscale x 32 x i8> @vfptosi_nxv32f16_nxv32i8(<vscale x 32 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.x.f.w v16, v8
; ZVFH-NEXT: vmv.v.v v8, v16
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv32f16_nxv32i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1684,7 +2075,6 @@ define <vscale x 32 x i8> @vfptoui_nxv32f16_nxv32i8(<vscale x 32 x half> %va) {
; ZVFH-NEXT: vfncvt.rtz.xu.f.w v16, v8
; ZVFH-NEXT: vmv.v.v v8, v16
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv32f16_nxv32i8:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1708,7 +2098,6 @@ define <vscale x 32 x i16> @vfptosi_nxv32f16_nxv32i16(<vscale x 32 x half> %va)
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptosi_nxv32f16_nxv32i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1727,7 +2116,6 @@ define <vscale x 32 x i16> @vfptoui_nxv32f16_nxv32i16(<vscale x 32 x half> %va)
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT: vfcvt.rtz.xu.f.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vfptoui_nxv32f16_nxv32i16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
index b93a4c166538a..80b32694e48f4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+experimental-zvfbfa,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+experimental-zvfbfa,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vsitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) strictfp {
@@ -1597,3 +1597,115 @@ define <vscale x 8 x double> @vuitofp_nxv8i64_nxv8f64(<vscale x 8 x i64> %va) st
%evec = call <vscale x 8 x double> @llvm.experimental.constrained.uitofp.nxv8f64.nxv8i64(<vscale x 8 x i64> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret <vscale x 8 x double> %evec
}
+
+define <vscale x 1 x bfloat> @vsitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) strictfp {
+; CHECK-LABEL: vsitofp_nxv1i1_nxv1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
+; CHECK-NEXT: vfwcvt.f.x.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 1 x bfloat> @llvm.experimental.constrained.sitofp.nxv1bf16.nxv1i1(<vscale x 1 x i1> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <vscale x 1 x bfloat> %evec
+}
+
+define <vscale x 1 x bfloat> @vuitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) strictfp {
+; CHECK-LABEL: vuitofp_nxv1i1_nxv1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
+; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 1 x bfloat> @llvm.experimental.constrained.uitofp.nxv1bf16.nxv1i1(<vscale x 1 x i1> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <vscale x 1 x bfloat> %evec
+}
+
+define <vscale x 1 x bfloat> @vsitofp_nxv1i8_nxv1bf16(<vscale x 1 x i8> %va) strictfp {
+; CHECK-LABEL: vsitofp_nxv1i8_nxv1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 1 x bfloat> @llvm.experimental.constrained.sitofp.nxv1bf16.nxv1i8(<vscale x 1 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <vscale x 1 x bfloat> %evec
+}
+
+define <vscale x 1 x bfloat> @vuitofp_nxv1i8_nxv1bf16(<vscale x 1 x i8> %va) strictfp {
+; CHECK-LABEL: vuitofp_nxv1i8_nxv1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 1 x bfloat> @llvm.experimental.constrained.uitofp.nxv1bf16.nxv1i8(<vscale x 1 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <vscale x 1 x bfloat> %evec
+}
+
+define <vscale x 2 x bfloat> @vsitofp_nxv2i8_nxv2bf16(<vscale x 2 x i8> %va) strictfp {
+; CHECK-LABEL: vsitofp_nxv2i8_nxv2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 2 x bfloat> @llvm.experimental.constrained.sitofp.nxv2bf16.nxv2i8(<vscale x 2 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <vscale x 2 x bfloat> %evec
+}
+
+define <vscale x 2 x bfloat> @vuitofp_nxv2i8_nxv2bf16(<vscale x 2 x i8> %va) strictfp {
+; CHECK-LABEL: vuitofp_nxv2i8_nxv2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 2 x bfloat> @llvm.experimental.constrained.uitofp.nxv2bf16.nxv2i8(<vscale x 2 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <vscale x 2 x bfloat> %evec
+}
+
+define <vscale x 4 x bfloat> @vsitofp_nxv4i8_nxv4bf16(<vscale x 4 x i8> %va) strictfp {
+; CHECK-LABEL: vsitofp_nxv4i8_nxv4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 4 x bfloat> @llvm.experimental.constrained.sitofp.nxv4bf16.nxv4i8(<vscale x 4 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <vscale x 4 x bfloat> %evec
+}
+
+define <vscale x 4 x bfloat> @vuitofp_nxv4i8_nxv4bf16(<vscale x 4 x i8> %va) strictfp {
+; CHECK-LABEL: vuitofp_nxv4i8_nxv4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %evec = call <vscale x 4 x bfloat> @llvm.experimental.constrained.uitofp.nxv4bf16.nxv4i8(<vscale x 4 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <vscale x 4 x bfloat> %evec
+}
+
+define <vscale x 8 x bfloat> @vsitofp_nxv8i8_nxv8bf16(<vscale x 8 x i8> %va) strictfp {
+; CHECK-LABEL: vsitofp_nxv8i8_nxv8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: vfwcvt.f.x.v v8, v10
+; CHECK-NEXT: ret
+ %evec = call <vscale x 8 x bfloat> @llvm.experimental.constrained.sitofp.nxv8bf16.nxv8i8(<vscale x 8 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <vscale x 8 x bfloat> %evec
+}
+
+define <vscale x 8 x bfloat> @vuitofp_nxv8i8_nxv8bf16(<vscale x 8 x i8> %va) strictfp {
+; CHECK-LABEL: vuitofp_nxv8i8_nxv8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: vfwcvt.f.xu.v v8, v10
+; CHECK-NEXT: ret
+ %evec = call <vscale x 8 x bfloat> @llvm.experimental.constrained.uitofp.nxv8bf16.nxv8i8(<vscale x 8 x i8> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
+ ret <vscale x 8 x bfloat> %evec
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
index 95b1c35d48bb3..146fb7b62c0a6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
@@ -1,717 +1,1167 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: --check-prefixes=CHECK,ZVFH,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: --check-prefixes=CHECK,ZVFH,ZVFBFMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: --check-prefixes=CHECK,ZVFHMIN,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: --check-prefixes=CHECK,ZVFHMIN,ZVFBFMIN
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+experimental-zvfbfa \
+; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
+; RUN: --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+experimental-zvfbfa \
+; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
+; RUN: --check-prefixes=CHECK,ZVFHMIN,ZVFBFA
define <vscale x 1 x bfloat> @vsitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) {
-; CHECK-LABEL: vsitofp_nxv1i1_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv1i1_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv1i1_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v9, v8, -1, v0
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vuitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) {
-; CHECK-LABEL: vuitofp_nxv1i1_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv1i1_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv1i1_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v9, v8, 1, v0
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vsitofp_nxv2i1_nxv2bf16(<vscale x 2 x i1> %va) {
-; CHECK-LABEL: vsitofp_nxv2i1_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv2i1_nxv2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv2i1_nxv2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v9, v8, -1, v0
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vuitofp_nxv2i1_nxv2bf16(<vscale x 2 x i1> %va) {
-; CHECK-LABEL: vuitofp_nxv2i1_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv2i1_nxv2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv2i1_nxv2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v9, v8, 1, v0
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vsitofp_nxv4i1_nxv4bf16(<vscale x 4 x i1> %va) {
-; CHECK-LABEL: vsitofp_nxv4i1_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v10, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv4i1_nxv4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v10, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv4i1_nxv4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v9, v8, -1, v0
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vuitofp_nxv4i1_nxv4bf16(<vscale x 4 x i1> %va) {
-; CHECK-LABEL: vuitofp_nxv4i1_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv4i1_nxv4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v10, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv4i1_nxv4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v9, v8, 1, v0
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vsitofp_nxv8i1_nxv8bf16(<vscale x 8 x i1> %va) {
-; CHECK-LABEL: vsitofp_nxv8i1_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v12, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv8i1_nxv8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v12, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv8i1_nxv8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v10, v8, -1, v0
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v10
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vuitofp_nxv8i1_nxv8bf16(<vscale x 8 x i1> %va) {
-; CHECK-LABEL: vuitofp_nxv8i1_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv8i1_nxv8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v12, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv8i1_nxv8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v10, v8, 1, v0
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v10
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 16 x bfloat> @vsitofp_nxv16i1_nxv16bf16(<vscale x 16 x i1> %va) {
-; CHECK-LABEL: vsitofp_nxv16i1_nxv16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v16, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv16i1_nxv16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, -1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv16i1_nxv16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m2, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v12, v8, -1, v0
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v12
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 16 x i1> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
}
define <vscale x 16 x bfloat> @vuitofp_nxv16i1_nxv16bf16(<vscale x 16 x i1> %va) {
-; CHECK-LABEL: vuitofp_nxv16i1_nxv16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv16i1_nxv16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v8, 0
+; ZVFBFMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv16i1_nxv16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m2, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v12, v8, 1, v0
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v12
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 16 x i1> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
}
define <vscale x 32 x bfloat> @vsitofp_nxv32i1_nxv32bf16(<vscale x 32 x i1> %va) {
-; CHECK-LABEL: vsitofp_nxv32i1_nxv32bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v8, v12, -1, v0
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vfwcvt.f.x.v v16, v8
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a0
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: vmerge.vim v12, v12, -1, v0
-; CHECK-NEXT: vfwcvt.f.x.v v16, v12
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv32i1_nxv32bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v12, 0
+; ZVFBFMIN-NEXT: csrr a0, vlenb
+; ZVFBFMIN-NEXT: vmerge.vim v8, v12, -1, v0
+; ZVFBFMIN-NEXT: srli a0, a0, 2
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; ZVFBFMIN-NEXT: vslidedown.vx v0, v0, a0
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: vmerge.vim v12, v12, -1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v12
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v12, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv32i1_nxv32bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m4, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v16, v8, -1, v0
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v16
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 32 x i1> %va to <vscale x 32 x bfloat>
ret <vscale x 32 x bfloat> %evec
}
define <vscale x 32 x bfloat> @vuitofp_nxv32i1_nxv32bf16(<vscale x 32 x i1> %va) {
-; CHECK-LABEL: vuitofp_nxv32i1_nxv32bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a0
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv32i1_nxv32bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vmv.v.i v12, 0
+; ZVFBFMIN-NEXT: csrr a0, vlenb
+; ZVFBFMIN-NEXT: vmerge.vim v8, v12, 1, v0
+; ZVFBFMIN-NEXT: srli a0, a0, 2
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; ZVFBFMIN-NEXT: vslidedown.vx v0, v0, a0
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: vmerge.vim v12, v12, 1, v0
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v12
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v12, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv32i1_nxv32bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m4, ta, ma
+; ZVFBFA-NEXT: vmv.v.i v8, 0
+; ZVFBFA-NEXT: vmerge.vim v16, v8, 1, v0
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v16
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 32 x i1> %va to <vscale x 32 x bfloat>
ret <vscale x 32 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vsitofp_nxv1i8_nxv1bf16(<vscale x 1 x i8> %va) {
-; CHECK-LABEL: vsitofp_nxv1i8_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vsext.vf2 v9, v8
-; CHECK-NEXT: vfwcvt.f.x.v v10, v9
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv1i8_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vsext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v10, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv1i8_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 1 x i8> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vsitofp_nxv1i7_nxv1bf16(<vscale x 1 x i7> %va) {
-; CHECK-LABEL: vsitofp_nxv1i7_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vadd.vv v8, v8, v8
-; CHECK-NEXT: vsra.vi v8, v8, 1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vsext.vf2 v9, v8
-; CHECK-NEXT: vfwcvt.f.x.v v10, v9
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv1i7_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; ZVFBFMIN-NEXT: vadd.vv v8, v8, v8
+; ZVFBFMIN-NEXT: vsra.vi v8, v8, 1
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vsext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v10, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv1i7_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vadd.vv v8, v8, v8
+; ZVFBFA-NEXT: vsra.vi v9, v8, 1
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 1 x i7> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vuitofp_nxv1i7_nxv1bf16(<vscale x 1 x i7> %va) {
-; CHECK-LABEL: vuitofp_nxv1i7_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 127
-; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vzext.vf2 v9, v8
-; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv1i7_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: li a0, 127
+; ZVFBFMIN-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vzext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v10, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv1i7_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a0, 127
+; ZVFBFA-NEXT: vsetvli a1, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vand.vx v9, v8, a0
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 1 x i7> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vuitofp_nxv1i8_nxv1bf16(<vscale x 1 x i8> %va) {
-; CHECK-LABEL: vuitofp_nxv1i8_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vzext.vf2 v9, v8
-; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv1i8_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vzext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v10, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv1i8_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf8, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 1 x i8> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vsitofp_nxv2i8_nxv2bf16(<vscale x 2 x i8> %va) {
-; CHECK-LABEL: vsitofp_nxv2i8_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vsext.vf2 v9, v8
-; CHECK-NEXT: vfwcvt.f.x.v v10, v9
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv2i8_nxv2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vsext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v10, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv2i8_nxv2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 2 x i8> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vuitofp_nxv2i8_nxv2bf16(<vscale x 2 x i8> %va) {
-; CHECK-LABEL: vuitofp_nxv2i8_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vzext.vf2 v9, v8
-; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv2i8_nxv2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vzext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v10, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv2i8_nxv2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 2 x i8> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vsitofp_nxv4i8_nxv4bf16(<vscale x 4 x i8> %va) {
-; CHECK-LABEL: vsitofp_nxv4i8_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vsext.vf2 v9, v8
-; CHECK-NEXT: vfwcvt.f.x.v v10, v9
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv4i8_nxv4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vsext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v10, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv4i8_nxv4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 4 x i8> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vuitofp_nxv4i8_nxv4bf16(<vscale x 4 x i8> %va) {
-; CHECK-LABEL: vuitofp_nxv4i8_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v9, v8
-; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv4i8_nxv4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vzext.vf2 v9, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v10, v9
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv4i8_nxv4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 4 x i8> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vsitofp_nxv8i8_nxv8bf16(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: vsitofp_nxv8i8_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vsext.vf2 v10, v8
-; CHECK-NEXT: vfwcvt.f.x.v v12, v10
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv8i8_nxv8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vsext.vf2 v10, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v12, v10
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv8i8_nxv8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; ZVFBFA-NEXT: vmv1r.v v10, v8
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v10
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 8 x i8> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vuitofp_nxv8i8_nxv8bf16(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: vuitofp_nxv8i8_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vzext.vf2 v10, v8
-; CHECK-NEXT: vfwcvt.f.xu.v v12, v10
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv8i8_nxv8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vzext.vf2 v10, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v12, v10
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv8i8_nxv8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m1, ta, ma
+; ZVFBFA-NEXT: vmv1r.v v10, v8
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v10
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 8 x i8> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 16 x bfloat> @vsitofp_nxv16i8_nxv16bf16(<vscale x 16 x i8> %va) {
-; CHECK-LABEL: vsitofp_nxv16i8_nxv16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vsext.vf2 v12, v8
-; CHECK-NEXT: vfwcvt.f.x.v v16, v12
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv16i8_nxv16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vsext.vf2 v12, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v12
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv16i8_nxv16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m2, ta, ma
+; ZVFBFA-NEXT: vmv2r.v v12, v8
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v12
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 16 x i8> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
}
define <vscale x 16 x bfloat> @vuitofp_nxv16i8_nxv16bf16(<vscale x 16 x i8> %va) {
-; CHECK-LABEL: vuitofp_nxv16i8_nxv16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv16i8_nxv16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vzext.vf2 v12, v8
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v12
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv16i8_nxv16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m2, ta, ma
+; ZVFBFA-NEXT: vmv2r.v v12, v8
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v12
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 16 x i8> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
}
define <vscale x 32 x bfloat> @vsitofp_nxv32i8_nxv32bf16(<vscale x 32 x i8> %va) {
-; CHECK-LABEL: vsitofp_nxv32i8_nxv32bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vsext.vf2 v12, v8
-; CHECK-NEXT: vsext.vf2 v24, v10
-; CHECK-NEXT: vfwcvt.f.x.v v16, v12
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: vfwcvt.f.x.v v16, v24
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv32i8_nxv32bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vsext.vf2 v12, v8
+; ZVFBFMIN-NEXT: vsext.vf2 v24, v10
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v12
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v24
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v12, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv32i8_nxv32bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m4, ta, ma
+; ZVFBFA-NEXT: vmv4r.v v16, v8
+; ZVFBFA-NEXT: vfwcvt.f.x.v v8, v16
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 32 x i8> %va to <vscale x 32 x bfloat>
ret <vscale x 32 x bfloat> %evec
}
define <vscale x 32 x bfloat> @vuitofp_nxv32i8_nxv32bf16(<vscale x 32 x i8> %va) {
-; CHECK-LABEL: vuitofp_nxv32i8_nxv32bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vzext.vf2 v24, v10
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v24
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv32i8_nxv32bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vzext.vf2 v12, v8
+; ZVFBFMIN-NEXT: vzext.vf2 v24, v10
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v12
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v24
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v12, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv32i8_nxv32bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e8alt, m4, ta, ma
+; ZVFBFA-NEXT: vmv4r.v v16, v8
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v8, v16
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 32 x i8> %va to <vscale x 32 x bfloat>
ret <vscale x 32 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vsitofp_nxv1i16_nxv1bf16(<vscale x 1 x i16> %va) {
-; CHECK-LABEL: vsitofp_nxv1i16_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvt.f.x.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv1i16_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv1i16_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 1 x i16> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vuitofp_nxv1i16_nxv1bf16(<vscale x 1 x i16> %va) {
-; CHECK-LABEL: vuitofp_nxv1i16_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv1i16_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv1i16_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 1 x i16> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vsitofp_nxv2i16_nxv2bf16(<vscale x 2 x i16> %va) {
-; CHECK-LABEL: vsitofp_nxv2i16_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.f.x.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv2i16_nxv2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv2i16_nxv2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 2 x i16> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vuitofp_nxv2i16_nxv2bf16(<vscale x 2 x i16> %va) {
-; CHECK-LABEL: vuitofp_nxv2i16_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv2i16_nxv2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv2i16_nxv2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 2 x i16> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vsitofp_nxv4i16_nxv4bf16(<vscale x 4 x i16> %va) {
-; CHECK-LABEL: vsitofp_nxv4i16_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvt.f.x.v v10, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv4i16_nxv4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v10, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv4i16_nxv4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v10
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 4 x i16> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vuitofp_nxv4i16_nxv4bf16(<vscale x 4 x i16> %va) {
-; CHECK-LABEL: vuitofp_nxv4i16_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv4i16_nxv4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v10, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv4i16_nxv4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v10
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 4 x i16> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vsitofp_nxv8i16_nxv8bf16(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: vsitofp_nxv8i16_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvt.f.x.v v12, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv8i16_nxv8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v12, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv8i16_nxv8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v12
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 8 x i16> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vuitofp_nxv8i16_nxv8bf16(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: vuitofp_nxv8i16_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv8i16_nxv8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v12, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv8i16_nxv8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v12
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 8 x i16> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 16 x bfloat> @vsitofp_nxv16i16_nxv16bf16(<vscale x 16 x i16> %va) {
-; CHECK-LABEL: vsitofp_nxv16i16_nxv16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvt.f.x.v v16, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv16i16_nxv16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv16i16_nxv16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 16 x i16> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
}
define <vscale x 16 x bfloat> @vuitofp_nxv16i16_nxv16bf16(<vscale x 16 x i16> %va) {
-; CHECK-LABEL: vuitofp_nxv16i16_nxv16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv16i16_nxv16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv16i16_nxv16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 16 x i16> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
}
define <vscale x 32 x bfloat> @vsitofp_nxv32i16_nxv32bf16(<vscale x 32 x i16> %va) {
-; CHECK-LABEL: vsitofp_nxv32i16_nxv32bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvt.f.x.v v16, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: vfwcvt.f.x.v v16, v12
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv32i16_nxv32bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: vfwcvt.f.x.v v16, v12
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v12, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv32i16_nxv32bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.x.v v16, v12
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v12, v16
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 32 x i16> %va to <vscale x 32 x bfloat>
ret <vscale x 32 x bfloat> %evec
}
define <vscale x 32 x bfloat> @vuitofp_nxv32i16_nxv32bf16(<vscale x 32 x i16> %va) {
-; CHECK-LABEL: vuitofp_nxv32i16_nxv32bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv32i16_nxv32bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v8
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: vfwcvt.f.xu.v v16, v12
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v12, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv32i16_nxv32bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
+; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.xu.v v16, v12
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v12, v16
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 32 x i16> %va to <vscale x 32 x bfloat>
ret <vscale x 32 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vsitofp_nxv1i32_nxv1bf16(<vscale x 1 x i32> %va) {
-; CHECK-LABEL: vsitofp_nxv1i32_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.f.x.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv1i32_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.f.x.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv1i32_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vfcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 1 x i32> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vuitofp_nxv1i32_nxv1bf16(<vscale x 1 x i32> %va) {
-; CHECK-LABEL: vuitofp_nxv1i32_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.f.xu.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv1i32_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.f.xu.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv1i32_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vfcvt.f.xu.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 1 x i32> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vsitofp_nxv2i32_nxv2bf16(<vscale x 2 x i32> %va) {
-; CHECK-LABEL: vsitofp_nxv2i32_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.f.x.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv2i32_nxv2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.f.x.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv2i32_nxv2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVFBFA-NEXT: vfcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 2 x i32> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vuitofp_nxv2i32_nxv2bf16(<vscale x 2 x i32> %va) {
-; CHECK-LABEL: vuitofp_nxv2i32_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.f.xu.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv2i32_nxv2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.f.xu.v v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv2i32_nxv2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVFBFA-NEXT: vfcvt.f.xu.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 2 x i32> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vsitofp_nxv4i32_nxv4bf16(<vscale x 4 x i32> %va) {
-; CHECK-LABEL: vsitofp_nxv4i32_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfcvt.f.x.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv4i32_nxv4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.f.x.v v10, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv4i32_nxv4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFBFA-NEXT: vfcvt.f.x.v v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v10
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 4 x i32> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vuitofp_nxv4i32_nxv4bf16(<vscale x 4 x i32> %va) {
-; CHECK-LABEL: vuitofp_nxv4i32_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfcvt.f.xu.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv4i32_nxv4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.f.xu.v v10, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv4i32_nxv4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFBFA-NEXT: vfcvt.f.xu.v v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v10
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 4 x i32> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vsitofp_nxv8i32_nxv8bf16(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: vsitofp_nxv8i32_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfcvt.f.x.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv8i32_nxv8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.f.x.v v12, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv8i32_nxv8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFBFA-NEXT: vfcvt.f.x.v v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v12
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 8 x i32> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vuitofp_nxv8i32_nxv8bf16(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: vuitofp_nxv8i32_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfcvt.f.xu.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv8i32_nxv8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.f.xu.v v12, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv8i32_nxv8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFBFA-NEXT: vfcvt.f.xu.v v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v12
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 8 x i32> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 16 x bfloat> @vsitofp_nxv16i32_nxv16bf16(<vscale x 16 x i32> %va) {
-; CHECK-LABEL: vsitofp_nxv16i32_nxv16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.f.x.v v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv16i32_nxv16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.f.x.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv16i32_nxv16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; ZVFBFA-NEXT: vfcvt.f.x.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 16 x i32> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
}
define <vscale x 16 x bfloat> @vuitofp_nxv16i32_nxv16bf16(<vscale x 16 x i32> %va) {
-; CHECK-LABEL: vuitofp_nxv16i32_nxv16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.f.xu.v v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv16i32_nxv16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; ZVFBFMIN-NEXT: vfcvt.f.xu.v v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv16i32_nxv16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; ZVFBFA-NEXT: vfcvt.f.xu.v v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 16 x i32> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vsitofp_nxv1i64_nxv1bf16(<vscale x 1 x i64> %va) {
-; CHECK-LABEL: vsitofp_nxv1i64_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfncvt.f.x.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv1i64_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.f.x.w v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv1i64_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.x.w v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 1 x i64> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vuitofp_nxv1i64_nxv1bf16(<vscale x 1 x i64> %va) {
-; CHECK-LABEL: vuitofp_nxv1i64_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfncvt.f.xu.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv1i64_nxv1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.f.xu.w v9, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv1i64_nxv1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.xu.w v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 1 x i64> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vsitofp_nxv2i64_nxv2bf16(<vscale x 2 x i64> %va) {
-; CHECK-LABEL: vsitofp_nxv2i64_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfncvt.f.x.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv2i64_nxv2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.f.x.w v10, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv2i64_nxv2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.x.w v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v10
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 2 x i64> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vuitofp_nxv2i64_nxv2bf16(<vscale x 2 x i64> %va) {
-; CHECK-LABEL: vuitofp_nxv2i64_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfncvt.f.xu.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv2i64_nxv2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.f.xu.w v10, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv2i64_nxv2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.xu.w v10, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v10
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 2 x i64> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vsitofp_nxv4i64_nxv4bf16(<vscale x 4 x i64> %va) {
-; CHECK-LABEL: vsitofp_nxv4i64_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfncvt.f.x.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv4i64_nxv4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.f.x.w v12, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv4i64_nxv4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.x.w v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v12
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 4 x i64> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vuitofp_nxv4i64_nxv4bf16(<vscale x 4 x i64> %va) {
-; CHECK-LABEL: vuitofp_nxv4i64_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfncvt.f.xu.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv4i64_nxv4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.f.xu.w v12, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv4i64_nxv4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.xu.w v12, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v12
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 4 x i64> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vsitofp_nxv8i64_nxv8bf16(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: vsitofp_nxv8i64_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfncvt.f.x.w v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vsitofp_nxv8i64_nxv8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.f.x.w v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vsitofp_nxv8i64_nxv8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.x.w v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
+; ZVFBFA-NEXT: ret
%evec = sitofp <vscale x 8 x i64> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vuitofp_nxv8i64_nxv8bf16(<vscale x 8 x i64> %va) {
-; CHECK-LABEL: vuitofp_nxv8i64_nxv8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfncvt.f.xu.w v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
-; CHECK-NEXT: ret
+; ZVFBFMIN-LABEL: vuitofp_nxv8i64_nxv8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFBFMIN-NEXT: vfncvt.f.xu.w v16, v8
+; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v16
+; ZVFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: vuitofp_nxv8i64_nxv8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.xu.w v16, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
+; ZVFBFA-NEXT: ret
%evec = uitofp <vscale x 8 x i64> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
@@ -724,7 +1174,6 @@ define <vscale x 1 x half> @vsitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v9, v8, -1, v0
; ZVFH-NEXT: vfwcvt.f.x.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv1i1_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -745,7 +1194,6 @@ define <vscale x 1 x half> @vuitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v9, v8, 1, v0
; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv1i1_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -814,7 +1262,6 @@ define <vscale x 2 x half> @vsitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v9, v8, -1, v0
; ZVFH-NEXT: vfwcvt.f.x.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv2i1_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -835,7 +1282,6 @@ define <vscale x 2 x half> @vuitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v9, v8, 1, v0
; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv2i1_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -904,7 +1350,6 @@ define <vscale x 4 x half> @vsitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v9, v8, -1, v0
; ZVFH-NEXT: vfwcvt.f.x.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv4i1_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -925,7 +1370,6 @@ define <vscale x 4 x half> @vuitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v9, v8, 1, v0
; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv4i1_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -994,7 +1438,6 @@ define <vscale x 8 x half> @vsitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v10, v8, -1, v0
; ZVFH-NEXT: vfwcvt.f.x.v v8, v10
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv8i1_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1015,7 +1458,6 @@ define <vscale x 8 x half> @vuitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v10, v8, 1, v0
; ZVFH-NEXT: vfwcvt.f.xu.v v8, v10
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv8i1_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1084,7 +1526,6 @@ define <vscale x 16 x half> @vsitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v12, v8, -1, v0
; ZVFH-NEXT: vfwcvt.f.x.v v8, v12
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv16i1_nxv16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1105,7 +1546,6 @@ define <vscale x 16 x half> @vuitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v12, v8, 1, v0
; ZVFH-NEXT: vfwcvt.f.xu.v v8, v12
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv16i1_nxv16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1150,7 +1590,6 @@ define <vscale x 32 x half> @vsitofp_nxv32i1_nxv32f16(<vscale x 32 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v16, v8, -1, v0
; ZVFH-NEXT: vfwcvt.f.x.v v8, v16
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv32i1_nxv32f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1179,7 +1618,6 @@ define <vscale x 32 x half> @vuitofp_nxv32i1_nxv32f16(<vscale x 32 x i1> %va) {
; ZVFH-NEXT: vmerge.vim v16, v8, 1, v0
; ZVFH-NEXT: vfwcvt.f.xu.v v8, v16
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv32i1_nxv32f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1207,7 +1645,6 @@ define <vscale x 1 x half> @vsitofp_nxv1i8_nxv1f16(<vscale x 1 x i8> %va) {
; ZVFH-NEXT: vfwcvt.f.x.v v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv1i8_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -1227,7 +1664,6 @@ define <vscale x 1 x half> @vsitofp_nxv1i7_nxv1f16(<vscale x 1 x i7> %va) {
; ZVFH-NEXT: vsra.vi v9, v8, 1
; ZVFH-NEXT: vfwcvt.f.x.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv1i7_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
@@ -1250,7 +1686,6 @@ define <vscale x 1 x half> @vuitofp_nxv1i7_nxv1f16(<vscale x 1 x i7> %va) {
; ZVFH-NEXT: vand.vx v9, v8, a0
; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv1i7_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: li a0, 127
@@ -1272,7 +1707,6 @@ define <vscale x 1 x half> @vuitofp_nxv1i8_nxv1f16(<vscale x 1 x i8> %va) {
; ZVFH-NEXT: vfwcvt.f.xu.v v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv1i8_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -1335,7 +1769,6 @@ define <vscale x 2 x half> @vsitofp_nxv2i8_nxv2f16(<vscale x 2 x i8> %va) {
; ZVFH-NEXT: vfwcvt.f.x.v v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv2i8_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1354,7 +1787,6 @@ define <vscale x 2 x half> @vuitofp_nxv2i8_nxv2f16(<vscale x 2 x i8> %va) {
; ZVFH-NEXT: vfwcvt.f.xu.v v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv2i8_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1417,7 +1849,6 @@ define <vscale x 4 x half> @vsitofp_nxv4i8_nxv4f16(<vscale x 4 x i8> %va) {
; ZVFH-NEXT: vfwcvt.f.x.v v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv4i8_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1436,7 +1867,6 @@ define <vscale x 4 x half> @vuitofp_nxv4i8_nxv4f16(<vscale x 4 x i8> %va) {
; ZVFH-NEXT: vfwcvt.f.xu.v v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv4i8_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1499,7 +1929,6 @@ define <vscale x 8 x half> @vsitofp_nxv8i8_nxv8f16(<vscale x 8 x i8> %va) {
; ZVFH-NEXT: vmv1r.v v10, v8
; ZVFH-NEXT: vfwcvt.f.x.v v8, v10
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv8i8_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1518,7 +1947,6 @@ define <vscale x 8 x half> @vuitofp_nxv8i8_nxv8f16(<vscale x 8 x i8> %va) {
; ZVFH-NEXT: vmv1r.v v10, v8
; ZVFH-NEXT: vfwcvt.f.xu.v v8, v10
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv8i8_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1581,7 +2009,6 @@ define <vscale x 16 x half> @vsitofp_nxv16i8_nxv16f16(<vscale x 16 x i8> %va) {
; ZVFH-NEXT: vmv2r.v v12, v8
; ZVFH-NEXT: vfwcvt.f.x.v v8, v12
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv16i8_nxv16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1600,7 +2027,6 @@ define <vscale x 16 x half> @vuitofp_nxv16i8_nxv16f16(<vscale x 16 x i8> %va) {
; ZVFH-NEXT: vmv2r.v v12, v8
; ZVFH-NEXT: vfwcvt.f.xu.v v8, v12
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv16i8_nxv16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1641,7 +2067,6 @@ define <vscale x 32 x half> @vsitofp_nxv32i8_nxv32f16(<vscale x 32 x i8> %va) {
; ZVFH-NEXT: vmv4r.v v16, v8
; ZVFH-NEXT: vfwcvt.f.x.v v8, v16
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv32i8_nxv32f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1663,7 +2088,6 @@ define <vscale x 32 x half> @vuitofp_nxv32i8_nxv32f16(<vscale x 32 x i8> %va) {
; ZVFH-NEXT: vmv4r.v v16, v8
; ZVFH-NEXT: vfwcvt.f.xu.v v8, v16
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv32i8_nxv32f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -1684,7 +2108,6 @@ define <vscale x 1 x half> @vsitofp_nxv1i16_nxv1f16(<vscale x 1 x i16> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.f.x.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv1i16_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -1701,7 +2124,6 @@ define <vscale x 1 x half> @vuitofp_nxv1i16_nxv1f16(<vscale x 1 x i16> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.f.xu.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv1i16_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
@@ -1762,7 +2184,6 @@ define <vscale x 2 x half> @vsitofp_nxv2i16_nxv2f16(<vscale x 2 x i16> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.f.x.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv2i16_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1779,7 +2200,6 @@ define <vscale x 2 x half> @vuitofp_nxv2i16_nxv2f16(<vscale x 2 x i16> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.f.xu.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv2i16_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1840,7 +2260,6 @@ define <vscale x 4 x half> @vsitofp_nxv4i16_nxv4f16(<vscale x 4 x i16> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.f.x.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv4i16_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1857,7 +2276,6 @@ define <vscale x 4 x half> @vuitofp_nxv4i16_nxv4f16(<vscale x 4 x i16> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.f.xu.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv4i16_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1918,7 +2336,6 @@ define <vscale x 8 x half> @vsitofp_nxv8i16_nxv8f16(<vscale x 8 x i16> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT: vfcvt.f.x.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv8i16_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1935,7 +2352,6 @@ define <vscale x 8 x half> @vuitofp_nxv8i16_nxv8f16(<vscale x 8 x i16> %va) {
; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT: vfcvt.f.xu.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv8i16_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1996,7 +2412,6 @@ define <vscale x 16 x half> @vsitofp_nxv16i16_nxv16f16(<vscale x 16 x i16> %va)
; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFH-NEXT: vfcvt.f.x.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv16i16_nxv16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -2013,7 +2428,6 @@ define <vscale x 16 x half> @vuitofp_nxv16i16_nxv16f16(<vscale x 16 x i16> %va)
; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFH-NEXT: vfcvt.f.xu.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv16i16_nxv16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -2052,7 +2466,6 @@ define <vscale x 32 x half> @vsitofp_nxv32i16_nxv32f16(<vscale x 32 x i16> %va)
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT: vfcvt.f.x.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv32i16_nxv32f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -2071,7 +2484,6 @@ define <vscale x 32 x half> @vuitofp_nxv32i16_nxv32f16(<vscale x 32 x i16> %va)
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT: vfcvt.f.xu.v v8, v8
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv32i16_nxv32f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -2091,7 +2503,6 @@ define <vscale x 1 x half> @vsitofp_nxv1i32_nxv1f16(<vscale x 1 x i32> %va) {
; ZVFH-NEXT: vfncvt.f.x.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv1i32_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
@@ -2110,7 +2521,6 @@ define <vscale x 1 x half> @vuitofp_nxv1i32_nxv1f16(<vscale x 1 x i32> %va) {
; ZVFH-NEXT: vfncvt.f.xu.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv1i32_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
@@ -2171,7 +2581,6 @@ define <vscale x 2 x half> @vsitofp_nxv2i32_nxv2f16(<vscale x 2 x i32> %va) {
; ZVFH-NEXT: vfncvt.f.x.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv2i32_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma
@@ -2190,7 +2599,6 @@ define <vscale x 2 x half> @vuitofp_nxv2i32_nxv2f16(<vscale x 2 x i32> %va) {
; ZVFH-NEXT: vfncvt.f.xu.w v9, v8
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv2i32_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma
@@ -2251,7 +2659,6 @@ define <vscale x 4 x half> @vsitofp_nxv4i32_nxv4f16(<vscale x 4 x i32> %va) {
; ZVFH-NEXT: vfncvt.f.x.w v10, v8
; ZVFH-NEXT: vmv.v.v v8, v10
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv4i32_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
@@ -2270,7 +2677,6 @@ define <vscale x 4 x half> @vuitofp_nxv4i32_nxv4f16(<vscale x 4 x i32> %va) {
; ZVFH-NEXT: vfncvt.f.xu.w v10, v8
; ZVFH-NEXT: vmv.v.v v8, v10
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv4i32_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
@@ -2331,7 +2737,6 @@ define <vscale x 8 x half> @vsitofp_nxv8i32_nxv8f16(<vscale x 8 x i32> %va) {
; ZVFH-NEXT: vfncvt.f.x.w v12, v8
; ZVFH-NEXT: vmv.v.v v8, v12
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv8i32_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
@@ -2350,7 +2755,6 @@ define <vscale x 8 x half> @vuitofp_nxv8i32_nxv8f16(<vscale x 8 x i32> %va) {
; ZVFH-NEXT: vfncvt.f.xu.w v12, v8
; ZVFH-NEXT: vmv.v.v v8, v12
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv8i32_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
@@ -2411,7 +2815,6 @@ define <vscale x 16 x half> @vsitofp_nxv16i32_nxv16f16(<vscale x 16 x i32> %va)
; ZVFH-NEXT: vfncvt.f.x.w v16, v8
; ZVFH-NEXT: vmv.v.v v8, v16
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vsitofp_nxv16i32_nxv16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma
@@ -2430,7 +2833,6 @@ define <vscale x 16 x half> @vuitofp_nxv16i32_nxv16f16(<vscale x 16 x i32> %va)
; ZVFH-NEXT: vfncvt.f.xu.w v16, v8
; ZVFH-NEXT: vmv.v.v v8, v16
; ZVFH-NEXT: ret
-;
; ZVFHMIN-LABEL: vuitofp_nxv16i32_nxv16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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