[llvm] 7f52105 - AMDGPU/GlobalISel: RegBankLegalize rules for G_INSERT_VECTOR_ELT (#191296)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 15 09:13:37 PDT 2026
Author: vangthao95
Date: 2026-04-15T09:13:31-07:00
New Revision: 7f521050d2c4141200b5f7cd75f81db99d26bcad
URL: https://github.com/llvm/llvm-project/commit/7f521050d2c4141200b5f7cd75f81db99d26bcad
DIFF: https://github.com/llvm/llvm-project/commit/7f521050d2c4141200b5f7cd75f81db99d26bcad.diff
LOG: AMDGPU/GlobalISel: RegBankLegalize rules for G_INSERT_VECTOR_ELT (#191296)
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 7183a38545fdf..7294166f5792d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -979,6 +979,110 @@ bool RegBankLegalizeHelper::lowerExtrVecEltTo32(MachineInstr &MI) {
return true;
}
+bool RegBankLegalizeHelper::lowerInsVecEltToSel(MachineInstr &MI) {
+ // Lower insert vector element to a compare-select chain:
+ // for i in 0..N-1:
+ // result[i] = (idx == i) ? elt : srcVec[i]
+ // dst = merge(result[0..N-1])
+ //
+ // VGPR B64 requires splitting to lo/hi s32 pairs since there is no
+ // v_cndmask_b64. SGPR B64/B32 and VGPR B32 can be handled natively.
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ Register Elt = MI.getOperand(2).getReg();
+ Register Idx = MI.getOperand(3).getReg();
+
+ LLT VecTy = MRI.getType(Src);
+ LLT ScalarTy = VecTy.getScalarType();
+ unsigned NumElts = VecTy.getNumElements();
+ const RegisterBank *SrcRB = MRI.getRegBank(Src);
+ bool IsSGPR = (SrcRB == SgprRB);
+ SmallVector<Register, 16> Selects;
+
+ if (!IsSGPR && ScalarTy.getSizeInBits() == 64) {
+ // VGPR B64: split to 32-bit lo/hi since there is no v_cndmask_b64.
+ auto Unmerge = B.buildUnmerge(VgprRB_S32, Src);
+ auto EltUnmerge = B.buildUnmerge(VgprRB_S32, Elt);
+ Register EltLo = EltUnmerge.getReg(0);
+ Register EltHi = EltUnmerge.getReg(1);
+ for (unsigned I = 0; I < NumElts; ++I) {
+ auto IdxConst = B.buildConstant(VgprRB_S32, I);
+ auto Cmp = B.buildICmp(CmpInst::ICMP_EQ, VccRB_S1, Idx, IdxConst);
+ Selects.push_back(
+ B.buildSelect(VgprRB_S32, Cmp, EltLo, Unmerge.getReg(2 * I))
+ .getReg(0));
+ Selects.push_back(
+ B.buildSelect(VgprRB_S32, Cmp, EltHi, Unmerge.getReg(2 * I + 1))
+ .getReg(0));
+ }
+ LLT Vec32Ty = LLT::fixed_vector(2 * NumElts, 32);
+ auto Vec32 = B.buildBuildVector({VgprRB, Vec32Ty}, Selects);
+ B.buildBitcast(Dst, Vec32);
+ } else if (ScalarTy.getSizeInBits() == 32 || ScalarTy.getSizeInBits() == 64) {
+ // B32 (any bank) and SGPR B64: element-wise select at native width.
+ MachineRegisterInfo::VRegAttrs SrcRB_EltTy = {SrcRB, ScalarTy};
+ MachineRegisterInfo::VRegAttrs CmpTy = IsSGPR ? SgprRB_S32 : VccRB_S1;
+ auto Unmerge = B.buildUnmerge(SrcRB_EltTy, Src);
+ for (unsigned I = 0; I < NumElts; ++I) {
+ auto IdxConst = B.buildConstant(SgprRB_S32, I);
+ auto Cmp = B.buildICmp(CmpInst::ICMP_EQ, CmpTy, Idx, IdxConst);
+ Selects.push_back(
+ B.buildSelect(SrcRB_EltTy, Cmp, Elt, Unmerge.getReg(I)).getReg(0));
+ }
+ B.buildMergeLikeInstr(Dst, Selects);
+ } else {
+ reportGISelFailure(
+ MF, MORE, "amdgpu-regbanklegalize",
+ "AMDGPU RegBankLegalize: InsVecEltToSel unsupported element type", MI);
+ return false;
+ }
+
+ MI.eraseFromParent();
+ return true;
+}
+
+bool RegBankLegalizeHelper::lowerInsVecEltTo32(MachineInstr &MI) {
+ // Reduce a 64-bit element insert to two 32-bit inserts:
+ // vec32 = bitcast <N x s64> to <2N x s32>
+ // lo, hi = unmerge elt
+ // vec32[idx * 2] = lo
+ // vec32[idx * 2 + 1] = hi
+ // dst = bitcast <2N x s32> to <N x s64>
+ //
+ // When the index is uniform, all lanes insert at the same position, so we
+ // can split the s64 insert into two s32 inserts which lower to MOVREL/GPRIDX.
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ Register Elt = MI.getOperand(2).getReg();
+ Register Idx = MI.getOperand(3).getReg();
+
+ LLT SrcTy = MRI.getType(Src);
+ LLT Vec32Ty = LLT::fixed_vector(2 * SrcTy.getNumElements(), 32);
+
+ assert(MRI.getRegBank(Src) == VgprRB && MRI.getRegBank(Idx) == SgprRB &&
+ "expected VGPR src and SGPR idx");
+
+ MachineRegisterInfo::VRegAttrs VgprRB_Vec32Ty = {VgprRB, Vec32Ty};
+
+ auto CastSrc = B.buildBitcast(VgprRB_Vec32Ty, Src);
+ auto EltUnmerge = B.buildUnmerge(VgprRB_S32, Elt);
+
+ // Calculate new Lo and Hi indices
+ auto One = B.buildConstant(SgprRB_S32, 1);
+ auto IdxLo = B.buildShl(SgprRB_S32, Idx, One);
+ auto IdxHi = B.buildAdd(SgprRB_S32, IdxLo, One);
+
+ auto InsLo = B.buildInsertVectorElement(VgprRB_Vec32Ty, CastSrc,
+ EltUnmerge.getReg(0), IdxLo);
+ auto InsHi = B.buildInsertVectorElement(VgprRB_Vec32Ty, InsLo,
+ EltUnmerge.getReg(1), IdxHi);
+
+ B.buildBitcast(Dst, InsHi);
+
+ MI.eraseFromParent();
+ return true;
+}
+
bool RegBankLegalizeHelper::lower(MachineInstr &MI,
const RegBankLLTMapping &Mapping,
WaterfallInfo &WFI) {
@@ -1257,6 +1361,10 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
return lowerExtrVecEltToSel(MI);
case ExtrVecEltTo32:
return lowerExtrVecEltTo32(MI);
+ case InsVecEltToSel:
+ return lowerInsVecEltToSel(MI);
+ case InsVecEltTo32:
+ return lowerInsVecEltTo32(MI);
}
if (!WFI.SgprWaterfallOperandRegs.empty()) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
index 8c39ad3238b18..57df192832dc6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
@@ -142,6 +142,8 @@ class RegBankLegalizeHelper {
bool lowerUnpackAExt(MachineInstr &MI);
bool lowerExtrVecEltToSel(MachineInstr &MI);
bool lowerExtrVecEltTo32(MachineInstr &MI);
+ bool lowerInsVecEltToSel(MachineInstr &MI);
+ bool lowerInsVecEltTo32(MachineInstr &MI);
bool applyRegisterBanksINTRIN_IMAGE(MachineInstr &MI);
};
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index b2801ce45cf34..531349ae45aad 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -689,6 +689,20 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{DivB64, BRC, DivS32},
{{VgprB64}, {VgprBRC, Vgpr32}, ExtrVecEltToSel}});
+ addRulesForGOpcs({G_INSERT_VECTOR_ELT})
+ .Any({{UniBRC, UniBRC, UniB32, UniS32},
+ {{SgprBRC}, {SgprBRC, SgprB32, Sgpr32}}})
+ .Any(
+ {{DivBRC, BRC, B32, UniS32}, {{VgprBRC}, {VgprBRC, VgprB32, Sgpr32}}})
+ .Any({{DivBRC, BRC, B32, DivS32},
+ {{VgprBRC}, {VgprBRC, VgprB32, Vgpr32}, InsVecEltToSel}})
+ .Any({{UniBRC, UniBRC, UniB64, UniS32},
+ {{SgprBRC}, {SgprBRC, SgprB64, Sgpr32}, InsVecEltToSel}})
+ .Any({{DivBRC, BRC, B64, UniS32},
+ {{VgprBRC}, {VgprBRC, VgprB64, Sgpr32}, InsVecEltTo32}})
+ .Any({{DivBRC, BRC, B64, DivS32},
+ {{VgprBRC}, {VgprBRC, VgprB64, Vgpr32}, InsVecEltToSel}});
+
// LOAD {Div}, {{VgprDst...}, {VgprSrc, ..., Sgpr_WF_RsrcIdx}}
// LOAD {Uni}, {{UniInVgprDst...}, {VgprSrc, ..., Sgpr_WF_RsrcIdx}}
// LOAD_NORET {}, {{}, {Imm, VgprSrc, ..., Sgpr_WF_RsrcIdx}}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index c2501faa2cf2c..be9d472f29be4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -293,7 +293,9 @@ enum LoweringMethodID {
ApplyINTRIN_IMAGE,
SplitBitCount64To32,
ExtrVecEltToSel,
- ExtrVecEltTo32
+ ExtrVecEltTo32,
+ InsVecEltToSel,
+ InsVecEltTo32
};
enum FastRulesTypes {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
index bc50852fb7918..103fefb26529b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
define amdgpu_ps void @insertelement_s_v2i16_s_s(ptr addrspace(4) inreg %ptr, i16 inreg %val, i32 inreg %idx) {
; GFX9-LABEL: insertelement_s_v2i16_s_s:
@@ -783,44 +783,42 @@ define amdgpu_ps void @insertelement_v_v4i16_s_s(ptr addrspace(1) %ptr, i16 inre
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_and_b32 s1, s3, 1
-; GFX9-NEXT: s_lshr_b32 s0, s3, 1
; GFX9-NEXT: s_and_b32 s2, s2, 0xffff
; GFX9-NEXT: s_lshl_b32 s1, s1, 4
+; GFX9-NEXT: s_lshr_b32 s0, s3, 1
; GFX9-NEXT: s_lshl_b32 s2, s2, s1
; GFX9-NEXT: s_lshl_b32 s1, 0xffff, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
; GFX9-NEXT: s_not_b32 s1, s1
-; GFX9-NEXT: v_mov_b32_e32 v4, s2
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
+; GFX9-NEXT: v_mov_b32_e32 v3, v0
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_or_b32 v4, v3, s1, v2
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
-; GFX9-NEXT: v_and_or_b32 v4, v5, s1, v4
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v4i16_s_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX8-NEXT: s_lshr_b32 s0, s3, 1
-; GFX8-NEXT: s_and_b32 s1, s3, 1
-; GFX8-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX8-NEXT: s_lshl_b32 s1, s1, 4
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
-; GFX8-NEXT: s_lshl_b32 s2, s2, s1
-; GFX8-NEXT: s_lshl_b32 s1, 0xffff, s1
-; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: s_and_b32 s0, s3, 1
+; GFX8-NEXT: s_lshr_b32 m0, s3, 1
+; GFX8-NEXT: s_and_b32 s1, s2, 0xffff
+; GFX8-NEXT: s_lshl_b32 s0, s0, 4
+; GFX8-NEXT: s_lshl_b32 s1, s1, s0
+; GFX8-NEXT: s_lshl_b32 s0, 0xffff, s0
; GFX8-NEXT: v_mov_b32_e32 v3, 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
-; GFX8-NEXT: v_bfi_b32 v4, s1, 0, v4
-; GFX8-NEXT: v_or_b32_e32 v4, s2, v4
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX8-NEXT: v_movrels_b32_e32 v2, v0
+; GFX8-NEXT: v_bfi_b32 v2, s0, 0, v2
+; GFX8-NEXT: v_or_b32_e32 v4, s1, v2
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: v_movreld_b32_e32 v0, v4
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
;
@@ -830,65 +828,58 @@ define amdgpu_ps void @insertelement_v_v4i16_s_s(ptr addrspace(1) %ptr, i16 inre
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_lshr_b32 s0, s3, 1
-; GFX7-NEXT: s_and_b32 s1, s3, 1
-; GFX7-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX7-NEXT: s_lshl_b32 s1, s1, 4
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
-; GFX7-NEXT: s_lshl_b32 s2, s2, s1
-; GFX7-NEXT: s_lshl_b32 s1, 0xffff, s1
+; GFX7-NEXT: s_and_b32 s0, s3, 1
+; GFX7-NEXT: s_lshr_b32 m0, s3, 1
+; GFX7-NEXT: s_and_b32 s1, s2, 0xffff
+; GFX7-NEXT: s_lshl_b32 s0, s0, 4
+; GFX7-NEXT: s_lshl_b32 s1, s1, s0
+; GFX7-NEXT: s_lshl_b32 s0, 0xffff, s0
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
-; GFX7-NEXT: v_bfi_b32 v2, s1, 0, v2
-; GFX7-NEXT: v_or_b32_e32 v2, s2, v2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_movrels_b32_e32 v2, v0
+; GFX7-NEXT: v_bfi_b32 v2, s0, 0, v2
+; GFX7-NEXT: v_or_b32_e32 v2, s1, v2
+; GFX7-NEXT: v_movreld_b32_e32 v0, v2
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_v_v4i16_s_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
-; GFX10-NEXT: s_lshr_b32 s0, s3, 1
-; GFX10-NEXT: s_and_b32 s1, s3, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1
-; GFX10-NEXT: s_lshl_b32 s1, s1, 4
-; GFX10-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX10-NEXT: s_lshl_b32 s3, 0xffff, s1
-; GFX10-NEXT: s_lshl_b32 s1, s2, s1
-; GFX10-NEXT: s_not_b32 s2, s3
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s0, 0
+; GFX10-NEXT: s_and_b32 s0, s3, 1
+; GFX10-NEXT: s_lshr_b32 m0, s3, 1
+; GFX10-NEXT: s_lshl_b32 s0, s0, 4
+; GFX10-NEXT: s_and_b32 s1, s2, 0xffff
+; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s0
+; GFX10-NEXT: s_lshl_b32 s0, s1, s0
+; GFX10-NEXT: s_not_b32 s1, s2
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc_lo
-; GFX10-NEXT: v_and_or_b32 v4, v2, s2, s1
+; GFX10-NEXT: v_movrels_b32_e32 v2, v0
+; GFX10-NEXT: v_and_or_b32 v4, v2, s1, s0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX10-NEXT: v_movreld_b32_e32 v0, v4
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_v_v4i16_s_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT: s_lshr_b32 s0, s3, 1
-; GFX11-NEXT: s_and_b32 s1, s3, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1
-; GFX11-NEXT: s_lshl_b32 s1, s1, 4
-; GFX11-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX11-NEXT: s_lshl_b32 s3, 0xffff, s1
-; GFX11-NEXT: s_lshl_b32 s1, s2, s1
-; GFX11-NEXT: s_not_b32 s2, s3
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s0, 0
+; GFX11-NEXT: s_and_b32 s0, s3, 1
+; GFX11-NEXT: s_lshr_b32 m0, s3, 1
+; GFX11-NEXT: s_lshl_b32 s0, s0, 4
+; GFX11-NEXT: s_and_b32 s1, s2, 0xffff
+; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s0
+; GFX11-NEXT: s_lshl_b32 s0, s1, s0
+; GFX11-NEXT: s_not_b32 s1, s2
+; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v2, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_and_or_b32 v4, v2, s2, s1
-; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v1, v4
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
+; GFX11-NEXT: v_movrels_b32_e32 v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_or_b32 v4, v2, s1, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: v_movreld_b32_e32 v0, v4
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-NEXT: s_endpgm
%vec = load <4 x i16>, ptr addrspace(1 ) %ptr
@@ -902,123 +893,106 @@ define amdgpu_ps void @insertelement_s_v4i16_v_s(ptr addrspace(4) inreg %ptr, i1
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX9-NEXT: s_lshr_b32 s2, s4, 1
-; GFX9-NEXT: s_cmp_eq_u32 s2, 1
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_cselect_b32 s3, s1, s0
; GFX9-NEXT: s_and_b32 s4, s4, 1
+; GFX9-NEXT: s_mov_b32 m0, s2
; GFX9-NEXT: s_lshl_b32 s4, s4, 4
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_movrels_b32 s3, s0
; GFX9-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX9-NEXT: s_andn2_b32 s3, s3, s5
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_lshl_or_b32 v4, v0, s4, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v4i16_v_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX8-NEXT: s_lshr_b32 s2, s4, 1
-; GFX8-NEXT: s_cmp_eq_u32 s2, 1
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: s_and_b32 s3, s4, 1
+; GFX8-NEXT: s_lshr_b32 m0, s4, 1
+; GFX8-NEXT: s_lshl_b32 s3, s3, 4
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_cselect_b32 s3, s1, s0
-; GFX8-NEXT: s_and_b32 s4, s4, 1
-; GFX8-NEXT: s_lshl_b32 s4, s4, 4
-; GFX8-NEXT: v_mov_b32_e32 v1, s4
-; GFX8-NEXT: s_lshl_b32 s4, 0xffff, s4
+; GFX8-NEXT: s_movrels_b32 s2, s0
+; GFX8-NEXT: s_lshl_b32 s3, 0xffff, s3
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT: s_andn2_b32 s3, s3, s4
-; GFX8-NEXT: v_or_b32_e32 v4, s3, v0
+; GFX8-NEXT: s_andn2_b32 s2, s2, s3
+; GFX8-NEXT: v_or_b32_e32 v4, s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: v_mov_b32_e32 v3, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX8-NEXT: v_movreld_b32_e32 v0, v4
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v4i16_v_s:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX7-NEXT: s_lshr_b32 s2, s4, 1
-; GFX7-NEXT: s_cmp_eq_u32 s2, 1
+; GFX7-NEXT: s_and_b32 s3, s4, 1
+; GFX7-NEXT: s_lshr_b32 m0, s4, 1
+; GFX7-NEXT: s_lshl_b32 s3, s3, 4
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_cselect_b32 s3, s1, s0
-; GFX7-NEXT: s_and_b32 s4, s4, 1
-; GFX7-NEXT: s_lshl_b32 s4, s4, 4
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX7-NEXT: s_lshl_b32 s4, 0xffff, s4
-; GFX7-NEXT: s_andn2_b32 s3, s3, s4
-; GFX7-NEXT: v_or_b32_e32 v2, s3, v0
+; GFX7-NEXT: s_movrels_b32 s2, s0
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, s3, v0
+; GFX7-NEXT: s_lshl_b32 s3, 0xffff, s3
+; GFX7-NEXT: s_andn2_b32 s2, s2, s3
+; GFX7-NEXT: v_or_b32_e32 v2, s2, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: v_movreld_b32_e32 v0, v2
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_s_v4i16_v_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX10-NEXT: s_lshr_b32 s2, s4, 1
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX10-NEXT: s_cmp_eq_u32 s2, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
+; GFX10-NEXT: s_and_b32 s2, s4, 1
+; GFX10-NEXT: s_lshr_b32 m0, s4, 1
+; GFX10-NEXT: s_lshl_b32 s2, s2, 4
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: s_lshl_b32 s3, 0xffff, s2
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_cselect_b32 s3, s1, s0
-; GFX10-NEXT: s_and_b32 s4, s4, 1
+; GFX10-NEXT: s_movrels_b32 s4, s0
+; GFX10-NEXT: s_andn2_b32 s3, s4, s3
+; GFX10-NEXT: v_lshl_or_b32 v4, v0, s2, s3
; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: s_lshl_b32 s4, s4, 4
; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: s_lshl_b32 s5, 0xffff, s4
-; GFX10-NEXT: s_andn2_b32 s3, s3, s5
-; GFX10-NEXT: v_lshl_or_b32 v4, v2, s4, s3
-; GFX10-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX10-NEXT: v_movreld_b32_e32 v0, v4
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v4i16_v_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
-; GFX11-NEXT: s_lshr_b32 s2, s4, 1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX11-NEXT: s_cmp_eq_u32 s2, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
+; GFX11-NEXT: s_and_b32 s2, s4, 1
+; GFX11-NEXT: s_lshr_b32 m0, s4, 1
+; GFX11-NEXT: s_lshl_b32 s2, s2, 4
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: s_lshl_b32 s3, 0xffff, s2
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s0
-; GFX11-NEXT: s_cselect_b32 s3, s1, s0
-; GFX11-NEXT: s_and_b32 s4, s4, 1
-; GFX11-NEXT: v_mov_b32_e32 v1, s1
-; GFX11-NEXT: s_lshl_b32 s4, s4, 4
+; GFX11-NEXT: s_movrels_b32 s4, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b32 s5, 0xffff, s4
-; GFX11-NEXT: s_and_not1_b32 s3, s3, s5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v4, v2, s4, s3
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v1, v4
+; GFX11-NEXT: s_and_not1_b32 s3, s4, s3
+; GFX11-NEXT: v_lshl_or_b32 v4, v0, s2, s3
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_movreld_b32_e32 v0, v4
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-NEXT: s_endpgm
%vec = load <4 x i16>, ptr addrspace(4) %ptr
@@ -1031,78 +1005,72 @@ define amdgpu_ps void @insertelement_s_v4i16_s_v(ptr addrspace(4) inreg %ptr, i1
; GFX9-LABEL: insertelement_s_v4i16_s_v:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v0
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX9-NEXT: v_mov_b32_e32 v6, 0xffff
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v1, s0
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
-; GFX9-NEXT: s_and_b32 s2, s4, 0xffff
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_lshlrev_b32_e64 v3, v0, s2
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v4
+; GFX9-NEXT: s_and_b32 s0, s4, 0xffff
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX9-NEXT: v_lshlrev_b32_e64 v5, v0, s0
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_and_or_b32 v4, v1, v0, v3
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_and_or_b32 v5, v4, v0, v5
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v5, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
+; GFX9-NEXT: global_store_dwordx2 v[3:4], v[0:1], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v4i16_s_v:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_mov_b32_e32 v1, s0
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
-; GFX8-NEXT: s_and_b32 s2, s4, 0xffff
-; GFX8-NEXT: v_mov_b32_e32 v4, 0xffff
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX8-NEXT: v_lshlrev_b32_e64 v3, v0, s2
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v4
-; GFX8-NEXT: v_bfi_b32 v0, v0, 0, v1
-; GFX8-NEXT: v_or_b32_e32 v4, v0, v3
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: s_and_b32 s0, s4, 0xffff
+; GFX8-NEXT: v_mov_b32_e32 v6, 0xffff
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
+; GFX8-NEXT: v_lshlrev_b32_e64 v5, v0, s0
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v6
+; GFX8-NEXT: v_bfi_b32 v0, v0, 0, v4
+; GFX8-NEXT: v_or_b32_e32 v5, v0, v5
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, v5, s[0:1]
; GFX8-NEXT: v_mov_b32_e32 v3, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
+; GFX8-NEXT: flat_store_dwordx2 v[3:4], v[0:1]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v4i16_s_v:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 1, v0
; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
-; GFX7-NEXT: s_and_b32 s2, s4, 0xffff
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX7-NEXT: v_lshl_b32_e32 v3, s2, v0
+; GFX7-NEXT: s_and_b32 s0, s4, 0xffff
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
+; GFX7-NEXT: v_lshl_b32_e32 v5, s0, v0
; GFX7-NEXT: v_lshl_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_bfi_b32 v0, v0, 0, v1
-; GFX7-NEXT: v_or_b32_e32 v3, v0, v3
-; GFX7-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX7-NEXT: v_bfi_b32 v0, v0, 0, v4
+; GFX7-NEXT: v_or_b32_e32 v4, v0, v5
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v1, v4, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
@@ -1115,18 +1083,17 @@ define amdgpu_ps void @insertelement_s_v4i16_s_v(ptr addrspace(4) inreg %ptr, i1
; GFX10-NEXT: v_and_b32_e32 v1, 1, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 1, v0
; GFX10-NEXT: s_and_b32 s2, s4, 0xffff
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xffff
-; GFX10-NEXT: v_lshlrev_b32_e64 v3, v1, s2
-; GFX10-NEXT: v_not_b32_e32 v2, v2
+; GFX10-NEXT: v_lshlrev_b32_e64 v3, v2, 0xffff
+; GFX10-NEXT: v_lshlrev_b32_e64 v2, v2, s2
+; GFX10-NEXT: v_not_b32_e32 v3, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v0, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v5, s0, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
-; GFX10-NEXT: v_and_or_b32 v5, v5, v2, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
+; GFX10-NEXT: v_and_or_b32 v5, v5, v3, v2
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
@@ -1140,20 +1107,21 @@ define amdgpu_ps void @insertelement_s_v4i16_s_v(ptr addrspace(4) inreg %ptr, i1
; GFX11-NEXT: v_and_b32_e32 v1, 1, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 1, v0
; GFX11-NEXT: s_and_b32 s2, s4, 0xffff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_lshlrev_b32 v1, 4, v1
-; GFX11-NEXT: v_cndmask_b32_e32 v5, s0, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b32_e64 v2, v1, 0xffff
-; GFX11-NEXT: v_lshlrev_b32_e64 v3, v1, s2
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b32_e64 v3, v2, 0xffff
+; GFX11-NEXT: v_lshlrev_b32_e64 v2, v2, s2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
-; GFX11-NEXT: v_not_b32_e32 v2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v5, v5, v2, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_not_b32_e32 v3, v3
+; GFX11-NEXT: v_and_or_b32 v5, v5, v3, v2
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
@@ -1168,76 +1136,70 @@ define amdgpu_ps void @insertelement_s_v4i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX9-LABEL: insertelement_s_v4i16_v_v:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v1
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 1, v1
; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v1
+; GFX9-NEXT: v_mov_b32_e32 v6, 0xffff
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v3, s0
-; GFX9-NEXT: v_mov_b32_e32 v4, s1
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v2, v3, vcc
; GFX9-NEXT: v_not_b32_e32 v1, v1
-; GFX9-NEXT: v_and_or_b32 v4, v3, v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
+; GFX9-NEXT: v_and_or_b32 v1, v5, v1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9-NEXT: global_store_dwordx2 v[4:5], v[0:1], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v4i16_v_v:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v1
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 1, v1
; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s0
-; GFX8-NEXT: v_mov_b32_e32 v4, s1
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX8-NEXT: v_mov_b32_e32 v4, 0xffff
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v6, 0xffff
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v2, v3, vcc
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v4
-; GFX8-NEXT: v_bfi_b32 v1, v1, 0, v3
-; GFX8-NEXT: v_or_b32_e32 v4, v1, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v2, 0
-; GFX8-NEXT: v_mov_b32_e32 v3, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v6
+; GFX8-NEXT: v_bfi_b32 v1, v1, 0, v5
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX8-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v4i16_v_v:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 1, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 1, v1
; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v3, s0
-; GFX7-NEXT: v_mov_b32_e32 v4, s1
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v2, v3, vcc
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
-; GFX7-NEXT: v_bfi_b32 v1, v1, 0, v3
-; GFX7-NEXT: v_or_b32_e32 v3, v1, v0
-; GFX7-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX7-NEXT: v_bfi_b32 v1, v1, 0, v5
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
@@ -1248,48 +1210,47 @@ define amdgpu_ps void @insertelement_s_v4i16_v_v(ptr addrspace(4) inreg %ptr, i1
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX10-NEXT: v_and_b32_e32 v2, 1, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v4, 1, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v2
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX10-NEXT: v_lshlrev_b32_e64 v3, v2, 0xffff
-; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX10-NEXT: v_not_b32_e32 v3, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v5, 1, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 4, v2
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX10-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff
+; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX10-NEXT: v_not_b32_e32 v3, v4
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v5, s0, v1, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
-; GFX10-NEXT: v_and_or_b32 v5, v5, v3, v2
-; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_mov_b32_e32 v2, s1
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc_lo
+; GFX10-NEXT: v_and_or_b32 v6, v4, v3, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
-; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, v6, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo
+; GFX10-NEXT: global_store_dwordx2 v[3:4], v[0:1], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v4i16_v_v:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX11-NEXT: v_and_b32_e32 v2, 1, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v4, 1, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v2, 4, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v5, s0, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b32_e64 v3, v2, 0xffff
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, v2, v0
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
-; GFX11-NEXT: v_not_b32_e32 v3, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v5, v5, v3, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v5
+; GFX11-NEXT: v_lshlrev_b32_e64 v4, v2, 0xffff
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, v2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_not_b32_e32 v3, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo
+; GFX11-NEXT: v_and_or_b32 v4, v4, v3, v2
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-NEXT: s_endpgm
%vec = load <4 x i16>, ptr addrspace(4) %ptr
@@ -1426,43 +1387,41 @@ define amdgpu_ps void @insertelement_v_v4i16_v_s(ptr addrspace(1) %ptr, i16 %val
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_and_b32 s1, s2, 1
-; GFX9-NEXT: s_lshr_b32 s0, s2, 1
; GFX9-NEXT: s_lshl_b32 s1, s1, 4
+; GFX9-NEXT: s_lshr_b32 s0, s2, 1
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_lshl_b32 s1, 0xffff, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
; GFX9-NEXT: s_not_b32 s1, s1
-; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
-; GFX9-NEXT: v_and_or_b32 v2, v5, s1, v2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: global_store_dwordx2 v[3:4], v[0:1], off
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
+; GFX9-NEXT: v_mov_b32_e32 v3, v0
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_or_b32 v4, v3, s1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v4i16_v_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX8-NEXT: s_and_b32 s1, s2, 1
-; GFX8-NEXT: s_lshr_b32 s0, s2, 1
-; GFX8-NEXT: s_lshl_b32 s1, s1, 4
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
-; GFX8-NEXT: s_lshl_b32 s1, 0xffff, s1
-; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT: v_mov_b32_e32 v3, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: s_and_b32 s0, s2, 1
+; GFX8-NEXT: s_lshl_b32 s0, s0, 4
+; GFX8-NEXT: s_lshr_b32 m0, s2, 1
+; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: s_lshl_b32 s0, 0xffff, s0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
-; GFX8-NEXT: v_bfi_b32 v5, s1, 0, v5
-; GFX8-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: flat_store_dwordx2 v[3:4], v[0:1]
+; GFX8-NEXT: v_movrels_b32_e32 v3, v0
+; GFX8-NEXT: v_bfi_b32 v3, s0, 0, v3
+; GFX8-NEXT: v_or_b32_e32 v4, v3, v2
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: v_mov_b32_e32 v3, 0
+; GFX8-NEXT: v_movreld_b32_e32 v0, v4
+; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_v_v4i16_v_s:
@@ -1471,66 +1430,58 @@ define amdgpu_ps void @insertelement_v_v4i16_v_s(ptr addrspace(1) %ptr, i16 %val
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_lshr_b32 s0, s2, 1
-; GFX7-NEXT: s_and_b32 s1, s2, 1
+; GFX7-NEXT: s_and_b32 s0, s2, 1
+; GFX7-NEXT: s_lshr_b32 m0, s2, 1
; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX7-NEXT: s_lshl_b32 s1, s1, 4
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, s1, v2
-; GFX7-NEXT: s_lshl_b32 s1, 0xffff, s1
+; GFX7-NEXT: s_lshl_b32 s0, s0, 4
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, s0, v2
+; GFX7-NEXT: s_lshl_b32 s0, 0xffff, s0
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
-; GFX7-NEXT: v_bfi_b32 v3, s1, 0, v3
+; GFX7-NEXT: v_movrels_b32_e32 v3, v0
+; GFX7-NEXT: v_bfi_b32 v3, s0, 0, v3
; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_movreld_b32_e32 v0, v2
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_v_v4i16_v_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
-; GFX10-NEXT: s_lshr_b32 s1, s2, 1
; GFX10-NEXT: s_and_b32 s0, s2, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s1, 1
+; GFX10-NEXT: s_lshr_b32 m0, s2, 1
; GFX10-NEXT: s_lshl_b32 s0, s0, 4
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_lshl_b32 s0, 0xffff, s0
; GFX10-NEXT: s_not_b32 s0, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc_lo
+; GFX10-NEXT: v_movrels_b32_e32 v3, v0
; GFX10-NEXT: v_and_or_b32 v4, v3, s0, v2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
+; GFX10-NEXT: v_movreld_b32_e32 v0, v4
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_v_v4i16_v_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT: s_lshr_b32 s1, s2, 1
-; GFX11-NEXT: s_and_b32 s0, s2, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s1, 1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: s_and_b32 s0, s2, 1
+; GFX11-NEXT: s_lshr_b32 m0, s2, 1
; GFX11-NEXT: s_lshl_b32 s0, s0, 4
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v3, v0, v1 :: v_dual_lshlrev_b32 v2, s0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, s0, v2
; GFX11-NEXT: s_lshl_b32 s0, 0xffff, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_not_b32 s0, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_movrels_b32_e32 v3, v0
; GFX11-NEXT: v_and_or_b32 v4, v3, s0, v2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s1, 0
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_movreld_b32_e32 v0, v4
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-NEXT: s_endpgm
%vec = load <4 x i16>, ptr addrspace(1) %ptr
@@ -1664,32 +1615,20 @@ define amdgpu_ps void @insertelement_s_v8i16_s_s(ptr addrspace(4) inreg %ptr, i1
; GFX9-LABEL: insertelement_s_v8i16_s_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX9-NEXT: s_lshr_b32 s6, s5, 1
-; GFX9-NEXT: s_cmp_eq_u32 s6, 1
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_cselect_b32 s7, s1, s0
-; GFX9-NEXT: s_cmp_eq_u32 s6, 2
-; GFX9-NEXT: s_cselect_b32 s7, s2, s7
-; GFX9-NEXT: s_cmp_eq_u32 s6, 3
-; GFX9-NEXT: s_cselect_b32 s7, s3, s7
+; GFX9-NEXT: s_lshr_b32 m0, s5, 1
; GFX9-NEXT: s_and_b32 s5, s5, 1
; GFX9-NEXT: s_lshl_b32 s5, s5, 4
; GFX9-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_movrels_b32 s6, s0
; GFX9-NEXT: s_lshl_b32 s4, s4, s5
; GFX9-NEXT: s_lshl_b32 s5, 0xffff, s5
-; GFX9-NEXT: s_andn2_b32 s5, s7, s5
+; GFX9-NEXT: s_andn2_b32 s5, s6, s5
; GFX9-NEXT: s_or_b32 s4, s5, s4
-; GFX9-NEXT: s_cmp_eq_u32 s6, 0
-; GFX9-NEXT: s_cselect_b32 s0, s4, s0
-; GFX9-NEXT: s_cmp_eq_u32 s6, 1
-; GFX9-NEXT: s_cselect_b32 s1, s4, s1
-; GFX9-NEXT: s_cmp_eq_u32 s6, 2
-; GFX9-NEXT: s_cselect_b32 s2, s4, s2
-; GFX9-NEXT: s_cmp_eq_u32 s6, 3
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
+; GFX9-NEXT: s_movreld_b32 s0, s4
; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
@@ -1699,32 +1638,20 @@ define amdgpu_ps void @insertelement_s_v8i16_s_s(ptr addrspace(4) inreg %ptr, i1
; GFX8-LABEL: insertelement_s_v8i16_s_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX8-NEXT: s_lshr_b32 s6, s5, 1
-; GFX8-NEXT: s_cmp_eq_u32 s6, 1
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
-; GFX8-NEXT: v_mov_b32_e32 v5, 0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_cselect_b32 s7, s1, s0
-; GFX8-NEXT: s_cmp_eq_u32 s6, 2
-; GFX8-NEXT: s_cselect_b32 s7, s2, s7
-; GFX8-NEXT: s_cmp_eq_u32 s6, 3
-; GFX8-NEXT: s_cselect_b32 s7, s3, s7
+; GFX8-NEXT: s_lshr_b32 m0, s5, 1
; GFX8-NEXT: s_and_b32 s5, s5, 1
; GFX8-NEXT: s_lshl_b32 s5, s5, 4
; GFX8-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_movrels_b32 s6, s0
; GFX8-NEXT: s_lshl_b32 s4, s4, s5
; GFX8-NEXT: s_lshl_b32 s5, 0xffff, s5
-; GFX8-NEXT: s_andn2_b32 s5, s7, s5
+; GFX8-NEXT: s_andn2_b32 s5, s6, s5
; GFX8-NEXT: s_or_b32 s4, s5, s4
-; GFX8-NEXT: s_cmp_eq_u32 s6, 0
-; GFX8-NEXT: s_cselect_b32 s0, s4, s0
-; GFX8-NEXT: s_cmp_eq_u32 s6, 1
-; GFX8-NEXT: s_cselect_b32 s1, s4, s1
-; GFX8-NEXT: s_cmp_eq_u32 s6, 2
-; GFX8-NEXT: s_cselect_b32 s2, s4, s2
-; GFX8-NEXT: s_cmp_eq_u32 s6, 3
-; GFX8-NEXT: s_cselect_b32 s3, s4, s3
+; GFX8-NEXT: s_movreld_b32 s0, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
@@ -1734,29 +1661,17 @@ define amdgpu_ps void @insertelement_s_v8i16_s_s(ptr addrspace(4) inreg %ptr, i1
; GFX7-LABEL: insertelement_s_v8i16_s_s:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX7-NEXT: s_lshr_b32 s6, s5, 1
-; GFX7-NEXT: s_cmp_eq_u32 s6, 1
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_cselect_b32 s7, s1, s0
-; GFX7-NEXT: s_cmp_eq_u32 s6, 2
-; GFX7-NEXT: s_cselect_b32 s7, s2, s7
-; GFX7-NEXT: s_cmp_eq_u32 s6, 3
-; GFX7-NEXT: s_cselect_b32 s7, s3, s7
+; GFX7-NEXT: s_lshr_b32 m0, s5, 1
; GFX7-NEXT: s_and_b32 s5, s5, 1
; GFX7-NEXT: s_lshl_b32 s5, s5, 4
; GFX7-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_movrels_b32 s6, s0
; GFX7-NEXT: s_lshl_b32 s4, s4, s5
; GFX7-NEXT: s_lshl_b32 s5, 0xffff, s5
-; GFX7-NEXT: s_andn2_b32 s5, s7, s5
+; GFX7-NEXT: s_andn2_b32 s5, s6, s5
; GFX7-NEXT: s_or_b32 s4, s5, s4
-; GFX7-NEXT: s_cmp_eq_u32 s6, 0
-; GFX7-NEXT: s_cselect_b32 s0, s4, s0
-; GFX7-NEXT: s_cmp_eq_u32 s6, 1
-; GFX7-NEXT: s_cselect_b32 s1, s4, s1
-; GFX7-NEXT: s_cmp_eq_u32 s6, 2
-; GFX7-NEXT: s_cselect_b32 s2, s4, s2
-; GFX7-NEXT: s_cmp_eq_u32 s6, 3
-; GFX7-NEXT: s_cselect_b32 s3, s4, s3
+; GFX7-NEXT: s_movreld_b32 s0, s4
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
@@ -1770,31 +1685,19 @@ define amdgpu_ps void @insertelement_s_v8i16_s_s(ptr addrspace(4) inreg %ptr, i1
; GFX10-LABEL: insertelement_s_v8i16_s_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX10-NEXT: s_lshr_b32 s6, s5, 1
-; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: s_cmp_eq_u32 s6, 1
-; GFX10-NEXT: v_mov_b32_e32 v5, 0
-; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_cselect_b32 s7, s1, s0
-; GFX10-NEXT: s_cmp_eq_u32 s6, 2
-; GFX10-NEXT: s_cselect_b32 s7, s2, s7
-; GFX10-NEXT: s_cmp_eq_u32 s6, 3
-; GFX10-NEXT: s_cselect_b32 s7, s3, s7
+; GFX10-NEXT: s_lshr_b32 m0, s5, 1
; GFX10-NEXT: s_and_b32 s5, s5, 1
; GFX10-NEXT: s_and_b32 s4, s4, 0xffff
; GFX10-NEXT: s_lshl_b32 s5, s5, 4
-; GFX10-NEXT: s_lshl_b32 s8, 0xffff, s5
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: s_lshl_b32 s7, 0xffff, s5
; GFX10-NEXT: s_lshl_b32 s4, s4, s5
-; GFX10-NEXT: s_andn2_b32 s5, s7, s8
+; GFX10-NEXT: v_mov_b32_e32 v5, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_movrels_b32 s6, s0
+; GFX10-NEXT: s_andn2_b32 s5, s6, s7
; GFX10-NEXT: s_or_b32 s4, s5, s4
-; GFX10-NEXT: s_cmp_eq_u32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s0, s4, s0
-; GFX10-NEXT: s_cmp_eq_u32 s6, 1
-; GFX10-NEXT: s_cselect_b32 s1, s4, s1
-; GFX10-NEXT: s_cmp_eq_u32 s6, 2
-; GFX10-NEXT: s_cselect_b32 s2, s4, s2
-; GFX10-NEXT: s_cmp_eq_u32 s6, 3
-; GFX10-NEXT: s_cselect_b32 s3, s4, s3
+; GFX10-NEXT: s_movreld_b32 s0, s4
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s2
@@ -1805,31 +1708,20 @@ define amdgpu_ps void @insertelement_s_v8i16_s_s(ptr addrspace(4) inreg %ptr, i1
; GFX11-LABEL: insertelement_s_v8i16_s_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0
-; GFX11-NEXT: s_lshr_b32 s6, s5, 1
-; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
-; GFX11-NEXT: s_cmp_eq_u32 s6, 1
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_cselect_b32 s7, s1, s0
-; GFX11-NEXT: s_cmp_eq_u32 s6, 2
-; GFX11-NEXT: s_cselect_b32 s7, s2, s7
-; GFX11-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-NEXT: s_cselect_b32 s7, s3, s7
+; GFX11-NEXT: s_lshr_b32 m0, s5, 1
; GFX11-NEXT: s_and_b32 s5, s5, 1
; GFX11-NEXT: s_and_b32 s4, s4, 0xffff
; GFX11-NEXT: s_lshl_b32 s5, s5, 4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b32 s8, 0xffff, s5
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
+; GFX11-NEXT: s_lshl_b32 s7, 0xffff, s5
; GFX11-NEXT: s_lshl_b32 s4, s4, s5
-; GFX11-NEXT: s_and_not1_b32 s5, s7, s8
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_movrels_b32 s6, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_not1_b32 s5, s6, s7
; GFX11-NEXT: s_or_b32 s4, s5, s4
-; GFX11-NEXT: s_cmp_eq_u32 s6, 0
-; GFX11-NEXT: s_cselect_b32 s0, s4, s0
-; GFX11-NEXT: s_cmp_eq_u32 s6, 1
-; GFX11-NEXT: s_cselect_b32 s1, s4, s1
-; GFX11-NEXT: s_cmp_eq_u32 s6, 2
-; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-NEXT: s_cselect_b32 s3, s4, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_movreld_b32 s0, s4
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
@@ -1844,145 +1736,104 @@ define amdgpu_ps void @insertelement_v_v8i16_s_s(ptr addrspace(1) %ptr, i16 inre
; GFX9-LABEL: insertelement_v_v8i16_s_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT: s_and_b32 s0, s3, 1
-; GFX9-NEXT: s_lshr_b32 s4, s3, 1
-; GFX9-NEXT: s_and_b32 s1, s2, 0xffff
-; GFX9-NEXT: s_lshl_b32 s0, s0, 4
-; GFX9-NEXT: s_lshl_b32 s1, s1, s0
-; GFX9-NEXT: s_lshl_b32 s0, 0xffff, s0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX9-NEXT: s_not_b32 s5, s0
-; GFX9-NEXT: v_mov_b32_e32 v6, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
+; GFX9-NEXT: s_and_b32 s1, s3, 1
+; GFX9-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX9-NEXT: s_lshl_b32 s1, s1, 4
+; GFX9-NEXT: s_lshr_b32 s0, s3, 1
+; GFX9-NEXT: s_lshl_b32 s2, s2, s1
+; GFX9-NEXT: s_lshl_b32 s1, 0xffff, s1
+; GFX9-NEXT: s_not_b32 s1, s1
+; GFX9-NEXT: v_mov_b32_e32 v4, s2
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
+; GFX9-NEXT: v_mov_b32_e32 v5, v0
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_or_b32 v6, v5, s1, v4
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v2, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v3, s[2:3]
-; GFX9-NEXT: v_and_or_b32 v6, v7, s5, v6
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v6
+; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v8i16_s_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
-; GFX8-NEXT: s_lshr_b32 s4, s3, 1
; GFX8-NEXT: s_and_b32 s0, s3, 1
+; GFX8-NEXT: s_lshr_b32 m0, s3, 1
; GFX8-NEXT: s_and_b32 s1, s2, 0xffff
; GFX8-NEXT: s_lshl_b32 s0, s0, 4
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX8-NEXT: s_lshl_b32 s5, s1, s0
-; GFX8-NEXT: s_lshl_b32 s6, 0xffff, s0
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: s_lshl_b32 s1, s1, s0
+; GFX8-NEXT: s_lshl_b32 s0, 0xffff, s0
; GFX8-NEXT: v_mov_b32_e32 v5, 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v2, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[2:3]
-; GFX8-NEXT: v_bfi_b32 v6, s6, 0, v6
-; GFX8-NEXT: v_or_b32_e32 v6, s5, v6
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
+; GFX8-NEXT: v_movrels_b32_e32 v4, v0
+; GFX8-NEXT: v_bfi_b32 v4, s0, 0, v4
+; GFX8-NEXT: v_or_b32_e32 v6, s1, v4
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_movreld_b32_e32 v0, v6
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_v_v8i16_s_s:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b64 s[8:9], 0
-; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_lshr_b32 s4, s3, 1
+; GFX7-NEXT: s_mov_b32 s6, 0
+; GFX7-NEXT: s_mov_b32 s7, 0xf000
+; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64
; GFX7-NEXT: s_and_b32 s0, s3, 1
+; GFX7-NEXT: s_lshr_b32 m0, s3, 1
; GFX7-NEXT: s_and_b32 s1, s2, 0xffff
; GFX7-NEXT: s_lshl_b32 s0, s0, 4
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX7-NEXT: s_lshl_b32 s5, s1, s0
-; GFX7-NEXT: s_lshl_b32 s6, 0xffff, s0
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
-; GFX7-NEXT: s_mov_b64 s[8:9], 0
-; GFX7-NEXT: s_mov_b32 s10, -1
+; GFX7-NEXT: s_lshl_b32 s1, s1, s0
+; GFX7-NEXT: s_lshl_b32 s0, 0xffff, s0
+; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v2, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[2:3]
-; GFX7-NEXT: v_bfi_b32 v4, s6, 0, v4
-; GFX7-NEXT: v_or_b32_e32 v4, s5, v4
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[2:3]
-; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX7-NEXT: v_movrels_b32_e32 v4, v0
+; GFX7-NEXT: v_bfi_b32 v4, s0, 0, v4
+; GFX7-NEXT: v_or_b32_e32 v4, s1, v4
+; GFX7-NEXT: v_movreld_b32_e32 v0, v4
+; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_v_v8i16_s_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-NEXT: s_lshr_b32 s4, s3, 1
-; GFX10-NEXT: s_and_b32 s1, s3, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s4, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s4, 2
-; GFX10-NEXT: s_lshl_b32 s3, s1, 4
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s4, 3
-; GFX10-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX10-NEXT: s_lshl_b32 s5, 0xffff, s3
-; GFX10-NEXT: s_lshl_b32 s2, s2, s3
-; GFX10-NEXT: s_not_b32 s3, s5
+; GFX10-NEXT: s_and_b32 s0, s3, 1
+; GFX10-NEXT: s_lshr_b32 m0, s3, 1
+; GFX10-NEXT: s_lshl_b32 s0, s0, 4
+; GFX10-NEXT: s_and_b32 s1, s2, 0xffff
+; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s0
+; GFX10-NEXT: s_lshl_b32 s0, s1, s0
+; GFX10-NEXT: s_not_b32 s1, s2
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v3, s1
-; GFX10-NEXT: v_and_or_b32 v6, v4, s3, s2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s4, 0
+; GFX10-NEXT: v_movrels_b32_e32 v4, v0
+; GFX10-NEXT: v_and_or_b32 v6, v4, s1, s0
; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v6, s1
+; GFX10-NEXT: v_movreld_b32_e32 v0, v6
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_v_v8i16_s_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
-; GFX11-NEXT: s_lshr_b32 s4, s3, 1
-; GFX11-NEXT: s_and_b32 s1, s3, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s4, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s4, 2
-; GFX11-NEXT: s_lshl_b32 s3, s1, 4
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s4, 3
-; GFX11-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX11-NEXT: s_lshl_b32 s5, 0xffff, s3
-; GFX11-NEXT: s_lshl_b32 s2, s2, s3
-; GFX11-NEXT: s_not_b32 s3, s5
+; GFX11-NEXT: s_and_b32 s0, s3, 1
+; GFX11-NEXT: s_lshr_b32 m0, s3, 1
+; GFX11-NEXT: s_lshl_b32 s0, s0, 4
+; GFX11-NEXT: s_and_b32 s1, s2, 0xffff
+; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s0
+; GFX11-NEXT: s_lshl_b32 s0, s1, s0
+; GFX11-NEXT: s_not_b32 s1, s2
+; GFX11-NEXT: v_mov_b32_e32 v5, 0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_cndmask_b32 v4, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v3, s1
+; GFX11-NEXT: v_movrels_b32_e32 v4, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v6, v4, s3, s2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, s4, 0
-; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v1, v1, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v6, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v6, s1
+; GFX11-NEXT: v_and_or_b32 v6, v4, s1, s0
+; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: v_movreld_b32_e32 v0, v6
; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
; GFX11-NEXT: s_endpgm
%vec = load <8 x i16>, ptr addrspace(1 ) %ptr
@@ -1996,173 +1847,115 @@ define amdgpu_ps void @insertelement_s_v8i16_v_s(ptr addrspace(4) inreg %ptr, i1
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
; GFX9-NEXT: s_lshr_b32 s5, s4, 1
-; GFX9-NEXT: s_cmp_eq_u32 s5, 1
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_cselect_b32 s6, s1, s0
-; GFX9-NEXT: s_cmp_eq_u32 s5, 2
-; GFX9-NEXT: s_cselect_b32 s6, s2, s6
-; GFX9-NEXT: s_cmp_eq_u32 s5, 3
-; GFX9-NEXT: s_cselect_b32 s6, s3, s6
; GFX9-NEXT: s_and_b32 s4, s4, 1
+; GFX9-NEXT: s_mov_b32 m0, s5
; GFX9-NEXT: s_lshl_b32 s4, s4, 4
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_movrels_b32 s6, s0
; GFX9-NEXT: s_lshl_b32 s7, 0xffff, s4
; GFX9-NEXT: s_andn2_b32 s6, s6, s7
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_lshl_or_b32 v6, v0, s4, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s5, 2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s5, 3
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: s_set_gpr_idx_on s5, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v6
+; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v8i16_v_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX8-NEXT: s_lshr_b32 s5, s4, 1
-; GFX8-NEXT: s_cmp_eq_u32 s5, 1
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_cselect_b32 s6, s1, s0
-; GFX8-NEXT: s_cmp_eq_u32 s5, 2
-; GFX8-NEXT: s_cselect_b32 s6, s2, s6
-; GFX8-NEXT: s_cmp_eq_u32 s5, 3
-; GFX8-NEXT: s_cselect_b32 s6, s3, s6
+; GFX8-NEXT: s_lshr_b32 m0, s4, 1
; GFX8-NEXT: s_and_b32 s4, s4, 1
; GFX8-NEXT: s_lshl_b32 s4, s4, 4
; GFX8-NEXT: v_mov_b32_e32 v1, s4
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_movrels_b32 s5, s0
; GFX8-NEXT: s_lshl_b32 s4, 0xffff, s4
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT: s_andn2_b32 s4, s6, s4
+; GFX8-NEXT: s_andn2_b32 s4, s5, s4
; GFX8-NEXT: v_or_b32_e32 v6, s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s5, 2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s5, 3
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
; GFX8-NEXT: v_mov_b32_e32 v5, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX8-NEXT: v_movreld_b32_e32 v0, v6
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v8i16_v_s:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX7-NEXT: s_lshr_b32 s5, s4, 1
-; GFX7-NEXT: s_cmp_eq_u32 s5, 1
-; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_cselect_b32 s6, s1, s0
-; GFX7-NEXT: s_cmp_eq_u32 s5, 2
-; GFX7-NEXT: s_cselect_b32 s6, s2, s6
-; GFX7-NEXT: s_cmp_eq_u32 s5, 3
-; GFX7-NEXT: s_cselect_b32 s6, s3, s6
+; GFX7-NEXT: s_lshr_b32 m0, s4, 1
; GFX7-NEXT: s_and_b32 s4, s4, 1
; GFX7-NEXT: s_lshl_b32 s4, s4, 4
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_movrels_b32 s5, s0
; GFX7-NEXT: v_lshlrev_b32_e32 v0, s4, v0
; GFX7-NEXT: s_lshl_b32 s4, 0xffff, s4
-; GFX7-NEXT: s_andn2_b32 s4, s6, s4
+; GFX7-NEXT: s_andn2_b32 s4, s5, s4
; GFX7-NEXT: v_or_b32_e32 v4, s4, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
; GFX7-NEXT: v_mov_b32_e32 v2, s2
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 3
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: v_movreld_b32_e32 v0, v4
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_s_v8i16_v_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX10-NEXT: s_lshr_b32 s5, s4, 1
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v0
-; GFX10-NEXT: s_cmp_eq_u32 s5, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 0
+; GFX10-NEXT: s_and_b32 s5, s4, 1
+; GFX10-NEXT: s_lshr_b32 m0, s4, 1
+; GFX10-NEXT: s_lshl_b32 s4, s5, 4
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: s_lshl_b32 s5, 0xffff, s4
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_cselect_b32 s6, s1, s0
-; GFX10-NEXT: s_cmp_eq_u32 s5, 2
+; GFX10-NEXT: s_movrels_b32 s6, s0
+; GFX10-NEXT: s_andn2_b32 s5, s6, s5
+; GFX10-NEXT: v_lshl_or_b32 v6, v0, s4, s5
; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: s_cselect_b32 s6, s2, s6
-; GFX10-NEXT: s_cmp_eq_u32 s5, 3
; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: s_cselect_b32 s6, s3, s6
-; GFX10-NEXT: s_and_b32 s4, s4, 1
; GFX10-NEXT: v_mov_b32_e32 v2, s2
-; GFX10-NEXT: s_lshl_b32 s4, s4, 4
; GFX10-NEXT: v_mov_b32_e32 v3, s3
-; GFX10-NEXT: s_lshl_b32 s7, 0xffff, s4
-; GFX10-NEXT: s_andn2_b32 s6, s6, s7
-; GFX10-NEXT: v_lshl_or_b32 v6, v4, s4, s6
-; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 1
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 2
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 3
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX10-NEXT: v_movreld_b32_e32 v0, v6
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v8i16_v_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0
-; GFX11-NEXT: s_lshr_b32 s5, s4, 1
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v0
-; GFX11-NEXT: s_cmp_eq_u32 s5, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 0
-; GFX11-NEXT: v_mov_b32_e32 v5, 0
+; GFX11-NEXT: s_and_b32 s5, s4, 1
+; GFX11-NEXT: s_lshr_b32 m0, s4, 1
+; GFX11-NEXT: s_lshl_b32 s4, s5, 4
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: s_lshl_b32 s5, 0xffff, s4
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_cselect_b32 s6, s1, s0
-; GFX11-NEXT: s_cmp_eq_u32 s5, 2
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX11-NEXT: s_cselect_b32 s6, s2, s6
-; GFX11-NEXT: s_cmp_eq_u32 s5, 3
-; GFX11-NEXT: v_mov_b32_e32 v1, s1
-; GFX11-NEXT: s_cselect_b32 s6, s3, s6
-; GFX11-NEXT: s_and_b32 s4, s4, 1
-; GFX11-NEXT: v_mov_b32_e32 v2, s2
-; GFX11-NEXT: s_lshl_b32 s4, s4, 4
+; GFX11-NEXT: s_movrels_b32 s6, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b32 s7, 0xffff, s4
-; GFX11-NEXT: s_and_not1_b32 s6, s6, s7
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v6, v4, s4, s6
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 1
-; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v1, v1, v6
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 2
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 3
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX11-NEXT: s_and_not1_b32 s5, s6, s5
+; GFX11-NEXT: v_lshl_or_b32 v6, v0, s4, s5
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_movreld_b32_e32 v0, v6
; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
; GFX11-NEXT: s_endpgm
%vec = load <8 x i16>, ptr addrspace(4) %ptr
@@ -2174,109 +1967,97 @@ define amdgpu_ps void @insertelement_s_v8i16_v_s(ptr addrspace(4) inreg %ptr, i1
define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i16 inreg %val, i32 %idx) {
; GFX9-LABEL: insertelement_s_v8i16_s_v:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 1, v0
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, s8
-; GFX9-NEXT: v_mov_b32_e32 v2, s9
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v4, s3
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s2
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
; GFX9-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xffff
-; GFX9-NEXT: v_mov_b32_e32 v5, s11
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
-; GFX9-NEXT: v_lshlrev_b32_e64 v2, v0, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v8, 0xffff
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
+; GFX9-NEXT: v_lshlrev_b32_e64 v7, v0, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_and_or_b32 v6, v1, v0, v2
-; GFX9-NEXT: v_mov_b32_e32 v0, s8
-; GFX9-NEXT: v_mov_b32_e32 v1, s9
-; GFX9-NEXT: v_mov_b32_e32 v2, s10
-; GFX9-NEXT: v_mov_b32_e32 v3, s11
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_and_or_b32 v7, v6, v0, v7
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v7, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v7, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
-; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v7, s[2:3]
+; GFX9-NEXT: global_store_dwordx4 v[5:6], v[0:3], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v8i16_s_v:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 1, v0
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s8
-; GFX8-NEXT: v_mov_b32_e32 v2, s9
-; GFX8-NEXT: v_mov_b32_e32 v3, s10
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: v_mov_b32_e32 v5, s11
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v4, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX8-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX8-NEXT: v_mov_b32_e32 v3, 0xffff
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
-; GFX8-NEXT: v_lshlrev_b32_e64 v2, v0, s4
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v3
-; GFX8-NEXT: v_bfi_b32 v0, v0, 0, v1
-; GFX8-NEXT: v_or_b32_e32 v6, v0, v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s8
-; GFX8-NEXT: v_mov_b32_e32 v1, s9
-; GFX8-NEXT: v_mov_b32_e32 v2, s10
-; GFX8-NEXT: v_mov_b32_e32 v3, s11
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_mov_b32_e32 v8, 0xffff
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
+; GFX8-NEXT: v_lshlrev_b32_e64 v7, v0, s4
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v8
+; GFX8-NEXT: v_bfi_b32 v0, v0, 0, v6
+; GFX8-NEXT: v_or_b32_e32 v7, v0, v7
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, v7, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v7, s[0:1]
; GFX8-NEXT: v_mov_b32_e32 v5, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v6, 0
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, v7, s[2:3]
+; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v8i16_s_v:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 1, v0
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v1, s8
-; GFX7-NEXT: v_mov_b32_e32 v2, s9
-; GFX7-NEXT: v_mov_b32_e32 v3, s10
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX7-NEXT: v_mov_b32_e32 v5, s11
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v4, s3
+; GFX7-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-NEXT: v_mov_b32_e32 v1, s0
+; GFX7-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX7-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
-; GFX7-NEXT: v_lshl_b32_e32 v2, s4, v0
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
+; GFX7-NEXT: v_lshl_b32_e32 v7, s4, v0
; GFX7-NEXT: v_lshl_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_bfi_b32 v0, v0, 0, v1
-; GFX7-NEXT: v_or_b32_e32 v5, v0, v2
-; GFX7-NEXT: v_mov_b32_e32 v0, s8
-; GFX7-NEXT: v_mov_b32_e32 v1, s9
-; GFX7-NEXT: v_mov_b32_e32 v2, s10
-; GFX7-NEXT: v_mov_b32_e32 v3, s11
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[2:3]
+; GFX7-NEXT: v_bfi_b32 v0, v0, 0, v6
+; GFX7-NEXT: v_or_b32_e32 v6, v0, v7
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v1, v6, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v3, v6, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v4, v6, s[2:3]
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
@@ -2285,28 +2066,27 @@ define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i1
;
; GFX10-LABEL: insertelement_s_v8i16_s_v:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 1, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 1, v0
-; GFX10-NEXT: s_and_b32 s1, s4, 0xffff
+; GFX10-NEXT: v_and_b32_e32 v4, 1, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 4, v4
+; GFX10-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff
+; GFX10-NEXT: v_not_b32_e32 v7, v7
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v6
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
-; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xffff
-; GFX10-NEXT: v_lshlrev_b32_e64 v4, v1, s1
+; GFX10-NEXT: s_and_b32 s1, s4, 0xffff
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e64 v4, v4, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v6
-; GFX10-NEXT: v_not_b32_e32 v5, v2
-; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v0, s9
-; GFX10-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s10, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v0, s11, s1
-; GFX10-NEXT: v_mov_b32_e32 v0, s8
-; GFX10-NEXT: v_mov_b32_e32 v1, s9
-; GFX10-NEXT: v_mov_b32_e32 v2, s10
-; GFX10-NEXT: v_mov_b32_e32 v3, s11
-; GFX10-NEXT: v_and_or_b32 v7, v7, v5, v4
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v3, s1
+; GFX10-NEXT: v_and_or_b32 v7, v5, v7, v4
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
@@ -2318,29 +2098,28 @@ define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i1
;
; GFX11-LABEL: insertelement_s_v8i16_s_v:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[8:11], s[2:3], 0x0
+; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 1, v0
-; GFX11-NEXT: v_and_b32_e32 v1, 1, v0
-; GFX11-NEXT: s_and_b32 s1, s4, 0xffff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_b32_e32 v4, 1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 4, v4
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v6
+; GFX11-NEXT: s_and_b32 s1, s4, 0xffff
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s9 :: v_dual_lshlrev_b32 v1, 4, v1
-; GFX11-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b32_e64 v2, v1, 0xffff
-; GFX11-NEXT: v_lshlrev_b32_e64 v4, v1, s1
+; GFX11-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff
+; GFX11-NEXT: v_lshlrev_b32_e64 v4, v4, s1
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v6
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s10, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_not_b32_e32 v5, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v0, s11, s1
-; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX11-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v7, v7, v5, v4
+; GFX11-NEXT: v_not_b32_e32 v7, v7
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v3, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_or_b32 v7, v5, v7, v4
; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
@@ -2357,107 +2136,95 @@ define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i1
define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i16 %val, i32 %idx) {
; GFX9-LABEL: insertelement_s_v8i16_v_v:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 1, v1
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 1, v1
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
-; GFX9-NEXT: v_mov_b32_e32 v3, s5
-; GFX9-NEXT: v_mov_b32_e32 v5, s6
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xffff
-; GFX9-NEXT: v_mov_b32_e32 v6, s7
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v5, s3
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v4, s2
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
+; GFX9-NEXT: v_mov_b32_e32 v8, 0xffff
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[2:3]
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX9-NEXT: v_not_b32_e32 v1, v1
-; GFX9-NEXT: v_and_or_b32 v6, v2, v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
-; GFX9-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-NEXT: v_mov_b32_e32 v2, s6
-; GFX9-NEXT: v_mov_b32_e32 v3, s7
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
-; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
+; GFX9-NEXT: v_and_or_b32 v8, v7, v1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v8, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v8, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: v_mov_b32_e32 v7, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v8, s[2:3]
+; GFX9-NEXT: global_store_dwordx4 v[6:7], v[0:3], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v8i16_v_v:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 1, v1
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 1, v1
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
-; GFX8-NEXT: v_mov_b32_e32 v3, s5
-; GFX8-NEXT: v_mov_b32_e32 v5, s6
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX8-NEXT: v_mov_b32_e32 v6, s7
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX8-NEXT: v_mov_b32_e32 v3, 0xffff
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[2:3]
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
+; GFX8-NEXT: v_mov_b32_e32 v8, 0xffff
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_bfi_b32 v1, v1, 0, v2
-; GFX8-NEXT: v_or_b32_e32 v6, v1, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_mov_b32_e32 v2, s6
-; GFX8-NEXT: v_mov_b32_e32 v3, s7
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
-; GFX8-NEXT: v_mov_b32_e32 v5, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v8
+; GFX8-NEXT: v_bfi_b32 v1, v1, 0, v7
+; GFX8-NEXT: v_or_b32_e32 v8, v1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v8, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, v8, s[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v6, 0
+; GFX8-NEXT: v_mov_b32_e32 v7, 0
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v8, s[2:3]
+; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v8i16_v_v:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 1, v1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 1, v1
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
-; GFX7-NEXT: v_mov_b32_e32 v3, s5
-; GFX7-NEXT: v_mov_b32_e32 v5, s6
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX7-NEXT: v_mov_b32_e32 v6, s7
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[2:3]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
-; GFX7-NEXT: v_bfi_b32 v1, v1, 0, v2
-; GFX7-NEXT: v_or_b32_e32 v5, v1, v0
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-NEXT: v_mov_b32_e32 v1, s5
-; GFX7-NEXT: v_mov_b32_e32 v2, s6
-; GFX7-NEXT: v_mov_b32_e32 v3, s7
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[2:3]
+; GFX7-NEXT: v_bfi_b32 v1, v1, 0, v7
+; GFX7-NEXT: v_or_b32_e32 v7, v1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, v7, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v7, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, v7, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[2:3]
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
@@ -2466,70 +2233,66 @@ define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i1
;
; GFX10-LABEL: insertelement_s_v8i16_v_v:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 1, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v1
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v6
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v6
-; GFX10-NEXT: s_mov_b32 null, 0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
-; GFX10-NEXT: v_lshlrev_b32_e64 v3, v2, 0xffff
-; GFX10-NEXT: v_lshlrev_b32_sdwa v4, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX10-NEXT: v_not_b32_e32 v5, v3
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX10-NEXT: v_lshrrev_b32_e32 v7, 1, v1
+; GFX10-NEXT: v_and_b32_e32 v5, 1, v1
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 4, v5
+; GFX10-NEXT: v_lshlrev_b32_e64 v8, v5, 0xffff
+; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX10-NEXT: v_not_b32_e32 v5, v8
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v1, s4, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v1, s7, s1
-; GFX10-NEXT: v_mov_b32_e32 v0, s4
-; GFX10-NEXT: v_mov_b32_e32 v1, s5
-; GFX10-NEXT: v_mov_b32_e32 v2, s6
-; GFX10-NEXT: v_mov_b32_e32 v3, s7
-; GFX10-NEXT: v_and_or_b32 v7, v7, v5, v4
-; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: v_mov_b32_e32 v4, s3
+; GFX10-NEXT: v_mov_b32_e32 v2, s1
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v7
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v7
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v3, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v4, s1
+; GFX10-NEXT: v_and_or_b32 v8, v6, v5, v0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
-; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
+; GFX10-NEXT: v_mov_b32_e32 v6, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, v8, s2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, v8, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, v8, s1
+; GFX10-NEXT: global_store_dwordx4 v[5:6], v[0:3], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v8i16_v_v:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 1, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 1, v1
+; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 1, v1
+; GFX11-NEXT: v_and_b32_e32 v5, 1, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v6
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v6
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_lshlrev_b32 v2, 4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, s4, v1, vcc_lo
-; GFX11-NEXT: v_lshlrev_b32_e64 v3, v2, 0xffff
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, v2, v0
+; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 4, v5
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v7
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v7
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e64 v8, v5, 0xffff
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, v5, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, s0
-; GFX11-NEXT: v_not_b32_e32 v5, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v1, s7, s1
-; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX11-NEXT: v_mov_b32_e32 v3, s7
-; GFX11-NEXT: v_and_or_b32 v7, v7, v5, v4
-; GFX11-NEXT: v_mov_b32_e32 v2, s6
-; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
-; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v3, s0
+; GFX11-NEXT: v_not_b32_e32 v5, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v4, s1
+; GFX11-NEXT: v_and_or_b32 v8, v6, v5, v0
+; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, v8, s2
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, v8, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, v8, s1
+; GFX11-NEXT: global_store_b128 v[5:6], v[0:3], off
; GFX11-NEXT: s_endpgm
%vec = load <8 x i16>, ptr addrspace(4) %ptr
%insert = insertelement <8 x i16> %vec, i16 %val, i32 %idx
@@ -2696,145 +2459,103 @@ define amdgpu_ps void @insertelement_v_v8i16_v_s(ptr addrspace(1) %ptr, i16 %val
; GFX9-LABEL: insertelement_v_v8i16_v_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
-; GFX9-NEXT: s_and_b32 s0, s2, 1
-; GFX9-NEXT: s_lshr_b32 s4, s2, 1
-; GFX9-NEXT: s_lshl_b32 s0, s0, 4
-; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX9-NEXT: s_lshl_b32 s0, 0xffff, s0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX9-NEXT: s_not_b32 s5, s0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
-; GFX9-NEXT: v_mov_b32_e32 v7, 0
-; GFX9-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-NEXT: s_and_b32 s1, s2, 1
+; GFX9-NEXT: s_lshl_b32 s1, s1, 4
+; GFX9-NEXT: s_lshr_b32 s0, s2, 1
+; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX9-NEXT: s_lshl_b32 s1, 0xffff, s1
+; GFX9-NEXT: s_not_b32 s1, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3]
-; GFX9-NEXT: v_and_or_b32 v9, v1, s5, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v9, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v9, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v9, s[2:3]
-; GFX9-NEXT: global_store_dwordx4 v[7:8], v[0:3], off
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
+; GFX9-NEXT: v_mov_b32_e32 v1, v3
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_or_b32 v2, v1, s1, v0
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v3, v2
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v8i16_v_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1]
-; GFX8-NEXT: s_lshr_b32 s4, s2, 1
; GFX8-NEXT: s_and_b32 s0, s2, 1
+; GFX8-NEXT: s_lshr_b32 m0, s2, 1
; GFX8-NEXT: s_lshl_b32 s0, s0, 4
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: s_lshl_b32 s5, 0xffff, s0
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
+; GFX8-NEXT: s_lshl_b32 s0, 0xffff, s0
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT: v_mov_b32_e32 v7, 0
-; GFX8-NEXT: v_mov_b32_e32 v8, 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3]
-; GFX8-NEXT: v_bfi_b32 v1, s5, 0, v1
-; GFX8-NEXT: v_or_b32_e32 v9, v1, v0
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v3, v9, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v5, v9, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v6, v9, s[2:3]
-; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[0:3]
+; GFX8-NEXT: v_movrels_b32_e32 v1, v3
+; GFX8-NEXT: v_bfi_b32 v1, s0, 0, v1
+; GFX8-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NEXT: v_movreld_b32_e32 v3, v2
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[3:6]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_v_v8i16_v_s:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b64 s[8:9], 0
-; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_lshr_b32 s4, s2, 1
+; GFX7-NEXT: s_mov_b32 s6, 0
+; GFX7-NEXT: s_mov_b32 s7, 0xf000
+; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[4:7], 0 addr64
; GFX7-NEXT: s_and_b32 s0, s2, 1
+; GFX7-NEXT: s_lshr_b32 m0, s2, 1
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v2
; GFX7-NEXT: s_lshl_b32 s0, s0, 4
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
; GFX7-NEXT: v_lshlrev_b32_e32 v0, s0, v0
-; GFX7-NEXT: s_lshl_b32 s5, 0xffff, s0
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
-; GFX7-NEXT: s_mov_b64 s[8:9], 0
-; GFX7-NEXT: s_mov_b32 s10, -1
+; GFX7-NEXT: s_lshl_b32 s0, 0xffff, s0
+; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3]
-; GFX7-NEXT: v_bfi_b32 v1, s5, 0, v1
-; GFX7-NEXT: v_or_b32_e32 v7, v1, v0
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v3, v7, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v5, v7, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v6, v7, s[2:3]
-; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX7-NEXT: v_movrels_b32_e32 v1, v3
+; GFX7-NEXT: v_bfi_b32 v1, s0, 0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX7-NEXT: v_movreld_b32_e32 v3, v0
+; GFX7-NEXT: buffer_store_dwordx4 v[3:6], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_v_v8i16_v_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
-; GFX10-NEXT: s_lshr_b32 s3, s2, 1
-; GFX10-NEXT: s_and_b32 s1, s2, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, 2
-; GFX10-NEXT: s_lshl_b32 s2, s1, 4
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s3, 3
-; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX10-NEXT: s_lshl_b32 s2, 0xffff, s2
-; GFX10-NEXT: v_mov_b32_e32 v7, 0
-; GFX10-NEXT: s_not_b32 s2, s2
-; GFX10-NEXT: v_mov_b32_e32 v8, 0
+; GFX10-NEXT: s_and_b32 s0, s2, 1
+; GFX10-NEXT: s_lshr_b32 m0, s2, 1
+; GFX10-NEXT: s_lshl_b32 s0, s0, 4
+; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX10-NEXT: s_lshl_b32 s0, 0xffff, s0
+; GFX10-NEXT: s_not_b32 s0, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s1
-; GFX10-NEXT: v_and_or_b32 v9, v0, s2, v1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s3, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v9, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v9, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v9, s1
-; GFX10-NEXT: global_store_dwordx4 v[7:8], v[0:3], off
+; GFX10-NEXT: v_movrels_b32_e32 v0, v3
+; GFX10-NEXT: v_and_or_b32 v2, v0, s0, v1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_movreld_b32_e32 v3, v2
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_v_v8i16_v_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
-; GFX11-NEXT: s_lshr_b32 s3, s2, 1
-; GFX11-NEXT: s_and_b32 s1, s2, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s3, 2
-; GFX11-NEXT: s_lshl_b32 s2, s1, 4
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s3, 3
-; GFX11-NEXT: v_mov_b32_e32 v7, 0
-; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v1, 0xffff, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, s2, v1
-; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s2
-; GFX11-NEXT: s_not_b32 s2, s2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v2
+; GFX11-NEXT: s_and_b32 s0, s2, 1
+; GFX11-NEXT: s_lshr_b32 m0, s2, 1
+; GFX11-NEXT: s_lshl_b32 s0, s0, 4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, s0, v0
+; GFX11-NEXT: s_lshl_b32 s0, 0xffff, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_not_b32 s0, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v6, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v9, v0, s2, v1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, s3, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
+; GFX11-NEXT: v_movrels_b32_e32 v1, v3
+; GFX11-NEXT: v_and_or_b32 v2, v1, s0, v0
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v3, v9, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v5, v9, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v6, v9, s1
-; GFX11-NEXT: global_store_b128 v[7:8], v[0:3], off
+; GFX11-NEXT: v_movreld_b32_e32 v3, v2
+; GFX11-NEXT: global_store_b128 v[0:1], v[3:6], off
; GFX11-NEXT: s_endpgm
%vec = load <8 x i16>, ptr addrspace(1) %ptr
%insert = insertelement <8 x i16> %vec, i16 %val, i32 %idx
@@ -2997,58 +2718,30 @@ define amdgpu_ps void @insertelement_s_v16i16_s_s(ptr addrspace(4) inreg %ptr, i
; GFX9-LABEL: insertelement_s_v16i16_s_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
-; GFX9-NEXT: s_lshr_b32 s7, s5, 1
-; GFX9-NEXT: s_cmp_eq_u32 s7, 1
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_cselect_b32 s0, s9, s8
-; GFX9-NEXT: s_cmp_eq_u32 s7, 2
-; GFX9-NEXT: s_cselect_b32 s0, s10, s0
-; GFX9-NEXT: s_cmp_eq_u32 s7, 3
-; GFX9-NEXT: s_cselect_b32 s0, s11, s0
-; GFX9-NEXT: s_cmp_eq_u32 s7, 4
-; GFX9-NEXT: s_cselect_b32 s0, s12, s0
-; GFX9-NEXT: s_cmp_eq_u32 s7, 5
-; GFX9-NEXT: s_cselect_b32 s0, s13, s0
-; GFX9-NEXT: s_cmp_eq_u32 s7, 6
-; GFX9-NEXT: s_cselect_b32 s0, s14, s0
-; GFX9-NEXT: s_cmp_eq_u32 s7, 7
-; GFX9-NEXT: s_cselect_b32 s0, s15, s0
; GFX9-NEXT: s_and_b32 s1, s5, 1
+; GFX9-NEXT: s_lshr_b32 m0, s5, 1
; GFX9-NEXT: s_lshl_b32 s1, s1, 4
; GFX9-NEXT: s_and_b32 s2, s4, 0xffff
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_movrels_b32 s0, s8
; GFX9-NEXT: s_lshl_b32 s2, s2, s1
; GFX9-NEXT: s_lshl_b32 s1, 0xffff, s1
; GFX9-NEXT: s_andn2_b32 s0, s0, s1
-; GFX9-NEXT: s_or_b32 s16, s0, s2
-; GFX9-NEXT: s_cmp_eq_u32 s7, 0
-; GFX9-NEXT: s_cselect_b32 s0, s16, s8
-; GFX9-NEXT: s_cmp_eq_u32 s7, 1
-; GFX9-NEXT: s_cselect_b32 s1, s16, s9
-; GFX9-NEXT: s_cmp_eq_u32 s7, 2
-; GFX9-NEXT: s_cselect_b32 s2, s16, s10
-; GFX9-NEXT: s_cmp_eq_u32 s7, 3
-; GFX9-NEXT: s_cselect_b32 s3, s16, s11
-; GFX9-NEXT: s_cmp_eq_u32 s7, 4
-; GFX9-NEXT: s_cselect_b32 s4, s16, s12
-; GFX9-NEXT: s_cmp_eq_u32 s7, 5
-; GFX9-NEXT: s_cselect_b32 s5, s16, s13
-; GFX9-NEXT: s_cmp_eq_u32 s7, 6
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: s_cselect_b32 s6, s16, s14
-; GFX9-NEXT: s_cmp_eq_u32 s7, 7
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_mov_b32_e32 v3, s3
-; GFX9-NEXT: s_cselect_b32 s7, s16, s15
+; GFX9-NEXT: s_or_b32 s0, s0, s2
+; GFX9-NEXT: s_movreld_b32 s8, s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, s9
+; GFX9-NEXT: v_mov_b32_e32 v2, s10
+; GFX9-NEXT: v_mov_b32_e32 v3, s11
; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX9-NEXT: v_mov_b32_e32 v4, 16
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s12
; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-NEXT: v_mov_b32_e32 v2, s6
-; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_mov_b32_e32 v1, s13
+; GFX9-NEXT: v_mov_b32_e32 v2, s14
+; GFX9-NEXT: v_mov_b32_e32 v3, s15
; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX9-NEXT: s_endpgm
;
@@ -3179,46 +2872,28 @@ define amdgpu_ps void @insertelement_v_v16i16_s_s(ptr addrspace(1) %ptr, i16 inr
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dwordx4 v[2:5], v[0:1], off
; GFX9-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:16
-; GFX9-NEXT: s_and_b32 s0, s3, 1
-; GFX9-NEXT: s_lshr_b32 s12, s3, 1
-; GFX9-NEXT: s_and_b32 s1, s2, 0xffff
-; GFX9-NEXT: s_lshl_b32 s0, s0, 4
-; GFX9-NEXT: s_lshl_b32 s1, s1, s0
-; GFX9-NEXT: s_lshl_b32 s0, 0xffff, s0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s12, 1
-; GFX9-NEXT: s_not_b32 s13, s0
-; GFX9-NEXT: v_mov_b32_e32 v0, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s12, 2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s12, 3
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 4
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], s12, 5
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], s12, 6
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], s12, 7
-; GFX9-NEXT: v_mov_b32_e32 v10, 0
+; GFX9-NEXT: s_and_b32 s1, s3, 1
+; GFX9-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX9-NEXT: s_lshl_b32 s1, s1, 4
+; GFX9-NEXT: s_lshr_b32 s0, s3, 1
+; GFX9-NEXT: s_lshl_b32 s2, s2, s1
+; GFX9-NEXT: s_lshl_b32 s1, 0xffff, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_not_b32 s1, s1
+; GFX9-NEXT: v_mov_b32_e32 v12, s2
+; GFX9-NEXT: v_mov_b32_e32 v10, 16
; GFX9-NEXT: v_mov_b32_e32 v11, 0
-; GFX9-NEXT: v_mov_b32_e32 v12, 16
-; GFX9-NEXT: v_mov_b32_e32 v13, 0
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[10:11]
-; GFX9-NEXT: v_and_or_b32 v14, v1, s13, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], s12, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v14, s[12:13]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v14, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v14, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v14, s[2:3]
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v6, v14, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v14, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v14, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v14, s[10:11]
-; GFX9-NEXT: global_store_dwordx4 v[10:11], v[0:3], off
-; GFX9-NEXT: global_store_dwordx4 v[12:13], v[4:7], off
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
+; GFX9-NEXT: v_mov_b32_e32 v13, v2
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_or_b32 v12, v13, s1, v12
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v2, v12
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX9-NEXT: global_store_dwordx4 v[10:11], v[6:9], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v16i16_s_s:
@@ -3330,52 +3005,27 @@ define amdgpu_ps void @insertelement_s_v16i16_v_s(ptr addrspace(4) inreg %ptr, i
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
; GFX9-NEXT: s_lshr_b32 s0, s4, 1
-; GFX9-NEXT: s_cmp_eq_u32 s0, 1
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_cselect_b32 s1, s9, s8
-; GFX9-NEXT: s_cmp_eq_u32 s0, 2
-; GFX9-NEXT: s_cselect_b32 s1, s10, s1
-; GFX9-NEXT: s_cmp_eq_u32 s0, 3
-; GFX9-NEXT: s_cselect_b32 s1, s11, s1
-; GFX9-NEXT: s_cmp_eq_u32 s0, 4
-; GFX9-NEXT: s_cselect_b32 s1, s12, s1
-; GFX9-NEXT: s_cmp_eq_u32 s0, 5
-; GFX9-NEXT: s_cselect_b32 s1, s13, s1
-; GFX9-NEXT: s_cmp_eq_u32 s0, 6
-; GFX9-NEXT: s_cselect_b32 s1, s14, s1
-; GFX9-NEXT: s_cmp_eq_u32 s0, 7
-; GFX9-NEXT: s_cselect_b32 s1, s15, s1
; GFX9-NEXT: s_and_b32 s2, s4, 1
+; GFX9-NEXT: s_mov_b32 m0, s0
; GFX9-NEXT: s_lshl_b32 s2, s2, 4
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_movrels_b32 s1, s8
; GFX9-NEXT: s_lshl_b32 s3, 0xffff, s2
; GFX9-NEXT: s_andn2_b32 s1, s1, s3
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_lshl_or_b32 v8, v0, s2, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_mov_b32_e32 v1, s9
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
; GFX9-NEXT: v_mov_b32_e32 v2, s10
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2
; GFX9-NEXT: v_mov_b32_e32 v3, s11
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3
; GFX9-NEXT: v_mov_b32_e32 v4, s12
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 4
; GFX9-NEXT: v_mov_b32_e32 v5, s13
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 5
; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 6
; GFX9-NEXT: v_mov_b32_e32 v7, s15
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v8
+; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mov_b32_e32 v9, 0
; GFX9-NEXT: v_mov_b32_e32 v10, 16
@@ -3507,56 +3157,48 @@ define amdgpu_ps void @insertelement_s_v16i16_v_s(ptr addrspace(4) inreg %ptr, i
define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i16 inreg %val, i32 %idx) {
; GFX9-LABEL: insertelement_s_v16i16_s_v:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx8 s[16:23], s[2:3], 0x0
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 1, v0
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v8
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v8
+; GFX9-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v9
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v9
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, s16
-; GFX9-NEXT: v_mov_b32_e32 v2, s17
-; GFX9-NEXT: v_mov_b32_e32 v3, s18
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, s19
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v5, s20
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[2:3]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 4, v8
-; GFX9-NEXT: v_mov_b32_e32 v6, s21
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[14:15]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v8
+; GFX9-NEXT: v_mov_b32_e32 v1, s8
+; GFX9-NEXT: v_mov_b32_e32 v2, s9
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v1, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, s11
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v3, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v5, s12
+; GFX9-NEXT: v_mov_b32_e32 v6, s13
+; GFX9-NEXT: v_mov_b32_e32 v7, s14
+; GFX9-NEXT: v_mov_b32_e32 v8, s15
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v4, s[2:3]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 4, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v5, s[14:15]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v9
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX9-NEXT: v_mov_b32_e32 v7, s22
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[6:7]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v6, s[6:7]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v9
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX9-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xffff
-; GFX9-NEXT: v_mov_b32_e32 v9, s23
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[8:9]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v8
-; GFX9-NEXT: v_lshlrev_b32_e64 v2, v0, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[10:11]
+; GFX9-NEXT: v_mov_b32_e32 v12, 0xffff
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v7, s[8:9]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v9
+; GFX9-NEXT: v_lshlrev_b32_e64 v11, v0, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v12
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v8, s[10:11]
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_and_or_b32 v9, v1, v0, v2
-; GFX9-NEXT: v_mov_b32_e32 v0, s16
-; GFX9-NEXT: v_mov_b32_e32 v1, s17
-; GFX9-NEXT: v_mov_b32_e32 v2, s18
-; GFX9-NEXT: v_mov_b32_e32 v3, s19
-; GFX9-NEXT: v_mov_b32_e32 v4, s20
-; GFX9-NEXT: v_mov_b32_e32 v5, s21
-; GFX9-NEXT: v_mov_b32_e32 v6, s22
-; GFX9-NEXT: v_mov_b32_e32 v7, s23
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v8
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[12:13]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[2:3]
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v9, s[14:15]
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[10:11]
+; GFX9-NEXT: v_and_or_b32 v10, v10, v0, v11
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v10, s[12:13]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v10, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v10, s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v5, v10, s[14:15]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v10, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v10, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[10:11]
; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mov_b32_e32 v9, 0
; GFX9-NEXT: v_mov_b32_e32 v10, 16
@@ -3567,56 +3209,48 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
;
; GFX8-LABEL: insertelement_s_v16i16_s_v:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_load_dwordx8 s[16:23], s[2:3], 0x0
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 1, v0
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v8
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v8
+; GFX8-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v9
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v9
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s16
-; GFX8-NEXT: v_mov_b32_e32 v2, s17
-; GFX8-NEXT: v_mov_b32_e32 v3, s18
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: v_mov_b32_e32 v4, s19
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v5, s20
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[2:3]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 4, v8
-; GFX8-NEXT: v_mov_b32_e32 v6, s21
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[14:15]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v8
-; GFX8-NEXT: v_mov_b32_e32 v7, s22
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[6:7]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v8
+; GFX8-NEXT: v_mov_b32_e32 v1, s8
+; GFX8-NEXT: v_mov_b32_e32 v2, s9
+; GFX8-NEXT: v_mov_b32_e32 v3, s10
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v1, v2, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, s11
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v3, s[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v5, s12
+; GFX8-NEXT: v_mov_b32_e32 v6, s13
+; GFX8-NEXT: v_mov_b32_e32 v7, s14
+; GFX8-NEXT: v_mov_b32_e32 v8, s15
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v4, s[2:3]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 4, v9
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v5, s[14:15]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v9
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v6, s[6:7]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v9
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX8-NEXT: v_mov_b32_e32 v9, s23
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[8:9]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v8
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v7, s[8:9]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v9
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX8-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX8-NEXT: v_mov_b32_e32 v3, 0xffff
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[10:11]
-; GFX8-NEXT: v_lshlrev_b32_e64 v2, v0, s4
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v3
-; GFX8-NEXT: v_bfi_b32 v0, v0, 0, v1
-; GFX8-NEXT: v_or_b32_e32 v9, v0, v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s16
-; GFX8-NEXT: v_mov_b32_e32 v1, s17
-; GFX8-NEXT: v_mov_b32_e32 v2, s18
-; GFX8-NEXT: v_mov_b32_e32 v3, s19
-; GFX8-NEXT: v_mov_b32_e32 v4, s20
-; GFX8-NEXT: v_mov_b32_e32 v5, s21
-; GFX8-NEXT: v_mov_b32_e32 v6, s22
-; GFX8-NEXT: v_mov_b32_e32 v7, s23
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v8
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[2:3]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v9, s[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[10:11]
+; GFX8-NEXT: v_mov_b32_e32 v12, 0xffff
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v8, s[10:11]
+; GFX8-NEXT: v_lshlrev_b32_e64 v11, v0, s4
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v12
+; GFX8-NEXT: v_bfi_b32 v0, v0, 0, v10
+; GFX8-NEXT: v_or_b32_e32 v10, v0, v11
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v9
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, v10, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v10, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, v10, s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v5, v10, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v6, v10, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v7, v10, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[10:11]
; GFX8-NEXT: v_mov_b32_e32 v8, 0
; GFX8-NEXT: v_mov_b32_e32 v9, 0
; GFX8-NEXT: v_mov_b32_e32 v10, 16
@@ -3627,58 +3261,50 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
;
; GFX7-LABEL: insertelement_s_v16i16_s_v:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_load_dwordx8 s[16:23], s[2:3], 0x0
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 1, v0
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v8
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v8
+; GFX7-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
+; GFX7-NEXT: v_lshrrev_b32_e32 v9, 1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v9
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v9
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v1, s16
-; GFX7-NEXT: v_mov_b32_e32 v2, s17
-; GFX7-NEXT: v_mov_b32_e32 v3, s18
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX7-NEXT: v_mov_b32_e32 v4, s19
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v5, s20
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[2:3]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[14:15], 4, v8
-; GFX7-NEXT: v_mov_b32_e32 v6, s21
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[14:15]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v8
-; GFX7-NEXT: v_mov_b32_e32 v7, s22
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[6:7]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v8
+; GFX7-NEXT: v_mov_b32_e32 v1, s8
+; GFX7-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-NEXT: v_mov_b32_e32 v3, s10
+; GFX7-NEXT: v_cndmask_b32_e32 v10, v1, v2, vcc
+; GFX7-NEXT: v_mov_b32_e32 v4, s11
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v3, s[0:1]
+; GFX7-NEXT: v_mov_b32_e32 v5, s12
+; GFX7-NEXT: v_mov_b32_e32 v6, s13
+; GFX7-NEXT: v_mov_b32_e32 v7, s14
+; GFX7-NEXT: v_mov_b32_e32 v8, s15
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v4, s[2:3]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[14:15], 4, v9
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v5, s[14:15]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v9
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v6, s[6:7]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v9
; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX7-NEXT: v_mov_b32_e32 v9, s23
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[8:9]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v8
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v7, s[8:9]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v9
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX7-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[10:11]
-; GFX7-NEXT: v_lshl_b32_e32 v2, s4, v0
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v8, s[10:11]
+; GFX7-NEXT: v_lshl_b32_e32 v11, s4, v0
; GFX7-NEXT: v_lshl_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_bfi_b32 v0, v0, 0, v1
-; GFX7-NEXT: v_or_b32_e32 v9, v0, v2
-; GFX7-NEXT: v_mov_b32_e32 v0, s16
-; GFX7-NEXT: v_mov_b32_e32 v1, s17
-; GFX7-NEXT: v_mov_b32_e32 v2, s18
-; GFX7-NEXT: v_mov_b32_e32 v3, s19
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v8
-; GFX7-NEXT: v_mov_b32_e32 v4, s20
-; GFX7-NEXT: v_mov_b32_e32 v5, s21
-; GFX7-NEXT: v_mov_b32_e32 v6, s22
-; GFX7-NEXT: v_mov_b32_e32 v7, s23
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[2:3]
+; GFX7-NEXT: v_bfi_b32 v0, v0, 0, v10
+; GFX7-NEXT: v_or_b32_e32 v10, v0, v11
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v9
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v1, v10, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v3, v10, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v4, v10, s[2:3]
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v9, s[14:15]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v5, v10, s[14:15]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v6, v10, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v7, v10, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[10:11]
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_mov_b64 s[0:1], 16
; GFX7-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
@@ -3687,106 +3313,105 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
; GFX10-LABEL: insertelement_s_v16i16_s_v:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v13, 1, v0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: s_and_b32 s5, s4, 0xffff
-; GFX10-NEXT: v_mov_b32_e32 v11, 0
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v12
+; GFX10-NEXT: v_mov_b32_e32 v11, 16
+; GFX10-NEXT: v_mov_b32_e32 v12, 0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v13
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v13
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v13
+; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v13
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v12
-; GFX10-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff
-; GFX10-NEXT: v_lshlrev_b32_e64 v8, v0, s5
-; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v12
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v13
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v13
+; GFX10-NEXT: v_lshlrev_b32_e64 v10, v0, 0xffff
+; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, s5
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v13
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, s9
-; GFX10-NEXT: v_not_b32_e32 v9, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s10, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s11, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s12, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s13, s3
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s14, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v1, s15, s5
-; GFX10-NEXT: v_mov_b32_e32 v0, s8
-; GFX10-NEXT: v_mov_b32_e32 v1, s9
-; GFX10-NEXT: v_mov_b32_e32 v2, s10
-; GFX10-NEXT: v_mov_b32_e32 v3, s11
-; GFX10-NEXT: v_and_or_b32 v13, v10, v9, v8
-; GFX10-NEXT: v_mov_b32_e32 v4, s12
-; GFX10-NEXT: v_mov_b32_e32 v5, s13
-; GFX10-NEXT: v_mov_b32_e32 v6, s14
-; GFX10-NEXT: v_mov_b32_e32 v7, s15
-; GFX10-NEXT: v_mov_b32_e32 v8, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, s8
+; GFX10-NEXT: v_mov_b32_e32 v2, s9
+; GFX10-NEXT: v_mov_b32_e32 v3, s10
+; GFX10-NEXT: v_mov_b32_e32 v4, s11
+; GFX10-NEXT: v_mov_b32_e32 v5, s12
+; GFX10-NEXT: v_mov_b32_e32 v6, s13
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v2, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v7, s14
+; GFX10-NEXT: v_mov_b32_e32 v8, s15
+; GFX10-NEXT: v_not_b32_e32 v10, v10
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v3, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v4, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v5, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v6, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v7, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v8, s5
+; GFX10-NEXT: v_and_or_b32 v14, v9, v10, v0
; GFX10-NEXT: v_mov_b32_e32 v9, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v13, s6
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v13, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v13, s1
-; GFX10-NEXT: v_mov_b32_e32 v10, 16
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v13, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v13, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v13, s5
-; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
-; GFX10-NEXT: global_store_dwordx4 v[10:11], v[4:7], off
+; GFX10-NEXT: v_mov_b32_e32 v10, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, v14, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, v14, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, v14, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, v14, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, v14, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, v14, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v8, v14, s5
+; GFX10-NEXT: global_store_dwordx4 v[9:10], v[0:3], off
+; GFX10-NEXT: global_store_dwordx4 v[11:12], v[4:7], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v16i16_s_v:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0
-; GFX11-NEXT: v_lshrrev_b32_e32 v12, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v13, 1, v0
; GFX11-NEXT: s_and_b32 s5, s4, 0xffff
-; GFX11-NEXT: v_dual_mov_b32 v11, 0 :: v_dual_and_b32 v0, 1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v12
+; GFX11-NEXT: v_dual_mov_b32 v11, 16 :: v_dual_and_b32 v0, 1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v13
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v13
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v13
+; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v13
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v12
-; GFX11-NEXT: v_lshlrev_b32_e64 v2, v0, 0xffff
-; GFX11-NEXT: v_lshlrev_b32_e64 v8, v0, s5
-; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v12
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_not_b32_e32 v9, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v13
+; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b32_e64 v10, v0, 0xffff
+; GFX11-NEXT: v_lshlrev_b32_e64 v0, v0, s5
+; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v13
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v1, s9
-; GFX11-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
+; GFX11-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v2, s9
+; GFX11-NEXT: v_dual_mov_b32 v3, s10 :: v_dual_mov_b32 v4, s11
+; GFX11-NEXT: v_dual_mov_b32 v5, s12 :: v_dual_mov_b32 v6, s13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v2, vcc_lo
+; GFX11-NEXT: v_dual_mov_b32 v7, s14 :: v_dual_mov_b32 v8, s15
+; GFX11-NEXT: v_not_b32_e32 v10, v10
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v3, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s10, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s11, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v4, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v5, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s12, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s13, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v6, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v7, s4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s14, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v1, s15, s5
-; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX11-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_and_or_b32 v13, v10, v9, v8
-; GFX11-NEXT: v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13
-; GFX11-NEXT: v_dual_mov_b32 v6, s14 :: v_dual_mov_b32 v7, s15
-; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v13, s6
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v13, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v13, s1
-; GFX11-NEXT: v_mov_b32_e32 v10, 16
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v13, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v13, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v13, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v8, s5
+; GFX11-NEXT: v_and_or_b32 v14, v9, v10, v0
+; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0
+; GFX11-NEXT: v_mov_b32_e32 v12, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, v14, s6
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v14, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, v14, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, v14, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v5, v14, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v14, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v7, v14, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v8, v14, s5
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off
-; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off
+; GFX11-NEXT: global_store_b128 v[9:10], v[0:3], off
+; GFX11-NEXT: global_store_b128 v[11:12], v[4:7], off
; GFX11-NEXT: s_endpgm
%vec = load <16 x i16>, ptr addrspace(4) %ptr
%insert = insertelement <16 x i16> %vec, i16 %val, i32 %idx
@@ -3797,55 +3422,47 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i
define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i16 %val, i32 %idx) {
; GFX9-LABEL: insertelement_s_v16i16_v_v:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx8 s[12:19], s[2:3], 0x0
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 1, v1
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v8
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v8
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v2, s12
-; GFX9-NEXT: v_mov_b32_e32 v3, s13
-; GFX9-NEXT: v_mov_b32_e32 v4, s14
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v5, s15
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v6, s16
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[2:3]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v8
-; GFX9-NEXT: v_mov_b32_e32 v7, s17
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[4:5]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v8
+; GFX9-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x0
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 1, v1
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_mov_b32_e32 v9, s18
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v7, s[6:7]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v8
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v9, s7
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v8, s6
+; GFX9-NEXT: v_mov_b32_e32 v7, s5
+; GFX9-NEXT: v_mov_b32_e32 v6, s4
+; GFX9-NEXT: v_mov_b32_e32 v5, s3
+; GFX9-NEXT: v_mov_b32_e32 v4, s2
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v2, v3, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v4, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v5, s[2:3]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v6, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v7, s[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xffff
-; GFX9-NEXT: v_mov_b32_e32 v10, s19
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[8:9]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v8
+; GFX9-NEXT: v_mov_b32_e32 v12, 0xffff
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v8, s[8:9]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v10
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[10:11]
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v12
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v9, s[10:11]
; GFX9-NEXT: v_not_b32_e32 v1, v1
-; GFX9-NEXT: v_and_or_b32 v9, v2, v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s12
-; GFX9-NEXT: v_mov_b32_e32 v1, s13
-; GFX9-NEXT: v_mov_b32_e32 v2, s14
-; GFX9-NEXT: v_mov_b32_e32 v3, s15
-; GFX9-NEXT: v_mov_b32_e32 v4, s16
-; GFX9-NEXT: v_mov_b32_e32 v5, s17
-; GFX9-NEXT: v_mov_b32_e32 v6, s18
-; GFX9-NEXT: v_mov_b32_e32 v7, s19
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v8
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[12:13]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[2:3]
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v9, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[10:11]
+; GFX9-NEXT: v_and_or_b32 v11, v11, v1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v11, s[12:13]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v11, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v11, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v11, s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v6, v11, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v11, s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v11, s[10:11]
; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mov_b32_e32 v9, 0
; GFX9-NEXT: v_mov_b32_e32 v10, 16
@@ -3856,55 +3473,47 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
;
; GFX8-LABEL: insertelement_s_v16i16_v_v:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_load_dwordx8 s[12:19], s[2:3], 0x0
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 1, v1
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v8
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, s12
-; GFX8-NEXT: v_mov_b32_e32 v3, s13
-; GFX8-NEXT: v_mov_b32_e32 v4, s14
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX8-NEXT: v_mov_b32_e32 v5, s15
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v6, s16
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[2:3]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v8
-; GFX8-NEXT: v_mov_b32_e32 v7, s17
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[4:5]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v8
-; GFX8-NEXT: v_mov_b32_e32 v9, s18
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v7, s[6:7]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v8
+; GFX8-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x0
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 1, v1
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX8-NEXT: v_mov_b32_e32 v10, s19
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[8:9]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v8
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v9, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v8, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v2, v3, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v10
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v4, s[0:1]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v10
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v5, s[2:3]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v10
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v6, s[4:5]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v10
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v7, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v8, s[8:9]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v10
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX8-NEXT: v_mov_b32_e32 v3, 0xffff
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[10:11]
+; GFX8-NEXT: v_mov_b32_e32 v12, 0xffff
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v9, s[10:11]
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_bfi_b32 v1, v1, 0, v2
-; GFX8-NEXT: v_or_b32_e32 v9, v1, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s12
-; GFX8-NEXT: v_mov_b32_e32 v1, s13
-; GFX8-NEXT: v_mov_b32_e32 v2, s14
-; GFX8-NEXT: v_mov_b32_e32 v3, s15
-; GFX8-NEXT: v_mov_b32_e32 v4, s16
-; GFX8-NEXT: v_mov_b32_e32 v5, s17
-; GFX8-NEXT: v_mov_b32_e32 v6, s18
-; GFX8-NEXT: v_mov_b32_e32 v7, s19
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v8
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[2:3]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v9, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[8:9]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[10:11]
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v12
+; GFX8-NEXT: v_bfi_b32 v1, v1, 0, v11
+; GFX8-NEXT: v_or_b32_e32 v11, v1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v10
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v11, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v11, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, v11, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v11, s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v6, v11, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, v11, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v9, v11, s[10:11]
; GFX8-NEXT: v_mov_b32_e32 v8, 0
; GFX8-NEXT: v_mov_b32_e32 v9, 0
; GFX8-NEXT: v_mov_b32_e32 v10, 16
@@ -3915,58 +3524,50 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
;
; GFX7-LABEL: insertelement_s_v16i16_v_v:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_load_dwordx8 s[12:19], s[2:3], 0x0
-; GFX7-NEXT: v_lshrrev_b32_e32 v8, 1, v1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v8
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v2, s12
-; GFX7-NEXT: v_mov_b32_e32 v3, s13
-; GFX7-NEXT: v_mov_b32_e32 v4, s14
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX7-NEXT: v_mov_b32_e32 v5, s15
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v6, s16
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[2:3]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v8
-; GFX7-NEXT: v_mov_b32_e32 v7, s17
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[4:5]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v8
-; GFX7-NEXT: v_mov_b32_e32 v9, s18
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v7, s[6:7]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v8
+; GFX7-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x0
+; GFX7-NEXT: v_lshrrev_b32_e32 v10, 1, v1
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v10
; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX7-NEXT: v_mov_b32_e32 v10, s19
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[8:9]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v8
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v9, s7
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-NEXT: v_mov_b32_e32 v8, s6
+; GFX7-NEXT: v_mov_b32_e32 v7, s5
+; GFX7-NEXT: v_mov_b32_e32 v6, s4
+; GFX7-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-NEXT: v_cndmask_b32_e32 v11, v2, v3, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v10
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v4, s[0:1]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v10
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v5, s[2:3]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v10
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v6, s[4:5]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v10
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v7, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v8, s[8:9]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v10
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v9, s[10:11]
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xffff, v1
-; GFX7-NEXT: v_bfi_b32 v1, v1, 0, v2
-; GFX7-NEXT: v_or_b32_e32 v9, v1, v0
-; GFX7-NEXT: v_mov_b32_e32 v0, s12
-; GFX7-NEXT: v_mov_b32_e32 v1, s13
-; GFX7-NEXT: v_mov_b32_e32 v2, s14
-; GFX7-NEXT: v_mov_b32_e32 v3, s15
-; GFX7-NEXT: v_mov_b32_e32 v4, s16
-; GFX7-NEXT: v_mov_b32_e32 v5, s17
-; GFX7-NEXT: v_mov_b32_e32 v6, s18
-; GFX7-NEXT: v_mov_b32_e32 v7, s19
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v8
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[12:13]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[2:3]
+; GFX7-NEXT: v_bfi_b32 v1, v1, 0, v11
+; GFX7-NEXT: v_or_b32_e32 v11, v1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v10
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, v11, s[12:13]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v11, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, v11, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v11, s[2:3]
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v9, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[6:7]
-; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[8:9]
-; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[10:11]
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v6, v11, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v7, v11, s[6:7]
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v8, v11, s[8:9]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v9, v11, s[10:11]
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_mov_b64 s[0:1], 16
; GFX7-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
@@ -3974,109 +3575,106 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i
;
; GFX10-LABEL: insertelement_s_v16i16_v_v:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 1, v1
+; GFX10-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x0
+; GFX10-NEXT: v_lshrrev_b32_e32 v14, 1, v1
; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX10-NEXT: v_mov_b32_e32 v11, 0
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v12
-; GFX10-NEXT: s_mov_b32 null, 0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v12
+; GFX10-NEXT: v_mov_b32_e32 v12, 16
+; GFX10-NEXT: v_mov_b32_e32 v13, 0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v12
-; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v12
-; GFX10-NEXT: v_lshlrev_b32_e64 v3, v1, 0xffff
-; GFX10-NEXT: v_lshlrev_b32_sdwa v8, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX10-NEXT: v_lshlrev_b32_e64 v11, v1, 0xffff
+; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX10-NEXT: v_not_b32_e32 v1, v11
+; GFX10-NEXT: v_mov_b32_e32 v11, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v2, s9
-; GFX10-NEXT: v_not_b32_e32 v9, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v2, s8, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s10, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s11, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s12, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s13, s3
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s14, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v2, s15, s5
-; GFX10-NEXT: v_mov_b32_e32 v0, s8
-; GFX10-NEXT: v_mov_b32_e32 v1, s9
-; GFX10-NEXT: v_mov_b32_e32 v2, s10
-; GFX10-NEXT: v_mov_b32_e32 v3, s11
-; GFX10-NEXT: v_and_or_b32 v13, v10, v9, v8
-; GFX10-NEXT: v_mov_b32_e32 v4, s12
-; GFX10-NEXT: v_mov_b32_e32 v5, s13
-; GFX10-NEXT: v_mov_b32_e32 v6, s14
-; GFX10-NEXT: v_mov_b32_e32 v7, s15
-; GFX10-NEXT: v_mov_b32_e32 v8, 0
-; GFX10-NEXT: v_mov_b32_e32 v9, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v13, s6
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v13, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v13, s1
-; GFX10-NEXT: v_mov_b32_e32 v10, 16
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v13, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v13, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v13, s5
-; GFX10-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
-; GFX10-NEXT: global_store_dwordx4 v[10:11], v[4:7], off
+; GFX10-NEXT: v_mov_b32_e32 v9, s7
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v8, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s2
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v2, v3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v14
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v14
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v14
+; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v14
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v14
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v4, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v14
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v14
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v5, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v6, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v7, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v8, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v9, s5
+; GFX10-NEXT: v_and_or_b32 v15, v10, v1, v0
+; GFX10-NEXT: v_mov_b32_e32 v10, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v15, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v15, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v15, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v15, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v15, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v7, v15, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v8, v15, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, v15, s5
+; GFX10-NEXT: global_store_dwordx4 v[10:11], v[0:3], off
+; GFX10-NEXT: global_store_dwordx4 v[12:13], v[4:7], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v16i16_v_v:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0
-; GFX11-NEXT: v_lshrrev_b32_e32 v12, 1, v1
+; GFX11-NEXT: s_load_b256 s[0:7], s[2:3], 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v14, 1, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-NEXT: v_mov_b32_e32 v11, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v12
+; GFX11-NEXT: v_mov_b32_e32 v13, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 4, v1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v12
-; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v12
-; GFX11-NEXT: v_lshlrev_b32_e64 v3, v1, 0xffff
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, v1, v0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v12
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_not_b32_e32 v9, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e64 v11, v1, 0xffff
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, v1, v0
+; GFX11-NEXT: v_not_b32_e32 v1, v11
+; GFX11-NEXT: v_mov_b32_e32 v11, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v2, s9
-; GFX11-NEXT: v_cndmask_b32_e32 v2, s8, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s10, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s11, s1
+; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
+; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v2, v3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v14
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v14
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v14
+; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v14
+; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v14
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v4, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v14
+; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v5, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v6, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s12, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s13, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v7, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v8, s4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s14, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v2, s15, s5
-; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v5, s13
-; GFX11-NEXT: v_dual_mov_b32 v1, s9 :: v_dual_mov_b32 v2, s10
-; GFX11-NEXT: v_mov_b32_e32 v7, s15
-; GFX11-NEXT: v_mov_b32_e32 v3, s11
-; GFX11-NEXT: v_and_or_b32 v13, v10, v9, v8
-; GFX11-NEXT: v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v9, 0
-; GFX11-NEXT: v_mov_b32_e32 v6, s14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_cndmask_b32 v1, v1, v13
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v13, s6
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v13, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v13, s1
-; GFX11-NEXT: v_mov_b32_e32 v10, 16
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v13, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v13, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v13, s4
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v13, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v9, s5
+; GFX11-NEXT: v_and_or_b32 v15, v10, v1, v0
+; GFX11-NEXT: v_mov_b32_e32 v10, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v12, 16 :: v_dual_cndmask_b32 v1, v3, v15
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v15, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v15, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, v15, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v6, v15, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v7, v15, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v8, v15, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, v15, s5
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off
-; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off
+; GFX11-NEXT: global_store_b128 v[10:11], v[0:3], off
+; GFX11-NEXT: global_store_b128 v[12:13], v[4:7], off
; GFX11-NEXT: s_endpgm
%vec = load <16 x i16>, ptr addrspace(4) %ptr
%insert = insertelement <16 x i16> %vec, i16 %val, i32 %idx
@@ -4333,44 +3931,26 @@ define amdgpu_ps void @insertelement_v_v16i16_v_s(ptr addrspace(1) %ptr, i16 %va
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
; GFX9-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16
-; GFX9-NEXT: s_and_b32 s0, s2, 1
-; GFX9-NEXT: s_lshr_b32 s12, s2, 1
-; GFX9-NEXT: s_lshl_b32 s0, s0, 4
-; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX9-NEXT: s_lshl_b32 s0, 0xffff, s0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s12, 1
-; GFX9-NEXT: s_not_b32 s13, s0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s12, 2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s12, 3
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 4
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], s12, 5
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], s12, 6
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], s12, 7
-; GFX9-NEXT: v_mov_b32_e32 v11, 0
+; GFX9-NEXT: s_and_b32 s1, s2, 1
+; GFX9-NEXT: s_lshl_b32 s1, s1, 4
+; GFX9-NEXT: s_lshr_b32 s0, s2, 1
+; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX9-NEXT: s_lshl_b32 s1, 0xffff, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_not_b32 s1, s1
+; GFX9-NEXT: v_mov_b32_e32 v11, 16
; GFX9-NEXT: v_mov_b32_e32 v12, 0
-; GFX9-NEXT: v_mov_b32_e32 v13, 16
-; GFX9-NEXT: v_mov_b32_e32 v14, 0
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v10, s[10:11]
-; GFX9-NEXT: v_and_or_b32 v15, v1, s13, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], s12, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v15, s[12:13]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v15, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v15, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v15, s[2:3]
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v15, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, v15, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v9, v15, s[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v10, v15, s[10:11]
-; GFX9-NEXT: global_store_dwordx4 v[11:12], v[0:3], off
-; GFX9-NEXT: global_store_dwordx4 v[13:14], v[4:7], off
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
+; GFX9-NEXT: v_mov_b32_e32 v13, v3
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_or_b32 v2, v13, s1, v2
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v3, v2
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
+; GFX9-NEXT: global_store_dwordx4 v[11:12], v[7:10], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v16i16_v_s:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
index 56401c25f55ae..30d6c871115e7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
@@ -1,27 +1,27 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11 %s
define amdgpu_ps void @insertelement_s_v2i8_s_s(ptr addrspace(4) inreg %ptr, i8 inreg %val, i32 inreg %idx) {
; GFX9-LABEL: insertelement_s_v2i8_s_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_load_ushort v0, v0, s[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v1, s4
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
+; GFX9-NEXT: s_mov_b32 m0, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: s_lshr_b32 s1, s0, 8
+; GFX9-NEXT: s_movreld_b32 s0, s4
+; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_and_b32 s0, s0, 0xff
+; GFX9-NEXT: s_lshl_b32 s1, s1, 8
+; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: global_store_short v[0:1], v2, off
; GFX9-NEXT: s_endpgm
;
@@ -30,18 +30,18 @@ define amdgpu_ps void @insertelement_s_v2i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s4
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
+; GFX8-NEXT: s_mov_b32 m0, s5
+; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 8, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: s_lshr_b32 s1, s0, 8
+; GFX8-NEXT: s_movreld_b32 s0, s4
+; GFX8-NEXT: s_and_b32 s1, s1, 0xff
+; GFX8-NEXT: s_and_b32 s0, s0, 0xff
+; GFX8-NEXT: s_lshl_b32 s1, s1, 8
+; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: v_mov_b32_e32 v0, 0
-; GFX8-NEXT: v_mov_b32_e32 v1, 0
-; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
;
@@ -52,57 +52,55 @@ define amdgpu_ps void @insertelement_s_v2i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0
-; GFX7-NEXT: v_mov_b32_e32 v1, s4
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
+; GFX7-NEXT: s_mov_b32 m0, s5
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 8, v0
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_readfirstlane_b32 s6, v0
+; GFX7-NEXT: s_lshr_b32 s7, s6, 8
+; GFX7-NEXT: s_movreld_b32 s6, s4
+; GFX7-NEXT: s_and_b32 s5, s7, 0xff
+; GFX7-NEXT: s_and_b32 s4, s6, 0xff
+; GFX7-NEXT: s_lshl_b32 s5, s5, 8
+; GFX7-NEXT: s_or_b32 s4, s4, s5
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_s_v2i8_s_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s5, 1
-; GFX10-NEXT: v_mov_b32_e32 v2, 0xff
+; GFX10-NEXT: s_mov_b32 m0, s5
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_load_ushort v0, v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s5, 0
-; GFX10-NEXT: v_and_b32_sdwa v2, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v0, s4, s0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: s_lshr_b32 s1, s0, 8
+; GFX10-NEXT: s_movreld_b32 s0, s4
+; GFX10-NEXT: s_and_b32 s1, s1, 0xff
+; GFX10-NEXT: s_and_b32 s0, s0, 0xff
+; GFX10-NEXT: s_lshl_b32 s1, s1, 8
+; GFX10-NEXT: s_or_b32 s0, s0, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v2i8_s_s:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s5, 1
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: s_mov_b32 m0, s5
; GFX11-NEXT: global_load_u16 v0, v0, s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s5, 0
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s4, s0
-; GFX11-NEXT: v_lshlrev_b16 v3, 8, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0xff, v0
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-NEXT: s_lshr_b32 s1, s0, 8
+; GFX11-NEXT: s_movreld_b32 s0, s4
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
%vec = load <2 x i8>, ptr addrspace(4) %ptr
@@ -115,37 +113,34 @@ define amdgpu_ps void @insertelement_v_v2i8_s_s(ptr addrspace(1) %ptr, i8 inreg
; GFX9-LABEL: insertelement_v_v2i8_s_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_ushort v0, v[0:1], off
-; GFX9-NEXT: v_mov_b32_e32 v1, s2
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s3, 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX9-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v2
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: global_store_short v[0:1], v2, off
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: global_store_short v[1:2], v0, off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v2i8_s_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s2
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
+; GFX8-NEXT: s_mov_b32 m0, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 8, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s3, 1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX8-NEXT: v_movreld_b32_e32 v0, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 0
-; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: flat_store_short v[0:1], v2
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: flat_store_short v[1:2], v0
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_v_v2i8_s_s:
@@ -154,15 +149,13 @@ define amdgpu_ps void @insertelement_v_v2i8_s_s(ptr addrspace(1) %ptr, i8 inreg
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: v_mov_b32_e32 v1, s2
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
+; GFX7-NEXT: s_mov_b32 m0, s3
+; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 8, v0
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s3, 1
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX7-NEXT: v_movreld_b32_e32 v0, v2
; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
@@ -173,37 +166,32 @@ define amdgpu_ps void @insertelement_v_v2i8_s_s(ptr addrspace(1) %ptr, i8 inreg
; GFX10-LABEL: insertelement_v_v2i8_s_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_ushort v0, v[0:1], off
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, 1
; GFX10-NEXT: v_mov_b32_e32 v2, 0xff
+; GFX10-NEXT: s_mov_b32 m0, s3
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s2, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, 0
-; GFX10-NEXT: v_and_b32_sdwa v2, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v0, s2, s0
-; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_movreld_b32_e32 v0, s2
+; GFX10-NEXT: v_and_b32_sdwa v3, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: global_store_short v[0:1], v2, off
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: global_store_short v[1:2], v0, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_v_v2i8_s_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_u16 v0, v[0:1], off
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s3, 1
+; GFX11-NEXT: s_mov_b32 m0, s3
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s2, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s3, 0
+; GFX11-NEXT: v_movreld_b32_e32 v0, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, s0
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b16 v3, 8, v1
; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
@@ -218,18 +206,20 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_load_ushort v1, v1, s[2:3]
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: global_store_short v[0:1], v2, off
+; GFX9-NEXT: v_readfirstlane_b32 s0, v1
+; GFX9-NEXT: s_lshr_b32 s1, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: s_set_gpr_idx_on s4, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v1, v0
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v2
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: global_store_short v[2:3], v0, off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v2i8_v_s:
@@ -237,18 +227,19 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX8-NEXT: v_mov_b32_e32 v1, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NEXT: flat_load_ushort v1, v[1:2]
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0
+; GFX8-NEXT: s_mov_b32 m0, s4
+; GFX8-NEXT: v_mov_b32_e32 v3, 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, 0
-; GFX8-NEXT: v_mov_b32_e32 v1, 0
-; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: flat_store_short v[0:1], v2
+; GFX8-NEXT: v_readfirstlane_b32 s0, v1
+; GFX8-NEXT: s_lshr_b32 s1, s0, 8
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_movreld_b32_e32 v1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: flat_store_short v[2:3], v0
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v2i8_v_s:
@@ -258,53 +249,57 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_ushort v1, off, s[0:3], 0
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0
+; GFX7-NEXT: s_mov_b32 m0, s4
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX7-NEXT: v_readfirstlane_b32 s4, v1
+; GFX7-NEXT: s_lshr_b32 s5, s4, 8
+; GFX7-NEXT: v_mov_b32_e32 v1, s4
+; GFX7-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-NEXT: v_movreld_b32_e32 v1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v1
+; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_s_v2i8_v_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s4, 1
-; GFX10-NEXT: v_mov_b32_e32 v3, 0xff
+; GFX10-NEXT: s_mov_b32 m0, s4
+; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: global_load_ushort v1, v1, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s4, 0
-; GFX10-NEXT: v_and_b32_sdwa v2, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: global_store_short v[0:1], v2, off
+; GFX10-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10-NEXT: s_lshr_b32 s1, s0, 8
+; GFX10-NEXT: v_mov_b32_e32 v2, s1
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_movreld_b32_e32 v1, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, 0xff
+; GFX10-NEXT: v_and_b32_sdwa v0, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v2i8_v_s:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s4, 1
; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_mov_b32 m0, s4
; GFX11-NEXT: global_load_u16 v1, v1, s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s4, 0
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_and_b32 v1, 0xff, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v0
-; GFX11-NEXT: v_lshlrev_b16 v3, 8, v1
-; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: s_lshr_b32 s1, s0, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: v_movreld_b32_e32 v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v1
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_lshlrev_b16 v3, 8, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
@@ -323,7 +318,10 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v1
+; GFX9-NEXT: s_lshr_b32 s1, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
@@ -343,7 +341,10 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v1
+; GFX8-NEXT: s_lshr_b32 s1, s0, 8
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
@@ -366,7 +367,10 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX7-NEXT: v_readfirstlane_b32 s4, v1
+; GFX7-NEXT: s_lshr_b32 s5, s4, 8
+; GFX7-NEXT: v_mov_b32_e32 v1, s4
+; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
@@ -384,14 +388,17 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX10-NEXT: v_mov_b32_e32 v3, 0xff
; GFX10-NEXT: global_load_ushort v1, v1, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s4, vcc_lo
+; GFX10-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10-NEXT: s_lshr_b32 s1, s0, 8
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: v_and_b32_sdwa v2, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v1, s4, vcc_lo
+; GFX10-NEXT: v_and_b32_sdwa v3, v1, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s4, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_endpgm
;
@@ -401,13 +408,16 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: global_load_u16 v1, v1, s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s4, vcc_lo
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: s_lshr_b32 s1, s0, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s4, vcc_lo
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, s4, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: v_lshlrev_b16 v3, 8, v1
@@ -429,7 +439,10 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX9-NEXT: global_load_ushort v2, v2, s[2:3]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v2
+; GFX9-NEXT: s_lshr_b32 s1, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
@@ -448,7 +461,10 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX8-NEXT: flat_load_ushort v2, v[2:3]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 8, v2
+; GFX8-NEXT: v_readfirstlane_b32 s0, v2
+; GFX8-NEXT: s_lshr_b32 s1, s0, 8
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
@@ -470,7 +486,10 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 8, v2
+; GFX7-NEXT: v_readfirstlane_b32 s4, v2
+; GFX7-NEXT: s_lshr_b32 s5, s4, 8
+; GFX7-NEXT: v_mov_b32_e32 v2, s4
+; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
@@ -485,35 +504,39 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX10-NEXT: v_mov_b32_e32 v4, 0xff
+; GFX10-NEXT: v_mov_b32_e32 v3, 0xff
; GFX10-NEXT: global_load_ushort v2, v2, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
+; GFX10-NEXT: v_readfirstlane_b32 s0, v2
+; GFX10-NEXT: s_lshr_b32 s1, s0, 8
+; GFX10-NEXT: v_cndmask_b32_e32 v2, s1, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_and_b32_sdwa v3, v3, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
+; GFX10-NEXT: v_and_b32_sdwa v2, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_cndmask_b32_e32 v4, s0, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v2i8_v_v:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX11-NEXT: global_load_u16 v2, v2, s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: s_lshr_b32 s1, s0, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, s1, v0, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_and_b32 v1, 0xff, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b16 v3, 8, v1
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0xff, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v0, s0, v0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: v_lshlrev_b16 v3, 8, v1
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
@@ -630,88 +653,79 @@ define amdgpu_ps void @insertelement_v_v2i8_v_s(ptr addrspace(1) %ptr, i8 %val,
; GFX9-LABEL: insertelement_v_v2i8_v_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_ushort v0, v[0:1], off
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v0, v2, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
-; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v2
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: global_store_short v[0:1], v2, off
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: global_store_short v[1:2], v0, off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v2i8_v_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
+; GFX8-NEXT: s_mov_b32 m0, s2
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v0, v2, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
-; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-NEXT: v_movreld_b32_e32 v0, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 0
-; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: flat_store_short v[0:1], v2
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: flat_store_short v[1:2], v0
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_v_v2i8_v_s:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_mov_b32 s6, 0
-; GFX7-NEXT: s_mov_b32 s7, 0xf000
-; GFX7-NEXT: s_mov_b64 s[4:5], 0
-; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GFX7-NEXT: s_mov_b64 s[4:5], 0
-; GFX7-NEXT: s_mov_b32 s6, -1
+; GFX7-NEXT: s_mov_b32 m0, s2
+; GFX7-NEXT: s_mov_b32 s2, 0
+; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: s_mov_b64 s[0:1], 0
+; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64
+; GFX7-NEXT: s_mov_b64 s[0:1], 0
+; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_movreld_b32_e32 v0, v2
; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX7-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_v_v2i8_v_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_ushort v0, v[0:1], off
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; GFX10-NEXT: v_mov_b32_e32 v3, 0xff
+; GFX10-NEXT: s_mov_b32 m0, s2
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; GFX10-NEXT: v_and_b32_sdwa v3, v1, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_movreld_b32_e32 v0, v2
+; GFX10-NEXT: v_mov_b32_e32 v2, 0xff
+; GFX10-NEXT: v_and_b32_sdwa v3, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: global_store_short v[0:1], v2, off
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: global_store_short v[1:2], v0, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_v_v2i8_v_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_u16 v0, v[0:1], off
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
+; GFX11-NEXT: s_mov_b32 m0, s2
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX11-NEXT: v_movreld_b32_e32 v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v1, 0xff, v1
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: v_lshlrev_b16 v3, 8, v1
; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -1507,24 +1521,20 @@ define amdgpu_ps void @insertelement_s_v8i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX9-LABEL: insertelement_s_v8i8_s_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX9-NEXT: s_lshr_b32 s2, s5, 2
-; GFX9-NEXT: s_cmp_eq_u32 s2, 1
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_cselect_b32 s3, s1, s0
-; GFX9-NEXT: s_and_b32 s5, s5, 3
-; GFX9-NEXT: s_lshl_b32 s5, s5, 3
+; GFX9-NEXT: s_and_b32 s3, s5, 3
+; GFX9-NEXT: s_lshr_b32 m0, s5, 2
+; GFX9-NEXT: s_lshl_b32 s3, s3, 3
; GFX9-NEXT: s_and_b32 s4, s4, 0xff
-; GFX9-NEXT: s_lshl_b32 s4, s4, s5
-; GFX9-NEXT: s_lshl_b32 s5, 0xff, s5
-; GFX9-NEXT: s_andn2_b32 s3, s3, s5
-; GFX9-NEXT: s_or_b32 s3, s3, s4
-; GFX9-NEXT: s_cmp_eq_u32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s0, s3, s0
-; GFX9-NEXT: s_cmp_eq_u32 s2, 1
-; GFX9-NEXT: s_cselect_b32 s1, s3, s1
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_movrels_b32 s2, s0
+; GFX9-NEXT: s_lshl_b32 s4, s4, s3
+; GFX9-NEXT: s_lshl_b32 s3, 0xff, s3
+; GFX9-NEXT: s_andn2_b32 s2, s2, s3
+; GFX9-NEXT: s_or_b32 s2, s2, s4
+; GFX9-NEXT: s_movreld_b32 s0, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; GFX9-NEXT: s_endpgm
@@ -1532,46 +1542,38 @@ define amdgpu_ps void @insertelement_s_v8i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX8-LABEL: insertelement_s_v8i8_s_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX8-NEXT: s_lshr_b32 s2, s5, 2
-; GFX8-NEXT: s_cmp_eq_u32 s2, 1
-; GFX8-NEXT: v_mov_b32_e32 v0, 0
-; GFX8-NEXT: v_mov_b32_e32 v1, 0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_cselect_b32 s3, s1, s0
-; GFX8-NEXT: s_and_b32 s5, s5, 3
-; GFX8-NEXT: s_lshl_b32 s5, s5, 3
+; GFX8-NEXT: s_and_b32 s3, s5, 3
+; GFX8-NEXT: s_lshr_b32 m0, s5, 2
+; GFX8-NEXT: s_lshl_b32 s3, s3, 3
; GFX8-NEXT: s_and_b32 s4, s4, 0xff
-; GFX8-NEXT: s_lshl_b32 s4, s4, s5
-; GFX8-NEXT: s_lshl_b32 s5, 0xff, s5
-; GFX8-NEXT: s_andn2_b32 s3, s3, s5
-; GFX8-NEXT: s_or_b32 s3, s3, s4
-; GFX8-NEXT: s_cmp_eq_u32 s2, 0
-; GFX8-NEXT: s_cselect_b32 s0, s3, s0
-; GFX8-NEXT: s_cmp_eq_u32 s2, 1
-; GFX8-NEXT: s_cselect_b32 s1, s3, s1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_movrels_b32 s2, s0
+; GFX8-NEXT: s_lshl_b32 s4, s4, s3
+; GFX8-NEXT: s_lshl_b32 s3, 0xff, s3
+; GFX8-NEXT: s_andn2_b32 s2, s2, s3
+; GFX8-NEXT: s_or_b32 s2, s2, s4
+; GFX8-NEXT: s_movreld_b32 s0, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v8i8_s_s:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX7-NEXT: s_lshr_b32 s3, s5, 2
-; GFX7-NEXT: s_cmp_eq_u32 s3, 1
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_cselect_b32 s2, s1, s0
-; GFX7-NEXT: s_and_b32 s5, s5, 3
-; GFX7-NEXT: s_lshl_b32 s5, s5, 3
+; GFX7-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-NEXT: s_and_b32 s1, s5, 3
+; GFX7-NEXT: s_lshr_b32 m0, s5, 2
+; GFX7-NEXT: s_lshl_b32 s1, s1, 3
; GFX7-NEXT: s_and_b32 s4, s4, 0xff
-; GFX7-NEXT: s_lshl_b32 s4, s4, s5
-; GFX7-NEXT: s_lshl_b32 s5, 0xff, s5
-; GFX7-NEXT: s_andn2_b32 s2, s2, s5
-; GFX7-NEXT: s_or_b32 s4, s2, s4
-; GFX7-NEXT: s_cmp_eq_u32 s3, 0
-; GFX7-NEXT: s_cselect_b32 s2, s4, s0
-; GFX7-NEXT: s_cmp_eq_u32 s3, 1
-; GFX7-NEXT: s_cselect_b32 s3, s4, s1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_movrels_b32 s0, s2
+; GFX7-NEXT: s_lshl_b32 s4, s4, s1
+; GFX7-NEXT: s_lshl_b32 s1, 0xff, s1
+; GFX7-NEXT: s_andn2_b32 s0, s0, s1
+; GFX7-NEXT: s_or_b32 s0, s0, s4
+; GFX7-NEXT: s_movreld_b32 s2, s0
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: v_mov_b32_e32 v1, s3
@@ -1583,23 +1585,19 @@ define amdgpu_ps void @insertelement_s_v8i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX10-LABEL: insertelement_s_v8i8_s_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX10-NEXT: s_lshr_b32 s2, s5, 2
+; GFX10-NEXT: s_and_b32 s2, s5, 3
+; GFX10-NEXT: s_lshr_b32 m0, s5, 2
+; GFX10-NEXT: s_lshl_b32 s2, s2, 3
+; GFX10-NEXT: s_and_b32 s3, s4, 0xff
+; GFX10-NEXT: s_lshl_b32 s5, 0xff, s2
+; GFX10-NEXT: s_lshl_b32 s2, s3, s2
; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: s_cmp_eq_u32 s2, 1
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_cselect_b32 s3, s1, s0
-; GFX10-NEXT: s_and_b32 s5, s5, 3
-; GFX10-NEXT: s_and_b32 s4, s4, 0xff
-; GFX10-NEXT: s_lshl_b32 s5, s5, 3
-; GFX10-NEXT: s_lshl_b32 s6, 0xff, s5
-; GFX10-NEXT: s_lshl_b32 s4, s4, s5
-; GFX10-NEXT: s_andn2_b32 s3, s3, s6
-; GFX10-NEXT: s_or_b32 s3, s3, s4
-; GFX10-NEXT: s_cmp_eq_u32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s0, s3, s0
-; GFX10-NEXT: s_cmp_eq_u32 s2, 1
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
+; GFX10-NEXT: s_movrels_b32 s4, s0
+; GFX10-NEXT: s_andn2_b32 s3, s4, s5
+; GFX10-NEXT: s_or_b32 s2, s3, s2
+; GFX10-NEXT: s_movreld_b32 s0, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
@@ -1608,24 +1606,20 @@ define amdgpu_ps void @insertelement_s_v8i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX11-LABEL: insertelement_s_v8i8_s_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
-; GFX11-NEXT: s_lshr_b32 s2, s5, 2
+; GFX11-NEXT: s_and_b32 s2, s5, 3
+; GFX11-NEXT: s_lshr_b32 m0, s5, 2
+; GFX11-NEXT: s_lshl_b32 s2, s2, 3
+; GFX11-NEXT: s_and_b32 s3, s4, 0xff
+; GFX11-NEXT: s_lshl_b32 s5, 0xff, s2
+; GFX11-NEXT: s_lshl_b32 s2, s3, s2
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s2, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_cselect_b32 s3, s1, s0
-; GFX11-NEXT: s_and_b32 s5, s5, 3
-; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: s_lshl_b32 s5, s5, 3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b32 s6, 0xff, s5
-; GFX11-NEXT: s_lshl_b32 s4, s4, s5
-; GFX11-NEXT: s_and_not1_b32 s3, s3, s6
-; GFX11-NEXT: s_or_b32 s3, s3, s4
-; GFX11-NEXT: s_cmp_eq_u32 s2, 0
-; GFX11-NEXT: s_cselect_b32 s0, s3, s0
-; GFX11-NEXT: s_cmp_eq_u32 s2, 1
-; GFX11-NEXT: s_cselect_b32 s1, s3, s1
+; GFX11-NEXT: s_movrels_b32 s4, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_not1_b32 s3, s4, s5
+; GFX11-NEXT: s_or_b32 s2, s3, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_movreld_b32 s0, s2
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX11-NEXT: s_endpgm
@@ -1640,44 +1634,42 @@ define amdgpu_ps void @insertelement_v_v8i8_s_s(ptr addrspace(1) %ptr, i8 inreg
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_and_b32 s1, s3, 3
-; GFX9-NEXT: s_lshr_b32 s0, s3, 2
; GFX9-NEXT: s_and_b32 s2, s2, 0xff
; GFX9-NEXT: s_lshl_b32 s1, s1, 3
+; GFX9-NEXT: s_lshr_b32 s0, s3, 2
; GFX9-NEXT: s_lshl_b32 s2, s2, s1
; GFX9-NEXT: s_lshl_b32 s1, 0xff, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
; GFX9-NEXT: s_not_b32 s1, s1
-; GFX9-NEXT: v_mov_b32_e32 v4, s2
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
+; GFX9-NEXT: v_mov_b32_e32 v3, v0
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_or_b32 v4, v3, s1, v2
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
-; GFX9-NEXT: v_and_or_b32 v4, v5, s1, v4
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v8i8_s_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX8-NEXT: s_lshr_b32 s0, s3, 2
-; GFX8-NEXT: s_and_b32 s1, s3, 3
-; GFX8-NEXT: s_and_b32 s2, s2, 0xff
-; GFX8-NEXT: s_lshl_b32 s1, s1, 3
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
-; GFX8-NEXT: s_lshl_b32 s2, s2, s1
-; GFX8-NEXT: s_lshl_b32 s1, 0xff, s1
-; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: s_and_b32 s0, s3, 3
+; GFX8-NEXT: s_lshr_b32 m0, s3, 2
+; GFX8-NEXT: s_and_b32 s1, s2, 0xff
+; GFX8-NEXT: s_lshl_b32 s0, s0, 3
+; GFX8-NEXT: s_lshl_b32 s1, s1, s0
+; GFX8-NEXT: s_lshl_b32 s0, 0xff, s0
; GFX8-NEXT: v_mov_b32_e32 v3, 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
-; GFX8-NEXT: v_bfi_b32 v4, s1, 0, v4
-; GFX8-NEXT: v_or_b32_e32 v4, s2, v4
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX8-NEXT: v_movrels_b32_e32 v2, v0
+; GFX8-NEXT: v_bfi_b32 v2, s0, 0, v2
+; GFX8-NEXT: v_or_b32_e32 v4, s1, v2
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: v_movreld_b32_e32 v0, v4
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
;
@@ -1687,65 +1679,58 @@ define amdgpu_ps void @insertelement_v_v8i8_s_s(ptr addrspace(1) %ptr, i8 inreg
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_lshr_b32 s0, s3, 2
-; GFX7-NEXT: s_and_b32 s1, s3, 3
-; GFX7-NEXT: s_and_b32 s2, s2, 0xff
-; GFX7-NEXT: s_lshl_b32 s1, s1, 3
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
-; GFX7-NEXT: s_lshl_b32 s2, s2, s1
-; GFX7-NEXT: s_lshl_b32 s1, 0xff, s1
+; GFX7-NEXT: s_and_b32 s0, s3, 3
+; GFX7-NEXT: s_lshr_b32 m0, s3, 2
+; GFX7-NEXT: s_and_b32 s1, s2, 0xff
+; GFX7-NEXT: s_lshl_b32 s0, s0, 3
+; GFX7-NEXT: s_lshl_b32 s1, s1, s0
+; GFX7-NEXT: s_lshl_b32 s0, 0xff, s0
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
-; GFX7-NEXT: v_bfi_b32 v2, s1, 0, v2
-; GFX7-NEXT: v_or_b32_e32 v2, s2, v2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_movrels_b32_e32 v2, v0
+; GFX7-NEXT: v_bfi_b32 v2, s0, 0, v2
+; GFX7-NEXT: v_or_b32_e32 v2, s1, v2
+; GFX7-NEXT: v_movreld_b32_e32 v0, v2
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_v_v8i8_s_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
-; GFX10-NEXT: s_lshr_b32 s0, s3, 2
-; GFX10-NEXT: s_and_b32 s1, s3, 3
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1
-; GFX10-NEXT: s_lshl_b32 s1, s1, 3
-; GFX10-NEXT: s_and_b32 s2, s2, 0xff
-; GFX10-NEXT: s_lshl_b32 s3, 0xff, s1
-; GFX10-NEXT: s_lshl_b32 s1, s2, s1
-; GFX10-NEXT: s_not_b32 s2, s3
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s0, 0
-; GFX10-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc_lo
-; GFX10-NEXT: v_and_or_b32 v4, v2, s2, s1
+; GFX10-NEXT: s_and_b32 s0, s3, 3
+; GFX10-NEXT: s_lshr_b32 m0, s3, 2
+; GFX10-NEXT: s_lshl_b32 s0, s0, 3
+; GFX10-NEXT: s_and_b32 s1, s2, 0xff
+; GFX10-NEXT: s_lshl_b32 s2, 0xff, s0
+; GFX10-NEXT: s_lshl_b32 s0, s1, s0
+; GFX10-NEXT: s_not_b32 s1, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, 0
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_movrels_b32_e32 v2, v0
+; GFX10-NEXT: v_and_or_b32 v4, v2, s1, s0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX10-NEXT: v_movreld_b32_e32 v0, v4
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_v_v8i8_s_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT: s_lshr_b32 s0, s3, 2
-; GFX11-NEXT: s_and_b32 s1, s3, 3
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1
-; GFX11-NEXT: s_lshl_b32 s1, s1, 3
-; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: s_lshl_b32 s3, 0xff, s1
-; GFX11-NEXT: s_lshl_b32 s1, s2, s1
-; GFX11-NEXT: s_not_b32 s2, s3
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s0, 0
+; GFX11-NEXT: s_and_b32 s0, s3, 3
+; GFX11-NEXT: s_lshr_b32 m0, s3, 2
+; GFX11-NEXT: s_lshl_b32 s0, s0, 3
+; GFX11-NEXT: s_and_b32 s1, s2, 0xff
+; GFX11-NEXT: s_lshl_b32 s2, 0xff, s0
+; GFX11-NEXT: s_lshl_b32 s0, s1, s0
+; GFX11-NEXT: s_not_b32 s1, s2
+; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v2, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_and_or_b32 v4, v2, s2, s1
-; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v1, v4
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
+; GFX11-NEXT: v_movrels_b32_e32 v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_or_b32 v4, v2, s1, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: v_movreld_b32_e32 v0, v4
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-NEXT: s_endpgm
%vec = load <8 x i8>, ptr addrspace(1 ) %ptr
@@ -1759,123 +1744,106 @@ define amdgpu_ps void @insertelement_s_v8i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX9-NEXT: s_lshr_b32 s2, s4, 2
-; GFX9-NEXT: s_cmp_eq_u32 s2, 1
-; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_cselect_b32 s3, s1, s0
; GFX9-NEXT: s_and_b32 s4, s4, 3
+; GFX9-NEXT: s_mov_b32 m0, s2
; GFX9-NEXT: s_lshl_b32 s4, s4, 3
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_movrels_b32 s3, s0
; GFX9-NEXT: s_lshl_b32 s5, 0xff, s4
; GFX9-NEXT: s_andn2_b32 s3, s3, s5
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_lshl_or_b32 v4, v0, s4, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v8i8_v_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX8-NEXT: s_lshr_b32 s2, s4, 2
-; GFX8-NEXT: s_cmp_eq_u32 s2, 1
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: s_and_b32 s3, s4, 3
+; GFX8-NEXT: s_lshr_b32 m0, s4, 2
+; GFX8-NEXT: s_lshl_b32 s3, s3, 3
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_cselect_b32 s3, s1, s0
-; GFX8-NEXT: s_and_b32 s4, s4, 3
-; GFX8-NEXT: s_lshl_b32 s4, s4, 3
-; GFX8-NEXT: v_mov_b32_e32 v1, s4
-; GFX8-NEXT: s_lshl_b32 s4, 0xff, s4
+; GFX8-NEXT: s_movrels_b32 s2, s0
+; GFX8-NEXT: s_lshl_b32 s3, 0xff, s3
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: s_andn2_b32 s3, s3, s4
-; GFX8-NEXT: v_or_b32_e32 v4, s3, v0
+; GFX8-NEXT: s_andn2_b32 s2, s2, s3
+; GFX8-NEXT: v_or_b32_e32 v4, s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: v_mov_b32_e32 v3, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX8-NEXT: v_movreld_b32_e32 v0, v4
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v8i8_v_s:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX7-NEXT: s_lshr_b32 s2, s4, 2
-; GFX7-NEXT: s_cmp_eq_u32 s2, 1
+; GFX7-NEXT: s_and_b32 s3, s4, 3
+; GFX7-NEXT: s_lshr_b32 m0, s4, 2
+; GFX7-NEXT: s_lshl_b32 s3, s3, 3
; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_cselect_b32 s3, s1, s0
-; GFX7-NEXT: s_and_b32 s4, s4, 3
-; GFX7-NEXT: s_lshl_b32 s4, s4, 3
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX7-NEXT: s_lshl_b32 s4, 0xff, s4
-; GFX7-NEXT: s_andn2_b32 s3, s3, s4
-; GFX7-NEXT: v_or_b32_e32 v2, s3, v0
+; GFX7-NEXT: s_movrels_b32 s2, s0
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, s3, v0
+; GFX7-NEXT: s_lshl_b32 s3, 0xff, s3
+; GFX7-NEXT: s_andn2_b32 s2, s2, s3
+; GFX7-NEXT: v_or_b32_e32 v2, s2, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: v_movreld_b32_e32 v0, v2
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_s_v8i8_v_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX10-NEXT: s_lshr_b32 s2, s4, 2
-; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v0
-; GFX10-NEXT: s_cmp_eq_u32 s2, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
+; GFX10-NEXT: s_and_b32 s2, s4, 3
+; GFX10-NEXT: s_lshr_b32 m0, s4, 2
+; GFX10-NEXT: s_lshl_b32 s2, s2, 3
+; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-NEXT: s_lshl_b32 s3, 0xff, s2
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_cselect_b32 s3, s1, s0
-; GFX10-NEXT: s_and_b32 s4, s4, 3
+; GFX10-NEXT: s_movrels_b32 s4, s0
+; GFX10-NEXT: s_andn2_b32 s3, s4, s3
+; GFX10-NEXT: v_lshl_or_b32 v4, v0, s2, s3
; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: s_lshl_b32 s4, s4, 3
; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: s_lshl_b32 s5, 0xff, s4
-; GFX10-NEXT: s_andn2_b32 s3, s3, s5
-; GFX10-NEXT: v_lshl_or_b32 v4, v2, s4, s3
-; GFX10-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX10-NEXT: v_movreld_b32_e32 v0, v4
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v8i8_v_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
-; GFX11-NEXT: s_lshr_b32 s2, s4, 2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v0
-; GFX11-NEXT: s_cmp_eq_u32 s2, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
+; GFX11-NEXT: s_and_b32 s2, s4, 3
+; GFX11-NEXT: s_lshr_b32 m0, s4, 2
+; GFX11-NEXT: s_lshl_b32 s2, s2, 3
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: s_lshl_b32 s3, 0xff, s2
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s0
-; GFX11-NEXT: s_cselect_b32 s3, s1, s0
-; GFX11-NEXT: s_and_b32 s4, s4, 3
-; GFX11-NEXT: v_mov_b32_e32 v1, s1
-; GFX11-NEXT: s_lshl_b32 s4, s4, 3
+; GFX11-NEXT: s_movrels_b32 s4, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b32 s5, 0xff, s4
-; GFX11-NEXT: s_and_not1_b32 s3, s3, s5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v4, v2, s4, s3
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v1, v4
+; GFX11-NEXT: s_and_not1_b32 s3, s4, s3
+; GFX11-NEXT: v_lshl_or_b32 v4, v0, s2, s3
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_movreld_b32_e32 v0, v4
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-NEXT: s_endpgm
%vec = load <8 x i8>, ptr addrspace(4) %ptr
@@ -1888,78 +1856,72 @@ define amdgpu_ps void @insertelement_s_v8i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX9-LABEL: insertelement_s_v8i8_s_v:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 2, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 2, v0
; GFX9-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; GFX9-NEXT: v_mov_b32_e32 v6, 0xff
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v1, s0
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
-; GFX9-NEXT: s_and_b32 s2, s4, 0xff
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xff
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_lshlrev_b32_e64 v3, v0, s2
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v4
+; GFX9-NEXT: s_and_b32 s0, s4, 0xff
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX9-NEXT: v_lshlrev_b32_e64 v5, v0, s0
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_and_or_b32 v4, v1, v0, v3
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_and_or_b32 v5, v4, v0, v5
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v5, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
+; GFX9-NEXT: global_store_dwordx2 v[3:4], v[0:1], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v8i8_s_v:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 2, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 2, v0
; GFX8-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_mov_b32_e32 v1, s0
-; GFX8-NEXT: v_mov_b32_e32 v3, s1
-; GFX8-NEXT: s_and_b32 s2, s4, 0xff
-; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX8-NEXT: v_lshlrev_b32_e64 v3, v0, s2
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v4
-; GFX8-NEXT: v_bfi_b32 v0, v0, 0, v1
-; GFX8-NEXT: v_or_b32_e32 v4, v0, v3
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: s_and_b32 s0, s4, 0xff
+; GFX8-NEXT: v_mov_b32_e32 v6, 0xff
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
+; GFX8-NEXT: v_lshlrev_b32_e64 v5, v0, s0
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v6
+; GFX8-NEXT: v_bfi_b32 v0, v0, 0, v4
+; GFX8-NEXT: v_or_b32_e32 v5, v0, v5
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, v5, s[0:1]
; GFX8-NEXT: v_mov_b32_e32 v3, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
+; GFX8-NEXT: flat_store_dwordx2 v[3:4], v[0:1]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v8i8_s_v:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 2, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 2, v0
; GFX7-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
-; GFX7-NEXT: v_mov_b32_e32 v3, s1
-; GFX7-NEXT: s_and_b32 s2, s4, 0xff
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX7-NEXT: v_lshl_b32_e32 v3, s2, v0
+; GFX7-NEXT: s_and_b32 s0, s4, 0xff
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc
+; GFX7-NEXT: v_lshl_b32_e32 v5, s0, v0
; GFX7-NEXT: v_lshl_b32_e32 v0, 0xff, v0
-; GFX7-NEXT: v_bfi_b32 v0, v0, 0, v1
-; GFX7-NEXT: v_or_b32_e32 v3, v0, v3
-; GFX7-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX7-NEXT: v_bfi_b32 v0, v0, 0, v4
+; GFX7-NEXT: v_or_b32_e32 v4, v0, v5
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v1, v4, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
@@ -1972,18 +1934,17 @@ define amdgpu_ps void @insertelement_s_v8i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX10-NEXT: v_and_b32_e32 v1, 3, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 2, v0
; GFX10-NEXT: s_and_b32 s2, s4, 0xff
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xff
-; GFX10-NEXT: v_lshlrev_b32_e64 v3, v1, s2
-; GFX10-NEXT: v_not_b32_e32 v2, v2
+; GFX10-NEXT: v_lshlrev_b32_e64 v3, v2, 0xff
+; GFX10-NEXT: v_lshlrev_b32_e64 v2, v2, s2
+; GFX10-NEXT: v_not_b32_e32 v3, v3
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v0, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v5, s0, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
-; GFX10-NEXT: v_and_or_b32 v5, v5, v2, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
+; GFX10-NEXT: v_and_or_b32 v5, v5, v3, v2
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
@@ -1997,20 +1958,21 @@ define amdgpu_ps void @insertelement_s_v8i8_s_v(ptr addrspace(4) inreg %ptr, i8
; GFX11-NEXT: v_and_b32_e32 v1, 3, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 2, v0
; GFX11-NEXT: s_and_b32 s2, s4, 0xff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_lshlrev_b32 v1, 3, v1
-; GFX11-NEXT: v_cndmask_b32_e32 v5, s0, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b32_e64 v2, v1, 0xff
-; GFX11-NEXT: v_lshlrev_b32_e64 v3, v1, s2
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b32_e64 v3, v2, 0xff
+; GFX11-NEXT: v_lshlrev_b32_e64 v2, v2, s2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
-; GFX11-NEXT: v_not_b32_e32 v2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v5, v5, v2, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_not_b32_e32 v3, v3
+; GFX11-NEXT: v_and_or_b32 v5, v5, v3, v2
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
@@ -2025,76 +1987,70 @@ define amdgpu_ps void @insertelement_s_v8i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX9-LABEL: insertelement_s_v8i8_v_v:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 2, v1
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 2, v1
; GFX9-NEXT: v_and_b32_e32 v1, 3, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 3, v1
+; GFX9-NEXT: v_mov_b32_e32 v6, 0xff
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v3, s0
-; GFX9-NEXT: v_mov_b32_e32 v4, s1
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xff
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v2, v3, vcc
; GFX9-NEXT: v_not_b32_e32 v1, v1
-; GFX9-NEXT: v_and_or_b32 v4, v3, v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
+; GFX9-NEXT: v_and_or_b32 v1, v5, v1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9-NEXT: global_store_dwordx2 v[4:5], v[0:1], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v8i8_v_v:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 2, v1
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 2, v1
; GFX8-NEXT: v_and_b32_e32 v1, 3, v1
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s0
-; GFX8-NEXT: v_mov_b32_e32 v4, s1
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v6, 0xff
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v2, v3, vcc
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v4
-; GFX8-NEXT: v_bfi_b32 v1, v1, 0, v3
-; GFX8-NEXT: v_or_b32_e32 v4, v1, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v2, 0
-; GFX8-NEXT: v_mov_b32_e32 v3, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v6
+; GFX8-NEXT: v_bfi_b32 v1, v1, 0, v5
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX8-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v8i8_v_v:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 2, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 2, v1
; GFX7-NEXT: v_and_b32_e32 v1, 3, v1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v3, s0
-; GFX7-NEXT: v_mov_b32_e32 v4, s1
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v2, v3, vcc
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xff, v1
-; GFX7-NEXT: v_bfi_b32 v1, v1, 0, v3
-; GFX7-NEXT: v_or_b32_e32 v3, v1, v0
-; GFX7-NEXT: v_mov_b32_e32 v0, s0
-; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX7-NEXT: v_bfi_b32 v1, v1, 0, v5
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
@@ -2105,48 +2061,47 @@ define amdgpu_ps void @insertelement_s_v8i8_v_v(ptr addrspace(4) inreg %ptr, i8
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
; GFX10-NEXT: v_and_b32_e32 v2, 3, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v4, 2, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v2
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX10-NEXT: v_lshlrev_b32_e64 v3, v2, 0xff
-; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-NEXT: v_not_b32_e32 v3, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v5, 2, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 3, v2
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX10-NEXT: v_lshlrev_b32_e64 v4, v3, 0xff
+; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-NEXT: v_not_b32_e32 v3, v4
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v5, s0, v1, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
-; GFX10-NEXT: v_and_or_b32 v5, v5, v3, v2
-; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_mov_b32_e32 v2, s1
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc_lo
+; GFX10-NEXT: v_and_or_b32 v6, v4, v3, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
-; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, v6, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo
+; GFX10-NEXT: global_store_dwordx2 v[3:4], v[0:1], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v8i8_v_v:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX11-NEXT: v_and_b32_e32 v2, 3, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v4, 2, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 2, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v2, 3, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v5, s0, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b32_e64 v3, v2, 0xff
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, v2, v0
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v4
-; GFX11-NEXT: v_not_b32_e32 v3, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v5, v5, v3, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v5
+; GFX11-NEXT: v_lshlrev_b32_e64 v4, v2, 0xff
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, v2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_not_b32_e32 v3, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo
+; GFX11-NEXT: v_and_or_b32 v4, v4, v3, v2
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-NEXT: s_endpgm
%vec = load <8 x i8>, ptr addrspace(4) %ptr
@@ -2283,43 +2238,41 @@ define amdgpu_ps void @insertelement_v_v8i8_v_s(ptr addrspace(1) %ptr, i8 %val,
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_and_b32 s1, s2, 3
-; GFX9-NEXT: s_lshr_b32 s0, s2, 2
; GFX9-NEXT: s_lshl_b32 s1, s1, 3
+; GFX9-NEXT: s_lshr_b32 s0, s2, 2
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_lshl_b32 s1, 0xff, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
; GFX9-NEXT: s_not_b32 s1, s1
-; GFX9-NEXT: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
-; GFX9-NEXT: v_and_or_b32 v2, v5, s1, v2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: global_store_dwordx2 v[3:4], v[0:1], off
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
+; GFX9-NEXT: v_mov_b32_e32 v3, v0
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_or_b32 v4, v3, s1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v8i8_v_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX8-NEXT: s_and_b32 s1, s2, 3
-; GFX8-NEXT: s_lshr_b32 s0, s2, 2
-; GFX8-NEXT: s_lshl_b32 s1, s1, 3
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
-; GFX8-NEXT: s_lshl_b32 s1, 0xff, s1
-; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_mov_b32_e32 v3, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: s_and_b32 s0, s2, 3
+; GFX8-NEXT: s_lshl_b32 s0, s0, 3
+; GFX8-NEXT: s_lshr_b32 m0, s2, 2
+; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: s_lshl_b32 s0, 0xff, s0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc
-; GFX8-NEXT: v_bfi_b32 v5, s1, 0, v5
-; GFX8-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: flat_store_dwordx2 v[3:4], v[0:1]
+; GFX8-NEXT: v_movrels_b32_e32 v3, v0
+; GFX8-NEXT: v_bfi_b32 v3, s0, 0, v3
+; GFX8-NEXT: v_or_b32_e32 v4, v3, v2
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: v_mov_b32_e32 v3, 0
+; GFX8-NEXT: v_movreld_b32_e32 v0, v4
+; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_v_v8i8_v_s:
@@ -2328,66 +2281,58 @@ define amdgpu_ps void @insertelement_v_v8i8_v_s(ptr addrspace(1) %ptr, i8 %val,
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_lshr_b32 s0, s2, 2
-; GFX7-NEXT: s_and_b32 s1, s2, 3
+; GFX7-NEXT: s_and_b32 s0, s2, 3
+; GFX7-NEXT: s_lshr_b32 m0, s2, 2
; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX7-NEXT: s_lshl_b32 s1, s1, 3
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, s1, v2
-; GFX7-NEXT: s_lshl_b32 s1, 0xff, s1
+; GFX7-NEXT: s_lshl_b32 s0, s0, 3
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, s0, v2
+; GFX7-NEXT: s_lshl_b32 s0, 0xff, s0
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
-; GFX7-NEXT: v_bfi_b32 v3, s1, 0, v3
+; GFX7-NEXT: v_movrels_b32_e32 v3, v0
+; GFX7-NEXT: v_bfi_b32 v3, s0, 0, v3
; GFX7-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_movreld_b32_e32 v0, v2
; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_v_v8i8_v_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
-; GFX10-NEXT: s_lshr_b32 s1, s2, 2
; GFX10-NEXT: s_and_b32 s0, s2, 3
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s1, 1
+; GFX10-NEXT: s_lshr_b32 m0, s2, 2
; GFX10-NEXT: s_lshl_b32 s0, s0, 3
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: s_lshl_b32 s0, 0xff, s0
; GFX10-NEXT: s_not_b32 s0, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc_lo
+; GFX10-NEXT: v_movrels_b32_e32 v3, v0
; GFX10-NEXT: v_and_or_b32 v4, v3, s0, v2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
+; GFX10-NEXT: v_movreld_b32_e32 v0, v4
; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_v_v8i8_v_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT: s_lshr_b32 s1, s2, 2
-; GFX11-NEXT: s_and_b32 s0, s2, 3
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s1, 1
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-NEXT: s_and_b32 s0, s2, 3
+; GFX11-NEXT: s_lshr_b32 m0, s2, 2
; GFX11-NEXT: s_lshl_b32 s0, s0, 3
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v3, v0, v1 :: v_dual_lshlrev_b32 v2, s0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, s0, v2
; GFX11-NEXT: s_lshl_b32 s0, 0xff, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_not_b32 s0, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_movrels_b32_e32 v3, v0
; GFX11-NEXT: v_and_or_b32 v4, v3, s0, v2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s1, 0
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v4, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_movreld_b32_e32 v0, v4
; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
; GFX11-NEXT: s_endpgm
%vec = load <8 x i8>, ptr addrspace(1) %ptr
@@ -2521,32 +2466,20 @@ define amdgpu_ps void @insertelement_s_v16i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX9-LABEL: insertelement_s_v16i8_s_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX9-NEXT: s_lshr_b32 s6, s5, 2
-; GFX9-NEXT: s_cmp_eq_u32 s6, 1
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_cselect_b32 s7, s1, s0
-; GFX9-NEXT: s_cmp_eq_u32 s6, 2
-; GFX9-NEXT: s_cselect_b32 s7, s2, s7
-; GFX9-NEXT: s_cmp_eq_u32 s6, 3
-; GFX9-NEXT: s_cselect_b32 s7, s3, s7
+; GFX9-NEXT: s_lshr_b32 m0, s5, 2
; GFX9-NEXT: s_and_b32 s5, s5, 3
; GFX9-NEXT: s_lshl_b32 s5, s5, 3
; GFX9-NEXT: s_and_b32 s4, s4, 0xff
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_movrels_b32 s6, s0
; GFX9-NEXT: s_lshl_b32 s4, s4, s5
; GFX9-NEXT: s_lshl_b32 s5, 0xff, s5
-; GFX9-NEXT: s_andn2_b32 s5, s7, s5
+; GFX9-NEXT: s_andn2_b32 s5, s6, s5
; GFX9-NEXT: s_or_b32 s4, s5, s4
-; GFX9-NEXT: s_cmp_eq_u32 s6, 0
-; GFX9-NEXT: s_cselect_b32 s0, s4, s0
-; GFX9-NEXT: s_cmp_eq_u32 s6, 1
-; GFX9-NEXT: s_cselect_b32 s1, s4, s1
-; GFX9-NEXT: s_cmp_eq_u32 s6, 2
-; GFX9-NEXT: s_cselect_b32 s2, s4, s2
-; GFX9-NEXT: s_cmp_eq_u32 s6, 3
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
+; GFX9-NEXT: s_movreld_b32 s0, s4
; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
@@ -2556,32 +2489,20 @@ define amdgpu_ps void @insertelement_s_v16i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX8-LABEL: insertelement_s_v16i8_s_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX8-NEXT: s_lshr_b32 s6, s5, 2
-; GFX8-NEXT: s_cmp_eq_u32 s6, 1
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
-; GFX8-NEXT: v_mov_b32_e32 v5, 0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_cselect_b32 s7, s1, s0
-; GFX8-NEXT: s_cmp_eq_u32 s6, 2
-; GFX8-NEXT: s_cselect_b32 s7, s2, s7
-; GFX8-NEXT: s_cmp_eq_u32 s6, 3
-; GFX8-NEXT: s_cselect_b32 s7, s3, s7
+; GFX8-NEXT: s_lshr_b32 m0, s5, 2
; GFX8-NEXT: s_and_b32 s5, s5, 3
; GFX8-NEXT: s_lshl_b32 s5, s5, 3
; GFX8-NEXT: s_and_b32 s4, s4, 0xff
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_movrels_b32 s6, s0
; GFX8-NEXT: s_lshl_b32 s4, s4, s5
; GFX8-NEXT: s_lshl_b32 s5, 0xff, s5
-; GFX8-NEXT: s_andn2_b32 s5, s7, s5
+; GFX8-NEXT: s_andn2_b32 s5, s6, s5
; GFX8-NEXT: s_or_b32 s4, s5, s4
-; GFX8-NEXT: s_cmp_eq_u32 s6, 0
-; GFX8-NEXT: s_cselect_b32 s0, s4, s0
-; GFX8-NEXT: s_cmp_eq_u32 s6, 1
-; GFX8-NEXT: s_cselect_b32 s1, s4, s1
-; GFX8-NEXT: s_cmp_eq_u32 s6, 2
-; GFX8-NEXT: s_cselect_b32 s2, s4, s2
-; GFX8-NEXT: s_cmp_eq_u32 s6, 3
-; GFX8-NEXT: s_cselect_b32 s3, s4, s3
+; GFX8-NEXT: s_movreld_b32 s0, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
@@ -2591,29 +2512,17 @@ define amdgpu_ps void @insertelement_s_v16i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX7-LABEL: insertelement_s_v16i8_s_s:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX7-NEXT: s_lshr_b32 s6, s5, 2
-; GFX7-NEXT: s_cmp_eq_u32 s6, 1
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_cselect_b32 s7, s1, s0
-; GFX7-NEXT: s_cmp_eq_u32 s6, 2
-; GFX7-NEXT: s_cselect_b32 s7, s2, s7
-; GFX7-NEXT: s_cmp_eq_u32 s6, 3
-; GFX7-NEXT: s_cselect_b32 s7, s3, s7
+; GFX7-NEXT: s_lshr_b32 m0, s5, 2
; GFX7-NEXT: s_and_b32 s5, s5, 3
; GFX7-NEXT: s_lshl_b32 s5, s5, 3
; GFX7-NEXT: s_and_b32 s4, s4, 0xff
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_movrels_b32 s6, s0
; GFX7-NEXT: s_lshl_b32 s4, s4, s5
; GFX7-NEXT: s_lshl_b32 s5, 0xff, s5
-; GFX7-NEXT: s_andn2_b32 s5, s7, s5
+; GFX7-NEXT: s_andn2_b32 s5, s6, s5
; GFX7-NEXT: s_or_b32 s4, s5, s4
-; GFX7-NEXT: s_cmp_eq_u32 s6, 0
-; GFX7-NEXT: s_cselect_b32 s0, s4, s0
-; GFX7-NEXT: s_cmp_eq_u32 s6, 1
-; GFX7-NEXT: s_cselect_b32 s1, s4, s1
-; GFX7-NEXT: s_cmp_eq_u32 s6, 2
-; GFX7-NEXT: s_cselect_b32 s2, s4, s2
-; GFX7-NEXT: s_cmp_eq_u32 s6, 3
-; GFX7-NEXT: s_cselect_b32 s3, s4, s3
+; GFX7-NEXT: s_movreld_b32 s0, s4
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
@@ -2627,31 +2536,19 @@ define amdgpu_ps void @insertelement_s_v16i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX10-LABEL: insertelement_s_v16i8_s_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX10-NEXT: s_lshr_b32 s6, s5, 2
-; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: s_cmp_eq_u32 s6, 1
-; GFX10-NEXT: v_mov_b32_e32 v5, 0
-; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_cselect_b32 s7, s1, s0
-; GFX10-NEXT: s_cmp_eq_u32 s6, 2
-; GFX10-NEXT: s_cselect_b32 s7, s2, s7
-; GFX10-NEXT: s_cmp_eq_u32 s6, 3
-; GFX10-NEXT: s_cselect_b32 s7, s3, s7
+; GFX10-NEXT: s_lshr_b32 m0, s5, 2
; GFX10-NEXT: s_and_b32 s5, s5, 3
; GFX10-NEXT: s_and_b32 s4, s4, 0xff
; GFX10-NEXT: s_lshl_b32 s5, s5, 3
-; GFX10-NEXT: s_lshl_b32 s8, 0xff, s5
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: s_lshl_b32 s7, 0xff, s5
; GFX10-NEXT: s_lshl_b32 s4, s4, s5
-; GFX10-NEXT: s_andn2_b32 s5, s7, s8
+; GFX10-NEXT: v_mov_b32_e32 v5, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_movrels_b32 s6, s0
+; GFX10-NEXT: s_andn2_b32 s5, s6, s7
; GFX10-NEXT: s_or_b32 s4, s5, s4
-; GFX10-NEXT: s_cmp_eq_u32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s0, s4, s0
-; GFX10-NEXT: s_cmp_eq_u32 s6, 1
-; GFX10-NEXT: s_cselect_b32 s1, s4, s1
-; GFX10-NEXT: s_cmp_eq_u32 s6, 2
-; GFX10-NEXT: s_cselect_b32 s2, s4, s2
-; GFX10-NEXT: s_cmp_eq_u32 s6, 3
-; GFX10-NEXT: s_cselect_b32 s3, s4, s3
+; GFX10-NEXT: s_movreld_b32 s0, s4
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s2
@@ -2662,31 +2559,20 @@ define amdgpu_ps void @insertelement_s_v16i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX11-LABEL: insertelement_s_v16i8_s_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0
-; GFX11-NEXT: s_lshr_b32 s6, s5, 2
-; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
-; GFX11-NEXT: s_cmp_eq_u32 s6, 1
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_cselect_b32 s7, s1, s0
-; GFX11-NEXT: s_cmp_eq_u32 s6, 2
-; GFX11-NEXT: s_cselect_b32 s7, s2, s7
-; GFX11-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-NEXT: s_cselect_b32 s7, s3, s7
+; GFX11-NEXT: s_lshr_b32 m0, s5, 2
; GFX11-NEXT: s_and_b32 s5, s5, 3
; GFX11-NEXT: s_and_b32 s4, s4, 0xff
; GFX11-NEXT: s_lshl_b32 s5, s5, 3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b32 s8, 0xff, s5
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
+; GFX11-NEXT: s_lshl_b32 s7, 0xff, s5
; GFX11-NEXT: s_lshl_b32 s4, s4, s5
-; GFX11-NEXT: s_and_not1_b32 s5, s7, s8
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_movrels_b32 s6, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_not1_b32 s5, s6, s7
; GFX11-NEXT: s_or_b32 s4, s5, s4
-; GFX11-NEXT: s_cmp_eq_u32 s6, 0
-; GFX11-NEXT: s_cselect_b32 s0, s4, s0
-; GFX11-NEXT: s_cmp_eq_u32 s6, 1
-; GFX11-NEXT: s_cselect_b32 s1, s4, s1
-; GFX11-NEXT: s_cmp_eq_u32 s6, 2
-; GFX11-NEXT: s_cselect_b32 s2, s4, s2
-; GFX11-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-NEXT: s_cselect_b32 s3, s4, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_movreld_b32 s0, s4
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
@@ -2701,145 +2587,104 @@ define amdgpu_ps void @insertelement_v_v16i8_s_s(ptr addrspace(1) %ptr, i8 inreg
; GFX9-LABEL: insertelement_v_v16i8_s_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT: s_and_b32 s0, s3, 3
-; GFX9-NEXT: s_lshr_b32 s4, s3, 2
-; GFX9-NEXT: s_and_b32 s1, s2, 0xff
-; GFX9-NEXT: s_lshl_b32 s0, s0, 3
-; GFX9-NEXT: s_lshl_b32 s1, s1, s0
-; GFX9-NEXT: s_lshl_b32 s0, 0xff, s0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX9-NEXT: s_not_b32 s5, s0
-; GFX9-NEXT: v_mov_b32_e32 v6, s1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
+; GFX9-NEXT: s_and_b32 s1, s3, 3
+; GFX9-NEXT: s_and_b32 s2, s2, 0xff
+; GFX9-NEXT: s_lshl_b32 s1, s1, 3
+; GFX9-NEXT: s_lshr_b32 s0, s3, 2
+; GFX9-NEXT: s_lshl_b32 s2, s2, s1
+; GFX9-NEXT: s_lshl_b32 s1, 0xff, s1
+; GFX9-NEXT: s_not_b32 s1, s1
+; GFX9-NEXT: v_mov_b32_e32 v4, s2
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
+; GFX9-NEXT: v_mov_b32_e32 v5, v0
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_or_b32 v6, v5, s1, v4
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v0, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v2, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v3, s[2:3]
-; GFX9-NEXT: v_and_or_b32 v6, v7, s5, v6
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v6
+; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v16i8_s_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
-; GFX8-NEXT: s_lshr_b32 s4, s3, 2
; GFX8-NEXT: s_and_b32 s0, s3, 3
+; GFX8-NEXT: s_lshr_b32 m0, s3, 2
; GFX8-NEXT: s_and_b32 s1, s2, 0xff
; GFX8-NEXT: s_lshl_b32 s0, s0, 3
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX8-NEXT: s_lshl_b32 s5, s1, s0
-; GFX8-NEXT: s_lshl_b32 s6, 0xff, s0
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: s_lshl_b32 s1, s1, s0
+; GFX8-NEXT: s_lshl_b32 s0, 0xff, s0
; GFX8-NEXT: v_mov_b32_e32 v5, 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v2, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[2:3]
-; GFX8-NEXT: v_bfi_b32 v6, s6, 0, v6
-; GFX8-NEXT: v_or_b32_e32 v6, s5, v6
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
+; GFX8-NEXT: v_movrels_b32_e32 v4, v0
+; GFX8-NEXT: v_bfi_b32 v4, s0, 0, v4
+; GFX8-NEXT: v_or_b32_e32 v6, s1, v4
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_movreld_b32_e32 v0, v6
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_v_v16i8_s_s:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b64 s[8:9], 0
-; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_lshr_b32 s4, s3, 2
+; GFX7-NEXT: s_mov_b32 s6, 0
+; GFX7-NEXT: s_mov_b32 s7, 0xf000
+; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64
; GFX7-NEXT: s_and_b32 s0, s3, 3
+; GFX7-NEXT: s_lshr_b32 m0, s3, 2
; GFX7-NEXT: s_and_b32 s1, s2, 0xff
; GFX7-NEXT: s_lshl_b32 s0, s0, 3
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX7-NEXT: s_lshl_b32 s5, s1, s0
-; GFX7-NEXT: s_lshl_b32 s6, 0xff, s0
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
-; GFX7-NEXT: s_mov_b64 s[8:9], 0
-; GFX7-NEXT: s_mov_b32 s10, -1
+; GFX7-NEXT: s_lshl_b32 s1, s1, s0
+; GFX7-NEXT: s_lshl_b32 s0, 0xff, s0
+; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v2, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v3, s[2:3]
-; GFX7-NEXT: v_bfi_b32 v4, s6, 0, v4
-; GFX7-NEXT: v_or_b32_e32 v4, s5, v4
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[2:3]
-; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX7-NEXT: v_movrels_b32_e32 v4, v0
+; GFX7-NEXT: v_bfi_b32 v4, s0, 0, v4
+; GFX7-NEXT: v_or_b32_e32 v4, s1, v4
+; GFX7-NEXT: v_movreld_b32_e32 v0, v4
+; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_v_v16i8_s_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-NEXT: s_lshr_b32 s4, s3, 2
-; GFX10-NEXT: s_and_b32 s1, s3, 3
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s4, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s4, 2
-; GFX10-NEXT: s_lshl_b32 s3, s1, 3
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s4, 3
-; GFX10-NEXT: s_and_b32 s2, s2, 0xff
-; GFX10-NEXT: s_lshl_b32 s5, 0xff, s3
-; GFX10-NEXT: s_lshl_b32 s2, s2, s3
-; GFX10-NEXT: s_not_b32 s3, s5
+; GFX10-NEXT: s_and_b32 s0, s3, 3
+; GFX10-NEXT: s_lshr_b32 m0, s3, 2
+; GFX10-NEXT: s_lshl_b32 s0, s0, 3
+; GFX10-NEXT: s_and_b32 s1, s2, 0xff
+; GFX10-NEXT: s_lshl_b32 s2, 0xff, s0
+; GFX10-NEXT: s_lshl_b32 s0, s1, s0
+; GFX10-NEXT: s_not_b32 s1, s2
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v3, s1
-; GFX10-NEXT: v_and_or_b32 v6, v4, s3, s2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s4, 0
+; GFX10-NEXT: v_movrels_b32_e32 v4, v0
+; GFX10-NEXT: v_and_or_b32 v6, v4, s1, s0
; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v6, s1
+; GFX10-NEXT: v_movreld_b32_e32 v0, v6
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_v_v16i8_s_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
-; GFX11-NEXT: s_lshr_b32 s4, s3, 2
-; GFX11-NEXT: s_and_b32 s1, s3, 3
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s4, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s4, 2
-; GFX11-NEXT: s_lshl_b32 s3, s1, 3
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s4, 3
-; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: s_lshl_b32 s5, 0xff, s3
-; GFX11-NEXT: s_lshl_b32 s2, s2, s3
-; GFX11-NEXT: s_not_b32 s3, s5
+; GFX11-NEXT: s_and_b32 s0, s3, 3
+; GFX11-NEXT: s_lshr_b32 m0, s3, 2
+; GFX11-NEXT: s_lshl_b32 s0, s0, 3
+; GFX11-NEXT: s_and_b32 s1, s2, 0xff
+; GFX11-NEXT: s_lshl_b32 s2, 0xff, s0
+; GFX11-NEXT: s_lshl_b32 s0, s1, s0
+; GFX11-NEXT: s_not_b32 s1, s2
+; GFX11-NEXT: v_mov_b32_e32 v5, 0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_cndmask_b32 v4, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v3, s1
+; GFX11-NEXT: v_movrels_b32_e32 v4, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v6, v4, s3, s2
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, s4, 0
-; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v1, v1, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v6, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v6, s1
+; GFX11-NEXT: v_and_or_b32 v6, v4, s1, s0
+; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: v_movreld_b32_e32 v0, v6
; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
; GFX11-NEXT: s_endpgm
%vec = load <16 x i8>, ptr addrspace(1 ) %ptr
@@ -2853,173 +2698,115 @@ define amdgpu_ps void @insertelement_s_v16i8_v_s(ptr addrspace(4) inreg %ptr, i8
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
; GFX9-NEXT: s_lshr_b32 s5, s4, 2
-; GFX9-NEXT: s_cmp_eq_u32 s5, 1
-; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_cselect_b32 s6, s1, s0
-; GFX9-NEXT: s_cmp_eq_u32 s5, 2
-; GFX9-NEXT: s_cselect_b32 s6, s2, s6
-; GFX9-NEXT: s_cmp_eq_u32 s5, 3
-; GFX9-NEXT: s_cselect_b32 s6, s3, s6
; GFX9-NEXT: s_and_b32 s4, s4, 3
+; GFX9-NEXT: s_mov_b32 m0, s5
; GFX9-NEXT: s_lshl_b32 s4, s4, 3
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_movrels_b32 s6, s0
; GFX9-NEXT: s_lshl_b32 s7, 0xff, s4
; GFX9-NEXT: s_andn2_b32 s6, s6, s7
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_lshl_or_b32 v6, v0, s4, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s5, 2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s5, 3
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: s_set_gpr_idx_on s5, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v0, v6
+; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v16i8_v_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX8-NEXT: s_lshr_b32 s5, s4, 2
-; GFX8-NEXT: s_cmp_eq_u32 s5, 1
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_cselect_b32 s6, s1, s0
-; GFX8-NEXT: s_cmp_eq_u32 s5, 2
-; GFX8-NEXT: s_cselect_b32 s6, s2, s6
-; GFX8-NEXT: s_cmp_eq_u32 s5, 3
-; GFX8-NEXT: s_cselect_b32 s6, s3, s6
+; GFX8-NEXT: s_lshr_b32 m0, s4, 2
; GFX8-NEXT: s_and_b32 s4, s4, 3
; GFX8-NEXT: s_lshl_b32 s4, s4, 3
; GFX8-NEXT: v_mov_b32_e32 v1, s4
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_movrels_b32 s5, s0
; GFX8-NEXT: s_lshl_b32 s4, 0xff, s4
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: s_andn2_b32 s4, s6, s4
+; GFX8-NEXT: s_andn2_b32 s4, s5, s4
; GFX8-NEXT: v_or_b32_e32 v6, s4, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s5, 2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s5, 3
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
; GFX8-NEXT: v_mov_b32_e32 v5, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX8-NEXT: v_movreld_b32_e32 v0, v6
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v16i8_v_s:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX7-NEXT: s_lshr_b32 s5, s4, 2
-; GFX7-NEXT: s_cmp_eq_u32 s5, 1
-; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_cselect_b32 s6, s1, s0
-; GFX7-NEXT: s_cmp_eq_u32 s5, 2
-; GFX7-NEXT: s_cselect_b32 s6, s2, s6
-; GFX7-NEXT: s_cmp_eq_u32 s5, 3
-; GFX7-NEXT: s_cselect_b32 s6, s3, s6
+; GFX7-NEXT: s_lshr_b32 m0, s4, 2
; GFX7-NEXT: s_and_b32 s4, s4, 3
; GFX7-NEXT: s_lshl_b32 s4, s4, 3
+; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_movrels_b32 s5, s0
; GFX7-NEXT: v_lshlrev_b32_e32 v0, s4, v0
; GFX7-NEXT: s_lshl_b32 s4, 0xff, s4
-; GFX7-NEXT: s_andn2_b32 s4, s6, s4
+; GFX7-NEXT: s_andn2_b32 s4, s5, s4
; GFX7-NEXT: v_or_b32_e32 v4, s4, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 1
; GFX7-NEXT: v_mov_b32_e32 v2, s2
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s5, 3
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: v_movreld_b32_e32 v0, v4
; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_s_v16i8_v_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
-; GFX10-NEXT: s_lshr_b32 s5, s4, 2
-; GFX10-NEXT: v_and_b32_e32 v4, 0xff, v0
-; GFX10-NEXT: s_cmp_eq_u32 s5, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 0
+; GFX10-NEXT: s_and_b32 s5, s4, 3
+; GFX10-NEXT: s_lshr_b32 m0, s4, 2
+; GFX10-NEXT: s_lshl_b32 s4, s5, 3
+; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-NEXT: s_lshl_b32 s5, 0xff, s4
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_cselect_b32 s6, s1, s0
-; GFX10-NEXT: s_cmp_eq_u32 s5, 2
+; GFX10-NEXT: s_movrels_b32 s6, s0
+; GFX10-NEXT: s_andn2_b32 s5, s6, s5
+; GFX10-NEXT: v_lshl_or_b32 v6, v0, s4, s5
; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: s_cselect_b32 s6, s2, s6
-; GFX10-NEXT: s_cmp_eq_u32 s5, 3
; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: s_cselect_b32 s6, s3, s6
-; GFX10-NEXT: s_and_b32 s4, s4, 3
; GFX10-NEXT: v_mov_b32_e32 v2, s2
-; GFX10-NEXT: s_lshl_b32 s4, s4, 3
; GFX10-NEXT: v_mov_b32_e32 v3, s3
-; GFX10-NEXT: s_lshl_b32 s7, 0xff, s4
-; GFX10-NEXT: s_andn2_b32 s6, s6, s7
-; GFX10-NEXT: v_lshl_or_b32 v6, v4, s4, s6
-; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 1
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 2
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 3
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX10-NEXT: v_movreld_b32_e32 v0, v6
; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v16i8_v_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0
-; GFX11-NEXT: s_lshr_b32 s5, s4, 2
-; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v0
-; GFX11-NEXT: s_cmp_eq_u32 s5, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 0
-; GFX11-NEXT: v_mov_b32_e32 v5, 0
+; GFX11-NEXT: s_and_b32 s5, s4, 3
+; GFX11-NEXT: s_lshr_b32 m0, s4, 2
+; GFX11-NEXT: s_lshl_b32 s4, s5, 3
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: s_lshl_b32 s5, 0xff, s4
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_cselect_b32 s6, s1, s0
-; GFX11-NEXT: s_cmp_eq_u32 s5, 2
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
-; GFX11-NEXT: s_cselect_b32 s6, s2, s6
-; GFX11-NEXT: s_cmp_eq_u32 s5, 3
-; GFX11-NEXT: v_mov_b32_e32 v1, s1
-; GFX11-NEXT: s_cselect_b32 s6, s3, s6
-; GFX11-NEXT: s_and_b32 s4, s4, 3
-; GFX11-NEXT: v_mov_b32_e32 v2, s2
-; GFX11-NEXT: s_lshl_b32 s4, s4, 3
+; GFX11-NEXT: s_movrels_b32 s6, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b32 s7, 0xff, s4
-; GFX11-NEXT: s_and_not1_b32 s6, s6, s7
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v6, v4, s4, s6
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 1
-; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v1, v1, v6
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 2
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s5, 3
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX11-NEXT: s_and_not1_b32 s5, s6, s5
+; GFX11-NEXT: v_lshl_or_b32 v6, v0, s4, s5
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_movreld_b32_e32 v0, v6
; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
; GFX11-NEXT: s_endpgm
%vec = load <16 x i8>, ptr addrspace(4) %ptr
@@ -3031,109 +2818,97 @@ define amdgpu_ps void @insertelement_s_v16i8_v_s(ptr addrspace(4) inreg %ptr, i8
define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8 inreg %val, i32 %idx) {
; GFX9-LABEL: insertelement_s_v16i8_s_v:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 2, v0
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 2, v0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
; GFX9-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, s8
-; GFX9-NEXT: v_mov_b32_e32 v2, s9
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v4, s3
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: v_mov_b32_e32 v3, s2
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
; GFX9-NEXT: s_and_b32 s4, s4, 0xff
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xff
-; GFX9-NEXT: v_mov_b32_e32 v5, s11
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
-; GFX9-NEXT: v_lshlrev_b32_e64 v2, v0, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v8, 0xff
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
+; GFX9-NEXT: v_lshlrev_b32_e64 v7, v0, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, v0, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
; GFX9-NEXT: v_not_b32_e32 v0, v0
-; GFX9-NEXT: v_and_or_b32 v6, v1, v0, v2
-; GFX9-NEXT: v_mov_b32_e32 v0, s8
-; GFX9-NEXT: v_mov_b32_e32 v1, s9
-; GFX9-NEXT: v_mov_b32_e32 v2, s10
-; GFX9-NEXT: v_mov_b32_e32 v3, s11
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_and_or_b32 v7, v6, v0, v7
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v1, v7, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v7, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
-; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v7, s[2:3]
+; GFX9-NEXT: global_store_dwordx4 v[5:6], v[0:3], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v16i8_s_v:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 2, v0
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 2, v0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
; GFX8-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s8
-; GFX8-NEXT: v_mov_b32_e32 v2, s9
-; GFX8-NEXT: v_mov_b32_e32 v3, s10
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: v_mov_b32_e32 v5, s11
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v4, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX8-NEXT: s_and_b32 s4, s4, 0xff
-; GFX8-NEXT: v_mov_b32_e32 v3, 0xff
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
-; GFX8-NEXT: v_lshlrev_b32_e64 v2, v0, s4
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v3
-; GFX8-NEXT: v_bfi_b32 v0, v0, 0, v1
-; GFX8-NEXT: v_or_b32_e32 v6, v0, v2
-; GFX8-NEXT: v_mov_b32_e32 v0, s8
-; GFX8-NEXT: v_mov_b32_e32 v1, s9
-; GFX8-NEXT: v_mov_b32_e32 v2, s10
-; GFX8-NEXT: v_mov_b32_e32 v3, s11
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_mov_b32_e32 v8, 0xff
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
+; GFX8-NEXT: v_lshlrev_b32_e64 v7, v0, s4
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, v0, v8
+; GFX8-NEXT: v_bfi_b32 v0, v0, 0, v6
+; GFX8-NEXT: v_or_b32_e32 v7, v0, v7
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, v7, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v7, s[0:1]
; GFX8-NEXT: v_mov_b32_e32 v5, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v6, 0
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, v7, s[2:3]
+; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v16i8_s_v:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 2, v0
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 2, v0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
; GFX7-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v1, s8
-; GFX7-NEXT: v_mov_b32_e32 v2, s9
-; GFX7-NEXT: v_mov_b32_e32 v3, s10
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX7-NEXT: v_mov_b32_e32 v5, s11
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v4, s3
+; GFX7-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-NEXT: v_mov_b32_e32 v1, s0
+; GFX7-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v5
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v3, s[0:1]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v5
; GFX7-NEXT: s_and_b32 s4, s4, 0xff
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
-; GFX7-NEXT: v_lshl_b32_e32 v2, s4, v0
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[2:3]
+; GFX7-NEXT: v_lshl_b32_e32 v7, s4, v0
; GFX7-NEXT: v_lshl_b32_e32 v0, 0xff, v0
-; GFX7-NEXT: v_bfi_b32 v0, v0, 0, v1
-; GFX7-NEXT: v_or_b32_e32 v5, v0, v2
-; GFX7-NEXT: v_mov_b32_e32 v0, s8
-; GFX7-NEXT: v_mov_b32_e32 v1, s9
-; GFX7-NEXT: v_mov_b32_e32 v2, s10
-; GFX7-NEXT: v_mov_b32_e32 v3, s11
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[2:3]
+; GFX7-NEXT: v_bfi_b32 v0, v0, 0, v6
+; GFX7-NEXT: v_or_b32_e32 v6, v0, v7
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v1, v6, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v3, v6, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v4, v6, s[2:3]
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
@@ -3142,28 +2917,27 @@ define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8
;
; GFX10-LABEL: insertelement_s_v16i8_s_v:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v6, 2, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 3, v0
-; GFX10-NEXT: s_and_b32 s1, s4, 0xff
+; GFX10-NEXT: v_and_b32_e32 v4, 3, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v4
+; GFX10-NEXT: v_lshlrev_b32_e64 v7, v4, 0xff
+; GFX10-NEXT: v_not_b32_e32 v7, v7
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v6
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
-; GFX10-NEXT: v_lshlrev_b32_e64 v2, v1, 0xff
-; GFX10-NEXT: v_lshlrev_b32_e64 v4, v1, s1
+; GFX10-NEXT: s_and_b32 s1, s4, 0xff
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e64 v4, v4, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v6
-; GFX10-NEXT: v_not_b32_e32 v5, v2
-; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v0, s9
-; GFX10-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s10, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v0, s11, s1
-; GFX10-NEXT: v_mov_b32_e32 v0, s8
-; GFX10-NEXT: v_mov_b32_e32 v1, s9
-; GFX10-NEXT: v_mov_b32_e32 v2, s10
-; GFX10-NEXT: v_mov_b32_e32 v3, s11
-; GFX10-NEXT: v_and_or_b32 v7, v7, v5, v4
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v3, s1
+; GFX10-NEXT: v_and_or_b32 v7, v5, v7, v4
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
@@ -3175,29 +2949,28 @@ define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8
;
; GFX11-LABEL: insertelement_s_v16i8_s_v:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[8:11], s[2:3], 0x0
+; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 2, v0
-; GFX11-NEXT: v_and_b32_e32 v1, 3, v0
-; GFX11-NEXT: s_and_b32 s1, s4, 0xff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_b32_e32 v4, 3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v4
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v6
+; GFX11-NEXT: s_and_b32 s1, s4, 0xff
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s9 :: v_dual_lshlrev_b32 v1, 3, v1
-; GFX11-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b32_e64 v2, v1, 0xff
-; GFX11-NEXT: v_lshlrev_b32_e64 v4, v1, s1
+; GFX11-NEXT: v_lshlrev_b32_e64 v7, v4, 0xff
+; GFX11-NEXT: v_lshlrev_b32_e64 v4, v4, s1
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v6
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s10, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_not_b32_e32 v5, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v0, s11, s1
-; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX11-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v7, v7, v5, v4
+; GFX11-NEXT: v_not_b32_e32 v7, v7
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v3, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_or_b32 v7, v5, v7, v4
; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
@@ -3214,107 +2987,95 @@ define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8
define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8 %val, i32 %idx) {
; GFX9-LABEL: insertelement_s_v16i8_v_v:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 2, v1
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 2, v1
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX9-NEXT: v_and_b32_e32 v1, 3, v1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
-; GFX9-NEXT: v_mov_b32_e32 v3, s5
-; GFX9-NEXT: v_mov_b32_e32 v5, s6
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 3, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xff
-; GFX9-NEXT: v_mov_b32_e32 v6, s7
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v5, s3
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_mov_b32_e32 v4, s2
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
+; GFX9-NEXT: v_mov_b32_e32 v8, 0xff
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[2:3]
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, v1, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX9-NEXT: v_not_b32_e32 v1, v1
-; GFX9-NEXT: v_and_or_b32 v6, v2, v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
-; GFX9-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-NEXT: v_mov_b32_e32 v2, s6
-; GFX9-NEXT: v_mov_b32_e32 v3, s7
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
-; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
+; GFX9-NEXT: v_and_or_b32 v8, v7, v1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v8, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v8, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: v_mov_b32_e32 v7, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v8, s[2:3]
+; GFX9-NEXT: global_store_dwordx4 v[6:7], v[0:3], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_s_v16i8_v_v:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 2, v1
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 2, v1
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX8-NEXT: v_and_b32_e32 v1, 3, v1
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
-; GFX8-NEXT: v_mov_b32_e32 v3, s5
-; GFX8-NEXT: v_mov_b32_e32 v5, s6
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX8-NEXT: v_mov_b32_e32 v6, s7
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 3, v1
-; GFX8-NEXT: v_mov_b32_e32 v3, 0xff
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[2:3]
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
+; GFX8-NEXT: v_mov_b32_e32 v8, 0xff
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_bfi_b32 v1, v1, 0, v2
-; GFX8-NEXT: v_or_b32_e32 v6, v1, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_mov_b32_e32 v2, s6
-; GFX8-NEXT: v_mov_b32_e32 v3, s7
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v4, 0
-; GFX8-NEXT: v_mov_b32_e32 v5, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[2:3]
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, v1, v8
+; GFX8-NEXT: v_bfi_b32 v1, v1, 0, v7
+; GFX8-NEXT: v_or_b32_e32 v8, v1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v8, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, v8, s[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v6, 0
+; GFX8-NEXT: v_mov_b32_e32 v7, 0
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v5, v8, s[2:3]
+; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_s_v16i8_v_v:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 2, v1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v4
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 2, v1
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX7-NEXT: v_and_b32_e32 v1, 3, v1
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v2, s4
-; GFX7-NEXT: v_mov_b32_e32 v3, s5
-; GFX7-NEXT: v_mov_b32_e32 v5, s6
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX7-NEXT: v_mov_b32_e32 v6, s7
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v4
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v2, v3, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v6
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v4, s[0:1]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v6
; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[2:3]
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[2:3]
; GFX7-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; GFX7-NEXT: v_lshl_b32_e32 v1, 0xff, v1
-; GFX7-NEXT: v_bfi_b32 v1, v1, 0, v2
-; GFX7-NEXT: v_or_b32_e32 v5, v1, v0
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-NEXT: v_mov_b32_e32 v1, s5
-; GFX7-NEXT: v_mov_b32_e32 v2, s6
-; GFX7-NEXT: v_mov_b32_e32 v3, s7
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[2:3]
+; GFX7-NEXT: v_bfi_b32 v1, v1, 0, v7
+; GFX7-NEXT: v_or_b32_e32 v7, v1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, v7, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v7, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v4, v7, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[2:3]
; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000
@@ -3323,70 +3084,66 @@ define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8
;
; GFX10-LABEL: insertelement_s_v16i8_v_v:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 2, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 3, v1
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v2
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v6
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v6
-; GFX10-NEXT: s_mov_b32 null, 0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
-; GFX10-NEXT: v_lshlrev_b32_e64 v3, v2, 0xff
-; GFX10-NEXT: v_lshlrev_b32_sdwa v4, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-NEXT: v_not_b32_e32 v5, v3
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
+; GFX10-NEXT: v_lshrrev_b32_e32 v7, 2, v1
+; GFX10-NEXT: v_and_b32_e32 v5, 3, v1
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 3, v5
+; GFX10-NEXT: v_lshlrev_b32_e64 v8, v5, 0xff
+; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-NEXT: v_not_b32_e32 v5, v8
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v1, s4, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v1, s7, s1
-; GFX10-NEXT: v_mov_b32_e32 v0, s4
-; GFX10-NEXT: v_mov_b32_e32 v1, s5
-; GFX10-NEXT: v_mov_b32_e32 v2, s6
-; GFX10-NEXT: v_mov_b32_e32 v3, s7
-; GFX10-NEXT: v_and_or_b32 v7, v7, v5, v4
-; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: v_mov_b32_e32 v4, s3
+; GFX10-NEXT: v_mov_b32_e32 v2, s1
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_mov_b32_e32 v3, s2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v7
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v7
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v3, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v4, s1
+; GFX10-NEXT: v_and_or_b32 v8, v6, v5, v0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
-; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
+; GFX10-NEXT: v_mov_b32_e32 v6, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, v8, s2
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, v8, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, v8, s1
+; GFX10-NEXT: global_store_dwordx4 v[5:6], v[0:3], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_s_v16i8_v_v:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 2, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 3, v1
+; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 2, v1
+; GFX11-NEXT: v_and_b32_e32 v5, 3, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v6
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v6
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_lshlrev_b32 v2, 3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, s4, v1, vcc_lo
-; GFX11-NEXT: v_lshlrev_b32_e64 v3, v2, 0xff
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, v2, v0
+; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 3, v5
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v7
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v7
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v1, v2, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e64 v8, v5, 0xff
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, v5, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, s0
-; GFX11-NEXT: v_not_b32_e32 v5, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v1, s7, s1
-; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX11-NEXT: v_mov_b32_e32 v3, s7
-; GFX11-NEXT: v_and_or_b32 v7, v7, v5, v4
-; GFX11-NEXT: v_mov_b32_e32 v2, s6
-; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v7, s1
-; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v3, s0
+; GFX11-NEXT: v_not_b32_e32 v5, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v4, s1
+; GFX11-NEXT: v_and_or_b32 v8, v6, v5, v0
+; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, v8, s2
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, v8, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, v8, s1
+; GFX11-NEXT: global_store_b128 v[5:6], v[0:3], off
; GFX11-NEXT: s_endpgm
%vec = load <16 x i8>, ptr addrspace(4) %ptr
%insert = insertelement <16 x i8> %vec, i8 %val, i32 %idx
@@ -3553,145 +3310,103 @@ define amdgpu_ps void @insertelement_v_v16i8_v_s(ptr addrspace(1) %ptr, i8 %val,
; GFX9-LABEL: insertelement_v_v16i8_v_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
-; GFX9-NEXT: s_and_b32 s0, s2, 3
-; GFX9-NEXT: s_lshr_b32 s4, s2, 2
-; GFX9-NEXT: s_lshl_b32 s0, s0, 3
-; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: s_lshl_b32 s0, 0xff, s0
-; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
-; GFX9-NEXT: s_not_b32 s5, s0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
-; GFX9-NEXT: v_mov_b32_e32 v7, 0
-; GFX9-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-NEXT: s_and_b32 s1, s2, 3
+; GFX9-NEXT: s_lshl_b32 s1, s1, 3
+; GFX9-NEXT: s_lshr_b32 s0, s2, 2
+; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: s_lshl_b32 s1, 0xff, s1
+; GFX9-NEXT: s_not_b32 s1, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3]
-; GFX9-NEXT: v_and_or_b32 v9, v1, s5, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v9, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v9, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v9, s[2:3]
-; GFX9-NEXT: global_store_dwordx4 v[7:8], v[0:3], off
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
+; GFX9-NEXT: v_mov_b32_e32 v1, v3
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: v_and_or_b32 v2, v1, s1, v0
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GFX9-NEXT: v_mov_b32_e32 v3, v2
+; GFX9-NEXT: s_set_gpr_idx_off
+; GFX9-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX9-NEXT: s_endpgm
;
; GFX8-LABEL: insertelement_v_v16i8_v_s:
; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1]
-; GFX8-NEXT: s_lshr_b32 s4, s2, 2
; GFX8-NEXT: s_and_b32 s0, s2, 3
+; GFX8-NEXT: s_lshr_b32 m0, s2, 2
; GFX8-NEXT: s_lshl_b32 s0, s0, 3
-; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: s_lshl_b32 s5, 0xff, s0
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
+; GFX8-NEXT: s_lshl_b32 s0, 0xff, s0
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_mov_b32_e32 v7, 0
-; GFX8-NEXT: v_mov_b32_e32 v8, 0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3]
-; GFX8-NEXT: v_bfi_b32 v1, s5, 0, v1
-; GFX8-NEXT: v_or_b32_e32 v9, v1, v0
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v3, v9, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v5, v9, s[0:1]
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v6, v9, s[2:3]
-; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[0:3]
+; GFX8-NEXT: v_movrels_b32_e32 v1, v3
+; GFX8-NEXT: v_bfi_b32 v1, s0, 0, v1
+; GFX8-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NEXT: v_movreld_b32_e32 v3, v2
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[3:6]
; GFX8-NEXT: s_endpgm
;
; GFX7-LABEL: insertelement_v_v16i8_v_s:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b64 s[8:9], 0
-; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_lshr_b32 s4, s2, 2
+; GFX7-NEXT: s_mov_b32 s6, 0
+; GFX7-NEXT: s_mov_b32 s7, 0xf000
+; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[4:7], 0 addr64
; GFX7-NEXT: s_and_b32 s0, s2, 3
+; GFX7-NEXT: s_lshr_b32 m0, s2, 2
; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v2
; GFX7-NEXT: s_lshl_b32 s0, s0, 3
-; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1
; GFX7-NEXT: v_lshlrev_b32_e32 v0, s0, v0
-; GFX7-NEXT: s_lshl_b32 s5, 0xff, s0
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, 2
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, 3
-; GFX7-NEXT: s_mov_b64 s[8:9], 0
-; GFX7-NEXT: s_mov_b32 s10, -1
+; GFX7-NEXT: s_lshl_b32 s0, 0xff, s0
+; GFX7-NEXT: s_mov_b64 s[4:5], 0
+; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3]
-; GFX7-NEXT: v_bfi_b32 v1, s5, 0, v1
-; GFX7-NEXT: v_or_b32_e32 v7, v1, v0
-; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 0
-; GFX7-NEXT: v_cndmask_b32_e64 v0, v3, v7, s[4:5]
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e64 v2, v5, v7, s[0:1]
-; GFX7-NEXT: v_cndmask_b32_e64 v3, v6, v7, s[2:3]
-; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX7-NEXT: v_movrels_b32_e32 v1, v3
+; GFX7-NEXT: v_bfi_b32 v1, s0, 0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX7-NEXT: v_movreld_b32_e32 v3, v0
+; GFX7-NEXT: buffer_store_dwordx4 v[3:6], off, s[4:7], 0
; GFX7-NEXT: s_endpgm
;
; GFX10-LABEL: insertelement_v_v16i8_v_s:
; GFX10: ; %bb.0:
; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
-; GFX10-NEXT: s_lshr_b32 s3, s2, 2
-; GFX10-NEXT: s_and_b32 s1, s2, 3
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, 2
-; GFX10-NEXT: s_lshl_b32 s2, s1, 3
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s3, 3
-; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-NEXT: s_lshl_b32 s2, 0xff, s2
-; GFX10-NEXT: v_mov_b32_e32 v7, 0
-; GFX10-NEXT: s_not_b32 s2, s2
-; GFX10-NEXT: v_mov_b32_e32 v8, 0
+; GFX10-NEXT: s_and_b32 s0, s2, 3
+; GFX10-NEXT: s_lshr_b32 m0, s2, 2
+; GFX10-NEXT: s_lshl_b32 s0, s0, 3
+; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-NEXT: s_lshl_b32 s0, 0xff, s0
+; GFX10-NEXT: s_not_b32 s0, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s1
-; GFX10-NEXT: v_and_or_b32 v9, v0, s2, v1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s2, s3, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, v9, s2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v9, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v6, v9, s1
-; GFX10-NEXT: global_store_dwordx4 v[7:8], v[0:3], off
+; GFX10-NEXT: v_movrels_b32_e32 v0, v3
+; GFX10-NEXT: v_and_or_b32 v2, v0, s0, v1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_movreld_b32_e32 v3, v2
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: insertelement_v_v16i8_v_s:
; GFX11: ; %bb.0:
; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
-; GFX11-NEXT: s_lshr_b32 s3, s2, 2
-; GFX11-NEXT: s_and_b32 s1, s2, 3
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s3, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s3, 2
-; GFX11-NEXT: s_lshl_b32 s2, s1, 3
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s3, 3
-; GFX11-NEXT: v_mov_b32_e32 v7, 0
-; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v1, 0xff, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, s2, v1
-; GFX11-NEXT: s_lshl_b32 s2, 0xff, s2
-; GFX11-NEXT: s_not_b32 s2, s2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v2
+; GFX11-NEXT: s_and_b32 s0, s2, 3
+; GFX11-NEXT: s_lshr_b32 m0, s2, 2
+; GFX11-NEXT: s_lshl_b32 s0, s0, 3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, s0, v0
+; GFX11-NEXT: s_lshl_b32 s0, 0xff, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_not_b32 s0, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v5, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v6, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_or_b32 v9, v0, s2, v1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s2, s3, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo
+; GFX11-NEXT: v_movrels_b32_e32 v1, v3
+; GFX11-NEXT: v_and_or_b32 v2, v1, s0, v0
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v3, v9, s2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v5, v9, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v6, v9, s1
-; GFX11-NEXT: global_store_b128 v[7:8], v[0:3], off
+; GFX11-NEXT: v_movreld_b32_e32 v3, v2
+; GFX11-NEXT: global_store_b128 v[0:1], v[3:6], off
; GFX11-NEXT: s_endpgm
%vec = load <16 x i8>, ptr addrspace(1) %ptr
%insert = insertelement <16 x i8> %vec, i8 %val, i32 %idx
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
index d4f7fc2bc6bb0..d0873872a684d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
@@ -1,31 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GPRIDX %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
-; RUN: not --crash llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
-
-; FIXME: Need constant bus fixup pre-gfx10 for movrel
-; ERR: Bad machine code: VOP* instruction violates constant bus restriction
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GPRIDX %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
define amdgpu_ps <8 x i32> @dyn_insertelement_v8i32_s_s_s(<8 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8i32_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 0
-; GPRIDX-NEXT: s_cselect_b32 s0, s10, s2
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 1
-; GPRIDX-NEXT: s_cselect_b32 s1, s10, s3
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 2
-; GPRIDX-NEXT: s_cselect_b32 s2, s10, s4
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 3
-; GPRIDX-NEXT: s_cselect_b32 s3, s10, s5
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 4
-; GPRIDX-NEXT: s_cselect_b32 s4, s10, s6
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 5
-; GPRIDX-NEXT: s_cselect_b32 s5, s10, s7
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 6
-; GPRIDX-NEXT: s_cselect_b32 s6, s10, s8
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 7
-; GPRIDX-NEXT: s_cselect_b32 s7, s10, s9
+; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
+; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
+; GPRIDX-NEXT: s_mov_b32 m0, s11
+; GPRIDX-NEXT: s_nop 0
+; GPRIDX-NEXT: s_movreld_b32 s0, s10
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v8i32_s_s_s:
@@ -41,6 +33,20 @@ define amdgpu_ps <8 x i32> @dyn_insertelement_v8i32_s_s_s(<8 x i32> inreg %vec,
; GFX10PLUS-NEXT: s_mov_b32 s7, s9
; GFX10PLUS-NEXT: s_movreld_b32 s0, s10
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8i32_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 m0, s11
+; GFX8-NEXT: s_movreld_b32 s0, s10
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x i32> %vec, i32 %val, i32 %idx
ret <8 x i32> %insert
@@ -49,22 +55,17 @@ entry:
define amdgpu_ps <8 x ptr addrspace(3)> @dyn_insertelement_v8p3i8_s_s_s(<8 x ptr addrspace(3)> inreg %vec, ptr addrspace(3) inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8p3i8_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 0
-; GPRIDX-NEXT: s_cselect_b32 s0, s10, s2
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 1
-; GPRIDX-NEXT: s_cselect_b32 s1, s10, s3
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 2
-; GPRIDX-NEXT: s_cselect_b32 s2, s10, s4
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 3
-; GPRIDX-NEXT: s_cselect_b32 s3, s10, s5
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 4
-; GPRIDX-NEXT: s_cselect_b32 s4, s10, s6
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 5
-; GPRIDX-NEXT: s_cselect_b32 s5, s10, s7
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 6
-; GPRIDX-NEXT: s_cselect_b32 s6, s10, s8
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 7
-; GPRIDX-NEXT: s_cselect_b32 s7, s10, s9
+; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
+; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
+; GPRIDX-NEXT: s_mov_b32 m0, s11
+; GPRIDX-NEXT: s_nop 0
+; GPRIDX-NEXT: s_movreld_b32 s0, s10
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v8p3i8_s_s_s:
@@ -80,6 +81,20 @@ define amdgpu_ps <8 x ptr addrspace(3)> @dyn_insertelement_v8p3i8_s_s_s(<8 x ptr
; GFX10PLUS-NEXT: s_mov_b32 s7, s9
; GFX10PLUS-NEXT: s_movreld_b32 s0, s10
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8p3i8_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 m0, s11
+; GFX8-NEXT: s_movreld_b32 s0, s10
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x ptr addrspace(3)> %vec, ptr addrspace(3) %val, i32 %idx
ret <8 x ptr addrspace(3)> %insert
@@ -158,6 +173,34 @@ define <8 x float> @dyn_insertelement_v8f32_const_s_v_v(float %val, i32 %idx) {
; GFX11-NEXT: v_mov_b32_e32 v1, v9
; GFX11-NEXT: v_dual_cndmask_b32 v7, 0x41000000, v0 :: v_dual_mov_b32 v0, v8
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_const_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v8, 1.0, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x40400000
+; GFX8-NEXT: v_cndmask_b32_e32 v9, 2.0, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x40a00000
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 4.0, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v1
+; GFX8-NEXT: v_mov_b32_e32 v5, 0x40c00000
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v1
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x40e00000
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v1
+; GFX8-NEXT: v_mov_b32_e32 v7, 0x41000000
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, v8
+; GFX8-NEXT: v_mov_b32_e32 v1, v9
+; GFX8-NEXT: s_setpc_b64 s[30:31]
entry:
%insert = insertelement <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, float %val, i32 %idx
ret <8 x float> %insert
@@ -166,76 +209,118 @@ entry:
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_v(<8 x float> inreg %vec, float inreg %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_s_s_v:
; GPRIDX: ; %bb.0: ; %entry
+; GPRIDX-NEXT: v_mov_b32_e32 v7, s10
; GPRIDX-NEXT: v_mov_b32_e32 v1, s2
-; GPRIDX-NEXT: v_mov_b32_e32 v10, s10
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GPRIDX-NEXT: v_mov_b32_e32 v2, s3
-; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v1, v10, vcc
+; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v1, v7, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GPRIDX-NEXT: v_mov_b32_e32 v3, s4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc
+; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GPRIDX-NEXT: v_mov_b32_e32 v4, s5
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v3, v10, vcc
+; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GPRIDX-NEXT: v_mov_b32_e32 v5, s6
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v4, v10, vcc
+; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GPRIDX-NEXT: v_mov_b32_e32 v6, s7
-; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v5, v10, vcc
+; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
-; GPRIDX-NEXT: v_mov_b32_e32 v7, s8
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc
+; GPRIDX-NEXT: v_mov_b32_e32 v9, s8
+; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
-; GPRIDX-NEXT: v_mov_b32_e32 v9, s9
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v7, v10, vcc
+; GPRIDX-NEXT: v_mov_b32_e32 v10, s9
+; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v9, v7, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
-; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
+; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: dyn_insertelement_v8f32_s_s_v:
; GFX10: ; %bb.0: ; %entry
-; GFX10-NEXT: v_mov_b32_e32 v7, s10
+; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v8, s2, v7, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v2, s3
+; GFX10-NEXT: v_mov_b32_e32 v3, s4
+; GFX10-NEXT: v_mov_b32_e32 v4, s5
+; GFX10-NEXT: v_mov_b32_e32 v5, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v1, s10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, s3, v7, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v6, s7
+; GFX10-NEXT: v_mov_b32_e32 v7, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v2, s4, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, s10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v3, s5, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, s10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v4, s6, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, s7, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, s10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v6, s8, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX10-NEXT: v_mov_b32_e32 v0, v8
-; GFX10-NEXT: v_cndmask_b32_e32 v7, s9, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, s10, vcc_lo
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v8f32_s_s_v:
; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: v_mov_b32_e32 v7, s10
+; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v8, s2, v7, vcc_lo
+; GFX11-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
+; GFX11-NEXT: v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s7
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v1, s10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v1, s3, v7, vcc_lo
+; GFX11-NEXT: v_mov_b32_e32 v7, s8
+; GFX11-NEXT: v_mov_b32_e32 v9, s9
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v2, s4, v7, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, s10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v3, s5, v7, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, s10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v4, s6, v7, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v5, s10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v5, s7, v7, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, s10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v6, s8, v7, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v7, s10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
-; GFX11-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_cndmask_b32 v7, s9, v7
+; GFX11-NEXT: v_mov_b32_e32 v0, v8
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, s10, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_s_s_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v7, s10
+; GFX8-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v1, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, s4
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
+; GFX8-NEXT: v_mov_b32_e32 v4, s5
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
+; GFX8-NEXT: v_mov_b32_e32 v5, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
+; GFX8-NEXT: v_mov_b32_e32 v6, s7
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
+; GFX8-NEXT: v_mov_b32_e32 v9, s8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
+; GFX8-NEXT: v_mov_b32_e32 v10, s9
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, v8
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -244,31 +329,26 @@ entry:
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_s(<8 x float> inreg %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_s_v_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: v_mov_b32_e32 v1, s2
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s10, 0
-; GPRIDX-NEXT: v_mov_b32_e32 v2, s3
-; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v1, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s10, 1
-; GPRIDX-NEXT: v_mov_b32_e32 v3, s4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s10, 2
-; GPRIDX-NEXT: v_mov_b32_e32 v4, s5
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v3, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s10, 3
-; GPRIDX-NEXT: v_mov_b32_e32 v5, s6
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s10, 4
-; GPRIDX-NEXT: v_mov_b32_e32 v6, s7
-; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v5, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s10, 5
-; GPRIDX-NEXT: v_mov_b32_e32 v7, s8
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v6, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s10, 6
-; GPRIDX-NEXT: v_mov_b32_e32 v9, s9
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v7, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s10, 7
-; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v9, v0, vcc
+; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
+; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
+; GPRIDX-NEXT: v_mov_b32_e32 v8, v0
+; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
+; GPRIDX-NEXT: v_mov_b32_e32 v1, s1
+; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
+; GPRIDX-NEXT: v_mov_b32_e32 v3, s3
+; GPRIDX-NEXT: v_mov_b32_e32 v4, s4
+; GPRIDX-NEXT: v_mov_b32_e32 v5, s5
+; GPRIDX-NEXT: v_mov_b32_e32 v6, s6
+; GPRIDX-NEXT: v_mov_b32_e32 v7, s7
+; GPRIDX-NEXT: s_set_gpr_idx_on s10, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
+; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: dyn_insertelement_v8f32_s_v_s:
@@ -312,6 +392,29 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_s(<8 x float> inreg %v
; GFX11-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v6, s6
; GFX11-NEXT: v_movreld_b32_e32 v0, v8
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: v_mov_b32_e32 v8, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: s_mov_b32 m0, s10
+; GFX8-NEXT: v_movreld_b32_e32 v0, v8
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -321,22 +424,9 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_s(<8 x float> %vec, fl
; GPRIDX-LABEL: dyn_insertelement_v8f32_v_s_s:
; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: v_mov_b32_e32 v8, s2
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
-; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s3, 1
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s3, 2
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s3, 3
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s3, 4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s3, 5
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s3, 6
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s3, 7
-; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GPRIDX-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST)
+; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
+; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_s_s:
@@ -344,6 +434,13 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_s(<8 x float> %vec, fl
; GFX10PLUS-NEXT: s_mov_b32 m0, s3
; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, s2
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_v_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v8, s2
+; GFX8-NEXT: s_mov_b32 m0, s3
+; GFX8-NEXT: v_movreld_b32_e32 v0, v8
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -422,6 +519,36 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_v(<8 x float> inreg %v
; GFX11-NEXT: v_mov_b32_e32 v1, v9
; GFX11-NEXT: v_dual_cndmask_b32 v7, s9, v0 :: v_dual_mov_b32 v0, v8
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v2, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v3, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v1
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v1
+; GFX8-NEXT: v_mov_b32_e32 v10, s8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v1
+; GFX8-NEXT: v_mov_b32_e32 v11, s9
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v0, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, v8
+; GFX8-NEXT: v_mov_b32_e32 v1, v9
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -468,6 +595,27 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_v(<8 x float> %vec, fl
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v8
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v7, v7, s2, vcc_lo
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_v_s_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v9, s2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -476,22 +624,9 @@ entry:
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_s(<8 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 2
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 3
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 5
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 6
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 7
-; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST)
+; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
+; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_v_s:
@@ -499,6 +634,12 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_s(<8 x float> %vec, fl
; GFX10PLUS-NEXT: s_mov_b32 m0, s2
; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v8
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 m0, s2
+; GFX8-NEXT: v_movreld_b32_e32 v0, v8
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -507,22 +648,9 @@ entry:
define amdgpu_ps <8 x float> @dyn_insertelement_v8p3i8_v_v_s(<8 x ptr addrspace(3)> %vec, ptr addrspace(3) %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8p3i8_v_v_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 2
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 3
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 5
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 6
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 7
-; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST)
+; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
+; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v8p3i8_v_v_s:
@@ -530,6 +658,12 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8p3i8_v_v_s(<8 x ptr addrspace(
; GFX10PLUS-NEXT: s_mov_b32 m0, s2
; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v8
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8p3i8_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 m0, s2
+; GFX8-NEXT: v_movreld_b32_e32 v0, v8
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x ptr addrspace(3)> %vec, ptr addrspace(3) %val, i32 %idx
%cast.0 = ptrtoint <8 x ptr addrspace(3)> %insert to <8 x i32>
@@ -577,6 +711,26 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v(<8 x float> %vec, fl
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_v_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -585,48 +739,63 @@ entry:
define amdgpu_ps <8 x i64> @dyn_insertelement_v8i64_s_s_s(<8 x i64> inreg %vec, i64 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8i64_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s0, s2
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s2, s4
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s4, s6
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s6, s8
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s8, s10
-; GPRIDX-NEXT: s_mov_b32 s9, s11
-; GPRIDX-NEXT: s_mov_b32 s10, s12
-; GPRIDX-NEXT: s_mov_b32 s11, s13
-; GPRIDX-NEXT: s_mov_b32 s12, s14
-; GPRIDX-NEXT: s_mov_b32 s13, s15
-; GPRIDX-NEXT: s_mov_b32 s14, s16
-; GPRIDX-NEXT: s_mov_b32 s15, s17
-; GPRIDX-NEXT: s_mov_b32 m0, s20
-; GPRIDX-NEXT: s_nop 0
-; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[18:19]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 0
+; GPRIDX-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 1
+; GPRIDX-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 2
+; GPRIDX-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 3
+; GPRIDX-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 4
+; GPRIDX-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 5
+; GPRIDX-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 6
+; GPRIDX-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 7
+; GPRIDX-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v8i64_s_s_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: s_mov_b32 s0, s2
-; GFX10PLUS-NEXT: s_mov_b32 s1, s3
-; GFX10PLUS-NEXT: s_mov_b32 m0, s20
-; GFX10PLUS-NEXT: s_mov_b32 s2, s4
-; GFX10PLUS-NEXT: s_mov_b32 s3, s5
-; GFX10PLUS-NEXT: s_mov_b32 s4, s6
-; GFX10PLUS-NEXT: s_mov_b32 s5, s7
-; GFX10PLUS-NEXT: s_mov_b32 s6, s8
-; GFX10PLUS-NEXT: s_mov_b32 s7, s9
-; GFX10PLUS-NEXT: s_mov_b32 s8, s10
-; GFX10PLUS-NEXT: s_mov_b32 s9, s11
-; GFX10PLUS-NEXT: s_mov_b32 s10, s12
-; GFX10PLUS-NEXT: s_mov_b32 s11, s13
-; GFX10PLUS-NEXT: s_mov_b32 s12, s14
-; GFX10PLUS-NEXT: s_mov_b32 s13, s15
-; GFX10PLUS-NEXT: s_mov_b32 s14, s16
-; GFX10PLUS-NEXT: s_mov_b32 s15, s17
-; GFX10PLUS-NEXT: s_movreld_b64 s[0:1], s[18:19]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 0
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 1
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 2
+; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 3
+; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 4
+; GFX10PLUS-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 5
+; GFX10PLUS-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 6
+; GFX10PLUS-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 7
+; GFX10PLUS-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8i64_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_cmp_eq_u32 s20, 0
+; GFX8-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 1
+; GFX8-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 2
+; GFX8-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 3
+; GFX8-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 4
+; GFX8-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 5
+; GFX8-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 6
+; GFX8-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 7
+; GFX8-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x i64> %vec, i64 %val, i32 %idx
ret <8 x i64> %insert
@@ -635,48 +804,63 @@ entry:
define amdgpu_ps <8 x ptr addrspace(1)> @dyn_insertelement_v8p1i8_s_s_s(<8 x ptr addrspace(1)> inreg %vec, ptr addrspace(1) inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8p1i8_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s0, s2
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s2, s4
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s4, s6
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s6, s8
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s8, s10
-; GPRIDX-NEXT: s_mov_b32 s9, s11
-; GPRIDX-NEXT: s_mov_b32 s10, s12
-; GPRIDX-NEXT: s_mov_b32 s11, s13
-; GPRIDX-NEXT: s_mov_b32 s12, s14
-; GPRIDX-NEXT: s_mov_b32 s13, s15
-; GPRIDX-NEXT: s_mov_b32 s14, s16
-; GPRIDX-NEXT: s_mov_b32 s15, s17
-; GPRIDX-NEXT: s_mov_b32 m0, s20
-; GPRIDX-NEXT: s_nop 0
-; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[18:19]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 0
+; GPRIDX-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 1
+; GPRIDX-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 2
+; GPRIDX-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 3
+; GPRIDX-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 4
+; GPRIDX-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 5
+; GPRIDX-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 6
+; GPRIDX-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 7
+; GPRIDX-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v8p1i8_s_s_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: s_mov_b32 s0, s2
-; GFX10PLUS-NEXT: s_mov_b32 s1, s3
-; GFX10PLUS-NEXT: s_mov_b32 m0, s20
-; GFX10PLUS-NEXT: s_mov_b32 s2, s4
-; GFX10PLUS-NEXT: s_mov_b32 s3, s5
-; GFX10PLUS-NEXT: s_mov_b32 s4, s6
-; GFX10PLUS-NEXT: s_mov_b32 s5, s7
-; GFX10PLUS-NEXT: s_mov_b32 s6, s8
-; GFX10PLUS-NEXT: s_mov_b32 s7, s9
-; GFX10PLUS-NEXT: s_mov_b32 s8, s10
-; GFX10PLUS-NEXT: s_mov_b32 s9, s11
-; GFX10PLUS-NEXT: s_mov_b32 s10, s12
-; GFX10PLUS-NEXT: s_mov_b32 s11, s13
-; GFX10PLUS-NEXT: s_mov_b32 s12, s14
-; GFX10PLUS-NEXT: s_mov_b32 s13, s15
-; GFX10PLUS-NEXT: s_mov_b32 s14, s16
-; GFX10PLUS-NEXT: s_mov_b32 s15, s17
-; GFX10PLUS-NEXT: s_movreld_b64 s[0:1], s[18:19]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 0
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 1
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 2
+; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 3
+; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 4
+; GFX10PLUS-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 5
+; GFX10PLUS-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 6
+; GFX10PLUS-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 7
+; GFX10PLUS-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8p1i8_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_cmp_eq_u32 s20, 0
+; GFX8-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 1
+; GFX8-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 2
+; GFX8-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 3
+; GFX8-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 4
+; GFX8-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 5
+; GFX8-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 6
+; GFX8-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 7
+; GFX8-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x ptr addrspace(1)> %vec, ptr addrspace(1) %val, i32 %idx
ret <8 x ptr addrspace(1)> %insert
@@ -868,6 +1052,72 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GFX11-NEXT: global_store_b128 v[0:1], v[15:18], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: dyn_insertelement_v8f64_const_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b64 s[4:5], 1.0
+; GFX8-NEXT: s_mov_b32 s18, 0
+; GFX8-NEXT: s_mov_b32 s19, 0x40200000
+; GFX8-NEXT: s_mov_b32 s16, 0
+; GFX8-NEXT: s_mov_b32 s17, 0x401c0000
+; GFX8-NEXT: s_mov_b32 s14, 0
+; GFX8-NEXT: s_mov_b32 s15, 0x40180000
+; GFX8-NEXT: s_mov_b32 s12, 0
+; GFX8-NEXT: s_mov_b32 s13, 0x40140000
+; GFX8-NEXT: s_mov_b64 s[10:11], 4.0
+; GFX8-NEXT: s_mov_b32 s8, 0
+; GFX8-NEXT: s_mov_b32 s9, 0x40080000
+; GFX8-NEXT: s_mov_b64 s[6:7], 2.0
+; GFX8-NEXT: v_mov_b32_e32 v3, s4
+; GFX8-NEXT: v_mov_b32_e32 v4, s5
+; GFX8-NEXT: v_mov_b32_e32 v5, s6
+; GFX8-NEXT: v_mov_b32_e32 v6, s7
+; GFX8-NEXT: v_mov_b32_e32 v7, s8
+; GFX8-NEXT: v_mov_b32_e32 v8, s9
+; GFX8-NEXT: v_mov_b32_e32 v9, s10
+; GFX8-NEXT: v_mov_b32_e32 v10, s11
+; GFX8-NEXT: v_mov_b32_e32 v11, s12
+; GFX8-NEXT: v_mov_b32_e32 v12, s13
+; GFX8-NEXT: v_mov_b32_e32 v13, s14
+; GFX8-NEXT: v_mov_b32_e32 v14, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s16
+; GFX8-NEXT: v_mov_b32_e32 v16, s17
+; GFX8-NEXT: v_mov_b32_e32 v17, s18
+; GFX8-NEXT: v_mov_b32_e32 v18, s19
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[16:17], 0, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 2, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 3, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 4, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 5, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 6, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 7, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v0, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v0, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v0, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v17, v17, v0, s[14:15]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, v1, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, v1, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, v1, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, v1, s[14:15]
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[3:6]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[7:10]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[11:14]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[15:18]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_setpc_b64 s[30:31]
entry:
%insert = insertelement <8 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0>, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
@@ -1079,6 +1329,76 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do
; GFX11-NEXT: global_store_b128 v[0:1], v[13:16], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_endpgm
+;
+; GFX8-LABEL: dyn_insertelement_v8f64_s_s_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: v_mov_b32_e32 v14, s13
+; GFX8-NEXT: v_mov_b32_e32 v13, s12
+; GFX8-NEXT: v_mov_b32_e32 v12, s11
+; GFX8-NEXT: v_mov_b32_e32 v11, s10
+; GFX8-NEXT: v_mov_b32_e32 v10, s9
+; GFX8-NEXT: v_mov_b32_e32 v9, s8
+; GFX8-NEXT: v_mov_b32_e32 v8, s7
+; GFX8-NEXT: v_mov_b32_e32 v7, s6
+; GFX8-NEXT: v_mov_b32_e32 v6, s5
+; GFX8-NEXT: v_mov_b32_e32 v5, s4
+; GFX8-NEXT: v_mov_b32_e32 v4, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_mov_b32_e32 v17, s18
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s19
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v0, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v17, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v17, s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v17, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v0, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, v0, s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, v0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, v0, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, v0, s[10:11]
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[1:4]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[5:8]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[9:12]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[13:16]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
@@ -1227,6 +1547,53 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_s(<8 x double> inreg %vec, do
; GFX11-NEXT: global_store_b128 v[0:1], v[14:17], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_endpgm
+;
+; GFX8-LABEL: dyn_insertelement_v8f64_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: v_mov_b32_e32 v17, s15
+; GFX8-NEXT: v_mov_b32_e32 v16, s14
+; GFX8-NEXT: v_mov_b32_e32 v15, s13
+; GFX8-NEXT: v_mov_b32_e32 v14, s12
+; GFX8-NEXT: v_mov_b32_e32 v13, s11
+; GFX8-NEXT: v_mov_b32_e32 v12, s10
+; GFX8-NEXT: v_mov_b32_e32 v11, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: s_lshl_b32 m0, s18, 1
+; GFX8-NEXT: v_movreld_b32_e32 v2, v0
+; GFX8-NEXT: v_movreld_b32_e32 v3, v1
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[6:9]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[10:13]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[14:17]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
@@ -1244,9 +1611,13 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_s(<8 x double> %vec, double i
; GPRIDX-LABEL: dyn_insertelement_v8f64_v_s_s:
; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_lshl_b32 s0, s4, 1
+; GPRIDX-NEXT: v_mov_b32_e32 v16, s2
+; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GPRIDX-NEXT: v_mov_b32_e32 v0, v16
+; GPRIDX-NEXT: s_set_gpr_idx_off
+; GPRIDX-NEXT: v_mov_b32_e32 v17, s3
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
-; GPRIDX-NEXT: v_mov_b32_e32 v0, s2
-; GPRIDX-NEXT: v_mov_b32_e32 v1, s3
+; GPRIDX-NEXT: v_mov_b32_e32 v1, v17
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
@@ -1287,6 +1658,23 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_s(<8 x double> %vec, double i
; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_endpgm
+;
+; GFX8-LABEL: dyn_insertelement_v8f64_v_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v16, s2
+; GFX8-NEXT: s_lshl_b32 m0, s4, 1
+; GFX8-NEXT: v_mov_b32_e32 v17, s3
+; GFX8-NEXT: v_movreld_b32_e32 v0, v16
+; GFX8-NEXT: v_movreld_b32_e32 v1, v17
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
@@ -1492,6 +1880,74 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
; GFX11-NEXT: global_store_b128 v[0:1], v[15:18], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_endpgm
+;
+; GFX8-LABEL: dyn_insertelement_v8f64_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: v_mov_b32_e32 v18, s15
+; GFX8-NEXT: v_mov_b32_e32 v17, s14
+; GFX8-NEXT: v_mov_b32_e32 v16, s13
+; GFX8-NEXT: v_mov_b32_e32 v15, s12
+; GFX8-NEXT: v_mov_b32_e32 v14, s11
+; GFX8-NEXT: v_mov_b32_e32 v13, s10
+; GFX8-NEXT: v_mov_b32_e32 v12, s9
+; GFX8-NEXT: v_mov_b32_e32 v11, s8
+; GFX8-NEXT: v_mov_b32_e32 v10, s7
+; GFX8-NEXT: v_mov_b32_e32 v9, s6
+; GFX8-NEXT: v_mov_b32_e32 v8, s5
+; GFX8-NEXT: v_mov_b32_e32 v7, s4
+; GFX8-NEXT: v_mov_b32_e32 v6, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s2
+; GFX8-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v0, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v0, s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v0, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v17, v17, v0, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, v1, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, v1, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, v1, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, v1, s[10:11]
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[3:6]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[7:10]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[11:14]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[15:18]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
@@ -1615,6 +2071,44 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_v(<8 x double> %vec, double i
; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_endpgm
+;
+; GFX8-LABEL: dyn_insertelement_v8f64_v_s_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v17, s2
+; GFX8-NEXT: v_mov_b32_e32 v18, s3
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v18, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v18, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v18, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v18, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v18, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v18, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
@@ -1675,6 +2169,21 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_s(<8 x double> %vec, double %
; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_endpgm
+;
+; GFX8-LABEL: dyn_insertelement_v8f64_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_lshl_b32 m0, s2, 1
+; GFX8-NEXT: v_movreld_b32_e32 v0, v16
+; GFX8-NEXT: v_movreld_b32_e32 v1, v17
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
@@ -1792,6 +2301,42 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v(<8 x double> %vec, double %
; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_endpgm
+;
+; GFX8-LABEL: dyn_insertelement_v8f64_v_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> poison, <2 x i32> <i32 0, i32 1>
@@ -1808,23 +2353,31 @@ entry:
define amdgpu_ps <3 x i32> @dyn_insertelement_v3i32_s_s_s(<3 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v3i32_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_cmp_eq_u32 s6, 0
-; GPRIDX-NEXT: s_cselect_b32 s0, s5, s2
-; GPRIDX-NEXT: s_cmp_eq_u32 s6, 1
-; GPRIDX-NEXT: s_cselect_b32 s1, s5, s3
-; GPRIDX-NEXT: s_cmp_eq_u32 s6, 2
-; GPRIDX-NEXT: s_cselect_b32 s2, s5, s4
+; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 m0, s6
+; GPRIDX-NEXT: s_nop 0
+; GPRIDX-NEXT: s_movreld_b32 s0, s5
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v3i32_s_s_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s6, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s0, s5, s2
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s6, 1
-; GFX10PLUS-NEXT: s_cselect_b32 s1, s5, s3
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s6, 2
-; GFX10PLUS-NEXT: s_cselect_b32 s2, s5, s4
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 m0, s6
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_movreld_b32 s0, s5
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v3i32_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 m0, s6
+; GFX8-NEXT: s_movreld_b32 s0, s5
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <3 x i32> %vec, i32 %val, i32 %idx
ret <3 x i32> %insert
@@ -1833,23 +2386,22 @@ entry:
define amdgpu_ps <3 x float> @dyn_insertelement_v3i32_v_v_s(<3 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v3i32_v_v_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 2
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST)
+; GPRIDX-NEXT: v_mov_b32_e32 v0, v3
+; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v3i32_v_v_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX10PLUS-NEXT: s_mov_b32 m0, s2
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v3
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v3i32_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 m0, s2
+; GFX8-NEXT: v_movreld_b32_e32 v0, v3
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <3 x float> %vec, float %val, i32 %idx
ret <3 x float> %insert
@@ -1858,31 +2410,37 @@ entry:
define amdgpu_ps <5 x i32> @dyn_insertelement_v5i32_s_s_s(<5 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5i32_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_cmp_eq_u32 s8, 0
-; GPRIDX-NEXT: s_cselect_b32 s0, s7, s2
-; GPRIDX-NEXT: s_cmp_eq_u32 s8, 1
-; GPRIDX-NEXT: s_cselect_b32 s1, s7, s3
-; GPRIDX-NEXT: s_cmp_eq_u32 s8, 2
-; GPRIDX-NEXT: s_cselect_b32 s2, s7, s4
-; GPRIDX-NEXT: s_cmp_eq_u32 s8, 3
-; GPRIDX-NEXT: s_cselect_b32 s3, s7, s5
-; GPRIDX-NEXT: s_cmp_eq_u32 s8, 4
-; GPRIDX-NEXT: s_cselect_b32 s4, s7, s6
+; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 m0, s8
+; GPRIDX-NEXT: s_nop 0
+; GPRIDX-NEXT: s_movreld_b32 s0, s7
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v5i32_s_s_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s8, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s0, s7, s2
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s8, 1
-; GFX10PLUS-NEXT: s_cselect_b32 s1, s7, s3
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s8, 2
-; GFX10PLUS-NEXT: s_cselect_b32 s2, s7, s4
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s8, 3
-; GFX10PLUS-NEXT: s_cselect_b32 s3, s7, s5
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s8, 4
-; GFX10PLUS-NEXT: s_cselect_b32 s4, s7, s6
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 m0, s8
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_movreld_b32 s0, s7
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v5i32_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 m0, s8
+; GFX8-NEXT: s_movreld_b32 s0, s7
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x i32> %vec, i32 %val, i32 %idx
ret <5 x i32> %insert
@@ -1891,31 +2449,22 @@ entry:
define amdgpu_ps <5 x float> @dyn_insertelement_v5i32_v_v_s(<5 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5i32_v_v_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 2
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 3
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST)
+; GPRIDX-NEXT: v_mov_b32_e32 v0, v5
+; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v5i32_v_v_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 4
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX10PLUS-NEXT: s_mov_b32 m0, s2
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v5
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v5i32_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 m0, s2
+; GFX8-NEXT: v_movreld_b32_e32 v0, v5
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x float> %vec, float %val, i32 %idx
ret <5 x float> %insert
@@ -1998,6 +2547,44 @@ define amdgpu_ps <32 x i32> @dyn_insertelement_v32i32_s_s_s(<32 x i32> inreg %ve
; GFX10PLUS-NEXT: s_mov_b32 s30, s32
; GFX10PLUS-NEXT: s_movreld_b32 s0, s34
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v32i32_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s16, s18
+; GFX8-NEXT: s_mov_b32 s17, s19
+; GFX8-NEXT: s_mov_b32 s18, s20
+; GFX8-NEXT: s_mov_b32 s19, s21
+; GFX8-NEXT: s_mov_b32 s20, s22
+; GFX8-NEXT: s_mov_b32 s21, s23
+; GFX8-NEXT: s_mov_b32 s22, s24
+; GFX8-NEXT: s_mov_b32 s23, s25
+; GFX8-NEXT: s_mov_b32 s24, s26
+; GFX8-NEXT: s_mov_b32 s25, s27
+; GFX8-NEXT: s_mov_b32 s26, s28
+; GFX8-NEXT: s_mov_b32 s27, s29
+; GFX8-NEXT: s_mov_b32 s28, s30
+; GFX8-NEXT: s_mov_b32 s29, s31
+; GFX8-NEXT: s_mov_b32 s31, s33
+; GFX8-NEXT: s_mov_b32 s30, s32
+; GFX8-NEXT: s_mov_b32 m0, s35
+; GFX8-NEXT: s_movreld_b32 s0, s34
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <32 x i32> %vec, i32 %val, i32 %idx
ret <32 x i32> %insert
@@ -2016,6 +2603,12 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32i32_v_v_s(<32 x float> %vec,
; GFX10PLUS-NEXT: s_mov_b32 m0, s2
; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v32
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v32i32_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 m0, s2
+; GFX8-NEXT: v_movreld_b32_e32 v0, v32
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <32 x float> %vec, float %val, i32 %idx
ret <32 x float> %insert
@@ -2024,30 +2617,25 @@ entry:
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_1(<8 x float> inreg %vec, float inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_s_s_s_add_1:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_add_u32 s0, s11, 1
-; GPRIDX-NEXT: s_cselect_b32 s1, s10, s2
-; GPRIDX-NEXT: s_cmp_eq_u32 s0, 1
-; GPRIDX-NEXT: s_cselect_b32 s2, s10, s3
-; GPRIDX-NEXT: s_cmp_eq_u32 s0, 2
-; GPRIDX-NEXT: s_cselect_b32 s3, s10, s4
-; GPRIDX-NEXT: s_cmp_eq_u32 s0, 3
-; GPRIDX-NEXT: s_cselect_b32 s4, s10, s5
-; GPRIDX-NEXT: s_cmp_eq_u32 s0, 4
-; GPRIDX-NEXT: s_cselect_b32 s5, s10, s6
-; GPRIDX-NEXT: s_cmp_eq_u32 s0, 5
-; GPRIDX-NEXT: s_cselect_b32 s6, s10, s7
-; GPRIDX-NEXT: s_cmp_eq_u32 s0, 6
-; GPRIDX-NEXT: s_cselect_b32 s7, s10, s8
-; GPRIDX-NEXT: s_cmp_eq_u32 s0, 7
-; GPRIDX-NEXT: s_cselect_b32 s0, s10, s9
-; GPRIDX-NEXT: v_mov_b32_e32 v0, s1
-; GPRIDX-NEXT: v_mov_b32_e32 v1, s2
-; GPRIDX-NEXT: v_mov_b32_e32 v2, s3
-; GPRIDX-NEXT: v_mov_b32_e32 v3, s4
-; GPRIDX-NEXT: v_mov_b32_e32 v4, s5
-; GPRIDX-NEXT: v_mov_b32_e32 v5, s6
-; GPRIDX-NEXT: v_mov_b32_e32 v6, s7
-; GPRIDX-NEXT: v_mov_b32_e32 v7, s0
+; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
+; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
+; GPRIDX-NEXT: s_mov_b32 m0, s11
+; GPRIDX-NEXT: s_nop 0
+; GPRIDX-NEXT: s_movreld_b32 s1, s10
+; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
+; GPRIDX-NEXT: v_mov_b32_e32 v1, s1
+; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
+; GPRIDX-NEXT: v_mov_b32_e32 v3, s3
+; GPRIDX-NEXT: v_mov_b32_e32 v4, s4
+; GPRIDX-NEXT: v_mov_b32_e32 v5, s5
+; GPRIDX-NEXT: v_mov_b32_e32 v6, s6
+; GPRIDX-NEXT: v_mov_b32_e32 v7, s7
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: dyn_insertelement_v8f32_s_s_s_add_1:
@@ -2089,6 +2677,28 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_1(<8 x float> in
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_s_s_s_add_1:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 m0, s11
+; GFX8-NEXT: s_movreld_b32 s1, s10
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: ; return to shader part epilog
entry:
%idx.add = add i32 %idx, 1
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
@@ -2098,23 +2708,17 @@ entry:
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_7(<8 x float> inreg %vec, float inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_s_s_s_add_7:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_add_i32 s11, s11, 7
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 0
-; GPRIDX-NEXT: s_cselect_b32 s0, s10, s2
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 1
-; GPRIDX-NEXT: s_cselect_b32 s1, s10, s3
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 2
-; GPRIDX-NEXT: s_cselect_b32 s2, s10, s4
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 3
-; GPRIDX-NEXT: s_cselect_b32 s3, s10, s5
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 4
-; GPRIDX-NEXT: s_cselect_b32 s4, s10, s6
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 5
-; GPRIDX-NEXT: s_cselect_b32 s5, s10, s7
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 6
-; GPRIDX-NEXT: s_cselect_b32 s6, s10, s8
-; GPRIDX-NEXT: s_cmp_eq_u32 s11, 7
-; GPRIDX-NEXT: s_cselect_b32 s7, s10, s9
+; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
+; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 s7, s9
+; GPRIDX-NEXT: s_mov_b32 m0, s11
+; GPRIDX-NEXT: s_nop 0
+; GPRIDX-NEXT: s_movreld_b32 s7, s10
; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
; GPRIDX-NEXT: v_mov_b32_e32 v1, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
@@ -2164,6 +2768,28 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_7(<8 x float> in
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_s_s_s_add_7:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 m0, s11
+; GFX8-NEXT: s_movreld_b32 s7, s10
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: ; return to shader part epilog
entry:
%idx.add = add i32 %idx, 7
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
@@ -2212,6 +2838,27 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v_add_1(<8 x float> %v
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_v_v_v_add_1:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 1, v9
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX8-NEXT: ; return to shader part epilog
entry:
%idx.add = add i32 %idx, 1
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
@@ -2260,6 +2907,27 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v_add_7(<8 x float> %v
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v8f32_v_v_v_add_7:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 7, v9
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX8-NEXT: ; return to shader part epilog
entry:
%idx.add = add i32 %idx, 7
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
@@ -2269,41 +2937,38 @@ entry:
define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_s_s_s_add_1:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s0, s2
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s2, s4
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s4, s6
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s6, s8
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s8, s10
-; GPRIDX-NEXT: s_mov_b32 s9, s11
-; GPRIDX-NEXT: s_mov_b32 s10, s12
-; GPRIDX-NEXT: s_mov_b32 s11, s13
-; GPRIDX-NEXT: s_mov_b32 s12, s14
-; GPRIDX-NEXT: s_mov_b32 s13, s15
-; GPRIDX-NEXT: s_mov_b32 s14, s16
-; GPRIDX-NEXT: s_mov_b32 s15, s17
-; GPRIDX-NEXT: s_mov_b32 m0, s20
-; GPRIDX-NEXT: s_nop 0
-; GPRIDX-NEXT: s_movreld_b64 s[2:3], s[18:19]
+; GPRIDX-NEXT: s_add_u32 s20, s20, 1
+; GPRIDX-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 1
+; GPRIDX-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 2
; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
+; GPRIDX-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 3
; GPRIDX-NEXT: v_mov_b32_e32 v1, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
; GPRIDX-NEXT: v_mov_b32_e32 v3, s3
+; GPRIDX-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 4
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
+; GPRIDX-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
; GPRIDX-NEXT: v_mov_b32_e32 v0, s4
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 5
; GPRIDX-NEXT: v_mov_b32_e32 v1, s5
; GPRIDX-NEXT: v_mov_b32_e32 v2, s6
; GPRIDX-NEXT: v_mov_b32_e32 v3, s7
+; GPRIDX-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 6
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
+; GPRIDX-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
; GPRIDX-NEXT: v_mov_b32_e32 v0, s8
+; GPRIDX-NEXT: s_cmp_eq_u32 s20, 7
; GPRIDX-NEXT: v_mov_b32_e32 v1, s9
; GPRIDX-NEXT: v_mov_b32_e32 v2, s10
; GPRIDX-NEXT: v_mov_b32_e32 v3, s11
+; GPRIDX-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: v_mov_b32_e32 v0, s12
@@ -2316,30 +2981,28 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %v
;
; GFX10-LABEL: dyn_insertelement_v8f64_s_s_s_add_1:
; GFX10: ; %bb.0: ; %entry
-; GFX10-NEXT: s_mov_b32 s0, s2
-; GFX10-NEXT: s_mov_b32 s1, s3
-; GFX10-NEXT: s_mov_b32 s2, s4
-; GFX10-NEXT: s_mov_b32 s3, s5
-; GFX10-NEXT: s_mov_b32 m0, s20
-; GFX10-NEXT: s_mov_b32 s4, s6
-; GFX10-NEXT: s_mov_b32 s5, s7
-; GFX10-NEXT: s_mov_b32 s6, s8
-; GFX10-NEXT: s_mov_b32 s7, s9
-; GFX10-NEXT: s_mov_b32 s8, s10
-; GFX10-NEXT: s_mov_b32 s9, s11
-; GFX10-NEXT: s_mov_b32 s10, s12
-; GFX10-NEXT: s_mov_b32 s11, s13
-; GFX10-NEXT: s_mov_b32 s12, s14
-; GFX10-NEXT: s_mov_b32 s13, s15
-; GFX10-NEXT: s_mov_b32 s14, s16
-; GFX10-NEXT: s_mov_b32 s15, s17
-; GFX10-NEXT: s_movreld_b64 s[2:3], s[18:19]
+; GFX10-NEXT: s_add_u32 s20, s20, 1
+; GFX10-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3]
+; GFX10-NEXT: s_cmp_eq_u32 s20, 1
+; GFX10-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
+; GFX10-NEXT: s_cmp_eq_u32 s20, 2
; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
+; GFX10-NEXT: s_cmp_eq_u32 s20, 3
; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GFX10-NEXT: s_cmp_eq_u32 s20, 4
; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GFX10-NEXT: s_cmp_eq_u32 s20, 5
; GFX10-NEXT: v_mov_b32_e32 v3, s3
+; GFX10-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GFX10-NEXT: s_cmp_eq_u32 s20, 6
; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GFX10-NEXT: s_cmp_eq_u32 s20, 7
; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GFX10-NEXT: v_mov_b32_e32 v6, s6
; GFX10-NEXT: v_mov_b32_e32 v7, s7
; GFX10-NEXT: v_mov_b32_e32 v8, s8
@@ -2362,30 +3025,28 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %v
;
; GFX11-LABEL: dyn_insertelement_v8f64_s_s_s_add_1:
; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_mov_b32 s0, s2
-; GFX11-NEXT: s_mov_b32 s1, s3
-; GFX11-NEXT: s_mov_b32 s2, s4
-; GFX11-NEXT: s_mov_b32 s3, s5
-; GFX11-NEXT: s_mov_b32 m0, s20
-; GFX11-NEXT: s_mov_b32 s4, s6
-; GFX11-NEXT: s_mov_b32 s5, s7
-; GFX11-NEXT: s_mov_b32 s6, s8
-; GFX11-NEXT: s_mov_b32 s7, s9
-; GFX11-NEXT: s_mov_b32 s8, s10
-; GFX11-NEXT: s_mov_b32 s9, s11
-; GFX11-NEXT: s_mov_b32 s10, s12
-; GFX11-NEXT: s_mov_b32 s11, s13
-; GFX11-NEXT: s_mov_b32 s12, s14
-; GFX11-NEXT: s_mov_b32 s13, s15
-; GFX11-NEXT: s_mov_b32 s14, s16
-; GFX11-NEXT: s_mov_b32 s15, s17
-; GFX11-NEXT: s_movreld_b64 s[2:3], s[18:19]
+; GFX11-NEXT: s_add_u32 s20, s20, 1
+; GFX11-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3]
+; GFX11-NEXT: s_cmp_eq_u32 s20, 1
+; GFX11-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
+; GFX11-NEXT: s_cmp_eq_u32 s20, 2
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
+; GFX11-NEXT: s_cmp_eq_u32 s20, 3
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GFX11-NEXT: s_cmp_eq_u32 s20, 4
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GFX11-NEXT: s_cmp_eq_u32 s20, 5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GFX11-NEXT: s_cmp_eq_u32 s20, 6
; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
+; GFX11-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GFX11-NEXT: s_cmp_eq_u32 s20, 7
; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
+; GFX11-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
@@ -2397,6 +3058,50 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %v
; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_endpgm
+;
+; GFX8-LABEL: dyn_insertelement_v8f64_s_s_s_add_1:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_add_u32 s20, s20, 1
+; GFX8-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 1
+; GFX8-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 2
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 3
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 4
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11]
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: s_cmp_eq_u32 s20, 5
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13]
+; GFX8-NEXT: s_cmp_eq_u32 s20, 6
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15]
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NEXT: s_cmp_eq_u32 s20, 7
+; GFX8-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NEXT: v_mov_b32_e32 v2, s10
+; GFX8-NEXT: v_mov_b32_e32 v3, s11
+; GFX8-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17]
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NEXT: v_mov_b32_e32 v1, s13
+; GFX8-NEXT: v_mov_b32_e32 v2, s14
+; GFX8-NEXT: v_mov_b32_e32 v3, s15
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
entry:
%idx.add = add i32 %idx, 1
%insert = insertelement <8 x double> %vec, double %val, i32 %idx.add
@@ -2519,6 +3224,43 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, do
; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_endpgm
+;
+; GFX8-LABEL: dyn_insertelement_v8f64_v_v_v_add_1:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_add_u32_e32 v18, vcc, 1, v18
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
entry:
%idx.add = add i32 %idx, 1
%insert = insertelement <8 x double> %vec, double %val, i32 %idx.add
@@ -2604,6 +3346,31 @@ define amdgpu_ps <9 x float> @dyn_insertelement_v9f32_s_v_s(<9 x float> inreg %v
; GFX11-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v8, s8
; GFX11-NEXT: v_movreld_b32_e32 v0, v9
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v9f32_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: v_mov_b32_e32 v9, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: s_mov_b32 m0, s11
+; GFX8-NEXT: v_movreld_b32_e32 v0, v9
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <9 x float> %vec, float %val, i32 %idx
ret <9 x float> %insert
@@ -2689,6 +3456,39 @@ define amdgpu_ps <9 x float> @dyn_insertelement_v9f32_s_v_v(<9 x float> inreg %v
; GFX11-NEXT: v_dual_mov_b32 v1, v9 :: v_dual_cndmask_b32 v8, s10, v0
; GFX11-NEXT: v_mov_b32_e32 v0, v10
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v9f32_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v2, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v3, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v1
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v1
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v1
+; GFX8-NEXT: v_mov_b32_e32 v11, s9
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v1
+; GFX8-NEXT: v_mov_b32_e32 v12, s10
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 8, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v12, v0, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, v10
+; GFX8-NEXT: v_mov_b32_e32 v1, v9
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <9 x float> %vec, float %val, i32 %idx
ret <9 x float> %insert
@@ -2707,6 +3507,12 @@ define amdgpu_ps <9 x float> @dyn_insertelement_v9f32_v_v_s(<9 x float> %vec, fl
; GFX10PLUS-NEXT: s_mov_b32 m0, s2
; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v9
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v9f32_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 m0, s2
+; GFX8-NEXT: v_movreld_b32_e32 v0, v9
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <9 x float> %vec, float %val, i32 %idx
ret <9 x float> %insert
@@ -2756,6 +3562,28 @@ define amdgpu_ps <9 x float> @dyn_insertelement_v9f32_v_v_v(<9 x float> %vec, fl
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v10
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v9f32_v_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 8, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <9 x float> %vec, float %val, i32 %idx
ret <9 x float> %insert
@@ -2838,6 +3666,33 @@ define amdgpu_ps <10 x float> @dyn_insertelement_v10f32_s_v_s(<10 x float> inreg
; GFX11-NEXT: v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v8, s8
; GFX11-NEXT: v_movreld_b32_e32 v0, v10
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v10f32_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: v_mov_b32_e32 v10, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: s_mov_b32 m0, s12
+; GFX8-NEXT: v_movreld_b32_e32 v0, v10
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <10 x float> %vec, float %val, i32 %idx
ret <10 x float> %insert
@@ -2930,6 +3785,42 @@ define amdgpu_ps <10 x float> @dyn_insertelement_v10f32_s_v_v(<10 x float> inreg
; GFX11-NEXT: v_mov_b32_e32 v1, v11
; GFX11-NEXT: v_dual_cndmask_b32 v9, s11, v0 :: v_dual_mov_b32 v0, v10
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v10f32_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v2, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v1
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v1
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v1
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v1
+; GFX8-NEXT: v_mov_b32_e32 v12, s10
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 8, v1
+; GFX8-NEXT: v_mov_b32_e32 v13, s11
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v12, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 9, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v13, v0, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, v10
+; GFX8-NEXT: v_mov_b32_e32 v1, v11
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <10 x float> %vec, float %val, i32 %idx
ret <10 x float> %insert
@@ -2948,6 +3839,12 @@ define amdgpu_ps <10 x float> @dyn_insertelement_v10f32_v_v_s(<10 x float> %vec,
; GFX10PLUS-NEXT: s_mov_b32 m0, s2
; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v10
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v10f32_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 m0, s2
+; GFX8-NEXT: v_movreld_b32_e32 v0, v10
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <10 x float> %vec, float %val, i32 %idx
ret <10 x float> %insert
@@ -3001,6 +3898,30 @@ define amdgpu_ps <10 x float> @dyn_insertelement_v10f32_v_v_v(<10 x float> %vec,
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v11
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc_lo
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v10f32_v_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 8, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 9, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <10 x float> %vec, float %val, i32 %idx
ret <10 x float> %insert
@@ -3088,6 +4009,35 @@ define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_s_v_s(<11 x float> inreg
; GFX11-NEXT: v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
; GFX11-NEXT: v_movreld_b32_e32 v0, v11
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v11f32_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: v_mov_b32_e32 v11, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s10
+; GFX8-NEXT: s_mov_b32 m0, s13
+; GFX8-NEXT: v_movreld_b32_e32 v0, v11
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <11 x float> %vec, float %val, i32 %idx
ret <11 x float> %insert
@@ -3187,6 +4137,45 @@ define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_s_v_v(<11 x float> inreg
; GFX11-NEXT: v_dual_mov_b32 v1, v11 :: v_dual_cndmask_b32 v10, s12, v0
; GFX11-NEXT: v_mov_b32_e32 v0, v12
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v11f32_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v2, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v1
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v1
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v1
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v1
+; GFX8-NEXT: v_mov_b32_e32 v10, s10
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 8, v1
+; GFX8-NEXT: v_mov_b32_e32 v13, s11
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 9, v1
+; GFX8-NEXT: v_mov_b32_e32 v14, s12
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v13, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 10, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v14, v0, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, v12
+; GFX8-NEXT: v_mov_b32_e32 v1, v11
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <11 x float> %vec, float %val, i32 %idx
ret <11 x float> %insert
@@ -3205,6 +4194,12 @@ define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_v_v_s(<11 x float> %vec,
; GFX10PLUS-NEXT: s_mov_b32 m0, s2
; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v11
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v11f32_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 m0, s2
+; GFX8-NEXT: v_movreld_b32_e32 v0, v11
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <11 x float> %vec, float %val, i32 %idx
ret <11 x float> %insert
@@ -3262,6 +4257,32 @@ define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_v_v_v(<11 x float> %vec,
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v12
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v11f32_v_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 8, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 9, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 10, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <11 x float> %vec, float %val, i32 %idx
ret <11 x float> %insert
@@ -3355,6 +4376,37 @@ define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_s_v_s(<12 x float> inreg
; GFX11-NEXT: v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v10, s10
; GFX11-NEXT: v_movreld_b32_e32 v0, v12
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v12f32_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: v_mov_b32_e32 v12, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s10
+; GFX8-NEXT: v_mov_b32_e32 v11, s11
+; GFX8-NEXT: s_mov_b32 m0, s14
+; GFX8-NEXT: v_movreld_b32_e32 v0, v12
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <12 x float> %vec, float %val, i32 %idx
ret <12 x float> %insert
@@ -3461,6 +4513,48 @@ define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_s_v_v(<12 x float> inreg
; GFX11-NEXT: v_mov_b32_e32 v1, v13
; GFX11-NEXT: v_dual_cndmask_b32 v11, s13, v0 :: v_dual_mov_b32 v0, v12
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v12f32_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v2, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v3, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v1
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v1
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v1
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v1
+; GFX8-NEXT: v_mov_b32_e32 v10, s10
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 8, v1
+; GFX8-NEXT: v_mov_b32_e32 v11, s11
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 9, v1
+; GFX8-NEXT: v_mov_b32_e32 v14, s12
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 10, v1
+; GFX8-NEXT: v_mov_b32_e32 v15, s13
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v14, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 11, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v15, v0, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, v12
+; GFX8-NEXT: v_mov_b32_e32 v1, v13
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <12 x float> %vec, float %val, i32 %idx
ret <12 x float> %insert
@@ -3479,6 +4573,12 @@ define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_v_v_s(<12 x float> %vec,
; GFX10PLUS-NEXT: s_mov_b32 m0, s2
; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v12
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v12f32_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 m0, s2
+; GFX8-NEXT: v_movreld_b32_e32 v0, v12
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <12 x float> %vec, float %val, i32 %idx
ret <12 x float> %insert
@@ -3540,6 +4640,34 @@ define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_v_v_v(<12 x float> %vec,
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 11, v13
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v12f32_v_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 8, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 9, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 10, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 11, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <12 x float> %vec, float %val, i32 %idx
ret <12 x float> %insert
@@ -3590,6 +4718,28 @@ define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_s_s(<16 x i32> inreg %ve
; GFX10PLUS-NEXT: s_mov_b32 s15, s17
; GFX10PLUS-NEXT: s_movreld_b32 s0, s18
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v16i32_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 m0, s19
+; GFX8-NEXT: s_movreld_b32 s0, s18
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x i32> %vec, i32 %val, i32 %idx
ret <16 x i32> %insert
@@ -3702,6 +4852,44 @@ define amdgpu_ps <16 x float> @dyn_insertelement_v16f32_s_s_s(<16 x float> inreg
; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v16f32_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 m0, s19
+; GFX8-NEXT: s_movreld_b32 s0, s18
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s10
+; GFX8-NEXT: v_mov_b32_e32 v11, s11
+; GFX8-NEXT: v_mov_b32_e32 v12, s12
+; GFX8-NEXT: v_mov_b32_e32 v13, s13
+; GFX8-NEXT: v_mov_b32_e32 v14, s14
+; GFX8-NEXT: v_mov_b32_e32 v15, s15
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x float> %vec, float %val, i32 %idx
ret <16 x float> %insert
@@ -3902,6 +5090,76 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32f32_s_s_s(<32 x float> inreg
; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v32f32_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s16, s18
+; GFX8-NEXT: s_mov_b32 s17, s19
+; GFX8-NEXT: s_mov_b32 s18, s20
+; GFX8-NEXT: s_mov_b32 s19, s21
+; GFX8-NEXT: s_mov_b32 s20, s22
+; GFX8-NEXT: s_mov_b32 s21, s23
+; GFX8-NEXT: s_mov_b32 s22, s24
+; GFX8-NEXT: s_mov_b32 s23, s25
+; GFX8-NEXT: s_mov_b32 s24, s26
+; GFX8-NEXT: s_mov_b32 s25, s27
+; GFX8-NEXT: s_mov_b32 s26, s28
+; GFX8-NEXT: s_mov_b32 s27, s29
+; GFX8-NEXT: s_mov_b32 s28, s30
+; GFX8-NEXT: s_mov_b32 s29, s31
+; GFX8-NEXT: s_mov_b32 s31, s33
+; GFX8-NEXT: s_mov_b32 s30, s32
+; GFX8-NEXT: s_mov_b32 m0, s35
+; GFX8-NEXT: s_movreld_b32 s0, s34
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s10
+; GFX8-NEXT: v_mov_b32_e32 v11, s11
+; GFX8-NEXT: v_mov_b32_e32 v12, s12
+; GFX8-NEXT: v_mov_b32_e32 v13, s13
+; GFX8-NEXT: v_mov_b32_e32 v14, s14
+; GFX8-NEXT: v_mov_b32_e32 v15, s15
+; GFX8-NEXT: v_mov_b32_e32 v16, s16
+; GFX8-NEXT: v_mov_b32_e32 v17, s17
+; GFX8-NEXT: v_mov_b32_e32 v18, s18
+; GFX8-NEXT: v_mov_b32_e32 v19, s19
+; GFX8-NEXT: v_mov_b32_e32 v20, s20
+; GFX8-NEXT: v_mov_b32_e32 v21, s21
+; GFX8-NEXT: v_mov_b32_e32 v22, s22
+; GFX8-NEXT: v_mov_b32_e32 v23, s23
+; GFX8-NEXT: v_mov_b32_e32 v24, s24
+; GFX8-NEXT: v_mov_b32_e32 v25, s25
+; GFX8-NEXT: v_mov_b32_e32 v26, s26
+; GFX8-NEXT: v_mov_b32_e32 v27, s27
+; GFX8-NEXT: v_mov_b32_e32 v28, s28
+; GFX8-NEXT: v_mov_b32_e32 v29, s29
+; GFX8-NEXT: v_mov_b32_e32 v30, s30
+; GFX8-NEXT: v_mov_b32_e32 v31, s31
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <32 x float> %vec, float %val, i32 %idx
ret <32 x float> %insert
@@ -3910,80 +5168,117 @@ entry:
define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_s_s(<16 x i64> inreg %vec, i64 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v16i64_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s0, s2
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s2, s4
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s4, s6
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s6, s8
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s8, s10
-; GPRIDX-NEXT: s_mov_b32 s9, s11
-; GPRIDX-NEXT: s_mov_b32 s10, s12
-; GPRIDX-NEXT: s_mov_b32 s11, s13
-; GPRIDX-NEXT: s_mov_b32 s12, s14
-; GPRIDX-NEXT: s_mov_b32 s13, s15
-; GPRIDX-NEXT: s_mov_b32 s14, s16
-; GPRIDX-NEXT: s_mov_b32 s15, s17
-; GPRIDX-NEXT: s_mov_b32 s16, s18
-; GPRIDX-NEXT: s_mov_b32 s17, s19
-; GPRIDX-NEXT: s_mov_b32 s18, s20
-; GPRIDX-NEXT: s_mov_b32 s19, s21
-; GPRIDX-NEXT: s_mov_b32 s20, s22
-; GPRIDX-NEXT: s_mov_b32 s21, s23
-; GPRIDX-NEXT: s_mov_b32 s22, s24
-; GPRIDX-NEXT: s_mov_b32 s23, s25
-; GPRIDX-NEXT: s_mov_b32 s24, s26
-; GPRIDX-NEXT: s_mov_b32 s25, s27
-; GPRIDX-NEXT: s_mov_b32 s26, s28
-; GPRIDX-NEXT: s_mov_b32 s27, s29
-; GPRIDX-NEXT: s_mov_b32 s28, s30
-; GPRIDX-NEXT: s_mov_b32 s29, s31
-; GPRIDX-NEXT: s_mov_b32 s31, s33
-; GPRIDX-NEXT: s_mov_b32 s30, s32
-; GPRIDX-NEXT: s_mov_b32 m0, s36
-; GPRIDX-NEXT: s_nop 0
-; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[34:35]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 0
+; GPRIDX-NEXT: s_cselect_b64 s[0:1], s[34:35], s[2:3]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 1
+; GPRIDX-NEXT: s_cselect_b64 s[2:3], s[34:35], s[4:5]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 2
+; GPRIDX-NEXT: s_cselect_b64 s[4:5], s[34:35], s[6:7]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 3
+; GPRIDX-NEXT: s_cselect_b64 s[6:7], s[34:35], s[8:9]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 4
+; GPRIDX-NEXT: s_cselect_b64 s[8:9], s[34:35], s[10:11]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 5
+; GPRIDX-NEXT: s_cselect_b64 s[10:11], s[34:35], s[12:13]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 6
+; GPRIDX-NEXT: s_cselect_b64 s[12:13], s[34:35], s[14:15]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 7
+; GPRIDX-NEXT: s_cselect_b64 s[14:15], s[34:35], s[16:17]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 8
+; GPRIDX-NEXT: s_cselect_b64 s[16:17], s[34:35], s[18:19]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 9
+; GPRIDX-NEXT: s_cselect_b64 s[18:19], s[34:35], s[20:21]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 10
+; GPRIDX-NEXT: s_cselect_b64 s[20:21], s[34:35], s[22:23]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 11
+; GPRIDX-NEXT: s_cselect_b64 s[22:23], s[34:35], s[24:25]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 12
+; GPRIDX-NEXT: s_cselect_b64 s[24:25], s[34:35], s[26:27]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 13
+; GPRIDX-NEXT: s_cselect_b64 s[26:27], s[34:35], s[28:29]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 14
+; GPRIDX-NEXT: s_mov_b32 s39, s33
+; GPRIDX-NEXT: s_mov_b32 s38, s32
+; GPRIDX-NEXT: s_cselect_b64 s[28:29], s[34:35], s[30:31]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 15
+; GPRIDX-NEXT: s_cselect_b64 s[30:31], s[34:35], s[38:39]
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v16i64_s_s_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: s_mov_b32 s0, s2
-; GFX10PLUS-NEXT: s_mov_b32 s1, s3
-; GFX10PLUS-NEXT: s_mov_b32 m0, s36
-; GFX10PLUS-NEXT: s_mov_b32 s2, s4
-; GFX10PLUS-NEXT: s_mov_b32 s3, s5
-; GFX10PLUS-NEXT: s_mov_b32 s4, s6
-; GFX10PLUS-NEXT: s_mov_b32 s5, s7
-; GFX10PLUS-NEXT: s_mov_b32 s6, s8
-; GFX10PLUS-NEXT: s_mov_b32 s7, s9
-; GFX10PLUS-NEXT: s_mov_b32 s8, s10
-; GFX10PLUS-NEXT: s_mov_b32 s9, s11
-; GFX10PLUS-NEXT: s_mov_b32 s10, s12
-; GFX10PLUS-NEXT: s_mov_b32 s11, s13
-; GFX10PLUS-NEXT: s_mov_b32 s12, s14
-; GFX10PLUS-NEXT: s_mov_b32 s13, s15
-; GFX10PLUS-NEXT: s_mov_b32 s14, s16
-; GFX10PLUS-NEXT: s_mov_b32 s15, s17
-; GFX10PLUS-NEXT: s_mov_b32 s16, s18
-; GFX10PLUS-NEXT: s_mov_b32 s17, s19
-; GFX10PLUS-NEXT: s_mov_b32 s18, s20
-; GFX10PLUS-NEXT: s_mov_b32 s19, s21
-; GFX10PLUS-NEXT: s_mov_b32 s20, s22
-; GFX10PLUS-NEXT: s_mov_b32 s21, s23
-; GFX10PLUS-NEXT: s_mov_b32 s22, s24
-; GFX10PLUS-NEXT: s_mov_b32 s23, s25
-; GFX10PLUS-NEXT: s_mov_b32 s24, s26
-; GFX10PLUS-NEXT: s_mov_b32 s25, s27
-; GFX10PLUS-NEXT: s_mov_b32 s26, s28
-; GFX10PLUS-NEXT: s_mov_b32 s27, s29
-; GFX10PLUS-NEXT: s_mov_b32 s28, s30
-; GFX10PLUS-NEXT: s_mov_b32 s29, s31
-; GFX10PLUS-NEXT: s_mov_b32 s31, s33
-; GFX10PLUS-NEXT: s_mov_b32 s30, s32
-; GFX10PLUS-NEXT: s_movreld_b64 s[0:1], s[34:35]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 0
+; GFX10PLUS-NEXT: s_mov_b32 s39, s33
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[34:35], s[2:3]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 1
+; GFX10PLUS-NEXT: s_mov_b32 s38, s32
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[34:35], s[4:5]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 2
+; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[34:35], s[6:7]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 3
+; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[34:35], s[8:9]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 4
+; GFX10PLUS-NEXT: s_cselect_b64 s[8:9], s[34:35], s[10:11]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 5
+; GFX10PLUS-NEXT: s_cselect_b64 s[10:11], s[34:35], s[12:13]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 6
+; GFX10PLUS-NEXT: s_cselect_b64 s[12:13], s[34:35], s[14:15]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 7
+; GFX10PLUS-NEXT: s_cselect_b64 s[14:15], s[34:35], s[16:17]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 8
+; GFX10PLUS-NEXT: s_cselect_b64 s[16:17], s[34:35], s[18:19]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 9
+; GFX10PLUS-NEXT: s_cselect_b64 s[18:19], s[34:35], s[20:21]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 10
+; GFX10PLUS-NEXT: s_cselect_b64 s[20:21], s[34:35], s[22:23]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 11
+; GFX10PLUS-NEXT: s_cselect_b64 s[22:23], s[34:35], s[24:25]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 12
+; GFX10PLUS-NEXT: s_cselect_b64 s[24:25], s[34:35], s[26:27]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 13
+; GFX10PLUS-NEXT: s_cselect_b64 s[26:27], s[34:35], s[28:29]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 14
+; GFX10PLUS-NEXT: s_cselect_b64 s[28:29], s[34:35], s[30:31]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 15
+; GFX10PLUS-NEXT: s_cselect_b64 s[30:31], s[34:35], s[38:39]
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v16i64_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_cmp_eq_u32 s36, 0
+; GFX8-NEXT: s_cselect_b64 s[0:1], s[34:35], s[2:3]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 1
+; GFX8-NEXT: s_cselect_b64 s[2:3], s[34:35], s[4:5]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 2
+; GFX8-NEXT: s_cselect_b64 s[4:5], s[34:35], s[6:7]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 3
+; GFX8-NEXT: s_cselect_b64 s[6:7], s[34:35], s[8:9]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 4
+; GFX8-NEXT: s_cselect_b64 s[8:9], s[34:35], s[10:11]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 5
+; GFX8-NEXT: s_cselect_b64 s[10:11], s[34:35], s[12:13]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 6
+; GFX8-NEXT: s_cselect_b64 s[12:13], s[34:35], s[14:15]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 7
+; GFX8-NEXT: s_cselect_b64 s[14:15], s[34:35], s[16:17]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 8
+; GFX8-NEXT: s_cselect_b64 s[16:17], s[34:35], s[18:19]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 9
+; GFX8-NEXT: s_cselect_b64 s[18:19], s[34:35], s[20:21]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 10
+; GFX8-NEXT: s_cselect_b64 s[20:21], s[34:35], s[22:23]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 11
+; GFX8-NEXT: s_cselect_b64 s[22:23], s[34:35], s[24:25]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 12
+; GFX8-NEXT: s_cselect_b64 s[24:25], s[34:35], s[26:27]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 13
+; GFX8-NEXT: s_cselect_b64 s[26:27], s[34:35], s[28:29]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 14
+; GFX8-NEXT: s_mov_b32 s39, s33
+; GFX8-NEXT: s_mov_b32 s38, s32
+; GFX8-NEXT: s_cselect_b64 s[28:29], s[34:35], s[30:31]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 15
+; GFX8-NEXT: s_cselect_b64 s[30:31], s[34:35], s[38:39]
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x i64> %vec, i64 %val, i32 %idx
ret <16 x i64> %insert
@@ -3992,80 +5287,117 @@ entry:
define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_s_s(<16 x double> inreg %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v16f64_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s0, s2
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s2, s4
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s4, s6
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s6, s8
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s8, s10
-; GPRIDX-NEXT: s_mov_b32 s9, s11
-; GPRIDX-NEXT: s_mov_b32 s10, s12
-; GPRIDX-NEXT: s_mov_b32 s11, s13
-; GPRIDX-NEXT: s_mov_b32 s12, s14
-; GPRIDX-NEXT: s_mov_b32 s13, s15
-; GPRIDX-NEXT: s_mov_b32 s14, s16
-; GPRIDX-NEXT: s_mov_b32 s15, s17
-; GPRIDX-NEXT: s_mov_b32 s16, s18
-; GPRIDX-NEXT: s_mov_b32 s17, s19
-; GPRIDX-NEXT: s_mov_b32 s18, s20
-; GPRIDX-NEXT: s_mov_b32 s19, s21
-; GPRIDX-NEXT: s_mov_b32 s20, s22
-; GPRIDX-NEXT: s_mov_b32 s21, s23
-; GPRIDX-NEXT: s_mov_b32 s22, s24
-; GPRIDX-NEXT: s_mov_b32 s23, s25
-; GPRIDX-NEXT: s_mov_b32 s24, s26
-; GPRIDX-NEXT: s_mov_b32 s25, s27
-; GPRIDX-NEXT: s_mov_b32 s26, s28
-; GPRIDX-NEXT: s_mov_b32 s27, s29
-; GPRIDX-NEXT: s_mov_b32 s28, s30
-; GPRIDX-NEXT: s_mov_b32 s29, s31
-; GPRIDX-NEXT: s_mov_b32 s31, s33
-; GPRIDX-NEXT: s_mov_b32 s30, s32
-; GPRIDX-NEXT: s_mov_b32 m0, s36
-; GPRIDX-NEXT: s_nop 0
-; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[34:35]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 0
+; GPRIDX-NEXT: s_cselect_b64 s[0:1], s[34:35], s[2:3]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 1
+; GPRIDX-NEXT: s_cselect_b64 s[2:3], s[34:35], s[4:5]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 2
+; GPRIDX-NEXT: s_cselect_b64 s[4:5], s[34:35], s[6:7]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 3
+; GPRIDX-NEXT: s_cselect_b64 s[6:7], s[34:35], s[8:9]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 4
+; GPRIDX-NEXT: s_cselect_b64 s[8:9], s[34:35], s[10:11]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 5
+; GPRIDX-NEXT: s_cselect_b64 s[10:11], s[34:35], s[12:13]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 6
+; GPRIDX-NEXT: s_cselect_b64 s[12:13], s[34:35], s[14:15]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 7
+; GPRIDX-NEXT: s_cselect_b64 s[14:15], s[34:35], s[16:17]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 8
+; GPRIDX-NEXT: s_cselect_b64 s[16:17], s[34:35], s[18:19]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 9
+; GPRIDX-NEXT: s_cselect_b64 s[18:19], s[34:35], s[20:21]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 10
+; GPRIDX-NEXT: s_cselect_b64 s[20:21], s[34:35], s[22:23]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 11
+; GPRIDX-NEXT: s_cselect_b64 s[22:23], s[34:35], s[24:25]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 12
+; GPRIDX-NEXT: s_cselect_b64 s[24:25], s[34:35], s[26:27]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 13
+; GPRIDX-NEXT: s_cselect_b64 s[26:27], s[34:35], s[28:29]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 14
+; GPRIDX-NEXT: s_mov_b32 s39, s33
+; GPRIDX-NEXT: s_mov_b32 s38, s32
+; GPRIDX-NEXT: s_cselect_b64 s[28:29], s[34:35], s[30:31]
+; GPRIDX-NEXT: s_cmp_eq_u32 s36, 15
+; GPRIDX-NEXT: s_cselect_b64 s[30:31], s[34:35], s[38:39]
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v16f64_s_s_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: s_mov_b32 s0, s2
-; GFX10PLUS-NEXT: s_mov_b32 s1, s3
-; GFX10PLUS-NEXT: s_mov_b32 m0, s36
-; GFX10PLUS-NEXT: s_mov_b32 s2, s4
-; GFX10PLUS-NEXT: s_mov_b32 s3, s5
-; GFX10PLUS-NEXT: s_mov_b32 s4, s6
-; GFX10PLUS-NEXT: s_mov_b32 s5, s7
-; GFX10PLUS-NEXT: s_mov_b32 s6, s8
-; GFX10PLUS-NEXT: s_mov_b32 s7, s9
-; GFX10PLUS-NEXT: s_mov_b32 s8, s10
-; GFX10PLUS-NEXT: s_mov_b32 s9, s11
-; GFX10PLUS-NEXT: s_mov_b32 s10, s12
-; GFX10PLUS-NEXT: s_mov_b32 s11, s13
-; GFX10PLUS-NEXT: s_mov_b32 s12, s14
-; GFX10PLUS-NEXT: s_mov_b32 s13, s15
-; GFX10PLUS-NEXT: s_mov_b32 s14, s16
-; GFX10PLUS-NEXT: s_mov_b32 s15, s17
-; GFX10PLUS-NEXT: s_mov_b32 s16, s18
-; GFX10PLUS-NEXT: s_mov_b32 s17, s19
-; GFX10PLUS-NEXT: s_mov_b32 s18, s20
-; GFX10PLUS-NEXT: s_mov_b32 s19, s21
-; GFX10PLUS-NEXT: s_mov_b32 s20, s22
-; GFX10PLUS-NEXT: s_mov_b32 s21, s23
-; GFX10PLUS-NEXT: s_mov_b32 s22, s24
-; GFX10PLUS-NEXT: s_mov_b32 s23, s25
-; GFX10PLUS-NEXT: s_mov_b32 s24, s26
-; GFX10PLUS-NEXT: s_mov_b32 s25, s27
-; GFX10PLUS-NEXT: s_mov_b32 s26, s28
-; GFX10PLUS-NEXT: s_mov_b32 s27, s29
-; GFX10PLUS-NEXT: s_mov_b32 s28, s30
-; GFX10PLUS-NEXT: s_mov_b32 s29, s31
-; GFX10PLUS-NEXT: s_mov_b32 s31, s33
-; GFX10PLUS-NEXT: s_mov_b32 s30, s32
-; GFX10PLUS-NEXT: s_movreld_b64 s[0:1], s[34:35]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 0
+; GFX10PLUS-NEXT: s_mov_b32 s39, s33
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[34:35], s[2:3]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 1
+; GFX10PLUS-NEXT: s_mov_b32 s38, s32
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[34:35], s[4:5]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 2
+; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[34:35], s[6:7]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 3
+; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[34:35], s[8:9]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 4
+; GFX10PLUS-NEXT: s_cselect_b64 s[8:9], s[34:35], s[10:11]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 5
+; GFX10PLUS-NEXT: s_cselect_b64 s[10:11], s[34:35], s[12:13]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 6
+; GFX10PLUS-NEXT: s_cselect_b64 s[12:13], s[34:35], s[14:15]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 7
+; GFX10PLUS-NEXT: s_cselect_b64 s[14:15], s[34:35], s[16:17]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 8
+; GFX10PLUS-NEXT: s_cselect_b64 s[16:17], s[34:35], s[18:19]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 9
+; GFX10PLUS-NEXT: s_cselect_b64 s[18:19], s[34:35], s[20:21]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 10
+; GFX10PLUS-NEXT: s_cselect_b64 s[20:21], s[34:35], s[22:23]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 11
+; GFX10PLUS-NEXT: s_cselect_b64 s[22:23], s[34:35], s[24:25]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 12
+; GFX10PLUS-NEXT: s_cselect_b64 s[24:25], s[34:35], s[26:27]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 13
+; GFX10PLUS-NEXT: s_cselect_b64 s[26:27], s[34:35], s[28:29]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 14
+; GFX10PLUS-NEXT: s_cselect_b64 s[28:29], s[34:35], s[30:31]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 15
+; GFX10PLUS-NEXT: s_cselect_b64 s[30:31], s[34:35], s[38:39]
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v16f64_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_cmp_eq_u32 s36, 0
+; GFX8-NEXT: s_cselect_b64 s[0:1], s[34:35], s[2:3]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 1
+; GFX8-NEXT: s_cselect_b64 s[2:3], s[34:35], s[4:5]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 2
+; GFX8-NEXT: s_cselect_b64 s[4:5], s[34:35], s[6:7]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 3
+; GFX8-NEXT: s_cselect_b64 s[6:7], s[34:35], s[8:9]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 4
+; GFX8-NEXT: s_cselect_b64 s[8:9], s[34:35], s[10:11]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 5
+; GFX8-NEXT: s_cselect_b64 s[10:11], s[34:35], s[12:13]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 6
+; GFX8-NEXT: s_cselect_b64 s[12:13], s[34:35], s[14:15]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 7
+; GFX8-NEXT: s_cselect_b64 s[14:15], s[34:35], s[16:17]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 8
+; GFX8-NEXT: s_cselect_b64 s[16:17], s[34:35], s[18:19]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 9
+; GFX8-NEXT: s_cselect_b64 s[18:19], s[34:35], s[20:21]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 10
+; GFX8-NEXT: s_cselect_b64 s[20:21], s[34:35], s[22:23]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 11
+; GFX8-NEXT: s_cselect_b64 s[22:23], s[34:35], s[24:25]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 12
+; GFX8-NEXT: s_cselect_b64 s[24:25], s[34:35], s[26:27]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 13
+; GFX8-NEXT: s_cselect_b64 s[26:27], s[34:35], s[28:29]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 14
+; GFX8-NEXT: s_mov_b32 s39, s33
+; GFX8-NEXT: s_mov_b32 s38, s32
+; GFX8-NEXT: s_cselect_b64 s[28:29], s[34:35], s[30:31]
+; GFX8-NEXT: s_cmp_eq_u32 s36, 15
+; GFX8-NEXT: s_cselect_b64 s[30:31], s[34:35], s[38:39]
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x double> %vec, double %val, i32 %idx
ret <16 x double> %insert
@@ -4226,6 +5558,60 @@ define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_v_s(<16 x i32> inreg %ve
; GFX11-NEXT: v_readfirstlane_b32 s14, v15
; GFX11-NEXT: v_readfirstlane_b32 s15, v16
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v16i32_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: v_mov_b32_e32 v14, s13
+; GFX8-NEXT: v_mov_b32_e32 v13, s12
+; GFX8-NEXT: v_mov_b32_e32 v12, s11
+; GFX8-NEXT: v_mov_b32_e32 v11, s10
+; GFX8-NEXT: v_mov_b32_e32 v10, s9
+; GFX8-NEXT: v_mov_b32_e32 v9, s8
+; GFX8-NEXT: v_mov_b32_e32 v8, s7
+; GFX8-NEXT: v_mov_b32_e32 v7, s6
+; GFX8-NEXT: v_mov_b32_e32 v6, s5
+; GFX8-NEXT: v_mov_b32_e32 v5, s4
+; GFX8-NEXT: v_mov_b32_e32 v4, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: s_mov_b32 m0, s18
+; GFX8-NEXT: v_movreld_b32_e32 v1, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v1
+; GFX8-NEXT: v_readfirstlane_b32 s1, v2
+; GFX8-NEXT: v_readfirstlane_b32 s2, v3
+; GFX8-NEXT: v_readfirstlane_b32 s3, v4
+; GFX8-NEXT: v_readfirstlane_b32 s4, v5
+; GFX8-NEXT: v_readfirstlane_b32 s5, v6
+; GFX8-NEXT: v_readfirstlane_b32 s6, v7
+; GFX8-NEXT: v_readfirstlane_b32 s7, v8
+; GFX8-NEXT: v_readfirstlane_b32 s8, v9
+; GFX8-NEXT: v_readfirstlane_b32 s9, v10
+; GFX8-NEXT: v_readfirstlane_b32 s10, v11
+; GFX8-NEXT: v_readfirstlane_b32 s11, v12
+; GFX8-NEXT: v_readfirstlane_b32 s12, v13
+; GFX8-NEXT: v_readfirstlane_b32 s13, v14
+; GFX8-NEXT: v_readfirstlane_b32 s14, v15
+; GFX8-NEXT: v_readfirstlane_b32 s15, v16
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x i32> %vec, i32 %val, i32 %idx
ret <16 x i32> %insert
@@ -4341,6 +5727,45 @@ define amdgpu_ps <16 x float> @dyn_insertelement_v16f32_s_v_s(<16 x float> inreg
; GFX11-NEXT: v_dual_mov_b32 v15, s15 :: v_dual_mov_b32 v14, s14
; GFX11-NEXT: v_movreld_b32_e32 v0, v16
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v16f32_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: v_mov_b32_e32 v16, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s10
+; GFX8-NEXT: v_mov_b32_e32 v11, s11
+; GFX8-NEXT: v_mov_b32_e32 v12, s12
+; GFX8-NEXT: v_mov_b32_e32 v13, s13
+; GFX8-NEXT: v_mov_b32_e32 v14, s14
+; GFX8-NEXT: v_mov_b32_e32 v15, s15
+; GFX8-NEXT: s_mov_b32 m0, s18
+; GFX8-NEXT: v_movreld_b32_e32 v0, v16
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x float> %vec, float %val, i32 %idx
ret <16 x float> %insert
@@ -4544,6 +5969,77 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32f32_s_v_s(<32 x float> inreg
; GFX11-NEXT: v_dual_mov_b32 v31, s31 :: v_dual_mov_b32 v30, s30
; GFX11-NEXT: v_movreld_b32_e32 v0, v32
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v32f32_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s16, s18
+; GFX8-NEXT: s_mov_b32 s17, s19
+; GFX8-NEXT: s_mov_b32 s18, s20
+; GFX8-NEXT: s_mov_b32 s19, s21
+; GFX8-NEXT: s_mov_b32 s20, s22
+; GFX8-NEXT: s_mov_b32 s21, s23
+; GFX8-NEXT: s_mov_b32 s22, s24
+; GFX8-NEXT: s_mov_b32 s23, s25
+; GFX8-NEXT: s_mov_b32 s24, s26
+; GFX8-NEXT: s_mov_b32 s25, s27
+; GFX8-NEXT: s_mov_b32 s26, s28
+; GFX8-NEXT: s_mov_b32 s27, s29
+; GFX8-NEXT: s_mov_b32 s28, s30
+; GFX8-NEXT: s_mov_b32 s29, s31
+; GFX8-NEXT: s_mov_b32 s31, s33
+; GFX8-NEXT: s_mov_b32 s30, s32
+; GFX8-NEXT: v_mov_b32_e32 v32, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s10
+; GFX8-NEXT: v_mov_b32_e32 v11, s11
+; GFX8-NEXT: v_mov_b32_e32 v12, s12
+; GFX8-NEXT: v_mov_b32_e32 v13, s13
+; GFX8-NEXT: v_mov_b32_e32 v14, s14
+; GFX8-NEXT: v_mov_b32_e32 v15, s15
+; GFX8-NEXT: v_mov_b32_e32 v16, s16
+; GFX8-NEXT: v_mov_b32_e32 v17, s17
+; GFX8-NEXT: v_mov_b32_e32 v18, s18
+; GFX8-NEXT: v_mov_b32_e32 v19, s19
+; GFX8-NEXT: v_mov_b32_e32 v20, s20
+; GFX8-NEXT: v_mov_b32_e32 v21, s21
+; GFX8-NEXT: v_mov_b32_e32 v22, s22
+; GFX8-NEXT: v_mov_b32_e32 v23, s23
+; GFX8-NEXT: v_mov_b32_e32 v24, s24
+; GFX8-NEXT: v_mov_b32_e32 v25, s25
+; GFX8-NEXT: v_mov_b32_e32 v26, s26
+; GFX8-NEXT: v_mov_b32_e32 v27, s27
+; GFX8-NEXT: v_mov_b32_e32 v28, s28
+; GFX8-NEXT: v_mov_b32_e32 v29, s29
+; GFX8-NEXT: v_mov_b32_e32 v30, s30
+; GFX8-NEXT: v_mov_b32_e32 v31, s31
+; GFX8-NEXT: s_mov_b32 m0, s34
+; GFX8-NEXT: v_movreld_b32_e32 v0, v32
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <32 x float> %vec, float %val, i32 %idx
ret <32 x float> %insert
@@ -4844,6 +6340,109 @@ define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_v_s(<16 x i64> inreg %ve
; GFX11-NEXT: v_readfirstlane_b32 s30, v32
; GFX11-NEXT: v_readfirstlane_b32 s31, v33
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v16i64_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s17, s19
+; GFX8-NEXT: s_mov_b32 s19, s21
+; GFX8-NEXT: s_mov_b32 s21, s23
+; GFX8-NEXT: s_mov_b32 s23, s25
+; GFX8-NEXT: s_mov_b32 s25, s27
+; GFX8-NEXT: s_mov_b32 s27, s29
+; GFX8-NEXT: s_mov_b32 s29, s31
+; GFX8-NEXT: s_mov_b32 s31, s33
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s16, s18
+; GFX8-NEXT: s_mov_b32 s18, s20
+; GFX8-NEXT: s_mov_b32 s20, s22
+; GFX8-NEXT: s_mov_b32 s22, s24
+; GFX8-NEXT: s_mov_b32 s24, s26
+; GFX8-NEXT: s_mov_b32 s26, s28
+; GFX8-NEXT: s_mov_b32 s28, s30
+; GFX8-NEXT: s_mov_b32 s30, s32
+; GFX8-NEXT: v_mov_b32_e32 v33, s31
+; GFX8-NEXT: s_lshl_b32 m0, s34, 1
+; GFX8-NEXT: v_mov_b32_e32 v32, s30
+; GFX8-NEXT: v_mov_b32_e32 v31, s29
+; GFX8-NEXT: v_mov_b32_e32 v30, s28
+; GFX8-NEXT: v_mov_b32_e32 v29, s27
+; GFX8-NEXT: v_mov_b32_e32 v28, s26
+; GFX8-NEXT: v_mov_b32_e32 v27, s25
+; GFX8-NEXT: v_mov_b32_e32 v26, s24
+; GFX8-NEXT: v_mov_b32_e32 v25, s23
+; GFX8-NEXT: v_mov_b32_e32 v24, s22
+; GFX8-NEXT: v_mov_b32_e32 v23, s21
+; GFX8-NEXT: v_mov_b32_e32 v22, s20
+; GFX8-NEXT: v_mov_b32_e32 v21, s19
+; GFX8-NEXT: v_mov_b32_e32 v20, s18
+; GFX8-NEXT: v_mov_b32_e32 v19, s17
+; GFX8-NEXT: v_mov_b32_e32 v18, s16
+; GFX8-NEXT: v_mov_b32_e32 v17, s15
+; GFX8-NEXT: v_mov_b32_e32 v16, s14
+; GFX8-NEXT: v_mov_b32_e32 v15, s13
+; GFX8-NEXT: v_mov_b32_e32 v14, s12
+; GFX8-NEXT: v_mov_b32_e32 v13, s11
+; GFX8-NEXT: v_mov_b32_e32 v12, s10
+; GFX8-NEXT: v_mov_b32_e32 v11, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_movreld_b32_e32 v2, v0
+; GFX8-NEXT: v_movreld_b32_e32 v3, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v2
+; GFX8-NEXT: v_readfirstlane_b32 s1, v3
+; GFX8-NEXT: v_readfirstlane_b32 s2, v4
+; GFX8-NEXT: v_readfirstlane_b32 s3, v5
+; GFX8-NEXT: v_readfirstlane_b32 s4, v6
+; GFX8-NEXT: v_readfirstlane_b32 s5, v7
+; GFX8-NEXT: v_readfirstlane_b32 s6, v8
+; GFX8-NEXT: v_readfirstlane_b32 s7, v9
+; GFX8-NEXT: v_readfirstlane_b32 s8, v10
+; GFX8-NEXT: v_readfirstlane_b32 s9, v11
+; GFX8-NEXT: v_readfirstlane_b32 s10, v12
+; GFX8-NEXT: v_readfirstlane_b32 s11, v13
+; GFX8-NEXT: v_readfirstlane_b32 s12, v14
+; GFX8-NEXT: v_readfirstlane_b32 s13, v15
+; GFX8-NEXT: v_readfirstlane_b32 s14, v16
+; GFX8-NEXT: v_readfirstlane_b32 s15, v17
+; GFX8-NEXT: v_readfirstlane_b32 s16, v18
+; GFX8-NEXT: v_readfirstlane_b32 s17, v19
+; GFX8-NEXT: v_readfirstlane_b32 s18, v20
+; GFX8-NEXT: v_readfirstlane_b32 s19, v21
+; GFX8-NEXT: v_readfirstlane_b32 s20, v22
+; GFX8-NEXT: v_readfirstlane_b32 s21, v23
+; GFX8-NEXT: v_readfirstlane_b32 s22, v24
+; GFX8-NEXT: v_readfirstlane_b32 s23, v25
+; GFX8-NEXT: v_readfirstlane_b32 s24, v26
+; GFX8-NEXT: v_readfirstlane_b32 s25, v27
+; GFX8-NEXT: v_readfirstlane_b32 s26, v28
+; GFX8-NEXT: v_readfirstlane_b32 s27, v29
+; GFX8-NEXT: v_readfirstlane_b32 s28, v30
+; GFX8-NEXT: v_readfirstlane_b32 s29, v31
+; GFX8-NEXT: v_readfirstlane_b32 s30, v32
+; GFX8-NEXT: v_readfirstlane_b32 s31, v33
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x i64> %vec, i64 %val, i32 %idx
ret <16 x i64> %insert
@@ -5144,6 +6743,109 @@ define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_v_s(<16 x double> inr
; GFX11-NEXT: v_readfirstlane_b32 s30, v32
; GFX11-NEXT: v_readfirstlane_b32 s31, v33
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v16f64_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: s_mov_b32 s15, s17
+; GFX8-NEXT: s_mov_b32 s17, s19
+; GFX8-NEXT: s_mov_b32 s19, s21
+; GFX8-NEXT: s_mov_b32 s21, s23
+; GFX8-NEXT: s_mov_b32 s23, s25
+; GFX8-NEXT: s_mov_b32 s25, s27
+; GFX8-NEXT: s_mov_b32 s27, s29
+; GFX8-NEXT: s_mov_b32 s29, s31
+; GFX8-NEXT: s_mov_b32 s31, s33
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s14, s16
+; GFX8-NEXT: s_mov_b32 s16, s18
+; GFX8-NEXT: s_mov_b32 s18, s20
+; GFX8-NEXT: s_mov_b32 s20, s22
+; GFX8-NEXT: s_mov_b32 s22, s24
+; GFX8-NEXT: s_mov_b32 s24, s26
+; GFX8-NEXT: s_mov_b32 s26, s28
+; GFX8-NEXT: s_mov_b32 s28, s30
+; GFX8-NEXT: s_mov_b32 s30, s32
+; GFX8-NEXT: v_mov_b32_e32 v33, s31
+; GFX8-NEXT: s_lshl_b32 m0, s34, 1
+; GFX8-NEXT: v_mov_b32_e32 v32, s30
+; GFX8-NEXT: v_mov_b32_e32 v31, s29
+; GFX8-NEXT: v_mov_b32_e32 v30, s28
+; GFX8-NEXT: v_mov_b32_e32 v29, s27
+; GFX8-NEXT: v_mov_b32_e32 v28, s26
+; GFX8-NEXT: v_mov_b32_e32 v27, s25
+; GFX8-NEXT: v_mov_b32_e32 v26, s24
+; GFX8-NEXT: v_mov_b32_e32 v25, s23
+; GFX8-NEXT: v_mov_b32_e32 v24, s22
+; GFX8-NEXT: v_mov_b32_e32 v23, s21
+; GFX8-NEXT: v_mov_b32_e32 v22, s20
+; GFX8-NEXT: v_mov_b32_e32 v21, s19
+; GFX8-NEXT: v_mov_b32_e32 v20, s18
+; GFX8-NEXT: v_mov_b32_e32 v19, s17
+; GFX8-NEXT: v_mov_b32_e32 v18, s16
+; GFX8-NEXT: v_mov_b32_e32 v17, s15
+; GFX8-NEXT: v_mov_b32_e32 v16, s14
+; GFX8-NEXT: v_mov_b32_e32 v15, s13
+; GFX8-NEXT: v_mov_b32_e32 v14, s12
+; GFX8-NEXT: v_mov_b32_e32 v13, s11
+; GFX8-NEXT: v_mov_b32_e32 v12, s10
+; GFX8-NEXT: v_mov_b32_e32 v11, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_movreld_b32_e32 v2, v0
+; GFX8-NEXT: v_movreld_b32_e32 v3, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v2
+; GFX8-NEXT: v_readfirstlane_b32 s1, v3
+; GFX8-NEXT: v_readfirstlane_b32 s2, v4
+; GFX8-NEXT: v_readfirstlane_b32 s3, v5
+; GFX8-NEXT: v_readfirstlane_b32 s4, v6
+; GFX8-NEXT: v_readfirstlane_b32 s5, v7
+; GFX8-NEXT: v_readfirstlane_b32 s6, v8
+; GFX8-NEXT: v_readfirstlane_b32 s7, v9
+; GFX8-NEXT: v_readfirstlane_b32 s8, v10
+; GFX8-NEXT: v_readfirstlane_b32 s9, v11
+; GFX8-NEXT: v_readfirstlane_b32 s10, v12
+; GFX8-NEXT: v_readfirstlane_b32 s11, v13
+; GFX8-NEXT: v_readfirstlane_b32 s12, v14
+; GFX8-NEXT: v_readfirstlane_b32 s13, v15
+; GFX8-NEXT: v_readfirstlane_b32 s14, v16
+; GFX8-NEXT: v_readfirstlane_b32 s15, v17
+; GFX8-NEXT: v_readfirstlane_b32 s16, v18
+; GFX8-NEXT: v_readfirstlane_b32 s17, v19
+; GFX8-NEXT: v_readfirstlane_b32 s18, v20
+; GFX8-NEXT: v_readfirstlane_b32 s19, v21
+; GFX8-NEXT: v_readfirstlane_b32 s20, v22
+; GFX8-NEXT: v_readfirstlane_b32 s21, v23
+; GFX8-NEXT: v_readfirstlane_b32 s22, v24
+; GFX8-NEXT: v_readfirstlane_b32 s23, v25
+; GFX8-NEXT: v_readfirstlane_b32 s24, v26
+; GFX8-NEXT: v_readfirstlane_b32 s25, v27
+; GFX8-NEXT: v_readfirstlane_b32 s26, v28
+; GFX8-NEXT: v_readfirstlane_b32 s27, v29
+; GFX8-NEXT: v_readfirstlane_b32 s28, v30
+; GFX8-NEXT: v_readfirstlane_b32 s29, v31
+; GFX8-NEXT: v_readfirstlane_b32 s30, v32
+; GFX8-NEXT: v_readfirstlane_b32 s31, v33
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x double> %vec, double %val, i32 %idx
ret <16 x double> %insert
@@ -5152,39 +6854,43 @@ entry:
define amdgpu_ps <7 x i32> @dyn_insertelement_v7i32_s_s_s(<7 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7i32_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 0
-; GPRIDX-NEXT: s_cselect_b32 s0, s9, s2
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 1
-; GPRIDX-NEXT: s_cselect_b32 s1, s9, s3
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 2
-; GPRIDX-NEXT: s_cselect_b32 s2, s9, s4
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 3
-; GPRIDX-NEXT: s_cselect_b32 s3, s9, s5
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 4
-; GPRIDX-NEXT: s_cselect_b32 s4, s9, s6
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 5
-; GPRIDX-NEXT: s_cselect_b32 s5, s9, s7
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 6
-; GPRIDX-NEXT: s_cselect_b32 s6, s9, s8
+; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
+; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 m0, s10
+; GPRIDX-NEXT: s_nop 0
+; GPRIDX-NEXT: s_movreld_b32 s0, s9
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v7i32_s_s_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s0, s9, s2
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 1
-; GFX10PLUS-NEXT: s_cselect_b32 s1, s9, s3
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 2
-; GFX10PLUS-NEXT: s_cselect_b32 s2, s9, s4
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 3
-; GFX10PLUS-NEXT: s_cselect_b32 s3, s9, s5
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 4
-; GFX10PLUS-NEXT: s_cselect_b32 s4, s9, s6
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 5
-; GFX10PLUS-NEXT: s_cselect_b32 s5, s9, s7
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 6
-; GFX10PLUS-NEXT: s_cselect_b32 s6, s9, s8
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 m0, s10
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_movreld_b32 s0, s9
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7i32_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 m0, s10
+; GFX8-NEXT: s_movreld_b32 s0, s9
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x i32> %vec, i32 %val, i32 %idx
ret <7 x i32> %insert
@@ -5193,39 +6899,43 @@ entry:
define amdgpu_ps <7 x ptr addrspace(3)> @dyn_insertelement_v7p3i8_s_s_s(<7 x ptr addrspace(3)> inreg %vec, ptr addrspace(3) inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7p3i8_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 0
-; GPRIDX-NEXT: s_cselect_b32 s0, s9, s2
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 1
-; GPRIDX-NEXT: s_cselect_b32 s1, s9, s3
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 2
-; GPRIDX-NEXT: s_cselect_b32 s2, s9, s4
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 3
-; GPRIDX-NEXT: s_cselect_b32 s3, s9, s5
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 4
-; GPRIDX-NEXT: s_cselect_b32 s4, s9, s6
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 5
-; GPRIDX-NEXT: s_cselect_b32 s5, s9, s7
-; GPRIDX-NEXT: s_cmp_eq_u32 s10, 6
-; GPRIDX-NEXT: s_cselect_b32 s6, s9, s8
+; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
+; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: s_mov_b32 m0, s10
+; GPRIDX-NEXT: s_nop 0
+; GPRIDX-NEXT: s_movreld_b32 s0, s9
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v7p3i8_s_s_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s0, s9, s2
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 1
-; GFX10PLUS-NEXT: s_cselect_b32 s1, s9, s3
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 2
-; GFX10PLUS-NEXT: s_cselect_b32 s2, s9, s4
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 3
-; GFX10PLUS-NEXT: s_cselect_b32 s3, s9, s5
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 4
-; GFX10PLUS-NEXT: s_cselect_b32 s4, s9, s6
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 5
-; GFX10PLUS-NEXT: s_cselect_b32 s5, s9, s7
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 6
-; GFX10PLUS-NEXT: s_cselect_b32 s6, s9, s8
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 m0, s10
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_movreld_b32 s0, s9
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7p3i8_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 m0, s10
+; GFX8-NEXT: s_movreld_b32 s0, s9
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x ptr addrspace(3)> %vec, ptr addrspace(3) %val, i32 %idx
ret <7 x ptr addrspace(3)> %insert
@@ -5234,48 +6944,84 @@ entry:
define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_s(<7 x float> inreg %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f32_s_v_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: v_mov_b32_e32 v1, s2
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0
-; GPRIDX-NEXT: v_mov_b32_e32 v2, s3
-; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v1, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s9, 1
-; GPRIDX-NEXT: v_mov_b32_e32 v3, s4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s9, 2
-; GPRIDX-NEXT: v_mov_b32_e32 v4, s5
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v3, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s9, 3
-; GPRIDX-NEXT: v_mov_b32_e32 v5, s6
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s9, 4
-; GPRIDX-NEXT: v_mov_b32_e32 v6, s7
-; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v5, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s9, 5
-; GPRIDX-NEXT: v_mov_b32_e32 v8, s8
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v6, v0, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s9, 6
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v8, v0, vcc
+; GPRIDX-NEXT: s_mov_b32 s0, s2
+; GPRIDX-NEXT: s_mov_b32 s1, s3
+; GPRIDX-NEXT: s_mov_b32 s2, s4
+; GPRIDX-NEXT: s_mov_b32 s3, s5
+; GPRIDX-NEXT: s_mov_b32 s4, s6
+; GPRIDX-NEXT: s_mov_b32 s5, s7
+; GPRIDX-NEXT: s_mov_b32 s6, s8
+; GPRIDX-NEXT: v_mov_b32_e32 v7, v0
+; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
+; GPRIDX-NEXT: v_mov_b32_e32 v1, s1
+; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
+; GPRIDX-NEXT: v_mov_b32_e32 v3, s3
+; GPRIDX-NEXT: v_mov_b32_e32 v4, s4
+; GPRIDX-NEXT: v_mov_b32_e32 v5, s5
+; GPRIDX-NEXT: v_mov_b32_e32 v6, s6
+; GPRIDX-NEXT: s_set_gpr_idx_on s9, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v0, v7
+; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
-; GFX10PLUS-LABEL: dyn_insertelement_v7f32_s_v_s:
-; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 0
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, s2, v0, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 1
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, s3, v0, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 2
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 3
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 4
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 5
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 6
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo
-; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v7
-; GFX10PLUS-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v7f32_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: v_mov_b32_e32 v7, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: s_mov_b32 m0, s9
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s6
+; GFX10-NEXT: v_movreld_b32_e32 v0, v7
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v7f32_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v0, s0
+; GFX11-NEXT: s_mov_b32 m0, s9
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v4, s4
+; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s6
+; GFX11-NEXT: v_movreld_b32_e32 v0, v7
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7f32_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: v_mov_b32_e32 v7, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: s_mov_b32 m0, s9
+; GFX8-NEXT: v_movreld_b32_e32 v0, v7
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert
@@ -5347,6 +7093,33 @@ define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_v(<7 x float> inreg %v
; GFX11-NEXT: v_dual_mov_b32 v1, v7 :: v_dual_cndmask_b32 v6, s8, v0
; GFX11-NEXT: v_mov_b32_e32 v0, v8
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7f32_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v2, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1
+; GFX8-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v1
+; GFX8-NEXT: v_mov_b32_e32 v9, s7
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v1
+; GFX8-NEXT: v_mov_b32_e32 v10, s8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v0, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v0, vcc
+; GFX8-NEXT: v_mov_b32_e32 v0, v8
+; GFX8-NEXT: v_mov_b32_e32 v1, v7
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert
@@ -5355,39 +7128,22 @@ entry:
define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_v_v_s(<7 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f32_v_v_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 2
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 3
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 5
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 6
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST)
+; GPRIDX-NEXT: v_mov_b32_e32 v0, v7
+; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v7f32_v_v_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 4
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 5
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 6
-; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
+; GFX10PLUS-NEXT: s_mov_b32 m0, s2
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v7
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7f32_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 m0, s2
+; GFX8-NEXT: v_movreld_b32_e32 v0, v7
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert
@@ -5429,6 +7185,24 @@ define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_v_v_v(<7 x float> %vec, fl
; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8
; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7f32_v_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert
@@ -5437,44 +7211,57 @@ entry:
define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_s_s(<7 x double> inreg %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f64_s_s_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: s_mov_b32 s0, s2
-; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 s2, s4
-; GPRIDX-NEXT: s_mov_b32 s3, s5
-; GPRIDX-NEXT: s_mov_b32 s4, s6
-; GPRIDX-NEXT: s_mov_b32 s5, s7
-; GPRIDX-NEXT: s_mov_b32 s6, s8
-; GPRIDX-NEXT: s_mov_b32 s7, s9
-; GPRIDX-NEXT: s_mov_b32 s8, s10
-; GPRIDX-NEXT: s_mov_b32 s9, s11
-; GPRIDX-NEXT: s_mov_b32 s10, s12
-; GPRIDX-NEXT: s_mov_b32 s11, s13
-; GPRIDX-NEXT: s_mov_b32 s12, s14
-; GPRIDX-NEXT: s_mov_b32 s13, s15
-; GPRIDX-NEXT: s_mov_b32 m0, s18
-; GPRIDX-NEXT: s_nop 0
-; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[16:17]
+; GPRIDX-NEXT: s_cmp_eq_u32 s18, 0
+; GPRIDX-NEXT: s_cselect_b64 s[0:1], s[16:17], s[2:3]
+; GPRIDX-NEXT: s_cmp_eq_u32 s18, 1
+; GPRIDX-NEXT: s_cselect_b64 s[2:3], s[16:17], s[4:5]
+; GPRIDX-NEXT: s_cmp_eq_u32 s18, 2
+; GPRIDX-NEXT: s_cselect_b64 s[4:5], s[16:17], s[6:7]
+; GPRIDX-NEXT: s_cmp_eq_u32 s18, 3
+; GPRIDX-NEXT: s_cselect_b64 s[6:7], s[16:17], s[8:9]
+; GPRIDX-NEXT: s_cmp_eq_u32 s18, 4
+; GPRIDX-NEXT: s_cselect_b64 s[8:9], s[16:17], s[10:11]
+; GPRIDX-NEXT: s_cmp_eq_u32 s18, 5
+; GPRIDX-NEXT: s_cselect_b64 s[10:11], s[16:17], s[12:13]
+; GPRIDX-NEXT: s_cmp_eq_u32 s18, 6
+; GPRIDX-NEXT: s_cselect_b64 s[12:13], s[16:17], s[14:15]
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_insertelement_v7f64_s_s_s:
; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: s_mov_b32 s0, s2
-; GFX10PLUS-NEXT: s_mov_b32 s1, s3
-; GFX10PLUS-NEXT: s_mov_b32 m0, s18
-; GFX10PLUS-NEXT: s_mov_b32 s2, s4
-; GFX10PLUS-NEXT: s_mov_b32 s3, s5
-; GFX10PLUS-NEXT: s_mov_b32 s4, s6
-; GFX10PLUS-NEXT: s_mov_b32 s5, s7
-; GFX10PLUS-NEXT: s_mov_b32 s6, s8
-; GFX10PLUS-NEXT: s_mov_b32 s7, s9
-; GFX10PLUS-NEXT: s_mov_b32 s8, s10
-; GFX10PLUS-NEXT: s_mov_b32 s9, s11
-; GFX10PLUS-NEXT: s_mov_b32 s10, s12
-; GFX10PLUS-NEXT: s_mov_b32 s11, s13
-; GFX10PLUS-NEXT: s_mov_b32 s12, s14
-; GFX10PLUS-NEXT: s_mov_b32 s13, s15
-; GFX10PLUS-NEXT: s_movreld_b64 s[0:1], s[16:17]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s18, 0
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[16:17], s[2:3]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s18, 1
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[16:17], s[4:5]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s18, 2
+; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[16:17], s[6:7]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s18, 3
+; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[16:17], s[8:9]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s18, 4
+; GFX10PLUS-NEXT: s_cselect_b64 s[8:9], s[16:17], s[10:11]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s18, 5
+; GFX10PLUS-NEXT: s_cselect_b64 s[10:11], s[16:17], s[12:13]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s18, 6
+; GFX10PLUS-NEXT: s_cselect_b64 s[12:13], s[16:17], s[14:15]
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7f64_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_cmp_eq_u32 s18, 0
+; GFX8-NEXT: s_cselect_b64 s[0:1], s[16:17], s[2:3]
+; GFX8-NEXT: s_cmp_eq_u32 s18, 1
+; GFX8-NEXT: s_cselect_b64 s[2:3], s[16:17], s[4:5]
+; GFX8-NEXT: s_cmp_eq_u32 s18, 2
+; GFX8-NEXT: s_cselect_b64 s[4:5], s[16:17], s[6:7]
+; GFX8-NEXT: s_cmp_eq_u32 s18, 3
+; GFX8-NEXT: s_cselect_b64 s[6:7], s[16:17], s[8:9]
+; GFX8-NEXT: s_cmp_eq_u32 s18, 4
+; GFX8-NEXT: s_cselect_b64 s[8:9], s[16:17], s[10:11]
+; GFX8-NEXT: s_cmp_eq_u32 s18, 5
+; GFX8-NEXT: s_cselect_b64 s[10:11], s[16:17], s[12:13]
+; GFX8-NEXT: s_cmp_eq_u32 s18, 6
+; GFX8-NEXT: s_cselect_b64 s[12:13], s[16:17], s[14:15]
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert
@@ -5627,6 +7414,57 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_s(<7 x double> inreg
; GFX11-NEXT: v_readfirstlane_b32 s12, v14
; GFX11-NEXT: v_readfirstlane_b32 s13, v15
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7f64_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: v_mov_b32_e32 v17, s15
+; GFX8-NEXT: v_mov_b32_e32 v16, s14
+; GFX8-NEXT: v_mov_b32_e32 v15, s13
+; GFX8-NEXT: v_mov_b32_e32 v14, s12
+; GFX8-NEXT: v_mov_b32_e32 v13, s11
+; GFX8-NEXT: v_mov_b32_e32 v12, s10
+; GFX8-NEXT: v_mov_b32_e32 v11, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: s_lshl_b32 m0, s16, 1
+; GFX8-NEXT: v_movreld_b32_e32 v2, v0
+; GFX8-NEXT: v_movreld_b32_e32 v3, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v2
+; GFX8-NEXT: v_readfirstlane_b32 s1, v3
+; GFX8-NEXT: v_readfirstlane_b32 s2, v4
+; GFX8-NEXT: v_readfirstlane_b32 s3, v5
+; GFX8-NEXT: v_readfirstlane_b32 s4, v6
+; GFX8-NEXT: v_readfirstlane_b32 s5, v7
+; GFX8-NEXT: v_readfirstlane_b32 s6, v8
+; GFX8-NEXT: v_readfirstlane_b32 s7, v9
+; GFX8-NEXT: v_readfirstlane_b32 s8, v10
+; GFX8-NEXT: v_readfirstlane_b32 s9, v11
+; GFX8-NEXT: v_readfirstlane_b32 s10, v12
+; GFX8-NEXT: v_readfirstlane_b32 s11, v13
+; GFX8-NEXT: v_readfirstlane_b32 s12, v14
+; GFX8-NEXT: v_readfirstlane_b32 s13, v15
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert
@@ -5828,6 +7666,75 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GFX11-NEXT: v_readfirstlane_b32 s12, v0
; GFX11-NEXT: v_readfirstlane_b32 s13, v1
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7f64_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s10, s12
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_mov_b32 s12, s14
+; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: v_mov_b32_e32 v18, s15
+; GFX8-NEXT: v_mov_b32_e32 v17, s14
+; GFX8-NEXT: v_mov_b32_e32 v16, s13
+; GFX8-NEXT: v_mov_b32_e32 v15, s12
+; GFX8-NEXT: v_mov_b32_e32 v14, s11
+; GFX8-NEXT: v_mov_b32_e32 v13, s10
+; GFX8-NEXT: v_mov_b32_e32 v12, s9
+; GFX8-NEXT: v_mov_b32_e32 v11, s8
+; GFX8-NEXT: v_mov_b32_e32 v10, s7
+; GFX8-NEXT: v_mov_b32_e32 v9, s6
+; GFX8-NEXT: v_mov_b32_e32 v8, s5
+; GFX8-NEXT: v_mov_b32_e32 v7, s4
+; GFX8-NEXT: v_mov_b32_e32 v6, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s2
+; GFX8-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v5, v0, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v0, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v9, v0, s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v11, v0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v13, v0, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v15, v0, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v1, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[2:3]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, v1, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v14, v1, s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v16, v1, s[8:9]
+; GFX8-NEXT: v_readfirstlane_b32 s0, v3
+; GFX8-NEXT: v_readfirstlane_b32 s1, v4
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v6
+; GFX8-NEXT: v_readfirstlane_b32 s4, v5
+; GFX8-NEXT: v_readfirstlane_b32 s5, v8
+; GFX8-NEXT: v_readfirstlane_b32 s6, v7
+; GFX8-NEXT: v_readfirstlane_b32 s7, v10
+; GFX8-NEXT: v_readfirstlane_b32 s8, v9
+; GFX8-NEXT: v_readfirstlane_b32 s9, v12
+; GFX8-NEXT: v_readfirstlane_b32 s10, v11
+; GFX8-NEXT: v_readfirstlane_b32 s11, v13
+; GFX8-NEXT: v_readfirstlane_b32 s12, v0
+; GFX8-NEXT: v_readfirstlane_b32 s13, v1
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert
@@ -5879,6 +7786,28 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_s(<7 x double> %vec,
; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12
; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7f64_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_lshl_b32 m0, s2, 1
+; GFX8-NEXT: v_mov_b32_e32 v16, v15
+; GFX8-NEXT: v_movreld_b32_e32 v0, v14
+; GFX8-NEXT: v_movreld_b32_e32 v1, v16
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
+; GFX8-NEXT: v_readfirstlane_b32 s4, v4
+; GFX8-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8-NEXT: v_readfirstlane_b32 s6, v6
+; GFX8-NEXT: v_readfirstlane_b32 s7, v7
+; GFX8-NEXT: v_readfirstlane_b32 s8, v8
+; GFX8-NEXT: v_readfirstlane_b32 s9, v9
+; GFX8-NEXT: v_readfirstlane_b32 s10, v10
+; GFX8-NEXT: v_readfirstlane_b32 s11, v11
+; GFX8-NEXT: v_readfirstlane_b32 s12, v12
+; GFX8-NEXT: v_readfirstlane_b32 s13, v13
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert
@@ -5998,6 +7927,45 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_v(<7 x double> %vec,
; GFX11-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-NEXT: v_readfirstlane_b32 s13, v13
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v7f64_v_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v15, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v15, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
+; GFX8-NEXT: v_readfirstlane_b32 s4, v4
+; GFX8-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8-NEXT: v_readfirstlane_b32 s6, v6
+; GFX8-NEXT: v_readfirstlane_b32 s7, v7
+; GFX8-NEXT: v_readfirstlane_b32 s8, v8
+; GFX8-NEXT: v_readfirstlane_b32 s9, v9
+; GFX8-NEXT: v_readfirstlane_b32 s10, v10
+; GFX8-NEXT: v_readfirstlane_b32 s11, v11
+; GFX8-NEXT: v_readfirstlane_b32 s12, v12
+; GFX8-NEXT: v_readfirstlane_b32 s13, v13
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert
@@ -6031,6 +7999,20 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_s_s(<5 x double> inreg
; GFX10PLUS-NEXT: s_cmp_eq_u32 s14, 4
; GFX10PLUS-NEXT: s_cselect_b64 s[8:9], s[12:13], s[10:11]
; GFX10PLUS-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v5f64_s_s_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_cmp_eq_u32 s14, 0
+; GFX8-NEXT: s_cselect_b64 s[0:1], s[12:13], s[2:3]
+; GFX8-NEXT: s_cmp_eq_u32 s14, 1
+; GFX8-NEXT: s_cselect_b64 s[2:3], s[12:13], s[4:5]
+; GFX8-NEXT: s_cmp_eq_u32 s14, 2
+; GFX8-NEXT: s_cselect_b64 s[4:5], s[12:13], s[6:7]
+; GFX8-NEXT: s_cmp_eq_u32 s14, 3
+; GFX8-NEXT: s_cselect_b64 s[6:7], s[12:13], s[8:9]
+; GFX8-NEXT: s_cmp_eq_u32 s14, 4
+; GFX8-NEXT: s_cselect_b64 s[8:9], s[12:13], s[10:11]
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
@@ -6050,30 +8032,20 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg
; GPRIDX-NEXT: s_mov_b32 s6, s8
; GPRIDX-NEXT: s_mov_b32 s8, s10
; GPRIDX-NEXT: v_mov_b32_e32 v11, s9
-; GPRIDX-NEXT: v_mov_b32_e32 v3, s1
-; GPRIDX-NEXT: v_mov_b32_e32 v2, s0
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s12, 0
-; GPRIDX-NEXT: v_mov_b32_e32 v5, s3
-; GPRIDX-NEXT: v_mov_b32_e32 v4, s2
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s12, 1
-; GPRIDX-NEXT: v_mov_b32_e32 v7, s5
-; GPRIDX-NEXT: v_mov_b32_e32 v6, s4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s12, 2
+; GPRIDX-NEXT: v_mov_b32_e32 v10, s8
; GPRIDX-NEXT: v_mov_b32_e32 v9, s7
; GPRIDX-NEXT: v_mov_b32_e32 v8, s6
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v1, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s12, 3
-; GPRIDX-NEXT: v_mov_b32_e32 v10, s8
-; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s12, 4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc
+; GPRIDX-NEXT: v_mov_b32_e32 v7, s5
+; GPRIDX-NEXT: v_mov_b32_e32 v6, s4
+; GPRIDX-NEXT: v_mov_b32_e32 v5, s3
+; GPRIDX-NEXT: v_mov_b32_e32 v4, s2
+; GPRIDX-NEXT: v_mov_b32_e32 v3, s1
+; GPRIDX-NEXT: v_mov_b32_e32 v2, s0
+; GPRIDX-NEXT: s_lshl_b32 s0, s12, 1
+; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GPRIDX-NEXT: v_mov_b32_e32 v2, v0
+; GPRIDX-NEXT: v_mov_b32_e32 v3, v1
+; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v3
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v4
@@ -6082,8 +8054,8 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v7
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v8
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v9
-; GPRIDX-NEXT: v_readfirstlane_b32 s8, v0
-; GPRIDX-NEXT: v_readfirstlane_b32 s9, v1
+; GPRIDX-NEXT: v_readfirstlane_b32 s8, v10
+; GPRIDX-NEXT: v_readfirstlane_b32 s9, v11
; GPRIDX-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: dyn_insertelement_v5f64_s_v_s:
@@ -6099,6 +8071,8 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: v_mov_b32_e32 v11, s9
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: s_lshl_b32 m0, s12, 1
; GFX10-NEXT: v_mov_b32_e32 v10, s8
; GFX10-NEXT: v_mov_b32_e32 v9, s7
; GFX10-NEXT: v_mov_b32_e32 v8, s6
@@ -6107,32 +8081,18 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg
; GFX10-NEXT: v_mov_b32_e32 v5, s3
; GFX10-NEXT: v_mov_b32_e32 v4, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s1
-; GFX10-NEXT: v_mov_b32_e32 v2, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s12, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s12, 4
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v0, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 2
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v1, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s12, 3
-; GFX10-NEXT: v_readfirstlane_b32 s2, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v10, v0, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v11, v1, s1
+; GFX10-NEXT: v_movreld_b32_e32 v2, v0
+; GFX10-NEXT: v_movreld_b32_e32 v3, v1
; GFX10-NEXT: v_readfirstlane_b32 s0, v2
; GFX10-NEXT: v_readfirstlane_b32 s1, v3
+; GFX10-NEXT: v_readfirstlane_b32 s2, v4
; GFX10-NEXT: v_readfirstlane_b32 s3, v5
; GFX10-NEXT: v_readfirstlane_b32 s4, v6
; GFX10-NEXT: v_readfirstlane_b32 s5, v7
; GFX10-NEXT: v_readfirstlane_b32 s6, v8
; GFX10-NEXT: v_readfirstlane_b32 s7, v9
-; GFX10-NEXT: v_readfirstlane_b32 s8, v0
-; GFX10-NEXT: v_readfirstlane_b32 s9, v1
+; GFX10-NEXT: v_readfirstlane_b32 s8, v10
+; GFX10-NEXT: v_readfirstlane_b32 s9, v11
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: dyn_insertelement_v5f64_s_v_s:
@@ -6148,34 +8108,61 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg
; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: s_lshl_b32 m0, s12, 1
; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
-; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s12, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s12, 4
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_cndmask_b32 v3, v3, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v0, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 2
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v1, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s12, 3
-; GFX11-NEXT: v_readfirstlane_b32 s2, v4
-; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v0 :: v_dual_cndmask_b32 v7, v7, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v1, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, v10, v0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v11, v1, s1
+; GFX11-NEXT: v_movreld_b32_e32 v2, v0
+; GFX11-NEXT: v_movreld_b32_e32 v3, v1
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: v_readfirstlane_b32 s2, v4
; GFX11-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-NEXT: v_readfirstlane_b32 s4, v6
; GFX11-NEXT: v_readfirstlane_b32 s5, v7
; GFX11-NEXT: v_readfirstlane_b32 s6, v8
; GFX11-NEXT: v_readfirstlane_b32 s7, v9
-; GFX11-NEXT: v_readfirstlane_b32 s8, v0
-; GFX11-NEXT: v_readfirstlane_b32 s9, v1
+; GFX11-NEXT: v_readfirstlane_b32 s8, v10
+; GFX11-NEXT: v_readfirstlane_b32 s9, v11
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v5f64_s_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: v_mov_b32_e32 v11, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s8
+; GFX8-NEXT: v_mov_b32_e32 v9, s7
+; GFX8-NEXT: v_mov_b32_e32 v8, s6
+; GFX8-NEXT: v_mov_b32_e32 v7, s5
+; GFX8-NEXT: v_mov_b32_e32 v6, s4
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: s_lshl_b32 m0, s12, 1
+; GFX8-NEXT: v_movreld_b32_e32 v2, v0
+; GFX8-NEXT: v_movreld_b32_e32 v3, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v2
+; GFX8-NEXT: v_readfirstlane_b32 s1, v3
+; GFX8-NEXT: v_readfirstlane_b32 s2, v4
+; GFX8-NEXT: v_readfirstlane_b32 s3, v5
+; GFX8-NEXT: v_readfirstlane_b32 s4, v6
+; GFX8-NEXT: v_readfirstlane_b32 s5, v7
+; GFX8-NEXT: v_readfirstlane_b32 s6, v8
+; GFX8-NEXT: v_readfirstlane_b32 s7, v9
+; GFX8-NEXT: v_readfirstlane_b32 s8, v10
+; GFX8-NEXT: v_readfirstlane_b32 s9, v11
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
@@ -6321,6 +8308,55 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
; GFX11-NEXT: v_readfirstlane_b32 s8, v0
; GFX11-NEXT: v_readfirstlane_b32 s9, v1
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v5f64_s_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: s_mov_b32 s9, s11
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s8, s10
+; GFX8-NEXT: v_mov_b32_e32 v12, s9
+; GFX8-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX8-NEXT: v_mov_b32_e32 v6, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s2
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_mov_b32_e32 v8, s5
+; GFX8-NEXT: v_mov_b32_e32 v7, s4
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
+; GFX8-NEXT: v_mov_b32_e32 v11, s8
+; GFX8-NEXT: v_mov_b32_e32 v10, s7
+; GFX8-NEXT: v_mov_b32_e32 v9, s6
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 4, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v10, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v11, v0, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v12, v1, s[0:1]
+; GFX8-NEXT: v_readfirstlane_b32 s0, v3
+; GFX8-NEXT: v_readfirstlane_b32 s1, v4
+; GFX8-NEXT: v_readfirstlane_b32 s2, v5
+; GFX8-NEXT: v_readfirstlane_b32 s3, v6
+; GFX8-NEXT: v_readfirstlane_b32 s4, v7
+; GFX8-NEXT: v_readfirstlane_b32 s5, v8
+; GFX8-NEXT: v_readfirstlane_b32 s6, v9
+; GFX8-NEXT: v_readfirstlane_b32 s7, v2
+; GFX8-NEXT: v_readfirstlane_b32 s8, v0
+; GFX8-NEXT: v_readfirstlane_b32 s9, v1
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
@@ -6329,21 +8365,11 @@ entry:
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_s(<5 x double> %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_v_v_s:
; GPRIDX: ; %bb.0: ; %entry
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
-; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
-; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 2
-; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 3
-; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
-; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 4
-; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
-; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; GPRIDX-NEXT: s_lshl_b32 s0, s2, 1
+; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
+; GPRIDX-NEXT: v_mov_b32_e32 v0, v10
+; GPRIDX-NEXT: v_mov_b32_e32 v1, v11
+; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v0
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v1
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v2
@@ -6356,61 +8382,39 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_s(<5 x double> %vec,
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: dyn_insertelement_v5f64_v_v_s:
-; GFX10: ; %bb.0: ; %entry
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s2, 1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s2, 4
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
-; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s2, 3
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10-NEXT: v_readfirstlane_b32 s5, v5
-; GFX10-NEXT: v_readfirstlane_b32 s6, v6
-; GFX10-NEXT: v_readfirstlane_b32 s7, v7
-; GFX10-NEXT: v_readfirstlane_b32 s8, v8
-; GFX10-NEXT: v_readfirstlane_b32 s9, v9
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v5f64_v_v_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s2, 1
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v10
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v1, v11
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10PLUS-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: dyn_insertelement_v5f64_v_v_s:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s2, 1
-; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s2, 4
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11
-; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
-; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
-; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s2, 3
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v5, v5, v11
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v10, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v11, s0
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: v_readfirstlane_b32 s1, v1
-; GFX11-NEXT: v_readfirstlane_b32 s2, v2
-; GFX11-NEXT: v_readfirstlane_b32 s3, v3
-; GFX11-NEXT: v_readfirstlane_b32 s4, v4
-; GFX11-NEXT: v_readfirstlane_b32 s5, v5
-; GFX11-NEXT: v_readfirstlane_b32 s6, v6
-; GFX11-NEXT: v_readfirstlane_b32 s7, v7
-; GFX11-NEXT: v_readfirstlane_b32 s8, v8
-; GFX11-NEXT: v_readfirstlane_b32 s9, v9
-; GFX11-NEXT: ; return to shader part epilog
+; GFX8-LABEL: dyn_insertelement_v5f64_v_v_s:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_lshl_b32 m0, s2, 1
+; GFX8-NEXT: v_movreld_b32_e32 v0, v10
+; GFX8-NEXT: v_movreld_b32_e32 v1, v11
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
+; GFX8-NEXT: v_readfirstlane_b32 s4, v4
+; GFX8-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8-NEXT: v_readfirstlane_b32 s6, v6
+; GFX8-NEXT: v_readfirstlane_b32 s7, v7
+; GFX8-NEXT: v_readfirstlane_b32 s8, v8
+; GFX8-NEXT: v_readfirstlane_b32 s9, v9
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
@@ -6501,6 +8505,35 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec,
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: dyn_insertelement_v5f64_v_v_v:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
+; GFX8-NEXT: v_readfirstlane_b32 s4, v4
+; GFX8-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8-NEXT: v_readfirstlane_b32 s6, v6
+; GFX8-NEXT: v_readfirstlane_b32 s7, v7
+; GFX8-NEXT: v_readfirstlane_b32 s8, v8
+; GFX8-NEXT: v_readfirstlane_b32 s9, v9
+; GFX8-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
@@ -6540,6 +8573,17 @@ define void @insert_very_small_from_very_large(<32 x i16> %L3, ptr %ptr) {
; GFX11-NEXT: flat_store_b8 v[16:17], v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: insert_very_small_from_very_large:
+; GFX8: ; %bb.0: ; %bb
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 3, v0
+; GFX8-NEXT: flat_store_byte v[16:17], v0
+; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_setpc_b64 s[30:31]
bb:
%a = bitcast <32 x i16> %L3 to i512
%b = trunc i512 %a to i8
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll b/llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
index bc2f5566b0e62..2a4aba4a68048 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O1 -global-isel < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O1 -global-isel -new-reg-bank-select < %s | FileCheck %s
; Test that V_INDIRECT_REG_READ_GPR_IDX expansion handles immediate index operands.
; The wave.reduce.umin with constant arguments folds to 0, which becomes an
More information about the llvm-commits
mailing list