[llvm] [AMDGPU] Introduce GCNPostGenericScheduler to model MFMA-VALU coexecution (PR #184084)
Frederik Harwath via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 15 07:50:19 PDT 2026
================
@@ -3244,6 +3244,41 @@ static bool hasIGLPInstrs(ScheduleDAGInstrs *DAG) {
});
}
+void GCNPostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
+ MachineBasicBlock::iterator End,
+ unsigned NumRegionInstrs) {
+ LastTopScheduledIsMFMA = false;
+ LastBottomScheduledIsMFMA = false;
+ PostGenericScheduler::initPolicy(Begin, End, NumRegionInstrs);
+}
+
+void GCNPostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
+ // A non-MFMA VALU scheduled immediately after an MFMA requires a nop in
+ // between. Account for this by advancing the top boundary by one cycle
+ // before the VALU is scheduled.
+ if (SU->isInstr()) {
+ MachineInstr *MI = SU->getInstr();
+ bool IsNonMFMAVALU = SIInstrInfo::isVALU(*MI) && !SIInstrInfo::isMFMA(*MI);
+ if (IsNonMFMAVALU) {
+ if (IsTopNode && isLastTopScheduledIsMFMA()) {
+ Top.bumpCycle(Top.getCurrCycle() + 1);
+ LastTopScheduledIsMFMA = false;
+ }
+ if (!IsTopNode && isLastBottomScheduledIsMFMA()) {
+ Bot.bumpCycle(Bot.getCurrCycle() + 1);
+ LastBottomScheduledIsMFMA = false;
+ }
+ } else if (SIInstrInfo::isMFMA(*MI)) {
+ if (IsTopNode)
+ LastTopScheduledIsMFMA = true;
+ if (!IsTopNode)
+ LastBottomScheduledIsMFMA = true;
+ }
+ }
----------------
frederik-h wrote:
```suggestion
if (SU->isInstr() && SIInstrInfo::isVALU(*SU->getInstr())) {
bool IsMFMA = SIInstrInfo::isMFMA(*SU->getInstr());
auto Bump = [IsMFMA](SchedBoundary &Boundary, bool &LastIsMFMA) {
if (LastIsMFMA && !IsMFMA)
Boundary.bumpCycle(Boundary.getCurrCycle() + 1);
LastIsMFMA = IsMFMA;
};
if (IsTopNode)
Bump(Top, LastTopScheduledIsMFMA);
else
Bump(Bot, LastBottomScheduledIsMFMA);
}
```
https://github.com/llvm/llvm-project/pull/184084
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