[llvm] [AMDGPU] Introduce GCNPostGenericScheduler to model MFMA-VALU coexecution (PR #184084)

[Frederik Harwath via llvm-commits]

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@@ -3244,6 +3244,41 @@ static bool hasIGLPInstrs(ScheduleDAGInstrs *DAG) {
   });
 }
 
+void GCNPostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
+                                         MachineBasicBlock::iterator End,
+                                         unsigned NumRegionInstrs) {
+  LastTopScheduledIsMFMA = false;
+  LastBottomScheduledIsMFMA = false;
+  PostGenericScheduler::initPolicy(Begin, End, NumRegionInstrs);
+}
+
+void GCNPostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
+  // A non-MFMA VALU scheduled immediately after an MFMA requires a nop in
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frederik-h wrote:

I think this comment does not really match the code. What about the bottom boundary? And what happens if an MFMA is followed by a non-VALU instruction after LastTopScheduledIsMFMA was set to true. It will still be true on the next VALU instruction although the MFMA does not _immediately_ follow the MFMA.

https://github.com/llvm/llvm-project/pull/184084