[llvm] [AArch64] Use `AArch64ISD::UADDLP` for manual widening adjacent arithmetic (zext/shuffle combination) (PR #189255)

[David Green via llvm-commits]

https://github.com/davemgreen commented:

OK Nice work. Can we do the tablegen patterns first and then apply the DAG combine as a separate patch. I think we can do it generically for all `uzp(zext(low(x)), zext(hi(x))`, in a similar way we do for performZExtUZPCombine, and it should be profitable on it's own. That makes it best to split out separately from the tablegen patterns though.

Can you add test for all these types and make sure they work OK through tablegen pattern: https://godbolt.org/z/q7P8Gqqv6
```
define <8 x i16> @vpaddlq_v16i8(<16 x i8> %a) {
start:
  %0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
  %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
  %2 = zext <8 x i8> %0 to <8 x i16>
  %3 = zext <8 x i8> %1 to <8 x i16>
  %4 = add <8 x i16> %2, %3
  ret <8 x i16> %4
}

define <4 x i32> @vpaddlq_v8i16(<8 x i16> %a) {
start:
  %0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %2 = zext <4 x i16> %0 to <4 x i32>
  %3 = zext <4 x i16> %1 to <4 x i32>
  %4 = add <4 x i32> %2, %3
  ret <4 x i32> %4
}

define <2 x i64> @vpaddlq_v4i32(<4 x i32> %a) {
start:
  %0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
  %1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
  %2 = zext <2 x i32> %0 to <2 x i64>
  %3 = zext <2 x i32> %1 to <2 x i64>
  %4 = add <2 x i64> %2, %3
  ret <2 x i64> %4
}
```

The last one might be a little different.

https://github.com/llvm/llvm-project/pull/189255