[llvm] [AArch64][SVE][SelectionDAG] Improve codegen for SVE patterns sext(icmp) and zext(icmp) (PR #192052)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --diff_from_common_commit
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index d35ddf675..d22158afd 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -24466,8 +24466,9 @@ static SDValue performExtendCombine(SDNode *N,
     unsigned BitwidthMinusOne = N->getValueType(0).getScalarSizeInBits() - 1;
     EVT PredVT =
         N->getValueType(0).changeElementType(*DAG.getContext(), MVT::i1);
-    //SDValue AllTruePred = getPTrue(DAG, DL, PredVT, AArch64SVEPredPattern::all);
-    SDValue AllTruePred = ComparePred ;
+    // SDValue AllTruePred = getPTrue(DAG, DL, PredVT,
+    // AArch64SVEPredPattern::all);
+    SDValue AllTruePred = ComparePred;
     EVT EltVT = N->getValueType(0).getVectorElementType();
     MVT ConstantTy = EltVT.bitsGT(MVT::i32) ? MVT::i64 : MVT::i32;
     SDValue ShiftAmt =

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https://github.com/llvm/llvm-project/pull/192052