[llvm] [LoongArch][NFC] Add tests for bitwise with byte splat immediates (PR #192216)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 15 02:12:47 PDT 2026
https://github.com/heiher created https://github.com/llvm/llvm-project/pull/192216
None
>From 522de78dc119cd7d901284f0c29282aa9f40e01f Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Wed, 15 Apr 2026 16:52:36 +0800
Subject: [PATCH] [LoongArch][NFC] Add tests for bitwise with byte splat
immediates
---
.../LoongArch/lasx/ir-instruction/and.ll | 33 +++++++++++++++++
.../LoongArch/lasx/ir-instruction/nor.ll | 36 +++++++++++++++++++
.../LoongArch/lasx/ir-instruction/or.ll | 33 +++++++++++++++++
.../LoongArch/lasx/ir-instruction/xor.ll | 33 +++++++++++++++++
.../LoongArch/lsx/ir-instruction/and.ll | 33 +++++++++++++++++
.../LoongArch/lsx/ir-instruction/nor.ll | 36 +++++++++++++++++++
.../LoongArch/lsx/ir-instruction/or.ll | 33 +++++++++++++++++
.../LoongArch/lsx/ir-instruction/xor.ll | 33 +++++++++++++++++
8 files changed, 270 insertions(+)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
index a2df7aa1ae6d7..91f50f28464d2 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
@@ -124,3 +124,36 @@ entry:
store <4 x i64> %v1, ptr %res
ret void
}
+
+define <16 x i16> @and_u_v16i16_1(<16 x i16> %a) nounwind {
+; CHECK-LABEL: and_u_v16i16_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <16 x i16> %a, splat (i16 257)
+ ret <16 x i16> %0
+}
+
+define <8 x i32> @and_u_v8i32_1(<8 x i32> %a) nounwind {
+; CHECK-LABEL: and_u_v8i32_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <8 x i32> %a, splat (i32 16843009)
+ ret <8 x i32> %0
+}
+
+define <4 x i64> @and_u_v4i64_1(<4 x i64> %a) nounwind {
+; CHECK-LABEL: and_u_v4i64_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <4 x i64> %a, splat (i64 72340172838076673)
+ ret <4 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/nor.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/nor.ll
index 5050b6b0ccddc..691b98b0b1646 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/nor.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/nor.ll
@@ -132,3 +132,39 @@ entry:
store <4 x i64> %v2, ptr %res
ret void
}
+
+define <16 x i16> @nor_u_v16i16_1(<16 x i16> %a) nounwind {
+; CHECK-LABEL: nor_u_v16i16_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <16 x i16> %a, splat (i16 257)
+ %1 = xor <16 x i16> %0, splat (i16 65535)
+ ret <16 x i16> %1
+}
+
+define <8 x i32> @nor_u_v8i32_1(<8 x i32> %a) nounwind {
+; CHECK-LABEL: nor_u_v8i32_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <8 x i32> %a, splat (i32 16843009)
+ %1 = xor <8 x i32> %0, splat (i32 4294967295)
+ ret <8 x i32> %1
+}
+
+define <4 x i64> @nor_u_v4i64_1(<4 x i64> %a) nounwind {
+; CHECK-LABEL: nor_u_v4i64_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvnor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i64> %a, splat (i64 72340172838076673)
+ %1 = xor <4 x i64> %0, splat (i64 18446744073709551615)
+ ret <4 x i64> %1
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll
index 07ccb88f2bbad..a6f5e473d643d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll
@@ -124,3 +124,36 @@ entry:
store <4 x i64> %v1, ptr %res
ret void
}
+
+define <16 x i16> @or_u_v16i16_1(<16 x i16> %a) nounwind {
+; CHECK-LABEL: or_u_v16i16_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <16 x i16> %a, splat (i16 257)
+ ret <16 x i16> %0
+}
+
+define <8 x i32> @or_u_v8i32_1(<8 x i32> %a) nounwind {
+; CHECK-LABEL: or_u_v8i32_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <8 x i32> %a, splat (i32 16843009)
+ ret <8 x i32> %0
+}
+
+define <4 x i64> @or_u_v4i64_1(<4 x i64> %a) nounwind {
+; CHECK-LABEL: or_u_v4i64_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i64> %a, splat (i64 72340172838076673)
+ ret <4 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
index 5365685d395e4..a518148fe696c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
@@ -124,3 +124,36 @@ entry:
store <4 x i64> %v1, ptr %res
ret void
}
+
+define <16 x i16> @xor_u_v16i16_1(<16 x i16> %a) nounwind {
+; CHECK-LABEL: xor_u_v16i16_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <16 x i16> %a, splat (i16 257)
+ ret <16 x i16> %0
+}
+
+define <8 x i32> @xor_u_v8i32_1(<8 x i32> %a) nounwind {
+; CHECK-LABEL: xor_u_v8i32_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <8 x i32> %a, splat (i32 16843009)
+ ret <8 x i32> %0
+}
+
+define <4 x i64> @xor_u_v4i64_1(<4 x i64> %a) nounwind {
+; CHECK-LABEL: xor_u_v4i64_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.b $xr1, 1
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <4 x i64> %a, splat (i64 72340172838076673)
+ ret <4 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
index 2d6f0bea07122..f90ae0d34cb8c 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
@@ -124,3 +124,36 @@ entry:
store <2 x i64> %v1, ptr %res
ret void
}
+
+define <8 x i16> @and_u_v8i16_1(<8 x i16> %a) nounwind {
+; CHECK-LABEL: and_u_v8i16_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <8 x i16> %a, splat (i16 257)
+ ret <8 x i16> %0
+}
+
+define <4 x i32> @and_u_v4i32_1(<4 x i32> %a) nounwind {
+; CHECK-LABEL: and_u_v4i32_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <4 x i32> %a, splat (i32 16843009)
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @and_u_v2i64_1(<2 x i64> %a) nounwind {
+; CHECK-LABEL: and_u_v2i64_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <2 x i64> %a, splat (i64 72340172838076673)
+ ret <2 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/nor.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/nor.ll
index fc3e1645a0594..a23899c81ca04 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/nor.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/nor.ll
@@ -132,3 +132,39 @@ entry:
store <2 x i64> %v2, ptr %res
ret void
}
+
+define <8 x i16> @nor_u_v8i16_1(<8 x i16> %a) nounwind {
+; CHECK-LABEL: nor_u_v8i16_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <8 x i16> %a, splat (i16 257)
+ %1 = xor <8 x i16> %0, splat (i16 65535)
+ ret <8 x i16> %1
+}
+
+define <4 x i32> @nor_u_v4i32_1(<4 x i32> %a) nounwind {
+; CHECK-LABEL: nor_u_v4i32_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i32> %a, splat (i32 16843009)
+ %1 = xor <4 x i32> %0, splat (i32 4294967295)
+ ret <4 x i32> %1
+}
+
+define <2 x i64> @nor_u_v2i64_1(<2 x i64> %a) nounwind {
+; CHECK-LABEL: nor_u_v2i64_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <2 x i64> %a, splat (i64 72340172838076673)
+ %1 = xor <2 x i64> %0, splat (i64 18446744073709551615)
+ ret <2 x i64> %1
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
index 94a1294384578..7188783b0ce56 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
@@ -124,3 +124,36 @@ entry:
store <2 x i64> %v1, ptr %res
ret void
}
+
+define <8 x i16> @or_u_v8i16_1(<8 x i16> %a) nounwind {
+; CHECK-LABEL: or_u_v8i16_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <8 x i16> %a, splat (i16 257)
+ ret <8 x i16> %0
+}
+
+define <4 x i32> @or_u_v4i32_1(<4 x i32> %a) nounwind {
+; CHECK-LABEL: or_u_v4i32_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i32> %a, splat (i32 16843009)
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @or_u_v2i64_1(<2 x i64> %a) nounwind {
+; CHECK-LABEL: or_u_v2i64_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <2 x i64> %a, splat (i64 72340172838076673)
+ ret <2 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
index fd63b2122a8b7..e7298fc28273e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
@@ -124,3 +124,36 @@ entry:
store <2 x i64> %v1, ptr %res
ret void
}
+
+define <8 x i16> @xor_u_v8i16_1(<8 x i16> %a) nounwind {
+; CHECK-LABEL: xor_u_v8i16_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <8 x i16> %a, splat (i16 257)
+ ret <8 x i16> %0
+}
+
+define <4 x i32> @xor_u_v4i32_1(<4 x i32> %a) nounwind {
+; CHECK-LABEL: xor_u_v4i32_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <4 x i32> %a, splat (i32 16843009)
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @xor_u_v2i64_1(<2 x i64> %a) nounwind {
+; CHECK-LABEL: xor_u_v2i64_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.b $vr1, 1
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <2 x i64> %a, splat (i64 72340172838076673)
+ ret <2 x i64> %0
+}
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