[llvm] [AArch64][GlobalISel] FP Info implementation for AArch64. (PR #177158)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 15 02:12:32 PDT 2026
https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/177158
>From c46e08dcf438302474e1af1397de58491ecb4983 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 13 Apr 2026 12:01:11 +0100
Subject: [PATCH 01/30] [AArch64][GISel] Regbank G_BITCAST using src regbank.
This takes the regbank of a G_BITCAST from the input srcreg that has already
been allocated, keeping the bitcast on the same bank. A copy then might be
added to the dst if needed.
onlyUsesFP is also improved for G_BITCAST, allowing operations to guess the
correct type through a onlyUsesFP too.
Originally from #177158 by Ryan Cowan with modifications.
---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 27 +++++--
.../GlobalISel/arm64-regbankselect.mir | 45 +++++-------
llvm/test/CodeGen/AArch64/add.ll | 3 +-
llvm/test/CodeGen/AArch64/andorxor.ll | 9 +--
.../test/CodeGen/AArch64/arm64-neon-3vdiff.ll | 72 +++++++------------
llvm/test/CodeGen/AArch64/concat-vector.ll | 48 ++++++-------
llvm/test/CodeGen/AArch64/ctlz.ll | 3 +-
llvm/test/CodeGen/AArch64/ctpop.ll | 7 +-
llvm/test/CodeGen/AArch64/cttz.ll | 3 +-
.../CodeGen/AArch64/highextractbitcast.ll | 5 +-
llvm/test/CodeGen/AArch64/mul.ll | 3 +-
llvm/test/CodeGen/AArch64/popcount.ll | 39 +++++-----
llvm/test/CodeGen/AArch64/qmovn.ll | 40 +++++------
llvm/test/CodeGen/AArch64/sadd_sat_vec.ll | 3 +-
llvm/test/CodeGen/AArch64/ssub_sat_vec.ll | 3 +-
llvm/test/CodeGen/AArch64/sub.ll | 3 +-
llvm/test/CodeGen/AArch64/uadd_sat_vec.ll | 3 +-
llvm/test/CodeGen/AArch64/usub_sat_vec.ll | 3 +-
18 files changed, 139 insertions(+), 180 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index de0577a893005..fba8323e62ff8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -712,6 +712,15 @@ bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
const AArch64RegisterInfo &TRI,
unsigned Depth) const {
switch (MI.getOpcode()) {
+ case TargetOpcode::G_BITCAST: {
+ Register DstReg = MI.getOperand(0).getReg();
+ return all_of(MRI.use_nodbg_instructions(DstReg),
+ [&](const MachineInstr &UseMI) {
+ return onlyUsesFP(UseMI, MRI, TRI, Depth + 1) ||
+ prefersFPUse(UseMI, MRI, TRI);
+ });
+ }
+
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_FPTOSI_SAT:
@@ -897,6 +906,19 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
&ValMappings[Shift64Imm], 3);
return getSameKindOfOperandsMapping(MI);
}
+ case TargetOpcode::G_BITCAST: {
+ Register SrcReg = MI.getOperand(1).getReg();
+ const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
+ if (SrcRB) {
+ TypeSize Size = getSizeInBits(SrcReg, MRI, TRI);
+ return getInstructionMapping(
+ DefaultMappingID, 0,
+ getCopyMapping(SrcRB->getID(), SrcRB->getID(), Size),
+ // We only care about the mapping of the destination.
+ /*NumOperands*/ 2);
+ }
+ [[fallthrough]];
+ }
case TargetOpcode::COPY: {
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
@@ -919,10 +941,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
// We only care about the mapping of the destination.
/*NumOperands*/ 1);
}
- // Both registers are generic, use G_BITCAST.
- [[fallthrough]];
- }
- case TargetOpcode::G_BITCAST: {
+ // Both registers are generic
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
TypeSize Size = DstTy.getSizeInBits();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
index a29a46bd43e49..b1eded3d40387 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
@@ -398,16 +398,14 @@ legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
-# FAST-NEXT: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }
-# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: body:
-# CHECK: %0:gpr(s32) = COPY $w0
-# FAST-NEXT: %1:fpr(<4 x s8>) = G_BITCAST %0
-# GREEDY-NEXT: %1:gpr(<4 x s8>) = G_BITCAST %0
+# CHECK: %0:gpr(s32) = COPY $w0
+# CHECK-NEXT: %1:gpr(<4 x s8>) = G_BITCAST %0
# The greedy check is incorrect and should produce fpr.
body: |
bb.0:
@@ -423,17 +421,15 @@ name: bitcast_s32_fpr
legalized: true
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '', flags: [ ] }
-# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
-# GREEDY-NEXT: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s16>) = COPY $s0
-# FAST: %1:gpr(s32) = G_BITCAST %0
-# GREEDY: %1:fpr(s32) = G_BITCAST %0
+# CHECK: %1:fpr(s32) = G_BITCAST %0
body: |
bb.0:
liveins: $s0
@@ -449,16 +445,14 @@ legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
-# FAST-NEXT: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }
-# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:gpr(s32) = COPY $w0
-# FAST: %1:fpr(<2 x s16>) = G_BITCAST %0
-# GREEDY: %1:gpr(<2 x s16>) = G_BITCAST %0
+# CHECK: %1:gpr(<2 x s16>) = G_BITCAST %0
body: |
bb.0:
liveins: $w0
@@ -476,8 +470,7 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s16>) = COPY $s0
-# FAST: %1:gpr(s32) = G_BITCAST %0
-# GREEDY: %1:fpr(s32) = G_BITCAST %0
+# CHECK: %1:fpr(s32) = G_BITCAST %0
body: |
bb.0:
liveins: $s0
@@ -495,8 +488,7 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:gpr(s64) = COPY $x0
-# FAST: %1:fpr(<2 x s32>) = G_BITCAST %0
-# GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0
+# CHECK: %1:gpr(<2 x s32>) = G_BITCAST %0
body: |
bb.0:
liveins: $x0
@@ -514,8 +506,7 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s32>) = COPY $d0
-# FAST: %1:gpr(s64) = G_BITCAST %0
-# GREEDY: %1:fpr(s64) = G_BITCAST %0
+# CHECK: %1:fpr(s64) = G_BITCAST %0
body: |
bb.0:
liveins: $d0
@@ -533,8 +524,7 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:gpr(s64) = COPY $x0
-# FAST: %1:fpr(<2 x s32>) = G_BITCAST %0
-# GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0
+# CHECK: %1:gpr(<2 x s32>) = G_BITCAST %0
body: |
bb.0:
liveins: $x0
@@ -552,8 +542,7 @@ registers:
- { id: 1, class: _ }
# CHECK: body:
# CHECK: %0:fpr(<2 x s32>) = COPY $d0
-# FAST: %1:gpr(s64) = G_BITCAST %0
-# GREEDY: %1:fpr(s64) = G_BITCAST %0
+# CHECK: %1:fpr(s64) = G_BITCAST %0
body: |
bb.0:
liveins: $d0
@@ -691,13 +680,15 @@ registers:
# No repairing should be necessary for both modes.
# CHECK: %0:gpr(s64) = COPY $x0
# CHECK-NEXT: %1:gpr(p0) = COPY $x1
-# FAST-NEXT: %2:fpr(<2 x s32>) = G_BITCAST %0(s64)
+# FAST-NEXT: %2:gpr(<2 x s32>) = G_BITCAST %0(s64)
# FAST-NEXT: %3:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>) from %ir.addr)
-# FAST-NEXT: %4:fpr(<2 x s32>) = G_OR %2, %3
+# FAST-NEXT: %6:fpr(<2 x s32>) = COPY %2
+# FAST-NEXT: %4:fpr(<2 x s32>) = G_OR %6, %3
+# FAST-NEXT: %5:fpr(s64) = G_BITCAST %4(<2 x s32>)
# GREEDY-NEXT: %2:gpr(<2 x s32>) = G_BITCAST %0(s64)
# GREEDY-NEXT: %3:gpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>) from %ir.addr)
# GREEDY-NEXT: %4:gpr(<2 x s32>) = G_OR %2, %3
-# CHECK-NEXT: %5:gpr(s64) = G_BITCAST %4(<2 x s32>)
+# GREEDY-NEXT: %5:gpr(s64) = G_BITCAST %4(<2 x s32>)
# CHECK-NEXT: $x0 = COPY %5(s64)
# CHECK-NEXT: RET_ReallyLR implicit $x0
body: |
diff --git a/llvm/test/CodeGen/AArch64/add.ll b/llvm/test/CodeGen/AArch64/add.ll
index 7502db4c5aa93..f2c7ca7bac03d 100644
--- a/llvm/test/CodeGen/AArch64/add.ll
+++ b/llvm/test/CodeGen/AArch64/add.ll
@@ -174,8 +174,7 @@ define void @v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: add v0.4h, v0.4h, v1.4h
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/andorxor.ll b/llvm/test/CodeGen/AArch64/andorxor.ll
index d8d003c85eed6..f967bf2fbaefc 100644
--- a/llvm/test/CodeGen/AArch64/andorxor.ll
+++ b/llvm/test/CodeGen/AArch64/andorxor.ll
@@ -472,8 +472,7 @@ define void @and_v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
@@ -521,8 +520,7 @@ define void @or_v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
@@ -570,8 +568,7 @@ define void @xor_v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll b/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
index 8cb319b2c3368..79822682c2178 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
@@ -1076,8 +1076,7 @@ define <16 x i8> @test_vaddhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addhn v1.8b, v1.8h, v2.8h
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vaddhn.i.i = add <8 x i16> %a, %b
@@ -1101,8 +1100,7 @@ define <8 x i16> @test_vaddhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addhn v1.4h, v1.4s, v2.4s
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vaddhn.i.i = add <4 x i32> %a, %b
@@ -1126,8 +1124,7 @@ define <4 x i32> @test_vaddhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addhn v1.2s, v1.2d, v2.2d
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vaddhn.i.i = add <2 x i64> %a, %b
@@ -1151,8 +1148,7 @@ define <16 x i8> @test_vaddhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addhn v1.8b, v1.8h, v2.8h
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vaddhn.i.i = add <8 x i16> %a, %b
@@ -1176,8 +1172,7 @@ define <8 x i16> @test_vaddhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addhn v1.4h, v1.4s, v2.4s
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vaddhn.i.i = add <4 x i32> %a, %b
@@ -1201,8 +1196,7 @@ define <4 x i32> @test_vaddhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: addhn v1.2s, v1.2d, v2.2d
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vaddhn.i.i = add <2 x i64> %a, %b
@@ -1286,8 +1280,7 @@ define <16 x i8> @test_vraddhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: raddhn v1.8b, v1.8h, v2.8h
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vraddhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)
@@ -1309,8 +1302,7 @@ define <8 x i16> @test_vraddhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: raddhn v1.4h, v1.4s, v2.4s
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vraddhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)
@@ -1332,8 +1324,7 @@ define <4 x i32> @test_vraddhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: raddhn v1.2s, v1.2d, v2.2d
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vraddhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)
@@ -1355,8 +1346,7 @@ define <16 x i8> @test_vraddhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: raddhn v1.8b, v1.8h, v2.8h
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vraddhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)
@@ -1378,8 +1368,7 @@ define <8 x i16> @test_vraddhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: raddhn v1.4h, v1.4s, v2.4s
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vraddhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)
@@ -1401,8 +1390,7 @@ define <4 x i32> @test_vraddhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: raddhn v1.2s, v1.2d, v2.2d
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vraddhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)
@@ -1496,8 +1484,7 @@ define <16 x i8> @test_vsubhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: subhn v1.8b, v1.8h, v2.8h
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vsubhn.i.i = sub <8 x i16> %a, %b
@@ -1521,8 +1508,7 @@ define <8 x i16> @test_vsubhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: subhn v1.4h, v1.4s, v2.4s
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vsubhn.i.i = sub <4 x i32> %a, %b
@@ -1546,8 +1532,7 @@ define <4 x i32> @test_vsubhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: subhn v1.2s, v1.2d, v2.2d
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vsubhn.i.i = sub <2 x i64> %a, %b
@@ -1571,8 +1556,7 @@ define <16 x i8> @test_vsubhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: subhn v1.8b, v1.8h, v2.8h
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vsubhn.i.i = sub <8 x i16> %a, %b
@@ -1596,8 +1580,7 @@ define <8 x i16> @test_vsubhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: subhn v1.4h, v1.4s, v2.4s
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vsubhn.i.i = sub <4 x i32> %a, %b
@@ -1621,8 +1604,7 @@ define <4 x i32> @test_vsubhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: subhn v1.2s, v1.2d, v2.2d
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vsubhn.i.i = sub <2 x i64> %a, %b
@@ -1706,8 +1688,7 @@ define <16 x i8> @test_vrsubhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: rsubhn v1.8b, v1.8h, v2.8h
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vrsubhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)
@@ -1729,8 +1710,7 @@ define <8 x i16> @test_vrsubhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: rsubhn v1.4h, v1.4s, v2.4s
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vrsubhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)
@@ -1752,8 +1732,7 @@ define <4 x i32> @test_vrsubhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: rsubhn v1.2s, v1.2d, v2.2d
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vrsubhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)
@@ -1775,8 +1754,7 @@ define <16 x i8> @test_vrsubhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b)
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: rsubhn v1.8b, v1.8h, v2.8h
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vrsubhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)
@@ -1798,8 +1776,7 @@ define <8 x i16> @test_vrsubhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: rsubhn v1.4h, v1.4s, v2.4s
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vrsubhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)
@@ -1821,8 +1798,7 @@ define <4 x i32> @test_vrsubhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: rsubhn v1.2s, v1.2d, v2.2d
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
%vrsubhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)
diff --git a/llvm/test/CodeGen/AArch64/concat-vector.ll b/llvm/test/CodeGen/AArch64/concat-vector.ll
index e6f27b95d92c8..e6e863b074592 100644
--- a/llvm/test/CodeGen/AArch64/concat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/concat-vector.ll
@@ -32,10 +32,9 @@ define <8 x i8> @concat2(<4 x i8> %A, <4 x i8> %B) {
;
; CHECK-GI-LABEL: concat2:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s1
-; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%v8i8 = shufflevector <4 x i8> %A, <4 x i8> %B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -61,10 +60,9 @@ define <4 x i16> @concat4(<2 x i16> %A, <2 x i16> %B) {
;
; CHECK-GI-LABEL: concat4:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: fmov w8, s1
-; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%v4i16 = shufflevector <2 x i16> %A, <2 x i16> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -125,9 +123,9 @@ define <4 x half> @concat9(<2 x half> %A, <2 x half> %B) {
;
; CHECK-GI-LABEL: concat9:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fmov w8, s1
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%v4half= shufflevector <2 x half> %A, <2 x half> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -215,16 +213,13 @@ define <16 x i8> @concat_v16s8_v4s8_reg(<4 x i8> %A, <4 x i8> %B, <4 x i8> %C, <
;
; CHECK-GI-LABEL: concat_v16s8_v4s8_reg:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: uzp1 v2.8b, v2.8b, v0.8b
-; CHECK-GI-NEXT: mov v0.s[1], w8
-; CHECK-GI-NEXT: fmov w8, s2
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: uzp1 v1.8b, v3.8b, v0.8b
-; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: fmov w8, s1
-; CHECK-GI-NEXT: mov v0.s[3], w8
+; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v1.s[0]
; CHECK-GI-NEXT: ret
%b = shufflevector <4 x i8> %A, <4 x i8> %B, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%c = shufflevector <4 x i8> %C, <4 x i8> %D, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -246,16 +241,13 @@ define <8 x i16> @concat_v8s16_v2s16_reg(<2 x i16> %A, <2 x i16> %B, <2 x i16> %
;
; CHECK-GI-LABEL: concat_v8s16_v2s16_reg:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: uzp1 v2.4h, v2.4h, v0.4h
-; CHECK-GI-NEXT: mov v0.s[1], w8
-; CHECK-GI-NEXT: fmov w8, s2
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: uzp1 v1.4h, v3.4h, v0.4h
-; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: fmov w8, s1
-; CHECK-GI-NEXT: mov v0.s[3], w8
+; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v1.s[0]
; CHECK-GI-NEXT: ret
%b = shufflevector <2 x i16> %A, <2 x i16> %B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%c = shufflevector <2 x i16> %C, <2 x i16> %D, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -273,9 +265,9 @@ define <4 x i16> @concat_undef_first_use_first(ptr %p1, ptr %p2) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldrh w8, [x0]
; CHECK-GI-NEXT: ldrh w9, [x0, #2]
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: mov v1.h[1], w9
-; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov v0.h[1], w9
+; CHECK-GI-NEXT: mov v0.s[1], v0.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%l1 = load <2 x i16>, ptr %p1
@@ -296,9 +288,9 @@ define <4 x i16> @concat_undef_first_use_second(ptr %p1, ptr %p2) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldrh w8, [x0]
; CHECK-GI-NEXT: ldrh w9, [x0, #2]
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: mov v1.h[1], w9
-; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov v0.h[1], w9
+; CHECK-GI-NEXT: mov v0.s[1], v0.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%l1 = load <2 x i16>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/ctlz.ll b/llvm/test/CodeGen/AArch64/ctlz.ll
index b45b48d06071b..5740eaa977875 100644
--- a/llvm/test/CodeGen/AArch64/ctlz.ll
+++ b/llvm/test/CodeGen/AArch64/ctlz.ll
@@ -99,8 +99,7 @@ define void @v4i8(ptr %p1) {
; CHECK-GI-NEXT: mov v2.b[2], v3.b[0]
; CHECK-GI-NEXT: mov v2.b[3], v0.b[0]
; CHECK-GI-NEXT: clz v0.8b, v2.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/ctpop.ll b/llvm/test/CodeGen/AArch64/ctpop.ll
index 9e7e5888fa6e6..be62efca6cb6a 100644
--- a/llvm/test/CodeGen/AArch64/ctpop.ll
+++ b/llvm/test/CodeGen/AArch64/ctpop.ll
@@ -97,8 +97,7 @@ define void @v4i8(ptr %p1) {
; CHECK-GI-NEXT: mov v2.b[2], v3.b[0]
; CHECK-GI-NEXT: mov v2.b[3], v0.b[0]
; CHECK-GI-NEXT: cnt v0.8b, v2.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
@@ -572,7 +571,7 @@ define i32 @i32_mask(i32 %x) {
; CHECK-GI-LABEL: i32_mask:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: and w8, w0, #0xff
-; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: fmov d0, x8
; CHECK-GI-NEXT: cnt v0.8b, v0.8b
; CHECK-GI-NEXT: uaddlv h0, v0.8b
; CHECK-GI-NEXT: fmov w0, s0
@@ -596,7 +595,7 @@ define i32 @i32_mask_negative(i32 %x) {
; CHECK-GI-LABEL: i32_mask_negative:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: and w8, w0, #0xffff
-; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: fmov d0, x8
; CHECK-GI-NEXT: cnt v0.8b, v0.8b
; CHECK-GI-NEXT: uaddlv h0, v0.8b
; CHECK-GI-NEXT: fmov w0, s0
diff --git a/llvm/test/CodeGen/AArch64/cttz.ll b/llvm/test/CodeGen/AArch64/cttz.ll
index 86c1aca9ed9e1..b04e8df455357 100644
--- a/llvm/test/CodeGen/AArch64/cttz.ll
+++ b/llvm/test/CodeGen/AArch64/cttz.ll
@@ -127,8 +127,7 @@ define void @v4i8(ptr %p1) {
; CHECK-GI-NEXT: and v0.8b, v2.8b, v0.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: cnt v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/highextractbitcast.ll b/llvm/test/CodeGen/AArch64/highextractbitcast.ll
index bd6c168ce8776..de2911b8a5127 100644
--- a/llvm/test/CodeGen/AArch64/highextractbitcast.ll
+++ b/llvm/test/CodeGen/AArch64/highextractbitcast.ll
@@ -599,10 +599,9 @@ define <8 x i16> @foov8i16(<16 x i8> %a1, <2 x i64> %b1) {
;
; CHECK-GI-LABEL: foov8i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: shrn v1.4h, v1.4s, #5
; CHECK-GI-NEXT: shrn v0.4h, v0.4s, #5
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: shrn v1.4h, v1.4s, #5
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
%a0 = bitcast <16 x i8> %a1 to <4 x i32>
%b0 = bitcast <2 x i64> %b1 to <4 x i32>
diff --git a/llvm/test/CodeGen/AArch64/mul.ll b/llvm/test/CodeGen/AArch64/mul.ll
index 475bd22c6ebcb..10400fd442cb1 100644
--- a/llvm/test/CodeGen/AArch64/mul.ll
+++ b/llvm/test/CodeGen/AArch64/mul.ll
@@ -186,8 +186,7 @@ define void @v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: mul v0.4h, v0.4h, v1.4h
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/popcount.ll b/llvm/test/CodeGen/AArch64/popcount.ll
index 5a759b0be06ac..bb81776a7f6d6 100644
--- a/llvm/test/CodeGen/AArch64/popcount.ll
+++ b/llvm/test/CodeGen/AArch64/popcount.ll
@@ -439,8 +439,6 @@ declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
define <1 x i64> @popcount1x64(<1 x i64> %0) {
; CHECKO0-LABEL: popcount1x64:
; CHECKO0: // %bb.0: // %Entry
-; CHECKO0-NEXT: fmov x0, d0
-; CHECKO0-NEXT: fmov d0, x0
; CHECKO0-NEXT: cnt v0.8b, v0.8b
; CHECKO0-NEXT: uaddlv h0, v0.8b
; CHECKO0-NEXT: // kill: def $q0 killed $h0
@@ -492,8 +490,6 @@ define <1 x i64> @popcount1x64(<1 x i64> %0) {
;
; GISELO0-LABEL: popcount1x64:
; GISELO0: // %bb.0: // %Entry
-; GISELO0-NEXT: fmov x0, d0
-; GISELO0-NEXT: fmov d0, x0
; GISELO0-NEXT: cnt v0.8b, v0.8b
; GISELO0-NEXT: uaddlv h0, v0.8b
; GISELO0-NEXT: // kill: def $q0 killed $h0
@@ -776,10 +772,11 @@ define i32 @ctpop_into_extract(ptr %p) {
; CHECKO0-NEXT: // implicit-def: $d2
; CHECKO0-NEXT: fmov s2, w8
; CHECKO0-NEXT: ldr d0, [x0]
-; CHECKO0-NEXT: fmov s1, s0
-; CHECKO0-NEXT: fmov w8, s1
-; CHECKO0-NEXT: fmov s1, w8
-; CHECKO0-NEXT: // kill: def $d1 killed $s1
+; CHECKO0-NEXT: // implicit-def: $q1
+; CHECKO0-NEXT: fmov d1, d0
+; CHECKO0-NEXT: mov w8, v1.s[0]
+; CHECKO0-NEXT: mov w1, w8
+; CHECKO0-NEXT: fmov d1, x1
; CHECKO0-NEXT: cnt v1.8b, v1.8b
; CHECKO0-NEXT: uaddlv h1, v1.8b
; CHECKO0-NEXT: // kill: def $q1 killed $h1
@@ -858,8 +855,8 @@ define i32 @ctpop_into_extract(ptr %p) {
; GISEL-NEXT: ldr d0, [x0]
; GISEL-NEXT: mov x8, x0
; GISEL-NEXT: mov w0, wzr
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: fmov s1, w9
+; GISEL-NEXT: mov w9, v0.s[0]
+; GISEL-NEXT: fmov d1, x9
; GISEL-NEXT: mov w9, #-1 // =0xffffffff
; GISEL-NEXT: fmov s2, w9
; GISEL-NEXT: cnt v1.8b, v1.8b
@@ -875,10 +872,11 @@ define i32 @ctpop_into_extract(ptr %p) {
; GISELO0-NEXT: // implicit-def: $d2
; GISELO0-NEXT: fmov s2, w8
; GISELO0-NEXT: ldr d0, [x0]
-; GISELO0-NEXT: fmov s1, s0
-; GISELO0-NEXT: fmov w8, s1
-; GISELO0-NEXT: fmov s1, w8
-; GISELO0-NEXT: // kill: def $d1 killed $s1
+; GISELO0-NEXT: // implicit-def: $q1
+; GISELO0-NEXT: fmov d1, d0
+; GISELO0-NEXT: mov w8, v1.s[0]
+; GISELO0-NEXT: mov w1, w8
+; GISELO0-NEXT: fmov d1, x1
; GISELO0-NEXT: cnt v1.8b, v1.8b
; GISELO0-NEXT: uaddlv h1, v1.8b
; GISELO0-NEXT: // kill: def $q1 killed $h1
@@ -905,8 +903,9 @@ define <8 x i8> @bitcast_upper_bits(i32 %b, <8 x i8> %v) {
; CHECKO0-LABEL: bitcast_upper_bits:
; CHECKO0: // %bb.0:
; CHECKO0-NEXT: fmov d1, d0
-; CHECKO0-NEXT: fmov s0, w0
-; CHECKO0-NEXT: // kill: def $d0 killed $s0
+; CHECKO0-NEXT: mov w8, w0
+; CHECKO0-NEXT: mov w0, w8
+; CHECKO0-NEXT: fmov d0, x0
; CHECKO0-NEXT: add v0.8b, v0.8b, v1.8b
; CHECKO0-NEXT: ret
;
@@ -926,15 +925,17 @@ define <8 x i8> @bitcast_upper_bits(i32 %b, <8 x i8> %v) {
;
; GISEL-LABEL: bitcast_upper_bits:
; GISEL: // %bb.0:
-; GISEL-NEXT: fmov s1, w0
+; GISEL-NEXT: mov w8, w0
+; GISEL-NEXT: fmov d1, x8
; GISEL-NEXT: add v0.8b, v1.8b, v0.8b
; GISEL-NEXT: ret
;
; GISELO0-LABEL: bitcast_upper_bits:
; GISELO0: // %bb.0:
; GISELO0-NEXT: fmov d1, d0
-; GISELO0-NEXT: fmov s0, w0
-; GISELO0-NEXT: // kill: def $d0 killed $s0
+; GISELO0-NEXT: mov w8, w0
+; GISELO0-NEXT: mov w0, w8
+; GISELO0-NEXT: fmov d0, x0
; GISELO0-NEXT: add v0.8b, v0.8b, v1.8b
; GISELO0-NEXT: ret
%a = zext i32 %b to i64
diff --git a/llvm/test/CodeGen/AArch64/qmovn.ll b/llvm/test/CodeGen/AArch64/qmovn.ll
index dc1b7df9b32ae..5d534e09cdbd3 100644
--- a/llvm/test/CodeGen/AArch64/qmovn.ll
+++ b/llvm/test/CodeGen/AArch64/qmovn.ll
@@ -645,16 +645,15 @@ define <4 x i16> @sminsmax_range_unsigned_i64_to_i16(<2 x i16> %x, <2 x i64> %y)
;
; CHECK-GI-LABEL: sminsmax_range_unsigned_i64_to_i16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, #0
-; CHECK-GI-NEXT: movi v3.2d, #0x0000000000ffff
-; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: cmgt v2.2d, v3.2d, v1.2d
-; CHECK-GI-NEXT: bif v1.16b, v3.16b, v2.16b
+; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, #0
+; CHECK-GI-NEXT: movi v2.2d, #0x0000000000ffff
+; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b
+; CHECK-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
; CHECK-GI-NEXT: xtn v1.2s, v1.2d
; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: fmov w8, s1
-; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -683,6 +682,7 @@ define <4 x i16> @sminsmax_range_signed_i64_to_i16(<2 x i16> %x, <2 x i64> %y) {
; CHECK-GI-LABEL: sminsmax_range_signed_i64_to_i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: adrp x8, .LCPI46_1
+; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI46_1]
; CHECK-GI-NEXT: adrp x8, .LCPI46_0
; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
@@ -692,9 +692,7 @@ define <4 x i16> @sminsmax_range_signed_i64_to_i16(<2 x i16> %x, <2 x i64> %y) {
; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
; CHECK-GI-NEXT: xtn v1.2s, v1.2d
; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: fmov w8, s1
-; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -718,13 +716,12 @@ define <4 x i16> @umin_range_unsigned_i64_to_i16(<2 x i16> %x, <2 x i64> %y) {
; CHECK-GI-LABEL: umin_range_unsigned_i64_to_i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.2d, #0x0000000000ffff
+; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: cmhi v3.2d, v2.2d, v1.2d
; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
; CHECK-GI-NEXT: xtn v1.2s, v1.2d
; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: fmov w8, s1
-; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -750,13 +747,12 @@ define <8 x i8> @sminsmax_range_unsigned_i64_to_i8(<4 x i8> %x, <4 x i32> %y) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
; CHECK-GI-NEXT: movi v3.2d, #0x0000ff000000ff
+; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
; CHECK-GI-NEXT: smin v1.4s, v1.4s, v3.4s
; CHECK-GI-NEXT: xtn v1.4h, v1.4s
; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s1
-; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -782,13 +778,12 @@ define <8 x i8> @sminsmax_range_signed_i32_to_i8(<4 x i8> %x, <4 x i32> %y) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mvni v2.4s, #127
; CHECK-GI-NEXT: movi v3.4s, #127
+; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
; CHECK-GI-NEXT: smin v1.4s, v1.4s, v3.4s
; CHECK-GI-NEXT: xtn v1.4h, v1.4s
; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s1
-; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -811,12 +806,11 @@ define <8 x i8> @umin_range_unsigned_i32_to_i8(<4 x i8> %x, <4 x i32> %y) {
; CHECK-GI-LABEL: umin_range_unsigned_i32_to_i8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.2d, #0x0000ff000000ff
+; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: umin v1.4s, v1.4s, v2.4s
; CHECK-GI-NEXT: xtn v1.4h, v1.4s
; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s1
-; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
index b31a5ea0b5d79..88f1324762f8f 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
@@ -146,8 +146,7 @@ define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]
; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]
; CHECK-GI-NEXT: sqadd v0.8b, v3.8b, v5.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x2]
+; CHECK-GI-NEXT: str s0, [x2]
; CHECK-GI-NEXT: ret
%x = load <4 x i8>, ptr %px
%y = load <4 x i8>, ptr %py
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
index 02eb40b412efd..55608f6ef21b8 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
@@ -146,8 +146,7 @@ define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]
; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]
; CHECK-GI-NEXT: sqsub v0.8b, v3.8b, v5.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x2]
+; CHECK-GI-NEXT: str s0, [x2]
; CHECK-GI-NEXT: ret
%x = load <4 x i8>, ptr %px
%y = load <4 x i8>, ptr %py
diff --git a/llvm/test/CodeGen/AArch64/sub.ll b/llvm/test/CodeGen/AArch64/sub.ll
index dd920b98e18eb..402f35e134dbe 100644
--- a/llvm/test/CodeGen/AArch64/sub.ll
+++ b/llvm/test/CodeGen/AArch64/sub.ll
@@ -174,8 +174,7 @@ define void @v4i8(ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: sub v0.4h, v0.4h, v1.4h
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x0]
+; CHECK-GI-NEXT: str s0, [x0]
; CHECK-GI-NEXT: ret
entry:
%d = load <4 x i8>, ptr %p1
diff --git a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
index cd02d18e61643..644313c953607 100644
--- a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
@@ -143,8 +143,7 @@ define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]
; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]
; CHECK-GI-NEXT: uqadd v0.8b, v3.8b, v5.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x2]
+; CHECK-GI-NEXT: str s0, [x2]
; CHECK-GI-NEXT: ret
%x = load <4 x i8>, ptr %px
%y = load <4 x i8>, ptr %py
diff --git a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
index ef70137e6deee..9a982f0196755 100644
--- a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
@@ -143,8 +143,7 @@ define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]
; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]
; CHECK-GI-NEXT: uqsub v0.8b, v3.8b, v5.8b
-; CHECK-GI-NEXT: fmov w8, s0
-; CHECK-GI-NEXT: str w8, [x2]
+; CHECK-GI-NEXT: str s0, [x2]
; CHECK-GI-NEXT: ret
%x = load <4 x i8>, ptr %px
%y = load <4 x i8>, ptr %py
>From b26b528f1e29f08e4bce865b10c29a7a949f6325 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 14:41:12 +0000
Subject: [PATCH 02/30] Try to match multiple types in the match table. Start
with the given type, then try integers and finally fall back to scalars.
---
.../GlobalISel/GIMatchTableExecutorImpl.h | 48 ++++++++++++++-----
1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index 8f6586e79d78a..de605d833a460 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -285,24 +285,46 @@ bool GIMatchTableExecutor::executeMatchTable(
break;
}
const LLT Ty = MRI.getType(MO.getReg());
- const auto TyI = ExecInfo.TypeIDMap.find(Ty);
- if (TyI == ExecInfo.TypeIDMap.end()) {
- CurrentIdx = Default;
- break;
- }
- const int64_t TypeID = TyI->second;
- if (TypeID < LowerBound || UpperBound <= TypeID) {
- CurrentIdx = Default;
+
+ SmallVector<LLT> TypesToTry;
+ TypesToTry.push_back(Ty);
+
+ // Always try the integer patterns as we now consider that to be generic
+ // (to an extent)
+ if (LLT::getUseExtended() && !Ty.getScalarType().isInteger())
+ TypesToTry.push_back(
+ Ty.changeElementType(LLT::integer(Ty.getScalarSizeInBits())));
+
+ if (LLT::getUseExtended() && Ty.isAnyScalar() &&
+ Ty.getScalarSizeInBits() > 8)
+ TypesToTry.push_back(
+ Ty.changeElementType(LLT::floatIEEE(Ty.getScalarSizeInBits())));
+
+ const auto JumpTableBase = CurrentIdx;
+ bool Matched = false;
+ for (LLT Type : TypesToTry) {
+ const auto TyI = ExecInfo.TypeIDMap.find(Type);
+ if (TyI == ExecInfo.TypeIDMap.end())
+ continue;
+ const int64_t TypeID = TyI->second;
+ if (TypeID < LowerBound || UpperBound <= TypeID)
+ continue;
+ const auto NumEntry = (TypeID - LowerBound);
+ // Each entry is 4 bytes
+ CurrentIdx =
+ readBytesAs<uint32_t>(MatchTable + JumpTableBase + (NumEntry * 4));
+ if (!CurrentIdx) {
+ CurrentIdx = Default;
+ continue;
+ }
+ Matched = true;
break;
}
- const auto NumEntry = (TypeID - LowerBound);
- // Each entry is 4 bytes
- CurrentIdx =
- readBytesAs<uint32_t>(MatchTable + CurrentIdx + (NumEntry * 4));
- if (!CurrentIdx) {
+ if (!Matched) {
CurrentIdx = Default;
break;
}
+
OnFailResumeAt.push_back(Default);
break;
}
>From 5e03ad2e1fdfd06f75c14cea87bd0dbfdf23f3b4 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 14:40:32 +0000
Subject: [PATCH 03/30] Enabled extended types in AArch64 & no longer skip bf16
patterns with extended types enabled.
---
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 ++
llvm/lib/Target/AArch64/CMakeLists.txt | 2 +-
llvm/utils/TableGen/GlobalISelEmitter.cpp | 3 ++-
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index a2dbdf2cef1e7..4716935b96ad5 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -397,6 +397,8 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
setGlobalISelAbort(GlobalISelAbortMode::Disable);
}
+ LLT::setUseExtended(true);
+
// AArch64 supports the MachineOutliner.
setMachineOutliner(true);
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt
index 0c9a567278c56..80848845c2c24 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -9,7 +9,7 @@ tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
-tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel -gisel-extended-llt)
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="AArch64O0PreLegalizerCombiner")
tablegen(LLVM AArch64GenPreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 15b5ae24bd5d1..db5b1ebdb4219 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -2462,7 +2462,8 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
// Skip any patterns containing BF16 types, as GISel cannot currently tell
// the difference between fp16 and bf16. FIXME: This can be removed once
// BF16 is supported properly.
- if (hasBFloatType(Pat.getSrcPattern()))
+ bool UseExtended = LLT::getUseExtended();
+ if (hasBFloatType(Pat.getSrcPattern()) && !UseExtended)
continue;
auto MatcherOrErr = runOnPattern(Pat);
>From 31bf4cd10c177c4599146eef89fc0573e0d11ddf Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 31 Dec 2025 09:35:38 +0000
Subject: [PATCH 04/30] Add mutation to allow for converting bf16 to fp32
---
.../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index 8d27f85c04b87..98b1106ff337e 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -870,6 +870,39 @@ class LegalizeRuleSet {
return actionFor(LegalizeAction::NarrowScalar, Types, Mutation);
}
+ /// Promote bf16 operands/results to \p PromoteEltTy so the operation executes
+ /// in that wider type before truncating back to bf16.
+ LegalizeRuleSet &convertBF16(unsigned TypeIdx = 0,
+ LLT PromoteEltTy = LLT::float32()) {
+ assert(!PromoteEltTy.isVector() && PromoteEltTy.isScalar() &&
+ PromoteEltTy.isFloat() &&
+ "convertBF16 expects a floating-point scalar promotion type");
+ typeIdx(TypeIdx);
+ const LLT BF16Ty = LLT::bfloat16();
+ return widenScalarIf(
+ [=](const LegalityQuery &Query) {
+ if (TypeIdx >= Query.Types.size())
+ return false;
+ const LLT Ty = Query.Types[TypeIdx];
+ if (!Ty.isValid())
+ return false;
+ if (Ty == BF16Ty)
+ return true;
+ if (Ty.isVector() && Ty.getElementType() == BF16Ty)
+ return true;
+ return false;
+ },
+ LegalizeMutations::changeElementTo(TypeIdx, PromoteEltTy));
+ }
+
+ /// Conditionally promote bf16 operands/results to \p PromoteEltTy.
+ LegalizeRuleSet &convertBF16(bool Enable, unsigned TypeIdx = 0,
+ LLT PromoteEltTy = LLT::float32()) {
+ if (!Enable)
+ return *this;
+ return convertBF16(TypeIdx, PromoteEltTy);
+ }
+
/// Add more elements to reach the type selected by the mutation if the
/// predicate is true.
LegalizeRuleSet &moreElementsIf(LegalityPredicate Predicate,
>From 325efe0b93485015b279790da520cbedf34627e6 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 2 Feb 2026 11:20:05 +0000
Subject: [PATCH 05/30] Modify construction of types to reduce the instances of
scalar types in AArch64.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 8 +-
.../AArch64/GISel/AArch64CallLowering.cpp | 10 +--
.../GISel/AArch64InstructionSelector.cpp | 5 +-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 86 ++++++++++---------
.../GISel/AArch64PostLegalizerCombiner.cpp | 5 +-
.../GISel/AArch64PostLegalizerLowering.cpp | 10 ++-
.../GISel/AArch64PreLegalizerCombiner.cpp | 26 +++---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 4 +-
8 files changed, 85 insertions(+), 69 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 9b34d9b385b4e..923bea3379913 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18966,14 +18966,14 @@ LLT AArch64TargetLowering::getOptimalMemOpLLT(
// NEON dup + scalar store works for any alignment and is efficient.
if (CanUseNEON && Op.isMemset() && !IsSmallZeroMemset &&
AlignmentIsAcceptable(MVT::v16i8, Align(1)))
- return LLT::fixed_vector(2, 64);
+ return LLT::fixed_vector(2, LLT::integer(64));
if (CanUseFP && !IsSmallZeroMemset &&
AlignmentIsAcceptable(MVT::f128, Align(16)))
- return LLT::scalar(128);
+ return LLT::floatIEEE(128);
if (Op.size() >= 8 && AlignmentIsAcceptable(MVT::i64, Align(8)))
- return LLT::scalar(64);
+ return LLT::integer(64);
if (Op.size() >= 4 && AlignmentIsAcceptable(MVT::i32, Align(4)))
- return LLT::scalar(32);
+ return LLT::integer(32);
return LLT();
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index d0bb509a097cb..f4229235e9743 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -259,7 +259,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
ISD::ArgFlagsTy Flags) override {
MachineFunction &MF = MIRBuilder.getMF();
LLT p0 = LLT::pointer(0, 64);
- LLT s64 = LLT::scalar(64);
+ LLT s64 = LLT::integer(64);
if (IsTailCall) {
assert(!Flags.isByVal() && "byval unhandled with tail calls");
@@ -446,7 +446,7 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
auto &Flags = CurArgInfo.Flags[0];
if (MRI.getType(CurVReg).getSizeInBits() == TypeSize::getFixed(1) &&
!Flags.isSExt() && !Flags.isZExt()) {
- CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
+ CurVReg = MIRBuilder.buildZExt(LLT::integer(8), CurVReg).getReg(0);
} else if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) ==
1) {
// Some types will need extending as specified by the CC.
@@ -629,7 +629,7 @@ void AArch64CallLowering::saveVarArgRegisters(
bool IsWin64CC = Subtarget.isCallingConvWin64(CCInfo.getCallingConv(),
MF.getFunction().isVarArg());
const LLT p0 = LLT::pointer(0, 64);
- const LLT s64 = LLT::scalar(64);
+ const LLT s64 = LLT::integer(64);
unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
unsigned NumVariadicGPRArgRegs = GPRArgRegs.size() - FirstVariadicGPR + 1;
@@ -753,7 +753,7 @@ bool AArch64CallLowering::lowerFormalArguments(
if (!Flags.isZExt() && !Flags.isSExt()) {
// Lower i1 argument as i8, and insert AssertZExt + Trunc later.
Register OrigReg = OrigArg.Regs[0];
- Register WideReg = MRI.createGenericVirtualRegister(LLT::scalar(8));
+ Register WideReg = MRI.createGenericVirtualRegister(LLT::integer(8));
OrigArg.Regs[0] = WideReg;
BoolArgs.push_back({OrigReg, WideReg});
}
@@ -1359,7 +1359,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// We cannot use a ZExt ArgInfo flag here, because it will
// zero-extend the argument to i32 instead of just i8.
OutArg.Regs[0] =
- MIRBuilder.buildZExt(LLT::scalar(8), OutArg.Regs[0]).getReg(0);
+ MIRBuilder.buildZExt(LLT::integer(8), OutArg.Regs[0]).getReg(0);
LLVMContext &Ctx = MF.getFunction().getContext();
OutArg.Ty = Type::getInt8Ty(Ctx);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 2fa0fca176c88..1bf58a11411e5 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2248,8 +2248,9 @@ bool AArch64InstructionSelector::convertPtrAddToAdd(
if (PtrTy.getAddressSpace() != 0)
return false;
- const LLT CastPtrTy =
- PtrTy.isVector() ? LLT::fixed_vector(2, 64) : LLT::scalar(64);
+ const LLT CastPtrTy = PtrTy.isVector()
+ ? LLT::fixed_vector(2, LLT::integer(64))
+ : LLT::integer(64);
auto PtrToInt = MIB.buildPtrToInt(CastPtrTy, AddOp1Reg);
// Set regbanks on the registers.
if (PtrTy.isVector())
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 5b07480677e47..a9605038d9ef6 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1827,20 +1827,22 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(2).getReg();
LLT DstTy = MRI.getType(DstReg);
+ LLT DstTyScalar = DstTy.getScalarType();
LLT MidTy, ExtTy;
if (DstTy.isScalar() && DstTy.getScalarSizeInBits() <= 32) {
- MidTy = LLT::fixed_vector(4, 32);
- ExtTy = LLT::scalar(32);
+ ExtTy = DstTyScalar.changeElementSize(32);
+ MidTy = LLT::fixed_vector(4, ExtTy);
} else {
- MidTy = LLT::fixed_vector(2, 64);
- ExtTy = LLT::scalar(64);
+ ExtTy = DstTy.changeElementSize(64);
+ MidTy = LLT::fixed_vector(2, ExtTy);
}
Register MidReg =
MIB.buildInstr(Opc, {MidTy}, {SrcReg})->getOperand(0).getReg();
- Register ZeroReg =
- MIB.buildConstant(LLT::scalar(64), 0)->getOperand(0).getReg();
+ Register ZeroReg = MIB.buildConstant(DstTyScalar.changeElementSize(64), 0)
+ ->getOperand(0)
+ .getReg();
Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy},
{MidReg, ZeroReg})
.getReg(0);
@@ -2049,6 +2051,7 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr(
// If the shift amount is a G_CONSTANT, promote it to a 64 bit type so the
// imported patterns can select it later. Either way, it will be legal.
Register AmtReg = MI.getOperand(2).getReg();
+ LLT AmtRegEltTy = MRI.getType(AmtReg).getScalarType();
auto VRegAndVal = getIConstantVRegValWithLookThrough(AmtReg, MRI);
if (!VRegAndVal)
return true;
@@ -2056,7 +2059,8 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr(
int64_t Amount = VRegAndVal->Value.getSExtValue();
if (Amount > 31)
return true; // This will have to remain a register variant.
- auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount);
+ auto ExtCst =
+ MIRBuilder.buildConstant(AmtRegEltTy.changeElementSize(64), Amount);
Observer.changingInstr(MI);
MI.getOperand(2).setReg(ExtCst.getReg(0));
Observer.changedInstr(MI);
@@ -2260,7 +2264,7 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
"Expected src and dst to have the same type!");
if (ST->hasCSSC() && Ty.isScalar() && Size == 128) {
- LLT s64 = LLT::scalar(64);
+ LLT s64 = Ty.changeElementSize(64);
auto Split = MIRBuilder.buildUnmerge(s64, Val);
auto CTPOP1 = MIRBuilder.buildCTPOP(s64, Split->getOperand(0));
@@ -2283,11 +2287,13 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
// Pre-conditioning: widen Val up to the nearest vector type.
// s32,s64,v4s16,v2s32 -> v8i8
// v8s16,v4s32,v2s64 -> v16i8
- LLT VTy = Size == 128 ? LLT::fixed_vector(16, 8) : LLT::fixed_vector(8, 8);
+ LLT ScalarTy = Ty.getScalarType();
+ LLT VTy = Size == 128 ? LLT::fixed_vector(16, ScalarTy.changeElementSize(8))
+ : LLT::fixed_vector(8, ScalarTy.changeElementSize(8));
if (Ty.isScalar()) {
assert((Size == 32 || Size == 64 || Size == 128) && "Expected only 32, 64, or 128 bit scalars!");
if (Size == 32) {
- Val = MIRBuilder.buildZExt(LLT::scalar(64), Val).getReg(0);
+ Val = MIRBuilder.buildZExt(ScalarTy.changeElementSize(64), Val).getReg(0);
}
}
Val = MIRBuilder.buildBitcast(VTy, Val).getReg(0);
@@ -2296,15 +2302,16 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
auto CTPOP = MIRBuilder.buildCTPOP(VTy, Val);
// Sum across lanes.
-
if (ST->hasDotProd() && Ty.isVector() && Ty.getNumElements() >= 2 &&
Ty.getScalarSizeInBits() != 16) {
- LLT Dt = Ty == LLT::fixed_vector(2, 64) ? LLT::fixed_vector(4, 32) : Ty;
+ LLT Dt = Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(64))
+ ? LLT::fixed_vector(4, ScalarTy.changeElementSize(32))
+ : Ty;
auto Zeros = MIRBuilder.buildConstant(Dt, 0);
auto Ones = MIRBuilder.buildConstant(VTy, 1);
MachineInstrBuilder Sum;
- if (Ty == LLT::fixed_vector(2, 64)) {
+ if (Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(64))) {
auto UDOT =
MIRBuilder.buildInstr(AArch64::G_UDOT, {Dt}, {Zeros, Ones, CTPOP});
Sum = MIRBuilder.buildInstr(AArch64::G_UADDLP, {Ty}, {UDOT});
@@ -2326,26 +2333,26 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
SmallVector<LLT> HAddTys;
if (Ty.isScalar()) {
Opc = Intrinsic::aarch64_neon_uaddlv;
- HAddTys.push_back(LLT::scalar(32));
- } else if (Ty == LLT::fixed_vector(8, 16)) {
+ HAddTys.push_back(ScalarTy.changeElementSize(32));
+ } else if (Ty == LLT::fixed_vector(8, ScalarTy.changeElementSize(16))) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(8, 16));
- } else if (Ty == LLT::fixed_vector(4, 32)) {
+ HAddTys.push_back(LLT::fixed_vector(8, ScalarTy.changeElementSize(16)));
+ } else if (Ty == LLT::fixed_vector(4, ScalarTy.changeElementSize(32))) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(8, 16));
- HAddTys.push_back(LLT::fixed_vector(4, 32));
- } else if (Ty == LLT::fixed_vector(2, 64)) {
+ HAddTys.push_back(LLT::fixed_vector(8, ScalarTy.changeElementSize(16)));
+ HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(32)));
+ } else if (Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(64))) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(8, 16));
- HAddTys.push_back(LLT::fixed_vector(4, 32));
- HAddTys.push_back(LLT::fixed_vector(2, 64));
- } else if (Ty == LLT::fixed_vector(4, 16)) {
+ HAddTys.push_back(LLT::fixed_vector(8, ScalarTy.changeElementSize(16)));
+ HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(32)));
+ HAddTys.push_back(LLT::fixed_vector(2, ScalarTy.changeElementSize(64)));
+ } else if (Ty == LLT::fixed_vector(4, ScalarTy.changeElementSize(16))) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(4, 16));
- } else if (Ty == LLT::fixed_vector(2, 32)) {
+ HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(16)));
+ } else if (Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(32))) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(4, 16));
- HAddTys.push_back(LLT::fixed_vector(2, 32));
+ HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(16)));
+ HAddTys.push_back(LLT::fixed_vector(2, ScalarTy.changeElementSize(32)));
} else
llvm_unreachable("unexpected vector shape");
MachineInstrBuilder UADD;
@@ -2366,12 +2373,12 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
bool AArch64LegalizerInfo::legalizeAtomicCmpxchg128(
MachineInstr &MI, MachineRegisterInfo &MRI, LegalizerHelper &Helper) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
- LLT s64 = LLT::scalar(64);
+ LLT i64 = LLT::integer(64);
auto Addr = MI.getOperand(1).getReg();
- auto DesiredI = MIRBuilder.buildUnmerge({s64, s64}, MI.getOperand(2));
- auto NewI = MIRBuilder.buildUnmerge({s64, s64}, MI.getOperand(3));
- auto DstLo = MRI.createGenericVirtualRegister(s64);
- auto DstHi = MRI.createGenericVirtualRegister(s64);
+ auto DesiredI = MIRBuilder.buildUnmerge({i64, i64}, MI.getOperand(2));
+ auto NewI = MIRBuilder.buildUnmerge({i64, i64}, MI.getOperand(3));
+ auto DstLo = MRI.createGenericVirtualRegister(i64);
+ auto DstHi = MRI.createGenericVirtualRegister(i64);
MachineInstrBuilder CAS;
if (ST->hasLSE()) {
@@ -2574,14 +2581,11 @@ bool AArch64LegalizerInfo::legalizeFptrunc(MachineInstr &MI,
assert(SrcTy.isFixedVector() && isPowerOf2_32(SrcTy.getNumElements()) &&
"Expected a power of 2 elements");
- LLT s16 = LLT::scalar(16);
- LLT s32 = LLT::scalar(32);
- LLT s64 = LLT::scalar(64);
- LLT v2s16 = LLT::fixed_vector(2, s16);
- LLT v4s16 = LLT::fixed_vector(4, s16);
- LLT v2s32 = LLT::fixed_vector(2, s32);
- LLT v4s32 = LLT::fixed_vector(4, s32);
- LLT v2s64 = LLT::fixed_vector(2, s64);
+ LLT v2s16 = DstTy.changeElementCount(2);
+ LLT v4s16 = DstTy.changeElementCount(4);
+ LLT v2s32 = SrcTy.changeElementCount(2).changeElementSize(32);
+ LLT v4s32 = SrcTy.changeElementCount(4).changeElementSize(32);
+ LLT v2s64 = SrcTy.changeElementCount(2);
SmallVector<Register> RegsToUnmergeTo;
SmallVector<Register> TruncOddDstRegs;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index 59349db88289b..ba0d9b542d1e9 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -222,7 +222,7 @@ bool matchAArch64MulConstCombine(
return false;
ApplyFn = [=](MachineIRBuilder &B, Register DstReg) {
- auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt);
+ auto Shift = B.buildConstant(LLT::integer(64), ShiftAmt);
auto ShiftedVal = B.buildShl(Ty, LHS, Shift);
Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS;
@@ -237,7 +237,8 @@ bool matchAArch64MulConstCombine(
}
// Shift the result.
if (TrailingZeroes) {
- B.buildShl(DstReg, Res, B.buildConstant(LLT::scalar(64), TrailingZeroes));
+ B.buildShl(DstReg, Res,
+ B.buildConstant(LLT::integer(64), TrailingZeroes));
return;
}
B.buildCopy(DstReg, Res.getReg(0));
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 2b34a89a1db64..64d9fd89c9218 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -556,9 +556,9 @@ void applyINS(MachineInstr &MI, MachineRegisterInfo &MRI,
Register DstVec, SrcVec;
int DstLane, SrcLane;
std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo;
- auto SrcCst = Builder.buildConstant(LLT::scalar(64), SrcLane);
+ auto SrcCst = Builder.buildConstant(LLT::integer(64), SrcLane);
auto Extract = Builder.buildExtractVectorElement(ScalarTy, SrcVec, SrcCst);
- auto DstCst = Builder.buildConstant(LLT::scalar(64), DstLane);
+ auto DstCst = Builder.buildConstant(LLT::integer(64), DstLane);
Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst);
MI.eraseFromParent();
}
@@ -971,7 +971,9 @@ void applySwapICmpOperands(MachineInstr &MI, GISelChangeObserver &Observer) {
std::function<Register(MachineIRBuilder &)>
getVectorFCMP(AArch64CC::CondCode CC, Register LHS, Register RHS, bool NoNans,
MachineRegisterInfo &MRI) {
- LLT DstTy = MRI.getType(LHS);
+ LLT OldTy = MRI.getType(LHS);
+ LLT DstTy =
+ LLT::fixed_vector(OldTy.getNumElements(), OldTy.getScalarSizeInBits());
assert(DstTy.isVector() && "Expected vector types only?");
assert(DstTy == MRI.getType(RHS) && "Src and Dst types must match!");
switch (CC) {
@@ -1102,7 +1104,7 @@ void applyLowerBuildToInsertVecElt(MachineInstr &MI, MachineRegisterInfo &MRI,
Register SrcReg = GBuildVec->getSourceReg(I);
if (mi_match(SrcReg, MRI, m_GImplicitDef()))
continue;
- auto IdxReg = B.buildConstant(LLT::scalar(64), I);
+ auto IdxReg = B.buildConstant(LLT::integer(64), I);
DstReg =
B.buildInsertVectorElement(DstTy, DstReg, SrcReg, IdxReg).getReg(0);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 42e0ab6537a84..abfac82ce5a86 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -478,11 +478,14 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
LLT LeftoverTy;
SmallVector<Register, 4> LeftoverRegs;
if (SrcScalSize == 8)
- MainTy = LLT::fixed_vector(16, 8);
+ MainTy =
+ LLT::fixed_vector(16, SrcTy.getScalarType().changeElementSize(8));
else if (SrcScalSize == 16)
- MainTy = LLT::fixed_vector(8, 16);
+ MainTy =
+ LLT::fixed_vector(8, SrcTy.getScalarType().changeElementSize(16));
else if (SrcScalSize == 32)
- MainTy = LLT::fixed_vector(4, 32);
+ MainTy =
+ LLT::fixed_vector(4, SrcTy.getScalarType().changeElementSize(32));
else
llvm_unreachable("Source's Scalar Size not supported");
@@ -497,8 +500,9 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
}
unsigned MidScalarSize = MainTy.getScalarSizeInBits() * 2;
- LLT MidScalarLLT = LLT::scalar(MidScalarSize);
- Register ZeroReg = B.buildConstant(LLT::scalar(64), 0).getReg(0);
+ LLT MidScalarLLT =
+ MainTy.changeElementSize(MidScalarSize).changeElementCount(1);
+ Register ZeroReg = B.buildConstant(LLT::integer(64), 0).getReg(0);
for (unsigned I = 0; I < WorkingRegisters.size(); I++) {
// If the number of elements is too small to build an instruction, extend
// its size before applying addlv
@@ -514,8 +518,9 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
// Generate the {U/S}ADDLV instruction, whose output is always double of the
// Src's Scalar size
- LLT AddlvTy = MidScalarSize <= 32 ? LLT::fixed_vector(4, 32)
- : LLT::fixed_vector(2, 64);
+ LLT AddlvTy = MidScalarSize <= 32
+ ? MainTy.changeElementSize(32).changeElementCount(4)
+ : MainTy.changeElementSize(64).changeElementCount(2);
Register AddlvReg =
B.buildInstr(Opc, {AddlvTy}, {WorkingRegisters[I]}).getReg(0);
@@ -529,9 +534,10 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
{MidScalarLLT}, {AddlvReg, ZeroReg})
.getReg(0);
} else {
- Register ExtractReg = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT,
- {LLT::scalar(32)}, {AddlvReg, ZeroReg})
- .getReg(0);
+ Register ExtractReg =
+ B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT,
+ {DstTy.changeElementSize(32)}, {AddlvReg, ZeroReg})
+ .getReg(0);
WorkingRegisters[I] =
B.buildTrunc({MidScalarLLT}, {ExtractReg}).getReg(0);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index fba8323e62ff8..b2958fd63415a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -518,7 +518,9 @@ void AArch64RegisterBankInfo::applyMappingImpl(
// Extend smaller gpr operands to 32 bit.
Builder.setInsertPt(*MI.getParent(), MI.getIterator());
- auto Ext = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(2).getReg());
+ LLT OperandType = MRI.getType(MI.getOperand(2).getReg());
+ auto Ext = Builder.buildAnyExt(OperandType.changeElementSize(32),
+ MI.getOperand(2).getReg());
MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID));
MI.getOperand(2).setReg(Ext.getReg(0));
return applyDefaultMapping(OpdMapper);
>From aa0339dfe638680341f46088f66d99ef539ae70d Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 2 Feb 2026 11:23:32 +0000
Subject: [PATCH 06/30] Allow AArch64RegisterBankInfo to see through bitcasts &
insert a copy when lowering ITOFP.
---
.../AArch64/GISel/AArch64InstructionSelector.cpp | 9 +++++++++
.../Target/AArch64/GISel/AArch64RegisterBankInfo.cpp | 10 +++++++---
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 1bf58a11411e5..dbaa056bb7b58 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2218,6 +2218,15 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
return false;
if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::FPRRegBankID) {
+ // Need to add a copy to change the type so that the existing patterns can
+ // match when there is an integer on an FPR bank.
+ if (SrcTy.getScalarType().isInteger()) {
+ auto Copy = MIB.buildCopy(DstTy, SrcReg);
+ I.getOperand(1).setReg(Copy.getReg(0));
+ MRI.setRegClass(Copy.getReg(0),
+ getRegClassForTypeOnBank(
+ SrcTy, RBI.getRegBank(AArch64::FPRRegBankID)));
+ }
if (I.getOpcode() == TargetOpcode::G_SITOFP)
I.setDesc(TII.get(AArch64::G_SITOF));
else
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index b2958fd63415a..3da5b3486e62d 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -947,8 +947,12 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
TypeSize Size = DstTy.getSizeInBits();
- bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64;
- bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64;
+ bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64 &&
+ DstTy.getScalarType().isInteger() &&
+ !(SrcTy.getSizeInBits() <= 16);
+ bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64 &&
+ SrcTy.getScalarType().isInteger() &&
+ !(SrcTy.getSizeInBits() <= 16);
const RegisterBank &DstRB =
DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
const RegisterBank &SrcRB =
@@ -1293,7 +1297,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)
OpRegBankIdx[2] = PMI_FirstFPR;
else {
- // If the type is i8/i16, and the regank will be GPR, then we change the
+ // If the type is i8/i16, and the regbank will be GPR, then we change the
// type to i32 in applyMappingImpl.
LLT Ty = MRI.getType(MI.getOperand(2).getReg());
if (Ty.getSizeInBits() == 8 || Ty.getSizeInBits() == 16) {
>From e2af6de222bb4deb61b60c3231134a2b717efcff Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 16:01:16 +0000
Subject: [PATCH 07/30] Make floating point types legal, bf16 legal & convert
from bf16 when necessary.
---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 73 ++++++++++++++-----
1 file changed, 56 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index a9605038d9ef6..ccac85e854636 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -65,6 +65,23 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
const LLT nxv4s32 = LLT::scalable_vector(4, s32);
const LLT nxv2s64 = LLT::scalable_vector(2, s64);
+ const LLT bf16 = LLT::bfloat16();
+ const LLT v4bf16 = LLT::fixed_vector(4, bf16);
+ const LLT v8bf16 = LLT::fixed_vector(8, bf16);
+
+ const LLT fp16 = LLT::float16();
+ const LLT v4fp16 = LLT::fixed_vector(4, fp16);
+ const LLT v8fp16 = LLT::fixed_vector(8, fp16);
+
+ const LLT fp32 = LLT::float32();
+ const LLT v2fp32 = LLT::fixed_vector(2, fp32);
+ const LLT v4fp32 = LLT::fixed_vector(4, fp32);
+
+ const LLT fp64 = LLT::float64();
+ const LLT v2fp64 = LLT::fixed_vector(2, fp64);
+
+ const LLT fp128 = LLT::float128();
+
std::initializer_list<LLT> PackedVectorAllTypeList = {/* Begin 128bit types */
v16s8, v8s16, v4s32,
v2s64, v2p0,
@@ -86,7 +103,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// Some instructions only support s16 if the subtarget has full 16-bit FP
// support.
const bool HasFP16 = ST.hasFullFP16();
- const LLT &MinFPScalar = HasFP16 ? s16 : s32;
+ const LLT &MinFPScalar = HasFP16 ? fp16 : fp32;
+
+ const bool HasBF16 = ST.hasBF16();
const bool HasCSSC = ST.hasCSSC();
const bool HasRCPC3 = ST.hasRCPC3();
@@ -97,6 +116,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalFor({p0, s8, s16, s32, s64})
.legalFor({v2s8, v4s8, v8s8, v16s8, v2s16, v4s16, v8s16, v2s32, v4s32,
v2s64, v2p0})
+ .legalFor(HasBF16, {bf16})
+ .legalFor(HasBF16, {v4bf16})
.widenScalarToNextPow2(0)
.clampScalar(0, s8, s64)
.moreElementsToNextPow2(0)
@@ -408,9 +429,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FSQRT, G_FMAXNUM, G_FMINNUM,
G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR, G_FRINT, G_FNEARBYINT,
G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN})
- .legalFor({s32, s64, v2s32, v4s32, v2s64})
- .legalFor(HasFP16, {s16, v4s16, v8s16})
- .libcallFor({s128})
+ .legalFor({fp32, fp64, v2fp32, v4fp32, v2fp64})
+ .convertBF16(HasBF16)
+ .legalFor(HasFP16, {fp16, s16, v4s16, v8s16})
+ .libcallFor({fp128})
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.minScalarOrElt(0, MinFPScalar)
.clampNumElements(0, v4s16, v8s16)
@@ -419,19 +441,20 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.moreElementsToNextPow2(0);
getActionDefinitionsBuilder({G_FABS, G_FNEG})
- .legalFor({s32, s64, v2s32, v4s32, v2s64})
- .legalFor(HasFP16, {s16, v4s16, v8s16})
+ .legalFor({fp32, fp64, v2fp32, v4fp32, v2fp64})
+ .legalFor(HasFP16, {fp16, v4fp16, v8fp16})
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.lowerIf(scalarOrEltWiderThan(0, 64))
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.moreElementsToNextPow2(0)
- .lowerFor({s16, v4s16, v8s16});
+ .lowerFor({fp16, v4fp16, v8fp16});
getActionDefinitionsBuilder(G_FREM)
- .libcallFor({s32, s64, s128})
- .minScalar(0, s32)
+ .libcallFor({fp32, fp64, fp128})
+ .convertBF16(HasBF16)
+ .minScalar(0, fp32)
.scalarize(0);
getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FPOW, G_FLOG, G_FLOG2,
@@ -440,12 +463,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
G_FSINH, G_FTANH, G_FMODF})
// We need a call for these, so we always need to scalarize.
.scalarize(0)
+ .convertBF16(HasBF16)
// Regardless of FP16 support, widen 16-bit elements to 32-bits.
- .minScalar(0, s32)
- .libcallFor({s32, s64, s128});
+ .minScalar(0, fp32)
+ .libcallFor({fp32, fp64, fp128});
getActionDefinitionsBuilder({G_FPOWI, G_FLDEXP})
.scalarize(0)
- .minScalar(0, s32)
+ .convertBF16(HasBF16)
+ .minScalar(0, fp32)
.libcallFor({{s32, s32}, {s64, s32}, {s128, s32}});
getActionDefinitionsBuilder({G_LROUND, G_INTRINSIC_LRINT})
@@ -691,7 +716,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampScalar(0, s8, s64);
getActionDefinitionsBuilder(G_FCONSTANT)
// Always legalize s16 to prevent G_FCONSTANT being widened to G_CONSTANT
- .legalFor({s16, s32, s64, s128})
+ .legalFor({s16, s32, s64, s128, bf16, fp16, fp32, fp64, fp128})
.clampScalar(0, MinFPScalar, s128);
// FIXME: fix moreElementsToNextPow2
@@ -733,6 +758,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{v2s64, v2s64}})
.legalFor(HasFP16, {{s32, s16}, {v4s16, v4s16}, {v8s16, v8s16}})
.widenScalarOrEltToNextPow2(1)
+ .convertBF16(HasBF16, 1)
.clampScalar(0, s32, s32)
.minScalarOrElt(1, MinFPScalar)
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
@@ -829,6 +855,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_FPTRUNC)
.legalFor(
{{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
+ .legalFor(HasBF16, {{bf16, fp32}, {bf16, fp64}, {v4bf16, v4fp32}})
.libcallFor({{s16, s128}, {s32, s128}, {s64, s128}})
.moreElementsToNextPow2(1)
.customIf([](const LegalityQuery &Q) {
@@ -844,8 +871,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.scalarize(0);
getActionDefinitionsBuilder(G_FPEXT)
- .legalFor(
- {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
+ .legalFor({{fp32, fp16},
+ {fp64, fp16},
+ {fp64, fp32},
+ {v4fp32, v4fp16},
+ {v2fp64, v2fp32}})
+ .legalFor(HasBF16, {{fp32, bf16}, {v4fp32, v4bf16}})
.libcallFor({{s128, s64}, {s128, s32}, {s128, s16}})
.moreElementsToNextPow2(0)
.widenScalarIf(
@@ -856,9 +887,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
SrcTy.getScalarSizeInBits() == 16 &&
DstTy.getScalarSizeInBits() == 64;
},
- changeElementTo(1, s32))
+ changeElementTo(1, fp32))
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
+ // bf16 -> fp32
+ .convertBF16(HasBF16, 1)
.scalarize(0);
// Conversions
@@ -958,13 +991,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{v2s32, v2s32},
{v4s32, v4s32},
{v2s64, v2s64}})
+ .convertBF16(HasBF16)
.legalFor(HasFP16,
{{s16, s32}, {s16, s64}, {v4s16, v4s16}, {v8s16, v8s16}})
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.moreElementsToNextPow2(1)
.widenScalarOrEltToNextPow2OrMinSize(1)
- .minScalar(1, s32)
+ .minScalar(1, fp32)
.lowerIf([](const LegalityQuery &Query) {
return Query.Types[1].isVector() &&
Query.Types[1].getScalarSizeInBits() == 64 &&
@@ -1045,6 +1079,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// Casts for 32 and 64-bit width type are just copies.
// Same for 128-bit width type, except they are on the FPR bank.
getActionDefinitionsBuilder(G_BITCAST)
+ .legalForCartesianProduct({s16})
// Keeping 32-bit instructions legal to prevent regression in some tests
.legalForCartesianProduct({s32, v2s16, v4s8})
.legalForCartesianProduct({s64, v8s8, v4s16, v2s32})
@@ -1141,6 +1176,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{s16, nxv8s16, s64},
{s32, nxv4s32, s64},
{s64, nxv2s64, s64}})
+ .legalFor(HasBF16, {{bf16, v8bf16, s64}, {bf16, v4bf16, s64}})
.unsupportedIf([=](const LegalityQuery &Query) {
const LLT &EltTy = Query.Types[1].getElementType();
if (Query.Types[1].isScalableVector())
@@ -1192,6 +1228,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
.legalIf(
typeInSet(0, {v8s8, v16s8, v4s16, v8s16, v2s32, v4s32, v2s64, v2p0}))
+ .legalFor(HasBF16, {{v4bf16}, {v8bf16}})
.legalFor(HasSVE, {{nxv16s8, s32, s64},
{nxv8s16, s32, s64},
{nxv4s32, s32, s64},
@@ -1214,6 +1251,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{v4s32, s32},
{v2s64, s64},
{v2p0, p0}})
+ .legalFor(HasBF16, {{v4bf16, bf16}, {v8bf16, bf16}})
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.minScalarOrElt(0, s8)
@@ -1261,6 +1299,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_CONCAT_VECTORS)
.legalFor({{v16s8, v8s8}, {v8s16, v4s16}, {v4s32, v2s32}})
+ .legalFor(HasBF16, {{v8bf16, v4bf16}})
.bitcastIf(
[=](const LegalityQuery &Query) {
return Query.Types[0].isFixedVector() &&
>From 27f614d4ebe7d23e8b8a740edc6ebb684454b192 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 16:02:29 +0000
Subject: [PATCH 08/30] Add slightly modified patterns to allow selection of
instructions that used to select but no longer do
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 4 +
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 10 +++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 90 +++++++++++++++++--
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 10 +++
4 files changed, 108 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 406ac2fa62df2..c2e1e883a0039 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -174,6 +174,10 @@ def extract_high_v4f32 :
def extract_high_v2f64 :
ComplexPattern<v1f64, 1, "SelectExtractHigh", [extract_subvector, bitconvert]>;
+def gi_extract_high_v8bf16 :
+ GIComplexOperandMatcher<v4s16, "selectExtractHigh">,
+ GIComplexPatternEquiv<extract_high_v8bf16>;
+
def gi_extract_high_v8f16 :
GIComplexOperandMatcher<v4s16, "selectExtractHigh">,
GIComplexPatternEquiv<extract_high_v8f16>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index db0d7d8c76f14..63d9a37514fa6 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -551,10 +551,18 @@ let AddedComplexity = 19 in {
defm : VecStoreLane64_0Pat<am_indexed16, store, v4i16, i16, hsub, uimm12s2, STRHui>;
defm : VecStoreLane64_0Pat<am_indexed32, store, v2i32, i32, ssub, uimm12s4, STRSui>;
+ defm : VecStoreLane64_0Pat<am_indexed16, store, v4f16, f16, hsub, uimm12s2, STRHui>;
+ defm : VecStoreLane64_0Pat<am_indexed32, store, v2f32, f32, ssub, uimm12s4, STRSui>;
+
defm : VecStoreULane64_0Pat<store, v4i16, i16, hsub, STURHi>;
defm : VecStoreULane64_0Pat<store, v2i32, i32, ssub, STURSi>;
defm : VecROStoreLane64_0Pat<ro16, store, v4i16, i16, hsub, STRHroW, STRHroX>;
defm : VecROStoreLane64_0Pat<ro32, store, v2i32, i32, ssub, STRSroW, STRSroX>;
+
+ defm : VecStoreULane64_0Pat<store, v4f16, f16, hsub, STURHi>;
+ defm : VecStoreULane64_0Pat<store, v2f32, f32, ssub, STURSi>;
+ defm : VecROStoreLane64_0Pat<ro16, store, v4f16, f16, hsub, STRHroW, STRHroX>;
+ defm : VecROStoreLane64_0Pat<ro32, store, v2f32, f32, ssub, STRSroW, STRSroX>;
}
def : Pat<(v8i8 (AArch64dup (i8 (load GPR64sp:$Rn)))),
@@ -573,3 +581,5 @@ def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
(LD1Rv2d GPR64sp:$Rn)>;
def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
(LD1Rv1d GPR64sp:$Rn)>;
+
+def : Pat<(f64 (bitconvert (i64 0))), (FMOVD0)>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index ab304744087f9..098b86b195988 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4433,6 +4433,9 @@ defm : LoadInsertPatterns<extloadi16, v8i16, v4i16, nxv8i16, i32,
vec_ins_or_scal_vec, vec_ins_or_scal_vec,
LDRHui, LDURHi, LDRHroW, LDRHroX,
ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
+defm : LoadInsertPatterns<load, v8i16, v4i16, nxv8i16, i16,
+ LDRHui, LDURHi, LDRHroW, LDRHroX,
+ ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
defm : LoadInsertPatterns<load, v4i32, v2i32, nxv4i32, i32,
vec_ins_or_scal_vec_v4f32, vec_ins_or_scal_vec_v2f32,
LDRSui, LDURSi, LDRSroW, LDRSroX,
@@ -4715,6 +4718,15 @@ let Predicates = [UseSTRQro], AddedComplexity = 10 in {
(ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
ro_Xextend128:$extend)),
(STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>;
+
+ def : Pat<(store (v2i64 FPR128:$Rt),
+ (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
+ ro_Wextend128:$extend)),
+ (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>;
+ def : Pat<(store (v2i64 FPR128:$Rt),
+ (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
+ ro_Xextend128:$extend)),
+ (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>;
}
multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
@@ -4798,6 +4810,7 @@ multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
let AddedComplexity = 19 in {
defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, f16, hsub, STRHroW, STRHroX>;
+ defm : VecROStoreLane0Pat<ro16, store, v8i16, i16, f16, hsub, STRHroW, STRHroX>;
defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, f16, hsub, STRHroW, STRHroX>;
defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, i32, ssub, STRSroW, STRSroX>;
defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, i32, ssub, STRSroW, STRSroX>;
@@ -4954,6 +4967,7 @@ multiclass VecStoreLane0Pat<ComplexPattern UIAddrMode, SDPatternOperator storeop
let AddedComplexity = 19 in {
defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, f16, hsub, uimm12s2, STRHui>;
+ defm : VecStoreLane0Pat<am_indexed16, store, v8i16, i16, f16, hsub, uimm12s2, STRHui>;
defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, f16, hsub, uimm12s2, STRHui>;
defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, i32, ssub, uimm12s4, STRSui>;
defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, i32, ssub, uimm12s4, STRSui>;
@@ -5107,6 +5121,7 @@ multiclass VecStoreULane0Pat<SDPatternOperator StoreOp,
let AddedComplexity = 19 in {
defm : VecStoreULane0Pat<truncstorei16, v8i16, i32, f16, hsub, STURHi>;
+ defm : VecStoreULane0Pat<store, v8i16, i16, f16, hsub, STURHi>;
defm : VecStoreULane0Pat<store, v8f16, f16, f16, hsub, STURHi>;
defm : VecStoreULane0Pat<store, v4i32, i32, i32, ssub, STURSi>;
defm : VecStoreULane0Pat<store, v4f32, f32, i32, ssub, STURSi>;
@@ -7833,6 +7848,31 @@ def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
+def : Pat<(v4i32 (AArch64dup (i32 FPR32:$src))),
+ (v4i32 (DUPv4i32lane
+ (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$src, ssub),
+ (i64 0)))>;
+
+def : Pat<(v2i64 (AArch64dup (i64 FPR64:$Rn))),
+ (v2i64 (DUPv2i64lane
+ (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
+ (i64 0)))>;
+
+def : Pat<(v2i32 (AArch64dup (i32 FPR32:$Rn))),
+ (v2i32 (DUPv2i32lane
+ (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
+ (i64 0)))>;
+
+def : Pat<(v4i16 (AArch64dup (i16 FPR16:$Rn))),
+ (v4i16 (DUPv4i16lane
+ (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
+ (i64 0)))>;
+
+def : Pat<(v8i16 (AArch64dup (i16 FPR16:$Rn))),
+ (v8i16 (DUPv8i16lane
+ (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
+ (i64 0)))>;
+
// DUP from a 64-bit register to a 64-bit register is just a copy
def : Pat<(v1i64 (AArch64dup (i64 GPR64:$Rn))),
(COPY_TO_REGCLASS GPR64:$Rn, FPR64)>;
@@ -8013,6 +8053,11 @@ def : Pat<(v4i32 (vec_ins_or_scal_vec GPR32:$Rn)),
def : Pat<(v2i64 (vec_ins_or_scal_vec GPR64:$Rn)),
(INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GPR64:$Rn, dsub)>;
+def : Pat<(v2i32 (vec_ins_or_scal_vec i32:$Rn)),
+ (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GPR32:$Rn, ssub)>;
+def : Pat<(v2i64 (vec_ins_or_scal_vec i64:$Rn)),
+ (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GPR64:$Rn, dsub)>;
+
def : Pat<(v4f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),
(INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
def : Pat<(v8f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),
@@ -8038,6 +8083,9 @@ def : Pat<(v4f32 (vec_ins_or_scal_vec (f32 FPR32:$Rn))),
def : Pat<(v2f32 (vec_ins_or_scal_vec (f32 FPR32:$Rn))),
(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
+def : Pat<(v4i32 (vec_ins_or_scal_vec (i32 FPR32:$Rn))),
+ (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
+
def : Pat<(v2f64 (vec_ins_or_scal_vec (f64 FPR64:$Rn))),
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
@@ -8064,6 +8112,29 @@ def : Pat<(vector_insert v2f64:$Rn, (f64 fpimm0), (i64 VectorIndexD:$imm)),
(INSvi64gpr V128:$Rn, VectorIndexS:$imm, XZR)>;
}
+def : Pat<(v8i16 (vector_insert (v8i16 V128:$Rn),
+ (i16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
+ (INSvi16lane
+ V128:$Rn, VectorIndexH:$imm,
+ (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
+ (i64 0))>;
+
+def : Pat<(v4i16 (vector_insert (v4i16 V64:$Rn),
+ (i16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
+ (EXTRACT_SUBREG
+ (INSvi16lane
+ (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
+ VectorIndexH:$imm,
+ (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
+ (i64 0)),
+ dsub)>;
+
+def : Pat<(v4i16 (vector_insert (v4i16 V64:$Rn), (i32 GPR32:$Rm), (i64 VectorIndexH:$imm))),
+ (EXTRACT_SUBREG
+ (INSvi16gpr (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
+ VectorIndexH:$imm, GPR32:$Rm),
+ dsub)>;
+
def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
(f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
(INSvi16lane
@@ -8228,21 +8299,24 @@ defm : Neon_INS_elt_pattern<v2f64, v1f64, nxv2f64, f64, VectorIndexD, INSvi6
// Accept i8 scalar argument in GlobalISel.
defm : Neon_INS_elt_pattern<v16i8, v8i8, nxv16i8, i8, VectorIndexB, INSvi8lane, DUPi8, bsub>;
defm : Neon_INS_elt_pattern<v16i8, v8i8, nxv16i8, i32, VectorIndexB, INSvi8lane, DUPi8, bsub>;
+defm : Neon_INS_elt_pattern<v8i16, v4i16, nxv8i16, i16, VectorIndexH, INSvi16lane, DUPi16, hsub>;
defm : Neon_INS_elt_pattern<v8i16, v4i16, nxv8i16, i32, VectorIndexH, INSvi16lane, DUPi16, hsub>;
defm : Neon_INS_elt_pattern<v4i32, v2i32, nxv4i32, i32, VectorIndexS, INSvi32lane, DUPi32, ssub>;
defm : Neon_INS_elt_pattern<v2i64, v1i64, nxv2i64, i64, VectorIndexD, INSvi64lane, DUPi64, dsub>;
// Insert from bitcast
-// vector_insert(bitcast(f32 src), n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)
-def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),
- (INSvi32lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>;
-def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),
+// vector_insert(i32, n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)
+def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 FPR32:$Sn), (i64 imm:$Immd))),
+ (INSvi32lane V128:$src, imm:$Immd,
+ (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>;
+def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 FPR32:$Sn), (i64 imm:$Immd))),
(EXTRACT_SUBREG
(INSvi32lane (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$src, dsub)),
imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0),
dsub)>;
-def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), (i64 imm:$Immd))),
- (INSvi64lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>;
+def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 FPR64:$Sn), (i64 imm:$Immd))),
+ (INSvi64lane V128:$src, imm:$Immd,
+ (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>;
// Patterns for i8/i16 -> v2i32/v4i16 lane moves via insert and extract that go via i32.
multiclass Neon_INS_elt_ext_pattern<ValueType VT128, ValueType VT64, ValueType OutVT,
@@ -9849,6 +9923,7 @@ class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
// Accept i8 scalar argument in GlobalISel.
def : Ld1Lane128Pat<load, VectorIndexB, v16i8, i8, LD1i8>;
def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
+def : Ld1Lane128Pat<load, VectorIndexH, v8i16, i16, LD1i16>;
def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
@@ -9925,6 +10000,7 @@ class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
// Accept i8 scalar argument in GlobalISel.
def : Ld1Lane64Pat<load, VectorIndexB, v8i8, i8, LD1i8>;
def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
+def : Ld1Lane64Pat<load, VectorIndexH, v4i16, i16, LD1i16>;
def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
@@ -9953,6 +10029,7 @@ class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
+def : St1Lane128Pat<store, VectorIndexH, v8i16, i16, ST1i16>;
def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
@@ -9971,6 +10048,7 @@ class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
+def : St1Lane64Pat<store, VectorIndexH, v4i16, i16, ST1i16>;
def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 436f50fe451be..d71ce27a145a9 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3612,6 +3612,14 @@ let Predicates = [HasSVE_or_SME] in {
def : Pat<(f64 (vector_extract nxv2f64:$vec, GPR64:$index)),
(LASTB_VPZ_D (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>;
+ // LASTB_RPZ_* expect a GPR destination register, LASTB_VPZ_* expect FPR destination registers
+ def : Pat<(i16 (vector_extract nxv8i16:$vec, GPR64:$index)),
+ (LASTB_VPZ_H (WHILELS_PXX_H XZR, GPR64:$index), ZPR:$vec)>;
+ def : Pat<(i32 (vector_extract nxv4i32:$vec, GPR64:$index)),
+ (LASTB_VPZ_S (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>;
+ def : Pat<(i64 (vector_extract nxv2i64:$vec, GPR64:$index)),
+ (LASTB_VPZ_D (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>;
+
// Extract element from vector with immediate index
def : Pat<(i32 (vector_extract nxv16i8:$vec, sve_elm_idx_extdup_b:$index)),
(EXTRACT_SUBREG (DUP_ZZI_B ZPR:$vec, sve_elm_idx_extdup_b:$index), ssub)>;
@@ -3708,6 +3716,8 @@ let Predicates = [HasSVE_or_SME] in {
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
def : Pat<(i32 (vector_extract nxv8i16:$Zs, (i64 0))),
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
+ def : Pat<(i16 (vector_extract nxv8i16:$Zs, (i64 0))),
+ (EXTRACT_SUBREG ZPR:$Zs, hsub)>;
def : Pat<(i32 (vector_extract nxv4i32:$Zs, (i64 0))),
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
def : Pat<(i64 (vector_extract nxv2i64:$Zs, (i64 0))),
>From fbc8c72f47cdaf7ad5fefda91e2cc0729cf6c714 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 29 Dec 2025 16:03:45 +0000
Subject: [PATCH 09/30] Add combine to store an i128 as a v2i64 when selecting
a store that can use register-indirect-offset addressing mode.
---
llvm/lib/Target/AArch64/AArch64Combine.td | 9 ++-
.../GISel/AArch64PostLegalizerLowering.cpp | 81 +++++++++++++++++++
2 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index fe953a627939d..7905f93a32d62 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -200,6 +200,13 @@ def vector_unmerge_lowering : GICombineRule <
(apply [{ applyScalarizeVectorUnmerge(*${root}, MRI, B); }])
>;
+def store_i128_as_v2i64 : GICombineRule <
+ (defs root:$root),
+ (match (wip_match_opcode G_STORE):$root,
+ [{ return matchStorei128AsV2i64(*${root}, MRI); }]),
+ (apply [{ applyStorei128AsV2i64(*${root}, MRI, B); }])
+>;
+
def adjust_icmp_imm_matchdata :
GIDefMatchData<"std::pair<uint64_t, CmpInst::Predicate>">;
def adjust_icmp_imm : GICombineRule <
@@ -352,7 +359,7 @@ def AArch64PostLegalizerLowering
lower_vector_fcmp, form_truncstore, fconstant_to_constant,
vector_sext_inreg_to_shift,
unmerge_ext_to_unmerge, lower_mulv2s64,
- vector_unmerge_lowering, insertelt_nonconst,
+ vector_unmerge_lowering, insertelt_nonconst, store_i128_as_v2i64,
unmerge_duplanes]> {
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 64d9fd89c9218..263c1e58fe6f3 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -706,6 +706,87 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
return std::nullopt;
}
+// Helper function for matchStorei128AsV2i64. This aids in finding pointers that
+// can use the register-indirect-offset addressing mode
+bool isPointerRoX(const MachineRegisterInfo &MRI, llvm::GStore *&Store) {
+ auto Ptr = Store->getPointerReg();
+ auto *PtrAdd = getOpcodeDef<GPtrAdd>(Ptr, MRI);
+ if (!PtrAdd || !MRI.hasOneNonDBGUse(Ptr))
+ return false;
+
+ Register Offset = PtrAdd->getOperand(2).getReg();
+ if (auto C = getIConstantVRegValWithLookThrough(Offset, MRI))
+ return false;
+
+ auto *OffsetDef = getDefIgnoringCopies(Offset, MRI);
+ if (!OffsetDef)
+ return false;
+
+ if (OffsetDef->getOpcode() == TargetOpcode::G_SHL ||
+ OffsetDef->getOpcode() == TargetOpcode::G_MUL) {
+ auto MaybeImm = getIConstantVRegValWithLookThrough(
+ OffsetDef->getOperand(2).getReg(), MRI);
+
+ if (!MaybeImm)
+ return false;
+
+ uint64_t Shift = OffsetDef->getOpcode() == TargetOpcode::G_SHL
+ ? MaybeImm->Value.getZExtValue()
+ : Log2_64(MaybeImm->Value.getZExtValue());
+
+ if (Shift != Log2_32(16))
+ return false;
+ }
+ return true;
+}
+
+// FPR128 doesn't allow i128 but it does allow v2i64. This means we can't
+// duplicate the pattern for f128 used here (AArch64InstrInfo.td:4617 STRQroX).
+// Instead, we can detect when this instruction would be used and force the
+// types to be a v2i64 thus allowing matching.
+bool matchStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI) {
+ assert(MI.getOpcode() == TargetOpcode::G_STORE &&
+ "Expected a store instruction");
+
+ auto *Store = cast<GStore>(&MI);
+ Register ValReg = Store->getValueReg();
+ LLT ValTy = MRI.getType(ValReg);
+
+ if (!ValTy.isInteger() && ValTy.getScalarSizeInBits() != 128)
+ return false;
+
+ auto *Merge = getOpcodeDef<GMerge>(ValReg, MRI);
+ if (!Merge || Merge->getNumSources() != 2)
+ return false;
+
+ if (!MRI.hasOneNonDBGUse(ValReg))
+ return false;
+
+ auto MergeUser = MRI.use_instr_nodbg_begin(ValReg);
+ if (MergeUser == MRI.use_instr_nodbg_end() || &*MergeUser != &MI)
+ return false;
+
+ if (MRI.getType(Merge->getSourceReg(0)).getScalarSizeInBits() != 64 ||
+ MRI.getType(Merge->getSourceReg(1)).getScalarSizeInBits() != 64)
+ return false;
+
+ return isPointerRoX(MRI, Store);
+};
+
+void applyStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI,
+ MachineIRBuilder &MIB) {
+ auto *Store = cast<GStore>(&MI);
+ Register ValReg = Store->getValueReg();
+
+ auto *Merge = getOpcodeDef<GMerge>(ValReg, MRI);
+
+ auto BV =
+ MIB.buildBuildVector(LLT::fixed_vector(2, LLT::integer(64)),
+ {Merge->getSourceReg(0), Merge->getSourceReg(1)})
+ .getReg(0);
+ MI.getOperand(0).setReg(BV);
+};
+
/// Determine whether or not it is possible to update the RHS and predicate of
/// a G_ICMP instruction such that the RHS will be selected as an arithmetic
/// immediate.
>From b04903fe2d97d820b6df8348249d38deb0b52443 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Wed, 8 Apr 2026 08:58:47 +0100
Subject: [PATCH 10/30] Update tests
---
.../Atomics/aarch64-atomic-store-rcpc_immo.ll | 2 +-
.../AArch64/Atomics/aarch64-atomicrmw-lsfe.ll | 100 +-
.../Atomics/aarch64-atomicrmw-v8a_fp.ll | 600 ++++----
.../AArch64/GlobalISel/arm64-atomic.ll | 80 +-
.../GlobalISel/arm64-callingconv-ios.ll | 136 +-
.../AArch64/GlobalISel/arm64-callingconv.ll | 250 +--
.../AArch64/GlobalISel/arm64-fallback.ll | 5 +-
.../GlobalISel/arm64-irtranslator-fmuladd.ll | 33 +-
.../GlobalISel/arm64-irtranslator-gep.ll | 68 +-
.../GlobalISel/arm64-irtranslator-switch.ll | 768 +++++-----
.../AArch64/GlobalISel/arm64-irtranslator.ll | 1334 +++++++++--------
.../AArch64/GlobalISel/arm64-pcsections.ll | 230 +--
.../AArch64/GlobalISel/bf16-fpext-fptrunc.ll | 127 ++
.../AArch64/GlobalISel/bf16-promote.ll | 200 +++
.../AArch64/GlobalISel/call-lowering-alias.ll | 2 +-
.../AArch64/GlobalISel/call-lowering-ifunc.ll | 2 +-
.../GlobalISel/call-lowering-signext.ll | 128 +-
.../GlobalISel/call-lowering-sret-demotion.ll | 156 +-
.../GlobalISel/call-lowering-vectors.ll | 57 +-
.../GlobalISel/call-lowering-zeroext.ll | 170 ++-
.../AArch64/GlobalISel/call-translator-cse.ll | 19 +-
.../AArch64/GlobalISel/call-translator-ios.ll | 59 +-
.../call-translator-tail-call-sret.ll | 12 +-
.../GlobalISel/call-translator-tail-call.ll | 330 ++--
.../AArch64/GlobalISel/call-translator.ll | 228 +--
.../AArch64/GlobalISel/combine-unmerge.mir | 8 +-
.../combiner-load-store-indexing.ll | 62 +-
.../AArch64/GlobalISel/constant-dbg-loc.ll | 18 +-
.../CodeGen/AArch64/GlobalISel/debug-insts.ll | 4 +-
.../AArch64/GlobalISel/dynamic-alloca.ll | 75 +-
.../AArch64/GlobalISel/fconstant-dbg-loc.ll | 2 +-
.../AArch64/GlobalISel/fold-fp-select.mir | 150 +-
.../GlobalISel/inline-memcpy-forced.mir | 36 +-
.../AArch64/GlobalISel/inline-memcpy.mir | 84 +-
.../AArch64/GlobalISel/inline-memmove.mir | 60 +-
.../AArch64/GlobalISel/inline-memset.mir | 68 +-
.../GlobalISel/inline-small-memcpy.mir | 8 +-
.../AArch64/GlobalISel/invoke-region.ll | 52 +-
.../GlobalISel/irtranslater-samesign.ll | 44 +-
.../GlobalISel/irtranslator-arguments.ll | 38 +-
.../irtranslator-atomic-metadata.ll | 84 +-
.../GlobalISel/irtranslator-bitcast.ll | 4 +-
.../irtranslator-condbr-lower-tree.ll | 364 +++--
.../irtranslator-convert-fp16-intrinsics.ll | 33 +
.../irtranslator-delayed-stack-protector.ll | 9 +-
.../GlobalISel/irtranslator-exceptions.ll | 58 +-
.../GlobalISel/irtranslator-extends.ll | 20 +-
.../irtranslator-fixed-point-intrinsics.ll | 152 +-
.../irtranslator-fp-min-max-intrinsics.ll | 110 +-
.../AArch64/GlobalISel/irtranslator-fpenv.ll | 16 +-
.../GlobalISel/irtranslator-gep-flags.ll | 238 +--
.../irtranslator-hoisted-constants.ll | 46 +-
.../GlobalISel/irtranslator-inline-asm.ll | 167 +--
.../GlobalISel/irtranslator-load-metadata.ll | 24 +-
.../GlobalISel/irtranslator-localescape.ll | 20 +-
.../irtranslator-max-address-space.ll | 7 +-
.../GlobalISel/irtranslator-memcpy-inline.ll | 120 +-
.../GlobalISel/irtranslator-nneg-disjoint.ll | 68 +-
.../irtranslator-no-op-intrinsics.ll | 20 +-
.../irtranslator-one-by-n-vector-ptr-add.ll | 24 +-
.../GlobalISel/irtranslator-reductions.ll | 173 +--
.../AArch64/GlobalISel/irtranslator-sincos.ll | 78 +-
.../irtranslator-split-vector-arg.ll | 15 +-
.../irtranslator-stack-evt-bug47619.ll | 31 +-
.../GlobalISel/irtranslator-stack-objects.ll | 12 +-
...slator-stack-protector-trap-unreachable.ll | 16 +-
.../GlobalISel/irtranslator-stepvector.ll | 16 +-
.../GlobalISel/irtranslator-store-metadata.ll | 16 +-
.../GlobalISel/irtranslator-subvector.ll | 246 +--
.../AArch64/GlobalISel/irtranslator-sucmp.ll | 24 +-
.../GlobalISel/irtranslator-switch-bittest.ll | 276 ++--
.../AArch64/GlobalISel/irtranslator-tbaa.ll | 11 +-
.../AArch64/GlobalISel/irtranslator-trunc.ll | 40 +-
.../irtranslator-unwind-inline-asm.ll | 6 +-
.../irtranslator-vector-deinterleave2.ll | 24 +-
.../irtranslator-vector-interleave2.ll | 16 +-
.../AArch64/GlobalISel/irtranslator-vscale.ll | 22 +-
.../AArch64/GlobalISel/legalize-and.mir | 49 +-
.../AArch64/GlobalISel/legalize-bitcast.mir | 120 +-
.../AArch64/GlobalISel/legalize-bswap.mir | 4 +-
.../GlobalISel/legalize-cmpxchg-128.mir | 18 +-
.../AArch64/GlobalISel/legalize-constant.mir | 32 +-
.../AArch64/GlobalISel/legalize-exceptions.ll | 10 +-
.../legalize-extract-vector-elt.mir | 16 +-
.../AArch64/GlobalISel/legalize-fcopysign.mir | 34 +-
.../GlobalISel/legalize-fp-arith-fp16.mir | 9 +-
.../AArch64/GlobalISel/legalize-fpext.mir | 42 +-
.../AArch64/GlobalISel/legalize-fptrunc.mir | 4 +-
.../GlobalISel/legalize-insert-vector-elt.mir | 8 +-
.../GlobalISel/legalize-intrinsic-min-max.mir | 32 +-
.../GlobalISel/legalize-load-store-vector.mir | 20 +-
.../GlobalISel/legalize-load-store.mir | 71 +-
.../AArch64/GlobalISel/legalize-min-max.mir | 192 +--
.../legalize-non-pow2-load-store.mir | 32 +-
.../AArch64/GlobalISel/legalize-or.mir | 16 +-
.../AArch64/GlobalISel/legalize-phi.mir | 16 +-
.../GlobalISel/legalize-reduce-add.mir | 7 +-
.../AArch64/GlobalISel/legalize-s128-div.mir | 36 +-
.../AArch64/GlobalISel/legalize-select.mir | 20 +-
.../GlobalISel/legalize-shuffle-vector.mir | 56 +-
.../legalize-store-vector-bools.mir | 104 +-
.../AArch64/GlobalISel/legalize-vacopy.mir | 18 +-
.../GlobalISel/legalize-vector-compress.mir | 4 +-
.../AArch64/GlobalISel/legalize-xor.mir | 40 +-
.../GlobalISel/load-addressing-modes.mir | 7 +-
.../AArch64/GlobalISel/localizer-arm64-tti.ll | 158 +-
.../AArch64/GlobalISel/phi-with-empty-type.ll | 4 +-
.../postlegalizer-combiner-unmergedup.mir | 8 +-
...legalizer-lowering-build-vector-to-dup.mir | 8 +-
.../postlegalizer-lowering-shuf-to-ins.mir | 72 +-
.../postlegalizer-lowering-shuffle-splat.mir | 48 +-
.../CodeGen/AArch64/GlobalISel/pr168872.ll | 36 +-
.../GlobalISel/preselect-process-phis.mir | 8 +-
.../GlobalISel/regbank-assert-sext.mir | 4 +-
.../GlobalISel/regbank-assert-zext.mir | 4 +-
.../CodeGen/AArch64/GlobalISel/ret-1x-vec.ll | 55 +-
.../AArch64/GlobalISel/ret-vec-promote.ll | 554 +++----
.../AArch64/GlobalISel/select-binop.mir | 64 +-
.../AArch64/GlobalISel/select-ceil.mir | 42 +-
.../AArch64/GlobalISel/select-constant.mir | 16 +-
.../CodeGen/AArch64/GlobalISel/select-dup.mir | 124 +-
.../AArch64/GlobalISel/select-fabs.mir | 42 +-
.../AArch64/GlobalISel/select-faddp.mir | 28 +-
.../AArch64/GlobalISel/select-fcmp.mir | 50 +-
.../AArch64/GlobalISel/select-floor.mir | 42 +-
.../AArch64/GlobalISel/select-fmaximum.mir | 24 +-
.../AArch64/GlobalISel/select-fminimum.mir | 24 +-
.../GlobalISel/select-fmul-indexed.mir | 18 +-
.../AArch64/GlobalISel/select-fp-casts.mir | 168 +--
.../GlobalISel/select-fp16-fconstant.mir | 12 +-
.../GlobalISel/select-frint-nofp16.mir | 98 +-
.../AArch64/GlobalISel/select-frint.mir | 48 +-
.../CodeGen/AArch64/GlobalISel/select-imm.mir | 24 +-
.../GlobalISel/select-insert-vector-elt.mir | 10 +-
.../GlobalISel/select-intrinsic-round.mir | 48 +-
.../GlobalISel/select-intrinsic-trunc.mir | 48 +-
.../AArch64/GlobalISel/select-nearbyint.mir | 42 +-
.../AArch64/GlobalISel/select-reduce-fadd.mir | 12 +-
.../AArch64/GlobalISel/select-sqrt.mir | 42 +-
.../select-with-no-legality-check.mir | 520 +++----
.../GlobalISel/store-addressing-modes.mir | 10 +-
.../GlobalISel/translate-constant-dag.ll | 45 +-
.../AArch64/GlobalISel/translate-gep.ll | 80 +-
.../AArch64/GlobalISel/translate-ret.ll | 47 +-
.../translate-sve-formal-argument-multiple.ll | 542 +++----
.../translate-sve-formal-argument.ll | 272 ++--
.../CodeGen/AArch64/GlobalISel/vec-param.ll | 378 ++---
.../AArch64/GlobalISel/vec-s16-param.ll | 20 +-
llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll | 43 +-
.../CodeGen/AArch64/arm64-arith-saturating.ll | 9 +-
.../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 213 +--
llvm/test/CodeGen/AArch64/arm64-neon-copy.ll | 5 -
llvm/test/CodeGen/AArch64/arm64-smaxv.ll | 85 +-
llvm/test/CodeGen/AArch64/arm64-sminv.ll | 85 +-
llvm/test/CodeGen/AArch64/arm64-vaddv.ll | 7 +-
llvm/test/CodeGen/AArch64/bitcast-extend.ll | 49 +-
llvm/test/CodeGen/AArch64/fcmp.ll | 12 +-
.../test/CodeGen/AArch64/fptosi-sat-scalar.ll | 60 +-
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 509 ++++---
.../test/CodeGen/AArch64/fptoui-sat-scalar.ll | 50 +-
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 477 +++---
llvm/test/CodeGen/AArch64/insertextract.ll | 8 +-
.../CodeGen/AArch64/neon-insextbitcast.ll | 24 +-
llvm/test/CodeGen/AArch64/popcount.ll | 43 +-
llvm/test/CodeGen/AArch64/ptrauth-isel.ll | 4 +-
165 files changed, 7852 insertions(+), 7158 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll
index 8c958459d93e8..eedae44e68798 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll
@@ -421,7 +421,7 @@ define void @store_atomic_i128_from_gep() {
; GISEL-LABEL: store_atomic_i128_from_gep:
; GISEL: bl init
; GISEL: dmb ish
-; GISEL: stp x8, x8, [x9, #16]
+; GISEL: stp x8, x9, [x10, #16]
;
; SDAG-LABEL: store_atomic_i128_from_gep:
; SDAG: bl init
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
index e0f2dd728c5e6..b18271dfd412c 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
@@ -379,10 +379,10 @@ define dso_local double @atomicrmw_fadd_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -393,10 +393,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -407,10 +407,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -421,10 +421,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -435,10 +435,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -539,9 +539,9 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_monotonic:
@@ -553,9 +553,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acquire:
@@ -567,9 +567,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_release:
@@ -581,9 +581,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
@@ -595,9 +595,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
@@ -609,9 +609,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_monotonic:
@@ -623,9 +623,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acquire:
@@ -637,9 +637,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_release:
@@ -651,9 +651,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
@@ -665,9 +665,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
index 4a1b7642eff4c..e56442e690645 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
@@ -5,10 +5,10 @@
define dso_local half @atomicrmw_fadd_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -19,10 +19,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fadd_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -33,10 +33,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fadd_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -47,10 +47,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fadd_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -61,10 +61,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fadd_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -165,9 +165,9 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fadd_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_monotonic:
@@ -179,9 +179,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fadd_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_acquire:
@@ -193,9 +193,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fadd_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_release:
@@ -207,9 +207,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fadd_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_acq_rel:
@@ -221,9 +221,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fadd_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_seq_cst:
@@ -235,9 +235,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fadd_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_monotonic:
@@ -249,9 +249,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fadd_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_acquire:
@@ -263,9 +263,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fadd_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_release:
@@ -277,9 +277,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fadd_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_acq_rel:
@@ -291,9 +291,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fadd_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_seq_cst:
@@ -480,10 +480,10 @@ define dso_local double @atomicrmw_fadd_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -494,10 +494,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -508,10 +508,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -522,10 +522,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -536,10 +536,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -640,9 +640,9 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_monotonic:
@@ -654,9 +654,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acquire:
@@ -668,9 +668,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_release:
@@ -682,9 +682,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
@@ -696,9 +696,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
@@ -710,9 +710,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_monotonic:
@@ -724,9 +724,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acquire:
@@ -738,9 +738,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_release:
@@ -752,9 +752,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
@@ -766,9 +766,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
@@ -955,10 +955,10 @@ define dso_local double @atomicrmw_fsub_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fmax_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -969,10 +969,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fmax_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -983,10 +983,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fmax_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -997,10 +997,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fmax_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1011,10 +1011,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fmax_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -1115,9 +1115,9 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fmax_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_monotonic:
@@ -1129,9 +1129,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fmax_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_acquire:
@@ -1143,9 +1143,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fmax_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_release:
@@ -1157,9 +1157,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fmax_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_acq_rel:
@@ -1171,9 +1171,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fmax_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_seq_cst:
@@ -1185,9 +1185,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fmax_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_monotonic:
@@ -1199,9 +1199,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fmax_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_acquire:
@@ -1213,9 +1213,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fmax_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_release:
@@ -1227,9 +1227,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fmax_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_acq_rel:
@@ -1241,9 +1241,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fmax_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_seq_cst:
@@ -1430,10 +1430,10 @@ define dso_local double @atomicrmw_fmax_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fmin_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -1444,10 +1444,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fmin_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -1458,10 +1458,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fmin_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -1472,10 +1472,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fmin_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1486,10 +1486,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fmin_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -1590,9 +1590,9 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fmin_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_monotonic:
@@ -1604,9 +1604,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fmin_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_acquire:
@@ -1618,9 +1618,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fmin_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_release:
@@ -1632,9 +1632,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fmin_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_acq_rel:
@@ -1646,9 +1646,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fmin_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_seq_cst:
@@ -1660,9 +1660,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fmin_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_monotonic:
@@ -1674,9 +1674,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fmin_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_acquire:
@@ -1688,9 +1688,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fmin_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_release:
@@ -1702,9 +1702,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fmin_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_acq_rel:
@@ -1716,9 +1716,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fmin_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_seq_cst:
@@ -1905,10 +1905,10 @@ define dso_local double @atomicrmw_fmin_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fmaximum_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -1919,10 +1919,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_monotonic(ptr %ptr, half
define dso_local half @atomicrmw_fmaximum_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -1933,10 +1933,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_acquire(ptr %ptr, half %v
define dso_local half @atomicrmw_fmaximum_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -1947,10 +1947,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_release(ptr %ptr, half %v
define dso_local half @atomicrmw_fmaximum_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1961,10 +1961,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_acq_rel(ptr %ptr, half %v
define dso_local half @atomicrmw_fmaximum_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2065,9 +2065,9 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_aligned_seq_cst(ptr %ptr, bfl
define dso_local float @atomicrmw_fmaximum_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_monotonic:
@@ -2079,9 +2079,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_monotonic(ptr %ptr, flo
define dso_local float @atomicrmw_fmaximum_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_acquire:
@@ -2093,9 +2093,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_acquire(ptr %ptr, float
define dso_local float @atomicrmw_fmaximum_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_release:
@@ -2107,9 +2107,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_release(ptr %ptr, float
define dso_local float @atomicrmw_fmaximum_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_acq_rel:
@@ -2121,9 +2121,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_acq_rel(ptr %ptr, float
define dso_local float @atomicrmw_fmaximum_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_seq_cst:
@@ -2135,9 +2135,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_seq_cst(ptr %ptr, float
define dso_local double @atomicrmw_fmaximum_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_monotonic:
@@ -2149,9 +2149,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_monotonic(ptr %ptr, d
define dso_local double @atomicrmw_fmaximum_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_acquire:
@@ -2163,9 +2163,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_acquire(ptr %ptr, dou
define dso_local double @atomicrmw_fmaximum_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_release:
@@ -2177,9 +2177,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_release(ptr %ptr, dou
define dso_local double @atomicrmw_fmaximum_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_acq_rel:
@@ -2191,9 +2191,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_acq_rel(ptr %ptr, dou
define dso_local double @atomicrmw_fmaximum_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_seq_cst:
@@ -2380,10 +2380,10 @@ define dso_local double @atomicrmw_fmaximum_double_unaligned_seq_cst(ptr %ptr, d
define dso_local half @atomicrmw_fminimum_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_monotonic:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -2394,10 +2394,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_monotonic(ptr %ptr, half
define dso_local half @atomicrmw_fminimum_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_acquire:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -2408,10 +2408,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_acquire(ptr %ptr, half %v
define dso_local half @atomicrmw_fminimum_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_release:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -2422,10 +2422,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_release(ptr %ptr, half %v
define dso_local half @atomicrmw_fminimum_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_acq_rel:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -2436,10 +2436,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_acq_rel(ptr %ptr, half %v
define dso_local half @atomicrmw_fminimum_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_seq_cst:
-; -O0: ldaxrh w0, [x9]
-; -O0: cmp w0, w10, uxth
-; -O0: stlxrh w8, w11, [x9]
-; -O0: subs w8, w8, w0, uxth
+; -O0: ldaxrh w9, [x10]
+; -O0: cmp w9, w11, uxth
+; -O0: stlxrh w8, w12, [x10]
+; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2540,9 +2540,9 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_aligned_seq_cst(ptr %ptr, bfl
define dso_local float @atomicrmw_fminimum_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_monotonic:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_monotonic:
@@ -2554,9 +2554,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_monotonic(ptr %ptr, flo
define dso_local float @atomicrmw_fminimum_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_acquire:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_acquire:
@@ -2568,9 +2568,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_acquire(ptr %ptr, float
define dso_local float @atomicrmw_fminimum_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_release:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_release:
@@ -2582,9 +2582,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_release(ptr %ptr, float
define dso_local float @atomicrmw_fminimum_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_acq_rel:
@@ -2596,9 +2596,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_acq_rel(ptr %ptr, float
define dso_local float @atomicrmw_fminimum_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x9]
-; -O0: cmp w0, w10
-; -O0: stlxr w8, w11, [x9]
+; -O0: ldaxr w0, [x10]
+; -O0: cmp w0, w8
+; -O0: stlxr w9, w11, [x10]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_seq_cst:
@@ -2610,9 +2610,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_seq_cst(ptr %ptr, float
define dso_local double @atomicrmw_fminimum_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_monotonic:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_monotonic:
@@ -2624,9 +2624,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_monotonic(ptr %ptr, d
define dso_local double @atomicrmw_fminimum_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_acquire:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_acquire:
@@ -2638,9 +2638,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_acquire(ptr %ptr, dou
define dso_local double @atomicrmw_fminimum_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_release:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_release:
@@ -2652,9 +2652,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_release(ptr %ptr, dou
define dso_local double @atomicrmw_fminimum_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_acq_rel:
@@ -2666,9 +2666,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_acq_rel(ptr %ptr, dou
define dso_local double @atomicrmw_fminimum_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x9]
-; -O0: cmp x0, x10
-; -O0: stlxr w8, x11, [x9]
+; -O0: ldaxr x0, [x10]
+; -O0: cmp x0, x8
+; -O0: stlxr w9, x11, [x10]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_seq_cst:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index 123df841402fc..4bc82a3719ae0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -2947,6 +2947,10 @@ define i16 @atomicrmw_add_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB37_1
; CHECK-NOLSE-O0-NEXT: b LBB37_5
@@ -3039,6 +3043,10 @@ define i16 @atomicrmw_xchg_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB38_1
; CHECK-NOLSE-O0-NEXT: b LBB38_5
@@ -3133,6 +3141,10 @@ define i16 @atomicrmw_sub_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB39_1
; CHECK-NOLSE-O0-NEXT: b LBB39_5
@@ -3231,6 +3243,10 @@ define i16 @atomicrmw_and_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB40_1
; CHECK-NOLSE-O0-NEXT: b LBB40_5
@@ -3329,6 +3345,10 @@ define i16 @atomicrmw_or_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB41_1
; CHECK-NOLSE-O0-NEXT: b LBB41_5
@@ -3423,6 +3443,10 @@ define i16 @atomicrmw_xor_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB42_1
; CHECK-NOLSE-O0-NEXT: b LBB42_5
@@ -3522,6 +3546,10 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB43_1
; CHECK-NOLSE-O0-NEXT: b LBB43_5
@@ -3539,8 +3567,8 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB43_1
; CHECK-OUTLINE-O0-NEXT: LBB43_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3557,7 +3585,11 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
+; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB43_1
; CHECK-OUTLINE-O0-NEXT: b LBB43_2
; CHECK-OUTLINE-O0-NEXT: LBB43_2: ; %atomicrmw.end
@@ -3642,6 +3674,10 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB44_1
; CHECK-NOLSE-O0-NEXT: b LBB44_5
@@ -3659,8 +3695,8 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB44_1
; CHECK-OUTLINE-O0-NEXT: LBB44_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3677,7 +3713,11 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
+; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB44_1
; CHECK-OUTLINE-O0-NEXT: b LBB44_2
; CHECK-OUTLINE-O0-NEXT: LBB44_2: ; %atomicrmw.end
@@ -3764,6 +3804,10 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB45_1
; CHECK-NOLSE-O0-NEXT: b LBB45_5
@@ -3781,8 +3825,8 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB45_1
; CHECK-OUTLINE-O0-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3799,7 +3843,11 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
+; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB45_1
; CHECK-OUTLINE-O0-NEXT: b LBB45_2
; CHECK-OUTLINE-O0-NEXT: LBB45_2: ; %atomicrmw.end
@@ -3886,6 +3934,10 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: fmov s0, w9
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB46_1
; CHECK-NOLSE-O0-NEXT: b LBB46_5
@@ -3903,8 +3955,8 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB46_1
; CHECK-OUTLINE-O0-NEXT: LBB46_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3921,7 +3973,11 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
+; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
+; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB46_1
; CHECK-OUTLINE-O0-NEXT: b LBB46_2
; CHECK-OUTLINE-O0-NEXT: LBB46_2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
index b34e5ae45f7dd..16ddaba8b29a0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
@@ -8,39 +8,39 @@ declare void @varargs(i32, double, i64, ...)
define void @test_varargs() {
; CHECK-LABEL: name: test_varargs
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i8) = G_CONSTANT i8 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f64) = G_FCONSTANT double 2.000000e+00
; CHECK-NEXT: ADJCALLSTACKDOWN 40, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C3]](s8)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[C3]](i8)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s64)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ANYEXT]](s32)
- ; CHECK-NEXT: G_STORE [[ANYEXT1]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 1)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[C4]](s16)
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s64)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[ANYEXT2]](s32)
- ; CHECK-NEXT: G_STORE [[ANYEXT3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into stack + 8, align 1)
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C10]](s64)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32)
- ; CHECK-NEXT: G_STORE [[ANYEXT4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into stack + 16, align 1)
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C11]](s64)
- ; CHECK-NEXT: G_STORE [[C6]](s32), [[PTR_ADD3]](p0) :: (store (s32) into stack + 24, align 1)
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
- ; CHECK-NEXT: G_STORE [[C7]](s64), [[PTR_ADD4]](p0) :: (store (s64) into stack + 32, align 1)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
- ; CHECK-NEXT: $d0 = COPY [[C1]](s64)
- ; CHECK-NEXT: $x1 = COPY [[C2]](s64)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](i64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i64) = G_ANYEXT [[ANYEXT]](i32)
+ ; CHECK-NEXT: G_STORE [[ANYEXT1]](i64), [[PTR_ADD]](p0) :: (store (i64) into stack, align 1)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[C4]](i16)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](i64)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i64) = G_ANYEXT [[ANYEXT2]](i32)
+ ; CHECK-NEXT: G_STORE [[ANYEXT3]](i64), [[PTR_ADD1]](p0) :: (store (i64) into stack + 8, align 1)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C10]](i64)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i64) = G_ANYEXT [[C5]](i32)
+ ; CHECK-NEXT: G_STORE [[ANYEXT4]](i64), [[PTR_ADD2]](p0) :: (store (i64) into stack + 16, align 1)
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C11]](i64)
+ ; CHECK-NEXT: G_STORE [[C6]](f32), [[PTR_ADD3]](p0) :: (store (f32) into stack + 24, align 1)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](i64)
+ ; CHECK-NEXT: G_STORE [[C7]](f64), [[PTR_ADD4]](p0) :: (store (f64) into stack + 32, align 1)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
+ ; CHECK-NEXT: $d0 = COPY [[C1]](f64)
+ ; CHECK-NEXT: $x1 = COPY [[C2]](i64)
; CHECK-NEXT: BL @varargs, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $d0, implicit $x1
; CHECK-NEXT: ADJCALLSTACKUP 40, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: RET_ReallyLR
@@ -53,47 +53,47 @@ declare i64 @i8i16callee(i64 %a1, i64 %a2, i64 %a3, i8 signext %a4, i16 signext
define i32 @i8i16caller() nounwind readnone {
; CHECK-LABEL: name: i8i16caller
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s8) = G_CONSTANT i8 97
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 98
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s8) = G_CONSTANT i8 99
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s8) = G_CONSTANT i8 100
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i8) = G_CONSTANT i8 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i8) = G_CONSTANT i8 97
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i16) = G_CONSTANT i16 98
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i8) = G_CONSTANT i8 99
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i8) = G_CONSTANT i8 100
; CHECK-NEXT: ADJCALLSTACKDOWN 6, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
- ; CHECK-NEXT: G_STORE [[C8]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s64)
- ; CHECK-NEXT: G_STORE [[C9]](s16), [[PTR_ADD1]](p0) :: (store (s16) into stack + 2, align 1)
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C14]](s64)
- ; CHECK-NEXT: G_STORE [[C10]](s8), [[PTR_ADD2]](p0) :: (store (s8) into stack + 4)
- ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C15]](s64)
- ; CHECK-NEXT: G_STORE [[C11]](s8), [[PTR_ADD3]](p0) :: (store (s8) into stack + 5)
- ; CHECK-NEXT: $x0 = COPY [[C]](s64)
- ; CHECK-NEXT: $x1 = COPY [[C1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[C2]](s64)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C3]](s8)
- ; CHECK-NEXT: $w3 = COPY [[SEXT]](s32)
- ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C4]](s16)
- ; CHECK-NEXT: $w4 = COPY [[SEXT1]](s32)
- ; CHECK-NEXT: $x5 = COPY [[C5]](s64)
- ; CHECK-NEXT: $x6 = COPY [[C6]](s64)
- ; CHECK-NEXT: $x7 = COPY [[C7]](s64)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](i64)
+ ; CHECK-NEXT: G_STORE [[C8]](i8), [[PTR_ADD]](p0) :: (store (i8) into stack)
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](i64)
+ ; CHECK-NEXT: G_STORE [[C9]](i16), [[PTR_ADD1]](p0) :: (store (i16) into stack + 2, align 1)
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C14]](i64)
+ ; CHECK-NEXT: G_STORE [[C10]](i8), [[PTR_ADD2]](p0) :: (store (i8) into stack + 4)
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C15]](i64)
+ ; CHECK-NEXT: G_STORE [[C11]](i8), [[PTR_ADD3]](p0) :: (store (i8) into stack + 5)
+ ; CHECK-NEXT: $x0 = COPY [[C]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[C1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[C2]](i64)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[C3]](i8)
+ ; CHECK-NEXT: $w3 = COPY [[SEXT]](i32)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(i32) = G_SEXT [[C4]](i16)
+ ; CHECK-NEXT: $w4 = COPY [[SEXT1]](i32)
+ ; CHECK-NEXT: $x5 = COPY [[C5]](i64)
+ ; CHECK-NEXT: $x6 = COPY [[C6]](i64)
+ ; CHECK-NEXT: $x7 = COPY [[C7]](i64)
; CHECK-NEXT: BL @i8i16callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $w4, implicit $x5, implicit $x6, implicit $x7, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 6, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY1]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%call = tail call i64 @i8i16callee(i64 0, i64 1, i64 2, i8 signext 3, i16 signext 4, i64 5, i64 6, i64 7, i8 97, i16 98, i8 99, i8 100)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
index 048063823d1c1..91c57b718efca 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
@@ -9,15 +9,15 @@ define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2, $w3, $w4, $w5, $w6, $w7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $w6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $w7
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $w5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $w6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $w7
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
i32 %w4, i32 %w5, i32 %w6, i32 %w7) {
ret i32 %w0
@@ -28,15 +28,15 @@ define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
i64 %x4, i64 %x5, i64 %x6, i64 %x7) {
ret i64 %x0
@@ -67,8 +67,8 @@ define [1 x double] @args_arr([1 x double] %d0) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: $d0 = COPY [[COPY]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret [1 x double] %d0
}
@@ -77,25 +77,25 @@ declare void @varargs(i32, double, i64, ...)
define void @test_varargs() {
; CHECK-LABEL: name: test_varargs
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i8) = G_CONSTANT i8 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f64) = G_FCONSTANT double 2.000000e+00
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C3]](s8)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C4]](s16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
- ; CHECK-NEXT: $d0 = COPY [[C1]](s64)
- ; CHECK-NEXT: $x1 = COPY [[C2]](s64)
- ; CHECK-NEXT: $w2 = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: $w3 = COPY [[ANYEXT1]](s32)
- ; CHECK-NEXT: $w4 = COPY [[C5]](s32)
- ; CHECK-NEXT: $s1 = COPY [[C6]](s32)
- ; CHECK-NEXT: $d2 = COPY [[C7]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[C3]](i8)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[C4]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
+ ; CHECK-NEXT: $d0 = COPY [[C1]](f64)
+ ; CHECK-NEXT: $x1 = COPY [[C2]](i64)
+ ; CHECK-NEXT: $w2 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: $w3 = COPY [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $w4 = COPY [[C5]](i32)
+ ; CHECK-NEXT: $s1 = COPY [[C6]](f32)
+ ; CHECK-NEXT: $d2 = COPY [[C7]](f64)
; CHECK-NEXT: BL @varargs, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $d0, implicit $x1, implicit $w2, implicit $w3, implicit $w4, implicit $s1, implicit $d2
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: RET_ReallyLR
@@ -111,21 +111,21 @@ declare void @stack_ext_needed([8 x i64], i8 signext %in)
define void @test_stack_ext_needed() {
; CHECK-LABEL: name: test_stack_ext_needed
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i8) = G_CONSTANT i8 42
; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
- ; CHECK-NEXT: $x0 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x1 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x2 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x3 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x4 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x5 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x6 = COPY [[DEF]](s64)
- ; CHECK-NEXT: $x7 = COPY [[DEF]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i8), [[PTR_ADD]](p0) :: (store (i8) into stack)
+ ; CHECK-NEXT: $x0 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x4 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x5 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x6 = COPY [[DEF]](i64)
+ ; CHECK-NEXT: $x7 = COPY [[DEF]](i64)
; CHECK-NEXT: BL @stack_ext_needed, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7
; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: RET_ReallyLR
@@ -133,40 +133,40 @@ define void @test_stack_ext_needed() {
ret void
}
-; Check that we can lower incoming i128 types into constituent s64 gprs.
+; Check that we can lower incoming i128 types into constituent i64 gprs.
define void @callee_s128(i128 %a, i128 %b, ptr %ptr) {
; CHECK-LABEL: name: callee_s128
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x4
- ; CHECK-NEXT: G_STORE [[MV1]](s128), [[COPY4]](p0) :: (store (s128) into %ir.ptr)
+ ; CHECK-NEXT: G_STORE [[MV1]](i128), [[COPY4]](p0) :: (store (i128) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
store i128 %b, ptr %ptr
ret void
}
-; Check we can lower outgoing s128 arguments into s64 gprs.
+; Check we can lower outgoing s128 arguments into i64 gprs.
define void @caller_s128(ptr %ptr) {
; CHECK-LABEL: name: caller_s128
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.ptr)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i128) = G_LOAD [[COPY]](p0) :: (load (i128) from %ir.ptr)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](i128)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](i128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
; CHECK-NEXT: $x4 = COPY [[COPY]](p0)
; CHECK-NEXT: BL @callee_s128, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
@@ -182,47 +182,47 @@ declare i64 @i8i16callee(i64 %a1, i64 %a2, i64 %a3, i8 signext %a4, i16 signext
define i32 @i8i16caller() nounwind readnone {
; CHECK-LABEL: name: i8i16caller
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s8) = G_CONSTANT i8 97
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 98
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s8) = G_CONSTANT i8 99
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s8) = G_CONSTANT i8 100
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i8) = G_CONSTANT i8 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i8) = G_CONSTANT i8 97
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i16) = G_CONSTANT i16 98
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i8) = G_CONSTANT i8 99
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i8) = G_CONSTANT i8 100
; CHECK-NEXT: ADJCALLSTACKDOWN 32, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
- ; CHECK-NEXT: G_STORE [[C8]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s64)
- ; CHECK-NEXT: G_STORE [[C9]](s16), [[PTR_ADD1]](p0) :: (store (s16) into stack + 8, align 1)
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C14]](s64)
- ; CHECK-NEXT: G_STORE [[C10]](s8), [[PTR_ADD2]](p0) :: (store (s8) into stack + 16)
- ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C15]](s64)
- ; CHECK-NEXT: G_STORE [[C11]](s8), [[PTR_ADD3]](p0) :: (store (s8) into stack + 24)
- ; CHECK-NEXT: $x0 = COPY [[C]](s64)
- ; CHECK-NEXT: $x1 = COPY [[C1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[C2]](s64)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C3]](s8)
- ; CHECK-NEXT: $w3 = COPY [[SEXT]](s32)
- ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C4]](s16)
- ; CHECK-NEXT: $w4 = COPY [[SEXT1]](s32)
- ; CHECK-NEXT: $x5 = COPY [[C5]](s64)
- ; CHECK-NEXT: $x6 = COPY [[C6]](s64)
- ; CHECK-NEXT: $x7 = COPY [[C7]](s64)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](i64)
+ ; CHECK-NEXT: G_STORE [[C8]](i8), [[PTR_ADD]](p0) :: (store (i8) into stack)
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](i64)
+ ; CHECK-NEXT: G_STORE [[C9]](i16), [[PTR_ADD1]](p0) :: (store (i16) into stack + 8, align 1)
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C14]](i64)
+ ; CHECK-NEXT: G_STORE [[C10]](i8), [[PTR_ADD2]](p0) :: (store (i8) into stack + 16)
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C15]](i64)
+ ; CHECK-NEXT: G_STORE [[C11]](i8), [[PTR_ADD3]](p0) :: (store (i8) into stack + 24)
+ ; CHECK-NEXT: $x0 = COPY [[C]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[C1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[C2]](i64)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[C3]](i8)
+ ; CHECK-NEXT: $w3 = COPY [[SEXT]](i32)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(i32) = G_SEXT [[C4]](i16)
+ ; CHECK-NEXT: $w4 = COPY [[SEXT1]](i32)
+ ; CHECK-NEXT: $x5 = COPY [[C5]](i64)
+ ; CHECK-NEXT: $x6 = COPY [[C6]](i64)
+ ; CHECK-NEXT: $x7 = COPY [[C7]](i64)
; CHECK-NEXT: BL @i8i16callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $w4, implicit $x5, implicit $x6, implicit $x7, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 32, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY1]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%call = tail call i64 @i8i16callee(i64 0, i64 1, i64 2, i8 signext 3, i16 signext 4, i64 5, i64 6, i64 7, i8 97, i16 98, i8 99, i8 100)
@@ -235,9 +235,9 @@ define void @arg_v2i64(<2 x i64> %arg) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[COPY]](<2 x s64>), [[DEF]](p0) :: (store (<2 x s64>) into `ptr undef`)
+ ; CHECK-NEXT: G_STORE [[COPY]](<2 x i64>), [[DEF]](p0) :: (store (<2 x i64>) into `ptr undef`)
; CHECK-NEXT: RET_ReallyLR
store <2 x i64> %arg, ptr undef
ret void
@@ -248,13 +248,13 @@ define void @arg_v8i64(<8 x i64> %arg) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>), [[COPY3]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x i64>) = G_CONCAT_VECTORS [[COPY]](<2 x i64>), [[COPY1]](<2 x i64>), [[COPY2]](<2 x i64>), [[COPY3]](<2 x i64>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<8 x s64>), [[DEF]](p0) :: (store (<8 x s64>) into `ptr undef`)
+ ; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<8 x i64>), [[DEF]](p0) :: (store (<8 x i64>) into `ptr undef`)
; CHECK-NEXT: RET_ReallyLR
store <8 x i64> %arg, ptr undef
ret void
@@ -265,10 +265,10 @@ define void @arg_v4f32(<4 x float> %arg) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[DEF]](p0) :: (store (<4 x s32>) into `ptr undef`)
+ ; CHECK-NEXT: G_STORE [[BITCAST]](<4 x f32>), [[DEF]](p0) :: (store (<4 x f32>) into `ptr undef`)
; CHECK-NEXT: RET_ReallyLR
store <4 x float> %arg, ptr undef
ret void
@@ -279,17 +279,17 @@ define void @ret_arg_v16f32(<16 x float> %arg) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY2]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY3]](<2 x s64>)
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[BITCAST]](<4 x s32>), [[BITCAST1]](<4 x s32>), [[BITCAST2]](<4 x s32>), [[BITCAST3]](<4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x f32>) = G_CONCAT_VECTORS [[BITCAST]](<4 x f32>), [[BITCAST1]](<4 x f32>), [[BITCAST2]](<4 x f32>), [[BITCAST3]](<4 x f32>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<16 x s32>), [[DEF]](p0) :: (store (<16 x s32>) into `ptr undef`)
+ ; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<16 x f32>), [[DEF]](p0) :: (store (<16 x f32>) into `ptr undef`)
; CHECK-NEXT: RET_ReallyLR
store <16 x float> %arg, ptr undef
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
index f8cd868a4c755..3b56d062ffc5c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err
; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err
@@ -16,7 +17,7 @@ target triple = "aarch64--"
; Make sure we don't mess up metadata arguments.
declare void @llvm.write_register.i64(metadata, i64)
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_WRITE_REGISTER !0, %0:_(s64) (in function: test_write_register_intrin)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_WRITE_REGISTER !0, %0:_(i64) (in function: test_write_register_intrin)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_write_register_intrin
; FALLBACK-WITH-REPORT-LABEL: test_write_register_intrin:
define void @test_write_register_intrin() {
@@ -101,7 +102,7 @@ entry:
ret void
}
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %4:_(s128), %5:_(s1) = G_UMULO %0:_, %6:_ (in function: umul_s128)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %4:_(i128), %5:_(i1) = G_UMULO %0:_, %6:_ (in function: umul_s128)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for umul_s128
; FALLBACK-WITH-REPORT-OUT-LABEL: umul_s128
declare {i128, i1} @llvm.umul.with.overflow.i128(i128, i128) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
index 371255a11dea9..b742689a3ca45 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
@@ -7,23 +7,26 @@ target triple = "aarch64--"
define float @test_fmuladd(float %x, float %y, float %z) {
; FPFAST-LABEL: name: test_fmuladd
; FPFAST: bb.1 (%ir-block.0):
- ; FPFAST: liveins: $s0, $s1, $s2
- ; FPFAST: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; FPFAST: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; FPFAST: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
- ; FPFAST: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
- ; FPFAST: $s0 = COPY [[FMA]](s32)
- ; FPFAST: RET_ReallyLR implicit $s0
+ ; FPFAST-NEXT: liveins: $s0, $s1, $s2
+ ; FPFAST-NEXT: {{ $}}
+ ; FPFAST-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; FPFAST-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; FPFAST-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s2
+ ; FPFAST-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+ ; FPFAST-NEXT: $s0 = COPY [[FMA]](f32)
+ ; FPFAST-NEXT: RET_ReallyLR implicit $s0
+ ;
; FPOFF-LABEL: name: test_fmuladd
; FPOFF: bb.1 (%ir-block.0):
- ; FPOFF: liveins: $s0, $s1, $s2
- ; FPOFF: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; FPOFF: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; FPOFF: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
- ; FPOFF: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
- ; FPOFF: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
- ; FPOFF: $s0 = COPY [[FADD]](s32)
- ; FPOFF: RET_ReallyLR implicit $s0
+ ; FPOFF-NEXT: liveins: $s0, $s1, $s2
+ ; FPOFF-NEXT: {{ $}}
+ ; FPOFF-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; FPOFF-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; FPOFF-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s2
+ ; FPOFF-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[COPY1]]
+ ; FPOFF-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[COPY2]]
+ ; FPOFF-NEXT: $s0 = COPY [[FADD]](f32)
+ ; FPOFF-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.fmuladd.f32(float %x, float %y, float %z)
ret float %res
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
index da171edb03808..269597cbd730b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll
@@ -10,20 +10,20 @@ define i32 @cse_gep(ptr %ptr, i32 %idx) {
; O0-NEXT: liveins: $w1, $x0
; O0-NEXT: {{ $}}
; O0-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; O0-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; O0-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; O0-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; O0-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; O0-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; O0-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; O0-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; O0-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; O0-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; O0-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; O0-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; O0-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; O0-NEXT: [[MUL1:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; O0-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; O0-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; O0-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; O0-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; O0-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; O0-NEXT: $w0 = COPY [[ADD]](s32)
+ ; O0-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; O0-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; O0-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; O0-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; O0-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; O0-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; O0-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; O0-NEXT: $w0 = COPY [[ADD]](i32)
; O0-NEXT: RET_ReallyLR implicit $w0
;
; O3-LABEL: name: cse_gep
@@ -31,18 +31,18 @@ define i32 @cse_gep(ptr %ptr, i32 %idx) {
; O3-NEXT: liveins: $w1, $x0
; O3-NEXT: {{ $}}
; O3-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; O3-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; O3-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; O3-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; O3-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; O3-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; O3-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; O3-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; O3-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; O3-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; O3-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; O3-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; O3-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; O3-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; O3-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C1]](s64)
- ; O3-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from %ir.gep2)
- ; O3-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; O3-NEXT: $w0 = COPY [[ADD]](s32)
+ ; O3-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; O3-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; O3-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C1]](i64)
+ ; O3-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD1]](p0) :: (load (i32) from %ir.gep2)
+ ; O3-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; O3-NEXT: $w0 = COPY [[ADD]](i32)
; O3-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -60,11 +60,11 @@ define void @ossfuzz65052() {
; O0-NEXT: successors: %bb.2(0x80000000)
; O0-NEXT: {{ $}}
; O0-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; O0-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -170141183460469231731687303715884105728
- ; O0-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[C]](s128)
- ; O0-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; O0-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[TRUNC]], [[C1]]
- ; O0-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[MUL]](s64)
+ ; O0-NEXT: [[C:%[0-9]+]]:_(i128) = G_CONSTANT i128 -170141183460469231731687303715884105728
+ ; O0-NEXT: [[TRUNC:%[0-9]+]]:_(i64) = G_TRUNC [[C]](i128)
+ ; O0-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; O0-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[TRUNC]], [[C1]]
+ ; O0-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[MUL]](i64)
; O0-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; O0-NEXT: G_BR %bb.2
; O0-NEXT: {{ $}}
@@ -78,11 +78,11 @@ define void @ossfuzz65052() {
; O3-NEXT: successors: %bb.2(0x80000000)
; O3-NEXT: {{ $}}
; O3-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; O3-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -170141183460469231731687303715884105728
- ; O3-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[C]](s128)
- ; O3-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; O3-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[TRUNC]], [[C1]]
- ; O3-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[MUL]](s64)
+ ; O3-NEXT: [[C:%[0-9]+]]:_(i128) = G_CONSTANT i128 -170141183460469231731687303715884105728
+ ; O3-NEXT: [[TRUNC:%[0-9]+]]:_(i64) = G_TRUNC [[C]](i128)
+ ; O3-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; O3-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[TRUNC]], [[C1]]
+ ; O3-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[MUL]](i64)
; O3-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; O3-NEXT: {{ $}}
; O3-NEXT: bb.2.BB:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
index 02a8a4f618156..46efce8004c9c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
@@ -6,36 +6,36 @@ define i32 @switch(i32 %argc) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 200
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 100
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 200
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.entry:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.4
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.default:
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C4]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[COPY]], [[C4]]
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.case100:
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C3]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[COPY]], [[C3]]
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.case200:
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(i32) = G_ADD [[COPY]], [[C2]]
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.return:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.2, [[ADD1]](s32), %bb.3, [[ADD2]](s32), %bb.4
- ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[ADD]](i32), %bb.2, [[ADD1]](i32), %bb.3, [[ADD2]](i32), %bb.4
+ ; CHECK-NEXT: $w0 = COPY [[PHI]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
switch i32 %argc, label %default [
@@ -65,30 +65,30 @@ define i32 @test_cfg_remap(i32 %in) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 57
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 57
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.next:
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.other:
- ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[DEF]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.phi.block:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.5, [[C2]](s32), %bb.2
- ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C]](i32), %bb.5, [[C2]](i32), %bb.2
+ ; CHECK-NEXT: $w0 = COPY [[PHI]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
switch i32 %in, label %phi.block [i32 1, label %next
@@ -110,25 +110,25 @@ define i32 @test_cfg_remap_multiple_preds(i32 %in) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 57
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 57
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 128
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.entry:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.4
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.entry:
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.5
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.5
; CHECK-NEXT: G_BR %bb.8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.8.entry:
@@ -141,12 +141,12 @@ define i32 @test_cfg_remap_multiple_preds(i32 %in) {
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.other:
- ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[DEF]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.phi.block:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.7, [[C]](s32), %bb.8, [[C4]](s32), %bb.3
- ; CHECK-NEXT: $w0 = COPY [[C3]](s32)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C]](i32), %bb.7, [[C]](i32), %bb.8, [[C4]](i32), %bb.3
+ ; CHECK-NEXT: $w0 = COPY [[C3]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
switch i32 %in, label %odd [i32 1, label %next
@@ -172,17 +172,17 @@ define i32 @jt_test(i32 %x) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 71
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C4]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[ZEXT]](s64), [[ZEXT1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 71
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[C4]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](i32)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[ZEXT]](s64), [[ZEXT1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
; CHECK-NEXT: successors: %bb.3, %bb.4, %bb.2
@@ -191,16 +191,16 @@ define i32 @jt_test(i32 %x) {
; CHECK-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[ZEXT]](s64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.bb:
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = nsw G_ADD [[COPY]], [[C2]]
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.sw.bb1:
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i32) = nsw G_MUL [[COPY]], [[C1]]
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.return:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C3]](s32), %bb.1, [[C3]](s32), %bb.5
- ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[MUL]](i32), %bb.3, [[ADD]](i32), %bb.2, [[C3]](i32), %bb.1, [[C3]](i32), %bb.5
+ ; CHECK-NEXT: $w0 = COPY [[PHI]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
switch i32 %x, label %return [
@@ -238,393 +238,393 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: liveins: $w1, $x0, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 18
- ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
- ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 22
- ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
- ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
- ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
- ; CHECK-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
- ; CHECK-NEXT: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
- ; CHECK-NEXT: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
- ; CHECK-NEXT: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
- ; CHECK-NEXT: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 34
- ; CHECK-NEXT: [[C31:%[0-9]+]]:_(s32) = G_CONSTANT i32 35
- ; CHECK-NEXT: [[C32:%[0-9]+]]:_(s32) = G_CONSTANT i32 36
- ; CHECK-NEXT: [[C33:%[0-9]+]]:_(s32) = G_CONSTANT i32 37
- ; CHECK-NEXT: [[C34:%[0-9]+]]:_(s32) = G_CONSTANT i32 38
- ; CHECK-NEXT: [[C35:%[0-9]+]]:_(s32) = G_CONSTANT i32 39
- ; CHECK-NEXT: [[C36:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
- ; CHECK-NEXT: [[C37:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C38:%[0-9]+]]:_(s32) = G_CONSTANT i32 43
- ; CHECK-NEXT: [[C39:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
- ; CHECK-NEXT: [[C40:%[0-9]+]]:_(s32) = G_CONSTANT i32 45
- ; CHECK-NEXT: [[C41:%[0-9]+]]:_(s32) = G_CONSTANT i32 46
- ; CHECK-NEXT: [[C42:%[0-9]+]]:_(s32) = G_CONSTANT i32 47
- ; CHECK-NEXT: [[C43:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
- ; CHECK-NEXT: [[C44:%[0-9]+]]:_(s32) = G_CONSTANT i32 49
- ; CHECK-NEXT: [[C45:%[0-9]+]]:_(s32) = G_CONSTANT i32 50
- ; CHECK-NEXT: [[C46:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
- ; CHECK-NEXT: [[C47:%[0-9]+]]:_(s32) = G_CONSTANT i32 52
- ; CHECK-NEXT: [[C48:%[0-9]+]]:_(s32) = G_CONSTANT i32 53
- ; CHECK-NEXT: [[C49:%[0-9]+]]:_(s32) = G_CONSTANT i32 54
- ; CHECK-NEXT: [[C50:%[0-9]+]]:_(s32) = G_CONSTANT i32 55
- ; CHECK-NEXT: [[C51:%[0-9]+]]:_(s32) = G_CONSTANT i32 4352
- ; CHECK-NEXT: [[C52:%[0-9]+]]:_(s32) = G_CONSTANT i32 4353
- ; CHECK-NEXT: [[C53:%[0-9]+]]:_(s32) = G_CONSTANT i32 4354
- ; CHECK-NEXT: [[C54:%[0-9]+]]:_(s32) = G_CONSTANT i32 4355
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 9
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 14
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i32) = G_CONSTANT i32 17
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i32) = G_CONSTANT i32 18
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i32) = G_CONSTANT i32 19
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 22
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 23
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(i32) = G_CONSTANT i32 25
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(i32) = G_CONSTANT i32 26
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(i32) = G_CONSTANT i32 27
+ ; CHECK-NEXT: [[C24:%[0-9]+]]:_(i32) = G_CONSTANT i32 28
+ ; CHECK-NEXT: [[C25:%[0-9]+]]:_(i32) = G_CONSTANT i32 29
+ ; CHECK-NEXT: [[C26:%[0-9]+]]:_(i32) = G_CONSTANT i32 30
+ ; CHECK-NEXT: [[C27:%[0-9]+]]:_(i32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[C28:%[0-9]+]]:_(i32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[C29:%[0-9]+]]:_(i32) = G_CONSTANT i32 33
+ ; CHECK-NEXT: [[C30:%[0-9]+]]:_(i32) = G_CONSTANT i32 34
+ ; CHECK-NEXT: [[C31:%[0-9]+]]:_(i32) = G_CONSTANT i32 35
+ ; CHECK-NEXT: [[C32:%[0-9]+]]:_(i32) = G_CONSTANT i32 36
+ ; CHECK-NEXT: [[C33:%[0-9]+]]:_(i32) = G_CONSTANT i32 37
+ ; CHECK-NEXT: [[C34:%[0-9]+]]:_(i32) = G_CONSTANT i32 38
+ ; CHECK-NEXT: [[C35:%[0-9]+]]:_(i32) = G_CONSTANT i32 39
+ ; CHECK-NEXT: [[C36:%[0-9]+]]:_(i32) = G_CONSTANT i32 41
+ ; CHECK-NEXT: [[C37:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C38:%[0-9]+]]:_(i32) = G_CONSTANT i32 43
+ ; CHECK-NEXT: [[C39:%[0-9]+]]:_(i32) = G_CONSTANT i32 44
+ ; CHECK-NEXT: [[C40:%[0-9]+]]:_(i32) = G_CONSTANT i32 45
+ ; CHECK-NEXT: [[C41:%[0-9]+]]:_(i32) = G_CONSTANT i32 46
+ ; CHECK-NEXT: [[C42:%[0-9]+]]:_(i32) = G_CONSTANT i32 47
+ ; CHECK-NEXT: [[C43:%[0-9]+]]:_(i32) = G_CONSTANT i32 48
+ ; CHECK-NEXT: [[C44:%[0-9]+]]:_(i32) = G_CONSTANT i32 49
+ ; CHECK-NEXT: [[C45:%[0-9]+]]:_(i32) = G_CONSTANT i32 50
+ ; CHECK-NEXT: [[C46:%[0-9]+]]:_(i32) = G_CONSTANT i32 51
+ ; CHECK-NEXT: [[C47:%[0-9]+]]:_(i32) = G_CONSTANT i32 52
+ ; CHECK-NEXT: [[C48:%[0-9]+]]:_(i32) = G_CONSTANT i32 53
+ ; CHECK-NEXT: [[C49:%[0-9]+]]:_(i32) = G_CONSTANT i32 54
+ ; CHECK-NEXT: [[C50:%[0-9]+]]:_(i32) = G_CONSTANT i32 55
+ ; CHECK-NEXT: [[C51:%[0-9]+]]:_(i32) = G_CONSTANT i32 4352
+ ; CHECK-NEXT: [[C52:%[0-9]+]]:_(i32) = G_CONSTANT i32 4353
+ ; CHECK-NEXT: [[C53:%[0-9]+]]:_(i32) = G_CONSTANT i32 4354
+ ; CHECK-NEXT: [[C54:%[0-9]+]]:_(i32) = G_CONSTANT i32 4355
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global
; CHECK-NEXT: [[C55:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C56:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C57:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C58:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C59:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C60:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C61:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C62:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[C63:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[C64:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[C65:%[0-9]+]]:_(s64) = G_CONSTANT i64 9
- ; CHECK-NEXT: [[C66:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
- ; CHECK-NEXT: [[C67:%[0-9]+]]:_(s64) = G_CONSTANT i64 11
- ; CHECK-NEXT: [[C68:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[C69:%[0-9]+]]:_(s64) = G_CONSTANT i64 13
- ; CHECK-NEXT: [[C70:%[0-9]+]]:_(s64) = G_CONSTANT i64 14
- ; CHECK-NEXT: [[C71:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK-NEXT: [[C72:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[C73:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
- ; CHECK-NEXT: [[C74:%[0-9]+]]:_(s64) = G_CONSTANT i64 18
- ; CHECK-NEXT: [[C75:%[0-9]+]]:_(s64) = G_CONSTANT i64 19
- ; CHECK-NEXT: [[C76:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
- ; CHECK-NEXT: [[C77:%[0-9]+]]:_(s64) = G_CONSTANT i64 21
- ; CHECK-NEXT: [[C78:%[0-9]+]]:_(s64) = G_CONSTANT i64 22
- ; CHECK-NEXT: [[C79:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
- ; CHECK-NEXT: [[C80:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[C81:%[0-9]+]]:_(s64) = G_CONSTANT i64 25
- ; CHECK-NEXT: [[C82:%[0-9]+]]:_(s64) = G_CONSTANT i64 26
- ; CHECK-NEXT: [[C83:%[0-9]+]]:_(s64) = G_CONSTANT i64 27
- ; CHECK-NEXT: [[C84:%[0-9]+]]:_(s64) = G_CONSTANT i64 28
- ; CHECK-NEXT: [[C85:%[0-9]+]]:_(s64) = G_CONSTANT i64 29
- ; CHECK-NEXT: [[C86:%[0-9]+]]:_(s64) = G_CONSTANT i64 30
- ; CHECK-NEXT: [[C87:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
- ; CHECK-NEXT: [[C88:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[C89:%[0-9]+]]:_(s64) = G_CONSTANT i64 33
- ; CHECK-NEXT: [[C90:%[0-9]+]]:_(s64) = G_CONSTANT i64 34
- ; CHECK-NEXT: [[C91:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
- ; CHECK-NEXT: [[C92:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
- ; CHECK-NEXT: [[C93:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[C94:%[0-9]+]]:_(s64) = G_CONSTANT i64 38
- ; CHECK-NEXT: [[C95:%[0-9]+]]:_(s64) = G_CONSTANT i64 39
- ; CHECK-NEXT: [[C96:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK-NEXT: [[C97:%[0-9]+]]:_(s64) = G_CONSTANT i64 41
- ; CHECK-NEXT: [[C98:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[C99:%[0-9]+]]:_(s64) = G_CONSTANT i64 43
- ; CHECK-NEXT: [[C100:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
- ; CHECK-NEXT: [[C101:%[0-9]+]]:_(s64) = G_CONSTANT i64 45
- ; CHECK-NEXT: [[C102:%[0-9]+]]:_(s64) = G_CONSTANT i64 46
- ; CHECK-NEXT: [[C103:%[0-9]+]]:_(s64) = G_CONSTANT i64 47
- ; CHECK-NEXT: [[C104:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[C105:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
- ; CHECK-NEXT: [[C106:%[0-9]+]]:_(s64) = G_CONSTANT i64 50
- ; CHECK-NEXT: [[C107:%[0-9]+]]:_(s64) = G_CONSTANT i64 51
- ; CHECK-NEXT: [[C108:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
- ; CHECK-NEXT: [[C109:%[0-9]+]]:_(s64) = G_CONSTANT i64 53
- ; CHECK-NEXT: [[C110:%[0-9]+]]:_(s64) = G_CONSTANT i64 54
+ ; CHECK-NEXT: [[C56:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C57:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C58:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C59:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C60:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C61:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C62:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[C63:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[C64:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[C65:%[0-9]+]]:_(i64) = G_CONSTANT i64 9
+ ; CHECK-NEXT: [[C66:%[0-9]+]]:_(i64) = G_CONSTANT i64 10
+ ; CHECK-NEXT: [[C67:%[0-9]+]]:_(i64) = G_CONSTANT i64 11
+ ; CHECK-NEXT: [[C68:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[C69:%[0-9]+]]:_(i64) = G_CONSTANT i64 13
+ ; CHECK-NEXT: [[C70:%[0-9]+]]:_(i64) = G_CONSTANT i64 14
+ ; CHECK-NEXT: [[C71:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
+ ; CHECK-NEXT: [[C72:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[C73:%[0-9]+]]:_(i64) = G_CONSTANT i64 17
+ ; CHECK-NEXT: [[C74:%[0-9]+]]:_(i64) = G_CONSTANT i64 18
+ ; CHECK-NEXT: [[C75:%[0-9]+]]:_(i64) = G_CONSTANT i64 19
+ ; CHECK-NEXT: [[C76:%[0-9]+]]:_(i64) = G_CONSTANT i64 20
+ ; CHECK-NEXT: [[C77:%[0-9]+]]:_(i64) = G_CONSTANT i64 21
+ ; CHECK-NEXT: [[C78:%[0-9]+]]:_(i64) = G_CONSTANT i64 22
+ ; CHECK-NEXT: [[C79:%[0-9]+]]:_(i64) = G_CONSTANT i64 23
+ ; CHECK-NEXT: [[C80:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[C81:%[0-9]+]]:_(i64) = G_CONSTANT i64 25
+ ; CHECK-NEXT: [[C82:%[0-9]+]]:_(i64) = G_CONSTANT i64 26
+ ; CHECK-NEXT: [[C83:%[0-9]+]]:_(i64) = G_CONSTANT i64 27
+ ; CHECK-NEXT: [[C84:%[0-9]+]]:_(i64) = G_CONSTANT i64 28
+ ; CHECK-NEXT: [[C85:%[0-9]+]]:_(i64) = G_CONSTANT i64 29
+ ; CHECK-NEXT: [[C86:%[0-9]+]]:_(i64) = G_CONSTANT i64 30
+ ; CHECK-NEXT: [[C87:%[0-9]+]]:_(i64) = G_CONSTANT i64 31
+ ; CHECK-NEXT: [[C88:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[C89:%[0-9]+]]:_(i64) = G_CONSTANT i64 33
+ ; CHECK-NEXT: [[C90:%[0-9]+]]:_(i64) = G_CONSTANT i64 34
+ ; CHECK-NEXT: [[C91:%[0-9]+]]:_(i64) = G_CONSTANT i64 35
+ ; CHECK-NEXT: [[C92:%[0-9]+]]:_(i64) = G_CONSTANT i64 36
+ ; CHECK-NEXT: [[C93:%[0-9]+]]:_(i64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[C94:%[0-9]+]]:_(i64) = G_CONSTANT i64 38
+ ; CHECK-NEXT: [[C95:%[0-9]+]]:_(i64) = G_CONSTANT i64 39
+ ; CHECK-NEXT: [[C96:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[C97:%[0-9]+]]:_(i64) = G_CONSTANT i64 41
+ ; CHECK-NEXT: [[C98:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[C99:%[0-9]+]]:_(i64) = G_CONSTANT i64 43
+ ; CHECK-NEXT: [[C100:%[0-9]+]]:_(i64) = G_CONSTANT i64 44
+ ; CHECK-NEXT: [[C101:%[0-9]+]]:_(i64) = G_CONSTANT i64 45
+ ; CHECK-NEXT: [[C102:%[0-9]+]]:_(i64) = G_CONSTANT i64 46
+ ; CHECK-NEXT: [[C103:%[0-9]+]]:_(i64) = G_CONSTANT i64 47
+ ; CHECK-NEXT: [[C104:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[C105:%[0-9]+]]:_(i64) = G_CONSTANT i64 49
+ ; CHECK-NEXT: [[C106:%[0-9]+]]:_(i64) = G_CONSTANT i64 50
+ ; CHECK-NEXT: [[C107:%[0-9]+]]:_(i64) = G_CONSTANT i64 51
+ ; CHECK-NEXT: [[C108:%[0-9]+]]:_(i64) = G_CONSTANT i64 52
+ ; CHECK-NEXT: [[C109:%[0-9]+]]:_(i64) = G_CONSTANT i64 53
+ ; CHECK-NEXT: [[C110:%[0-9]+]]:_(i64) = G_CONSTANT i64 54
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.tmp
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.56
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.56
; CHECK-NEXT: G_BR %bb.61
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.61.bb:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.2
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.62
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.62.bb:
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.63
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.63.bb:
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C3]]
- ; CHECK-NEXT: G_BRCOND [[ICMP3]](s1), %bb.4
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.64
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.64.bb:
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C4]]
- ; CHECK-NEXT: G_BRCOND [[ICMP4]](s1), %bb.5
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C4]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP4]](i1), %bb.5
; CHECK-NEXT: G_BR %bb.65
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.65.bb:
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C5]]
- ; CHECK-NEXT: G_BRCOND [[ICMP5]](s1), %bb.6
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C5]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP5]](i1), %bb.6
; CHECK-NEXT: G_BR %bb.66
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.66.bb:
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C6]]
- ; CHECK-NEXT: G_BRCOND [[ICMP6]](s1), %bb.7
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C6]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP6]](i1), %bb.7
; CHECK-NEXT: G_BR %bb.67
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.67.bb:
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C7]]
- ; CHECK-NEXT: G_BRCOND [[ICMP7]](s1), %bb.8
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C7]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP7]](i1), %bb.8
; CHECK-NEXT: G_BR %bb.68
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.68.bb:
- ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C8]]
- ; CHECK-NEXT: G_BRCOND [[ICMP8]](s1), %bb.9
+ ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C8]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP8]](i1), %bb.9
; CHECK-NEXT: G_BR %bb.69
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.69.bb:
- ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C9]]
- ; CHECK-NEXT: G_BRCOND [[ICMP9]](s1), %bb.10
+ ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C9]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP9]](i1), %bb.10
; CHECK-NEXT: G_BR %bb.70
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.70.bb:
- ; CHECK-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C10]]
- ; CHECK-NEXT: G_BRCOND [[ICMP10]](s1), %bb.11
+ ; CHECK-NEXT: [[ICMP10:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C10]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP10]](i1), %bb.11
; CHECK-NEXT: G_BR %bb.71
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.71.bb:
- ; CHECK-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C11]]
- ; CHECK-NEXT: G_BRCOND [[ICMP11]](s1), %bb.12
+ ; CHECK-NEXT: [[ICMP11:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C11]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP11]](i1), %bb.12
; CHECK-NEXT: G_BR %bb.72
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.72.bb:
- ; CHECK-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C12]]
- ; CHECK-NEXT: G_BRCOND [[ICMP12]](s1), %bb.13
+ ; CHECK-NEXT: [[ICMP12:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C12]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP12]](i1), %bb.13
; CHECK-NEXT: G_BR %bb.73
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.73.bb:
- ; CHECK-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C13]]
- ; CHECK-NEXT: G_BRCOND [[ICMP13]](s1), %bb.14
+ ; CHECK-NEXT: [[ICMP13:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C13]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP13]](i1), %bb.14
; CHECK-NEXT: G_BR %bb.74
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.74.bb:
- ; CHECK-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C14]]
- ; CHECK-NEXT: G_BRCOND [[ICMP14]](s1), %bb.15
+ ; CHECK-NEXT: [[ICMP14:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C14]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP14]](i1), %bb.15
; CHECK-NEXT: G_BR %bb.75
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.75.bb:
- ; CHECK-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C15]]
- ; CHECK-NEXT: G_BRCOND [[ICMP15]](s1), %bb.16
+ ; CHECK-NEXT: [[ICMP15:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C15]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP15]](i1), %bb.16
; CHECK-NEXT: G_BR %bb.76
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.76.bb:
- ; CHECK-NEXT: [[ICMP16:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C16]]
- ; CHECK-NEXT: G_BRCOND [[ICMP16]](s1), %bb.17
+ ; CHECK-NEXT: [[ICMP16:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C16]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP16]](i1), %bb.17
; CHECK-NEXT: G_BR %bb.77
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.77.bb:
- ; CHECK-NEXT: [[ICMP17:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C17]]
- ; CHECK-NEXT: G_BRCOND [[ICMP17]](s1), %bb.18
+ ; CHECK-NEXT: [[ICMP17:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C17]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP17]](i1), %bb.18
; CHECK-NEXT: G_BR %bb.78
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.78.bb:
- ; CHECK-NEXT: [[ICMP18:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C18]]
- ; CHECK-NEXT: G_BRCOND [[ICMP18]](s1), %bb.19
+ ; CHECK-NEXT: [[ICMP18:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C18]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP18]](i1), %bb.19
; CHECK-NEXT: G_BR %bb.79
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.79.bb:
- ; CHECK-NEXT: [[ICMP19:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C19]]
- ; CHECK-NEXT: G_BRCOND [[ICMP19]](s1), %bb.20
+ ; CHECK-NEXT: [[ICMP19:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C19]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP19]](i1), %bb.20
; CHECK-NEXT: G_BR %bb.80
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.80.bb:
- ; CHECK-NEXT: [[ICMP20:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C20]]
- ; CHECK-NEXT: G_BRCOND [[ICMP20]](s1), %bb.21
+ ; CHECK-NEXT: [[ICMP20:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C20]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP20]](i1), %bb.21
; CHECK-NEXT: G_BR %bb.81
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.81.bb:
- ; CHECK-NEXT: [[ICMP21:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C21]]
- ; CHECK-NEXT: G_BRCOND [[ICMP21]](s1), %bb.22
+ ; CHECK-NEXT: [[ICMP21:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C21]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP21]](i1), %bb.22
; CHECK-NEXT: G_BR %bb.82
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.82.bb:
- ; CHECK-NEXT: [[ICMP22:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C22]]
- ; CHECK-NEXT: G_BRCOND [[ICMP22]](s1), %bb.23
+ ; CHECK-NEXT: [[ICMP22:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C22]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP22]](i1), %bb.23
; CHECK-NEXT: G_BR %bb.83
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.83.bb:
- ; CHECK-NEXT: [[ICMP23:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C23]]
- ; CHECK-NEXT: G_BRCOND [[ICMP23]](s1), %bb.24
+ ; CHECK-NEXT: [[ICMP23:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C23]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP23]](i1), %bb.24
; CHECK-NEXT: G_BR %bb.84
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.84.bb:
- ; CHECK-NEXT: [[ICMP24:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C24]]
- ; CHECK-NEXT: G_BRCOND [[ICMP24]](s1), %bb.25
+ ; CHECK-NEXT: [[ICMP24:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C24]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP24]](i1), %bb.25
; CHECK-NEXT: G_BR %bb.85
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.85.bb:
- ; CHECK-NEXT: [[ICMP25:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C25]]
- ; CHECK-NEXT: G_BRCOND [[ICMP25]](s1), %bb.26
+ ; CHECK-NEXT: [[ICMP25:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C25]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP25]](i1), %bb.26
; CHECK-NEXT: G_BR %bb.86
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.86.bb:
- ; CHECK-NEXT: [[ICMP26:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C26]]
- ; CHECK-NEXT: G_BRCOND [[ICMP26]](s1), %bb.27
+ ; CHECK-NEXT: [[ICMP26:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C26]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP26]](i1), %bb.27
; CHECK-NEXT: G_BR %bb.87
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.87.bb:
- ; CHECK-NEXT: [[ICMP27:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C27]]
- ; CHECK-NEXT: G_BRCOND [[ICMP27]](s1), %bb.28
+ ; CHECK-NEXT: [[ICMP27:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C27]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP27]](i1), %bb.28
; CHECK-NEXT: G_BR %bb.88
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.88.bb:
- ; CHECK-NEXT: [[ICMP28:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C28]]
- ; CHECK-NEXT: G_BRCOND [[ICMP28]](s1), %bb.29
+ ; CHECK-NEXT: [[ICMP28:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C28]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP28]](i1), %bb.29
; CHECK-NEXT: G_BR %bb.89
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.89.bb:
- ; CHECK-NEXT: [[ICMP29:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C29]]
- ; CHECK-NEXT: G_BRCOND [[ICMP29]](s1), %bb.30
+ ; CHECK-NEXT: [[ICMP29:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C29]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP29]](i1), %bb.30
; CHECK-NEXT: G_BR %bb.90
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.90.bb:
- ; CHECK-NEXT: [[ICMP30:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C30]]
- ; CHECK-NEXT: G_BRCOND [[ICMP30]](s1), %bb.31
+ ; CHECK-NEXT: [[ICMP30:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C30]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP30]](i1), %bb.31
; CHECK-NEXT: G_BR %bb.91
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.91.bb:
- ; CHECK-NEXT: [[ICMP31:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C31]]
- ; CHECK-NEXT: G_BRCOND [[ICMP31]](s1), %bb.32
+ ; CHECK-NEXT: [[ICMP31:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C31]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP31]](i1), %bb.32
; CHECK-NEXT: G_BR %bb.92
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.92.bb:
- ; CHECK-NEXT: [[ICMP32:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C32]]
- ; CHECK-NEXT: G_BRCOND [[ICMP32]](s1), %bb.33
+ ; CHECK-NEXT: [[ICMP32:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C32]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP32]](i1), %bb.33
; CHECK-NEXT: G_BR %bb.93
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.93.bb:
- ; CHECK-NEXT: [[ICMP33:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C33]]
- ; CHECK-NEXT: G_BRCOND [[ICMP33]](s1), %bb.34
+ ; CHECK-NEXT: [[ICMP33:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C33]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP33]](i1), %bb.34
; CHECK-NEXT: G_BR %bb.94
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.94.bb:
- ; CHECK-NEXT: [[ICMP34:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C34]]
- ; CHECK-NEXT: G_BRCOND [[ICMP34]](s1), %bb.35
+ ; CHECK-NEXT: [[ICMP34:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C34]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP34]](i1), %bb.35
; CHECK-NEXT: G_BR %bb.95
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.95.bb:
- ; CHECK-NEXT: [[ICMP35:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C35]]
- ; CHECK-NEXT: G_BRCOND [[ICMP35]](s1), %bb.36
+ ; CHECK-NEXT: [[ICMP35:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C35]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP35]](i1), %bb.36
; CHECK-NEXT: G_BR %bb.96
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.96.bb:
- ; CHECK-NEXT: [[ICMP36:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C36]]
- ; CHECK-NEXT: G_BRCOND [[ICMP36]](s1), %bb.37
+ ; CHECK-NEXT: [[ICMP36:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C36]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP36]](i1), %bb.37
; CHECK-NEXT: G_BR %bb.97
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.97.bb:
- ; CHECK-NEXT: [[ICMP37:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C37]]
- ; CHECK-NEXT: G_BRCOND [[ICMP37]](s1), %bb.38
+ ; CHECK-NEXT: [[ICMP37:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C37]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP37]](i1), %bb.38
; CHECK-NEXT: G_BR %bb.98
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.98.bb:
- ; CHECK-NEXT: [[ICMP38:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C38]]
- ; CHECK-NEXT: G_BRCOND [[ICMP38]](s1), %bb.39
+ ; CHECK-NEXT: [[ICMP38:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C38]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP38]](i1), %bb.39
; CHECK-NEXT: G_BR %bb.99
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.99.bb:
- ; CHECK-NEXT: [[ICMP39:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C39]]
- ; CHECK-NEXT: G_BRCOND [[ICMP39]](s1), %bb.40
+ ; CHECK-NEXT: [[ICMP39:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C39]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP39]](i1), %bb.40
; CHECK-NEXT: G_BR %bb.100
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.100.bb:
- ; CHECK-NEXT: [[ICMP40:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C40]]
- ; CHECK-NEXT: G_BRCOND [[ICMP40]](s1), %bb.41
+ ; CHECK-NEXT: [[ICMP40:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C40]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP40]](i1), %bb.41
; CHECK-NEXT: G_BR %bb.101
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.101.bb:
- ; CHECK-NEXT: [[ICMP41:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C41]]
- ; CHECK-NEXT: G_BRCOND [[ICMP41]](s1), %bb.42
+ ; CHECK-NEXT: [[ICMP41:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C41]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP41]](i1), %bb.42
; CHECK-NEXT: G_BR %bb.102
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.102.bb:
- ; CHECK-NEXT: [[ICMP42:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C42]]
- ; CHECK-NEXT: G_BRCOND [[ICMP42]](s1), %bb.43
+ ; CHECK-NEXT: [[ICMP42:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C42]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP42]](i1), %bb.43
; CHECK-NEXT: G_BR %bb.103
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.103.bb:
- ; CHECK-NEXT: [[ICMP43:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C43]]
- ; CHECK-NEXT: G_BRCOND [[ICMP43]](s1), %bb.44
+ ; CHECK-NEXT: [[ICMP43:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C43]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP43]](i1), %bb.44
; CHECK-NEXT: G_BR %bb.104
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.104.bb:
- ; CHECK-NEXT: [[ICMP44:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C44]]
- ; CHECK-NEXT: G_BRCOND [[ICMP44]](s1), %bb.45
+ ; CHECK-NEXT: [[ICMP44:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C44]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP44]](i1), %bb.45
; CHECK-NEXT: G_BR %bb.105
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.105.bb:
- ; CHECK-NEXT: [[ICMP45:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C45]]
- ; CHECK-NEXT: G_BRCOND [[ICMP45]](s1), %bb.46
+ ; CHECK-NEXT: [[ICMP45:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C45]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP45]](i1), %bb.46
; CHECK-NEXT: G_BR %bb.106
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.106.bb:
- ; CHECK-NEXT: [[ICMP46:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C46]]
- ; CHECK-NEXT: G_BRCOND [[ICMP46]](s1), %bb.47
+ ; CHECK-NEXT: [[ICMP46:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C46]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP46]](i1), %bb.47
; CHECK-NEXT: G_BR %bb.107
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.107.bb:
- ; CHECK-NEXT: [[ICMP47:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C47]]
- ; CHECK-NEXT: G_BRCOND [[ICMP47]](s1), %bb.48
+ ; CHECK-NEXT: [[ICMP47:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C47]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP47]](i1), %bb.48
; CHECK-NEXT: G_BR %bb.108
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.108.bb:
- ; CHECK-NEXT: [[ICMP48:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C48]]
- ; CHECK-NEXT: G_BRCOND [[ICMP48]](s1), %bb.49
+ ; CHECK-NEXT: [[ICMP48:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C48]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP48]](i1), %bb.49
; CHECK-NEXT: G_BR %bb.109
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.109.bb:
- ; CHECK-NEXT: [[ICMP49:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C49]]
- ; CHECK-NEXT: G_BRCOND [[ICMP49]](s1), %bb.50
+ ; CHECK-NEXT: [[ICMP49:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C49]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP49]](i1), %bb.50
; CHECK-NEXT: G_BR %bb.110
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.110.bb:
- ; CHECK-NEXT: [[ICMP50:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C50]]
- ; CHECK-NEXT: G_BRCOND [[ICMP50]](s1), %bb.51
+ ; CHECK-NEXT: [[ICMP50:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C50]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP50]](i1), %bb.51
; CHECK-NEXT: G_BR %bb.111
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.111.bb:
- ; CHECK-NEXT: [[ICMP51:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C51]]
- ; CHECK-NEXT: G_BRCOND [[ICMP51]](s1), %bb.52
+ ; CHECK-NEXT: [[ICMP51:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C51]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP51]](i1), %bb.52
; CHECK-NEXT: G_BR %bb.112
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.112.bb:
- ; CHECK-NEXT: [[ICMP52:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C52]]
- ; CHECK-NEXT: G_BRCOND [[ICMP52]](s1), %bb.53
+ ; CHECK-NEXT: [[ICMP52:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C52]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP52]](i1), %bb.53
; CHECK-NEXT: G_BR %bb.113
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.113.bb:
- ; CHECK-NEXT: [[ICMP53:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C53]]
- ; CHECK-NEXT: G_BRCOND [[ICMP53]](s1), %bb.54
+ ; CHECK-NEXT: [[ICMP53:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C53]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP53]](i1), %bb.54
; CHECK-NEXT: G_BR %bb.114
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.114.bb:
- ; CHECK-NEXT: [[ICMP54:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C54]]
- ; CHECK-NEXT: G_BRCOND [[ICMP54]](s1), %bb.55
+ ; CHECK-NEXT: [[ICMP54:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY1]](i32), [[C54]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP54]](i1), %bb.55
; CHECK-NEXT: G_BR %bb.60
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb3:
@@ -790,12 +790,12 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: G_BR %bb.56
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.56.bb57:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[C56]](s64), %bb.1, [[C57]](s64), %bb.2, [[C58]](s64), %bb.3, [[C59]](s64), %bb.4, [[C60]](s64), %bb.5, [[C61]](s64), %bb.6, [[C62]](s64), %bb.7, [[C63]](s64), %bb.8, [[C64]](s64), %bb.9, [[C65]](s64), %bb.10, [[C66]](s64), %bb.11, [[C67]](s64), %bb.12, [[C68]](s64), %bb.13, [[C69]](s64), %bb.14, [[C70]](s64), %bb.15, [[C71]](s64), %bb.16, [[C72]](s64), %bb.17, [[C73]](s64), %bb.18, [[C74]](s64), %bb.19, [[C75]](s64), %bb.20, [[C76]](s64), %bb.21, [[C77]](s64), %bb.22, [[C78]](s64), %bb.23, [[C79]](s64), %bb.24, [[C80]](s64), %bb.25, [[C81]](s64), %bb.26, [[C82]](s64), %bb.27, [[C83]](s64), %bb.28, [[C84]](s64), %bb.29, [[C85]](s64), %bb.30, [[C86]](s64), %bb.31, [[C87]](s64), %bb.32, [[C88]](s64), %bb.33, [[C89]](s64), %bb.34, [[C90]](s64), %bb.35, [[C91]](s64), %bb.36, [[C92]](s64), %bb.37, [[C93]](s64), %bb.38, [[C94]](s64), %bb.39, [[C95]](s64), %bb.40, [[C96]](s64), %bb.41, [[C97]](s64), %bb.42, [[C98]](s64), %bb.43, [[C99]](s64), %bb.44, [[C100]](s64), %bb.45, [[C101]](s64), %bb.46, [[C102]](s64), %bb.47, [[C103]](s64), %bb.48, [[C104]](s64), %bb.49, [[C105]](s64), %bb.50, [[C106]](s64), %bb.51, [[C107]](s64), %bb.52, [[C108]](s64), %bb.53, [[C109]](s64), %bb.54, [[C110]](s64), %bb.55
- ; CHECK-NEXT: [[C111:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[PHI]], [[C111]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[GV]], [[MUL]](s64)
- ; CHECK-NEXT: [[C112:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C112]](s64)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i64) = G_PHI [[C56]](i64), %bb.1, [[C57]](i64), %bb.2, [[C58]](i64), %bb.3, [[C59]](i64), %bb.4, [[C60]](i64), %bb.5, [[C61]](i64), %bb.6, [[C62]](i64), %bb.7, [[C63]](i64), %bb.8, [[C64]](i64), %bb.9, [[C65]](i64), %bb.10, [[C66]](i64), %bb.11, [[C67]](i64), %bb.12, [[C68]](i64), %bb.13, [[C69]](i64), %bb.14, [[C70]](i64), %bb.15, [[C71]](i64), %bb.16, [[C72]](i64), %bb.17, [[C73]](i64), %bb.18, [[C74]](i64), %bb.19, [[C75]](i64), %bb.20, [[C76]](i64), %bb.21, [[C77]](i64), %bb.22, [[C78]](i64), %bb.23, [[C79]](i64), %bb.24, [[C80]](i64), %bb.25, [[C81]](i64), %bb.26, [[C82]](i64), %bb.27, [[C83]](i64), %bb.28, [[C84]](i64), %bb.29, [[C85]](i64), %bb.30, [[C86]](i64), %bb.31, [[C87]](i64), %bb.32, [[C88]](i64), %bb.33, [[C89]](i64), %bb.34, [[C90]](i64), %bb.35, [[C91]](i64), %bb.36, [[C92]](i64), %bb.37, [[C93]](i64), %bb.38, [[C94]](i64), %bb.39, [[C95]](i64), %bb.40, [[C96]](i64), %bb.41, [[C97]](i64), %bb.42, [[C98]](i64), %bb.43, [[C99]](i64), %bb.44, [[C100]](i64), %bb.45, [[C101]](i64), %bb.46, [[C102]](i64), %bb.47, [[C103]](i64), %bb.48, [[C104]](i64), %bb.49, [[C105]](i64), %bb.50, [[C106]](i64), %bb.51, [[C107]](i64), %bb.52, [[C108]](i64), %bb.53, [[C109]](i64), %bb.54, [[C110]](i64), %bb.55
+ ; CHECK-NEXT: [[C111:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[PHI]], [[C111]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[GV]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C112:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C112]](i64)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD1]](p0) :: (load (p0) from %ir.tmp59)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
@@ -816,7 +816,7 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.58.bb64:
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]](i32)
; CHECK-NEXT: $x1 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @baz, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $x1
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
@@ -832,8 +832,8 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.60.bb69:
- ; CHECK-NEXT: [[ICMP55:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](p0), [[C55]]
- ; CHECK-NEXT: G_BRCOND [[ICMP55]](s1), %bb.58
+ ; CHECK-NEXT: [[ICMP55:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY2]](p0), [[C55]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP55]](i1), %bb.58
; CHECK-NEXT: G_BR %bb.57
bb:
%tmp = alloca [16 x i32], align 4
@@ -1092,53 +1092,53 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-LABEL: name: jt_2_tables_phi_edge_from_second
; CHECK: bb.1.entry:
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 123
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 263
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 265
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 270
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 279
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 37
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 43
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 45
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 60
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 278
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 280
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 281
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 283
- ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
- ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32) from `ptr undef`, align 8)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.6
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 123
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 263
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 265
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 270
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 279
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 37
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 43
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 45
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i32) = G_CONSTANT i32 60
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 278
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 280
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 281
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i32) = G_CONSTANT i32 283
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(i1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 9
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[DEF]](p0) :: (load (i32) from `ptr undef`, align 8)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.6
; CHECK-NEXT: G_BR %bb.19
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.19.entry:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.4
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.20
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.20.entry:
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.7
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.7
; CHECK-NEXT: G_BR %bb.21
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.21.entry:
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]]
- ; CHECK-NEXT: G_BRCOND [[ICMP3]](s1), %bb.2
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.22
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.22.entry:
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C4]]
- ; CHECK-NEXT: G_BRCOND [[ICMP4]](s1), %bb.5
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C4]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP4]](i1), %bb.5
; CHECK-NEXT: G_BR %bb.23
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.23.entry:
@@ -1160,43 +1160,43 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C5]]
- ; CHECK-NEXT: G_BRCOND [[ICMP5]](s1), %bb.10
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C5]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP5]](i1), %bb.10
; CHECK-NEXT: G_BR %bb.24
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.24.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C6]]
- ; CHECK-NEXT: G_BRCOND [[ICMP6]](s1), %bb.16
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C6]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP6]](i1), %bb.16
; CHECK-NEXT: G_BR %bb.25
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.25.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C7]]
- ; CHECK-NEXT: G_BRCOND [[ICMP7]](s1), %bb.9
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C7]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP7]](i1), %bb.9
; CHECK-NEXT: G_BR %bb.26
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.26.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C8]]
- ; CHECK-NEXT: G_BRCOND [[ICMP8]](s1), %bb.14
+ ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C8]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP8]](i1), %bb.14
; CHECK-NEXT: G_BR %bb.27
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.27.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C9]]
- ; CHECK-NEXT: G_BRCOND [[ICMP9]](s1), %bb.11
+ ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C9]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP9]](i1), %bb.11
; CHECK-NEXT: G_BR %bb.28
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.28.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C10]]
- ; CHECK-NEXT: G_BRCOND [[ICMP10]](s1), %bb.13
+ ; CHECK-NEXT: [[ICMP10:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C10]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP10]](i1), %bb.13
; CHECK-NEXT: G_BR %bb.29
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.29.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C11]]
- ; CHECK-NEXT: G_BRCOND [[ICMP11]](s1), %bb.15
+ ; CHECK-NEXT: [[ICMP11:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C11]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP11]](i1), %bb.15
; CHECK-NEXT: G_BR %bb.30
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.30.sw.bb14.i48:
- ; CHECK-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C12]]
- ; CHECK-NEXT: G_BRCOND [[ICMP12]](s1), %bb.12
+ ; CHECK-NEXT: [[ICMP12:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF1]](i32), [[C12]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP12]](i1), %bb.12
; CHECK-NEXT: G_BR %bb.18
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.8.sw.default.i49:
@@ -1224,8 +1224,8 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: G_BR %bb.16
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.16.land.rhs.lr.ph:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C13]](s32), %bb.24, [[C14]](s32), %bb.9, [[C15]](s32), %bb.10, [[C16]](s32), %bb.11, [[C17]](s32), %bb.12, [[C18]](s32), %bb.13, [[C19]](s32), %bb.14, [[C20]](s32), %bb.15
- ; CHECK-NEXT: G_BRCOND [[DEF2]](s1), %bb.17
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C13]](i32), %bb.24, [[C14]](i32), %bb.9, [[C15]](i32), %bb.10, [[C16]](i32), %bb.11, [[C17]](i32), %bb.12, [[C18]](i32), %bb.13, [[C19]](i32), %bb.14, [[C20]](i32), %bb.15
+ ; CHECK-NEXT: G_BRCOND [[DEF2]](i1), %bb.17
; CHECK-NEXT: G_BR %bb.18
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.17.while.body:
@@ -1236,7 +1236,7 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.18.while.end:
- ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C21]](s32), %bb.30, [[PHI]](s32), %bb.16
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(i32) = G_PHI [[C21]](i32), %bb.30, [[PHI]](i32), %bb.16
; CHECK-NEXT: RET_ReallyLR
entry:
%0 = load i32, ptr undef, align 8
@@ -1319,34 +1319,34 @@ define i32 @range_test(i32 %x) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[SUB]](s32), [[C5]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.2
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(ule), [[SUB]](i32), [[C5]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.bb:
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C3]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = nsw G_ADD [[COPY]], [[C3]]
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.sw.bb1:
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i32) = nsw G_MUL [[COPY]], [[C2]]
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.return:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C4]](s32), %bb.5
- ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[MUL]](i32), %bb.3, [[ADD]](i32), %bb.2, [[C4]](i32), %bb.5
+ ; CHECK-NEXT: $w0 = COPY [[PHI]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
switch i32 %x, label %return [
@@ -1372,29 +1372,29 @@ return:
define ptr @test_range_phi_switch_cycle() {
; CHECK-LABEL: name: test_range_phi_switch_cycle
; CHECK: bb.1.bb:
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 305
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 307
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 497
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 305
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 307
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 497
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb1:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[DEF]](s32), %bb.1, [[C3]](s32), %bb.3, [[C4]](s32), %bb.4, [[C5]](s32), %bb.2
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.2
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[DEF]](i32), %bb.1, [[C3]](i32), %bb.3, [[C4]](i32), %bb.4, [[C5]](i32), %bb.2
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.bb1:
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.bb1:
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF]](s32), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.4
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[DEF]](i32), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.bb2:
@@ -1405,7 +1405,7 @@ define ptr @test_range_phi_switch_cycle() {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.bb4:
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[PHI]](i32)
; CHECK-NEXT: BL @ham, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
@@ -1444,14 +1444,14 @@ define i1 @i1_value_cmp_is_signed(i1) {
; CHECK: bb.1.Entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC]], 1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[TRUNC1]](s1), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TRUNC]], 1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_ZEXT]](i8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(sle), [[TRUNC1]](i1), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.BadValue:
@@ -1462,9 +1462,9 @@ define i1 @i1_value_cmp_is_signed(i1) {
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.OkValue:
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC1]](s1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[TRUNC1]](i1)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
Entry:
switch i1 %0, label %BadValue [
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index c68ae925d4295..d54a0581ceac8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat=false 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CV
; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CI
; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
@@ -9,9 +10,9 @@ target triple = "aarch64--"
; Tests for add.
; CHECK-LABEL: name: addi64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_ADD [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_ADD [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @addi64(i64 %arg1, i64 %arg2) {
@@ -20,9 +21,9 @@ define i64 @addi64(i64 %arg1, i64 %arg2) {
}
; CHECK-LABEL: name: muli64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_MUL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_MUL [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @muli64(i64 %arg1, i64 %arg2) {
@@ -110,8 +111,8 @@ end:
; CHECK: [[ADDR:%.*]]:_(p0) = COPY $x0
;
; Check that we emit the correct branch.
-; CHECK: [[TST:%.*]]:_(s1) = G_LOAD [[ADDR]](p0)
-; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]]
+; CHECK: [[TST:%.*]]:_(i1) = G_LOAD [[ADDR]](p0)
+; CHECK: G_BRCOND [[TST]](i1), %[[TRUE]]
; CHECK: G_BR %[[FALSE]]
;
; Check that each successor contains the return instruction.
@@ -165,9 +166,9 @@ L2: ; preds = %L1
; Tests for or.
; CHECK-LABEL: name: ori64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_OR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_OR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @ori64(i64 %arg1, i64 %arg2) {
@@ -176,9 +177,9 @@ define i64 @ori64(i64 %arg1, i64 %arg2) {
}
; CHECK-LABEL: name: ori32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_OR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_OR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @ori32(i32 %arg1, i32 %arg2) {
@@ -188,9 +189,9 @@ define i32 @ori32(i32 %arg1, i32 %arg2) {
; Tests for xor.
; CHECK-LABEL: name: xori64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_XOR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_XOR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @xori64(i64 %arg1, i64 %arg2) {
@@ -198,10 +199,11 @@ define i64 @xori64(i64 %arg1, i64 %arg2) {
ret i64 %res
}
+
; CHECK-LABEL: name: xori32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_XOR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_XOR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @xori32(i32 %arg1, i32 %arg2) {
@@ -211,9 +213,9 @@ define i32 @xori32(i32 %arg1, i32 %arg2) {
; Tests for and.
; CHECK-LABEL: name: andi64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_AND [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_AND [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @andi64(i64 %arg1, i64 %arg2) {
@@ -222,9 +224,9 @@ define i64 @andi64(i64 %arg1, i64 %arg2) {
}
; CHECK-LABEL: name: andi32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_AND [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_AND [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @andi32(i32 %arg1, i32 %arg2) {
@@ -234,9 +236,9 @@ define i32 @andi32(i32 %arg1, i32 %arg2) {
; Tests for sub.
; CHECK-LABEL: name: subi64
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_SUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_SUB [[ARG1]], [[ARG2]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
define i64 @subi64(i64 %arg1, i64 %arg2) {
@@ -245,9 +247,9 @@ define i64 @subi64(i64 %arg1, i64 %arg2) {
}
; CHECK-LABEL: name: subi32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_SUB [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @subi32(i32 %arg1, i32 %arg2) {
@@ -257,7 +259,7 @@ define i32 @subi32(i32 %arg1, i32 %arg2) {
; CHECK-LABEL: name: ptrtoint
; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[ARG1]]
+; CHECK: [[RES:%[0-9]+]]:_(i64) = G_PTRTOINT [[ARG1]]
; CHECK: $x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit $x0
define i64 @ptrtoint(ptr %a) {
@@ -266,7 +268,7 @@ define i64 @ptrtoint(ptr %a) {
}
; CHECK-LABEL: name: inttoptr
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
; CHECK: [[RES:%[0-9]+]]:_(p0) = G_INTTOPTR [[ARG1]]
; CHECK: $x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit $x0
@@ -284,7 +286,7 @@ define ptr @trivial_bitcast(ptr %a) {
}
; CHECK-LABEL: name: trivial_bitcast_with_copy
-; CHECK: [[A:%[0-9]+]]:_(s64) = COPY $d0
+; CHECK: [[A:%[0-9]+]]:_(i64) = COPY $x0
; CHECK: G_BR %[[CAST:bb\.[0-9]+]]
; CHECK: [[END:bb\.[0-9]+]].{{[a-zA-Z0-9.]+}}:
@@ -292,21 +294,21 @@ define ptr @trivial_bitcast(ptr %a) {
; CHECK: [[CAST]].{{[a-zA-Z0-9.]+}}:
; CHECK: G_BR %[[END]]
-define i64 @trivial_bitcast_with_copy(double %a) {
+define i64 @trivial_bitcast_with_copy(i64 %a) {
br label %cast
end:
ret i64 %val
cast:
- %val = bitcast double %a to i64
+ %val = bitcast i64 %a to i64
br label %end
}
; CHECK-LABEL: name: bitcast
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[RES1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[ARG1]]
-; CHECK: [[RES2:%[0-9]+]]:_(s64) = G_BITCAST [[RES1]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[RES1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[ARG1]]
+; CHECK: [[RES2:%[0-9]+]]:_(i64) = G_BITCAST [[RES1]]
; CHECK: $x0 = COPY [[RES2]]
; CHECK: RET_ReallyLR implicit $x0
define i64 @bitcast(i64 %a) {
@@ -328,10 +330,10 @@ define ptr @addrspacecast(ptr addrspace(1) %a) {
}
; CHECK-LABEL: name: trunc
-; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_LOAD
-; CHECK: [[RES1:%[0-9]+]]:_(s8) = G_TRUNC [[ARG1]]
-; CHECK: [[RES2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[VEC]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x i32>) = G_LOAD
+; CHECK: [[RES1:%[0-9]+]]:_(i8) = G_TRUNC [[ARG1]]
+; CHECK: [[RES2:%[0-9]+]]:_(<4 x i16>) = G_TRUNC [[VEC]]
define void @trunc(i64 %a) {
%vecptr = alloca <4 x i32>
%vec = load <4 x i32>, ptr %vecptr
@@ -343,13 +345,13 @@ define void @trunc(i64 %a) {
; CHECK-LABEL: name: load
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY $x1
-; CHECK: [[VAL1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load (s64) from %ir.addr, align 16)
-; CHECK: [[VAL2:%[0-9]+]]:_(s64) = G_LOAD [[ADDR42]](p42) :: (load (s64) from %ir.addr42, addrspace 42)
-; CHECK: [[SUM2:%.*]]:_(s64) = G_ADD [[VAL1]], [[VAL2]]
-; CHECK: [[VAL3:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (volatile load (s64) from %ir.addr)
-; CHECK: [[SUM3:%[0-9]+]]:_(s64) = G_ADD [[SUM2]], [[VAL3]]
-; CHECK: [[VAL4:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load (s64) from %ir.addr, !range !0)
-; CHECK: [[SUM4:%[0-9]+]]:_(s64) = G_ADD [[SUM3]], [[VAL4]]
+; CHECK: [[VAL1:%[0-9]+]]:_(i64) = G_LOAD [[ADDR]](p0) :: (load (i64) from %ir.addr, align 16)
+; CHECK: [[VAL2:%[0-9]+]]:_(i64) = G_LOAD [[ADDR42]](p42) :: (load (i64) from %ir.addr42, addrspace 42)
+; CHECK: [[SUM2:%.*]]:_(i64) = G_ADD [[VAL1]], [[VAL2]]
+; CHECK: [[VAL3:%[0-9]+]]:_(i64) = G_LOAD [[ADDR]](p0) :: (volatile load (i64) from %ir.addr)
+; CHECK: [[SUM3:%[0-9]+]]:_(i64) = G_ADD [[SUM2]], [[VAL3]]
+; CHECK: [[VAL4:%[0-9]+]]:_(i64) = G_LOAD [[ADDR]](p0) :: (load (i64) from %ir.addr, !range !0)
+; CHECK: [[SUM4:%[0-9]+]]:_(i64) = G_ADD [[SUM3]], [[VAL4]]
; CHECK: $x0 = COPY [[SUM4]]
; CHECK: RET_ReallyLR implicit $x0
define i64 @load(ptr %addr, ptr addrspace(42) %addr42) {
@@ -369,11 +371,11 @@ define i64 @load(ptr %addr, ptr addrspace(42) %addr42) {
; CHECK-LABEL: name: store
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY $x1
-; CHECK: [[VAL1:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: [[VAL2:%[0-9]+]]:_(s64) = COPY $x3
-; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (store (s64) into %ir.addr, align 16)
-; CHECK: G_STORE [[VAL2]](s64), [[ADDR42]](p42) :: (store (s64) into %ir.addr42, addrspace 42)
-; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (volatile store (s64) into %ir.addr)
+; CHECK: [[VAL1:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: [[VAL2:%[0-9]+]]:_(i64) = COPY $x3
+; CHECK: G_STORE [[VAL1]](i64), [[ADDR]](p0) :: (store (i64) into %ir.addr, align 16)
+; CHECK: G_STORE [[VAL2]](i64), [[ADDR42]](p42) :: (store (i64) into %ir.addr42, addrspace 42)
+; CHECK: G_STORE [[VAL1]](i64), [[ADDR]](p0) :: (volatile store (i64) into %ir.addr)
; CHECK: RET_ReallyLR
define void @store(ptr %addr, ptr addrspace(42) %addr42, i64 %val1, i64 %val2) {
store i64 %val1, ptr %addr, align 16
@@ -384,12 +386,12 @@ define void @store(ptr %addr, ptr addrspace(42) %addr42, i64 %val1, i64 %val2) {
}
; CHECK-LABEL: name: intrinsics
-; CHECK: [[CUR:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[BITS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[CUR:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[BITS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
; CHECK: [[PTR_VEC:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr.vec
-; CHECK: [[VEC:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[PTR_VEC]]
-; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), [[VEC]](<8 x s8>), [[VEC]](<8 x s8>), [[PTR]](p0)
+; CHECK: [[VEC:%[0-9]+]]:_(<8 x i8>) = G_LOAD [[PTR_VEC]]
+; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), [[VEC]](<8 x i8>), [[VEC]](<8 x i8>), [[PTR]](p0)
; CHECK: RET_ReallyLR
declare ptr @llvm.returnaddress(i32)
declare void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8>, <8 x i8>, ptr)
@@ -407,12 +409,12 @@ define void @intrinsics(i32 %cur, i32 %bits) {
; CHECK: G_BR %[[FALSE:bb\.[0-9]+]]
; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}:
-; CHECK: [[RES1:%[0-9]+]]:_(s32) = G_LOAD
+; CHECK: [[RES1:%[0-9]+]]:_(i32) = G_LOAD
; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}:
-; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_LOAD
+; CHECK: [[RES2:%[0-9]+]]:_(i32) = G_LOAD
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_PHI [[RES1]](i32), %[[TRUE]], [[RES2]](i32), %[[FALSE]]
; CHECK: $w0 = COPY [[RES]]
define i32 @test_phi(ptr %addr1, ptr %addr2, i1 %tst) {
br i1 %tst, label %true, label %false
@@ -441,13 +443,13 @@ define void @unreachable(i32 %a) {
; It's important that constants are after argument passing, but before the
; rest of the entry block.
; CHECK-LABEL: name: constant_int
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[ONE:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
-; CHECK: [[SUM1:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
-; CHECK: [[SUM2:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[SUM1]], [[SUM2]]
+; CHECK: [[SUM1:%[0-9]+]]:_(i32) = G_ADD [[IN]], [[ONE]]
+; CHECK: [[SUM2:%[0-9]+]]:_(i32) = G_ADD [[IN]], [[ONE]]
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_ADD [[SUM1]], [[SUM2]]
; CHECK: $w0 = COPY [[RES]]
define i32 @constant_int(i32 %in) {
@@ -461,23 +463,23 @@ next:
}
; CHECK-LABEL: name: constant_int_start
-; CHECK: [[TWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
+; CHECK: [[TWO:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+; CHECK: [[ANSWER:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_CONSTANT i32 44
define i32 @constant_int_start() {
%res = add i32 2, 42
ret i32 %res
}
; CHECK-LABEL: name: test_undef
-; CHECK: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+; CHECK: [[UNDEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
; CHECK: $w0 = COPY [[UNDEF]]
define i32 @test_undef() {
ret i32 undef
}
; CHECK-LABEL: name: test_constant_inttoptr
-; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+; CHECK: [[ONE:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ONE]]
; CHECK: $x0 = COPY [[PTR]]
define ptr @test_constant_inttoptr() {
@@ -487,15 +489,15 @@ define ptr @test_constant_inttoptr() {
; This failed purely because the Constant -> VReg map was kept across
; functions, so reuse the "i64 1" from above.
; CHECK-LABEL: name: test_reused_constant
-; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+; CHECK: [[ONE:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK: $x0 = COPY [[ONE]]
define i64 @test_reused_constant() {
ret i64 1
}
; CHECK-LABEL: name: test_sext
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_SEXT [[IN]]
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i64) = G_SEXT [[IN]]
; CHECK: $x0 = COPY [[RES]]
define i64 @test_sext(i32 %in) {
%res = sext i32 %in to i64
@@ -503,8 +505,8 @@ define i64 @test_sext(i32 %in) {
}
; CHECK-LABEL: name: test_zext
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ZEXT [[IN]]
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i64) = G_ZEXT [[IN]]
; CHECK: $x0 = COPY [[RES]]
define i64 @test_zext(i32 %in) {
%res = zext i32 %in to i64
@@ -512,9 +514,9 @@ define i64 @test_zext(i32 %in) {
}
; CHECK-LABEL: name: test_shl
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SHL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_SHL [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_shl(i32 %arg1, i32 %arg2) {
@@ -524,9 +526,9 @@ define i32 @test_shl(i32 %arg1, i32 %arg2) {
; CHECK-LABEL: name: test_lshr
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_LSHR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_LSHR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_lshr(i32 %arg1, i32 %arg2) {
@@ -535,9 +537,9 @@ define i32 @test_lshr(i32 %arg1, i32 %arg2) {
}
; CHECK-LABEL: name: test_ashr
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_ASHR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_ASHR [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_ashr(i32 %arg1, i32 %arg2) {
@@ -546,9 +548,9 @@ define i32 @test_ashr(i32 %arg1, i32 %arg2) {
}
; CHECK-LABEL: name: test_sdiv
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_SDIV [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
@@ -557,9 +559,9 @@ define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
}
; CHECK-LABEL: name: test_udiv
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_UDIV [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_udiv(i32 %arg1, i32 %arg2) {
@@ -568,9 +570,9 @@ define i32 @test_udiv(i32 %arg1, i32 %arg2) {
}
; CHECK-LABEL: name: test_srem
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_SREM [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_srem(i32 %arg1, i32 %arg2) {
@@ -579,9 +581,9 @@ define i32 @test_srem(i32 %arg1, i32 %arg2) {
}
; CHECK-LABEL: name: test_urem
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(i32) = G_UREM [[ARG1]], [[ARG2]]
; CHECK-NEXT: $w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
define i32 @test_urem(i32 %arg1, i32 %arg2) {
@@ -598,13 +600,13 @@ define ptr @test_constant_null() {
; CHECK-LABEL: name: test_struct_memops
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[VAL1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64)
-; CHECK: [[VAL2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load (s32) from %ir.addr + 4)
-; CHECK: G_STORE [[VAL1]](s8), [[ADDR]](p0) :: (store (s8) into %ir.addr, align 4)
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64)
-; CHECK: G_STORE [[VAL2]](s32), [[GEP2]](p0) :: (store (s32) into %ir.addr + 4)
+; CHECK: [[VAL1:%[0-9]+]]:_(i8) = G_LOAD %0(p0) :: (load (i8) from %ir.addr, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](i64)
+; CHECK: [[VAL2:%[0-9]+]]:_(i32) = G_LOAD [[GEP1]](p0) :: (load (i32) from %ir.addr + 4)
+; CHECK: G_STORE [[VAL1]](i8), [[ADDR]](p0) :: (store (i8) into %ir.addr, align 4)
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](i64)
+; CHECK: G_STORE [[VAL2]](i32), [[GEP2]](p0) :: (store (i32) into %ir.addr + 4)
define void @test_struct_memops(ptr %addr) {
%val = load { i8, i32 }, ptr %addr
store { i8, i32 } %val, ptr %addr
@@ -613,8 +615,8 @@ define void @test_struct_memops(ptr %addr) {
; CHECK-LABEL: name: test_i1_memops
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[VAL:%[0-9]+]]:_(s1) = G_LOAD [[ADDR]](p0) :: (load (s1) from %ir.addr)
-; CHECK: G_STORE [[VAL]](s1), [[ADDR]](p0) :: (store (s1) into %ir.addr)
+; CHECK: [[VAL:%[0-9]+]]:_(i1) = G_LOAD [[ADDR]](p0) :: (load (i1) from %ir.addr)
+; CHECK: G_STORE [[VAL]](i1), [[ADDR]](p0) :: (store (i1) into %ir.addr)
define void @test_i1_memops(ptr %addr) {
%val = load i1, ptr %addr
store i1 %val, ptr %addr
@@ -622,11 +624,11 @@ define void @test_i1_memops(ptr %addr) {
}
; CHECK-LABEL: name: int_comparison
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]]
-; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
+; CHECK: [[TST:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LHS]](i32), [[RHS]]
+; CHECK: G_STORE [[TST]](i1), [[ADDR]](p0)
define void @int_comparison(i32 %a, i32 %b, ptr %addr) {
%res = icmp ne i32 %a, %b
store i1 %res, ptr %addr
@@ -637,8 +639,8 @@ define void @int_comparison(i32 %a, i32 %b, ptr %addr) {
; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
-; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
+; CHECK: [[TST:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
+; CHECK: G_STORE [[TST]](i1), [[ADDR]](p0)
define void @ptr_comparison(ptr %a, ptr %b, ptr %addr) {
%res = icmp eq ptr %a, %b
store i1 %res, ptr %addr
@@ -646,9 +648,9 @@ define void @ptr_comparison(ptr %a, ptr %b, ptr %addr) {
}
; CHECK-LABEL: name: test_fadd
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FADD [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(f32) = G_FADD [[ARG1]], [[ARG2]]
; CHECK-NEXT: $s0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
define float @test_fadd(float %arg1, float %arg2) {
@@ -657,9 +659,9 @@ define float @test_fadd(float %arg1, float %arg2) {
}
; CHECK-LABEL: name: test_fsub
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FSUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(f32) = G_FSUB [[ARG1]], [[ARG2]]
; CHECK-NEXT: $s0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
define float @test_fsub(float %arg1, float %arg2) {
@@ -668,9 +670,9 @@ define float @test_fsub(float %arg1, float %arg2) {
}
; CHECK-LABEL: name: test_fmul
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FMUL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(f32) = G_FMUL [[ARG1]], [[ARG2]]
; CHECK-NEXT: $s0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
define float @test_fmul(float %arg1, float %arg2) {
@@ -679,9 +681,9 @@ define float @test_fmul(float %arg1, float %arg2) {
}
; CHECK-LABEL: name: test_fdiv
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(f32) = G_FDIV [[ARG1]], [[ARG2]]
; CHECK-NEXT: $s0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
define float @test_fdiv(float %arg1, float %arg2) {
@@ -690,9 +692,9 @@ define float @test_fdiv(float %arg1, float %arg2) {
}
; CHECK-LABEL: name: test_frem
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(f32) = G_FREM [[ARG1]], [[ARG2]]
; CHECK-NEXT: $s0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
define float @test_frem(float %arg1, float %arg2) {
@@ -701,14 +703,14 @@ define float @test_frem(float %arg1, float %arg2) {
}
; CHECK-LABEL: name: test_sadd_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SADDO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_SADDO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.addr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.addr + 4, align 4)
declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
define void @test_sadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
%res = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -717,14 +719,14 @@ define void @test_sadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
}
; CHECK-LABEL: name: test_uadd_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UADDO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_UADDO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.addr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.addr + 4, align 4)
declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
define void @test_uadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
%res = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -733,14 +735,14 @@ define void @test_uadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
}
; CHECK-LABEL: name: test_ssub_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SSUBO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.subr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.subr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_SSUBO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.subr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.subr + 4, align 4)
declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32)
define void @test_ssub_overflow(i32 %lhs, i32 %rhs, ptr %subr) {
%res = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -749,14 +751,14 @@ define void @test_ssub_overflow(i32 %lhs, i32 %rhs, ptr %subr) {
}
; CHECK-LABEL: name: test_usub_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_USUBO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.subr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.subr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_USUBO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.subr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.subr + 4, align 4)
declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32)
define void @test_usub_overflow(i32 %lhs, i32 %rhs, ptr %subr) {
%res = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -765,14 +767,14 @@ define void @test_usub_overflow(i32 %lhs, i32 %rhs, ptr %subr) {
}
; CHECK-LABEL: name: test_smul_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SMULO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_SMULO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.addr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.addr + 4, align 4)
declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
define void @test_smul_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
%res = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -781,14 +783,14 @@ define void @test_smul_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
}
; CHECK-LABEL: name: test_umul_overflow
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w1
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UMULO [[LHS]], [[RHS]]
-; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)
+; CHECK: [[VAL:%[0-9]+]]:_(i32), [[OVERFLOW:%[0-9]+]]:_(i1) = G_UMULO [[LHS]], [[RHS]]
+; CHECK: G_STORE [[VAL]](i32), [[ADDR]](p0) :: (store (i32) into %ir.addr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: G_STORE [[OVERFLOW]](i1), [[GEP]](p0) :: (store (i1) into %ir.addr + 4, align 4)
declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
define void @test_umul_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
%res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
@@ -798,17 +800,17 @@ define void @test_umul_overflow(i32 %lhs, i32 %rhs, ptr %addr) {
; CHECK-LABEL: name: test_extractvalue
; CHECK: %0:_(p0) = COPY $x0
-; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12)
-; CHECK: $w0 = COPY [[LD3]](s32)
+; CHECK: [[LD1:%[0-9]+]]:_(i8) = G_LOAD %0(p0) :: (load (i8) from %ir.addr, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i8) = G_LOAD [[GEP1]](p0) :: (load (i8) from %ir.addr + 4, align 4)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i32) = G_LOAD [[GEP2]](p0) :: (load (i32) from %ir.addr + 8)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: [[LD4:%[0-9]+]]:_(i32) = G_LOAD [[GEP3]](p0) :: (load (i32) from %ir.addr + 12)
+; CHECK: $w0 = COPY [[LD3]](i32)
%struct.nested = type {i8, { i8, i32 }, i32}
define i32 @test_extractvalue(ptr %addr) {
%struct = load %struct.nested, ptr %addr
@@ -819,19 +821,19 @@ define i32 @test_extractvalue(ptr %addr) {
; CHECK-LABEL: name: test_extractvalue_agg
; CHECK: %0:_(p0) = COPY $x0
; CHECK: %1:_(p0) = COPY $x1
-; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12)
-; CHECK: G_STORE [[LD2]](s8), %1(p0) :: (store (s8) into %ir.addr2, align 4)
-; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](s64)
-; CHECK: G_STORE [[LD3]](s32), [[GEP4]](p0) :: (store (s32) into %ir.addr2 + 4)
+; CHECK: [[LD1:%[0-9]+]]:_(i8) = G_LOAD %0(p0) :: (load (i8) from %ir.addr, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i8) = G_LOAD [[GEP1]](p0) :: (load (i8) from %ir.addr + 4, align 4)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i32) = G_LOAD [[GEP2]](p0) :: (load (i32) from %ir.addr + 8)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: [[LD4:%[0-9]+]]:_(i32) = G_LOAD [[GEP3]](p0) :: (load (i32) from %ir.addr + 12)
+; CHECK: G_STORE [[LD2]](i8), %1(p0) :: (store (i8) into %ir.addr2, align 4)
+; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](i64)
+; CHECK: G_STORE [[LD3]](i32), [[GEP4]](p0) :: (store (i32) into %ir.addr2 + 4)
define void @test_extractvalue_agg(ptr %addr, ptr %addr2) {
%struct = load %struct.nested, ptr %addr
%res = extractvalue %struct.nested %struct, 1
@@ -841,9 +843,9 @@ define void @test_extractvalue_agg(ptr %addr, ptr %addr2) {
; CHECK-LABEL: name: test_trivial_extract_ptr
; CHECK: [[STRUCT:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[VAL32:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_TRUNC [[VAL32]]
-; CHECK: G_STORE [[VAL]](s8), [[STRUCT]](p0)
+; CHECK: [[VAL32:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[VAL:%[0-9]+]]:_(i8) = G_TRUNC [[VAL32]]
+; CHECK: G_STORE [[VAL]](i8), [[STRUCT]](p0)
define void @test_trivial_extract_ptr([1 x ptr] %s, i8 %val) {
%addr = extractvalue [1 x ptr] %s, 0
store i8 %val, ptr %addr
@@ -852,24 +854,24 @@ define void @test_trivial_extract_ptr([1 x ptr] %s, i8 %val) {
; CHECK-LABEL: name: test_insertvalue
; CHECK: %0:_(p0) = COPY $x0
-; CHECK: %1:_(s32) = COPY $w1
-; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12)
-; CHECK: G_STORE [[LD1]](s8), %0(p0) :: (store (s8) into %ir.addr, align 4)
-; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: G_STORE [[LD2]](s8), [[GEP4]](p0) :: (store (s8) into %ir.addr + 4, align 4)
-; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)
-; CHECK: G_STORE %1(s32), [[GEP5]](p0) :: (store (s32) into %ir.addr + 8)
-; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: G_STORE [[LD4]](s32), [[GEP6]](p0) :: (store (s32) into %ir.addr + 12)
+; CHECK: %1:_(i32) = COPY $w1
+; CHECK: [[LD1:%[0-9]+]]:_(i8) = G_LOAD %0(p0) :: (load (i8) from %ir.addr, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i8) = G_LOAD [[GEP1]](p0) :: (load (i8) from %ir.addr + 4, align 4)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i32) = G_LOAD [[GEP2]](p0) :: (load (i32) from %ir.addr + 8)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: [[LD4:%[0-9]+]]:_(i32) = G_LOAD [[GEP3]](p0) :: (load (i32) from %ir.addr + 12)
+; CHECK: G_STORE [[LD1]](i8), %0(p0) :: (store (i8) into %ir.addr, align 4)
+; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: G_STORE [[LD2]](i8), [[GEP4]](p0) :: (store (i8) into %ir.addr + 4, align 4)
+; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](i64)
+; CHECK: G_STORE %1(i32), [[GEP5]](p0) :: (store (i32) into %ir.addr + 8)
+; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: G_STORE [[LD4]](i32), [[GEP6]](p0) :: (store (i32) into %ir.addr + 12)
define void @test_insertvalue(ptr %addr, i32 %val) {
%struct = load %struct.nested, ptr %addr
%newstruct = insertvalue %struct.nested %struct, i32 %val, 1, 1
@@ -879,8 +881,8 @@ define void @test_insertvalue(ptr %addr, i32 %val) {
define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) {
; CHECK-LABEL: name: test_trivial_insert
-; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[VAL:%[0-9]+]]:_(s64) = COPY $x1
+; CHECK: [[STRUCT:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[VAL:%[0-9]+]]:_(i64) = COPY $x1
; CHECK: $x0 = COPY [[VAL]]
%res = insertvalue [1 x i64] %s, i64 %val, 0
ret [1 x i64] %res
@@ -898,26 +900,26 @@ define [1 x ptr] @test_trivial_insert_ptr([1 x ptr] %s, ptr %val) {
; CHECK-LABEL: name: test_insertvalue_agg
; CHECK: %0:_(p0) = COPY $x0
; CHECK: %1:_(p0) = COPY $x1
-; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %1(p0) :: (load (s8) from %ir.addr2, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load (s32) from %ir.addr2 + 4)
-; CHECK: [[LD3:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: [[LD4:%[0-9]+]]:_(s8) = G_LOAD [[GEP2]](p0) :: (load (s8) from %ir.addr + 4, align 4)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: [[LD5:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 8)
-; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
-; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST4]](s64)
-; CHECK: [[LD6:%[0-9]+]]:_(s32) = G_LOAD [[GEP4]](p0) :: (load (s32) from %ir.addr + 12)
-; CHECK: G_STORE [[LD3]](s8), %0(p0) :: (store (s8) into %ir.addr, align 4)
-; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: G_STORE [[LD1]](s8), [[GEP5]](p0) :: (store (s8) into %ir.addr + 4, align 4)
-; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: G_STORE [[LD2]](s32), [[GEP6]](p0) :: (store (s32) into %ir.addr + 8)
-; CHECK: [[GEP7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST4]](s64)
-; CHECK: G_STORE [[LD6]](s32), [[GEP7]](p0) :: (store (s32) into %ir.addr + 12)
+; CHECK: [[LD1:%[0-9]+]]:_(i8) = G_LOAD %1(p0) :: (load (i8) from %ir.addr2, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i32) = G_LOAD [[GEP1]](p0) :: (load (i32) from %ir.addr2 + 4)
+; CHECK: [[LD3:%[0-9]+]]:_(i8) = G_LOAD %0(p0) :: (load (i8) from %ir.addr, align 4)
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: [[LD4:%[0-9]+]]:_(i8) = G_LOAD [[GEP2]](p0) :: (load (i8) from %ir.addr + 4, align 4)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: [[LD5:%[0-9]+]]:_(i32) = G_LOAD [[GEP3]](p0) :: (load (i32) from %ir.addr + 8)
+; CHECK: [[CST4:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST4]](i64)
+; CHECK: [[LD6:%[0-9]+]]:_(i32) = G_LOAD [[GEP4]](p0) :: (load (i32) from %ir.addr + 12)
+; CHECK: G_STORE [[LD3]](i8), %0(p0) :: (store (i8) into %ir.addr, align 4)
+; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: G_STORE [[LD1]](i8), [[GEP5]](p0) :: (store (i8) into %ir.addr + 4, align 4)
+; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: G_STORE [[LD2]](i32), [[GEP6]](p0) :: (store (i32) into %ir.addr + 8)
+; CHECK: [[GEP7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST4]](i64)
+; CHECK: G_STORE [[LD6]](i32), [[GEP7]](p0) :: (store (i32) into %ir.addr + 12)
define void @test_insertvalue_agg(ptr %addr, ptr %addr2) {
%smallstruct = load {i8, i32}, ptr %addr2
%struct = load %struct.nested, ptr %addr
@@ -927,13 +929,13 @@ define void @test_insertvalue_agg(ptr %addr, ptr %addr2) {
}
; CHECK-LABEL: name: test_select
-; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[TSTEXT:%[0-9]+]]:_(s8) = G_TRUNC [[TST_C]]
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w2
-; CHECK: [[TSTASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TSTEXT]], 1
-; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TSTASSERT]]
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TST_C:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[TSTEXT:%[0-9]+]]:_(i8) = G_TRUNC [[TST_C]]
+; CHECK: [[LHS:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w2
+; CHECK: [[TSTASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TSTEXT]], 1
+; CHECK: [[TST:%[0-9]+]]:_(i1) = G_TRUNC [[TSTASSERT]]
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_SELECT [[TST]](i1), [[LHS]], [[RHS]]
; CHECK: $w0 = COPY [[RES]]
define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {
%res = select i1 %tst, i32 %lhs, i32 %rhs
@@ -941,13 +943,13 @@ define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {
}
; CHECK-LABEL: name: test_select_flags
-; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]]
-; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC8]], 1
-; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNCASSERT]]
-; CHECK: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
+; CHECK: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[TRUNC8:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]]
+; CHECK: [[COPY1:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[COPY2:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TRUNC8]], 1
+; CHECK: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[TRUNCASSERT]]
+; CHECK: [[SELECT:%[0-9]+]]:_(f32) = nnan G_SELECT [[TRUNC]](i1), [[COPY1]], [[COPY2]]
define float @test_select_flags(i1 %tst, float %lhs, float %rhs) {
%res = select nnan i1 %tst, float %lhs, float %rhs
ret float %res
@@ -955,12 +957,12 @@ define float @test_select_flags(i1 %tst, float %lhs, float %rhs) {
; Don't take the flags from the compare condition
; CHECK-LABEL: name: test_select_cmp_flags
-; CHECK: [[COPY0:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
-; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s3
-; CHECK: [[CMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(oeq), [[COPY0]](s32), [[COPY1]]
-; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[CMP]](s1), [[COPY2]], [[COPY3]]
+; CHECK: [[COPY0:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[COPY2:%[0-9]+]]:_(f32) = COPY $s2
+; CHECK: [[COPY3:%[0-9]+]]:_(f32) = COPY $s3
+; CHECK: [[CMP:%[0-9]+]]:_(i1) = nsz G_FCMP floatpred(oeq), [[COPY0]](f32), [[COPY1]]
+; CHECK: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[CMP]](i1), [[COPY2]], [[COPY3]]
define float @test_select_cmp_flags(float %cmp0, float %cmp1, float %lhs, float %rhs) {
%tst = fcmp nsz oeq float %cmp0, %cmp1
%res = select i1 %tst, float %lhs, float %rhs
@@ -968,13 +970,13 @@ define float @test_select_cmp_flags(float %cmp0, float %cmp1, float %lhs, float
}
; CHECK-LABEL: name: test_select_ptr
-; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[TSTEXT:%[0-9]+]]:_(s8) = G_TRUNC [[TST_C]]
+; CHECK: [[TST_C:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[TSTEXT:%[0-9]+]]:_(i8) = G_TRUNC [[TST_C]]
; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[TSTASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TSTEXT]], 1
-; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TSTASSERT]]
-; CHECK: [[RES:%[0-9]+]]:_(p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TSTASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TSTEXT]], 1
+; CHECK: [[TST:%[0-9]+]]:_(i1) = G_TRUNC [[TSTASSERT]]
+; CHECK: [[RES:%[0-9]+]]:_(p0) = G_SELECT [[TST]](i1), [[LHS]], [[RHS]]
; CHECK: $x0 = COPY [[RES]]
define ptr @test_select_ptr(i1 %tst, ptr %lhs, ptr %rhs) {
%res = select i1 %tst, ptr %lhs, ptr %rhs
@@ -982,13 +984,13 @@ define ptr @test_select_ptr(i1 %tst, ptr %lhs, ptr %rhs) {
}
; CHECK-LABEL: name: test_select_vec
-; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[TSTEXT:%[0-9]+]]:_(s8) = G_TRUNC [[TST_C]]
-; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY $q0
-; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY $q1
-; CHECK: [[TSTASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TSTEXT]], 1
-; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TSTASSERT]]
-; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TST_C:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[TSTEXT:%[0-9]+]]:_(i8) = G_TRUNC [[TST_C]]
+; CHECK: [[LHS:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+; CHECK: [[RHS:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+; CHECK: [[TSTASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TSTEXT]], 1
+; CHECK: [[TST:%[0-9]+]]:_(i1) = G_TRUNC [[TSTASSERT]]
+; CHECK: [[RES:%[0-9]+]]:_(<4 x i32>) = G_SELECT [[TST]](i1), [[LHS]], [[RHS]]
; CHECK: $q0 = COPY [[RES]]
define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
%res = select i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs
@@ -996,11 +998,11 @@ define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
}
; CHECK-LABEL: name: test_vselect_vec
-; CHECK: [[TST32:%[0-9]+]]:_(<4 x s32>) = COPY $q0
-; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY $q1
-; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY $q2
-; CHECK: [[TST:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>)
-; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]]
+; CHECK: [[TST32:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+; CHECK: [[LHS:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+; CHECK: [[RHS:%[0-9]+]]:_(<4 x i32>) = COPY $q2
+; CHECK: [[TST:%[0-9]+]]:_(<4 x i1>) = G_TRUNC [[TST32]](<4 x i32>)
+; CHECK: [[RES:%[0-9]+]]:_(<4 x i32>) = G_SELECT [[TST]](<4 x i1>), [[LHS]], [[RHS]]
; CHECK: $q0 = COPY [[RES]]
define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %rhs) {
%tst = trunc <4 x i32> %tst32 to <4 x i1>
@@ -1010,8 +1012,8 @@ define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %
; CHECK-LABEL: name: test_fptosi
; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOSI [[FP]](s32)
+; CHECK: [[FP:%[0-9]+]]:_(f32) = G_LOAD [[FPADDR]](p0)
+; CHECK: [[RES:%[0-9]+]]:_(i64) = G_FPTOSI [[FP]](f32)
; CHECK: $x0 = COPY [[RES]]
define i64 @test_fptosi(ptr %fp.addr) {
%fp = load float, ptr %fp.addr
@@ -1021,8 +1023,8 @@ define i64 @test_fptosi(ptr %fp.addr) {
; CHECK-LABEL: name: test_fptoui
; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOUI [[FP]](s32)
+; CHECK: [[FP:%[0-9]+]]:_(f32) = G_LOAD [[FPADDR]](p0)
+; CHECK: [[RES:%[0-9]+]]:_(i64) = G_FPTOUI [[FP]](f32)
; CHECK: $x0 = COPY [[RES]]
define i64 @test_fptoui(ptr %fp.addr) {
%fp = load float, ptr %fp.addr
@@ -1032,9 +1034,9 @@ define i64 @test_fptoui(ptr %fp.addr) {
; CHECK-LABEL: name: test_sitofp
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[FP:%[0-9]+]]:_(s64) = G_SITOFP [[IN]](s32)
-; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[FP:%[0-9]+]]:_(f64) = G_SITOFP [[IN]](i32)
+; CHECK: G_STORE [[FP]](f64), [[ADDR]](p0)
define void @test_sitofp(ptr %addr, i32 %in) {
%fp = sitofp i32 %in to double
store double %fp, ptr %addr
@@ -1043,9 +1045,9 @@ define void @test_sitofp(ptr %addr, i32 %in) {
; CHECK-LABEL: name: test_uitofp
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[FP:%[0-9]+]]:_(s64) = G_UITOFP [[IN]](s32)
-; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[FP:%[0-9]+]]:_(f64) = G_UITOFP [[IN]](i32)
+; CHECK: G_STORE [[FP]](f64), [[ADDR]](p0)
define void @test_uitofp(ptr %addr, i32 %in) {
%fp = uitofp i32 %in to double
store double %fp, ptr %addr
@@ -1053,8 +1055,8 @@ define void @test_uitofp(ptr %addr, i32 %in) {
}
; CHECK-LABEL: name: test_fpext
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPEXT [[IN]](s32)
+; CHECK: [[IN:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f64) = G_FPEXT [[IN]](f32)
; CHECK: $d0 = COPY [[RES]]
define double @test_fpext(float %in) {
%res = fpext float %in to double
@@ -1062,8 +1064,8 @@ define double @test_fpext(float %in) {
}
; CHECK-LABEL: name: test_fptrunc
-; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY $d0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPTRUNC [[IN]](s64)
+; CHECK: [[IN:%[0-9]+]]:_(f64) = COPY $d0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = G_FPTRUNC [[IN]](f64)
; CHECK: $s0 = COPY [[RES]]
define float @test_fptrunc(double %in) {
%res = fptrunc double %in to float
@@ -1072,8 +1074,8 @@ define float @test_fptrunc(double %in) {
; CHECK-LABEL: name: test_constant_float
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[TMP:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+00
-; CHECK: G_STORE [[TMP]](s32), [[ADDR]](p0)
+; CHECK: [[TMP:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.500000e+00
+; CHECK: G_STORE [[TMP]](f32), [[ADDR]](p0)
define void @test_constant_float(ptr %addr) {
store float 1.5, ptr %addr
ret void
@@ -1083,10 +1085,10 @@ define void @test_constant_float(ptr %addr) {
; CHECK: [[LHSADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[RHSADDR:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[BOOLADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_LOAD [[LHSADDR]](p0)
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_LOAD [[RHSADDR]](p0)
-; CHECK: [[TST:%[0-9]+]]:_(s1) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
-; CHECK: G_STORE [[TST]](s1), [[BOOLADDR]](p0)
+; CHECK: [[LHS:%[0-9]+]]:_(f32) = G_LOAD [[LHSADDR]](p0)
+; CHECK: [[RHS:%[0-9]+]]:_(f32) = G_LOAD [[RHSADDR]](p0)
+; CHECK: [[TST:%[0-9]+]]:_(i1) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(oge), [[LHS]](f32), [[RHS]]
+; CHECK: G_STORE [[TST]](i1), [[BOOLADDR]](p0)
define void @float_comparison(ptr %a.addr, ptr %b.addr, ptr %bool.addr) {
%a = load float, ptr %a.addr
%b = load float, ptr %b.addr
@@ -1096,10 +1098,10 @@ define void @float_comparison(ptr %a.addr, ptr %b.addr, ptr %bool.addr) {
}
; CHECK-LABEL: name: trivial_float_comparison
-; CHECK: [[ENTRY_R1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
-; CHECK: [[ENTRY_R2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
-; CHECK: [[R1:%[0-9]+]]:_(s1) = COPY [[ENTRY_R1]](s1)
-; CHECK: [[R2:%[0-9]+]]:_(s1) = COPY [[ENTRY_R2]](s1)
+; CHECK: [[ENTRY_R1:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+; CHECK: [[ENTRY_R2:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+; CHECK: [[R1:%[0-9]+]]:_(i1) = COPY [[ENTRY_R1]](i1)
+; CHECK: [[R2:%[0-9]+]]:_(i1) = COPY [[ENTRY_R2]](i1)
; CHECK: G_ADD [[R1]], [[R2]]
define i1 @trivial_float_comparison(double %a, double %b) {
%r1 = fcmp false double %a, %b
@@ -1141,8 +1143,8 @@ define void @test_memcpy(ptr %dst, ptr %src, i64 %size) {
; CHECK-LABEL: name: test_memcpy
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
-; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: G_MEMCPY [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+; CHECK: [[SIZE:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: G_MEMCPY [[DST]](p0), [[SRC]](p0), [[SIZE]](i64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
call void @llvm.memcpy.p0.p0.i64(ptr %dst, ptr %src, i64 %size, i1 0)
ret void
}
@@ -1151,8 +1153,8 @@ define void @test_memcpy_tail(ptr %dst, ptr %src, i64 %size) {
; CHECK-LABEL: name: test_memcpy_tail
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
-; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: G_MEMCPY [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+; CHECK: [[SIZE:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: G_MEMCPY [[DST]](p0), [[SRC]](p0), [[SIZE]](i64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
tail call void @llvm.memcpy.p0.p0.i64(ptr %dst, ptr %src, i64 %size, i1 0)
ret void
}
@@ -1162,8 +1164,8 @@ define void @test_memcpy_nonzero_as(ptr addrspace(1) %dst, ptr addrspace(1) %src
; CHECK-LABEL: name: test_memcpy_nonzero_as
; CHECK: [[DST:%[0-9]+]]:_(p1) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p1) = COPY $x1
-; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: G_MEMCPY [[DST]](p1), [[SRC]](p1), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst, addrspace 1), (load (s8) from %ir.src, addrspace 1)
+; CHECK: [[SIZE:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: G_MEMCPY [[DST]](p1), [[SRC]](p1), [[SIZE]](i64), 0 :: (store (s8) into %ir.dst, addrspace 1), (load (s8) from %ir.src, addrspace 1)
call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) %dst, ptr addrspace(1) %src, i64 %size, i1 0)
ret void
}
@@ -1173,8 +1175,8 @@ define void @test_memmove(ptr %dst, ptr %src, i64 %size) {
; CHECK-LABEL: name: test_memmove
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
-; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: G_MEMMOVE [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+; CHECK: [[SIZE:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: G_MEMMOVE [[DST]](p0), [[SRC]](p0), [[SIZE]](i64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
call void @llvm.memmove.p0.p0.i64(ptr %dst, ptr %src, i64 %size, i1 0)
ret void
}
@@ -1183,10 +1185,10 @@ declare void @llvm.memset.p0.i64(ptr, i8, i64, i1)
define void @test_memset(ptr %dst, i8 %val, i64 %size) {
; CHECK-LABEL: name: test_memset
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[SRC_C:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[SRC:%[0-9]+]]:_(s8) = G_TRUNC [[SRC_C]]
-; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: G_MEMSET [[DST]](p0), [[SRC]](s8), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst)
+; CHECK: [[SRC_C:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[SRC:%[0-9]+]]:_(i8) = G_TRUNC [[SRC_C]]
+; CHECK: [[SIZE:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: G_MEMSET [[DST]](p0), [[SRC]](i8), [[SIZE]](i64), 0 :: (store (s8) into %ir.dst)
call void @llvm.memset.p0.i64(ptr %dst, i8 %val, i64 %size, i1 0)
ret void
}
@@ -1194,8 +1196,8 @@ define void @test_memset(ptr %dst, i8 %val, i64 %size) {
define void @test_large_const(ptr %addr) {
; CHECK-LABEL: name: test_large_const
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[VAL:%[0-9]+]]:_(s128) = G_CONSTANT i128 42
-; CHECK: G_STORE [[VAL]](s128), [[ADDR]](p0)
+; CHECK: [[VAL:%[0-9]+]]:_(i128) = G_CONSTANT i128 42
+; CHECK: G_STORE [[VAL]](i128), [[ADDR]](p0)
store i128 42, ptr %addr
ret void
}
@@ -1207,8 +1209,8 @@ define void @test_large_const(ptr %addr) {
define ptr @test_const_placement() {
; CHECK-LABEL: name: test_const_placement
; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
-; CHECK: [[VAL_INT:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
-; CHECK: [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](s32)
+; CHECK: [[VAL_INT:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+; CHECK: [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](i32)
; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
br label %next
@@ -1242,9 +1244,9 @@ define void @test_va_arg(ptr %list) {
declare float @llvm.pow.f32(float, float)
define float @test_pow_intrin(float %l, float %r) {
; CHECK-LABEL: name: test_pow_intrin
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOW [[LHS]], [[RHS]]
+; CHECK: [[LHS:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RHS:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FPOW [[LHS]], [[RHS]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.pow.f32(float %l, float %r)
ret float %res
@@ -1253,9 +1255,9 @@ define float @test_pow_intrin(float %l, float %r) {
declare float @llvm.powi.f32.i32(float, i32)
define float @test_powi_intrin(float %l, i32 %r) {
; CHECK-LABEL: name: test_powi_intrin
-; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOWI [[LHS]], [[RHS]]
+; CHECK: [[LHS:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RHS:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FPOWI [[LHS]], [[RHS]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.powi.f32.i32(float %l, i32 %r)
ret float %res
@@ -1264,10 +1266,10 @@ define float @test_powi_intrin(float %l, i32 %r) {
declare float @llvm.fma.f32(float, float, float)
define float @test_fma_intrin(float %a, float %b, float %c) {
; CHECK-LABEL: name: test_fma_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $s2
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[A]], [[B]], [[C]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[B:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[C:%[0-9]+]]:_(f32) = COPY $s2
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[A]], [[B]], [[C]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.fma.f32(float %a, float %b, float %c)
ret float %res
@@ -1276,8 +1278,8 @@ define float @test_fma_intrin(float %a, float %b, float %c) {
declare float @llvm.exp.f32(float)
define float @test_exp_intrin(float %a) {
; CHECK-LABEL: name: test_exp_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FEXP [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FEXP [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.exp.f32(float %a)
ret float %res
@@ -1286,8 +1288,8 @@ define float @test_exp_intrin(float %a) {
declare float @llvm.exp2.f32(float)
define float @test_exp2_intrin(float %a) {
; CHECK-LABEL: name: test_exp2_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FEXP2 [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FEXP2 [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.exp2.f32(float %a)
ret float %res
@@ -1296,8 +1298,8 @@ define float @test_exp2_intrin(float %a) {
declare float @llvm.log.f32(float)
define float @test_log_intrin(float %a) {
; CHECK-LABEL: name: test_log_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FLOG [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FLOG [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.log.f32(float %a)
ret float %res
@@ -1306,8 +1308,8 @@ define float @test_log_intrin(float %a) {
declare float @llvm.log2.f32(float)
define float @test_log2_intrin(float %a) {
; CHECK-LABEL: name: test_log2_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG2 [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = G_FLOG2 [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call float @llvm.log2.f32(float %a)
ret float %res
@@ -1316,8 +1318,8 @@ define float @test_log2_intrin(float %a) {
declare float @llvm.log10.f32(float)
define float @test_log10_intrin(float %a) {
; CHECK-LABEL: name: test_log10_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FLOG10 [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FLOG10 [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.log10.f32(float %a)
ret float %res
@@ -1326,8 +1328,8 @@ define float @test_log10_intrin(float %a) {
declare float @llvm.fabs.f32(float)
define float @test_fabs_intrin(float %a) {
; CHECK-LABEL: name: test_fabs_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FABS [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FABS [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.fabs.f32(float %a)
ret float %res
@@ -1336,9 +1338,9 @@ define float @test_fabs_intrin(float %a) {
declare float @llvm.copysign.f32(float, float)
define float @test_fcopysign_intrin(float %a, float %b) {
; CHECK-LABEL: name: test_fcopysign_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FCOPYSIGN [[A]], [[B]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[B:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FCOPYSIGN [[A]], [[B]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.copysign.f32(float %a, float %b)
@@ -1348,8 +1350,8 @@ define float @test_fcopysign_intrin(float %a, float %b) {
declare float @llvm.canonicalize.f32(float)
define float @test_fcanonicalize_intrin(float %a) {
; CHECK-LABEL: name: test_fcanonicalize_intrin
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FCANONICALIZE [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FCANONICALIZE [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call nnan ninf nsz arcp contract afn reassoc float @llvm.canonicalize.f32(float %a)
ret float %res
@@ -1358,8 +1360,8 @@ define float @test_fcanonicalize_intrin(float %a) {
declare float @llvm.trunc.f32(float)
define float @test_intrinsic_trunc(float %a) {
; CHECK-LABEL: name: test_intrinsic_trunc
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call float @llvm.trunc.f32(float %a)
ret float %res
@@ -1368,8 +1370,8 @@ define float @test_intrinsic_trunc(float %a) {
declare float @llvm.round.f32(float)
define float @test_intrinsic_round(float %a) {
; CHECK-LABEL: name: test_intrinsic_round
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUND [[A]]
; CHECK: $s0 = COPY [[RES]]
%res = call float @llvm.round.f32(float %a)
ret float %res
@@ -1378,8 +1380,8 @@ define float @test_intrinsic_round(float %a) {
declare i32 @llvm.lrint.i32.f32(float)
define i32 @test_intrinsic_lrint(float %a) {
; CHECK-LABEL: name: test_intrinsic_lrint
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_LRINT [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_INTRINSIC_LRINT [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.lrint.i32.f32(float %a)
ret i32 %res
@@ -1388,8 +1390,8 @@ define i32 @test_intrinsic_lrint(float %a) {
declare i32 @llvm.llrint.i32.f32(float)
define i32 @test_intrinsic_llrint(float %a) {
; CHECK-LABEL: name: test_intrinsic_llrint
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_LLRINT [[A]]
+; CHECK: [[A:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_INTRINSIC_LLRINT [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.llrint.i32.f32(float %a)
ret i32 %res
@@ -1398,8 +1400,8 @@ define i32 @test_intrinsic_llrint(float %a) {
declare i32 @llvm.ctlz.i32(i32, i1)
define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CTLZ [[A]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_CTLZ [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.ctlz.i32(i32 %a, i1 0)
ret i32 %res
@@ -1408,8 +1410,8 @@ define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
declare i32 @llvm.cttz.i32(i32, i1)
define i32 @test_cttz_intrinsic_zero_undef(i32 %a) {
; CHECK-LABEL: name: test_cttz_intrinsic_zero_undef
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[A]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_CTTZ_ZERO_UNDEF [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.cttz.i32(i32 %a, i1 1)
ret i32 %res
@@ -1418,8 +1420,8 @@ define i32 @test_cttz_intrinsic_zero_undef(i32 %a) {
declare i32 @llvm.ctpop.i32(i32)
define i32 @test_ctpop_intrinsic(i32 %a) {
; CHECK-LABEL: name: test_ctpop
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CTPOP [[A]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_CTPOP [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %res
@@ -1428,8 +1430,8 @@ define i32 @test_ctpop_intrinsic(i32 %a) {
declare i32 @llvm.bitreverse.i32(i32)
define i32 @test_bitreverse_intrinsic(i32 %a) {
; CHECK-LABEL: name: test_bitreverse
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_BITREVERSE [[A]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_BITREVERSE [[A]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.bitreverse.i32(i32 %a)
ret i32 %res
@@ -1438,10 +1440,10 @@ define i32 @test_bitreverse_intrinsic(i32 %a) {
declare i32 @llvm.fshl.i32(i32, i32, i32)
define i32 @test_fshl_intrinsic(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: name: test_fshl_intrinsic
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $w2
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FSHL [[A]], [[B]], [[C]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[B:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[C:%[0-9]+]]:_(i32) = COPY $w2
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_FSHL [[A]], [[B]], [[C]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
ret i32 %res
@@ -1450,10 +1452,10 @@ define i32 @test_fshl_intrinsic(i32 %a, i32 %b, i32 %c) {
declare i32 @llvm.fshr.i32(i32, i32, i32)
define i32 @test_fshr_intrinsic(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: name: test_fshr_intrinsic
-; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $w2
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FSHR [[A]], [[B]], [[C]]
+; CHECK: [[A:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[B:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[C:%[0-9]+]]:_(i32) = COPY $w2
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_FSHR [[A]], [[B]], [[C]]
; CHECK: $w0 = COPY [[RES]]
%res = call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
ret i32 %res
@@ -1494,12 +1496,12 @@ define void @test_lifetime_intrin_optnone() optnone noinline {
define void @test_load_store_atomics(ptr %addr) {
; CHECK-LABEL: name: test_load_store_atomics
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[V0:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load unordered (s8) from %ir.addr)
-; CHECK: G_STORE [[V0]](s8), [[ADDR]](p0) :: (store monotonic (s8) into %ir.addr)
-; CHECK: [[V1:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load acquire (s8) from %ir.addr)
-; CHECK: G_STORE [[V1]](s8), [[ADDR]](p0) :: (store release (s8) into %ir.addr)
-; CHECK: [[V2:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst (s8) from %ir.addr)
-; CHECK: G_STORE [[V2]](s8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic (s8) into %ir.addr)
+; CHECK: [[V0:%[0-9]+]]:_(i8) = G_LOAD [[ADDR]](p0) :: (load unordered (i8) from %ir.addr)
+; CHECK: G_STORE [[V0]](i8), [[ADDR]](p0) :: (store monotonic (i8) into %ir.addr)
+; CHECK: [[V1:%[0-9]+]]:_(i8) = G_LOAD [[ADDR]](p0) :: (load acquire (i8) from %ir.addr)
+; CHECK: G_STORE [[V1]](i8), [[ADDR]](p0) :: (store release (i8) into %ir.addr)
+; CHECK: [[V2:%[0-9]+]]:_(i8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst (i8) from %ir.addr)
+; CHECK: G_STORE [[V2]](i8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic (i8) into %ir.addr)
%v0 = load atomic i8, ptr %addr unordered, align 1
store atomic i8 %v0, ptr %addr monotonic, align 1
@@ -1514,36 +1516,36 @@ define void @test_load_store_atomics(ptr %addr) {
define float @test_fneg_f32(float %x) {
; CHECK-LABEL: name: test_fneg_f32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FNEG [[ARG]]
-; CHECK: $s0 = COPY [[RES]](s32)
+; CHECK: [[ARG:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = G_FNEG [[ARG]]
+; CHECK: $s0 = COPY [[RES]](f32)
%neg = fneg float %x
ret float %neg
}
define float @test_fneg_f32_fmf(float %x) {
; CHECK-LABEL: name: test_fneg_f32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
-; CHECK: $s0 = COPY [[RES]](s32)
+; CHECK: [[ARG:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[RES:%[0-9]+]]:_(f32) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
+; CHECK: $s0 = COPY [[RES]](f32)
%neg = fneg fast float %x
ret float %neg
}
define double @test_fneg_f64(double %x) {
; CHECK-LABEL: name: test_fneg_f64
-; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FNEG [[ARG]]
-; CHECK: $d0 = COPY [[RES]](s64)
+; CHECK: [[ARG:%[0-9]+]]:_(f64) = COPY $d0
+; CHECK: [[RES:%[0-9]+]]:_(f64) = G_FNEG [[ARG]]
+; CHECK: $d0 = COPY [[RES]](f64)
%neg = fneg double %x
ret double %neg
}
define double @test_fneg_f64_fmf(double %x) {
; CHECK-LABEL: name: test_fneg_f64
-; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
-; CHECK: $d0 = COPY [[RES]](s64)
+; CHECK: [[ARG:%[0-9]+]]:_(f64) = COPY $d0
+; CHECK: [[RES:%[0-9]+]]:_(f64) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
+; CHECK: $d0 = COPY [[RES]](f64)
%neg = fneg fast double %x
ret double %neg
}
@@ -1559,53 +1561,53 @@ define void @test_trivial_inlineasm() {
define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){
; CHECK-LABEL: name: test_insertelement
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[IDX2:%[0-9]+]]:_(s64) = G_ZEXT [[IDX]]
-; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX2]](s64)
-; CHECK: $d0 = COPY [[RES]](<2 x s32>)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[ELT:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[IDX:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[IDX2:%[0-9]+]]:_(i64) = G_ZEXT [[IDX]]
+; CHECK: [[RES:%[0-9]+]]:_(<2 x i32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](i32), [[IDX2]](i64)
+; CHECK: $d0 = COPY [[RES]](<2 x i32>)
%res = insertelement <2 x i32> %vec, i32 %elt, i32 %idx
ret <2 x i32> %res
}
define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) {
; CHECK-LABEL: name: test_extractelement
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[IDXEXT:%[0-9]+]]:_(s64) = G_ZEXT [[IDX]]
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDXEXT]](s64)
-; CHECK: $w0 = COPY [[RES]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[IDX:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[IDXEXT:%[0-9]+]]:_(i64) = G_ZEXT [[IDX]]
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x i32>), [[IDXEXT]](i64)
+; CHECK: $w0 = COPY [[RES]](i32)
%res = extractelement <2 x i32> %vec, i32 %idx
ret i32 %res
}
define i32 @test_extractelement_const_idx(<2 x i32> %vec) {
; CHECK-LABEL: name: test_extractelement
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)
-; CHECK: $w0 = COPY [[RES]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[IDX:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x i32>), [[IDX]](i64)
+; CHECK: $w0 = COPY [[RES]](i32)
%res = extractelement <2 x i32> %vec, i32 1
ret i32 %res
}
define i32 @test_extractelement_const_idx_zext_i1(<2 x i32> %vec) {
; CHECK-LABEL: name: test_extractelement
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)
-; CHECK: $w0 = COPY [[RES]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[IDX:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x i32>), [[IDX]](i64)
+; CHECK: $w0 = COPY [[RES]](i32)
%res = extractelement <2 x i32> %vec, i1 true
ret i32 %res
}
define i32 @test_extractelement_const_idx_zext_i8(<2 x i32> %vec) {
; CHECK-LABEL: name: test_extractelement
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)
-; CHECK: $w0 = COPY [[RES]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[IDX:%[0-9]+]]:_(i64) = G_CONSTANT i64 255
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x i32>), [[IDX]](i64)
+; CHECK: $w0 = COPY [[RES]](i32)
%res = extractelement <2 x i32> %vec, i8 255
ret i32 %res
}
@@ -1613,10 +1615,10 @@ define i32 @test_extractelement_const_idx_zext_i8(<2 x i32> %vec) {
define i32 @test_singleelementvector(i32 %elt){
; CHECK-LABEL: name: test_singleelementvector
-; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w0
+; CHECK: [[ELT:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NOT: G_INSERT_VECTOR_ELT
; CHECK-NOT: G_EXTRACT_VECTOR_ELT
-; CHECK: $w0 = COPY [[ELT]](s32)
+; CHECK: $w0 = COPY [[ELT]](i32)
%vec = insertelement <1 x i32> undef, i32 %elt, i32 0
%res = extractelement <1 x i32> %vec, i32 0
ret i32 %res
@@ -1624,75 +1626,75 @@ define i32 @test_singleelementvector(i32 %elt){
define <2 x i32> @test_constantaggzerovector_v2i32() {
; CHECK-LABEL: name: test_constantaggzerovector_v2i32
-; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ZERO]](s32), [[ZERO]](s32)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+; CHECK: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[ZERO]](i32), [[ZERO]](i32)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
ret <2 x i32> zeroinitializer
}
define <2 x float> @test_constantaggzerovector_v2f32() {
; CHECK-LABEL: name: test_constantaggzerovector_v2f32
-; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ZERO]](s32), [[ZERO]](s32)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+; CHECK: [[ZERO:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[ZERO]](f32), [[ZERO]](f32)
+; CHECK: $d0 = COPY [[VEC]](<2 x f32>)
ret <2 x float> zeroinitializer
}
define i32 @test_constantaggzerovector_v3i32() {
; CHECK-LABEL: name: test_constantaggzerovector_v3i32
-; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ZERO]](s32), [[ZERO]](s32), [[ZERO]](s32)
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
+; CHECK: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ZERO]](i32), [[ZERO]](i32), [[ZERO]](i32)
+; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x i32>)
%elt = extractelement <3 x i32> zeroinitializer, i32 1
ret i32 %elt
}
define <2 x i32> @test_constantdatavector_v2i32() {
; CHECK-LABEL: name: test_constantdatavector_v2i32
-; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+; CHECK: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C2]](i32)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
ret <2 x i32> <i32 1, i32 2>
}
define i32 @test_constantdatavector_v3i32() {
; CHECK-LABEL: name: test_constantdatavector_v3i32
-; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32), [[C3]](s32)
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
+; CHECK: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+; CHECK: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C2]](i32), [[C3]](i32)
+; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x i32>)
%elt = extractelement <3 x i32> <i32 1, i32 2, i32 3>, i32 1
ret i32 %elt
}
define <4 x i32> @test_constantdatavector_v4i32() {
; CHECK-LABEL: name: test_constantdatavector_v4i32
-; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
-; CHECK: $q0 = COPY [[VEC]](<4 x s32>)
+; CHECK: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+; CHECK: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+; CHECK: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C2]](i32), [[C3]](i32), [[C4]](i32)
+; CHECK: $q0 = COPY [[VEC]](<4 x i32>)
ret <4 x i32> <i32 1, i32 2, i32 3, i32 4>
}
define <2 x double> @test_constantdatavector_v2f64() {
; CHECK-LABEL: name: test_constantdatavector_v2f64
-; CHECK: [[FC1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
-; CHECK: [[FC2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FC1]](s64), [[FC2]](s64)
-; CHECK: $q0 = COPY [[VEC]](<2 x s64>)
+; CHECK: [[FC1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+; CHECK: [[FC2:%[0-9]+]]:_(f64) = G_FCONSTANT double 2.000000e+00
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FC1]](f64), [[FC2]](f64)
+; CHECK: $q0 = COPY [[VEC]](<2 x f64>)
ret <2 x double> <double 1.0, double 2.0>
}
-define i32 @test_constantaggzerovector_v1s32(i32 %arg){
-; CHECK-LABEL: name: test_constantaggzerovector_v1s32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+define i32 @test_constantaggzerovector_v1i32(i32 %arg){
+; CHECK-LABEL: name: test_constantaggzerovector_v1i32
+; CHECK: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[C0:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NOT: G_MERGE_VALUES
-; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C0]]
+; CHECK: [[COPY:%[0-9]+]]:_(i32) = COPY [[C0]]
; CHECK-NOT: G_MERGE_VALUES
; CHECK: G_ADD [[ARG]], [[COPY]]
%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
@@ -1701,18 +1703,18 @@ define i32 @test_constantaggzerovector_v1s32(i32 %arg){
ret i32 %res
}
-define i32 @test_constantdatavector_v1s32(i32 %arg){
-; CHECK-CV-LABEL: name: test_constantdatavector_v1s32
-; CHECK-CV: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-CV: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+define i32 @test_constantdatavector_v1i32(i32 %arg){
+; CHECK-CV-LABEL: name: test_constantdatavector_v1i32
+; CHECK-CV: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-CV: [[C0:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-CV-NOT: G_MERGE_VALUES
-; CHECK-CV: [[COPY:%[0-9]+]]:_(s32) = COPY [[C0]]
+; CHECK-CV: [[COPY:%[0-9]+]]:_(i32) = COPY [[C0]]
; CHECK-CV-NOT: G_MERGE_VALUES
; CHECK-CV: G_ADD [[ARG]], [[COPY]]
;
-; CHECK-CI-LABEL: name: test_constantdatavector_v1s32
-; CHECK-CI: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK-CI: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-CI-LABEL: name: test_constantdatavector_v1i32
+; CHECK-CI: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK-CI: [[C0:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-CI-NOT: G_MERGE_VALUES
; CHECK-CI: G_ADD [[ARG]], [[C0]]
%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
@@ -1724,111 +1726,111 @@ define i32 @test_constantdatavector_v1s32(i32 %arg){
declare ghccc float @different_call_conv_target(float %x)
define float @test_different_call_conv_target(float %x) {
; CHECK-LABEL: name: test_different_call_conv
-; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[X:%[0-9]+]]:_(f32) = COPY $s0
; CHECK: $s8 = COPY [[X]]
; CHECK: BL @different_call_conv_target, csr_aarch64_noregs, implicit-def $lr, implicit $sp, implicit $s8, implicit-def $s0
%res = call ghccc float @different_call_conv_target(float %x)
ret float %res
}
-define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
-; CHECK-LABEL: name: test_shufflevector_s32_v2s32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ARG]](s32), [[ARG]](s32)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+define <2 x i32> @test_shufflevector_i32_v2i32(i32 %arg) {
+; CHECK-LABEL: name: test_shufflevector_i32_v2i32
+; CHECK: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[ARG]](i32), [[ARG]](i32)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
%res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
ret <2 x i32> %res
}
-define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_s32
-; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[ARG]](<2 x s32>), [[IDX]](s64)
-; CHECK: $w0 = COPY [[RES]](s32)
+define i32 @test_shufflevector_v2i32_i32(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_i32
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[IDX:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[ARG]](<2 x i32>), [[IDX]](i64)
+; CHECK: $w0 = COPY [[RES]](i32)
%vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32> <i32 1>
%res = extractelement <1 x i32> %vec, i32 0
ret i32 %res
}
-define <2 x i32> @test_shufflevector_v2s32_v2s32_undef(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_undef
-; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(undef, undef)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+define <2 x i32> @test_shufflevector_v2i32_v2i32_undef(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_v2i32_undef
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(undef, undef)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
%res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> undef
ret <2 x i32> %res
}
-define <2 x i32> @test_shufflevector_v2s32_v2s32_undef_0(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_undef_0
-; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(undef, 0)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+define <2 x i32> @test_shufflevector_v2i32_v2i32_undef_0(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_v2i32_undef_0
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(undef, 0)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
%res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 undef, i32 0>
ret <2 x i32> %res
}
-define <2 x i32> @test_shufflevector_v2s32_v2s32_0_undef(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_0_undef
-; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(0, undef)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+define <2 x i32> @test_shufflevector_v2i32_v2i32_0_undef(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_v2i32_0_undef
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(0, undef)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
%res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 0, i32 undef>
ret <2 x i32> %res
}
-define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
-; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
-; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(1, 0, 1)
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
+define i32 @test_shufflevector_v2i32_v3i32(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_v3i32
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(1, 0, 1)
+; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x i32>)
%vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
%res = extractelement <3 x i32> %vec, i32 0
ret i32 %res
}
-define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
-; CHECK: [[ARG1:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-; CHECK: [[ARG2:%[0-9]+]]:_(<2 x s32>) = COPY $d1
-; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], shufflemask(0, 1, 2, 3)
-; CHECK: $q0 = COPY [[VEC]](<4 x s32>)
+define <4 x i32> @test_shufflevector_v2i32_v4i32(<2 x i32> %arg1, <2 x i32> %arg2) {
+; CHECK-LABEL: name: test_shufflevector_v2i32_v4i32
+; CHECK: [[ARG1:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+; CHECK: [[ARG2:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x i32>), [[ARG2]], shufflemask(0, 1, 2, 3)
+; CHECK: $q0 = COPY [[VEC]](<4 x i32>)
%res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x i32> %res
}
-define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
-; CHECK: [[ARG:%[0-9]+]]:_(<4 x s32>) = COPY $q0
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], shufflemask(1, 3)
-; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
+define <2 x i32> @test_shufflevector_v4i32_v2i32(<4 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v4i32_v2i32
+; CHECK: [[ARG:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x i32>), [[UNDEF]], shufflemask(1, 3)
+; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
%res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
ret <2 x i32> %res
}
-define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) {
-; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8
-; CHECK: [[ARG1:%[0-9]+]]:_(<8 x s8>) = COPY $d0
-; CHECK: [[ARG2:%[0-9]+]]:_(<8 x s8>) = COPY $d1
-; CHECK: [[VEC:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], shufflemask(0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15)
-; CHECK: $q0 = COPY [[VEC]](<16 x s8>)
+define <16 x i8> @test_shufflevector_v8i8_v16i8(<8 x i8> %arg1, <8 x i8> %arg2) {
+; CHECK-LABEL: name: test_shufflevector_v8i8_v16i8
+; CHECK: [[ARG1:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+; CHECK: [[ARG2:%[0-9]+]]:_(<8 x i8>) = COPY $d1
+; CHECK: [[VEC:%[0-9]+]]:_(<16 x i8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x i8>), [[ARG2]], shufflemask(0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15)
+; CHECK: $q0 = COPY [[VEC]](<16 x i8>)
%res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
ret <16 x i8> %res
}
; CHECK-LABEL: test_constant_vector
-; CHECK: [[UNDEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
-; CHECK: [[F:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
-; CHECK: [[M:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
-; CHECK: $d0 = COPY [[M]](<4 x s16>)
+; CHECK: [[UNDEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+; CHECK: [[F:%[0-9]+]]:_(f16) = G_FCONSTANT half 0xH3C00
+; CHECK: [[M:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UNDEF]](f16), [[UNDEF]](f16), [[UNDEF]](f16), [[F]](f16)
+; CHECK: $d0 = COPY [[M]](<4 x f16>)
define <4 x half> @test_constant_vector() {
ret <4 x half> <half undef, half undef, half undef, half 0xH3C00>
}
@@ -1836,8 +1838,8 @@ define <4 x half> @test_constant_vector() {
define i32 @test_target_mem_intrinsic(ptr %addr) {
; CHECK-LABEL: name: test_target_mem_intrinsic
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load (s32) from %ir.addr)
-; CHECK: G_TRUNC [[VAL]](s64)
+; CHECK: [[VAL:%[0-9]+]]:_(i64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load (i32) from %ir.addr)
+; CHECK: G_TRUNC [[VAL]](i64)
%val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i32) %addr)
%trunc = trunc i64 %val to i32
ret i32 %trunc
@@ -1861,22 +1863,22 @@ entry:
define i64 @test_phi_loop(i32 %n) {
; CHECK-LABEL: name: test_phi_loop
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
-; CHECK: [[CST1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[CST2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-
-; CHECK: [[PN1:%[0-9]+]]:_(s32) = G_PHI [[ARG1]](s32), %bb.1, [[SUB:%[0-9]+]](s32), %bb.2
-; CHECK: [[PN2:%[0-9]+]]:_(s64) = G_PHI [[CST3]](s64), %bb.1, [[PN3:%[0-9]+]](s64), %bb.2
-; CHECK: [[PN3]]:_(s64) = G_PHI [[CST4]](s64), %bb.1, [[ADD:%[0-9]+]](s64), %bb.2
-; CHECK: [[ADD]]:_(s64) = G_ADD [[PN2]], [[PN3]]
-; CHECK: [[SUB]]:_(s32) = G_SUB [[PN1]], [[CST1]]
-; CHECK: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[PN1]](s32), [[CST2]]
-; CHECK: G_BRCOND [[CMP]](s1), %bb.3
+; CHECK: [[ARG1:%[0-9]+]]:_(i32) = COPY $w0
+; CHECK: [[CST1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK: [[CST2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[CST4:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+
+; CHECK: [[PN1:%[0-9]+]]:_(i32) = G_PHI [[ARG1]](i32), %bb.1, [[SUB:%[0-9]+]](i32), %bb.2
+; CHECK: [[PN2:%[0-9]+]]:_(i64) = G_PHI [[CST3]](i64), %bb.1, [[PN3:%[0-9]+]](i64), %bb.2
+; CHECK: [[PN3]]:_(i64) = G_PHI [[CST4]](i64), %bb.1, [[ADD:%[0-9]+]](i64), %bb.2
+; CHECK: [[ADD]]:_(i64) = G_ADD [[PN2]], [[PN3]]
+; CHECK: [[SUB]]:_(i32) = G_SUB [[PN1]], [[CST1]]
+; CHECK: [[CMP:%[0-9]+]]:_(i1) = G_ICMP intpred(sle), [[PN1]](i32), [[CST2]]
+; CHECK: G_BRCOND [[CMP]](i1), %bb.3
; CHECK: G_BR %bb.2
-; CHECK: $x0 = COPY [[PN2]](s64)
+; CHECK: $x0 = COPY [[PN2]](i64)
; CHECK: RET_ReallyLR implicit $x0
entry:
br label %loop
@@ -1902,41 +1904,41 @@ define void @test_phi_diamond(ptr %a.ptr, ptr %b.ptr, i1 %selector, ptr %dst) {
; CHECK-LABEL: name: test_phi_diamond
; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ARG2:%[0-9]+]]:_(p0) = COPY $x1
-; CHECK: [[ARG3:%[0-9]+]]:_(s32) = COPY $w2
-; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[ARG3]]
+; CHECK: [[ARG3:%[0-9]+]]:_(i32) = COPY $w2
+; CHECK: [[TRUNC8:%[0-9]+]]:_(i8) = G_TRUNC [[ARG3]]
; CHECK: [[ARG4:%[0-9]+]]:_(p0) = COPY $x3
-; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC8]], 1
-; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNCASSERT]]
-; CHECK: G_BRCOND [[TRUNC]](s1), %bb.2
+; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TRUNC8]], 1
+; CHECK: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[TRUNCASSERT]]
+; CHECK: G_BRCOND [[TRUNC]](i1), %bb.2
; CHECK: G_BR %bb.3
-; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD [[ARG1]](p0) :: (load (s8) from %ir.a.ptr, align 4)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG1]], [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s16) = G_LOAD [[GEP1]](p0) :: (load (s16) from %ir.a.ptr + 2)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG1]], [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.a.ptr + 4)
+; CHECK: [[LD1:%[0-9]+]]:_(i8) = G_LOAD [[ARG1]](p0) :: (load (i8) from %ir.a.ptr, align 4)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG1]], [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i16) = G_LOAD [[GEP1]](p0) :: (load (i16) from %ir.a.ptr + 2)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG1]], [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i32) = G_LOAD [[GEP2]](p0) :: (load (i32) from %ir.a.ptr + 4)
; CHECK: G_BR %bb.4
-; CHECK: [[LD4:%[0-9]+]]:_(s8) = G_LOAD [[ARG2]](p0) :: (load (s8) from %ir.b.ptr, align 4)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG2]], [[CST3]](s64)
-; CHECK: [[LD5:%[0-9]+]]:_(s16) = G_LOAD [[GEP3]](p0) :: (load (s16) from %ir.b.ptr + 2)
-; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG2]], [[CST4]](s64)
-; CHECK: [[LD6:%[0-9]+]]:_(s32) = G_LOAD [[GEP4]](p0) :: (load (s32) from %ir.b.ptr + 4)
-
-; CHECK: [[PN1:%[0-9]+]]:_(s8) = G_PHI [[LD1]](s8), %bb.2, [[LD4]](s8), %bb.3
-; CHECK: [[PN2:%[0-9]+]]:_(s16) = G_PHI [[LD2]](s16), %bb.2, [[LD5]](s16), %bb.3
-; CHECK: [[PN3:%[0-9]+]]:_(s32) = G_PHI [[LD3]](s32), %bb.2, [[LD6]](s32), %bb.3
-; CHECK: G_STORE [[PN1]](s8), [[ARG4]](p0) :: (store (s8) into %ir.dst, align 4)
-; CHECK: [[CST5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
-; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG4]], [[CST5]](s64)
-; CHECK: G_STORE [[PN2]](s16), [[GEP5]](p0) :: (store (s16) into %ir.dst + 2)
-; CHECK: [[CST6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG4]], [[CST6]](s64)
-; CHECK: G_STORE [[PN3]](s32), [[GEP6]](p0) :: (store (s32) into %ir.dst + 4)
+; CHECK: [[LD4:%[0-9]+]]:_(i8) = G_LOAD [[ARG2]](p0) :: (load (i8) from %ir.b.ptr, align 4)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG2]], [[CST3]](i64)
+; CHECK: [[LD5:%[0-9]+]]:_(i16) = G_LOAD [[GEP3]](p0) :: (load (i16) from %ir.b.ptr + 2)
+; CHECK: [[CST4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG2]], [[CST4]](i64)
+; CHECK: [[LD6:%[0-9]+]]:_(i32) = G_LOAD [[GEP4]](p0) :: (load (i32) from %ir.b.ptr + 4)
+
+; CHECK: [[PN1:%[0-9]+]]:_(i8) = G_PHI [[LD1]](i8), %bb.2, [[LD4]](i8), %bb.3
+; CHECK: [[PN2:%[0-9]+]]:_(i16) = G_PHI [[LD2]](i16), %bb.2, [[LD5]](i16), %bb.3
+; CHECK: [[PN3:%[0-9]+]]:_(i32) = G_PHI [[LD3]](i32), %bb.2, [[LD6]](i32), %bb.3
+; CHECK: G_STORE [[PN1]](i8), [[ARG4]](p0) :: (store (i8) into %ir.dst, align 4)
+; CHECK: [[CST5:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG4]], [[CST5]](i64)
+; CHECK: G_STORE [[PN2]](i16), [[GEP5]](p0) :: (store (i16) into %ir.dst + 2)
+; CHECK: [[CST6:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG4]], [[CST6]](i64)
+; CHECK: G_STORE [[PN3]](i32), [[GEP6]](p0) :: (store (i32) into %ir.dst + 4)
; CHECK: RET_ReallyLR
entry:
@@ -1963,31 +1965,31 @@ join:
define void @test_nested_aggregate_const(ptr %ptr) {
; CHECK-LABEL: name: test_nested_aggregate_const
; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[CST1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[CST2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
-; CHECK: [[CST3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
-; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
-; CHECK: [[CST5:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[CST6:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
-; CHECK: G_STORE [[CST1]](s32), [[BASE]](p0) :: (store (s32) into %ir.ptr, align 8)
-; CHECK: [[CST7:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST7]](s64)
-; CHECK: G_STORE [[CST1]](s32), [[GEP1]](p0) :: (store (s32) into %ir.ptr + 4)
-; CHECK: [[CST8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST8]](s64)
-; CHECK: G_STORE [[CST2]](s16), [[GEP2]](p0) :: (store (s16) into %ir.ptr + 8, align 8)
-; CHECK: [[CST9:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST9]](s64)
-; CHECK: G_STORE [[CST3]](s8), [[GEP3]](p0) :: (store (s8) into %ir.ptr + 10, align 2)
-; CHECK: [[CST10:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST10]](s64)
-; CHECK: G_STORE [[CST4]](s64), [[GEP4]](p0) :: (store (s64) into %ir.ptr + 16)
-; CHECK: [[CST11:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
-; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST11]](s64)
-; CHECK: G_STORE [[CST5]](s64), [[GEP5]](p0) :: (store (s64) into %ir.ptr + 24)
-; CHECK: [[CST12:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
-; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST12]](s64)
-; CHECK: G_STORE [[CST6]](s32), [[GEP6]](p0) :: (store (s32) into %ir.ptr + 32, align 8)
+; CHECK: [[CST1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK: [[CST2:%[0-9]+]]:_(i16) = G_CONSTANT i16 2
+; CHECK: [[CST3:%[0-9]+]]:_(i8) = G_CONSTANT i8 3
+; CHECK: [[CST4:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+; CHECK: [[CST5:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[CST6:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+; CHECK: G_STORE [[CST1]](i32), [[BASE]](p0) :: (store (i32) into %ir.ptr, align 8)
+; CHECK: [[CST7:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST7]](i64)
+; CHECK: G_STORE [[CST1]](i32), [[GEP1]](p0) :: (store (i32) into %ir.ptr + 4)
+; CHECK: [[CST8:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST8]](i64)
+; CHECK: G_STORE [[CST2]](i16), [[GEP2]](p0) :: (store (i16) into %ir.ptr + 8, align 8)
+; CHECK: [[CST9:%[0-9]+]]:_(i64) = G_CONSTANT i64 10
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST9]](i64)
+; CHECK: G_STORE [[CST3]](i8), [[GEP3]](p0) :: (store (i8) into %ir.ptr + 10, align 2)
+; CHECK: [[CST10:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST10]](i64)
+; CHECK: G_STORE [[CST4]](i64), [[GEP4]](p0) :: (store (i64) into %ir.ptr + 16)
+; CHECK: [[CST11:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST11]](i64)
+; CHECK: G_STORE [[CST5]](i64), [[GEP5]](p0) :: (store (i64) into %ir.ptr + 24)
+; CHECK: [[CST12:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST12]](i64)
+; CHECK: G_STORE [[CST6]](i32), [[GEP6]](p0) :: (store (i32) into %ir.ptr + 32, align 8)
store %agg.nested { i32 1, i32 1, %agg.inner { i16 2, i8 3, %agg.inner.inner {i64 5, i64 8} }, i32 13}, ptr %ptr
ret void
}
@@ -1995,10 +1997,10 @@ define void @test_nested_aggregate_const(ptr %ptr) {
define i1 @return_i1_zext() {
; AAPCS ABI says that booleans can only be 1 or 0, so we need to zero-extend.
; CHECK-LABEL: name: return_i1_zext
-; CHECK: [[CST:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
-; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[CST]](s1)
-; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
-; CHECK: $w0 = COPY [[ANYEXT]](s32)
+; CHECK: [[CST:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+; CHECK: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[CST]](i1)
+; CHECK: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
+; CHECK: $w0 = COPY [[ANYEXT]](i32)
; CHECK: RET_ReallyLR implicit $w0
ret i1 true
}
@@ -2010,12 +2012,12 @@ define i32 @test_atomic_cmpxchg_1(ptr %addr) {
; CHECK-NEXT: successors: %bb.{{[^)]+}}
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK: bb.2.repeat:
; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
-; CHECK: [[OLDVALRES:%[0-9]+]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic (s32) on %ir.addr)
-; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK: [[OLDVALRES:%[0-9]+]]:_(i32), [[SUCCESS:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic (i32) on %ir.addr)
+; CHECK-NEXT: G_BRCOND [[SUCCESS]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK: bb.3.done:
entry:
@@ -2036,12 +2038,12 @@ define i32 @test_weak_atomic_cmpxchg_1(ptr %addr) {
; CHECK-NEXT: successors: %bb.{{[^)]+}}
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK: bb.2.repeat:
; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
-; CHECK: [[OLDVALRES:%[0-9]+]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic (s32) on %ir.addr)
-; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK: [[OLDVALRES:%[0-9]+]]:_(i32), [[SUCCESS:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic (i32) on %ir.addr)
+; CHECK-NEXT: G_BRCOND [[SUCCESS]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK: bb.3.done:
entry:
@@ -2062,12 +2064,12 @@ define i16 @test_atomic_cmpxchg_2(ptr %addr) {
; CHECK-NEXT: successors: %bb.2({{[^)]+}})
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
-; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(i16) = G_CONSTANT i16 0
+; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
; CHECK: bb.2.repeat:
; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
-; CHECK: [[OLDVALRES:%[0-9]+]]:_(s16), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (s16) on %ir.addr)
-; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK: [[OLDVALRES:%[0-9]+]]:_(i16), [[SUCCESS:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (i16) on %ir.addr)
+; CHECK-NEXT: G_BRCOND [[SUCCESS]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK: bb.3.done:
entry:
@@ -2088,12 +2090,12 @@ define i64 @test_atomic_cmpxchg_3(ptr %addr) {
; CHECK-NEXT: successors: %bb.2({{[^)]+}})
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK: bb.2.repeat:
; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
-; CHECK: [[OLDVALRES:%[0-9]+]]:_(s64), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst acquire (s64) on %ir.addr)
-; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK: [[OLDVALRES:%[0-9]+]]:_(i64), [[SUCCESS:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst acquire (i64) on %ir.addr)
+; CHECK-NEXT: G_BRCOND [[SUCCESS]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK: bb.3.done:
entry:
@@ -2113,8 +2115,8 @@ define i32 @test_atomicrmw_xchg(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_XCHG [[ADDR]](p0), [[VAL]] :: (load store monotonic (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_XCHG [[ADDR]](p0), [[VAL]] :: (load store monotonic (i32) on %ir.addr)
%oldval = atomicrmw xchg ptr %addr, i32 1 monotonic
ret i32 %oldval
}
@@ -2125,8 +2127,8 @@ define i32 @test_atomicrmw_add(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[ADDR]](p0), [[VAL]] :: (load store acquire (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_ADD [[ADDR]](p0), [[VAL]] :: (load store acquire (i32) on %ir.addr)
%oldval = atomicrmw add ptr %addr, i32 1 acquire
ret i32 %oldval
}
@@ -2137,8 +2139,8 @@ define i32 @test_atomicrmw_sub(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_SUB [[ADDR]](p0), [[VAL]] :: (load store release (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_SUB [[ADDR]](p0), [[VAL]] :: (load store release (i32) on %ir.addr)
%oldval = atomicrmw sub ptr %addr, i32 1 release
ret i32 %oldval
}
@@ -2149,8 +2151,8 @@ define i32 @test_atomicrmw_and(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[ADDR]](p0), [[VAL]] :: (load store acq_rel (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_AND [[ADDR]](p0), [[VAL]] :: (load store acq_rel (i32) on %ir.addr)
%oldval = atomicrmw and ptr %addr, i32 1 acq_rel
ret i32 %oldval
}
@@ -2163,16 +2165,16 @@ define i32 @test_atomicrmw_nand(ptr %addr) {
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[NEG1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
-; CHECK-NEXT: [[OLDVALSTART:%[0-9]+]]:_(s32) = G_LOAD [[ADDR]](p0) :: (load (s32) from %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[NEG1:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1
+; CHECK-NEXT: [[OLDVALSTART:%[0-9]+]]:_(i32) = G_LOAD [[ADDR]](p0) :: (load (i32) from %ir.addr)
; CHECK: bb.2.atomicrmw.start:
; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})
-; CHECK: [[OLDVAL:%[0-9]+]]:_(s32) = G_PHI [[OLDVALSTART]](s32), %bb.1, [[OLDVALRES:%[0-9]+]](s32), %bb.2
-; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[OLDVAL]], [[VAL]]
-; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s32) = G_XOR [[AND]], [[NEG1]]
-; CHECK: [[OLDVALRES]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (s32) on %ir.addr)
-; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.3
+; CHECK: [[OLDVAL:%[0-9]+]]:_(i32) = G_PHI [[OLDVALSTART]](i32), %bb.1, [[OLDVALRES:%[0-9]+]](i32), %bb.2
+; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[OLDVAL]], [[VAL]]
+; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(i32) = G_XOR [[AND]], [[NEG1]]
+; CHECK: [[OLDVALRES]]:_(i32), [[SUCCESS:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (i32) on %ir.addr)
+; CHECK-NEXT: G_BRCOND [[SUCCESS]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK: bb.3.atomicrmw.end:
%oldval = atomicrmw nand ptr %addr, i32 1 seq_cst
@@ -2185,8 +2187,8 @@ define i32 @test_atomicrmw_or(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_OR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_OR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw or ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2197,8 +2199,8 @@ define i32 @test_atomicrmw_xor(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_XOR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_XOR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw xor ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2209,8 +2211,8 @@ define i32 @test_atomicrmw_min(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_MIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_MIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw min ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2221,8 +2223,8 @@ define i32 @test_atomicrmw_max(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_MAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_MAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw max ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2233,8 +2235,8 @@ define i32 @test_atomicrmw_umin(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_UMIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_UMIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw umin ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2245,8 +2247,8 @@ define i32 @test_atomicrmw_umax(ptr %addr) {
; CHECK: bb.1 (%ir-block.{{[0-9]+}}):
; CHECK-NEXT: liveins: $x0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_UMAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)
+; CHECK-NEXT: [[VAL:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(i32) = G_ATOMICRMW_UMAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (i32) on %ir.addr)
%oldval = atomicrmw umax ptr %addr, i32 1 seq_cst
ret i32 %oldval
}
@@ -2279,7 +2281,7 @@ define void @test_invariant_intrin() {
declare float @llvm.ceil.f32(float)
define float @test_ceil_f32(float %x) {
; CHECK-LABEL: name: test_ceil_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FCEIL %{{[0-9]+}}
%y = call float @llvm.ceil.f32(float %x)
ret float %y
}
@@ -2287,7 +2289,7 @@ define float @test_ceil_f32(float %x) {
declare double @llvm.ceil.f64(double)
define double @test_ceil_f64(double %x) {
; CHECK-LABEL: name: test_ceil_f64
- ; CHECK: %{{[0-9]+}}:_(s64) = G_FCEIL %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f64) = G_FCEIL %{{[0-9]+}}
%y = call double @llvm.ceil.f64(double %x)
ret double %y
}
@@ -2295,7 +2297,7 @@ define double @test_ceil_f64(double %x) {
declare <2 x float> @llvm.ceil.v2f32(<2 x float>)
define <2 x float> @test_ceil_v2f32(<2 x float> %x) {
; CHECK-LABEL: name: test_ceil_v2f32
- ; CHECK: %{{[0-9]+}}:_(<2 x s32>) = G_FCEIL %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(<2 x f32>) = G_FCEIL %{{[0-9]+}}
%y = call <2 x float> @llvm.ceil.v2f32(<2 x float> %x)
ret <2 x float> %y
}
@@ -2303,7 +2305,7 @@ define <2 x float> @test_ceil_v2f32(<2 x float> %x) {
declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
define <4 x float> @test_ceil_v4f32(<4 x float> %x) {
; CHECK-LABEL: name: test_ceil_v4f32
- ; CHECK: %{{[0-9]+}}:_(<4 x s32>) = G_FCEIL %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(<4 x f32>) = G_FCEIL %{{[0-9]+}}
; SELECT: %{{[0-9]+}}:fpr128 = FRINTPv4f32 %{{[0-9]+}}
%y = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x)
ret <4 x float> %y
@@ -2312,7 +2314,7 @@ define <4 x float> @test_ceil_v4f32(<4 x float> %x) {
declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
define <2 x double> @test_ceil_v2f64(<2 x double> %x) {
; CHECK-LABEL: name: test_ceil_v2f64
- ; CHECK: %{{[0-9]+}}:_(<2 x s64>) = G_FCEIL %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(<2 x f64>) = G_FCEIL %{{[0-9]+}}
%y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x)
ret <2 x double> %y
}
@@ -2320,7 +2322,7 @@ define <2 x double> @test_ceil_v2f64(<2 x double> %x) {
declare float @llvm.cos.f32(float)
define float @test_cos_f32(float %x) {
; CHECK-LABEL: name: test_cos_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FCOS %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FCOS %{{[0-9]+}}
%y = call float @llvm.cos.f32(float %x)
ret float %y
}
@@ -2328,7 +2330,7 @@ define float @test_cos_f32(float %x) {
declare float @llvm.sin.f32(float)
define float @test_sin_f32(float %x) {
; CHECK-LABEL: name: test_sin_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSIN %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FSIN %{{[0-9]+}}
%y = call float @llvm.sin.f32(float %x)
ret float %y
}
@@ -2336,7 +2338,7 @@ define float @test_sin_f32(float %x) {
declare float @llvm.tan.f32(float)
define float @test_tan_f32(float %x) {
; CHECK-LABEL: name: test_tan_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FTAN %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FTAN %{{[0-9]+}}
%y = call float @llvm.tan.f32(float %x)
ret float %y
}
@@ -2344,7 +2346,7 @@ define float @test_tan_f32(float %x) {
declare float @llvm.acos.f32(float)
define float @test_acos_f32(float %x) {
; CHECK-LABEL: name: test_acos_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FACOS %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FACOS %{{[0-9]+}}
%y = call float @llvm.acos.f32(float %x)
ret float %y
}
@@ -2352,7 +2354,7 @@ define float @test_acos_f32(float %x) {
declare float @llvm.asin.f32(float)
define float @test_asin_f32(float %x) {
; CHECK-LABEL: name: test_asin_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FASIN %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FASIN %{{[0-9]+}}
%y = call float @llvm.asin.f32(float %x)
ret float %y
}
@@ -2360,7 +2362,7 @@ define float @test_asin_f32(float %x) {
declare float @llvm.atan.f32(float)
define float @test_atan_f32(float %x) {
; CHECK-LABEL: name: test_atan_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FATAN %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FATAN %{{[0-9]+}}
%y = call float @llvm.atan.f32(float %x)
ret float %y
}
@@ -2368,7 +2370,7 @@ define float @test_atan_f32(float %x) {
declare float @llvm.atan2.f32(float, float)
define float @test_atan2_f32(float %x, float %y) {
; CHECK-LABEL: name: test_atan2_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FATAN2 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FATAN2 %{{[0-9]+}}
%z = call float @llvm.atan2.f32(float %x, float %y)
ret float %z
}
@@ -2376,7 +2378,7 @@ define float @test_atan2_f32(float %x, float %y) {
declare float @llvm.cosh.f32(float)
define float @test_cosh_f32(float %x) {
; CHECK-LABEL: name: test_cosh_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FCOSH %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FCOSH %{{[0-9]+}}
%y = call float @llvm.cosh.f32(float %x)
ret float %y
}
@@ -2384,7 +2386,7 @@ define float @test_cosh_f32(float %x) {
declare float @llvm.sinh.f32(float)
define float @test_sinh_f32(float %x) {
; CHECK-LABEL: name: test_sinh_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSINH %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FSINH %{{[0-9]+}}
%y = call float @llvm.sinh.f32(float %x)
ret float %y
}
@@ -2392,7 +2394,7 @@ define float @test_sinh_f32(float %x) {
declare float @llvm.tanh.f32(float)
define float @test_tanh_f32(float %x) {
; CHECK-LABEL: name: test_tanh_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FTANH %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FTANH %{{[0-9]+}}
%y = call float @llvm.tanh.f32(float %x)
ret float %y
}
@@ -2400,7 +2402,7 @@ define float @test_tanh_f32(float %x) {
declare float @llvm.sqrt.f32(float)
define float @test_sqrt_f32(float %x) {
; CHECK-LABEL: name: test_sqrt_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FSQRT %{{[0-9]+}}
%y = call float @llvm.sqrt.f32(float %x)
ret float %y
}
@@ -2408,7 +2410,7 @@ define float @test_sqrt_f32(float %x) {
declare float @llvm.floor.f32(float)
define float @test_floor_f32(float %x) {
; CHECK-LABEL: name: test_floor_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FFLOOR %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FFLOOR %{{[0-9]+}}
%y = call float @llvm.floor.f32(float %x)
ret float %y
}
@@ -2416,13 +2418,13 @@ define float @test_floor_f32(float %x) {
declare float @llvm.nearbyint.f32(float)
define float @test_nearbyint_f32(float %x) {
; CHECK-LABEL: name: test_nearbyint_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FNEARBYINT %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FNEARBYINT %{{[0-9]+}}
%y = call float @llvm.nearbyint.f32(float %x)
ret float %y
}
; CHECK-LABEL: name: test_llvm.aarch64.neon.ld3.v4i32.p0i32
-; CHECK: %1:_(<4 x s32>), %2:_(<4 x s32>), %3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load (s384) from %ir.ptr, align 64)
+; CHECK: %1:_(<4 x i32>), %2:_(<4 x i32>), %3:_(<4 x i32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load (s384) from %ir.ptr, align 64)
define void @test_llvm.aarch64.neon.ld3.v4i32.p0i32(ptr %ptr) {
%arst = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %ptr)
ret void
@@ -2432,10 +2434,10 @@ declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr)
define void @test_i1_arg_zext(ptr %f) {
; CHECK-LABEL: name: test_i1_arg_zext
-; CHECK: [[I1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
-; CHECK: [[ZEXT0:%[0-9]+]]:_(s8) = G_ZEXT [[I1]](s1)
-; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT0]](s8)
-; CHECK: $w0 = COPY [[ZEXT1]](s32)
+; CHECK: [[I1:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+; CHECK: [[ZEXT0:%[0-9]+]]:_(i8) = G_ZEXT [[I1]](i1)
+; CHECK: [[ZEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT0]](i8)
+; CHECK: $w0 = COPY [[ZEXT1]](i32)
call void %f(i1 true)
ret void
}
@@ -2455,7 +2457,7 @@ define void @test_stacksaverestore() {
declare float @llvm.rint.f32(float)
define float @test_rint_f32(float %x) {
; CHECK-LABEL: name: test_rint_f32
- ; CHECK: %{{[0-9]+}}:_(s32) = G_FRINT %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:_(f32) = G_FRINT %{{[0-9]+}}
%y = call float @llvm.rint.f32(float %x)
ret float %y
}
@@ -2504,7 +2506,7 @@ define void @test_var_annotation(ptr, ptr, ptr, i32) {
declare i64 @llvm.readcyclecounter()
define i64 @test_readcyclecounter() {
; CHECK-LABEL: name: test_readcyclecounter
- ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_READCYCLECOUNTER{{$}}
+ ; CHECK: [[RES:%[0-9]+]]:_(i64) = G_READCYCLECOUNTER{{$}}
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = call i64 @llvm.readcyclecounter()
@@ -2513,8 +2515,8 @@ define i64 @test_readcyclecounter() {
define i64 @test_freeze(i64 %a) {
; CHECK-LABEL: name: test_freeze
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]
+ ; CHECK: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[RES:%[0-9]+]]:_(i64) = G_FREEZE [[COPY]]
; CHECK-NEXT: $x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = freeze i64 %a
@@ -2524,13 +2526,13 @@ define i64 @test_freeze(i64 %a) {
define {i8, i32} @test_freeze_struct(ptr %addr) {
; CHECK-LABEL: name: test_freeze_struct
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]]
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[LOAD]]
- ; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(s32) = G_FREEZE [[LOAD1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE]]
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(i8) = G_FREEZE [[LOAD]]
+ ; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(i32) = G_FREEZE [[LOAD1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FREEZE]]
; CHECK-NEXT: $w0 = COPY [[ANYEXT]]
; CHECK-NEXT: $w1 = COPY [[FREEZE1]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
@@ -2546,9 +2548,9 @@ define i64 @lround(float %x) {
; CHECK-LABEL: name: lround
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $s0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[LROUND:%[0-9]+]]:_(s64) = G_LROUND [[COPY]](s32)
- ; CHECK: $x0 = COPY [[LROUND]](s64)
+ ; CHECK: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK: [[LROUND:%[0-9]+]]:_(i64) = G_LROUND [[COPY]](f32)
+ ; CHECK: $x0 = COPY [[LROUND]](i64)
; CHECK: RET_ReallyLR implicit $x0
%lround = tail call i64 @llvm.lround.i64.f32(float %x)
ret i64 %lround
@@ -2559,9 +2561,9 @@ define i64 @llround(float %x) {
; CHECK-LABEL: name: llround
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $s0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[LLROUND:%[0-9]+]]:_(s64) = G_LLROUND [[COPY]](s32)
- ; CHECK: $x0 = COPY [[LLROUND]](s64)
+ ; CHECK: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK: [[LLROUND:%[0-9]+]]:_(i64) = G_LLROUND [[COPY]](f32)
+ ; CHECK: $x0 = COPY [[LLROUND]](i64)
; CHECK: RET_ReallyLR implicit $x0
%lround = tail call i64 @llvm.llround.i64.f32(float %x)
ret i64 %lround
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
index 98840bb4b68e2..d48077c606e04 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
@@ -12,7 +12,7 @@ define i32 @val_compare_and_swap(ptr %p, i32 %cmp, i32 %new) {
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -20,7 +20,7 @@ define i32 @val_compare_and_swap(ptr %p, i32 %cmp, i32 %new) {
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STXRW renamable $w2, renamable $x0, pcsections !0 :: (volatile store (s32) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STXRW renamable $w2, renamable $x0, pcsections !0 :: (volatile store (i32) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -46,13 +46,13 @@ define i32 @val_compare_and_swap_from_load(ptr %p, i32 %cmp, ptr %pnew) {
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $w1, $x0, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w9 = LDRWui killed renamable $x2, 0, implicit-def $x9, pcsections !0 :: (load (s32) from %ir.pnew)
+ ; CHECK-NEXT: renamable $w9 = LDRWui killed renamable $x2, 0, implicit-def $x9, pcsections !0 :: (load (i32) from %ir.pnew)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.cmpxchg.start:
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $w1, $x0, $x9
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -60,7 +60,7 @@ define i32 @val_compare_and_swap_from_load(ptr %p, i32 %cmp, ptr %pnew) {
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $x0, $x8, $x9
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRW renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s32) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRW renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i32) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -91,7 +91,7 @@ define i32 @val_compare_and_swap_rel(ptr %p, i32 %cmp, i32 %new) {
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -99,7 +99,7 @@ define i32 @val_compare_and_swap_rel(ptr %p, i32 %cmp, i32 %new) {
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STLXRW renamable $w2, renamable $x0, pcsections !0 :: (volatile store (s32) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STLXRW renamable $w2, renamable $x0, pcsections !0 :: (volatile store (i32) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -129,7 +129,7 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) {
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDXRX renamable $x0, pcsections !0 :: (volatile load (s64) from %ir.p)
+ ; CHECK-NEXT: renamable $x8 = LDXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: $xzr = SUBSXrs renamable $x8, renamable $x1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -137,7 +137,7 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) {
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (s64) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (i64) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -167,7 +167,7 @@ define i64 @val_compare_and_swap_64_monotonic_seqcst(ptr %p, i64 %cmp, i64 %new)
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (s64) from %ir.p)
+ ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: $xzr = SUBSXrs renamable $x8, renamable $x1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -175,7 +175,7 @@ define i64 @val_compare_and_swap_64_monotonic_seqcst(ptr %p, i64 %cmp, i64 %new)
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STLXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (s64) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STLXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (i64) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -205,7 +205,7 @@ define i64 @val_compare_and_swap_64_release_acquire(ptr %p, i64 %cmp, i64 %new)
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (s64) from %ir.p)
+ ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: $xzr = SUBSXrs renamable $x8, renamable $x1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -213,7 +213,7 @@ define i64 @val_compare_and_swap_64_release_acquire(ptr %p, i64 %cmp, i64 %new)
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STLXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (s64) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STLXRX renamable $x2, renamable $x0, pcsections !0 :: (volatile store (i64) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
@@ -243,10 +243,10 @@ define i32 @fetch_and_nand(ptr %p) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w8 = LDXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w8, 2, pcsections !0
; CHECK-NEXT: $w9 = ORNWrs $wzr, killed renamable $w9, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRW killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s32) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRW killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i32) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -268,10 +268,10 @@ define i64 @fetch_and_nand_64(ptr %p) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (s64) from %ir.p)
+ ; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: renamable $x9 = ANDXri renamable $x8, 4098, pcsections !0
; CHECK-NEXT: $x9 = ORNXrs $xzr, killed renamable $x9, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRX killed renamable $x9, renamable $x0, pcsections !0 :: (volatile store (s64) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRX killed renamable $x9, renamable $x0, pcsections !0 :: (volatile store (i64) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -295,9 +295,9 @@ define i32 @fetch_and_or(ptr %p) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $w10 = ORRWrs renamable $w8, renamable $w9, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w11 = STLXRW killed renamable $w10, renamable $x0, pcsections !0 :: (volatile store (s32) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w11 = STLXRW killed renamable $w10, renamable $x0, pcsections !0 :: (volatile store (i32) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -319,9 +319,9 @@ define i64 @fetch_and_or_64(ptr %p) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDXRX renamable $x0, pcsections !0 :: (volatile load (s64) from %ir.p)
+ ; CHECK-NEXT: renamable $x8 = LDXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: renamable $x9 = ORRXri renamable $x8, 4098, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRX killed renamable $x9, renamable $x0, pcsections !0 :: (volatile store (s64) into %ir.p)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRX killed renamable $x9, renamable $x0, pcsections !0 :: (volatile store (i64) into %ir.p)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -365,7 +365,7 @@ define i32 @atomic_load(ptr %p) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (s32) from %ir.p)
+ ; CHECK-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (i32) from %ir.p)
; CHECK-NEXT: RET undef $lr, implicit $w0
%r = load atomic i32, ptr %p seq_cst, align 4, !pcsections !0
ret i32 %r
@@ -376,13 +376,13 @@ define i8 @atomic_load_relaxed_8(ptr %p, i32 %off32) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDRBBui renamable $x0, 4095, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unsigned)
- ; CHECK-NEXT: renamable $w9 = LDRBBroW renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_regoff)
- ; CHECK-NEXT: renamable $w10 = LDURBBi renamable $x0, -256, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unscaled)
+ ; CHECK-NEXT: renamable $w8 = LDRBBui renamable $x0, 4095, pcsections !0 :: (load monotonic (i8) from %ir.ptr_unsigned)
+ ; CHECK-NEXT: renamable $w9 = LDRBBroW renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (load unordered (i8) from %ir.ptr_regoff)
+ ; CHECK-NEXT: renamable $w10 = LDURBBi renamable $x0, -256, pcsections !0 :: (load monotonic (i8) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w9, killed renamable $w8, 0, pcsections !0
; CHECK-NEXT: renamable $x9 = ADDXri killed renamable $x0, 291, 12
; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w8, killed renamable $w10, 0, pcsections !0
- ; CHECK-NEXT: renamable $w9 = LDRBBui killed renamable $x9, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_random)
+ ; CHECK-NEXT: renamable $w9 = LDRBBui killed renamable $x9, 0, pcsections !0 :: (load unordered (i8) from %ir.ptr_random)
; CHECK-NEXT: renamable $w0 = ADDWrx killed renamable $w8, killed renamable $w9, 0, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $w0
%ptr_unsigned = getelementptr i8, ptr %p, i32 4095
@@ -408,13 +408,13 @@ define i16 @atomic_load_relaxed_16(ptr %p, i32 %off32) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDRHHui renamable $x0, 4095, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unsigned)
- ; CHECK-NEXT: renamable $w9 = LDRHHroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s16) from %ir.ptr_regoff)
- ; CHECK-NEXT: renamable $w10 = LDURHHi renamable $x0, -256, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unscaled)
+ ; CHECK-NEXT: renamable $w8 = LDRHHui renamable $x0, 4095, pcsections !0 :: (load monotonic (i16) from %ir.ptr_unsigned)
+ ; CHECK-NEXT: renamable $w9 = LDRHHroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (i16) from %ir.ptr_regoff)
+ ; CHECK-NEXT: renamable $w10 = LDURHHi renamable $x0, -256, pcsections !0 :: (load monotonic (i16) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w9, killed renamable $w8, 8, pcsections !0
; CHECK-NEXT: renamable $x9 = ADDXri killed renamable $x0, 291, 12
; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w8, killed renamable $w10, 8, pcsections !0
- ; CHECK-NEXT: renamable $w9 = LDRHHui killed renamable $x9, 0, pcsections !0 :: (load unordered (s16) from %ir.ptr_random)
+ ; CHECK-NEXT: renamable $w9 = LDRHHui killed renamable $x9, 0, pcsections !0 :: (load unordered (i16) from %ir.ptr_random)
; CHECK-NEXT: renamable $w0 = ADDWrx killed renamable $w8, killed renamable $w9, 8, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $w0
%ptr_unsigned = getelementptr i16, ptr %p, i32 4095
@@ -440,12 +440,12 @@ define i32 @atomic_load_relaxed_32(ptr %p, i32 %off32) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDRWui renamable $x0, 4095, pcsections !0 :: (load monotonic (s32) from %ir.ptr_unsigned)
- ; CHECK-NEXT: renamable $w9 = LDRWroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s32) from %ir.ptr_regoff)
- ; CHECK-NEXT: renamable $w10 = LDURWi renamable $x0, -256, pcsections !0 :: (load monotonic (s32) from %ir.ptr_unscaled)
+ ; CHECK-NEXT: renamable $w8 = LDRWui renamable $x0, 4095, pcsections !0 :: (load monotonic (i32) from %ir.ptr_unsigned)
+ ; CHECK-NEXT: renamable $w9 = LDRWroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (i32) from %ir.ptr_regoff)
+ ; CHECK-NEXT: renamable $w10 = LDURWi renamable $x0, -256, pcsections !0 :: (load monotonic (i32) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x11 = ADDXri killed renamable $x0, 291, 12
; CHECK-NEXT: $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0, pcsections !0
- ; CHECK-NEXT: renamable $w9 = LDRWui killed renamable $x11, 0, pcsections !0 :: (load unordered (s32) from %ir.ptr_random)
+ ; CHECK-NEXT: renamable $w9 = LDRWui killed renamable $x11, 0, pcsections !0 :: (load unordered (i32) from %ir.ptr_random)
; CHECK-NEXT: $w8 = ADDWrs killed renamable $w8, killed renamable $w10, 0, pcsections !0
; CHECK-NEXT: $w0 = ADDWrs killed renamable $w8, killed renamable $w9, 0, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $w0
@@ -472,12 +472,12 @@ define i64 @atomic_load_relaxed_64(ptr %p, i32 %off32) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x8 = LDRXui renamable $x0, 4095, pcsections !0 :: (load monotonic (s64) from %ir.ptr_unsigned)
- ; CHECK-NEXT: renamable $x9 = LDRXroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s64) from %ir.ptr_regoff)
- ; CHECK-NEXT: renamable $x10 = LDURXi renamable $x0, -256, pcsections !0 :: (load monotonic (s64) from %ir.ptr_unscaled)
+ ; CHECK-NEXT: renamable $x8 = LDRXui renamable $x0, 4095, pcsections !0 :: (load monotonic (i64) from %ir.ptr_unsigned)
+ ; CHECK-NEXT: renamable $x9 = LDRXroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (i64) from %ir.ptr_regoff)
+ ; CHECK-NEXT: renamable $x10 = LDURXi renamable $x0, -256, pcsections !0 :: (load monotonic (i64) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x11 = ADDXri killed renamable $x0, 291, 12
; CHECK-NEXT: $x8 = ADDXrs killed renamable $x8, killed renamable $x9, 0, pcsections !0
- ; CHECK-NEXT: renamable $x9 = LDRXui killed renamable $x11, 0, pcsections !0 :: (load unordered (s64) from %ir.ptr_random)
+ ; CHECK-NEXT: renamable $x9 = LDRXui killed renamable $x11, 0, pcsections !0 :: (load unordered (i64) from %ir.ptr_random)
; CHECK-NEXT: $x8 = ADDXrs killed renamable $x8, killed renamable $x10, 0, pcsections !0
; CHECK-NEXT: $x0 = ADDXrs killed renamable $x8, killed renamable $x9, 0, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $x0
@@ -506,7 +506,7 @@ define void @atomc_store(ptr %p) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w8 = MOVZWi 4, 0
- ; CHECK-NEXT: STLRW killed renamable $w8, killed renamable $x0, pcsections !0 :: (store seq_cst (s32) into %ir.p)
+ ; CHECK-NEXT: STLRW killed renamable $w8, killed renamable $x0, pcsections !0 :: (store seq_cst (i32) into %ir.p)
; CHECK-NEXT: RET undef $lr
store atomic i32 4, ptr %p seq_cst, align 4, !pcsections !0
ret void
@@ -517,11 +517,11 @@ define void @atomic_store_relaxed_8(ptr %p, i32 %off32, i8 %val) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRBBui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (s8) into %ir.ptr_unsigned)
- ; CHECK-NEXT: STRBBroW renamable $w2, renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (store unordered (s8) into %ir.ptr_regoff)
- ; CHECK-NEXT: STURBBi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (s8) into %ir.ptr_unscaled)
+ ; CHECK-NEXT: STRBBui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (i8) into %ir.ptr_unsigned)
+ ; CHECK-NEXT: STRBBroW renamable $w2, renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (store unordered (i8) into %ir.ptr_regoff)
+ ; CHECK-NEXT: STURBBi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (i8) into %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x8 = ADDXri killed renamable $x0, 291, 12
- ; CHECK-NEXT: STRBBui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (s8) into %ir.ptr_random)
+ ; CHECK-NEXT: STRBBui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (i8) into %ir.ptr_random)
; CHECK-NEXT: RET undef $lr
%ptr_unsigned = getelementptr i8, ptr %p, i32 4095
store atomic i8 %val, ptr %ptr_unsigned monotonic, align 1, !pcsections !0
@@ -543,11 +543,11 @@ define void @atomic_store_relaxed_16(ptr %p, i32 %off32, i16 %val) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRHHui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (s16) into %ir.ptr_unsigned)
- ; CHECK-NEXT: STRHHroW renamable $w2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (s16) into %ir.ptr_regoff)
- ; CHECK-NEXT: STURHHi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (s16) into %ir.ptr_unscaled)
+ ; CHECK-NEXT: STRHHui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (i16) into %ir.ptr_unsigned)
+ ; CHECK-NEXT: STRHHroW renamable $w2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (i16) into %ir.ptr_regoff)
+ ; CHECK-NEXT: STURHHi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (i16) into %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x8 = ADDXri killed renamable $x0, 291, 12
- ; CHECK-NEXT: STRHHui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (s16) into %ir.ptr_random)
+ ; CHECK-NEXT: STRHHui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (i16) into %ir.ptr_random)
; CHECK-NEXT: RET undef $lr
%ptr_unsigned = getelementptr i16, ptr %p, i32 4095
store atomic i16 %val, ptr %ptr_unsigned monotonic, align 2, !pcsections !0
@@ -569,11 +569,11 @@ define void @atomic_store_relaxed_32(ptr %p, i32 %off32, i32 %val) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRWui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (s32) into %ir.ptr_unsigned)
- ; CHECK-NEXT: STRWroW renamable $w2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (s32) into %ir.ptr_regoff)
- ; CHECK-NEXT: STURWi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (s32) into %ir.ptr_unscaled)
+ ; CHECK-NEXT: STRWui renamable $w2, renamable $x0, 4095, pcsections !0 :: (store monotonic (i32) into %ir.ptr_unsigned)
+ ; CHECK-NEXT: STRWroW renamable $w2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (i32) into %ir.ptr_regoff)
+ ; CHECK-NEXT: STURWi renamable $w2, renamable $x0, -256, pcsections !0 :: (store monotonic (i32) into %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x8 = ADDXri killed renamable $x0, 291, 12
- ; CHECK-NEXT: STRWui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (s32) into %ir.ptr_random)
+ ; CHECK-NEXT: STRWui killed renamable $w2, killed renamable $x8, 0, pcsections !0 :: (store unordered (i32) into %ir.ptr_random)
; CHECK-NEXT: RET undef $lr
%ptr_unsigned = getelementptr i32, ptr %p, i32 4095
store atomic i32 %val, ptr %ptr_unsigned monotonic, align 4, !pcsections !0
@@ -595,11 +595,11 @@ define void @atomic_store_relaxed_64(ptr %p, i32 %off32, i64 %val) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w1, $x0, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui renamable $x2, renamable $x0, 4095, pcsections !0 :: (store monotonic (s64) into %ir.ptr_unsigned)
- ; CHECK-NEXT: STRXroW renamable $x2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (s64) into %ir.ptr_regoff)
- ; CHECK-NEXT: STURXi renamable $x2, renamable $x0, -256, pcsections !0 :: (store monotonic (s64) into %ir.ptr_unscaled)
+ ; CHECK-NEXT: STRXui renamable $x2, renamable $x0, 4095, pcsections !0 :: (store monotonic (i64) into %ir.ptr_unsigned)
+ ; CHECK-NEXT: STRXroW renamable $x2, renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (store unordered (i64) into %ir.ptr_regoff)
+ ; CHECK-NEXT: STURXi renamable $x2, renamable $x0, -256, pcsections !0 :: (store monotonic (i64) into %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x8 = ADDXri killed renamable $x0, 291, 12
- ; CHECK-NEXT: STRXui killed renamable $x2, killed renamable $x8, 0, pcsections !0 :: (store unordered (s64) into %ir.ptr_random)
+ ; CHECK-NEXT: STRXui killed renamable $x2, killed renamable $x8, 0, pcsections !0 :: (store unordered (i64) into %ir.ptr_random)
; CHECK-NEXT: RET undef $lr
%ptr_unsigned = getelementptr i64, ptr %p, i32 4095
store atomic i64 %val, ptr %ptr_unsigned monotonic, align 8, !pcsections !0
@@ -621,8 +621,8 @@ define i32 @load_zext(ptr %p8, ptr %p16) {
; CHECK-NOLSE: bb.0 (%ir-block.0):
; CHECK-NOLSE-NEXT: liveins: $x0, $x1
; CHECK-NOLSE-NEXT: {{ $}}
- ; CHECK-NOLSE-NEXT: renamable $w8 = LDARB killed renamable $x0, pcsections !0 :: (load acquire (s8) from %ir.p8)
- ; CHECK-NOLSE-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (s16) from %ir.p16)
+ ; CHECK-NOLSE-NEXT: renamable $w8 = LDARB killed renamable $x0, pcsections !0 :: (load acquire (i8) from %ir.p8)
+ ; CHECK-NOLSE-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (i16) from %ir.p16)
; CHECK-NOLSE-NEXT: renamable $w9 = UBFMWri killed renamable $w9, 0, 15
; CHECK-NOLSE-NEXT: renamable $w0 = ADDWrx killed renamable $w9, killed renamable $w8, 0, pcsections !0
; CHECK-NOLSE-NEXT: RET undef $lr, implicit $w0
@@ -631,8 +631,8 @@ define i32 @load_zext(ptr %p8, ptr %p16) {
; CHECK-LDAPR: bb.0 (%ir-block.0):
; CHECK-LDAPR-NEXT: liveins: $x0, $x1
; CHECK-LDAPR-NEXT: {{ $}}
- ; CHECK-LDAPR-NEXT: renamable $w8 = LDAPRB killed renamable $x0, pcsections !0 :: (load acquire (s8) from %ir.p8)
- ; CHECK-LDAPR-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (s16) from %ir.p16)
+ ; CHECK-LDAPR-NEXT: renamable $w8 = LDAPRB killed renamable $x0, pcsections !0 :: (load acquire (i8) from %ir.p8)
+ ; CHECK-LDAPR-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (i16) from %ir.p16)
; CHECK-LDAPR-NEXT: renamable $w9 = UBFMWri killed renamable $w9, 0, 15
; CHECK-LDAPR-NEXT: renamable $w0 = ADDWrx killed renamable $w9, killed renamable $w8, 0, pcsections !0
; CHECK-LDAPR-NEXT: RET undef $lr, implicit $w0
@@ -651,16 +651,16 @@ define { i32, i64 } @load_acq(ptr %p32, ptr %p64) {
; CHECK-NOLSE: bb.0 (%ir-block.0):
; CHECK-NOLSE-NEXT: liveins: $x0, $x1
; CHECK-NOLSE-NEXT: {{ $}}
- ; CHECK-NOLSE-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (s32) from %ir.p32)
- ; CHECK-NOLSE-NEXT: renamable $x1 = LDARX killed renamable $x1, pcsections !0 :: (load acquire (s64) from %ir.p64)
+ ; CHECK-NOLSE-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (i32) from %ir.p32)
+ ; CHECK-NOLSE-NEXT: renamable $x1 = LDARX killed renamable $x1, pcsections !0 :: (load acquire (i64) from %ir.p64)
; CHECK-NOLSE-NEXT: RET undef $lr, implicit $w0, implicit $x1
;
; CHECK-LDAPR-LABEL: name: load_acq
; CHECK-LDAPR: bb.0 (%ir-block.0):
; CHECK-LDAPR-NEXT: liveins: $x0, $x1
; CHECK-LDAPR-NEXT: {{ $}}
- ; CHECK-LDAPR-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (s32) from %ir.p32)
- ; CHECK-LDAPR-NEXT: renamable $x1 = LDAPRX killed renamable $x1, pcsections !0 :: (load acquire (s64) from %ir.p64)
+ ; CHECK-LDAPR-NEXT: renamable $w0 = LDARW killed renamable $x0, pcsections !0 :: (load seq_cst (i32) from %ir.p32)
+ ; CHECK-LDAPR-NEXT: renamable $x1 = LDAPRX killed renamable $x1, pcsections !0 :: (load acquire (i64) from %ir.p64)
; CHECK-LDAPR-NEXT: RET undef $lr, implicit $w0, implicit $x1
%val32 = load atomic i32, ptr %p32 seq_cst, align 4, !pcsections !0
%tmp = insertvalue { i32, i64 } undef, i32 %val32, 0
@@ -676,8 +676,8 @@ define i32 @load_sext(ptr %p8, ptr %p16) {
; CHECK-NOLSE: bb.0 (%ir-block.0):
; CHECK-NOLSE-NEXT: liveins: $x0, $x1
; CHECK-NOLSE-NEXT: {{ $}}
- ; CHECK-NOLSE-NEXT: renamable $w8 = LDARB killed renamable $x0, pcsections !0 :: (load acquire (s8) from %ir.p8)
- ; CHECK-NOLSE-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (s16) from %ir.p16)
+ ; CHECK-NOLSE-NEXT: renamable $w8 = LDARB killed renamable $x0, pcsections !0 :: (load acquire (i8) from %ir.p8)
+ ; CHECK-NOLSE-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (i16) from %ir.p16)
; CHECK-NOLSE-NEXT: renamable $w9 = SBFMWri killed renamable $w9, 0, 15
; CHECK-NOLSE-NEXT: renamable $w0 = ADDWrx killed renamable $w9, killed renamable $w8, 32, pcsections !0
; CHECK-NOLSE-NEXT: RET undef $lr, implicit $w0
@@ -686,8 +686,8 @@ define i32 @load_sext(ptr %p8, ptr %p16) {
; CHECK-LDAPR: bb.0 (%ir-block.0):
; CHECK-LDAPR-NEXT: liveins: $x0, $x1
; CHECK-LDAPR-NEXT: {{ $}}
- ; CHECK-LDAPR-NEXT: renamable $w8 = LDAPRB killed renamable $x0, pcsections !0 :: (load acquire (s8) from %ir.p8)
- ; CHECK-LDAPR-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (s16) from %ir.p16)
+ ; CHECK-LDAPR-NEXT: renamable $w8 = LDAPRB killed renamable $x0, pcsections !0 :: (load acquire (i8) from %ir.p8)
+ ; CHECK-LDAPR-NEXT: renamable $w9 = LDRHHui killed renamable $x1, 0, pcsections !0 :: (load unordered (i16) from %ir.p16)
; CHECK-LDAPR-NEXT: renamable $w9 = SBFMWri killed renamable $w9, 0, 15
; CHECK-LDAPR-NEXT: renamable $w0 = ADDWrx killed renamable $w9, killed renamable $w8, 32, pcsections !0
; CHECK-LDAPR-NEXT: RET undef $lr, implicit $w0
@@ -706,8 +706,8 @@ define void @store_trunc(i32 %val, ptr %p8, ptr %p16) {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STLRB renamable $w0, killed renamable $x1, pcsections !0 :: (store seq_cst (s8) into %ir.p8)
- ; CHECK-NEXT: STRHHui killed renamable $w0, killed renamable $x2, 0, pcsections !0 :: (store monotonic (s16) into %ir.p16)
+ ; CHECK-NEXT: STLRB renamable $w0, killed renamable $x1, pcsections !0 :: (store seq_cst (i8) into %ir.p8)
+ ; CHECK-NEXT: STRHHui killed renamable $w0, killed renamable $x2, 0, pcsections !0 :: (store monotonic (i16) into %ir.p16)
; CHECK-NEXT: RET undef $lr
%val8 = trunc i32 %val to i8
store atomic i8 %val8, ptr %p8 seq_cst, align 1, !pcsections !0
@@ -728,9 +728,9 @@ define i8 @atomicrmw_add_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $w9 = ADDWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -752,8 +752,8 @@ define i8 @atomicrmw_xchg_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
- ; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w1, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w1, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -775,9 +775,9 @@ define i8 @atomicrmw_sub_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $w9 = SUBWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -799,9 +799,9 @@ define i8 @atomicrmw_and_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $w9 = ANDWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -823,9 +823,9 @@ define i8 @atomicrmw_or_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $w9 = ORRWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -847,9 +847,9 @@ define i8 @atomicrmw_xor_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $w9 = EORWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -871,11 +871,11 @@ define i8 @atomicrmw_min_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 7, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 32, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 11, implicit killed $nzcv, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -897,11 +897,11 @@ define i8 @atomicrmw_max_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 7, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 32, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 12, implicit killed $nzcv, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -925,11 +925,11 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 7, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w11 = STLXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w11 = STLXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -953,11 +953,11 @@ define i8 @atomicrmw_umax_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 7, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w11 = STXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w11 = STXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -979,9 +979,9 @@ define i16 @atomicrmw_add_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: $w9 = ADDWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1003,8 +1003,8 @@ define i16 @atomicrmw_xchg_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
- ; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w1, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w1, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1026,9 +1026,9 @@ define i16 @atomicrmw_sub_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: $w9 = SUBWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1050,9 +1050,9 @@ define i16 @atomicrmw_and_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: $w9 = ANDWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1074,9 +1074,9 @@ define i16 @atomicrmw_or_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: $w9 = ORRWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1098,9 +1098,9 @@ define i16 @atomicrmw_xor_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: $w9 = EORWrs renamable $w8, renamable $w1, 0, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1122,11 +1122,11 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 15, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 40, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 11, implicit killed $nzcv, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1148,11 +1148,11 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 15, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 40, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 12, implicit killed $nzcv, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1176,11 +1176,11 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 15, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w11 = STLXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w11 = STLXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1204,11 +1204,11 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 15, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
- ; CHECK-NEXT: early-clobber renamable $w11 = STXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w11 = STXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
@@ -1232,21 +1232,24 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 7, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
+ ; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: renamable $w9 = MOVZWi 1, 0
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
; CHECK-NEXT: B %bb.4
+ ; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cmpxchg.nostore:
+ ; CHECK-NEXT: bb.3.cmpxchg.nostore:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
@@ -1275,16 +1278,17 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-NEXT: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s16) from %ir.ptr)
+ ; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 15, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 8, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
+ ; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w10 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: renamable $w9 = MOVZWi 1, 0
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
; CHECK-NEXT: B %bb.4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll
new file mode 100644
index 0000000000000..2fd07dc2fa729
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll
@@ -0,0 +1,127 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O3 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-SD
+; RUN: llc < %s -O3 -global-isel -global-isel-abort=1 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-GIS
+
+define bfloat @scalar_fptrunc_float(float %a) {
+; SCALAR-LABEL: scalar_fptrunc_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: bfcvt h0, s0
+; SCALAR-NEXT: ret
+entry:
+ %res = fptrunc float %a to bfloat
+ ret bfloat %res
+}
+
+define float @scalar_fpext(bfloat %a) {
+; SCALAR-LABEL: scalar_fpext:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-NEXT: // kill: def $s0 killed $s0 killed $q0
+; SCALAR-NEXT: ret
+entry:
+ %res = fpext bfloat %a to float
+ ret float %res
+}
+
+define double @scalar_fpext_double(bfloat %a) {
+; SCALAR-LABEL: scalar_fpext_double:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-NEXT: fcvt d0, s0
+; SCALAR-NEXT: ret
+entry:
+ %res = fpext bfloat %a to double
+ ret double %res
+}
+
+define <2 x bfloat> @v2bf16_fptrunc_float(<2 x float> %a) {
+; SCALAR-LABEL: v2bf16_fptrunc_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: // kill: def $d0 killed $d0 def $q0
+; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-NEXT: ret
+entry:
+ %res = fptrunc <2 x float> %a to <2 x bfloat>
+ ret <2 x bfloat> %res
+}
+
+define <3 x bfloat> @v3bf16_fptrunc_float(<3 x float> %a) {
+; SCALAR-LABEL: v3bf16_fptrunc_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-NEXT: ret
+entry:
+ %res = fptrunc <3 x float> %a to <3 x bfloat>
+ ret <3 x bfloat> %res
+}
+
+define <4 x bfloat> @v4bf16_fptrunc_float(<4 x float> %a) {
+; SCALAR-LABEL: v4bf16_fptrunc_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-NEXT: ret
+entry:
+ %res = fptrunc <4 x float> %a to <4 x bfloat>
+ ret <4 x bfloat> %res
+}
+
+define <4 x bfloat> @v4bf16_fptrunc_double(<4 x double> %a) {
+; SCALAR-SD-LABEL: v4bf16_fptrunc_double:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: fcvtxn v0.2s, v0.2d
+; SCALAR-SD-NEXT: fcvtxn2 v0.4s, v1.2d
+; SCALAR-SD-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: v4bf16_fptrunc_double:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: fcvtxn v0.2s, v0.2d
+; SCALAR-GIS-NEXT: fcvtxn2 v0.4s, v1.2d
+; SCALAR-GIS-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fptrunc <4 x double> %a to <4 x bfloat>
+ ret <4 x bfloat> %res
+}
+
+define <2 x float> @v2bf16_fpext_float(<2 x bfloat> %a) {
+; SCALAR-LABEL: v2bf16_fpext_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-NEXT: // kill: def $d0 killed $d0 killed $q0
+; SCALAR-NEXT: ret
+entry:
+ %res = fpext <2 x bfloat> %a to <2 x float>
+ ret <2 x float> %res
+}
+
+define <4 x float> @v4bf16_fpext_float(<4 x bfloat> %a) {
+; SCALAR-LABEL: v4bf16_fpext_float:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-NEXT: ret
+entry:
+ %res = fpext <4 x bfloat> %a to <4 x float>
+ ret <4 x float> %res
+}
+
+define <4 x double> @v4bf16_fpext_double(<4 x bfloat> %a) {
+; SCALAR-SD-LABEL: v4bf16_fpext_double:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fcvtl2 v1.2d, v0.4s
+; SCALAR-SD-NEXT: fcvtl v0.2d, v0.2s
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: v4bf16_fpext_double:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: shll v1.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: fcvtl v0.2d, v1.2s
+; SCALAR-GIS-NEXT: fcvtl2 v1.2d, v1.4s
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fpext <4 x bfloat> %a to <4 x double>
+ ret <4 x double> %res
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll b/llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll
new file mode 100644
index 0000000000000..75f5f68aa1904
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll
@@ -0,0 +1,200 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O3 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-SD
+; RUN: llc < %s -O3 -global-isel -global-isel-abort=1 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-GIS
+
+define bfloat @scalar_fadd(bfloat %a, bfloat %b) {
+; SCALAR-SD-LABEL: scalar_fadd:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fadd s0, s0, s1
+; SCALAR-SD-NEXT: bfcvt h0, s0
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_fadd:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fadd s0, s0, s1
+; SCALAR-GIS-NEXT: bfcvt h0, s0
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fadd bfloat %a, %b
+ ret bfloat %res
+}
+
+define <2 x bfloat> @v2bf16_fadd(<2 x bfloat> %a, <2 x bfloat> %b) {
+; SCALAR-SD-LABEL: v2bf16_fadd:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fadd v0.4s, v0.4s, v1.4s
+; SCALAR-SD-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: v2bf16_fadd:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fadd v0.2s, v0.2s, v1.2s
+; SCALAR-GIS-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fadd <2 x bfloat> %a, %b
+ ret <2 x bfloat> %res
+}
+
+
+define <4 x bfloat> @v4bf16_fadd(<4 x bfloat> %a, <4 x bfloat> %b) {
+; SCALAR-SD-LABEL: v4bf16_fadd:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fadd v0.4s, v0.4s, v1.4s
+; SCALAR-SD-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: v4bf16_fadd:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fadd v0.4s, v0.4s, v1.4s
+; SCALAR-GIS-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fadd <4 x bfloat> %a, %b
+ ret <4 x bfloat> %res
+}
+
+define bfloat @scalar_fsub(bfloat %a, bfloat %b) {
+; SCALAR-SD-LABEL: scalar_fsub:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fsub s0, s0, s1
+; SCALAR-SD-NEXT: bfcvt h0, s0
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_fsub:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fsub s0, s0, s1
+; SCALAR-GIS-NEXT: bfcvt h0, s0
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fsub bfloat %a, %b
+ ret bfloat %res
+}
+
+define bfloat @scalar_fmul(bfloat %a, bfloat %b) {
+; SCALAR-SD-LABEL: scalar_fmul:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fmul s0, s0, s1
+; SCALAR-SD-NEXT: bfcvt h0, s0
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_fmul:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fmul s0, s0, s1
+; SCALAR-GIS-NEXT: bfcvt h0, s0
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fmul bfloat %a, %b
+ ret bfloat %res
+}
+
+define bfloat @scalar_fdiv(bfloat %a, bfloat %b) {
+; SCALAR-SD-LABEL: scalar_fdiv:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fdiv s0, s0, s1
+; SCALAR-SD-NEXT: bfcvt h0, s0
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_fdiv:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fdiv s0, s0, s1
+; SCALAR-GIS-NEXT: bfcvt h0, s0
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = fdiv bfloat %a, %b
+ ret bfloat %res
+}
+
+define i1 @scalar_fcmp(bfloat %a, bfloat %b) {
+; SCALAR-SD-LABEL: scalar_fcmp:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-SD-NEXT: fcmp s0, s1
+; SCALAR-SD-NEXT: cset w0, gt
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_fcmp:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
+; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
+; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
+; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
+; SCALAR-GIS-NEXT: fcmp s0, s1
+; SCALAR-GIS-NEXT: cset w0, gt
+; SCALAR-GIS-NEXT: ret
+entry:
+ %cmp = fcmp ogt bfloat %a, %b
+ ret i1 %cmp
+}
+
+define bfloat @scalar_sitofp(i32 %a) {
+; SCALAR-SD-LABEL: scalar_sitofp:
+; SCALAR-SD: // %bb.0: // %entry
+; SCALAR-SD-NEXT: scvtf d0, w0
+; SCALAR-SD-NEXT: fcvtxn s0, d0
+; SCALAR-SD-NEXT: bfcvt h0, s0
+; SCALAR-SD-NEXT: ret
+;
+; SCALAR-GIS-LABEL: scalar_sitofp:
+; SCALAR-GIS: // %bb.0: // %entry
+; SCALAR-GIS-NEXT: scvtf s0, w0
+; SCALAR-GIS-NEXT: bfcvt h0, s0
+; SCALAR-GIS-NEXT: ret
+entry:
+ %res = sitofp i32 %a to bfloat
+ ret bfloat %res
+}
+
+define <4 x bfloat> @v4i32_sitofp(<4 x i32> %a) {
+; SCALAR-LABEL: v4i32_sitofp:
+; SCALAR: // %bb.0: // %entry
+; SCALAR-NEXT: scvtf v0.4s, v0.4s
+; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
+; SCALAR-NEXT: ret
+entry:
+ %res = sitofp <4 x i32> %a to <4 x bfloat>
+ ret <4 x bfloat> %res
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
index 2305c2694131c..51d7e2bcd218d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
@@ -19,7 +19,7 @@ define void @caller() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @foo_alias, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: RET_ReallyLR
entry:
%0 = call i32 @foo_alias()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
index 982f096fdba55..d5d3b12291b52 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
@@ -20,7 +20,7 @@ define void @caller() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @foo_ifunc, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: RET_ReallyLR
entry:
%0 = call i32 @foo_ifunc()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
index 4224c1cad1b6f..dedbd82e49dc7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
@@ -8,11 +8,11 @@ define i8 @signext_param_i8(i8 signext %x) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY]], 8
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i8 %x
}
@@ -22,10 +22,10 @@ define i8 @no_signext_param(i8 %x) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i8 %x
}
@@ -36,8 +36,8 @@ define i32 @signext_param_i32(i32 signext %x) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i32 %x
}
@@ -48,22 +48,22 @@ define i32 @signext_param_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[SEXTLOAD]], 1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(i32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (i8) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[SEXTLOAD]], 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %g, i64 %h, i64 %i, i1 signext %j) {
%v = zext i1 %j to i32
@@ -76,19 +76,19 @@ define i32 @dont_need_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s32) from %fixed-stack.0, align 8)
- ; CHECK-NEXT: $w0 = COPY [[LOAD1]](s32)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (i32) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %f, i64 %g, i64 %h, i64 %i,
i32 signext %j) {
@@ -101,22 +101,22 @@ define i8 @s8_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[SEXTLOAD]], 8
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(i32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (i8) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[SEXTLOAD]], 8
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %f, i64 %g, i64 %h, i64 %i,
i8 signext %j) {
@@ -128,11 +128,11 @@ define i32 @callee_signext_i1(i1 signext %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s1)
- ; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY]], 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[TRUNC]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[SEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = sext i1 %0 to i32
ret i32 %r
@@ -141,15 +141,15 @@ define i32 @callee_signext_i1(i1 signext %0) {
define i32 @caller_signext_i1() {
; CHECK-LABEL: name: caller_signext_i1
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s8) = G_SEXT [[C]](s1)
- ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[SEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[SEXT1]](s32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i8) = G_SEXT [[C]](i1)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(i32) = G_SEXT [[SEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[SEXT1]](i32)
; CHECK-NEXT: BL @callee_signext_i1, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = call i32 @callee_signext_i1(i1 signext true)
ret i32 %r
@@ -158,9 +158,9 @@ define i32 @caller_signext_i1() {
define signext i1 @ret_signext_i1() {
; CHECK-LABEL: name: ret_signext_i1
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
- ; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[C]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[SEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i1 true
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
index 08021ccedb71b..6a2be75c34efd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
@@ -8,32 +8,32 @@ define [9 x i64] @callee_sret_demotion() {
; CHECK-NEXT: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD1]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD2]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD3]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD4]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD5]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD6]](p0) :: (store (s64))
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C8]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD7]](p0) :: (store (s64))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD1]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD2]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD3]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD4]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD5]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD6]](p0) :: (store (i64))
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C8]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD7]](p0) :: (store (i64))
; CHECK-NEXT: RET_ReallyLR
ret [9 x i64] zeroinitializer
}
@@ -46,32 +46,32 @@ define i64 @caller() {
; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @callee_sret_demotion, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD3]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C4]](s64)
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD4]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C5]](s64)
- ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD5]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C6]](s64)
- ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C7]](s64)
- ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD7]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: $x0 = COPY [[LOAD4]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD1]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](i64)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD2]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C3]](i64)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD3]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C4]](i64)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD4]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C5]](i64)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD5]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C6]](i64)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD6]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C7]](i64)
+ ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD7]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: $x0 = COPY [[LOAD4]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = call [9 x i64] @callee_sret_demotion()
%val = extractvalue [9 x i64] %res, 4
@@ -86,32 +86,32 @@ define i64 @caller_tail() {
; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @callee_sret_demotion, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD3]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C4]](s64)
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD4]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C5]](s64)
- ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD5]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C6]](s64)
- ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C7]](s64)
- ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD7]](p0) :: (load (s64) from %stack.0)
- ; CHECK-NEXT: $x0 = COPY [[LOAD4]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD1]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](i64)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD2]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C3]](i64)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD3]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C4]](i64)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD4]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C5]](i64)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD5]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C6]](i64)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD6]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C7]](i64)
+ ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD7]](p0) :: (load (i64) from %stack.0)
+ ; CHECK-NEXT: $x0 = COPY [[LOAD4]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = tail call [9 x i64] @callee_sret_demotion()
%val = extractvalue [9 x i64] %res, 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
index e5db9c2baa88f..4149fb8e17058 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
@@ -6,10 +6,10 @@ define i8 @v1s8_add(<1 x i8> %a0) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<8 x s8>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8), [[UV2:%[0-9]+]]:_(i8), [[UV3:%[0-9]+]]:_(i8), [[UV4:%[0-9]+]]:_(i8), [[UV5:%[0-9]+]]:_(i8), [[UV6:%[0-9]+]]:_(i8), [[UV7:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[COPY]](<8 x i8>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UV]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = bitcast <1 x i8> %a0 to i8
ret i8 %res
@@ -20,14 +20,14 @@ define i24 @test_v3i8(<3 x i8> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[BUILD_VECTOR]](<3 x s32>)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s24) = G_BITCAST [[TRUNC]](<3 x s8>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[BITCAST]](s24)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x i8>) = G_TRUNC [[BUILD_VECTOR]](<3 x i32>)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i24) = G_BITCAST [[TRUNC]](<3 x i8>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](i24)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = bitcast <3 x i8> %a to i24
ret i24 %res
@@ -39,10 +39,11 @@ define <1 x half> @test_v1s16(<1 x float> %x) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[UV]](s32)
- ; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](s16)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<2 x f32>)
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[UV]](f32)
+ ; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](f16)
; CHECK-NEXT: RET_ReallyLR implicit $h0
%tmp = fptrunc <1 x float> %x to <1 x half>
ret <1 x half> %tmp
@@ -52,15 +53,15 @@ declare <3 x float> @bar(float)
define void @test_return_v3f32() {
; CHECK-LABEL: name: test_return_v3f32
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(f32) = G_IMPLICIT_DEF
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: $s0 = COPY [[DEF]](s32)
+ ; CHECK-NEXT: $s0 = COPY [[DEF]](f32)
; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $q0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[UV]](f32), [[UV1]](f32), [[UV2]](f32)
; CHECK-NEXT: RET_ReallyLR
%call = call <3 x float> @bar(float undef)
ret void
@@ -70,13 +71,13 @@ declare void @foo(<3 x i32>)
define void @test_v3i32_arg() {
; CHECK-LABEL: name: test_v3i32_arg
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32), [[C]](i32)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[DEF]](s32)
- ; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR1]](<4 x s32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x i32>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[UV]](i32), [[UV1]](i32), [[UV2]](i32), [[DEF]](i32)
+ ; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR1]](<4 x i32>)
; CHECK-NEXT: BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
index 02ab7a0772d89..3e6b8c1a1acd1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
@@ -6,25 +6,27 @@
define i8 @zeroext_param_i8(i8 zeroext %x) {
; CHECK-LABEL: name: zeroext_param_i8
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY]], 8
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i8 %x
}
define i8 @no_zeroext_param(i8 %x) {
; CHECK-LABEL: name: no_zeroext_param
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i8 %x
}
@@ -32,10 +34,11 @@ define i8 @no_zeroext_param(i8 %x) {
define i32 @zeroext_param_i32(i32 zeroext %x) {
; CHECK-LABEL: name: zeroext_param_i32
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: $w0 = COPY [[COPY]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i32 %x
}
@@ -43,24 +46,25 @@ define i32 @zeroext_param_i32(i32 zeroext %x) {
define i32 @zeroext_param_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
; CHECK-LABEL: name: zeroext_param_stack
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
- ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
- ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[ZEXTLOAD]], 1
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
- ; CHECK: $w0 = COPY [[ZEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (i8) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[ZEXTLOAD]], 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %g, i64 %h, i64 %i, i1 zeroext %j) {
%v = zext i1 %j to i32
ret i32 %v
@@ -70,21 +74,22 @@ define i32 @zeroext_param_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
define i32 @dont_need_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
; CHECK-LABEL: name: dont_need_assert_zext_stack
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
- ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s32) from %fixed-stack.0, align 8)
- ; CHECK: $w0 = COPY [[LOAD1]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (i32) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD1]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %f, i64 %g, i64 %h, i64 %i,
i32 zeroext %j) {
ret i32 %j
@@ -94,24 +99,25 @@ define i32 @dont_need_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
define i8 @s8_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
; CHECK-LABEL: name: s8_assert_zext_stack
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
- ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
- ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[ZEXTLOAD]], 8
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (i8) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[ZEXTLOAD]], 8
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
i64 %f, i64 %g, i64 %h, i64 %i,
i8 zeroext %j) {
ret i8 %j
@@ -122,11 +128,11 @@ define i32 @callee_zeroext_i1(i1 zeroext %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY]], 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = zext i1 %0 to i32
ret i32 %r
@@ -135,15 +141,15 @@ define i32 @callee_zeroext_i1(i1 zeroext %0) {
define i32 @caller_zeroext_i1() {
; CHECK-LABEL: name: caller_zeroext_i1
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[C]](s1)
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ZEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT1]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[C]](i1)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[ZEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT1]](i32)
; CHECK-NEXT: BL @callee_zeroext_i1, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = call i32 @callee_zeroext_i1(i1 zeroext true)
ret i32 %r
@@ -152,9 +158,9 @@ define i32 @caller_zeroext_i1() {
define zeroext i1 @ret_zeroext_i1() {
; CHECK-LABEL: name: ret_zeroext_i1
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s1)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[C]](i1)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret i1 true
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
index 39860a73bcda4..4ac1adc0ee2f9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
@@ -1,18 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=irtranslator -enable-cse-in-irtranslator=1 -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
; CHECK-LABEL: name: test_split_struct
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load (s64) from %ir.ptr + 8)
+; CHECK: [[LO:%[0-9]+]]:_(i64) = G_LOAD %0(p0) :: (load (i64) from %ir.ptr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: [[HI:%[0-9]+]]:_(i64) = G_LOAD [[GEP]](p0) :: (load (i64) from %ir.ptr + 8)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST2]](s64)
-; CHECK: G_STORE [[LO]](s64), [[GEP2]](p0) :: (store (s64) into stack, align 1)
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST]](s64)
-; CHECK: G_STORE [[HI]](s64), [[GEP3]](p0) :: (store (s64) into stack + 8, align 1)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST2]](i64)
+; CHECK: G_STORE [[LO]](i64), [[GEP2]](p0) :: (store (i64) into stack, align 1)
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST]](i64)
+; CHECK: G_STORE [[HI]](i64), [[GEP3]](p0) :: (store (i64) into stack + 8, align 1)
define void @test_split_struct(ptr %ptr) {
%struct = load [2 x i64], ptr %ptr
call void @take_split_struct(ptr null, i64 1, i64 2, i64 3,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
index b3e436bdfec4a..d5ffcb2b9b556 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-apple-ios -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
@@ -6,16 +7,16 @@
; CHECK-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1,
; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1,
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
-; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX]](p0) :: (invariant load (s8) from %fixed-stack.1, align 16)
-; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD]], 8
-; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
+; CHECK: [[LOAD:%[0-9]+]]:_(i32) = G_SEXTLOAD [[FRAME_INDEX]](p0) :: (invariant load (i8) from %fixed-stack.1, align 16)
+; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[LOAD]], 8
+; CHECK: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT]](i32)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
-; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0)
-; CHECK: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD1]], 8
-; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT1]](s32)
-; CHECK: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
-; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ADD]](s8)
-; CHECK: $w0 = COPY [[SEXT]](s32)
+; CHECK: [[LOAD1:%[0-9]+]]:_(i32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (i8) from %fixed-stack.0)
+; CHECK: [[ASSERT_SEXT1:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[LOAD1]], 8
+; CHECK: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT1]](i32)
+; CHECK: [[ADD:%[0-9]+]]:_(i8) = G_ADD [[TRUNC]], [[TRUNC1]]
+; CHECK: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[ADD]](i8)
+; CHECK: $w0 = COPY [[SEXT]](i32)
; CHECK: RET_ReallyLR implicit $w0
define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) {
%sum = add i8 %lhs, %rhs
@@ -23,15 +24,15 @@ define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs)
}
; CHECK-LABEL: name: test_call_stack
-; CHECK: [[C42:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
-; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 12
+; CHECK: [[C42:%[0-9]+]]:_(i8) = G_CONSTANT i8 42
+; CHECK: [[C12:%[0-9]+]]:_(i8) = G_CONSTANT i8 12
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
-; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C42_OFFS]](s64)
-; CHECK: G_STORE [[C42]](s8), [[C42_LOC]](p0) :: (store (s8) into stack)
-; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
-; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C12_OFFS]](s64)
-; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store (s8) into stack + 1)
+; CHECK: [[C42_OFFS:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C42_OFFS]](i64)
+; CHECK: G_STORE [[C42]](i8), [[C42_LOC]](p0) :: (store (i8) into stack)
+; CHECK: [[C12_OFFS:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C12_OFFS]](i64)
+; CHECK: G_STORE [[C12]](i8), [[C12_LOC]](p0) :: (store (i8) into stack + 1)
; CHECK: BL @test_stack_slots
define void @test_call_stack() {
call signext i8 @test_stack_slots([8 x i64] undef, i8 signext 42, i8 signext 12)
@@ -51,26 +52,26 @@ define void @test_128bit_struct(ptr %ptr) {
; CHECK-LABEL: name: take_128bit_struct
; CHECK: {{%.*}}:_(p0) = COPY $x0
-; CHECK: {{%.*}}:_(s64) = COPY $x1
-; CHECK: {{%.*}}:_(s64) = COPY $x2
+; CHECK: {{%.*}}:_(i64) = COPY $x1
+; CHECK: {{%.*}}:_(i64) = COPY $x2
define void @take_128bit_struct(ptr %ptr, [2 x i64] %in) {
store [2 x i64] %in, ptr %ptr
ret void
}
; CHECK-LABEL: name: test_split_struct
-; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD %3(p0) :: (load (s64) from %ir.ptr + 8)
+; CHECK: [[LD1:%[0-9]+]]:_(i64) = G_LOAD %0(p0) :: (load (i64) from %ir.ptr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i64) = G_LOAD %3(p0) :: (load (i64) from %ir.ptr + 8)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
-; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF]](s64)
-; CHECK: G_STORE [[LD1]](s64), [[ADDR]](p0) :: (store (s64) into stack, align 1)
+; CHECK: [[OFF:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF]](i64)
+; CHECK: G_STORE [[LD1]](i64), [[ADDR]](p0) :: (store (i64) into stack, align 1)
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST]]
-; CHECK: G_STORE [[LD2]](s64), [[ADDR]](p0) :: (store (s64) into stack + 8, align 1)
+; CHECK: G_STORE [[LD2]](i64), [[ADDR]](p0) :: (store (i64) into stack + 8, align 1)
define void @test_split_struct(ptr %ptr) {
%struct = load [2 x i64], ptr %ptr
call void @take_split_struct(ptr null, i64 1, i64 2, i64 3,
@@ -85,10 +86,10 @@ define void @test_split_struct(ptr %ptr) {
; CHECK-DAG: - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8
; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
-; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load (s64) from %fixed-stack.[[LO_FRAME]], align 16)
+; CHECK: [[LO:%[0-9]+]]:_(i64) = G_LOAD [[LOPTR]](p0) :: (invariant load (i64) from %fixed-stack.[[LO_FRAME]], align 16)
; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
-; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load (s64) from %fixed-stack.[[HI_FRAME]])
+; CHECK: [[HI:%[0-9]+]]:_(i64) = G_LOAD [[HIPTR]](p0) :: (invariant load (i64) from %fixed-stack.[[HI_FRAME]])
define void @take_split_struct(ptr %ptr, i64, i64, i64,
i64, i64, i64,
[2 x i64] %in) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
index 0ff6ae28279f8..545d854f047ec 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
@@ -54,8 +54,8 @@ define void @dont_tail_call_explicit_sret_alloca_dummyusers(ptr %ptr) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.l
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir.ptr)
- ; CHECK-NEXT: G_STORE [[LOAD]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %ir.l)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[COPY]](p0) :: (load (i64) from %ir.ptr)
+ ; CHECK-NEXT: G_STORE [[LOAD]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into %ir.l)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8
@@ -74,8 +74,8 @@ define void @dont_tail_call_tailcall_explicit_sret_gep(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x8 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8
@@ -94,8 +94,8 @@ define i64 @dont_tail_call_sret_alloca_returned() {
; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.l)
- ; CHECK-NEXT: $x0 = COPY [[LOAD]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (i64) from %ir.l)
+ ; CHECK-NEXT: $x0 = COPY [[LOAD]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%l = alloca i64, align 8
tail call void @test_explicit_sret(ptr %l)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
index 9828cc8572cca..4328ccb94efe2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
@@ -7,6 +7,7 @@ define void @tail_call() {
; DARWIN-LABEL: name: tail_call
; DARWIN: bb.1 (%ir-block.0):
; DARWIN-NEXT: TCRETURNdi @simple_fn, 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: tail_call
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: TCRETURNdi @simple_fn, 0, csr_aarch64_aapcs, implicit $sp
@@ -23,6 +24,7 @@ define void @indirect_tail_call(ptr %func) {
; DARWIN-NEXT: {{ $}}
; DARWIN-NEXT: [[COPY:%[0-9]+]]:tcgpr64(p0) = COPY $x0
; DARWIN-NEXT: TCRETURNri [[COPY]](p0), 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: indirect_tail_call
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: liveins: $x0
@@ -39,15 +41,16 @@ define void @test_outgoing_args(i32 %a) {
; DARWIN: bb.1 (%ir-block.0):
; DARWIN-NEXT: liveins: $w0
; DARWIN-NEXT: {{ $}}
- ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; DARWIN-NEXT: $w0 = COPY [[COPY]](s32)
+ ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; DARWIN-NEXT: $w0 = COPY [[COPY]](i32)
; DARWIN-NEXT: TCRETURNdi @outgoing_args_fn, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $w0
+ ;
; WINDOWS-LABEL: name: test_outgoing_args
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: liveins: $w0
; WINDOWS-NEXT: {{ $}}
- ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; WINDOWS-NEXT: $w0 = COPY [[COPY]](s32)
+ ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; WINDOWS-NEXT: $w0 = COPY [[COPY]](i32)
; WINDOWS-NEXT: TCRETURNdi @outgoing_args_fn, 0, csr_aarch64_aapcs, implicit $sp, implicit $w0
tail call void @outgoing_args_fn(i32 %a)
ret void
@@ -62,33 +65,50 @@ define void @test_outgoing_stack_args([8 x <2 x double>], <4 x half> %arg) {
; DARWIN: bb.1 (%ir-block.1):
; DARWIN-NEXT: liveins: $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
; DARWIN-NEXT: {{ $}}
- ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; DARWIN-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; DARWIN-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; DARWIN-NEXT: [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $q4
- ; DARWIN-NEXT: [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $q5
- ; DARWIN-NEXT: [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $q6
- ; DARWIN-NEXT: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $q7
+ ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; DARWIN-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; DARWIN-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; DARWIN-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; DARWIN-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY4:%[0-9]+]]:_(<2 x i64>) = COPY $q4
+ ; DARWIN-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY4]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY5:%[0-9]+]]:_(<2 x i64>) = COPY $q5
+ ; DARWIN-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY5]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY6:%[0-9]+]]:_(<2 x i64>) = COPY $q6
+ ; DARWIN-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY6]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY7:%[0-9]+]]:_(<2 x i64>) = COPY $q7
+ ; DARWIN-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY7]](<2 x i64>)
; DARWIN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; DARWIN-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x s16>) from %fixed-stack.0, align 16)
- ; DARWIN-NEXT: $d0 = COPY [[LOAD]](<4 x s16>)
+ ; DARWIN-NEXT: [[LOAD:%[0-9]+]]:_(<4 x f16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x f16>) from %fixed-stack.0, align 16)
+ ; DARWIN-NEXT: $d0 = COPY [[LOAD]](<4 x f16>)
; DARWIN-NEXT: TCRETURNdi @outgoing_stack_args_fn, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $d0
+ ;
; WINDOWS-LABEL: name: test_outgoing_stack_args
; WINDOWS: bb.1 (%ir-block.1):
; WINDOWS-NEXT: liveins: $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
; WINDOWS-NEXT: {{ $}}
- ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; WINDOWS-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; WINDOWS-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; WINDOWS-NEXT: [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $q4
- ; WINDOWS-NEXT: [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $q5
- ; WINDOWS-NEXT: [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $q6
- ; WINDOWS-NEXT: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $q7
+ ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; WINDOWS-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; WINDOWS-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; WINDOWS-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; WINDOWS-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY4:%[0-9]+]]:_(<2 x i64>) = COPY $q4
+ ; WINDOWS-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY4]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY5:%[0-9]+]]:_(<2 x i64>) = COPY $q5
+ ; WINDOWS-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY5]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY6:%[0-9]+]]:_(<2 x i64>) = COPY $q6
+ ; WINDOWS-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY6]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY7:%[0-9]+]]:_(<2 x i64>) = COPY $q7
+ ; WINDOWS-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY7]](<2 x i64>)
; WINDOWS-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; WINDOWS-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x s16>) from %fixed-stack.0, align 16)
- ; WINDOWS-NEXT: $d0 = COPY [[LOAD]](<4 x s16>)
+ ; WINDOWS-NEXT: [[LOAD:%[0-9]+]]:_(<4 x f16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x f16>) from %fixed-stack.0, align 16)
+ ; WINDOWS-NEXT: $d0 = COPY [[LOAD]](<4 x f16>)
; WINDOWS-NEXT: TCRETURNdi @outgoing_stack_args_fn, 0, csr_aarch64_aapcs, implicit $sp, implicit $d0
tail call void @outgoing_stack_args_fn(<4 x half> %arg)
ret void
@@ -100,55 +120,56 @@ declare i32 @too_big_stack(i64 %x0, i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5,
define i32 @test_too_big_stack() {
; DARWIN-LABEL: name: test_too_big_stack
; DARWIN: bb.1.entry:
- ; DARWIN-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; DARWIN-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 8
- ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
+ ; DARWIN-NEXT: [[DEF:%[0-9]+]]:_(i64) = G_IMPLICIT_DEF
+ ; DARWIN-NEXT: [[C:%[0-9]+]]:_(i8) = G_CONSTANT i8 8
+ ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 9
; DARWIN-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; DARWIN-NEXT: G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
- ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; DARWIN-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; DARWIN-NEXT: G_STORE [[C1]](s16), [[PTR_ADD1]](p0) :: (store (s16) into stack + 2, align 1)
- ; DARWIN-NEXT: $x0 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x1 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x2 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x3 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x4 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x5 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x6 = COPY [[DEF]](s64)
- ; DARWIN-NEXT: $x7 = COPY [[DEF]](s64)
+ ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](i64)
+ ; DARWIN-NEXT: G_STORE [[C]](i8), [[PTR_ADD]](p0) :: (store (i8) into stack)
+ ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; DARWIN-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; DARWIN-NEXT: G_STORE [[C1]](i16), [[PTR_ADD1]](p0) :: (store (i16) into stack + 2, align 1)
+ ; DARWIN-NEXT: $x0 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x1 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x2 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x3 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x4 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x5 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x6 = COPY [[DEF]](i64)
+ ; DARWIN-NEXT: $x7 = COPY [[DEF]](i64)
; DARWIN-NEXT: BL @too_big_stack, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit-def $w0
; DARWIN-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $sp, implicit $sp
- ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
- ; DARWIN-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w0
+ ; DARWIN-NEXT: $w0 = COPY [[COPY1]](i32)
; DARWIN-NEXT: RET_ReallyLR implicit $w0
+ ;
; WINDOWS-LABEL: name: test_too_big_stack
; WINDOWS: bb.1.entry:
- ; WINDOWS-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 8
- ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
+ ; WINDOWS-NEXT: [[DEF:%[0-9]+]]:_(i64) = G_IMPLICIT_DEF
+ ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(i8) = G_CONSTANT i8 8
+ ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 9
; WINDOWS-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; WINDOWS-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; WINDOWS-NEXT: G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
- ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; WINDOWS-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; WINDOWS-NEXT: G_STORE [[C1]](s16), [[PTR_ADD1]](p0) :: (store (s16) into stack + 8, align 1)
- ; WINDOWS-NEXT: $x0 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x1 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x2 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x3 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x4 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x5 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x6 = COPY [[DEF]](s64)
- ; WINDOWS-NEXT: $x7 = COPY [[DEF]](s64)
+ ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; WINDOWS-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](i64)
+ ; WINDOWS-NEXT: G_STORE [[C]](i8), [[PTR_ADD]](p0) :: (store (i8) into stack)
+ ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; WINDOWS-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; WINDOWS-NEXT: G_STORE [[C1]](i16), [[PTR_ADD1]](p0) :: (store (i16) into stack + 8, align 1)
+ ; WINDOWS-NEXT: $x0 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x1 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x2 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x3 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x4 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x5 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x6 = COPY [[DEF]](i64)
+ ; WINDOWS-NEXT: $x7 = COPY [[DEF]](i64)
; WINDOWS-NEXT: BL @too_big_stack, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit-def $w0
; WINDOWS-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
- ; WINDOWS-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w0
+ ; WINDOWS-NEXT: $w0 = COPY [[COPY1]](i32)
; WINDOWS-NEXT: RET_ReallyLR implicit $w0
entry:
%call = tail call i32 @too_big_stack(i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i8 8, i16 9)
@@ -163,6 +184,7 @@ define i32 @test_nonvoid_ret() {
; DARWIN-LABEL: name: test_nonvoid_ret
; DARWIN: bb.1 (%ir-block.0):
; DARWIN-NEXT: TCRETURNdi @nonvoid_ret, 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: test_nonvoid_ret
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: TCRETURNdi @nonvoid_ret, 0, csr_aarch64_aapcs, implicit $sp
@@ -174,21 +196,22 @@ declare void @varargs(i32, double, i64, ...)
define void @test_varargs() {
; DARWIN-LABEL: name: test_varargs
; DARWIN: bb.1 (%ir-block.0):
- ; DARWIN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; DARWIN-NEXT: $w0 = COPY [[C]](s32)
- ; DARWIN-NEXT: $d0 = COPY [[C1]](s64)
- ; DARWIN-NEXT: $x1 = COPY [[C2]](s64)
+ ; DARWIN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; DARWIN-NEXT: $w0 = COPY [[C]](i32)
+ ; DARWIN-NEXT: $d0 = COPY [[C1]](f64)
+ ; DARWIN-NEXT: $x1 = COPY [[C2]](i64)
; DARWIN-NEXT: TCRETURNdi @varargs, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $w0, implicit $d0, implicit $x1
+ ;
; WINDOWS-LABEL: name: test_varargs
; WINDOWS: bb.1 (%ir-block.0):
- ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; WINDOWS-NEXT: $w0 = COPY [[C]](s32)
- ; WINDOWS-NEXT: $x1 = COPY [[C1]](s64)
- ; WINDOWS-NEXT: $x2 = COPY [[C2]](s64)
+ ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; WINDOWS-NEXT: $w0 = COPY [[C]](i32)
+ ; WINDOWS-NEXT: $x1 = COPY [[C1]](f64)
+ ; WINDOWS-NEXT: $x2 = COPY [[C2]](i64)
; WINDOWS-NEXT: TCRETURNdi @varargs, 0, csr_aarch64_aapcs, implicit $sp, implicit $w0, implicit $x1, implicit $x2
tail call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12)
ret void
@@ -201,31 +224,32 @@ define void @test_varargs_2() {
; DARWIN-LABEL: name: test_varargs_2
; DARWIN: bb.1 (%ir-block.0):
- ; DARWIN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 314
+ ; DARWIN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 314
; DARWIN-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; DARWIN-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; DARWIN-NEXT: G_STORE [[C3]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 1)
- ; DARWIN-NEXT: $w0 = COPY [[C]](s32)
- ; DARWIN-NEXT: $d0 = COPY [[C1]](s64)
- ; DARWIN-NEXT: $x1 = COPY [[C2]](s64)
+ ; DARWIN-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](i64)
+ ; DARWIN-NEXT: G_STORE [[C3]](i64), [[PTR_ADD]](p0) :: (store (i64) into stack, align 1)
+ ; DARWIN-NEXT: $w0 = COPY [[C]](i32)
+ ; DARWIN-NEXT: $d0 = COPY [[C1]](f64)
+ ; DARWIN-NEXT: $x1 = COPY [[C2]](i64)
; DARWIN-NEXT: BL @varargs, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $d0, implicit $x1
; DARWIN-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: RET_ReallyLR
+ ;
; WINDOWS-LABEL: name: test_varargs_2
; WINDOWS: bb.1 (%ir-block.0):
- ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 314
- ; WINDOWS-NEXT: $w0 = COPY [[C]](s32)
- ; WINDOWS-NEXT: $x1 = COPY [[C1]](s64)
- ; WINDOWS-NEXT: $x2 = COPY [[C2]](s64)
- ; WINDOWS-NEXT: $x3 = COPY [[C3]](s64)
+ ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 314
+ ; WINDOWS-NEXT: $w0 = COPY [[C]](i32)
+ ; WINDOWS-NEXT: $x1 = COPY [[C1]](f64)
+ ; WINDOWS-NEXT: $x2 = COPY [[C2]](i64)
+ ; WINDOWS-NEXT: $x3 = COPY [[C3]](i64)
; WINDOWS-NEXT: TCRETURNdi @varargs, 0, csr_aarch64_aapcs, implicit $sp, implicit $w0, implicit $x1, implicit $x2, implicit $x3
tail call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i64 314)
ret void
@@ -240,53 +264,70 @@ define void @test_varargs_3([8 x <2 x double>], <4 x half> %arg) {
; DARWIN: bb.1 (%ir-block.1):
; DARWIN-NEXT: liveins: $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
; DARWIN-NEXT: {{ $}}
- ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; DARWIN-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; DARWIN-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; DARWIN-NEXT: [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $q4
- ; DARWIN-NEXT: [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $q5
- ; DARWIN-NEXT: [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $q6
- ; DARWIN-NEXT: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $q7
+ ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; DARWIN-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; DARWIN-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; DARWIN-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; DARWIN-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY4:%[0-9]+]]:_(<2 x i64>) = COPY $q4
+ ; DARWIN-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY4]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY5:%[0-9]+]]:_(<2 x i64>) = COPY $q5
+ ; DARWIN-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY5]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY6:%[0-9]+]]:_(<2 x i64>) = COPY $q6
+ ; DARWIN-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY6]](<2 x i64>)
+ ; DARWIN-NEXT: [[COPY7:%[0-9]+]]:_(<2 x i64>) = COPY $q7
+ ; DARWIN-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY7]](<2 x i64>)
; DARWIN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; DARWIN-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x s16>) from %fixed-stack.0, align 16)
- ; DARWIN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 314
+ ; DARWIN-NEXT: [[LOAD:%[0-9]+]]:_(<4 x f16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x f16>) from %fixed-stack.0, align 16)
+ ; DARWIN-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; DARWIN-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; DARWIN-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; DARWIN-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 314
; DARWIN-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: [[COPY8:%[0-9]+]]:_(p0) = COPY $sp
- ; DARWIN-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY8]], [[C4]](s64)
- ; DARWIN-NEXT: G_STORE [[C3]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 1)
- ; DARWIN-NEXT: $w0 = COPY [[C]](s32)
- ; DARWIN-NEXT: $d0 = COPY [[C1]](s64)
- ; DARWIN-NEXT: $x1 = COPY [[C2]](s64)
+ ; DARWIN-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; DARWIN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY8]], [[C4]](i64)
+ ; DARWIN-NEXT: G_STORE [[C3]](i64), [[PTR_ADD]](p0) :: (store (i64) into stack, align 1)
+ ; DARWIN-NEXT: $w0 = COPY [[C]](i32)
+ ; DARWIN-NEXT: $d0 = COPY [[C1]](f64)
+ ; DARWIN-NEXT: $x1 = COPY [[C2]](i64)
; DARWIN-NEXT: BL @varargs, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $d0, implicit $x1
; DARWIN-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: RET_ReallyLR
+ ;
; WINDOWS-LABEL: name: test_varargs_3
; WINDOWS: bb.1 (%ir-block.1):
; WINDOWS-NEXT: liveins: $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
; WINDOWS-NEXT: {{ $}}
- ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; WINDOWS-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; WINDOWS-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; WINDOWS-NEXT: [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $q4
- ; WINDOWS-NEXT: [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $q5
- ; WINDOWS-NEXT: [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $q6
- ; WINDOWS-NEXT: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $q7
+ ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; WINDOWS-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; WINDOWS-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; WINDOWS-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; WINDOWS-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY3]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY4:%[0-9]+]]:_(<2 x i64>) = COPY $q4
+ ; WINDOWS-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY4]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY5:%[0-9]+]]:_(<2 x i64>) = COPY $q5
+ ; WINDOWS-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY5]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY6:%[0-9]+]]:_(<2 x i64>) = COPY $q6
+ ; WINDOWS-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY6]](<2 x i64>)
+ ; WINDOWS-NEXT: [[COPY7:%[0-9]+]]:_(<2 x i64>) = COPY $q7
+ ; WINDOWS-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY7]](<2 x i64>)
; WINDOWS-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; WINDOWS-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x s16>) from %fixed-stack.0, align 16)
- ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 314
- ; WINDOWS-NEXT: $w0 = COPY [[C]](s32)
- ; WINDOWS-NEXT: $x1 = COPY [[C1]](s64)
- ; WINDOWS-NEXT: $x2 = COPY [[C2]](s64)
- ; WINDOWS-NEXT: $x3 = COPY [[C3]](s64)
+ ; WINDOWS-NEXT: [[LOAD:%[0-9]+]]:_(<4 x f16>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (<4 x f16>) from %fixed-stack.0, align 16)
+ ; WINDOWS-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; WINDOWS-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; WINDOWS-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; WINDOWS-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 314
+ ; WINDOWS-NEXT: $w0 = COPY [[C]](i32)
+ ; WINDOWS-NEXT: $x1 = COPY [[C1]](f64)
+ ; WINDOWS-NEXT: $x2 = COPY [[C2]](i64)
+ ; WINDOWS-NEXT: $x3 = COPY [[C3]](i64)
; WINDOWS-NEXT: TCRETURNdi @varargs, 0, csr_aarch64_aapcs, implicit $sp, implicit $w0, implicit $x1, implicit $x2, implicit $x3
tail call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i64 314)
ret void
@@ -302,6 +343,7 @@ define void @test_bad_call_conv() {
; DARWIN-NEXT: BL @bad_call_conv_fn, csr_aarch64_noregs, implicit-def $lr, implicit $sp
; DARWIN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: RET_ReallyLR
+ ;
; WINDOWS-LABEL: name: test_bad_call_conv
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
@@ -322,6 +364,7 @@ define void @test_byval(ptr byval(i8) %ptr) {
; DARWIN-NEXT: BL @simple_fn, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; DARWIN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: RET_ReallyLR
+ ;
; WINDOWS-LABEL: name: test_byval
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -345,6 +388,7 @@ define void @test_inreg(ptr inreg %ptr) {
; DARWIN-NEXT: BL @simple_fn, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; DARWIN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: RET_ReallyLR
+ ;
; WINDOWS-LABEL: name: test_inreg
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: liveins: $x0
@@ -363,6 +407,7 @@ define void @test_mismatched_caller() {
; DARWIN-LABEL: name: test_mismatched_caller
; DARWIN: bb.1 (%ir-block.0):
; DARWIN-NEXT: TCRETURNdi @fast_fn, 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: test_mismatched_caller
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: TCRETURNdi @fast_fn, 0, csr_aarch64_aapcs, implicit $sp
@@ -376,6 +421,7 @@ define void @test_assume() local_unnamed_addr {
; DARWIN-LABEL: name: test_assume
; DARWIN: bb.1.entry:
; DARWIN-NEXT: TCRETURNdi @nonvoid_ret, 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: test_assume
; WINDOWS: bb.1.entry:
; WINDOWS-NEXT: TCRETURNdi @nonvoid_ret, 0, csr_aarch64_aapcs, implicit $sp
@@ -394,6 +440,7 @@ define void @test_lifetime() local_unnamed_addr {
; DARWIN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.t
; DARWIN-NEXT: LIFETIME_START %stack.0.t
; DARWIN-NEXT: TCRETURNdi @nonvoid_ret, 0, csr_darwin_aarch64_aapcs, implicit $sp
+ ;
; WINDOWS-LABEL: name: test_lifetime
; WINDOWS: bb.1.entry:
; WINDOWS-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.t
@@ -424,6 +471,7 @@ define hidden swiftcc i64 @swiftself_indirect_tail(ptr swiftself %arg) {
; DARWIN-NEXT: [[COPY1:%[0-9]+]]:tcgpr64(p0) = COPY $x0
; DARWIN-NEXT: $x20 = COPY [[COPY]](p0)
; DARWIN-NEXT: TCRETURNri [[COPY1]](p0), 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $x20
+ ;
; WINDOWS-LABEL: name: swiftself_indirect_tail
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: liveins: $x20
@@ -451,6 +499,7 @@ define void @foo(ptr) {
; DARWIN-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; DARWIN-NEXT: $x0 = COPY [[C]](p0)
; DARWIN-NEXT: TCRETURNdi @must_callee, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $x0
+ ;
; WINDOWS-LABEL: name: foo
; WINDOWS: bb.1 (%ir-block.1):
; WINDOWS-NEXT: liveins: $x0
@@ -471,23 +520,24 @@ define void @test_tail_call_outgoing_v16f16(<16 x half> %arg) {
; DARWIN: bb.1 (%ir-block.0):
; DARWIN-NEXT: liveins: $q0, $q1
; DARWIN-NEXT: {{ $}}
- ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
- ; DARWIN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[COPY]](<8 x s16>), [[COPY1]](<8 x s16>)
- ; DARWIN-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s16>)
- ; DARWIN-NEXT: $q0 = COPY [[UV]](<8 x s16>)
- ; DARWIN-NEXT: $q1 = COPY [[UV1]](<8 x s16>)
+ ; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
+ ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(<8 x f16>) = COPY $q1
+ ; DARWIN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x f16>) = G_CONCAT_VECTORS [[COPY]](<8 x f16>), [[COPY1]](<8 x f16>)
+ ; DARWIN-NEXT: [[UV:%[0-9]+]]:_(<8 x f16>), [[UV1:%[0-9]+]]:_(<8 x f16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f16>)
+ ; DARWIN-NEXT: $q0 = COPY [[UV]](<8 x f16>)
+ ; DARWIN-NEXT: $q1 = COPY [[UV1]](<8 x f16>)
; DARWIN-NEXT: TCRETURNdi @outgoing_v16f16, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1
+ ;
; WINDOWS-LABEL: name: test_tail_call_outgoing_v16f16
; WINDOWS: bb.1 (%ir-block.0):
; WINDOWS-NEXT: liveins: $q0, $q1
; WINDOWS-NEXT: {{ $}}
- ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
- ; WINDOWS-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[COPY]](<8 x s16>), [[COPY1]](<8 x s16>)
- ; WINDOWS-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x s16>)
- ; WINDOWS-NEXT: $q0 = COPY [[UV]](<8 x s16>)
- ; WINDOWS-NEXT: $q1 = COPY [[UV1]](<8 x s16>)
+ ; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(<8 x f16>) = COPY $q0
+ ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(<8 x f16>) = COPY $q1
+ ; WINDOWS-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x f16>) = G_CONCAT_VECTORS [[COPY]](<8 x f16>), [[COPY1]](<8 x f16>)
+ ; WINDOWS-NEXT: [[UV:%[0-9]+]]:_(<8 x f16>), [[UV1:%[0-9]+]]:_(<8 x f16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<16 x f16>)
+ ; WINDOWS-NEXT: $q0 = COPY [[UV]](<8 x f16>)
+ ; WINDOWS-NEXT: $q1 = COPY [[UV1]](<8 x f16>)
; WINDOWS-NEXT: TCRETURNdi @outgoing_v16f16, 0, csr_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1
tail call void @outgoing_v16f16(<16 x half> %arg)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
index 36529be38253e..25baf6a295b14 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
@@ -12,7 +12,7 @@ define void @test_trivial_call() {
; CHECK-LABEL: name: test_simple_return
; CHECK: BL @simple_return_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
-; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY $x0
+; CHECK: [[RES:%[0-9]+]]:_(i64) = COPY $x0
; CHECK: $x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit $x0
declare i64 @simple_return_callee()
@@ -22,7 +22,7 @@ define i64 @test_simple_return() {
}
; CHECK-LABEL: name: test_simple_arg
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w0
; CHECK: $w0 = COPY [[IN]]
; CHECK: BL @simple_arg_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
; CHECK: RET_ReallyLR
@@ -45,8 +45,8 @@ define void @test_indirect_call(ptr %func) {
}
; CHECK-LABEL: name: test_multiple_args
-; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK: [[IN:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[ANSWER:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
; CHECK: $w0 = COPY [[ANSWER]]
; CHECK: $x1 = COPY [[IN]]
; CHECK: BL @multiple_args_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $x1
@@ -59,19 +59,19 @@ define void @test_multiple_args(i64 %in) {
; CHECK-LABEL: name: test_struct_formal
-; CHECK: [[DBL:%[0-9]+]]:_(s64) = COPY $d0
-; CHECK: [[I64:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[I8_C:%[0-9]+]]:_(s32) = COPY $w1
-; CHECK: [[I8:%[0-9]+]]:_(s8) = G_TRUNC [[I8_C]]
+; CHECK: [[DBL:%[0-9]+]]:_(f64) = COPY $d0
+; CHECK: [[I64:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[I8_C:%[0-9]+]]:_(i32) = COPY $w1
+; CHECK: [[I8:%[0-9]+]]:_(i8) = G_TRUNC [[I8_C]]
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
-; CHECK: G_STORE [[DBL]](s64), [[ADDR]](p0) :: (store (s64) into %ir.addr)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64)
-; CHECK: G_STORE [[I64]](s64), [[GEP1]](p0) :: (store (s64) into %ir.addr + 8)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST2]](s64)
-; CHECK: G_STORE [[I8]](s8), [[GEP2]](p0) :: (store (s8) into %ir.addr + 16, align 8)
+; CHECK: G_STORE [[DBL]](f64), [[ADDR]](p0) :: (store (f64) into %ir.addr)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](i64)
+; CHECK: G_STORE [[I64]](i64), [[GEP1]](p0) :: (store (i64) into %ir.addr + 8)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST2]](i64)
+; CHECK: G_STORE [[I8]](i8), [[GEP2]](p0) :: (store (i8) into %ir.addr + 16, align 8)
; CHECK: RET_ReallyLR
define void @test_struct_formal({double, i64, i8} %in, ptr %addr) {
store {double, i64, i8} %in, ptr %addr
@@ -82,17 +82,17 @@ define void @test_struct_formal({double, i64, i8} %in, ptr %addr) {
; CHECK-LABEL: name: test_struct_return
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load (s64) from %ir.addr)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load (s64) from %ir.addr + 8)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 16, align 8)
-
-; CHECK: $d0 = COPY [[LD1]](s64)
-; CHECK: $x0 = COPY [[LD2]](s64)
-; CHECK: $w1 = COPY [[LD3]](s32)
+; CHECK: [[LD1:%[0-9]+]]:_(f64) = G_LOAD [[ADDR]](p0) :: (load (f64) from %ir.addr)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i64) = G_LOAD [[GEP1]](p0) :: (load (i64) from %ir.addr + 8)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i32) = G_LOAD [[GEP2]](p0) :: (load (i32) from %ir.addr + 16, align 8)
+
+; CHECK: $d0 = COPY [[LD1]](f64)
+; CHECK: $x0 = COPY [[LD2]](i64)
+; CHECK: $w1 = COPY [[LD3]](i32)
; CHECK: RET_ReallyLR implicit $d0, implicit $x0, implicit $w1
define {double, i64, i32} @test_struct_return(ptr %addr) {
%val = load {double, i64, i32}, ptr %addr
@@ -101,26 +101,26 @@ define {double, i64, i32} @test_struct_return(ptr %addr) {
; CHECK-LABEL: name: test_arr_call
; CHECK: %0:_(p0) = COPY $x0
-; CHECK: [[LD1:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.addr)
-; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)
-; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load (s64) from %ir.addr + 8)
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)
-; CHECK: [[LD3:%[0-9]+]]:_(s64) = G_LOAD [[GEP2]](p0) :: (load (s64) from %ir.addr + 16)
-; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)
-; CHECK: [[LD4:%[0-9]+]]:_(s64) = G_LOAD [[GEP3]](p0) :: (load (s64) from %ir.addr + 24)
-
-; CHECK: $x0 = COPY [[LD1]](s64)
-; CHECK: $x1 = COPY [[LD2]](s64)
-; CHECK: $x2 = COPY [[LD3]](s64)
-; CHECK: $x3 = COPY [[LD4]](s64)
+; CHECK: [[LD1:%[0-9]+]]:_(i64) = G_LOAD %0(p0) :: (load (i64) from %ir.addr)
+; CHECK: [[CST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](i64)
+; CHECK: [[LD2:%[0-9]+]]:_(i64) = G_LOAD [[GEP1]](p0) :: (load (i64) from %ir.addr + 8)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](i64)
+; CHECK: [[LD3:%[0-9]+]]:_(i64) = G_LOAD [[GEP2]](p0) :: (load (i64) from %ir.addr + 16)
+; CHECK: [[CST3:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](i64)
+; CHECK: [[LD4:%[0-9]+]]:_(i64) = G_LOAD [[GEP3]](p0) :: (load (i64) from %ir.addr + 24)
+
+; CHECK: $x0 = COPY [[LD1]](i64)
+; CHECK: $x1 = COPY [[LD2]](i64)
+; CHECK: $x2 = COPY [[LD3]](i64)
+; CHECK: $x3 = COPY [[LD4]](i64)
; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1, implicit-def $x2, implicit-def $x3
-; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY $x0
-; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY $x1
-; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY $x2
-; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY $x3
+; CHECK: [[E0:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[E1:%[0-9]+]]:_(i64) = COPY $x1
+; CHECK: [[E2:%[0-9]+]]:_(i64) = COPY $x2
+; CHECK: [[E3:%[0-9]+]]:_(i64) = COPY $x3
; CHECK: $x0 = COPY [[E1]]
declare [4 x i64] @arr_callee([4 x i64])
define i64 @test_arr_call(ptr %addr) {
@@ -132,15 +132,15 @@ define i64 @test_arr_call(ptr %addr) {
; CHECK-LABEL: name: test_abi_exts_call
-; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
-; CHECK: [[VAL_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[VAL]]
+; CHECK: [[VAL:%[0-9]+]]:_(i8) = G_LOAD
+; CHECK: [[VAL_TMP:%[0-9]+]]:_(i32) = G_ANYEXT [[VAL]]
; CHECK: $w0 = COPY [[VAL_TMP]]
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
-; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
-; CHECK: $w0 = COPY [[SVAL]](s32)
+; CHECK: [[SVAL:%[0-9]+]]:_(i32) = G_SEXT [[VAL]](i8)
+; CHECK: $w0 = COPY [[SVAL]](i32)
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
-; CHECK: [[ZVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
-; CHECK: $w0 = COPY [[ZVAL]](s32)
+; CHECK: [[ZVAL:%[0-9]+]]:_(i32) = G_ZEXT [[VAL]](i8)
+; CHECK: $w0 = COPY [[ZVAL]](i32)
; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
declare void @take_char(i8)
define void @test_abi_exts_call(ptr %addr) {
@@ -155,10 +155,10 @@ define void @test_abi_exts_call(ptr %addr) {
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.addr)
+; CHECK: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0) :: (load (i8) from %ir.addr)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
-; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s8)
-; CHECK: $w0 = COPY [[ZEXT]](s32)
+; CHECK: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[LOAD]](i8)
+; CHECK: $w0 = COPY [[ZEXT]](i32)
; CHECK: BL @has_zext_param, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: RET_ReallyLR
@@ -173,10 +173,10 @@ define void @test_zext_in_callee(ptr %addr) {
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.addr)
+; CHECK: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0) :: (load (i8) from %ir.addr)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
-; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD]](s8)
-; CHECK: $w0 = COPY [[SEXT]](s32)
+; CHECK: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[LOAD]](i8)
+; CHECK: $w0 = COPY [[SEXT]](i32)
; CHECK: BL @has_sext_param, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: RET_ReallyLR
@@ -188,9 +188,9 @@ define void @test_sext_in_callee(ptr %addr) {
}
; CHECK-LABEL: name: test_abi_sext_ret
-; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
-; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
-; CHECK: $w0 = COPY [[SVAL]](s32)
+; CHECK: [[VAL:%[0-9]+]]:_(i8) = G_LOAD
+; CHECK: [[SVAL:%[0-9]+]]:_(i32) = G_SEXT [[VAL]](i8)
+; CHECK: $w0 = COPY [[SVAL]](i32)
; CHECK: RET_ReallyLR implicit $w0
define signext i8 @test_abi_sext_ret(ptr %addr) {
%val = load i8, ptr %addr
@@ -198,9 +198,9 @@ define signext i8 @test_abi_sext_ret(ptr %addr) {
}
; CHECK-LABEL: name: test_abi_zext_ret
-; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
-; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
-; CHECK: $w0 = COPY [[SVAL]](s32)
+; CHECK: [[VAL:%[0-9]+]]:_(i8) = G_LOAD
+; CHECK: [[SVAL:%[0-9]+]]:_(i32) = G_ZEXT [[VAL]](i8)
+; CHECK: $w0 = COPY [[SVAL]](i32)
; CHECK: RET_ReallyLR implicit $w0
define zeroext i8 @test_abi_zext_ret(ptr %addr) {
%val = load i8, ptr %addr
@@ -213,13 +213,13 @@ define zeroext i8 @test_abi_zext_ret(ptr %addr) {
; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8,
; CHECK-DAG: - { id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 8,
; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; CHECK: [[LHS:%[0-9]+]]:_(s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load (s64) from %fixed-stack.[[STACK0]], align 16)
+; CHECK: [[LHS:%[0-9]+]]:_(i64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load (i64) from %fixed-stack.[[STACK0]], align 16)
; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; CHECK: [[RHS:%[0-9]+]]:_(s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load (s64) from %fixed-stack.[[STACK8]])
+; CHECK: [[RHS:%[0-9]+]]:_(i64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load (i64) from %fixed-stack.[[STACK8]])
; CHECK: [[ADDR_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load (p0) from %fixed-stack.[[STACK16]], align 16)
-; CHECK: [[SUM:%[0-9]+]]:_(s64) = G_ADD [[LHS]], [[RHS]]
-; CHECK: G_STORE [[SUM]](s64), [[ADDR]](p0)
+; CHECK: [[SUM:%[0-9]+]]:_(i64) = G_ADD [[LHS]], [[RHS]]
+; CHECK: G_STORE [[SUM]](i64), [[ADDR]](p0)
define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, ptr %addr) {
%sum = add i64 %lhs, %rhs
store i64 %sum, ptr %addr
@@ -227,19 +227,19 @@ define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, ptr %addr) {
}
; CHECK-LABEL: name: test_call_stack
-; CHECK: [[C42:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
-; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+; CHECK: [[C42:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+; CHECK: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
-; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C42_OFFS]](s64)
-; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store (s64) into stack, align 1)
-; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C12_OFFS]](s64)
-; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store (s64) into stack + 8, align 1)
-; CHECK: [[PTR_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[PTR_OFFS]](s64)
+; CHECK: [[C42_OFFS:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C42_OFFS]](i64)
+; CHECK: G_STORE [[C42]](i64), [[C42_LOC]](p0) :: (store (i64) into stack, align 1)
+; CHECK: [[C12_OFFS:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[C12_OFFS]](i64)
+; CHECK: G_STORE [[C12]](i64), [[C12_LOC]](p0) :: (store (i64) into stack + 8, align 1)
+; CHECK: [[PTR_OFFS:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[PTR_OFFS]](i64)
; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store (p0) into stack + 16, align 1)
; CHECK: BL @test_stack_slots
; CHECK: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
@@ -253,10 +253,10 @@ define void @test_call_stack() {
; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, stack-id: default,
; CHECK-NEXT: isImmutable: true,
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
-; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[ADDR]](p0) :: (invariant load (s8) from %fixed-stack.[[SLOT]], align 16)
-; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[LOAD]]
-; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC8]], 1
-; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[TRUNCASSERT]]
+; CHECK: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[ADDR]](p0) :: (invariant load (i8) from %fixed-stack.[[SLOT]], align 16)
+; CHECK: [[TRUNC8:%[0-9]+]]:_(i8) = G_TRUNC [[LOAD]]
+; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TRUNC8]], 1
+; CHECK: {{%[0-9]+}}:_(i1) = G_TRUNC [[TRUNCASSERT]]
define void @test_mem_i1([8 x i64], i1 %in) {
ret void
@@ -275,8 +275,8 @@ define void @test_128bit_struct(ptr %ptr) {
; CHECK-LABEL: name: take_128bit_struct
; CHECK: {{%.*}}:_(p0) = COPY $x0
-; CHECK: {{%.*}}:_(s64) = COPY $x1
-; CHECK: {{%.*}}:_(s64) = COPY $x2
+; CHECK: {{%.*}}:_(i64) = COPY $x1
+; CHECK: {{%.*}}:_(i64) = COPY $x2
define void @take_128bit_struct(ptr %ptr, [2 x i64] %in) {
store [2 x i64] %in, ptr %ptr
ret void
@@ -284,17 +284,17 @@ define void @take_128bit_struct(ptr %ptr, [2 x i64] %in) {
; CHECK-LABEL: name: test_split_struct
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
-; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
-; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)
-; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load (s64) from %ir.ptr + 8)
+; CHECK: [[LO:%[0-9]+]]:_(i64) = G_LOAD %0(p0) :: (load (i64) from %ir.ptr)
+; CHECK: [[CST:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](i64)
+; CHECK: [[HI:%[0-9]+]]:_(i64) = G_LOAD [[GEP]](p0) :: (load (i64) from %ir.ptr + 8)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
-; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST2]](s64)
-; CHECK: G_STORE [[LO]](s64), [[GEP2]](p0) :: (store (s64) into stack, align 1)
-; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST]](s64)
-; CHECK: G_STORE [[HI]](s64), [[GEP3]](p0) :: (store (s64) into stack + 8, align 1)
+; CHECK: [[CST2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST2]](i64)
+; CHECK: G_STORE [[LO]](i64), [[GEP2]](p0) :: (store (i64) into stack, align 1)
+; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[CST]](i64)
+; CHECK: G_STORE [[HI]](i64), [[GEP3]](p0) :: (store (i64) into stack + 8, align 1)
define void @test_split_struct(ptr %ptr) {
%struct = load [2 x i64], ptr %ptr
call void @take_split_struct(ptr null, i64 1, i64 2, i64 3,
@@ -309,10 +309,10 @@ define void @test_split_struct(ptr %ptr) {
; CHECK-DAG: - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8
; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
-; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load (s64) from %fixed-stack.[[LO_FRAME]], align 16)
+; CHECK: [[LO:%[0-9]+]]:_(i64) = G_LOAD [[LOPTR]](p0) :: (invariant load (i64) from %fixed-stack.[[LO_FRAME]], align 16)
; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
-; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load (s64) from %fixed-stack.[[HI_FRAME]])
+; CHECK: [[HI:%[0-9]+]]:_(i64) = G_LOAD [[HIPTR]](p0) :: (invariant load (i64) from %fixed-stack.[[HI_FRAME]])
define void @take_split_struct(ptr %ptr, i64, i64, i64,
i64, i64, i64,
[2 x i64] %in) {
@@ -373,11 +373,11 @@ define i32 @test_zext_return_from_callee() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_zext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY]], 16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%val = call i16 @has_zext_return()
%ext = zext i16 %val to i32
@@ -392,11 +392,11 @@ define i32 @test_zext_return_from_callee2() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_zext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[COPY]], 16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%val = call zeroext i16 @has_zext_return()
%ext = zext i16 %val to i32
@@ -412,11 +412,11 @@ define i32 @test_sext_return_from_callee() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_sext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY]], 16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[SEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%val = call i16 @has_sext_return()
%ext = sext i16 %val to i32
@@ -431,11 +431,11 @@ define i32 @test_sext_return_from_callee2() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_sext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[COPY]], 16
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[SEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%val = call signext i16 @has_sext_return()
%ext = sext i16 %val to i32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
index f427f8648a301..e5e6517f6391f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
@@ -266,10 +266,10 @@ name: test_combine_unmerge_fpcst
body: |
bb.1:
; CHECK-LABEL: name: test_combine_unmerge_fpcst
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4000
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4400
; CHECK-NEXT: $h0 = COPY [[C]](s16)
; CHECK-NEXT: $h1 = COPY [[C1]](s16)
; CHECK-NEXT: $h2 = COPY [[C2]](s16)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll b/llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
index 5b04f63679161..b4d4e9d94193f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
@@ -9,8 +9,8 @@ define ptr @test_simple_load_pre(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(s8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[C]](s64), 1 :: (volatile load (s8) from %ir.next)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[C]](i64), 1 :: (volatile load (i8) from %ir.next)
; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%next = getelementptr i8, ptr %ptr, i32 42
@@ -25,9 +25,9 @@ define ptr @test_unused_load_pre(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (s8) from %ir.next)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (i8) from %ir.next)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: $x0 = COPY [[C1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -43,9 +43,9 @@ define ptr @test_simple_store_pre(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
- ; CHECK-NEXT: [[INDEXED_STORE:%[0-9]+]]:_(p0) = G_INDEXED_STORE [[C1]](s8), [[COPY]], [[C]](s64), 1 :: (volatile store (s8) into %ir.next)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i8) = G_CONSTANT i8 0
+ ; CHECK-NEXT: [[INDEXED_STORE:%[0-9]+]]:_(p0) = G_INDEXED_STORE [[C1]](i8), [[COPY]], [[C]](i64), 1 :: (volatile store (i8) into %ir.next)
; CHECK-NEXT: $x0 = COPY [[INDEXED_STORE]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%next = getelementptr i8, ptr %ptr, i32 42
@@ -62,8 +62,8 @@ define ptr @test_store_pre_val_loop(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 336
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 336
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[PTR_ADD]](p0) :: (volatile store (p0) into %ir.next)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -81,12 +81,12 @@ define ptr @test_load_pre_before(ptr %ptr) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: BL @bar, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (s8) from %ir.next)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD]](p0) :: (volatile load (i8) from %ir.next)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%next = getelementptr i8, ptr %ptr, i32 42
@@ -101,10 +101,10 @@ define ptr @test_alloca_load_pre() {
; CHECK-LABEL: name: test_alloca_load_pre
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD]](p0) :: (volatile dereferenceable load (s8) from %ir.next)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[PTR_ADD]](p0) :: (volatile dereferenceable load (i8) from %ir.next)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%ptr = alloca i8, i32 128
@@ -120,8 +120,8 @@ define ptr @test_simple_load_post(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(s8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[C]](s64), 0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[C]](i64), 0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%next = getelementptr i8, ptr %ptr, i32 42
@@ -139,8 +139,8 @@ define ptr @test_simple_load_post_gep_after(ptr %ptr) {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @get_offset, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(s8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[COPY1]](s64), 0 :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[COPY1]](i64), 0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%offset = call i64 @get_offset()
@@ -159,13 +159,13 @@ define ptr @test_load_post_keep_looking(ptr %ptr) {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @get_offset, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(s8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[COPY1]](s64), 0 :: (volatile load (s8) from %ir.ptr)
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[PTRTOINT]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[INDEXED_LOAD:%[0-9]+]]:_(i8), [[INDEXED_LOAD1:%[0-9]+]]:_(p0) = G_INDEXED_LOAD [[COPY]], [[COPY1]](i64), 0 :: (volatile load (i8) from %ir.ptr)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[PTRTOINT]](i64)
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var
; CHECK-NEXT: [[ADD_LOW:%[0-9]+]]:_(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var
- ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[ADD_LOW]](p0) :: (store (s8) into @var)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i8), [[ADD_LOW]](p0) :: (store (i8) into @var)
; CHECK-NEXT: $x0 = COPY [[INDEXED_LOAD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%offset = call i64 @get_offset()
@@ -183,9 +183,9 @@ define ptr @test_load_post_alloca() {
; CHECK-LABEL: name: test_load_post_alloca
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (volatile dereferenceable load (s8) from %ir.ptr)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[FRAME_INDEX]](p0) :: (volatile dereferenceable load (i8) from %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%ptr = alloca i8, i32 128
@@ -202,12 +202,12 @@ define ptr @test_load_post_gep_offset_after(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (volatile load (s8) from %ir.ptr)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0) :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @get_offset, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[COPY1]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
load volatile i8, ptr %ptr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
index 5e667eba741aa..32394c4c6f0a7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll
@@ -12,26 +12,26 @@ define i32 @main() #0 !dbg !14 {
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
- ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %ir.retval)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0), debug-location !17 :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C1]], debug-location !19
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.2, debug-location !20
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %ir.retval)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV]](p0), debug-location !17 :: (dereferenceable load (i32) from @var1)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[LOAD]](i32), [[C1]], debug-location !19
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2, debug-location !20
; CHECK-NEXT: G_BR %bb.3, debug-location !20
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: G_STORE [[C2]](s32), [[GV1]](p0), debug-location !21 :: (store (s32) into @var2)
+ ; CHECK-NEXT: G_STORE [[C2]](i32), [[GV1]](p0), debug-location !21 :: (store (i32) into @var2)
; CHECK-NEXT: G_BR %bb.3, debug-location !23
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
- ; CHECK-NEXT: $w0 = COPY [[C]](s32), debug-location !24
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32), debug-location !24
; CHECK-NEXT: RET_ReallyLR implicit $w0, debug-location !24
entry:
%retval = alloca i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll b/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
index 64fde65bf8b5e..d24d1f822e4ac 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
@@ -31,11 +31,11 @@ entry:
; CHECK-LABEL: name: debug_value
; CHECK: stack:
; CHECK: - { id: {{.*}}, name: addr
-; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
+; CHECK: [[IN:%[0-9]+]]:_(i32) = COPY $w0
define void @debug_value(i32 %in) #0 !dbg !16 {
; CHECK: G_FRAME_INDEX %[[stack_slot:.*]]
%addr = alloca i32
-; CHECK: DBG_VALUE [[IN]](s32), $noreg, !17, !DIExpression(), debug-location !18
+; CHECK: DBG_VALUE [[IN]](i32), $noreg, !17, !DIExpression(), debug-location !18
call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
store i32 %in, ptr %addr
; CHECK: DBG_VALUE %[[stack_slot]], 0, !17, !DIExpression(), debug-location !18
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll b/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
index 88eaa1382d1d6..f46cc65b5c60f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
@@ -4,18 +4,19 @@
define ptr @test_simple_alloca(i32 %numelts) {
; CHECK-LABEL: name: test_simple_alloca
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
- ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
- ; CHECK: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1
- ; CHECK: $x0 = COPY [[DYN_STACKALLOC]](p0)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY]](i32)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = nuw G_ADD [[MUL]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -16
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[ADD]], [[C2]]
+ ; CHECK-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](i64), 1
+ ; CHECK-NEXT: $x0 = COPY [[DYN_STACKALLOC]](p0)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%addr = alloca i8, i32 %numelts
ret ptr %addr
}
@@ -23,18 +24,19 @@ define ptr @test_simple_alloca(i32 %numelts) {
define ptr @test_aligned_alloca(i32 %numelts) {
; CHECK-LABEL: name: test_aligned_alloca
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
- ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
- ; CHECK: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 32
- ; CHECK: $x0 = COPY [[DYN_STACKALLOC]](p0)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY]](i32)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = nuw G_ADD [[MUL]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -16
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[ADD]], [[C2]]
+ ; CHECK-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](i64), 32
+ ; CHECK-NEXT: $x0 = COPY [[DYN_STACKALLOC]](p0)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%addr = alloca i8, i32 %numelts, align 32
ret ptr %addr
}
@@ -42,18 +44,19 @@ define ptr @test_aligned_alloca(i32 %numelts) {
define ptr @test_natural_alloca(i32 %numelts) {
; CHECK-LABEL: name: test_natural_alloca
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
- ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
- ; CHECK: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1
- ; CHECK: $x0 = COPY [[DYN_STACKALLOC]](p0)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY]](i32)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 15
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = nuw G_ADD [[MUL]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -16
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[ADD]], [[C2]]
+ ; CHECK-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](i64), 1
+ ; CHECK-NEXT: $x0 = COPY [[DYN_STACKALLOC]](p0)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%addr = alloca i128, i32 %numelts
ret ptr %addr
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll
index c1c918ff64a6c..6281c2f5c0a78 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fconstant-dbg-loc.ll
@@ -5,7 +5,7 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios5.0.0"
define float @main() #0 !dbg !14 {
-; CHECK: %0:_(s32) = G_FCONSTANT float 0.000000e+00
+; CHECK: %0:_(f32) = G_FCONSTANT float 0.000000e+00
ret float 0.000000e+00, !dbg !24
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
index cb01154a872bb..c499984775e89 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
@@ -35,13 +35,13 @@ body: |
; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %2, %1
- $w1 = COPY %5(s32)
- $s0 = COPY %4(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(oeq), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %2, %1
+ $w1 = COPY %5(f32)
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -68,14 +68,14 @@ body: |
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: $s1 = COPY [[FCSELSrrr1]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %2, %1
- %7:fpr(s32) = G_SELECT %5, %1, %2
- $s0 = COPY %4(s32)
- $s1 = COPY %7(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(oeq), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %2, %1
+ %7:fpr(f32) = G_SELECT %5, %1, %2
+ $s0 = COPY %4(f32)
+ $s1 = COPY %7(f32)
RET_ReallyLR implicit $s0
...
@@ -99,13 +99,13 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:gpr(s32) = COPY $w0
- %1:fpr(s32) = COPY $s0
- %2:gpr(s32) = G_CONSTANT i32 0
- %5:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %6:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
- %4:fpr(s32) = G_SELECT %6, %1, %5
- $s0 = COPY %4(s32)
+ %0:gpr(f32) = COPY $w0
+ %1:fpr(f32) = COPY $s0
+ %2:gpr(f32) = G_CONSTANT i32 0
+ %5:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %6:gpr(f32) = G_ICMP intpred(eq), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %6, %1, %5
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -129,12 +129,12 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %2, %1
- $s0 = COPY %4(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(oeq), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %2, %1
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -162,12 +162,12 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(ueq), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %2, %1
- $s0 = COPY %4(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(ueq), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %2, %1
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -195,12 +195,12 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(one), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %1, %2
- $s0 = COPY %4(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(one), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %1, %2
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -224,12 +224,12 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(une), %0(s32), %2
- %4:fpr(s32) = G_SELECT %5, %1, %2
- $s0 = COPY %4(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(une), %0(f32), %2
+ %4:fpr(f32) = G_SELECT %5, %1, %2
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
@@ -253,12 +253,12 @@ body: |
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 0, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
- %4:fpr(s64) = G_SELECT %5, %2, %1
- $d0 = COPY %4(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(oeq), %0(f64), %2
+ %4:fpr(f64) = G_SELECT %5, %2, %1
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -286,12 +286,12 @@ body: |
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(ueq), %0(s64), %2
- %4:fpr(s64) = G_SELECT %5, %2, %1
- $d0 = COPY %4(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(ueq), %0(f64), %2
+ %4:fpr(f64) = G_SELECT %5, %2, %1
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -319,12 +319,12 @@ body: |
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(one), %0(s64), %2
- %4:fpr(s64) = G_SELECT %5, %1, %2
- $d0 = COPY %4(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(one), %0(f64), %2
+ %4:fpr(f64) = G_SELECT %5, %1, %2
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -348,12 +348,12 @@ body: |
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
- %5:gpr(s32) = G_FCMP floatpred(une), %0(s64), %2
- %4:fpr(s64) = G_SELECT %5, %1, %2
- $d0 = COPY %4(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 0.000000e+00
+ %5:gpr(f32) = G_FCMP floatpred(une), %0(f64), %2
+ %4:fpr(f64) = G_SELECT %5, %1, %2
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -379,13 +379,13 @@ body: |
; CHECK-NEXT: BL @copy_from_physreg, implicit-def $w0
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:gpr(s32) = COPY $w0
- %1:fpr(s32) = COPY $s0
- %5:fpr(s32) = G_FCONSTANT float 0.000000e+00
+ %0:gpr(f32) = COPY $w0
+ %1:fpr(f32) = COPY $s0
+ %5:fpr(f32) = G_FCONSTANT float 0.000000e+00
BL @copy_from_physreg, implicit-def $w0
- %4:fpr(s32) = G_SELECT %5, %1, %5
+ %4:fpr(f32) = G_SELECT %5, %1, %5
BL @copy_from_physreg, implicit-def $w0
- $s0 = COPY %4(s32)
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
index 1c0fc3fb36a0d..1e3855cf534a4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
@@ -35,48 +35,48 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD4]](s128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD4]](f128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 80
; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s64)
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD5]](s128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD5]](f128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 96
; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](s64)
- ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD6]](s128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD6]](f128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 112
; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C6]](s64)
- ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD7]](s128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD7]](f128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 127
; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C7]](s64)
- ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
+ ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
; CHECK-NEXT: [[PTR_ADD15:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD8]](s128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
+ ; CHECK-NEXT: G_STORE [[LOAD8]](f128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
index b040ff2932ce8..c33e5641b1acb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
@@ -108,23 +108,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %ir.1 + 64, align 4)
@@ -156,23 +156,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %ir.1 + 64, align 4)
@@ -232,48 +232,48 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD4]](s128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD4]](f128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 80
; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s64)
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD5]](s128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD5]](f128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 96
; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](s64)
- ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD6]](s128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD6]](f128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 112
; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C6]](s64)
- ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD7]](s128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD7]](f128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 127
; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C7]](s64)
- ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
+ ; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
; CHECK-NEXT: [[PTR_ADD15:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD8]](s128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
+ ; CHECK-NEXT: G_STORE [[LOAD8]](f128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
@@ -300,23 +300,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p2) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p2) :: (load (s128) from %ir.1 + 48, align 4, addrspace 2)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p2) :: (load (s128) from %ir.1 + 48, align 4, addrspace 2)
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD5]](p1) :: (store (s128) into %ir.0 + 48, align 4, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p1) :: (store (s128) into %ir.0 + 48, align 4, addrspace 1)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p2) :: (load (s64) from %ir.1 + 64, align 4, addrspace 2)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
index f24aeaed1d8bc..b06b064b361de 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
@@ -87,20 +87,20 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD2]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD2]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
@@ -122,38 +122,38 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 48, align 4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 48, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD3]](p0) :: (load (s128) from %ir.1 + 64, align 4)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD3]](p0) :: (load (s128) from %ir.1 + 64, align 4)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 80
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s64)
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 80, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 80, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD6]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD6]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 48, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 48, align 4)
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C8]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD4]](s128), [[PTR_ADD8]](p0) :: (store (s128) into %ir.0 + 64, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD4]](f128), [[PTR_ADD8]](p0) :: (store (s128) into %ir.0 + 64, align 4)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 80
; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C9]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD5]](s128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD5]](f128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
@@ -175,23 +175,23 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.1 + 48)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD4]](p0) :: (store (s128) into %ir.0 + 32, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD4]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
; CHECK-NEXT: G_STORE [[LOAD3]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %ir.0 + 48)
@@ -216,20 +216,20 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p2) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD1]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD2]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD2]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
+ ; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p1) = COPY $x0
%1:_(p2) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
index af01789fa75d4..e5f444154f5fd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
@@ -95,11 +95,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MUL]](s64), [[MUL]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: G_STORE [[MUL]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: G_STORE [[MUL]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
@@ -121,18 +123,18 @@ body: |
; CHECK: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %ir.dst + 16, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD]](p0) :: (store (<2 x i64>) into %ir.dst + 16, align 1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into %ir.dst + 32, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD1]](p0) :: (store (<2 x i64>) into %ir.dst + 32, align 1)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD2]](p0) :: (store (<2 x s64>) into %ir.dst + 48, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD2]](p0) :: (store (<2 x i64>) into %ir.dst + 48, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 0
@@ -155,9 +157,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4629771061636907072
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4629771061636907072
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 64
@@ -180,20 +184,20 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MUL]](s64), [[MUL]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MUL]](i64), [[MUL]](i64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %ir.dst + 16, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD]](p0) :: (store (<2 x i64>) into %ir.dst + 16, align 1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into %ir.dst + 32, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD1]](p0) :: (store (<2 x i64>) into %ir.dst + 32, align 1)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD2]](p0) :: (store (<2 x s64>) into %ir.dst + 44, align 1)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[PTR_ADD2]](p0) :: (store (<2 x i64>) into %ir.dst + 44, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
@@ -215,9 +219,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4629771061636907072
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4629771061636907072
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 16448
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
@@ -243,11 +249,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MUL]](s64), [[MUL]](s64)
- ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
+ ; CHECK-NEXT: G_STORE [[MUL]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: G_STORE [[MUL]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
index 73930911e304f..bd73e6870a14e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
@@ -43,13 +43,13 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
- ; CHECK-NEXT: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD1]](s128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll b/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
index 39ad002a0763f..ecf5aeee05896 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
@@ -13,10 +13,10 @@ define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: G_STORE [[C]](s32), [[GV]](p0) :: (store (s32) into @global_var)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[GV]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
@@ -29,19 +29,19 @@ define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C1]](i32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV1]](p0) :: (store (s32) into @global_var)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: G_STORE [[PHI]](i32), [[GV1]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i16) = G_CONSTANT i16 0
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
- ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[C2]](s16), %bb.1, [[C3]](s16), %bb.2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
- ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(i16) = G_PHI [[C2]](i16), %bb.1, [[C3]](i16), %bb.2
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[PHI1]](i16)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C4]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
store i32 42, ptr @global_var
invoke void @may_throw()
@@ -68,12 +68,12 @@ define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_pe
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: G_STORE [[C]](s32), [[GV]](p0) :: (store (s32) into @global_var)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.ptr)
- ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[ASSERT_ZEXT]](s8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[GV]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i8) = G_LOAD [[COPY]](p0) :: (load (i8) from %ir.ptr)
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[LOAD]], 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[ASSERT_ZEXT]](i8)
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
@@ -86,19 +86,19 @@ define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_pe
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C1]](i32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV1]](p0) :: (store (s32) into @global_var)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: G_STORE [[PHI]](i32), [[GV1]](p0) :: (store (i32) into @global_var)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i16) = G_CONSTANT i16 0
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
- ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[ANYEXT]](s16), %bb.1, [[C2]](s16), %bb.2
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
- ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(i16) = G_PHI [[ANYEXT]](i16), %bb.1, [[C2]](i16), %bb.2
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[PHI1]](i16)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C3]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
store i32 42, ptr @global_var
%v = load i1, ptr %ptr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll
index 0173f92c98220..5dbd18a148222 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll
@@ -7,11 +7,11 @@ define <2 x i1> @call_icmp_samesign_vector(<2 x i32> %a, <2 x i32> %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: %2:_(<2 x s1>) = samesign G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i1>) = samesign G_ICMP intpred(ult), [[COPY]](<2 x i32>), [[COPY1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x i32>) = G_ANYEXT [[ICMP]](<2 x i1>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
entry:
%result = icmp samesign ult <2 x i32> %a, %b
@@ -23,11 +23,11 @@ define <2 x i1> @call_icmp_vector(<2 x i32> %a, <2 x i32> %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[ICMP]](<2 x s1>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i1>) = G_ICMP intpred(ult), [[COPY]](<2 x i32>), [[COPY1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x i32>) = G_ANYEXT [[ICMP]](<2 x i1>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
entry:
%result = icmp ult <2 x i32> %a, %b
@@ -39,12 +39,12 @@ define i1 @call_icmp(i32 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[ICMP]](s1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ult), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[ICMP]](i1)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = icmp ult i32 %a, 3
@@ -56,12 +56,12 @@ define i1 @call_icmp_samesign(i32 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: %2:_(s1) = samesign G_ICMP intpred(ult), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT %2(s1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = samesign G_ICMP intpred(ult), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[ICMP]](i1)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = icmp samesign ult i32 %a, 3
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
index d2989a852a032..b741093e5a7ef 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
@@ -9,31 +9,31 @@ define i32 @call_use_s128(i32 %p1, i128 %p2, i32 %p3, i32 %p4, i32 %p5, i128 %p6
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $w4, $w5, $w6, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY1]](s64), [[COPY2]](s64)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w5
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w6
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY1]](i64), [[COPY2]](i64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w5
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $w6
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.2, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.2, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s64) from %fixed-stack.1)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD]](s64), [[LOAD1]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (i64) from %fixed-stack.1)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[LOAD]](i64), [[LOAD1]](i64)
; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (s32) from %fixed-stack.0, align 16)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (i32) from %fixed-stack.0, align 16)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s128)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV1]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[MV]](i128)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[MV1]](i128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
; CHECK-NEXT: BL @use_s128, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
call void @use_s128(i128 %p2, i128 %p6)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
index c471ba0cabaad..1b36f217dbc9e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-atomic-metadata.ll
@@ -4,12 +4,13 @@
define i32 @atomicrmw_volatile(ptr %ptr) {
; CHECK-LABEL: name: atomicrmw_volatile
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (volatile load store monotonic (s32) on %ir.ptr)
- ; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(i32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (volatile load store monotonic (i32) on %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMICRMW_ADD]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%oldval = atomicrmw volatile add ptr %ptr, i32 1 monotonic
ret i32 %oldval
}
@@ -17,12 +18,13 @@ define i32 @atomicrmw_volatile(ptr %ptr) {
define i32 @atomicrmw_falkor(ptr %ptr) {
; CHECK-LABEL: name: atomicrmw_falkor
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: ("aarch64-strided-access" load store monotonic (s32) on %ir.ptr)
- ; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(i32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: ("aarch64-strided-access" load store monotonic (i32) on %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMICRMW_ADD]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%oldval = atomicrmw add ptr %ptr, i32 1 monotonic, !falkor.strided.access !0
ret i32 %oldval
}
@@ -30,12 +32,13 @@ define i32 @atomicrmw_falkor(ptr %ptr) {
define i32 @atomicrmw_volatile_falkor(ptr %ptr) {
; CHECK-LABEL: name: atomicrmw_volatile_falkor
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (volatile "aarch64-strided-access" load store monotonic (s32) on %ir.ptr)
- ; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMICRMW_ADD:%[0-9]+]]:_(i32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (volatile "aarch64-strided-access" load store monotonic (i32) on %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMICRMW_ADD]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%oldval = atomicrmw volatile add ptr %ptr, i32 1 monotonic, !falkor.strided.access !0
ret i32 %oldval
}
@@ -43,13 +46,14 @@ define i32 @atomicrmw_volatile_falkor(ptr %ptr) {
define i32 @cmpxchg_volatile(ptr %addr) {
; CHECK-LABEL: name: cmpxchg_volatile
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: (volatile load store monotonic monotonic (s32) on %ir.addr)
- ; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(i32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: (volatile load store monotonic monotonic (i32) on %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%val_success = cmpxchg volatile ptr %addr, i32 0, i32 1 monotonic monotonic
%value_loaded = extractvalue { i32, i1 } %val_success, 0
ret i32 %value_loaded
@@ -58,13 +62,14 @@ define i32 @cmpxchg_volatile(ptr %addr) {
define i32 @cmpxchg_falkor(ptr %addr) {
; CHECK-LABEL: name: cmpxchg_falkor
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: ("aarch64-strided-access" load store monotonic monotonic (s32) on %ir.addr)
- ; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(i32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: ("aarch64-strided-access" load store monotonic monotonic (i32) on %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%val_success = cmpxchg ptr %addr, i32 0, i32 1 monotonic monotonic, !falkor.strided.access !0
%value_loaded = extractvalue { i32, i1 } %val_success, 0
ret i32 %value_loaded
@@ -73,13 +78,14 @@ define i32 @cmpxchg_falkor(ptr %addr) {
define i32 @cmpxchg_volatile_falkor(ptr %addr) {
; CHECK-LABEL: name: cmpxchg_volatile_falkor
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: (volatile "aarch64-strided-access" load store monotonic monotonic (s32) on %ir.addr)
- ; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(i32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(i1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: (volatile "aarch64-strided-access" load store monotonic monotonic (i32) on %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[ATOMIC_CMPXCHG_WITH_SUCCESS]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%val_success = cmpxchg volatile ptr %addr, i32 0, i32 1 monotonic monotonic, !falkor.strided.access !0
%value_loaded = extractvalue { i32, i1 } %val_success, 0
ret i32 %value_loaded
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
index f84f156d154a4..8f482dda4a491 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
@@ -23,8 +23,8 @@ define i32 @test_bitcast_invalid_vreg() {
%tmp15 = add i32 30, 30
; At this point we mapped 46 values. The 'i32 100' constant will grow the map.
-; CHECK: %46:_(s32) = G_CONSTANT i32 100
-; CHECK: $w0 = COPY %47(s32)
+; CHECK: %46:_(i32) = G_CONSTANT i32 100
+; CHECK: $w0 = COPY %47(i32)
%res = bitcast i32 100 to i32
ret i32 %res
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
index 30eca0d463eb2..8f5c41de13d3b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
@@ -5,28 +5,33 @@ declare i32 @bar(...)
define void @or_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x20000000), %bb.4(0x60000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.3
- ; CHECK: G_BR %bb.4
- ; CHECK: bb.4.entry:
- ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x20000000), %bb.4(0x60000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
@@ -44,29 +49,34 @@ UnifiedReturnBlock:
define void @or_cond_select(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_select
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x20000000), %bb.4(0x60000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: [[SELECT:%[0-9]+]]:_(s1) = G_SELECT [[ICMP1]](s1), [[C2]], [[ICMP]]
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.3
- ; CHECK: G_BR %bb.4
- ; CHECK: bb.4.entry:
- ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x20000000), %bb.4(0x60000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i1) = G_SELECT [[ICMP1]](i1), [[C2]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
@@ -84,28 +94,33 @@ UnifiedReturnBlock:
define void @and_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: and_cond
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.4(0x60000000), %bb.2(0x20000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP1]], [[ICMP]]
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.4.entry:
- ; CHECK: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.4(0x60000000), %bb.2(0x20000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i1) = G_AND [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.4
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
@@ -123,29 +138,34 @@ UnifiedReturnBlock:
define void @and_cond_select(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: and_cond_select
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.4(0x60000000), %bb.2(0x20000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: [[SELECT:%[0-9]+]]:_(s1) = G_SELECT [[ICMP1]](s1), [[ICMP]], [[C2]]
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.4.entry:
- ; CHECK: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.4(0x60000000), %bb.2(0x20000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i1) = G_SELECT [[ICMP1]](i1), [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.4
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
@@ -164,21 +184,24 @@ UnifiedReturnBlock:
define void @or_cond_same_values_cmp(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_same_values_cmp
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
- ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
- ; CHECK: G_BRCOND [[OR]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: G_BRCOND [[OR]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 5
%tmp3 = icmp slt i32 %X, 5
@@ -197,34 +220,41 @@ UnifiedReturnBlock:
define void @or_cond_multiple_cases(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_multiple_cases
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x10000000), %bb.5(0x70000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
- ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
- ; CHECK: [[OR1:%[0-9]+]]:_(s1) = G_OR [[OR]], [[ICMP2]]
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
- ; CHECK: G_BR %bb.5
- ; CHECK: bb.5.entry:
- ; CHECK: successors: %bb.3(0x12492492), %bb.4(0x6db6db6e)
- ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP4]](s1), %bb.3
- ; CHECK: G_BR %bb.4
- ; CHECK: bb.4.entry:
- ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
- ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP5]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x10000000), %bb.5(0x70000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY2]](i32), [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i1) = G_OR [[OR]], [[ICMP2]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x12492492), %bb.4(0x6db6db6e)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP4]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY2]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP5]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 5
%tmp3 = icmp slt i32 %X, 5
@@ -246,21 +276,24 @@ UnifiedReturnBlock:
define void @or_cond_ne_null(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_ne_null
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
- ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
- ; CHECK: G_BRCOND [[OR]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[COPY1]](i32), [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: G_BRCOND [[OR]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp ne i32 %X, 0
%tmp3 = icmp ne i32 %Y, 0
@@ -281,22 +314,25 @@ UnifiedReturnBlock:
define void @unpredictable(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: unpredictable
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
- ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
- ; CHECK: G_BRCOND [[OR]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.common.ret:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.cond_true:
- ; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[COPY]](i32), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[COPY1]](i32), [[C1]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i1) = G_OR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: G_BRCOND [[OR]](i1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.common.ret:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.cond_true:
+ ; CHECK-NEXT: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry:
%tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
new file mode 100644
index 0000000000000..c153d08a3ebdb
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=aarch64-- -mcpu=falkor -mattr=+lse -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+
+define i16 @convert_to_fp16(float %src) {
+ ; CHECK-LABEL: name: convert_to_fp16
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(i16) = G_FPTRUNC [[COPY]](f32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
+ %cvt = call i16 @llvm.convert.to.fp16.f32(float %src)
+ ret i16 %cvt
+}
+
+define float @convert_from_fp16(i16 %src) {
+ ; CHECK-LABEL: name: convert_from_fp16
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $s0 = COPY [[FPEXT]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ %cvt = call float @llvm.convert.from.fp16.f32(i16 %src)
+ ret float %cvt
+}
+
+declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
+declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
index 4a3b85d9cec18..2edbb53991ac4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
@@ -16,15 +16,16 @@ define void @caller() sspreq {
; CHECK-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (s64) from %stack.0.StackGuardSlot)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (i64) from %stack.0.StackGuardSlot)
; CHECK-NEXT: [[LOAD_STACK_GUARD2:%[0-9]+]]:gpr64sp(s64) = LOAD_STACK_GUARD :: (dereferenceable invariant load (p0) from @__stack_chk_guard)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.entry:
; CHECK-NEXT: successors:
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL &__stack_chk_fail, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
index 8d68f384db907..9235371a500bd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
@@ -12,16 +12,16 @@ define { ptr, i32 } @bar() personality ptr @__gxx_personality_v0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
@@ -32,15 +32,15 @@ define { ptr, i32 } @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY2]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
- ; CHECK-NEXT: $w1 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[PTRTOINT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: $x0 = COPY [[DEF]](p0)
- ; CHECK-NEXT: $w1 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
%res32 = invoke i32 @foo(i32 42) to label %continue unwind label %broken
@@ -77,7 +77,7 @@ define void @test_invoke_indirect(ptr %callee) personality ptr @__gxx_personalit
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
@@ -99,19 +99,19 @@ define void @test_invoke_varargs() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)
- ; CHECK-NEXT: G_STORE [[ANYEXT]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 1)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[C2]](s32), [[PTR_ADD1]](p0) :: (store (s32) into stack + 8, align 1)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[C1]](i32)
+ ; CHECK-NEXT: G_STORE [[ANYEXT]](i64), [[PTR_ADD]](p0) :: (store (i64) into stack, align 1)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](i64)
+ ; CHECK-NEXT: G_STORE [[C2]](f32), [[PTR_ADD1]](p0) :: (store (f32) into stack + 8, align 1)
; CHECK-NEXT: $x0 = COPY [[C]](p0)
; CHECK-NEXT: BL @printf, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
@@ -125,7 +125,7 @@ define void @test_invoke_varargs() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
@@ -148,12 +148,12 @@ define i32 @test_lpad_phi() personality ptr @__gxx_personality_v0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 55
- ; CHECK-NEXT: G_STORE [[C]](s32), [[GV]](p0) :: (store (s32) into @global_var)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 55
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[GV]](p0) :: (store (i32) into @global_var)
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
@@ -166,18 +166,18 @@ define i32 @test_lpad_phi() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI [[C1]](i32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV]](p0) :: (store (s32) into @global_var)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: G_STORE [[PHI]](i32), [[GV]](p0) :: (store (i32) into @global_var)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
- ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C2]](s32), %bb.1, [[C3]](s32), %bb.2
- ; CHECK-NEXT: $w0 = COPY [[PHI1]](s32)
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(i32) = G_PHI [[C2]](i32), %bb.1, [[C3]](i32), %bb.2
+ ; CHECK-NEXT: $w0 = COPY [[PHI1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
store i32 42, ptr @global_var
invoke void @may_throw()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll
index b5658155f468b..249bca91a3cb4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-extends.ll
@@ -5,11 +5,11 @@
define i32 @test_zext(i32 %a) {
; CHECK-LABEL: name: test_zext
- ; CHECK: %0:_(s32) = COPY $w0
- ; CHECK: %1:_(s8) = G_TRUNC %0(s32)
- ; CHECK: %2:_(s16) = G_ZEXT %1(s8)
- ; CHECK: %3:_(s32) = G_ZEXT %2(s16)
- ; CHECK: $w0 = COPY %3(s32)
+ ; CHECK: %0:_(i32) = COPY $w0
+ ; CHECK: %1:_(i8) = G_TRUNC %0(i32)
+ ; CHECK: %2:_(i16) = G_ZEXT %1(i8)
+ ; CHECK: %3:_(i32) = G_ZEXT %2(i16)
+ ; CHECK: $w0 = COPY %3(i32)
%tmp0 = trunc i32 %a to i8
%tmp1 = zext i8 %tmp0 to i16
%tmp2 = zext i16 %tmp1 to i32
@@ -18,11 +18,11 @@ define i32 @test_zext(i32 %a) {
define i32 @test_sext(i32 %a) {
; CHECK-LABEL: name: test_sext
- ; CHECK: %0:_(s32) = COPY $w0
- ; CHECK: %1:_(s8) = G_TRUNC %0(s32)
- ; CHECK: %2:_(s16) = G_SEXT %1(s8)
- ; CHECK: %3:_(s32) = G_SEXT %2(s16)
- ; CHECK: $w0 = COPY %3(s32)
+ ; CHECK: %0:_(i32) = COPY $w0
+ ; CHECK: %1:_(i8) = G_TRUNC %0(i32)
+ ; CHECK: %2:_(i16) = G_SEXT %1(i8)
+ ; CHECK: %3:_(i32) = G_SEXT %2(i16)
+ ; CHECK: $w0 = COPY %3(i32)
%tmp0 = trunc i32 %a to i8
%tmp1 = sext i8 %tmp0 to i16
%tmp2 = sext i16 %tmp1 to i32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll
index c70b93e50ded8..a9301581e7694 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fixed-point-intrinsics.ll
@@ -4,15 +4,16 @@
define i16 @smul_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: smul_fix
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[SMULFIX:%[0-9]+]]:_(s16) = G_SMULFIX [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMULFIX]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[SMULFIX:%[0-9]+]]:_(i16) = G_SMULFIX [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SMULFIX]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.smul.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -20,15 +21,16 @@ define i16 @smul_fix(i16 %arg0, i16 %arg1) {
define i16 @umul_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: umul_fix
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[UMULFIX:%[0-9]+]]:_(s16) = G_UMULFIX [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMULFIX]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[UMULFIX:%[0-9]+]]:_(i16) = G_UMULFIX [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UMULFIX]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.umul.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -36,15 +38,16 @@ define i16 @umul_fix(i16 %arg0, i16 %arg1) {
define i16 @smul_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: smul_fix_sat
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[SMULFIXSAT:%[0-9]+]]:_(s16) = G_SMULFIXSAT [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMULFIXSAT]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[SMULFIXSAT:%[0-9]+]]:_(i16) = G_SMULFIXSAT [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SMULFIXSAT]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.smul.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -52,15 +55,16 @@ define i16 @smul_fix_sat(i16 %arg0, i16 %arg1) {
define i16 @umul_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: umul_fix_sat
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[UMULFIXSAT:%[0-9]+]]:_(s16) = G_UMULFIXSAT [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMULFIXSAT]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[UMULFIXSAT:%[0-9]+]]:_(i16) = G_UMULFIXSAT [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UMULFIXSAT]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.umul.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -68,15 +72,16 @@ define i16 @umul_fix_sat(i16 %arg0, i16 %arg1) {
define i16 @sdiv_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: sdiv_fix
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[SDIVFIX:%[0-9]+]]:_(s16) = G_SDIVFIX [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SDIVFIX]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[SDIVFIX:%[0-9]+]]:_(i16) = G_SDIVFIX [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SDIVFIX]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.sdiv.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -84,15 +89,16 @@ define i16 @sdiv_fix(i16 %arg0, i16 %arg1) {
define i16 @udiv_fix(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: udiv_fix
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[UDIVFIX:%[0-9]+]]:_(s16) = G_UDIVFIX [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UDIVFIX]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[UDIVFIX:%[0-9]+]]:_(i16) = G_UDIVFIX [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UDIVFIX]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.udiv.fix.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -100,15 +106,16 @@ define i16 @udiv_fix(i16 %arg0, i16 %arg1) {
define i16 @sdiv_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: sdiv_fix_sat
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[SDIVFIXSAT:%[0-9]+]]:_(s16) = G_SDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SDIVFIXSAT]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[SDIVFIXSAT:%[0-9]+]]:_(i16) = G_SDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SDIVFIXSAT]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.sdiv.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
@@ -116,15 +123,16 @@ define i16 @sdiv_fix_sat(i16 %arg0, i16 %arg1) {
define i16 @udiv_fix_sat(i16 %arg0, i16 %arg1) {
; CHECK-LABEL: name: udiv_fix_sat
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: [[UDIVFIXSAT:%[0-9]+]]:_(s16) = G_UDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UDIVFIXSAT]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[UDIVFIXSAT:%[0-9]+]]:_(i16) = G_UDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UDIVFIXSAT]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i16 @llvm.udiv.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)
ret i16 %res
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
index 4e639974b66e0..d8e172d93513a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fp-min-max-intrinsics.ll
@@ -4,12 +4,13 @@
define float @test_minnum(float %x, float %y) {
; CHECK-LABEL: name: test_minnum
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY [[FMINNUM]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(f32) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINNUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.minnum.f32(float %x, float %y)
ret float %val
}
@@ -17,12 +18,13 @@ define float @test_minnum(float %x, float %y) {
define float @test_minnum_nnan(float %x, float %y) {
; CHECK-LABEL: name: test_minnum_nnan
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: %2:_(s32) = nnan G_FMINNUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY %2(s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(f32) = nnan G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINNUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call nnan float @llvm.minnum.f32(float %x, float %y)
ret float %val
}
@@ -30,12 +32,13 @@ define float @test_minnum_nnan(float %x, float %y) {
define float @test_maxnum(float %x, float %y) {
; CHECK-LABEL: name: test_maxnum
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY [[FMAXNUM]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(f32) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMAXNUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.maxnum.f32(float %x, float %y)
ret float %val
}
@@ -43,12 +46,13 @@ define float @test_maxnum(float %x, float %y) {
define float @test_minimum(float %x, float %y) {
; CHECK-LABEL: name: test_minimum
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: [[FMINIMUM:%[0-9]+]]:_(s32) = G_FMINIMUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY [[FMINIMUM]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINIMUM:%[0-9]+]]:_(f32) = G_FMINIMUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINIMUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.minimum.f32(float %x, float %y)
ret float %val
}
@@ -56,12 +60,13 @@ define float @test_minimum(float %x, float %y) {
define float @test_minimum_nnan(float %x, float %y) {
; CHECK-LABEL: name: test_minimum_nnan
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: %2:_(s32) = nnan G_FMINIMUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY %2(s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINIMUM:%[0-9]+]]:_(f32) = nnan G_FMINIMUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINIMUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call nnan float @llvm.minimum.f32(float %x, float %y)
ret float %val
}
@@ -69,12 +74,13 @@ define float @test_minimum_nnan(float %x, float %y) {
define float @test_maximum(float %x, float %y) {
; CHECK-LABEL: name: test_maximum
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK: [[FMAXIMUM:%[0-9]+]]:_(s32) = G_FMAXIMUM [[COPY]], [[COPY1]]
- ; CHECK: $s0 = COPY [[FMAXIMUM]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(f32) = G_FMAXIMUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMAXIMUM]](f32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.maximum.f32(float %x, float %y)
ret float %val
}
@@ -84,10 +90,10 @@ define float @test_minimumnum(float %x, float %y) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(s32) = G_FMINIMUMNUM [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $s0 = COPY [[FMINIMUMNUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(f32) = G_FMINIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINIMUMNUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %val
@@ -98,10 +104,10 @@ define float @test_minimumnum_nnan(float %x, float %y) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(s32) = nnan G_FMINIMUMNUM [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $s0 = COPY [[FMINIMUMNUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:_(f32) = nnan G_FMINIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMINIMUMNUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call nnan float @llvm.minimumnum.f32(float %x, float %y)
ret float %val
@@ -112,10 +118,10 @@ define float @test_maximumnum(float %x, float %y) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(s32) = G_FMAXIMUMNUM [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $s0 = COPY [[FMAXIMUMNUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(f32) = G_FMAXIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMAXIMUMNUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %val
@@ -126,10 +132,10 @@ define float @test_maximumnum_nnan(float %x, float %y) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(s32) = nnan G_FMAXIMUMNUM [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $s0 = COPY [[FMAXIMUMNUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:_(f32) = nnan G_FMAXIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FMAXIMUMNUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%val = call nnan float @llvm.maximumnum.f32(float %x, float %y)
ret float %val
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
index 9a8e5529f0a1e..56354d5ddfd33 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-fpenv.ll
@@ -11,8 +11,8 @@ declare void @llvm.reset.fpmode()
define i64 @func_get_fpenv() #0 {
; CHECK-LABEL: name: func_get_fpenv
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[GET_FPENV:%[0-9]+]]:_(s64) = G_GET_FPENV
- ; CHECK-NEXT: $x0 = COPY [[GET_FPENV]](s64)
+ ; CHECK-NEXT: [[GET_FPENV:%[0-9]+]]:_(i64) = G_GET_FPENV
+ ; CHECK-NEXT: $x0 = COPY [[GET_FPENV]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%fpenv = call i64 @llvm.get.fpenv.i64()
@@ -24,8 +24,8 @@ define void @func_set_fpenv(i64 %fpenv) #0 {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: G_SET_FPENV [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: G_SET_FPENV [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.set.fpenv.i64(i64 %fpenv)
@@ -45,8 +45,8 @@ entry:
define i32 @func_get_fpmode() #0 {
; CHECK-LABEL: name: func_get_fpmode
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[GET_FPMODE:%[0-9]+]]:_(s32) = G_GET_FPMODE
- ; CHECK-NEXT: $w0 = COPY [[GET_FPMODE]](s32)
+ ; CHECK-NEXT: [[GET_FPMODE:%[0-9]+]]:_(i32) = G_GET_FPMODE
+ ; CHECK-NEXT: $w0 = COPY [[GET_FPMODE]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%fpmode = call i32 @llvm.get.fpmode.i32()
@@ -58,8 +58,8 @@ define void @func_set_fpmode(i32 %fpmode) #0 {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: G_SET_FPMODE [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: G_SET_FPMODE [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.set.fpmode.i32(i32 %fpmode)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
index b7cf9b31e345a..24e85f566e0c5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-gep-flags.ll
@@ -7,20 +7,20 @@ define i32 @gep_nusw_nuw(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = nuw nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nuw nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -37,20 +37,20 @@ define i32 @gep_nuw(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = nuw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nuw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -67,20 +67,20 @@ define i32 @gep_nusw(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -97,20 +97,20 @@ define i32 @gep_none(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -127,20 +127,20 @@ define i32 @gep_nusw_negative(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1)
- ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[COPY]], [[MUL1]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY2]](p0) :: (load (i32) from %ir.gep1)
+ ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[COPY]], [[MUL1]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](i64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (i32) from %ir.gep2)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[LOAD]], [[LOAD1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], ptr %ptr, i64 %sidx, i64 0
@@ -157,15 +157,15 @@ define ptr @gep_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
@@ -179,15 +179,15 @@ define ptr @gep_nuw_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nuw G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nuw G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
@@ -201,15 +201,15 @@ define ptr @gep_nusw_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
@@ -223,15 +223,15 @@ define ptr @gep_inbounds_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nsw G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nsw G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
@@ -245,15 +245,15 @@ define ptr @gep_nuw_nusw_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nuw nsw G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nuw nsw G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
@@ -267,15 +267,15 @@ define ptr @gep_nuw_inbounds_many_indices(ptr %ptr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 108
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = nuw nsw G_MUL [[SEXT]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 108
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 12
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = nuw nsw G_MUL [[SEXT]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -4
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%sidx = sext i32 %idx to i64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
index 1602480ea3e0d..1be3988d2cfd4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
@@ -14,26 +14,26 @@ define i32 @test(i32 %a, i1 %c) {
; TRANSLATED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; TRANSLATED-NEXT: liveins: $w0, $w1
; TRANSLATED-NEXT: {{ $}}
- ; TRANSLATED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; TRANSLATED-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; TRANSLATED-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; TRANSLATED-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC]], 1
- ; TRANSLATED-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s8)
- ; TRANSLATED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 100000
- ; TRANSLATED-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; TRANSLATED-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s32) = G_CONSTANT_FOLD_BARRIER [[C]]
- ; TRANSLATED-NEXT: G_BRCOND [[TRUNC1]](s1), %bb.3
+ ; TRANSLATED-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; TRANSLATED-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; TRANSLATED-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
+ ; TRANSLATED-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i8) = G_ASSERT_ZEXT [[TRUNC]], 1
+ ; TRANSLATED-NEXT: [[TRUNC1:%[0-9]+]]:_(i1) = G_TRUNC [[ASSERT_ZEXT]](i8)
+ ; TRANSLATED-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 100000
+ ; TRANSLATED-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; TRANSLATED-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(i32) = G_CONSTANT_FOLD_BARRIER [[C]]
+ ; TRANSLATED-NEXT: G_BRCOND [[TRUNC1]](i1), %bb.3
; TRANSLATED-NEXT: G_BR %bb.2
; TRANSLATED-NEXT: {{ $}}
; TRANSLATED-NEXT: bb.2.common.ret:
- ; TRANSLATED-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.3, [[C1]](s32), %bb.1
- ; TRANSLATED-NEXT: $w0 = COPY [[PHI]](s32)
+ ; TRANSLATED-NEXT: [[PHI:%[0-9]+]]:_(i32) = G_PHI %7(i32), %bb.3, [[C1]](i32), %bb.1
+ ; TRANSLATED-NEXT: $w0 = COPY [[PHI]](i32)
; TRANSLATED-NEXT: RET_ReallyLR implicit $w0
; TRANSLATED-NEXT: {{ $}}
; TRANSLATED-NEXT: bb.3.cont:
; TRANSLATED-NEXT: successors: %bb.2(0x80000000)
; TRANSLATED-NEXT: {{ $}}
- ; TRANSLATED-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
+ ; TRANSLATED-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
; TRANSLATED-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; TRANSLATED-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; TRANSLATED-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
@@ -44,25 +44,25 @@ define i32 @test(i32 %a, i1 %c) {
; PRESELECTION-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; PRESELECTION-NEXT: liveins: $w0, $w1
; PRESELECTION-NEXT: {{ $}}
- ; PRESELECTION-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
- ; PRESELECTION-NEXT: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
- ; PRESELECTION-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 100000
- ; PRESELECTION-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:gpr(s32) = G_CONSTANT_FOLD_BARRIER [[C]]
- ; PRESELECTION-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; PRESELECTION-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; PRESELECTION-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[COPY1]], [[C2]]
- ; PRESELECTION-NEXT: G_BRCOND [[AND]](s32), %bb.3
+ ; PRESELECTION-NEXT: [[COPY:%[0-9]+]]:gpr(i32) = COPY $w0
+ ; PRESELECTION-NEXT: [[COPY1:%[0-9]+]]:gpr(i32) = COPY $w1
+ ; PRESELECTION-NEXT: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 100000
+ ; PRESELECTION-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:gpr(i32) = G_CONSTANT_FOLD_BARRIER [[C]]
+ ; PRESELECTION-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 0
+ ; PRESELECTION-NEXT: [[C2:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 1
+ ; PRESELECTION-NEXT: [[AND:%[0-9]+]]:gpr(i32) = G_AND [[COPY1]], [[C2]]
+ ; PRESELECTION-NEXT: G_BRCOND [[AND]](i32), %bb.3
; PRESELECTION-NEXT: G_BR %bb.2
; PRESELECTION-NEXT: {{ $}}
; PRESELECTION-NEXT: bb.2.common.ret:
- ; PRESELECTION-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI %7(s32), %bb.3, [[C1]](s32), %bb.1
- ; PRESELECTION-NEXT: $w0 = COPY [[PHI]](s32)
+ ; PRESELECTION-NEXT: [[PHI:%[0-9]+]]:gpr(i32) = G_PHI %7(i32), %bb.3, [[C1]](i32), %bb.1
+ ; PRESELECTION-NEXT: $w0 = COPY [[PHI]](i32)
; PRESELECTION-NEXT: RET_ReallyLR implicit $w0
; PRESELECTION-NEXT: {{ $}}
; PRESELECTION-NEXT: bb.3.cont:
; PRESELECTION-NEXT: successors: %bb.2(0x80000000)
; PRESELECTION-NEXT: {{ $}}
- ; PRESELECTION-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
+ ; PRESELECTION-NEXT: [[ADD:%[0-9]+]]:gpr(i32) = G_ADD [[COPY]], [[CONSTANT_FOLD_BARRIER]]
; PRESELECTION-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; PRESELECTION-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; PRESELECTION-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
index 74c60a1a3ecbd..18574893ce133 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
@@ -26,11 +26,11 @@ define void @asm_simple_register_clobber() {
define i64 @asm_register_early_clobber() {
; CHECK-LABEL: name: asm_register_early_clobber
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef-ec:GPR64common */, def early-clobber %0, {{[0-9]+}} /* regdef-ec:GPR64common */, def early-clobber %1, !0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY %0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $x0 = COPY [[ADD]](s64)
+ ; CHECK-NEXT: INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 3866635 /* regdef-ec:GPR64common */, def early-clobber %0, 3866635 /* regdef-ec:GPR64common */, def early-clobber %1, !0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY %0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY %1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x0 = COPY [[ADD]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
call { i64, i64 } asm sideeffect "mov $0, 7; mov $1, 7", "=&r,=&r"(), !srcloc !0
%asmresult = extractvalue { i64, i64 } %1, 0
@@ -43,8 +43,8 @@ define i32 @test_specific_register_output() nounwind ssp {
; CHECK-LABEL: name: test_specific_register_output
; CHECK: bb.1.entry:
; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $w0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = tail call i32 asm "mov ${0:w}, 7", "={w0}"() nounwind
@@ -54,9 +54,9 @@ entry:
define i32 @test_single_register_output() nounwind ssp {
; CHECK-LABEL: name: test_single_register_output
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %0
- ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY %0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind
@@ -66,9 +66,9 @@ entry:
define i64 @test_single_register_output_s64() nounwind ssp {
; CHECK-LABEL: name: test_single_register_output_s64
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"mov $0, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR64common */, def %0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY %0
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: INLINEASM &"mov $0, 7", 0 /* attdialect */, 3866634 /* regdef:GPR64common */, def %0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY %0
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = tail call i64 asm "mov $0, 7", "=r"() nounwind
@@ -79,11 +79,11 @@ entry:
define float @test_multiple_register_outputs_same() #0 {
; CHECK-LABEL: name: test_multiple_register_outputs_same
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:GPR32common */, def %1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)
+ ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %0, 2818058 /* regdef:GPR32common */, def %1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY %0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY %1
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $s0 = COPY [[FADD]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"()
%asmresult = extractvalue { float, float } %1, 0
@@ -96,10 +96,10 @@ define float @test_multiple_register_outputs_same() #0 {
define double @test_multiple_register_outputs_mixed() #0 {
; CHECK-LABEL: name: test_multiple_register_outputs_mixed
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:FPR64 */, def %1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %1
- ; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %0, 3670026 /* regdef:FPR64 */, def %1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY %0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY %1
+ ; CHECK-NEXT: $d0 = COPY [[COPY1]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1 = call { float, double } asm "mov $0, #0; mov $1, #0", "=r,=w"()
%asmresult = extractvalue { float, double } %1, 1
@@ -111,8 +111,8 @@ define i32 @test_specific_register_output_trunc() nounwind ssp {
; CHECK: bb.1.entry:
; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $x0
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = tail call i32 asm "mov ${0:w}, 7", "={x0}"() nounwind
@@ -125,11 +125,11 @@ define zeroext i8 @test_register_output_trunc(ptr %src) nounwind {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1
+ ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = tail call i8 asm "mov ${0:w}, 32", "=r"() nounwind
@@ -139,11 +139,11 @@ entry:
define float @test_vector_output() nounwind {
; CHECK-LABEL: name: test_vector_output
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: INLINEASM &"fmov ${0}.2s, #1.0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $d14
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d14
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: $s0 = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $d14
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x f32>), [[C]](i64)
+ ; CHECK-NEXT: $s0 = COPY [[EVEC]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%1 = tail call <2 x float> asm sideeffect "fmov ${0}.2s, #1.0", "={v14}"() nounwind
%2 = extractelement <2 x float> %1, i32 0
@@ -153,9 +153,9 @@ define float @test_vector_output() nounwind {
define void @test_input_register_imm() {
; CHECK-LABEL: name: test_input_register_imm
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](s64)
- ; CHECK-NEXT: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:GPR64common */, [[COPY]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](i64)
+ ; CHECK-NEXT: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 3866633 /* reguse:GPR64common */, [[COPY]]
; CHECK-NEXT: RET_ReallyLR
call void asm sideeffect "mov x0, $0", "r"(i64 42)
ret void
@@ -165,9 +165,9 @@ define void @test_input_register_imm() {
define i32 @test_boolean_imm_ext() {
; CHECK-LABEL: name: test_boolean_imm_ext
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: INLINEASM &"#TEST 42 + ${0:c} - .\0A\09", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 1
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
tail call void asm sideeffect "#TEST 42 + ${0:c} - .\0A\09", "i"(i1 true)
@@ -209,11 +209,11 @@ define zeroext i8 @test_input_register(ptr %src) nounwind {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0)
- ; CHECK-NEXT: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, {{[0-9]+}} /* reguse:GPR64common */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %1, 3866633 /* reguse:GPR64common */, [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY2]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(ptr %src) nounwind
@@ -226,9 +226,9 @@ define i32 @test_memory_constraint(ptr %a) nounwind {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
- ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 2818058 /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY %1
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1 = tail call i32 asm "ldr $0, $1", "=r,*m"(ptr elementtype(i32) %a)
ret i32 %1
@@ -237,14 +237,14 @@ define i32 @test_memory_constraint(ptr %a) nounwind {
define i16 @test_anyext_input() {
; CHECK-LABEL: name: test_anyext_input
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](i16)
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* reguse:GPR32common */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2818058 /* regdef:GPR32common */, def %0, 2818057 /* reguse:GPR32common */, [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1 = call i16 asm sideeffect "", "=r,r"(i16 1)
ret i16 %1
@@ -253,14 +253,14 @@ define i16 @test_anyext_input() {
define i16 @test_anyext_input_with_matching_constraint() {
; CHECK-LABEL: name: test_anyext_input_with_matching_constraint
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](i16)
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2818058 /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1 = call i16 asm sideeffect "", "=r,0"(i16 1)
ret i16 %1
@@ -269,11 +269,10 @@ define i16 @test_anyext_input_with_matching_constraint() {
define i64 @test_input_with_matching_constraint_to_physical_register() {
; CHECK-LABEL: name: test_input_with_matching_constraint_to_physical_register
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: %0:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %1:gpr64arg = COPY %0(s64)
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, %1(tied-def 3)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, [[C]](tied-def 3)(i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%1 = tail call i64 asm "", "={x2},0"(i64 0)
ret i64 %1
@@ -284,13 +283,13 @@ define void @test_indirectify_i32_value(i32 %x, i32 %y) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[COPY]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %stack.0)
+ ; CHECK-NEXT: G_STORE [[COPY]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %stack.0)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1
- ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %stack.1)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)
+ ; CHECK-NEXT: G_STORE [[COPY1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %stack.1)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 %x, i32 %y)
@@ -300,13 +299,13 @@ entry:
define void @test_indirectify_i32_constant() {
; CHECK-LABEL: name: test_indirectify_i32_constant
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %stack.0)
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %stack.0)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1
- ; CHECK-NEXT: G_STORE [[C1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %stack.1)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)
+ ; CHECK-NEXT: G_STORE [[C1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %stack.1)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 42, i32 0)
@@ -318,11 +317,11 @@ define void @test_indirectify_i16_value(i16 %val) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[FRAME_INDEX]](p0) :: (store (s16) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i16), [[FRAME_INDEX]](p0) :: (store (i16) into %stack.0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i16 %val)
@@ -332,10 +331,10 @@ entry:
define void @test_indirectify_i16_constant() {
; CHECK-LABEL: name: test_indirectify_i16_constant
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[C]](s16), [[FRAME_INDEX]](p0) :: (store (s16) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: G_STORE [[C]](i16), [[FRAME_INDEX]](p0) :: (store (i16) into %stack.0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i16 42)
@@ -347,10 +346,10 @@ define void @test_indirectify_i64_value(i64 %val) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[COPY]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: G_STORE [[COPY]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into %stack.0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i64 %val)
@@ -360,10 +359,10 @@ entry:
define void @test_indirectify_i64_constant() {
; CHECK-LABEL: name: test_indirectify_i64_constant
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: G_STORE [[C]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into %stack.0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i64 42)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
index e955b52e1643b..52f6d90e2c72b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
@@ -7,8 +7,8 @@ define i32 @load_invariant(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (invariant load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (invariant load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !invariant.load !0
ret i32 %load
@@ -20,8 +20,8 @@ define i32 @load_volatile_invariant(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (volatile invariant load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (volatile invariant load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load volatile i32, ptr %ptr, align 4, !invariant.load !0
ret i32 %load
@@ -33,8 +33,8 @@ define i32 @load_dereferenceable(ptr dereferenceable(4) %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4
ret i32 %load
@@ -46,8 +46,8 @@ define i32 @load_dereferenceable_invariant(ptr dereferenceable(4) %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (invariant load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (invariant load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !invariant.load !0
ret i32 %load
@@ -59,8 +59,8 @@ define i32 @load_nontemporal(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (non-temporal load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (non-temporal load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !nontemporal !0
ret i32 %load
@@ -72,8 +72,8 @@ define i32 @load_falkor_strided_access(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load (s32) from %ir.ptr)
- ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load (i32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !falkor.strided.access !0
ret i32 %load
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
index 91f4a480ccef2..e58874a0b2730 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
@@ -6,12 +6,12 @@ define void @local_escape() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: LOCAL_ESCAPE <mcsymbol .Llocal_escape$frame_escape_1>, %stack.1.b
; CHECK-NEXT: LOCAL_ESCAPE <mcsymbol .Llocal_escape$frame_escape_0>, %stack.0.a
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.a
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.b
- ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %ir.a)
- ; CHECK-NEXT: G_STORE [[C1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.b)
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %ir.a)
+ ; CHECK-NEXT: G_STORE [[C1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %ir.b)
; CHECK-NEXT: RET_ReallyLR
%a = alloca i32
%b = alloca i32, i32 2
@@ -27,12 +27,12 @@ define void @local_escape_insert_point() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: LOCAL_ESCAPE <mcsymbol .Llocal_escape_insert_point$frame_escape_2>, %stack.1.b
; CHECK-NEXT: LOCAL_ESCAPE <mcsymbol .Llocal_escape_insert_point$frame_escape_0>, %stack.0.a
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.a
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.b
- ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %ir.a)
- ; CHECK-NEXT: G_STORE [[C1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.b)
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %ir.a)
+ ; CHECK-NEXT: G_STORE [[C1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %ir.b)
; CHECK-NEXT: RET_ReallyLR
%a = alloca i32
%b = alloca i32, i32 2
@@ -49,9 +49,9 @@ define void @local_escape_strip_ptr_cast() {
; CHECK-LABEL: name: local_escape_strip_ptr_cast
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: LOCAL_ESCAPE <mcsymbol .Llocal_escape_strip_ptr_cast$frame_escape_0>, %stack.0.a
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.a
- ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %ir.a)
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %ir.a)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
index 8ff8349d15916..2e4d020cc495c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
@@ -1,8 +1,9 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
; CHECK-LABEL: name: store_max_address_space
; CHECK: %0:_(p16777215) = COPY $x0
-; CHECK: G_STORE %1(s32), %0(p16777215) :: (store (s32) into %ir.ptr, addrspace 16777215)
+; CHECK: G_STORE %1(i32), %0(p16777215) :: (store (i32) into %ir.ptr, addrspace 16777215)
define void @store_max_address_space(ptr addrspace(16777215) %ptr) {
store i32 0, ptr addrspace(16777215) %ptr
ret void
@@ -10,8 +11,8 @@ define void @store_max_address_space(ptr addrspace(16777215) %ptr) {
; CHECK-LABEL: name: store_max_address_space_vector
; CHECK: %0:_(<2 x p16777215>) = COPY $q0
-; CHECK: %1:_(p16777215) = G_EXTRACT_VECTOR_ELT %0(<2 x p16777215>), %2(s64)
-; CHECK: %1(p16777215) :: (store (s32) into %ir.elt0, addrspace 16777215)
+; CHECK: %1:_(p16777215) = G_EXTRACT_VECTOR_ELT %0(<2 x p16777215>), %2(i64)
+; CHECK: %1(p16777215) :: (store (i32) into %ir.elt0, addrspace 16777215)
define void @store_max_address_space_vector(<2 x ptr addrspace(16777215)> %vptr) {
%elt0 = extractelement <2 x ptr addrspace(16777215)> %vptr, i32 0
store i32 0, ptr addrspace(16777215) %elt0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
index fd12932cfd536..1d4f53d2ed4dd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
@@ -4,13 +4,14 @@
define void @copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: copy
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
@@ -19,13 +20,14 @@ entry:
define void @inline_copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: inline_copy
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
@@ -34,13 +36,14 @@ entry:
define void @copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: copy_volatile
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 0 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
@@ -49,13 +52,14 @@ entry:
define void @inline_copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: inline_copy_volatile
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
@@ -64,13 +68,14 @@ entry:
define void @tail_copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_copy
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
tail call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
@@ -79,13 +84,14 @@ entry:
define void @tail_inline_copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_inline_copy
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
tail call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
@@ -94,13 +100,14 @@ entry:
define void @tail_copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_copy_volatile
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64), 1 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
tail call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
@@ -109,13 +116,14 @@ entry:
define void @tail_inline_copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_inline_copy_volatile
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
- ; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](i64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
tail call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll
index 32c742316b872..af07caa67539d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-nneg-disjoint.ll
@@ -6,10 +6,10 @@ define i32 @call_nneg(i16 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: %2:_(s32) = nneg G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY %2(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = nneg G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = zext nneg i16 %a to i32
@@ -21,10 +21,10 @@ define i32 @call_not_nneg(i16 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = zext i16 %a to i32
@@ -36,10 +36,10 @@ define i32 @call_disjoint(i32 %a, i32 %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: %2:_(s32) = disjoint G_OR [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $w0 = COPY %2(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = or disjoint i32 %a, %b
@@ -51,10 +51,10 @@ define i32 @call_add(i32 %a, i32 %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = nsw G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = add nsw i32 %a, %b
@@ -66,10 +66,10 @@ define i32 @call_not_disjoint(i32 %a, i32 %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $w0 = COPY [[OR]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = or i32 %a, %b
@@ -81,10 +81,10 @@ define <2 x i64> @call_not_disjoint_vector(<2 x i64> %a, <2 x i64> %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[OR]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i64>) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[OR]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%result = or <2 x i64> %a, %b
@@ -96,10 +96,10 @@ define <2 x i64> @call_disjoint_vector(<2 x i64> %a, <2 x i64> %b) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: %2:_(<2 x s64>) = disjoint G_OR [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY %2(<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i64>) = disjoint G_OR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[OR]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%result = or disjoint <2 x i64> %a, %b
@@ -111,9 +111,9 @@ define <2 x i64> @call_nneg_vector(<2 x i32> %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: %1:_(<2 x s64>) = nneg G_ZEXT [[COPY]](<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY %1(<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x i64>) = nneg G_ZEXT [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%result = zext nneg <2 x i32> %a to <2 x i64>
@@ -125,9 +125,9 @@ define <2 x i64> @call_not_nneg_vector(<2 x i32> %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%result = zext <2 x i32> %a to <2 x i64>
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
index 4ab347c37f0d7..3ab10edc726ff 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
@@ -6,9 +6,9 @@ define i64 @expect_i64(i64 %arg0) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: $x0 = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[COPY]](i64)
+ ; CHECK-NEXT: $x0 = COPY [[COPY1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%expval = call i64 @llvm.expect.i64(i64 %arg0, i64 1)
ret i64 %expval
@@ -19,9 +19,9 @@ define i64 @expect_with_probability_i64(i64 %arg0) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: $x0 = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[COPY]](i64)
+ ; CHECK-NEXT: $x0 = COPY [[COPY1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%expval = call i64 @llvm.expect.with.probability.i64(i64 %arg0, i64 1, double 0.5)
ret i64 %expval
@@ -35,7 +35,7 @@ define ptr @ptr_annotate(ptr %arg0, ptr %arg1, ptr %arg2, i32 %arg3) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY4]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -51,9 +51,9 @@ define i32 @annotation(i32 %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[COPY]](i32)
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%call = call i32 @llvm.annotation.i32(i32 %a, ptr @.str, ptr @.str1, i32 2)
ret i32 %call
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
index 78b0c720d51a3..07d406726e253 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
@@ -13,10 +13,10 @@ define <1 x ptr> @one_elt_vector_ptr_add_non_vector_idx(<1 x ptr> %vec) {
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $d0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[C]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $d0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -26,8 +26,8 @@ define <1 x ptr> @one_elt_vector_ptr_add_non_vector_idx(<1 x ptr> %vec) {
; CHECK-CI-NEXT: liveins: $d0
; CHECK-CI-NEXT: {{ $}}
; CHECK-CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $d0
- ; CHECK-CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-CI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-CI-NEXT: $d0 = COPY [[PTR_ADD]](p0)
; CHECK-CI-NEXT: RET_ReallyLR implicit $d0
%ptr_add = getelementptr i8, <1 x ptr> %vec, <1 x i32> <i32 1>
@@ -43,10 +43,10 @@ define <1 x ptr> @one_elt_vector_ptr_add_non_vector_ptr(ptr %vec) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[C]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $d0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -56,8 +56,8 @@ define <1 x ptr> @one_elt_vector_ptr_add_non_vector_ptr(ptr %vec) {
; CHECK-CI-NEXT: liveins: $x0
; CHECK-CI-NEXT: {{ $}}
; CHECK-CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-CI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-CI-NEXT: $d0 = COPY [[PTR_ADD]](p0)
; CHECK-CI-NEXT: RET_ReallyLR implicit $d0
%ptr_add = getelementptr i8, ptr %vec, <1 x i32> <i32 1>
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
index c791e35946f72..d7d5bdf6d1c22 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
@@ -6,11 +6,11 @@ define float @fadd_seq(float %start, <4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q1, $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_SEQ_FADD:%[0-9]+]]:_(s32) = G_VECREDUCE_SEQ_FADD [[COPY]](s32), [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_SEQ_FADD]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_SEQ_FADD:%[0-9]+]]:_(f32) = G_VECREDUCE_SEQ_FADD [[COPY]](f32), [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_SEQ_FADD]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %vec)
ret float %res
@@ -21,11 +21,12 @@ define float @fadd_seq_scalar(float %start, <1 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d1, $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[UV]]
- ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<2 x f32>)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[UV]]
+ ; CHECK-NEXT: $s0 = COPY [[FADD]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fadd.v1f32(float %start, <1 x float> %vec)
ret float %res
@@ -36,12 +37,12 @@ define float @fadd_fast(float %start, <4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q1, $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FADD:%[0-9]+]]:_(s32) = reassoc G_VECREDUCE_FADD [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = reassoc G_FADD [[COPY]], [[VECREDUCE_FADD]]
- ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FADD:%[0-9]+]]:_(f32) = reassoc G_VECREDUCE_FADD [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = reassoc G_FADD [[COPY]], [[VECREDUCE_FADD]]
+ ; CHECK-NEXT: $s0 = COPY [[FADD]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %vec)
ret float %res
@@ -52,12 +53,14 @@ define double @fmul_seq(double %start, <4 x double> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0, $q1, $q2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_SEQ_FMUL:%[0-9]+]]:_(s64) = G_VECREDUCE_SEQ_FMUL [[COPY]](s64), [[CONCAT_VECTORS]](<4 x s64>)
- ; CHECK-NEXT: $d0 = COPY [[VECREDUCE_SEQ_FMUL]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f64>) = G_CONCAT_VECTORS [[BITCAST]](<2 x f64>), [[BITCAST1]](<2 x f64>)
+ ; CHECK-NEXT: [[VECREDUCE_SEQ_FMUL:%[0-9]+]]:_(f64) = G_VECREDUCE_SEQ_FMUL [[COPY]](f64), [[CONCAT_VECTORS]](<4 x f64>)
+ ; CHECK-NEXT: $d0 = COPY [[VECREDUCE_SEQ_FMUL]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%res = call double @llvm.vector.reduce.fmul.v4f64(double %start, <4 x double> %vec)
ret double %res
@@ -68,10 +71,10 @@ define double @fmul_seq_scalar(double %start, <1 x double> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $d0 = COPY [[FMUL]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $d1
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[FMUL]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%res = call double @llvm.vector.reduce.fmul.v1f64(double %start, <1 x double> %vec)
ret double %res
@@ -82,13 +85,15 @@ define double @fmul_fast(double %start, <4 x double> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0, $q1, $q2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMUL:%[0-9]+]]:_(s64) = reassoc G_VECREDUCE_FMUL [[CONCAT_VECTORS]](<4 x s64>)
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = reassoc G_FMUL [[COPY]], [[VECREDUCE_FMUL]]
- ; CHECK-NEXT: $d0 = COPY [[FMUL]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f64>) = G_CONCAT_VECTORS [[BITCAST]](<2 x f64>), [[BITCAST1]](<2 x f64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMUL:%[0-9]+]]:_(f64) = reassoc G_VECREDUCE_FMUL [[CONCAT_VECTORS]](<4 x f64>)
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f64) = reassoc G_FMUL [[COPY]], [[VECREDUCE_FMUL]]
+ ; CHECK-NEXT: $d0 = COPY [[FMUL]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%res = call reassoc double @llvm.vector.reduce.fmul.v4f64(double %start, <4 x double> %vec)
ret double %res
@@ -99,10 +104,10 @@ define float @fmax(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAX [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMAX]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMAX:%[0-9]+]]:_(f32) = G_VECREDUCE_FMAX [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMAX]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %vec)
ret float %res
@@ -113,10 +118,10 @@ define float @fmin(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_FMIN [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(f32) = G_VECREDUCE_FMIN [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %vec)
ret float %res
@@ -127,10 +132,10 @@ define float @fmin_nnan(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = nnan G_VECREDUCE_FMIN [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(f32) = nnan G_VECREDUCE_FMIN [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %vec)
ret float %res
@@ -141,10 +146,10 @@ define float @fmaximum(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMAXIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAXIMUM [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMAXIMUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMAXIMUM:%[0-9]+]]:_(f32) = G_VECREDUCE_FMAXIMUM [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMAXIMUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %vec)
ret float %res
@@ -155,10 +160,10 @@ define float @fminimum(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(f32) = G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %vec)
ret float %res
@@ -169,10 +174,10 @@ define float @fminimum_nnan(<4 x float> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(s32) = nnan G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(f32) = nnan G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%res = call nnan float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %vec)
ret float %res
@@ -183,9 +188,9 @@ define i32 @add(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(i32) = G_VECREDUCE_ADD [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -196,9 +201,9 @@ define i32 @mul(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_MUL:%[0-9]+]]:_(s32) = G_VECREDUCE_MUL [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_MUL]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_MUL:%[0-9]+]]:_(i32) = G_VECREDUCE_MUL [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_MUL]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -209,9 +214,9 @@ define i32 @and(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_AND:%[0-9]+]]:_(s32) = G_VECREDUCE_AND [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_AND]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_AND:%[0-9]+]]:_(i32) = G_VECREDUCE_AND [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_AND]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -222,9 +227,9 @@ define i32 @or(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_OR:%[0-9]+]]:_(s32) = G_VECREDUCE_OR [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_OR]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_OR:%[0-9]+]]:_(i32) = G_VECREDUCE_OR [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_OR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -235,9 +240,9 @@ define i32 @xor(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_XOR:%[0-9]+]]:_(s32) = G_VECREDUCE_XOR [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_XOR]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_XOR:%[0-9]+]]:_(i32) = G_VECREDUCE_XOR [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_XOR]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -248,9 +253,9 @@ define i32 @smax(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_SMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_SMAX [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_SMAX]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_SMAX:%[0-9]+]]:_(i32) = G_VECREDUCE_SMAX [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_SMAX]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -261,9 +266,9 @@ define i32 @smin(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_SMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_SMIN [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_SMIN]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_SMIN:%[0-9]+]]:_(i32) = G_VECREDUCE_SMIN [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_SMIN]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -274,9 +279,9 @@ define i32 @umax(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_UMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_UMAX [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_UMAX]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_UMAX:%[0-9]+]]:_(i32) = G_VECREDUCE_UMAX [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_UMAX]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %vec)
ret i32 %res
@@ -287,9 +292,9 @@ define i32 @umin(<4 x i32> %vec) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[VECREDUCE_UMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_UMIN [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_UMIN]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[VECREDUCE_UMIN:%[0-9]+]]:_(i32) = G_VECREDUCE_UMIN [[COPY]](<4 x i32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_UMIN]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %vec)
ret i32 %res
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll
index 69cd6ce87b5c6..471fb5ad0017f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll
@@ -6,10 +6,10 @@ define { half, half } @test_sincos_f16(half %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $h0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(s16), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $h0 = COPY [[FSINCOS]](s16)
- ; CHECK-NEXT: $h1 = COPY [[FSINCOS1]](s16)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f16) = COPY $h0
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(f16), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
+ ; CHECK-NEXT: $h0 = COPY [[FSINCOS]](f16)
+ ; CHECK-NEXT: $h1 = COPY [[FSINCOS1]](f16)
; CHECK-NEXT: RET_ReallyLR implicit $h0, implicit $h1
%result = call { half, half } @llvm.sincos.f16(half %a)
ret { half, half } %result
@@ -20,16 +20,16 @@ define { <2 x half>, <2 x half> } @test_sincos_v2f16(<2 x half> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x s16>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[UV]]
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[FSINCOS]](<2 x s16>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV2]](s16), [[UV3]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[FSINCOS1]](<2 x s16>)
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV4]](s16), [[UV5]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
- ; CHECK-NEXT: $d1 = COPY [[BUILD_VECTOR1]](<4 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x f16>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[UV]]
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f16), [[UV3:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[FSINCOS]](<2 x f16>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UV2]](f16), [[UV3]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(f16), [[UV5:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[FSINCOS1]](<2 x f16>)
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UV4]](f16), [[UV5]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x f16>)
+ ; CHECK-NEXT: $d1 = COPY [[BUILD_VECTOR1]](<4 x f16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%result = call { <2 x half>, <2 x half> } @llvm.sincos.v2f16(<2 x half> %a)
ret { <2 x half>, <2 x half> } %result
@@ -40,10 +40,10 @@ define { float, float } @test_sincos_f32(float %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(s32), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $s0 = COPY [[FSINCOS]](s32)
- ; CHECK-NEXT: $s1 = COPY [[FSINCOS1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(f32), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
+ ; CHECK-NEXT: $s0 = COPY [[FSINCOS]](f32)
+ ; CHECK-NEXT: $s1 = COPY [[FSINCOS1]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0, implicit $s1
%result = call { float, float } @llvm.sincos.f32(float %a)
ret { float, float } %result
@@ -54,10 +54,11 @@ define { <2 x float>, <2 x float> } @test_sincos_v2f32(<2 x float> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x s32>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $d0 = COPY [[FSINCOS]](<2 x s32>)
- ; CHECK-NEXT: $d1 = COPY [[FSINCOS1]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x f32>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[BITCAST]]
+ ; CHECK-NEXT: $d0 = COPY [[FSINCOS]](<2 x f32>)
+ ; CHECK-NEXT: $d1 = COPY [[FSINCOS1]](<2 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%result = call { <2 x float>, <2 x float> } @llvm.sincos.v2f32(<2 x float> %a)
ret { <2 x float>, <2 x float> } %result
@@ -68,10 +69,10 @@ define { double, double } @test_sincos_f64(double %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(s64), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $d0 = COPY [[FSINCOS]](s64)
- ; CHECK-NEXT: $d1 = COPY [[FSINCOS1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(f64), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
+ ; CHECK-NEXT: $d0 = COPY [[FSINCOS]](f64)
+ ; CHECK-NEXT: $d1 = COPY [[FSINCOS1]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
%result = call { double, double } @llvm.sincos.f64(double %a)
ret { double, double } %result
@@ -82,10 +83,11 @@ define { <2 x double>, <2 x double> } @test_sincos_v2f64(<2 x double> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x s64>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $q0 = COPY [[FSINCOS]](<2 x s64>)
- ; CHECK-NEXT: $q1 = COPY [[FSINCOS1]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(<2 x f64>), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[BITCAST]]
+ ; CHECK-NEXT: $q0 = COPY [[FSINCOS]](<2 x f64>)
+ ; CHECK-NEXT: $q1 = COPY [[FSINCOS1]](<2 x f64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%result = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> %a)
ret { <2 x double>, <2 x double> } %result
@@ -96,10 +98,10 @@ define { fp128, fp128 } @test_sincos_f128(fp128 %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(s128), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $q0 = COPY [[FSINCOS]](s128)
- ; CHECK-NEXT: $q1 = COPY [[FSINCOS1]](s128)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f128) = COPY $q0
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(f128), [[FSINCOS1:%[0-9]+]]:_ = G_FSINCOS [[COPY]]
+ ; CHECK-NEXT: $q0 = COPY [[FSINCOS]](f128)
+ ; CHECK-NEXT: $q1 = COPY [[FSINCOS1]](f128)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%result = call { fp128, fp128 } @llvm.sincos.f16(fp128 %a)
ret { fp128, fp128 } %result
@@ -110,10 +112,10 @@ define { float, float } @test_sincos_f32_afn(float %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(s32), [[FSINCOS1:%[0-9]+]]:_ = afn G_FSINCOS [[COPY]]
- ; CHECK-NEXT: $s0 = COPY [[FSINCOS]](s32)
- ; CHECK-NEXT: $s1 = COPY [[FSINCOS1]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[FSINCOS:%[0-9]+]]:_(f32), [[FSINCOS1:%[0-9]+]]:_ = afn G_FSINCOS [[COPY]]
+ ; CHECK-NEXT: $s0 = COPY [[FSINCOS]](f32)
+ ; CHECK-NEXT: $s1 = COPY [[FSINCOS1]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0, implicit $s1
%result = call afn { float, float } @llvm.sincos.f32(float %a)
ret { float, float } %result
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll
index ef74cdb4aada3..749c221651f81 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll
@@ -7,13 +7,14 @@ target triple = "aarch64-apple-ios"
define hidden fastcc <4 x float> @foo(<4 x i64> %arg) unnamed_addr #0 {
; CHECK-LABEL: name: foo
; CHECK: bb.1.bb:
- ; CHECK: liveins: $q0, $q1
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>)
- ; CHECK: [[UITOFP:%[0-9]+]]:_(<4 x s32>) = G_UITOFP [[CONCAT_VECTORS]](<4 x s64>)
- ; CHECK: $q0 = COPY [[UITOFP]](<4 x s32>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: liveins: $q0, $q1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x i64>) = G_CONCAT_VECTORS [[COPY]](<2 x i64>), [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(<4 x f32>) = G_UITOFP [[CONCAT_VECTORS]](<4 x i64>)
+ ; CHECK-NEXT: $q0 = COPY [[UITOFP]](<4 x f32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
bb:
%tmp = uitofp <4 x i64> %arg to <4 x float>
ret <4 x float> %tmp
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
index 92ef424a9283e..f6421dfc2c9e2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
@@ -7,21 +7,22 @@
define i3 @bug47619(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i3 %arg8) {
; CHECK-LABEL: name: bug47619
; CHECK: bb.1.bb:
- ; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s32) from %fixed-stack.0, align 16)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s3) = G_TRUNC [[LOAD]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s3)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i32) from %fixed-stack.0, align 16)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i3) = G_TRUNC [[LOAD]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i3)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
bb:
ret i3 %arg8
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
index d8fcf8161baf4..256ab9c2bd705 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
@@ -15,16 +15,16 @@ define void @stack_passed_i64(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3, i64 %ar
i64 %arg7, i64 %arg8, ptr byval(i64) %arg9, ptr byval(i64) align(8) %arg10) {
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.2, align 16)
+ ; CHECK: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.2, align 16)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[COPY8:%[0-9]+]]:_(p0) = COPY [[FRAME_INDEX1]](p0)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[COPY9:%[0-9]+]]:_(p0) = COPY [[FRAME_INDEX2]](p0)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[COPY8]](p0) :: (load (s64) from %ir.arg9)
- ; CHECK: [[ADD0:%[0-9]+]]:_(s64) = G_ADD [[LOAD1]], [[LOAD]]
- ; CHECK: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[COPY9]](p0) :: (dereferenceable load (s64) from %ir.arg10)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD0]], [[LOAD2]]
- ; CHECK: G_STORE [[ADD1]](s64), [[COPY8]](p0) :: (volatile store (s64) into %ir.arg9)
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[COPY8]](p0) :: (load (i64) from %ir.arg9)
+ ; CHECK: [[ADD0:%[0-9]+]]:_(i64) = G_ADD [[LOAD1]], [[LOAD]]
+ ; CHECK: [[LOAD2:%[0-9]+]]:_(i64) = G_LOAD [[COPY9]](p0) :: (dereferenceable load (i64) from %ir.arg10)
+ ; CHECK: [[ADD1:%[0-9]+]]:_(i64) = G_ADD [[ADD0]], [[LOAD2]]
+ ; CHECK: G_STORE [[ADD1]](i64), [[COPY8]](p0) :: (volatile store (i64) into %ir.arg9)
; CHECK: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
index 00ad8fec95638..5be17b2b71d02 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
@@ -22,12 +22,12 @@ define void @test() nounwind ssp {
; NO_TRAP_UNREACHABLE-NEXT: $x0 = COPY [[FRAME_INDEX1]](p0)
; NO_TRAP_UNREACHABLE-NEXT: BL @callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def $w0
; NO_TRAP_UNREACHABLE-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; NO_TRAP_UNREACHABLE-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; NO_TRAP_UNREACHABLE-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; NO_TRAP_UNREACHABLE-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
- ; NO_TRAP_UNREACHABLE-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (s64) from %stack.0.StackGuardSlot)
+ ; NO_TRAP_UNREACHABLE-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (i64) from %stack.0.StackGuardSlot)
; NO_TRAP_UNREACHABLE-NEXT: [[LOAD_STACK_GUARD2:%[0-9]+]]:gpr64sp(s64) = LOAD_STACK_GUARD :: (dereferenceable invariant load (p0) from @__stack_chk_guard)
- ; NO_TRAP_UNREACHABLE-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
- ; NO_TRAP_UNREACHABLE-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; NO_TRAP_UNREACHABLE-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
+ ; NO_TRAP_UNREACHABLE-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; NO_TRAP_UNREACHABLE-NEXT: G_BR %bb.2
; NO_TRAP_UNREACHABLE-NEXT: {{ $}}
; NO_TRAP_UNREACHABLE-NEXT: bb.3.entry:
@@ -53,12 +53,12 @@ define void @test() nounwind ssp {
; TRAP_UNREACHABLE-NEXT: $x0 = COPY [[FRAME_INDEX1]](p0)
; TRAP_UNREACHABLE-NEXT: BL @callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def $w0
; TRAP_UNREACHABLE-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; TRAP_UNREACHABLE-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; TRAP_UNREACHABLE-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; TRAP_UNREACHABLE-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
- ; TRAP_UNREACHABLE-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (s64) from %stack.0.StackGuardSlot)
+ ; TRAP_UNREACHABLE-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX2]](p0) :: (volatile load (i64) from %stack.0.StackGuardSlot)
; TRAP_UNREACHABLE-NEXT: [[LOAD_STACK_GUARD2:%[0-9]+]]:gpr64sp(s64) = LOAD_STACK_GUARD :: (dereferenceable invariant load (p0) from @__stack_chk_guard)
- ; TRAP_UNREACHABLE-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
- ; TRAP_UNREACHABLE-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; TRAP_UNREACHABLE-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD_STACK_GUARD2]](s64), [[LOAD]]
+ ; TRAP_UNREACHABLE-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; TRAP_UNREACHABLE-NEXT: G_BR %bb.2
; TRAP_UNREACHABLE-NEXT: {{ $}}
; TRAP_UNREACHABLE-NEXT: bb.3.entry:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
index 08a1ac3135bd2..164435ee8f52d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
@@ -4,8 +4,8 @@
define <vscale x 2 x i64> @call_step_vector_i64() {
; CHECK-LABEL: name: call_step_vector_i64
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_STEP_VECTOR i64 1
- ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 2 x i64>) = G_STEP_VECTOR i64 1
+ ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $z0
entry:
%steps = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()
@@ -15,8 +15,8 @@ entry:
define <vscale x 4 x i32> @call_step_vector_i32() {
; CHECK-LABEL: name: call_step_vector_i32
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_STEP_VECTOR i32 1
- ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 4 x i32>) = G_STEP_VECTOR i32 1
+ ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $z0
entry:
%steps = call <vscale x 4 x i32> @llvm.stepvector.nxv4i32()
@@ -26,8 +26,8 @@ entry:
define <vscale x 8 x i16> @call_step_vector_i16() {
; CHECK-LABEL: name: call_step_vector_i16
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_STEP_VECTOR i16 1
- ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 8 x i16>) = G_STEP_VECTOR i16 1
+ ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $z0
entry:
%steps = call <vscale x 8 x i16> @llvm.stepvector.nxv8i16()
@@ -37,8 +37,8 @@ entry:
define <vscale x 16 x i8> @call_step_vector_i8() {
; CHECK-LABEL: name: call_step_vector_i8
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_STEP_VECTOR i8 1
- ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[STEP_VECTOR:%[0-9]+]]:_(<vscale x 16 x i8>) = G_STEP_VECTOR i8 1
+ ; CHECK-NEXT: $z0 = COPY [[STEP_VECTOR]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $z0
entry:
%steps = call <vscale x 16 x i8> @llvm.stepvector.nxv16i8()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
index baed1263008da..a9521bc852644 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
@@ -7,8 +7,8 @@ define void @store_nontemporal(ptr dereferenceable(4) %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (non-temporal store (s32) into %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[COPY]](p0) :: (non-temporal store (i32) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
store i32 0, ptr %ptr, align 4, !nontemporal !0
ret void
@@ -20,8 +20,8 @@ define void @store_dereferenceable(ptr dereferenceable(4) %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[COPY]](p0) :: (store (i32) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
store i32 0, ptr %ptr, align 4
ret void
@@ -33,8 +33,8 @@ define void @store_volatile_dereferenceable(ptr dereferenceable(4) %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (volatile store (s32) into %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[COPY]](p0) :: (volatile store (i32) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
store volatile i32 0, ptr %ptr, align 4
ret void
@@ -46,8 +46,8 @@ define void @store_falkor_strided_access(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store (s32) into %ir.ptr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: G_STORE [[C]](i32), [[COPY]](p0) :: ("aarch64-strided-access" store (i32) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
store i32 0, ptr %ptr, align 4, !falkor.strided.access !0
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
index 862e0f6022395..546aa0f874e64 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
@@ -6,13 +6,13 @@ define i32 @extract_v4i32_vector_insert_const(<4 x i32> %a, <2 x i32> %b, i32 %c
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $q0, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x s32>), 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x i32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x i32>), 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x i32>), [[C]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[EVEC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> %a, <2 x i32> %b, i64 0)
@@ -25,15 +25,18 @@ define double @extract_v4double_vector_insert_const(<4 x double> %a, <2 x double
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1, $q2, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s64>) = G_INSERT_SUBVECTOR [[CONCAT_VECTORS]], [[COPY2]](<2 x s64>), 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s64>), [[C]](s64)
- ; CHECK-NEXT: $d0 = COPY [[EVEC]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f64>) = G_CONCAT_VECTORS [[BITCAST]](<2 x f64>), [[BITCAST1]](<2 x f64>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f64>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x f64>) = G_INSERT_SUBVECTOR [[CONCAT_VECTORS]], [[BITCAST2]](<2 x f64>), 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f64) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x f64>), [[C]](i64)
+ ; CHECK-NEXT: $d0 = COPY [[EVEC]](f64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
entry:
%vector = call <4 x double> @llvm.vector.insert.v4f64.v2f64(<4 x double> %a, <2 x double> %b, i64 0)
@@ -46,14 +49,15 @@ define float @extract_v4float_vector_insert_const(<4 x float> %a, <2 x float> %b
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $q0, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[BITCAST]], [[COPY1]](<2 x s32>), 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: $s0 = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x f32>) = G_INSERT_SUBVECTOR [[BITCAST]], [[BITCAST1]](<2 x f32>), 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(f32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x f32>), [[C]](i64)
+ ; CHECK-NEXT: $s0 = COPY [[EVEC]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
entry:
%vector = call <4 x float> @llvm.vector.insert.v4f32.v2f32(<4 x float> %a, <2 x float> %b, i64 0)
@@ -66,13 +70,13 @@ define i32 @extract_v4i32_vector_insert(<4 x i32> %a, <2 x i32> %b, i32 %c) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $q0, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x s32>), 0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[ZEXT]](s64)
- ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x i32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x i32>), 0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY2]](i32)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x i32>), [[ZEXT]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[EVEC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> %a, <2 x i32> %b, i64 0)
@@ -85,13 +89,13 @@ define i32 @extract_v4i32_vector_extract(<4 x i32> %a, <2 x i32> %b, i32 %c) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $q0, $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<4 x s32>), 0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[EXTRACT_SUBVECTOR]](<4 x s32>), [[ZEXT]](s64)
- ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<4 x i32>) = G_EXTRACT_SUBVECTOR [[COPY]](<4 x i32>), 0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY2]](i32)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[EXTRACT_SUBVECTOR]](<4 x i32>), [[ZEXT]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[EVEC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <4 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %a, i64 0)
@@ -104,13 +108,13 @@ define i32 @extract_v4i32_vector_extract_const(<vscale x 4 x i32> %a, i32 %c, pt
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $x1, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 4 x s32>), 0
- ; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 4 x s32>), [[COPY2]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x i32>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 4 x i32>), 0
+ ; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 4 x i32>), [[COPY2]](p0) :: (store (<vscale x 4 x i32>) into %ir.p)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <vscale x 4 x i32> @llvm.vector.extract(<vscale x 4 x i32> %a, i64 0)
@@ -123,13 +127,13 @@ define i32 @extract_v2double_vector_extract_const(<vscale x 2 x double> %a, i32
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $x1, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 2 x s64>), 0
- ; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 2 x s64>), [[COPY2]](p0) :: (store (<vscale x 2 x s64>) into %ir.p)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x f64>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 2 x f64>), 0
+ ; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 2 x f64>), [[COPY2]](p0) :: (store (<vscale x 2 x f64>) into %ir.p)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <vscale x 2 x double> @llvm.vector.extract(<vscale x 2 x double> %a, i64 0)
@@ -142,14 +146,14 @@ define i32 @extract_v4i32_vector_insert_const_vscale(<vscale x 4 x i32> %a, <vsc
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $w0, $x1, $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<vscale x 4 x s32>), 0
- ; CHECK-NEXT: G_STORE [[INSERT_SUBVECTOR]](<vscale x 4 x s32>), [[COPY3]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x i32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<vscale x 4 x i32>), 0
+ ; CHECK-NEXT: G_STORE [[INSERT_SUBVECTOR]](<vscale x 4 x i32>), [[COPY3]](p0) :: (store (<vscale x 4 x i32>) into %ir.p)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i64 0)
@@ -162,13 +166,13 @@ define i32 @extract_v4i32_vector_extract_const_illegal_fixed(<4 x i32> %a, ptr %
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: G_STORE [[EVEC]](s32), [[COPY1]](p0) :: (store (s32) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x i32>), [[C]](i64)
+ ; CHECK-NEXT: G_STORE [[EVEC]](i32), [[COPY1]](p0) :: (store (i32) into %ir.p, align 16)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x i32> @llvm.vector.extract(<4 x i32> %a, i64 0)
@@ -181,15 +185,15 @@ define i32 @extract_v4i32_vector_extract_const_illegal_scalable(<vscale x 4 x i3
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[VSCALE]], [[C]]
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s32>), [[MUL]](s64)
- ; CHECK-NEXT: G_STORE [[EVEC]](s32), [[COPY1]](p0) :: (store (s32) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x i32>), [[MUL]](s64)
+ ; CHECK-NEXT: G_STORE [[EVEC]](i32), [[COPY1]](p0) :: (store (i32) into %ir.p, align 16)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x i32> @llvm.vector.extract(<vscale x 4 x i32> %a, i64 0)
@@ -202,18 +206,18 @@ define i32 @extract_v4i32_vector_insert_const_illegal_scalable(<vscale x 4 x i32
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $w0, $x1, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[VSCALE]], [[C]]
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](s32), [[MUL]](s64)
- ; CHECK-NEXT: G_STORE [[IVEC]](<vscale x 4 x s32>), [[COPY3]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x i32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](i32), [[MUL]](s64)
+ ; CHECK-NEXT: G_STORE [[IVEC]](<vscale x 4 x i32>), [[COPY3]](p0) :: (store (<vscale x 4 x i32>) into %ir.p)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %a, <1 x i32> %b, i64 0)
@@ -226,16 +230,16 @@ define i32 @extract_v4i32_vector_insert_const_fixed(<4 x i32> %a, <1 x i32> %b,
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d1, $q0, $w0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](s32), [[C]](s64)
- ; CHECK-NEXT: G_STORE [[IVEC]](<4 x s32>), [[COPY3]](p0) :: (store (<4 x s32>) into %ir.p)
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](i32), [[C]](i64)
+ ; CHECK-NEXT: G_STORE [[IVEC]](<4 x i32>), [[COPY3]](p0) :: (store (<4 x i32>) into %ir.p)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <4 x i32> @llvm.vector.insert.v4i32.v4i32(<4 x i32> %a, <1 x i32> %b, i64 0)
@@ -248,16 +252,16 @@ define i32 @extract_v4i32_vector_insert_const_fixed_illegal(<1 x i32> %a, <1 x i
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0, $d1, $w0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: G_STORE [[COPY4]](s32), [[COPY3]](p0) :: (store (s32) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY [[UV]](i32)
+ ; CHECK-NEXT: G_STORE [[COPY4]](i32), [[COPY3]](p0) :: (store (i32) into %ir.p, align 16)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x i32> @llvm.vector.insert.v1i32.v4i32(<1 x i32> %a, <1 x i32> %b, i64 0)
@@ -272,12 +276,12 @@ define i32 @extract_v4ptr_vector_insert_const_fixed_illegal(<1 x ptr> %a, <1 x p
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: G_STORE [[COPY4]](p0), [[COPY3]](p0) :: (store (p0) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x ptr> @llvm.vector.insert.v1ptr.v4ptr(<1 x ptr> %a, <1 x ptr> %b, i64 0)
@@ -290,16 +294,18 @@ define i32 @extract_v4ifloat_vector_insert_const_fixed_illegal(<1 x float> %a, <
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $d0, $d1, $s2, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<2 x f32>)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY1]](<2 x i32>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST1]](<2 x f32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK-NEXT: G_STORE [[COPY4]](s32), [[COPY3]](p0) :: (store (s32) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY [[UV]](f32)
+ ; CHECK-NEXT: G_STORE [[COPY4]](f32), [[COPY3]](p0) :: (store (f32) into %ir.p, align 16)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x float> @llvm.vector.insert.v1f32.v4f32(<1 x float> %a, <1 x float> %b, i64 0)
@@ -316,10 +322,10 @@ define i32 @extract_v4iptr_vector_insert_const_fixed_illegal(<1 x ptr> %a, <1 x
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $d1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: G_STORE [[COPY4]](p0), [[COPY3]](p0) :: (store (p0) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <1 x ptr> @llvm.vector.insert.v1ptr.v4ptr(<1 x ptr> %a, <1 x ptr> %b, i64 0)
@@ -332,22 +338,22 @@ define i32 @extract_v4iptr_vector_insert_const_fixed_legal(<4 x ptr> %a, <4 x pt
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3, $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<2 x p0>), [[BITCAST1]](<2 x p0>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY2]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY3]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i64>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i64>) = COPY $q3
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY2]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY3]](<2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x p0>), [[BITCAST3]](<2 x p0>)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x p0>) = G_INSERT_SUBVECTOR [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]](<4 x p0>), 0
; CHECK-NEXT: G_STORE [[INSERT_SUBVECTOR]](<4 x p0>), [[COPY5]](p0) :: (store (<4 x p0>) into %ir.p, align 16)
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%vector = call <4 x ptr> @llvm.vector.insert.v4ptr.v4ptr(<4 x ptr> %a, <4 x ptr> %b, i64 0)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
index 1fa21bfb733e8..09efe53912453 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
@@ -6,9 +6,9 @@ define void @scmp_i32(i32 %arg1, i32 %arg2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(s4) = G_SCMP [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(i4) = G_SCMP [[COPY]](i32), [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%res4 = call i4 @llvm.scmp.i4.i32(i32 %arg1, i32 %arg2)
ret void
@@ -19,9 +19,9 @@ define void @scmp_4_32i(<4 x i32> %arg1, <4 x i32> %arg2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(<4 x s32>) = G_SCMP [[COPY]](<4 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(<4 x i32>) = G_SCMP [[COPY]](<4 x i32>), [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%res4 = call <4 x i32> @llvm.scmp.v4i32.i32(<4 x i32> %arg1, <4 x i32> %arg2)
ret void
@@ -32,9 +32,9 @@ define void @ucmp_i32(i32 %arg1, i32 %arg2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(s4) = G_UCMP [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(i4) = G_UCMP [[COPY]](i32), [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%res4 = call i4 @llvm.ucmp.i4.i32(i32 %arg1, i32 %arg2)
ret void
@@ -45,9 +45,9 @@ define void @ucmp_4_32i(<4 x i32> %arg1, <4 x i32> %arg2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(<4 x s32>) = G_UCMP [[COPY]](<4 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i32>) = COPY $q1
+ ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(<4 x i32>) = G_UCMP [[COPY]](<4 x i32>), [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%res4 = call <4 x i32> @llvm.ucmp.v4i32.i32(<4 x i32> %arg1, <4 x i32> %arg2)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
index 38c04e2a3ed69..d39fa9ecc3a42 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
@@ -7,45 +7,45 @@ define i32 @test_bittest(i16 %p) {
; CHECK-NEXT: successors: %bb.4(0x1b6db6db), %bb.5(0x64924925)
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 114
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ZEXT]], [[C3]]
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 59
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C4]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 114
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[ZEXT]], [[C3]]
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](i32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 59
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i32), [[C4]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[ZEXT]](i32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C5]], [[ZEXT1]](s64)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C6]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.3
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[ZEXT1]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C6]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i64), [[C7]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.epilog:
- ; CHECK-NEXT: $w0 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C2]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cb1:
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
switch i16 %p, label %sw.epilog [
i16 58, label %cb1
@@ -71,47 +71,47 @@ define void @test_bittest_2_bt(i32 %p) {
; CHECK-NEXT: successors: %bb.5(0x345d1746), %bb.6(0x4ba2e8ba)
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 176
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.5
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 176
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.5
; CHECK-NEXT: G_BR %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
; CHECK-NEXT: successors: %bb.4(0x0ccccccd), %bb.7(0x73333333)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C2]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB1]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 38
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB1]](s32), [[C3]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.4
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB1]](i32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 38
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB1]](i32), [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.entry:
; CHECK-NEXT: successors: %bb.2(0x76276276), %bb.5(0x09d89d8a)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[SUB]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 57351
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C5]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C6]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.2
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[C4]], [[SUB]](i32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 57351
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C5]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i32), [[C6]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.2
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.entry:
; CHECK-NEXT: successors: %bb.3(0x71c71c72), %bb.4(0x0e38e38e)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[C7]], [[ZEXT]](s64)
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 365072220160
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C8]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND1]](s64), [[C9]]
- ; CHECK-NEXT: G_BRCOND [[ICMP3]](s1), %bb.3
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i64) = G_SHL [[C7]], [[ZEXT]](s64)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 365072220160
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[SHL1]], [[C8]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND1]](i64), [[C9]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP3]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.bb37:
@@ -154,35 +154,35 @@ define i32 @test_bittest_single_bt_only_with_fallthrough(i16 %p) {
; CHECK-NEXT: successors: %bb.2(0x0aaaaaab), %bb.4(0x75555555)
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ZEXT]], [[C2]]
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 59
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s32), [[C3]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[ZEXT]], [[C2]]
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](i32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 59
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i32), [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.2(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C4]], [[ZEXT1]](s64)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C5]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C6]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C4]], [[ZEXT1]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C5]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i64), [[C6]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.epilog:
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cb1:
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
switch i16 %p, label %sw.epilog [
i16 58, label %cb1
@@ -203,36 +203,38 @@ define void @bit_test_block_incomplete_phi() {
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[DEF]], [[C2]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[DEF]], [[C2]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
; CHECK-NEXT: successors: %bb.3(0x51745d17), %bb.4(0x2e8ba2e9)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[SUB]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 491
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C4]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C5]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[C3]], [[SUB]](i32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 491
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SHL]], [[C4]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i32), [[C5]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.entry:
; CHECK-NEXT: successors:
- ; CHECK: bb.2.sw.epilog.i:
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.sw.epilog.i:
; CHECK-NEXT: successors:
- ; CHECK: bb.3.if.end:
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[DEF1]](p0) :: (load (p0) from `ptr undef`)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.return:
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.3, [[C1]](s1), %bb.5
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(i1) = G_PHI [[C]](i1), %bb.3, [[C1]](i1), %bb.5
; CHECK-NEXT: RET_ReallyLR
entry:
switch i32 undef, label %sw.epilog.i [
@@ -267,50 +269,50 @@ define i32 @test_odd_type(i328 %p) {
; CHECK-NEXT: successors: %bb.4(0x1b6db6db), %bb.5(0x64924925)
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s384) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s328) = G_TRUNC [[MV]](s384)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s328) = G_CONSTANT i328 114
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s328) = G_CONSTANT i328 0
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s328) = G_SUB [[TRUNC]], [[C3]]
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[SUB]](s328)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s328) = G_CONSTANT i328 59
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s328), [[C4]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s384) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64), [[COPY2]](i64), [[COPY3]](i64), [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i328) = G_TRUNC [[MV]](s384)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i328) = G_CONSTANT i328 114
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i328) = G_CONSTANT i328 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i328) = G_SUB [[TRUNC]], [[C3]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[SUB]](i328)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i328) = G_CONSTANT i328 59
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i328), [[C4]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s328), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[TRUNC]](i328), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C5]], [[TRUNC1]](s64)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C6]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.3
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[TRUNC1]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C6]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i64), [[C7]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.epilog:
- ; CHECK-NEXT: $w0 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C2]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cb1:
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
switch i328 %p, label %sw.epilog [
i328 58, label %cb1
@@ -332,47 +334,47 @@ define i32 @test_large_pow2_type(i256 %p) {
; CHECK-NEXT: successors: %bb.4(0x1b6db6db), %bb.5(0x64924925)
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s256) = G_CONSTANT i256 114
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s256) = G_CONSTANT i256 0
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s256) = G_SUB [[MV]], [[C3]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[SUB]](s256)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s256) = G_CONSTANT i256 59
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[SUB]](s256), [[C4]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i256) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64), [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i256) = G_CONSTANT i256 114
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i256) = G_CONSTANT i256 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i256) = G_SUB [[MV]], [[C3]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[SUB]](i256)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i256) = G_CONSTANT i256 59
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i256), [[C4]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[MV]](s256), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[MV]](i256), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C5]], [[TRUNC]](s64)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 866239240827043840
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C6]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[C7]]
- ; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.3
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[TRUNC]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C6]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[AND]](i64), [[C7]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP2]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.epilog:
- ; CHECK-NEXT: $w0 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C2]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cb1:
- ; CHECK-NEXT: $w0 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
switch i256 %p, label %sw.epilog [
i256 58, label %cb1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
index 3daeebe27a2a8..fd324071306e9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
@@ -1,14 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -mtriple=aarch64-unknown-unknown -stop-after=irtranslator -o - %s | FileCheck %s
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
define void @snork() {
+ ; CHECK-LABEL: name: snork
+ ; CHECK: bb.1.bb:
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i16) = G_LOAD [[C]](p0) :: (load (i16) from `ptr null`, !tbaa !0)
+ ; CHECK-NEXT: G_STORE [[LOAD]](i16), [[C2]](p0) :: (store (i16) into %ir.tmp5, !tbaa !0)
+ ; CHECK-NEXT: RET_ReallyLR
bb:
%tmp5 = getelementptr i16, ptr null, i64 2
%tmp6 = load i16, ptr null, align 2, !tbaa !0
store i16 %tmp6, ptr %tmp5, align 2, !tbaa !0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD %{{[0-9]+}}(p0) :: (load (s16) from `ptr null`, !tbaa !0)
- ; CHECK: G_STORE [[LOAD]](s16), %{{[0-9]+}}(p0) :: (store (s16) into %ir.tmp5, !tbaa !0)
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll
index d87e9c4b18550..598e91fa0e2f5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-trunc.ll
@@ -6,9 +6,9 @@ define i32 @call_trunc_no_flags(i64 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = trunc i64 %a to i32
@@ -20,9 +20,9 @@ define i32 @call_trunc_nsw_flags(i64 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nsw G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = nsw G_TRUNC [[COPY]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = trunc nsw i64 %a to i32
@@ -34,9 +34,9 @@ define i32 @call_trunc_nuw_flags(i64 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nuw G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = nuw G_TRUNC [[COPY]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = trunc nuw i64 %a to i32
@@ -48,9 +48,9 @@ define i32 @call_trunc_all_flags(i64 %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = nuw nsw G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = nuw nsw G_TRUNC [[COPY]](i64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%result = trunc nsw nuw i64 %a to i32
@@ -62,10 +62,10 @@ define <2 x i64> @call_trunc_noop_signed_vector(<2 x i64> %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = nsw G_TRUNC [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[TRUNC]](<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[SEXT]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i32>) = nsw G_TRUNC [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<2 x i64>) = G_SEXT [[TRUNC]](<2 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[SEXT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%truncate = trunc nsw <2 x i64> %a to <2 x i32>
@@ -78,10 +78,10 @@ define <2 x i64> @call_trunc_noop_unsigned_vector(<2 x i64> %a) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = nuw G_TRUNC [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[TRUNC]](<2 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i32>) = nuw G_TRUNC [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x i64>) = G_ZEXT [[TRUNC]](<2 x i32>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%truncate = trunc nuw <2 x i64> %a to <2 x i32>
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
index 1d22682a804ea..c28894b746f5e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
@@ -35,7 +35,7 @@ define dso_local void @test() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY1]](p0)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[GV]](p0)
; CHECK-NEXT: BL @printf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
@@ -71,7 +71,7 @@ define void @test2() #0 personality ptr @__gcc_personality_v0 {
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[DEF]](p0)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:GPR64common */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3866633 /* reguse:GPR64common */, [[COPY]]
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
@@ -85,7 +85,7 @@ define void @test2() #0 personality ptr @__gcc_personality_v0 {
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY2]](p0)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
; CHECK-NEXT: BL @_Unwind_Resume, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll
index 4dcdd967ac152..d818bcb17e1a8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll
@@ -6,10 +6,10 @@ define void @vector_deinterleave2_v4i32(<4 x i32> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[DEF]], shufflemask(0, 2)
- ; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[DEF]], shufflemask(1, 3)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i32>) = COPY $q0
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x i32>), [[DEF]], shufflemask(0, 2)
+ ; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x i32>), [[DEF]], shufflemask(1, 3)
; CHECK-NEXT: RET_ReallyLR
%res = call {<2 x i32>, <2 x i32>} @llvm.vector.deinterleave2.v4i32(<4 x i32> %a)
ret void
@@ -20,14 +20,14 @@ define void @vector_deinterleave2_v8f32(<8 x float> %a) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[BITCAST]](<4 x s32>), [[BITCAST1]](<4 x s32>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x s32>), [[DEF]], shufflemask(0, 2, 4, 6)
- ; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x s32>), [[DEF]], shufflemask(1, 3, 5, 7)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x f32>) = G_CONCAT_VECTORS [[BITCAST]](<4 x f32>), [[BITCAST1]](<4 x f32>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x f32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x f32>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x f32>), [[DEF]], shufflemask(0, 2, 4, 6)
+ ; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<4 x f32>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x f32>), [[DEF]], shufflemask(1, 3, 5, 7)
; CHECK-NEXT: RET_ReallyLR
%res = call {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float> %a)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll
index 1870faad157c7..c5cddbae4ed48 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll
@@ -6,9 +6,9 @@ define void @vector_interleave2_v4i32(<2 x i32> %a, <2 x i32> %b) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s32>), [[COPY1]], shufflemask(0, 2, 1, 3)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[COPY]](<2 x i32>), [[COPY1]], shufflemask(0, 2, 1, 3)
; CHECK-NEXT: RET_ReallyLR
%res = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %a, <2 x i32> %b)
ret void
@@ -19,11 +19,11 @@ define void @vector_interleave2_v8f32(<4 x float> %a, <4 x float> %b) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<8 x s32>) = G_SHUFFLE_VECTOR [[BITCAST]](<4 x s32>), [[BITCAST1]], shufflemask(0, 4, 1, 5, 2, 6, 3, 7)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x f32>) = G_BITCAST [[COPY1]](<2 x i64>)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<8 x f32>) = G_SHUFFLE_VECTOR [[BITCAST]](<4 x f32>), [[BITCAST1]], shufflemask(0, 4, 1, 5, 2, 6, 3, 7)
; CHECK-NEXT: RET_ReallyLR
%res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
index d06e2c64c2457..137064dc3464a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll
@@ -4,8 +4,8 @@
define i64 @call_vscale_i64() {
; CHECK-LABEL: name: call_vscale_i64
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
- ; CHECK-NEXT: $x0 = COPY [[VSCALE]](s64)
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(i64) = G_VSCALE i64 1
+ ; CHECK-NEXT: $x0 = COPY [[VSCALE]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%vscale = call i64 @llvm.vscale.64()
@@ -15,9 +15,9 @@ entry:
define i64 @call_vscale_i32() {
; CHECK-LABEL: name: call_vscale_i32
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s32) = G_VSCALE i32 1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s32)
- ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(i32) = G_VSCALE i32 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[VSCALE]](i32)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%vscale = call i32 @llvm.vscale.32()
@@ -28,9 +28,9 @@ entry:
define i64 @call_vscale_i16() {
; CHECK-LABEL: name: call_vscale_i16
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s16) = G_VSCALE i16 1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s16)
- ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(i16) = G_VSCALE i16 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[VSCALE]](i16)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%vscale = call i16 @llvm.vscale.16()
@@ -41,9 +41,9 @@ entry:
define i64 @call_vscale_i8() {
; CHECK-LABEL: name: call_vscale_i8
; CHECK: bb.1.entry:
- ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s8) = G_VSCALE i8 1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s8)
- ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(i8) = G_VSCALE i8 1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[VSCALE]](i8)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%vscale = call i8 @llvm.vscale.8()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index 1a210644f6517..da37555a4ef37 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -46,9 +46,8 @@ body: |
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[C]], [[LOAD]]
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR]], [[C]]
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64), align 16)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY1]](p0) :: (load (s16) from unknown-address + 8, align 8)
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
+ ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 8, align 8)
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 10, align 2)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD3]](s32), [[DEF]](s32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C3]](s64)
@@ -57,13 +56,15 @@ body: |
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[C]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[OR4]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[OR5]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64)
- ; CHECK-NEXT: G_STORE [[COPY2]](s64), %ptr(p0) :: (store (s64), align 16)
+ ; CHECK-NEXT: G_STORE [[COPY1]](s64), %ptr(p0) :: (store (s64), align 16)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 8, align 8)
- ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD3]](p0) :: (store (s16) into unknown-address + 8, align 8)
+ ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD4]](p0) :: (store (s8) into unknown-address + 10, align 2)
%ptr:_(p0) = COPY $x0
%a:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
%b:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
@@ -95,17 +96,17 @@ body: |
; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C]]
; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]]
; CHECK-NEXT: G_STORE [[AND5]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND6]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND7]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND8]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND9]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
@@ -139,17 +140,17 @@ body: |
; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C]]
; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]]
; CHECK-NEXT: G_STORE [[AND5]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND6]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND7]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND8]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND9]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
index 4d461c971d332..f08db556d14d8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir
@@ -54,67 +54,67 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: boolean_vector_to_scalar
- ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s8>) = G_IMPLICIT_DEF
+ ; CHECK: [[DEF:%[0-9]+]]:_(<8 x i8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](s8)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s64)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C4]](s64)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC2]](s8)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C4]](s64)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C5]](s64)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](s8)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C1]]
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C6]](s64)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC4]](s8)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C1]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C6]](s64)
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C7]](s64)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](s8)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C1]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C7]](s64)
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C8]](s64)
- ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC6]](s8)
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C1]]
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s64)
- ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C9]](s64)
- ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC7]](s8)
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C1]]
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s64)
- ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR7]](s32)
- ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[FRAME_INDEX]](p0) :: (store (s8) into %stack.0)
- ; CHECK-NEXT: %bc:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s8) from %stack.0)
- ; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %bc(s8)
- ; CHECK-NEXT: $w0 = COPY %ext(s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i8)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C3]](i64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC1]](i8)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C3]](i64)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C4]](i64)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC2]](i8)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ANYEXT2]], [[C1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C4]](i64)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C5]](i64)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC3]](i8)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ANYEXT3]], [[C1]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C5]](i64)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C6]](i64)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC4]](i8)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ANYEXT4]], [[C1]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C6]](i64)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C7]](i64)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC5]](i8)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[ANYEXT5]], [[C1]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C7]](i64)
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C8]](i64)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC6]](i8)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[ANYEXT6]], [[C1]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C8]](i64)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[OR5]], [[SHL6]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(i8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x i8>), [[C9]](i64)
+ ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC7]](i8)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[ANYEXT7]], [[C1]]
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C9]](i64)
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[OR6]], [[SHL7]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[OR7]](i32)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i8), [[FRAME_INDEX]](p0) :: (store (i8) into %stack.0)
+ ; CHECK-NEXT: %bc:_(i8) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i8) from %stack.0)
+ ; CHECK-NEXT: %ext:_(i32) = G_ANYEXT %bc(i8)
+ ; CHECK-NEXT: $w0 = COPY %ext(i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %vec:_(<8 x s1>) = G_IMPLICIT_DEF
- %bc:_(s8) = G_BITCAST %vec(<8 x s1>)
- %ext:_(s32) = G_ANYEXT %bc(s8)
- $w0 = COPY %ext(s32)
+ %vec:_(<8 x i1>) = G_IMPLICIT_DEF
+ %bc:_(i8) = G_BITCAST %vec(<8 x i1>)
+ %ext:_(i32) = G_ANYEXT %bc(i8)
+ $w0 = COPY %ext(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
index 2378401b2e7ed..c220e14177bc9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
@@ -198,8 +198,8 @@ body: |
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[UV]](s64), [[COPY]](p0) :: (store (s32), align 16)
; CHECK-NEXT: G_STORE [[LSHR1]](s64), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4, align 4)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C1]](s64)
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[UV1]](s64), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 6, align 2)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
index 26230efbbe863..19f604fbd2b64 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
@@ -20,13 +20,13 @@ body: |
; CHECK-NOLSE-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NOLSE-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NOLSE-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NOLSE-NEXT: [[COPY5:%[0-9]+]]:gpr64(s64) = COPY [[COPY1]](s64)
- ; CHECK-NOLSE-NEXT: [[COPY6:%[0-9]+]]:gpr64(s64) = COPY [[COPY2]](s64)
- ; CHECK-NOLSE-NEXT: [[COPY7:%[0-9]+]]:gpr64(s64) = COPY [[COPY3]](s64)
- ; CHECK-NOLSE-NEXT: [[COPY8:%[0-9]+]]:gpr64(s64) = COPY [[COPY4]](s64)
- ; CHECK-NOLSE-NEXT: early-clobber %14:gpr64common(s64), early-clobber %15:gpr64common(s64), early-clobber %17:gpr32common = CMP_SWAP_128_ACQUIRE [[COPY]](p0), [[COPY5]](s64), [[COPY6]](s64), [[COPY7]](s64), [[COPY8]](s64) :: (load store acquire acquire (s128))
+ ; CHECK-NOLSE-NEXT: [[COPY5:%[0-9]+]]:gpr64(i64) = COPY [[COPY1]](s64)
+ ; CHECK-NOLSE-NEXT: [[COPY6:%[0-9]+]]:gpr64(i64) = COPY [[COPY2]](s64)
+ ; CHECK-NOLSE-NEXT: [[COPY7:%[0-9]+]]:gpr64(i64) = COPY [[COPY3]](s64)
+ ; CHECK-NOLSE-NEXT: [[COPY8:%[0-9]+]]:gpr64(i64) = COPY [[COPY4]](s64)
+ ; CHECK-NOLSE-NEXT: early-clobber %14:gpr64common(i64), early-clobber %15:gpr64common(i64), early-clobber %17:gpr32common = CMP_SWAP_128_ACQUIRE [[COPY]](p0), [[COPY5]](i64), [[COPY6]](i64), [[COPY7]](i64), [[COPY8]](i64) :: (load store acquire acquire (s128))
; CHECK-NOLSE-NEXT: [[COPY9:%[0-9]+]]:gpr64 = COPY %17
- ; CHECK-NOLSE-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES %14(s64), %15(s64)
+ ; CHECK-NOLSE-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES %14(i64), %15(i64)
; CHECK-NOLSE-NEXT: [[COPY10:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
; CHECK-NOLSE-NEXT: G_STORE [[COPY10]](s128), [[COPY]](p0) :: (store (s128))
; CHECK-NOLSE-NEXT: RET_ReallyLR
@@ -42,9 +42,9 @@ body: |
; CHECK-LSE-NEXT: [[REG_SEQUENCE:%[0-9]+]]:xseqpairsclass(s128) = REG_SEQUENCE [[COPY1]](s64), %subreg.sube64, [[COPY2]](s64), %subreg.subo64
; CHECK-LSE-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:xseqpairsclass(s128) = REG_SEQUENCE [[COPY3]](s64), %subreg.sube64, [[COPY4]](s64), %subreg.subo64
; CHECK-LSE-NEXT: [[CASPAX:%[0-9]+]]:xseqpairsclass(s128) = CASPAX [[REG_SEQUENCE]](s128), [[REG_SEQUENCE1]](s128), [[COPY]](p0) :: (load store acquire acquire (s128))
- ; CHECK-LSE-NEXT: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[CASPAX]](s128), 0
- ; CHECK-LSE-NEXT: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[CASPAX]](s128), 64
- ; CHECK-LSE-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[EXTRACT]](s64), [[EXTRACT1]](s64)
+ ; CHECK-LSE-NEXT: [[EXTRACT:%[0-9]+]]:_(i64) = G_EXTRACT [[CASPAX]](s128), 0
+ ; CHECK-LSE-NEXT: [[EXTRACT1:%[0-9]+]]:_(i64) = G_EXTRACT [[CASPAX]](s128), 64
+ ; CHECK-LSE-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[EXTRACT]](i64), [[EXTRACT1]](i64)
; CHECK-LSE-NEXT: [[COPY5:%[0-9]+]]:_(s128) = COPY [[MV]](s128)
; CHECK-LSE-NEXT: G_STORE [[COPY5]](s128), [[COPY]](p0) :: (store (s128))
; CHECK-LSE-NEXT: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
index c00ce2242a888..ba7b3b426fce4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
@@ -97,17 +97,17 @@ body: |
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C2]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C3]]
; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C6]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C6]](i64)
; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C7]](s64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C7]](i64)
; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%cst:_(s318) = G_CONSTANT i318 1234
@@ -136,11 +136,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[AND2]](s64), 0
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[EXTRACT]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%cst:_(s158) = G_CONSTANT i158 1234
@@ -170,11 +170,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[AND2]](s64), 0
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[EXTRACT]](s16), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%cst:_(s142) = G_CONSTANT i142 1234
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
index f7550ceb2799a..a5c43a4ef9b46 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
@@ -16,8 +16,8 @@ define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: $w0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: $w0 = COPY [[C]](i32)
; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: EH_LABEL <mcsymbol >
@@ -30,12 +30,12 @@ define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
; CHECK-NEXT: G_STORE [[COPY]](p0), [[FRAME_INDEX]](p0) :: (store (p0) into %ir.exn.slot)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ehselector.slot
- ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.ehselector.slot)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %ir.ehselector.slot)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
index dafc304901209..fe0d46d47debd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
@@ -327,8 +327,8 @@ body: |
; CHECK-NEXT: %idx:_(s64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[COPY]](<2 x s64>), [[FRAME_INDEX]](p0) :: (store (<2 x s64>) into %stack.0, align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %stack.0 + 16, basealign 32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %idx, [[C1]]
@@ -425,8 +425,8 @@ body: |
; CHECK-NEXT: %idxprom:_(s64) = G_SEXT %idx(s32)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[COPY]](<4 x s32>), [[FRAME_INDEX]](p0) :: (store (<4 x s32>) into %stack.0, align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into %stack.0 + 16, basealign 32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %idxprom, [[C1]]
@@ -459,8 +459,8 @@ body: |
; CHECK-NEXT: %idxprom:_(s64) = G_SEXT %idx(s32)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[COPY]](<8 x s16>), [[FRAME_INDEX]](p0) :: (store (<8 x s16>) into %stack.0, align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into %stack.0 + 16, basealign 32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %idxprom, [[C1]]
@@ -494,8 +494,8 @@ body: |
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST]](<2 x s64>), [[FRAME_INDEX]](p0) :: (store (<2 x s64>) into %stack.0, align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %stack.0 + 16, basealign 32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
index 131a6563a1bcb..4f036d275b24d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
@@ -16,14 +16,15 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %val(s32), [[DEF]](s32)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %sign(s32), [[DEF]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
- ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](<2 x s32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[OR]](<2 x i32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK-NEXT: %fcopysign:_(s32) = COPY [[UV]](s32)
; CHECK-NEXT: $s0 = COPY %fcopysign(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
@@ -48,14 +49,15 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %val(s64), [[DEF]](s64)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %sign(s64), [[DEF]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
- ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
- ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = disjoint G_OR [[AND]], [[AND1]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[OR]](<2 x s64>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C1]](i64), [[C1]](i64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i64>) = disjoint G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[OR]](<2 x i64>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK-NEXT: %fcopysign:_(s64) = COPY [[UV]](s64)
; CHECK-NEXT: $d0 = COPY %fcopysign(s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
index 42538d58c87bf..e3c0d4989fc2c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
@@ -150,10 +150,11 @@ body: |
; NO-FP16: liveins: $h0
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %x:_(s16) = COPY $h0
- ; NO-FP16-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %x(s16)
- ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; NO-FP16-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ANYEXT]], [[C]]
- ; NO-FP16-NEXT: %op:_(s16) = G_TRUNC [[XOR]](s32)
+ ; NO-FP16-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT %x(s16)
+ ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -32768
+ ; NO-FP16-NEXT: [[XOR:%[0-9]+]]:_(i32) = G_XOR [[ANYEXT]], [[C]]
+ ; NO-FP16-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[XOR]](i32)
+ ; NO-FP16-NEXT: %op:_(s16) = G_BITCAST [[TRUNC]](i16)
; NO-FP16-NEXT: $h0 = COPY %op(s16)
; NO-FP16-NEXT: RET_ReallyLR implicit $h0
;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
index 50394b6bbbf99..1bbdeedd87be8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
@@ -21,8 +21,8 @@ body: |
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x s32>)
; CHECK-NEXT: G_STORE [[FPEXT]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
; CHECK-NEXT: G_STORE [[FPEXT1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%0:_(<4 x s32>) = COPY $q0
@@ -61,9 +61,9 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x s32>)
- ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f32>), [[UV1:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x f32>)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x f32>)
; CHECK-NEXT: $q0 = COPY [[FPEXT1]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:_(<4 x s16>) = COPY $d0
@@ -83,10 +83,10 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x s32>)
- ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
- ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x s32>)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f32>), [[UV1:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x f32>)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x f32>)
+ ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x f32>)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT1]](<2 x s64>)
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPEXT2]](<2 x s64>)
; CHECK-NEXT: $d0 = COPY [[UV2]](s64)
@@ -114,10 +114,10 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x s32>)
- ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x s32>)
- ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x s32>)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f32>), [[UV1:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x f32>)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV]](<2 x f32>)
+ ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV1]](<2 x f32>)
; CHECK-NEXT: $q0 = COPY [[FPEXT1]](<2 x s64>)
; CHECK-NEXT: $q1 = COPY [[FPEXT2]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
@@ -140,14 +140,14 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
- ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x s32>), [[UV3:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x s32>)
- ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<2 x s32>), [[UV5:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT1]](<4 x s32>)
- ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV2]](<2 x s32>)
- ; CHECK-NEXT: [[FPEXT3:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV3]](<2 x s32>)
- ; CHECK-NEXT: [[FPEXT4:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV4]](<2 x s32>)
- ; CHECK-NEXT: [[FPEXT5:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV5]](<2 x s32>)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV]](<4 x s16>)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x f32>) = G_FPEXT [[UV1]](<4 x s16>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x f32>), [[UV3:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x f32>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<2 x f32>), [[UV5:%[0-9]+]]:_(<2 x f32>) = G_UNMERGE_VALUES [[FPEXT1]](<4 x f32>)
+ ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV2]](<2 x f32>)
+ ; CHECK-NEXT: [[FPEXT3:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV3]](<2 x f32>)
+ ; CHECK-NEXT: [[FPEXT4:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV4]](<2 x f32>)
+ ; CHECK-NEXT: [[FPEXT5:%[0-9]+]]:_(<2 x s64>) = G_FPEXT [[UV5]](<2 x f32>)
; CHECK-NEXT: $q0 = COPY [[FPEXT2]](<2 x s64>)
; CHECK-NEXT: $q1 = COPY [[FPEXT3]](<2 x s64>)
; CHECK-NEXT: $q2 = COPY [[FPEXT4]](<2 x s64>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
index a19ab0b5e7bfc..0113170631931 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
@@ -134,8 +134,8 @@ body: |
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[FPTRUNC]](<2 x s32>), [[FPTRUNC1]](<2 x s32>)
; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[FPTRUNC2]](<2 x s32>), [[FPTRUNC3]](<2 x s32>)
; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<4 x s32>), [[COPY5]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY5]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY5]], [[C]](i64)
; CHECK-NEXT: G_STORE [[CONCAT_VECTORS1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%2:_(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
index 1cf066dc894de..1bb66511ae7eb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
@@ -255,11 +255,11 @@ body: |
; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(<4 x s32>) = G_UITOFP [[BITCAST]](<4 x s32>)
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UITOFP]](<4 x s32>)
; CHECK-NEXT: G_STORE [[UV6]](s32), [[COPY]](p0) :: (store (s32), align 16)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
; CHECK-NEXT: G_STORE [[UV7]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](i64)
; CHECK-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 8, align 8)
; CHECK-NEXT: G_BR %bb.1
bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
index fafaa4646fa22..dac87b1cedaeb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
@@ -17,8 +17,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -44,8 +44,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -71,8 +71,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -98,8 +98,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -127,8 +127,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -154,8 +154,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -181,8 +181,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -208,8 +208,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
index 29a3e383a4f53..98f822d09b035 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
@@ -45,8 +45,8 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x8
@@ -71,8 +71,8 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x8
@@ -94,8 +94,8 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64), align 16)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[C1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x8
@@ -139,8 +139,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: $q0 = COPY [[LOAD]](<2 x s64>)
; CHECK-NEXT: $q1 = COPY [[LOAD1]](<2 x s64>)
@@ -165,8 +165,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: $q0 = COPY [[LOAD]](<2 x s64>)
; CHECK-NEXT: $q1 = COPY [[LOAD1]](<2 x s64>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index eb305812a2061..92a82ba7bbf2b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -331,8 +331,8 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[DEF]](<16 x s8>), %ptr(p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[DEF]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%val:_(<32 x s8>) = G_IMPLICIT_DEF
@@ -354,8 +354,8 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[DEF]](<8 x s16>), %ptr(p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[DEF]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%val:_(<16 x s16>) = G_IMPLICIT_DEF
@@ -377,8 +377,8 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[DEF]](<4 x s32>), %ptr(p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[DEF]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%val:_(<8 x s32>) = G_IMPLICIT_DEF
@@ -400,8 +400,8 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%val:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -422,11 +422,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD %ptr(p0) :: (load (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[PTR_ADD]](p0) :: (load (<16 x s8>) from unknown-address + 16)
; CHECK-NEXT: G_STORE [[LOAD]](<16 x s8>), %ptr(p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](<16 x s8>), [[PTR_ADD1]](p0) :: (store (<16 x s8>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -447,11 +447,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD %ptr(p0) :: (load (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[PTR_ADD]](p0) :: (load (<8 x s16>) from unknown-address + 16)
; CHECK-NEXT: G_STORE [[LOAD]](<8 x s16>), %ptr(p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](<8 x s16>), [[PTR_ADD1]](p0) :: (store (<8 x s16>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -472,11 +472,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD %ptr(p0) :: (load (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p0) :: (load (<4 x s32>) from unknown-address + 16)
; CHECK-NEXT: G_STORE [[LOAD]](<4 x s32>), %ptr(p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](<4 x s32>), [[PTR_ADD1]](p0) :: (store (<4 x s32>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -497,11 +497,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr(p0) :: (load (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: G_STORE [[LOAD]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -551,11 +551,11 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64)
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>))
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR2]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 32)
; CHECK-NEXT: RET_ReallyLR
%val:_(<6 x s64>) = G_IMPLICIT_DEF
@@ -577,8 +577,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $s0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
; CHECK-NEXT: G_STORE [[UV]](s16), [[COPY]](p0) :: (store (s16), align 4)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UV1]](s16), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
@@ -599,8 +599,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s16)
@@ -644,7 +644,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[OR1]](s64)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64)
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 16)
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD2]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8)
@@ -712,20 +713,20 @@ body: |
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr(p0) :: (load (<2 x s64>), align 64)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](i64)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 32, align 32)
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x s64>)
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BITCAST]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST3]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 64)
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BITCAST1]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST4]](<2 x s64>), [[PTR_ADD2]](p0) :: (store (<2 x s64>) into unknown-address + 16)
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](i64)
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BITCAST2]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST5]](<2 x s64>), [[PTR_ADD3]](p0) :: (store (<2 x s64>) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
index 30afd7e85dfa7..b03163ee63f77 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
@@ -60,8 +60,8 @@ body: |
; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<16 x s8>) = G_SMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMIN1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
%vec:_(<32 x s8>) = G_IMPLICIT_DEF
%vec1:_(<32 x s8>) = G_IMPLICIT_DEF
@@ -129,8 +129,8 @@ body: |
; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<8 x s16>) = G_SMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMIN1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
%vec:_(<16 x s16>) = G_IMPLICIT_DEF
%vec1:_(<16 x s16>) = G_IMPLICIT_DEF
@@ -198,8 +198,8 @@ body: |
; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<4 x s32>) = G_SMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMIN1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
%vec:_(<8 x s32>) = G_IMPLICIT_DEF
%vec1:_(<8 x s32>) = G_IMPLICIT_DEF
@@ -220,12 +220,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), %vec(<2 x s64>), %vec1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(slt), %vec(<2 x s64>), %vec1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND %vec, [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND %vec1, [[XOR]]
; CHECK-NEXT: %smin:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY %smin(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -247,22 +247,22 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -330,8 +330,8 @@ body: |
; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<16 x s8>) = G_UMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMIN1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
%vec:_(<32 x s8>) = G_IMPLICIT_DEF
%vec1:_(<32 x s8>) = G_IMPLICIT_DEF
@@ -399,8 +399,8 @@ body: |
; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<8 x s16>) = G_UMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMIN1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
%vec:_(<16 x s16>) = G_IMPLICIT_DEF
%vec1:_(<16 x s16>) = G_IMPLICIT_DEF
@@ -468,8 +468,8 @@ body: |
; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<4 x s32>) = G_UMIN [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMIN1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
%vec:_(<8 x s32>) = G_IMPLICIT_DEF
%vec1:_(<8 x s32>) = G_IMPLICIT_DEF
@@ -490,12 +490,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), %vec(<2 x s64>), %vec1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ult), %vec(<2 x s64>), %vec1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND %vec, [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND %vec1, [[XOR]]
; CHECK-NEXT: %umin:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY %umin(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -517,22 +517,22 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -622,8 +622,8 @@ body: |
; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<16 x s8>) = G_SMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMAX]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMAX1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
%vec:_(<32 x s8>) = G_IMPLICIT_DEF
%vec1:_(<32 x s8>) = G_IMPLICIT_DEF
@@ -669,8 +669,8 @@ body: |
; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<8 x s16>) = G_SMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMAX]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMAX1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
%vec:_(<16 x s16>) = G_IMPLICIT_DEF
%vec1:_(<16 x s16>) = G_IMPLICIT_DEF
@@ -738,8 +738,8 @@ body: |
; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<4 x s32>) = G_SMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[SMAX]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SMAX1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
%vec:_(<8 x s32>) = G_IMPLICIT_DEF
%vec1:_(<8 x s32>) = G_IMPLICIT_DEF
@@ -760,12 +760,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), %vec(<2 x s64>), %vec1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(sgt), %vec(<2 x s64>), %vec1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND %vec, [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND %vec1, [[XOR]]
; CHECK-NEXT: %smax:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY %smax(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -787,22 +787,22 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -870,8 +870,8 @@ body: |
; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<16 x s8>) = G_UMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMAX]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMAX1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
%vec:_(<32 x s8>) = G_IMPLICIT_DEF
%vec1:_(<32 x s8>) = G_IMPLICIT_DEF
@@ -939,8 +939,8 @@ body: |
; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<8 x s16>) = G_UMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMAX]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMAX1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
%vec:_(<16 x s16>) = G_IMPLICIT_DEF
%vec1:_(<16 x s16>) = G_IMPLICIT_DEF
@@ -1008,8 +1008,8 @@ body: |
; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<4 x s32>) = G_UMAX [[DEF]], [[DEF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[UMAX]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[UMAX1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
%vec:_(<8 x s32>) = G_IMPLICIT_DEF
%vec1:_(<8 x s32>) = G_IMPLICIT_DEF
@@ -1030,12 +1030,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), %vec(<2 x s64>), %vec1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), %vec(<2 x s64>), %vec1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND %vec, [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND %vec1, [[XOR]]
; CHECK-NEXT: %umax:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY %umax(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -1057,22 +1057,22 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[ICMP1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[DEF]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
index b6488e94d7859..28ecce778c741 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
@@ -90,17 +90,17 @@ body: |
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64))
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -129,11 +129,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[AND2]](s64), 0
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64))
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[EXTRACT]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 16, align 8)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
@@ -162,11 +162,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[AND2]](s64), 0
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64))
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[EXTRACT]](s16), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 16, align 8)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
index 9edc1cb0b213d..a75c22fd74360 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
@@ -83,17 +83,17 @@ body: |
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[C1]]
; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
index 47aa570720a90..31d30126dd65d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -714,8 +714,8 @@ body: |
; CHECK-NEXT: %ptr1:_(p0) = COPY $x1
; CHECK-NEXT: %ptr2:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr1, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr1, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -727,8 +727,8 @@ body: |
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr2, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr2, [[C2]](i64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
@@ -902,8 +902,8 @@ body: |
; CHECK-NEXT: %ptr2:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr1, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr1, [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
@@ -917,8 +917,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x s64>)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr2, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr2, [[C2]](i64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD3]](<2 x s64>)
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
index a18bd0f2f90eb..bbb4ff258dfa5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
@@ -160,9 +160,10 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[IVEC]], [[C]](s64), [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s64), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[IVEC]], [[C]](s64), [[C2]](i64)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[IVEC1]]
; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
index 49e03251daa6c..543de33847303 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
@@ -29,17 +29,17 @@ body: |
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.v1ptr)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.v2ptr)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](s128)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD1]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
; CHECK-NEXT: BL &__udivti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
@@ -71,17 +71,17 @@ body: |
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.v1ptr)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.v2ptr)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](s128)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD1]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
; CHECK-NEXT: BL &__divti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
index 1c5ae0d49a148..6705ee0d7f7c5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
@@ -125,8 +125,8 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](i64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)
@@ -197,8 +197,8 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](i64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)
@@ -244,8 +244,8 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXT_INREG]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C2]](i64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C3]](s64), [[C3]](s64)
@@ -291,9 +291,9 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP2]], 1
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[DEF1]], [[TRUNC]](s16), [[C1]](s64)
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[DEF1]], [[TRUNC]](s16), [[C1]](i64)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[IVEC]](<4 x s16>)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s16)
@@ -365,8 +365,8 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXT_INREG]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C1]](i64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
index 352f4e7bd0b38..364df8a7c8cc9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
@@ -137,8 +137,8 @@ body: |
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY1]](<2 x s64>), [[COPY2]], shufflemask(1, 2)
; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY3]](<2 x s64>), [[COPY]], shufflemask(1, 2)
; CHECK-NEXT: G_STORE [[SHUF]](<2 x s64>), [[COPY4]](p0) :: (store (<2 x s64>), align 32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY4]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY4]], [[C]](i64)
; CHECK-NEXT: G_STORE [[SHUF1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%3:_(<2 x s64>) = COPY $q0
@@ -180,8 +180,8 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[EVEC]](s32), [[EVEC1]](s32), [[EVEC2]](s32), [[EVEC3]](s32)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY1]](<4 x s32>), [[COPY]], shufflemask(2, 6, 5, 3)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s32>), [[COPY4]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY4]], [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY4]], [[C4]](i64)
; CHECK-NEXT: G_STORE [[SHUF]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
; CHECK-NEXT: RET_ReallyLR
%3:_(<4 x s32>) = COPY $q0
@@ -243,11 +243,11 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[EVEC]](s64), [[EVEC1]](s64)
; CHECK-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[EVEC2]](s64), [[EVEC3]](s64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR6]](<2 x s64>), [[COPY8]](p0) :: (store (<2 x s64>), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR7]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C3]](i64)
; CHECK-NEXT: G_STORE [[SHUF]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR
%3:_(s64) = COPY $d0
@@ -292,14 +292,14 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[DEF]](s32)
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[DEF]](s32)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]], shufflemask(0, 1, 5, 6)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C2]](s64)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C3]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C2]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C3]](i64)
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[EVEC]](s32), [[EVEC1]](s32), [[EVEC2]](s32), [[EVEC3]](s32)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR2]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -414,23 +414,23 @@ body: |
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]], shufflemask(3, 4, 7, 0)
; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]], shufflemask(1, 5, undef, undef)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C2]](s64)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C3]](s64)
- ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF1]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF1]](<4 x s32>), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C2]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C3]](i64)
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF1]](<4 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF1]](<4 x s32>), [[C1]](i64)
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[EVEC]](s32), [[EVEC1]](s32)
; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[EVEC2]](s32), [[EVEC3]](s32)
; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[EVEC4]](s32), [[EVEC5]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<2 x s32>), [[BUILD_VECTOR3]](<2 x s32>)
; CHECK-NEXT: G_STORE [[CONCAT_VECTORS]](<4 x s32>), [[COPY8]](p0) :: (store (<4 x s32>), align 32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY8]], [[C4]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR4]](<2 x s32>), [[PTR_ADD]](p0) :: (store (<2 x s32>) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR
%3:_(s32) = COPY $s0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
index 1df6297e36383..84e4ca21a5575 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir
@@ -21,58 +21,58 @@ body: |
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C1]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](s8)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s64)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C4]](s64)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC2]](s8)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C4]](s64)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C5]](s64)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](s8)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C2]]
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C6]](s64)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC4]](s8)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C2]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C6]](s64)
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C7]](s64)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](s8)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C2]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C7]](s64)
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C8]](s64)
- ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC6]](s8)
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C2]]
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s64)
- ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C9]](s64)
- ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC7]](s8)
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C2]]
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s64)
- ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR7]](s32)
- ; CHECK-NEXT: G_STORE [[TRUNC3]](s8), %ptr(p0) :: (store (s8))
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C1]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](s8)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C1]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[C3]], [[SHL]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C4]](i64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC1]](s8)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C4]](i64)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C5]](i64)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC2]](s8)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ANYEXT2]], [[C2]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C5]](i64)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C6]](i64)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC3]](s8)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ANYEXT3]], [[C2]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C6]](i64)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C7]](i64)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC4]](s8)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[ANYEXT4]], [[C2]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C7]](i64)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C8]](i64)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC5]](s8)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[ANYEXT5]], [[C2]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C8]](i64)
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C9]](i64)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC6]](s8)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[ANYEXT6]], [[C2]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C9]](i64)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[OR5]], [[SHL6]]
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C10]](i64)
+ ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC7]](s8)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[ANYEXT7]], [[C2]]
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C10]](i64)
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[OR6]], [[SHL7]]
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[OR7]](i32)
+ ; CHECK-NEXT: G_STORE [[TRUNC3]](i8), %ptr(p0) :: (store (i8))
; CHECK-NEXT: RET_ReallyLR
%1:_(<4 x s32>) = COPY $q0
%2:_(<4 x s32>) = COPY $q1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir
index 4f93f69023b4e..eaae73dd90b7e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir
@@ -23,21 +23,21 @@ body: |
; CHECK-LINUX-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-LINUX-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-LINUX-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY1]](p0) :: (load (s64))
- ; CHECK-LINUX-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-LINUX-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; CHECK-LINUX-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-LINUX-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
; CHECK-LINUX-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from unknown-address + 8)
- ; CHECK-LINUX-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-LINUX-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
+ ; CHECK-LINUX-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-LINUX-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
; CHECK-LINUX-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from unknown-address + 16)
- ; CHECK-LINUX-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-LINUX-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
+ ; CHECK-LINUX-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-LINUX-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
; CHECK-LINUX-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from unknown-address + 24)
; CHECK-LINUX-NEXT: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store (s64))
- ; CHECK-LINUX-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-LINUX-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-LINUX-NEXT: G_STORE [[LOAD1]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-LINUX-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-LINUX-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-LINUX-NEXT: G_STORE [[LOAD2]](s64), [[PTR_ADD4]](p0) :: (store (s64) into unknown-address + 16)
- ; CHECK-LINUX-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-LINUX-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-LINUX-NEXT: G_STORE [[LOAD3]](s64), [[PTR_ADD5]](p0) :: (store (s64) into unknown-address + 24)
; CHECK-LINUX-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir
index c2bf95ce21adf..afa2f76375b15 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-compress.mir
@@ -135,8 +135,8 @@ body: |
; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C4]]
; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND7]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD3]](s32), [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ADD3]], [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](i32), [[ADD3]], [[C1]]
; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C1]]
; CHECK-NEXT: [[SEXT4:%[0-9]+]]:_(s64) = G_SEXT [[AND8]](s32)
; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s64) = G_MUL [[SEXT4]], [[C2]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
index 1e1ae01786c05..aadb873da633c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
@@ -45,17 +45,17 @@ body: |
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[XOR3]], [[C]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[XOR4]], [[C1]]
; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
@@ -89,17 +89,17 @@ body: |
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[XOR3]], [[C]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[XOR4]], [[C1]]
; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s319) = G_IMPLICIT_DEF
@@ -132,11 +132,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[AND2]](s64), 0
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
; CHECK-NEXT: G_STORE [[EXTRACT]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s158) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
index 2aee1bbc8ddd4..140543c4ea390 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
@@ -884,10 +884,11 @@ body: |
; CHECK-LABEL: name: ldrsrox
; CHECK: liveins: $d0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $d0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK-NEXT: [[LDRSroX:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], [[COPY1]], 0, 0 :: (load (s32) from %ir.addr)
- ; CHECK-NEXT: $s2 = COPY [[LDRSroX]]
+ ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADDXrr]], 0 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: $s2 = COPY [[LDRSui]]
; CHECK-NEXT: RET_ReallyLR implicit $h2
%0:gpr(p0) = COPY $d0
%1:gpr(s64) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
index c4e07de265edd..3edc7774ec4d9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
@@ -19,36 +19,36 @@ define i32 @foo() {
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i32) from @var1)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i32), [[C3]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV3]](p0) :: (store (s32) into @var2)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: G_STORE [[C5]](i32), [[GV3]](p0) :: (store (i32) into @var2)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: G_STORE [[C6]](s32), [[GV4]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_STORE [[C6]](i32), [[GV4]](p0) :: (store (i32) into @var1)
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV5]](p0) :: (store (s32) into @var3)
- ; CHECK-NEXT: G_STORE [[C6]](s32), [[GV4]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_STORE [[C5]](i32), [[GV5]](p0) :: (store (i32) into @var3)
+ ; CHECK-NEXT: G_STORE [[C6]](i32), [[GV4]](p0) :: (store (i32) into @var1)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $w0 = COPY [[C7]](s32)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C7]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, ptr @var1, align 4
@@ -80,26 +80,26 @@ define i32 @darwin_tls() {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @tls_gv
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i32) from @var1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i32), [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @tls_gv)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[GV]](p0) :: (dereferenceable load (i32) from @tls_gv)
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: G_STORE [[LOAD1]](s32), [[GV3]](p0) :: (store (s32) into @var2)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](i32), [[GV3]](p0) :: (store (i32) into @var2)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $w0 = COPY [[C3]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C3]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, ptr @var1, align 4
@@ -122,36 +122,36 @@ define i32 @imm_cost_too_large_cost_of_2() {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2228259
- ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s32) = G_CONSTANT_FOLD_BARRIER [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i32) from @var1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2228259
+ ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(i32) = G_CONSTANT_FOLD_BARRIER [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i32), [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s32), [[GV3]](p0) :: (store (s32) into @var2)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i32), [[GV3]](p0) :: (store (i32) into @var2)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s32), [[GV4]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i32), [[GV4]](p0) :: (store (i32) into @var1)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s32), [[GV5]](p0) :: (store (s32) into @var3)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $w0 = COPY [[C4]](s32)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i32), [[GV5]](p0) :: (store (i32) into @var3)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C4]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, ptr @var1, align 4
@@ -179,36 +179,36 @@ define i64 @imm_cost_too_large_cost_of_4() {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s64) from @var1_64, align 4)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2228259
- ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(s64) = G_CONSTANT_FOLD_BARRIER [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s64), [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i64) from @var1_64, align 4)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -2228259
+ ; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(i64) = G_CONSTANT_FOLD_BARRIER [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i64), [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s64), [[GV3]](p0) :: (store (s64) into @var2_64)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i64), [[GV3]](p0) :: (store (i64) into @var2_64)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s64), [[GV4]](p0) :: (store (s64) into @var1_64)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i64), [[GV4]](p0) :: (store (i64) into @var1_64)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](s64), [[GV5]](p0) :: (store (s64) into @var3_64)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: $x0 = COPY [[C4]](s64)
+ ; CHECK-NEXT: G_STORE [[CONSTANT_FOLD_BARRIER]](i64), [[GV5]](p0) :: (store (i64) into @var3_64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY [[C4]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = load i64, ptr @var1_64, align 4
@@ -235,37 +235,37 @@ define i64 @f64_imm_cost_too_high(double %a) {
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e-02
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e-02
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s64) from @var1_64, align 4)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s64), [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i64) from @var1_64, align 4)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i64), [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
- ; CHECK-NEXT: G_STORE [[C]](s64), [[GV3]](p0) :: (store (s64) into @var2_64)
+ ; CHECK-NEXT: G_STORE [[C]](f64), [[GV3]](p0) :: (store (f64) into @var2_64)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: G_STORE [[C]](s64), [[GV4]](p0) :: (store (s64) into @var1_64)
+ ; CHECK-NEXT: G_STORE [[C]](f64), [[GV4]](p0) :: (store (f64) into @var1_64)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: G_STORE [[C]](s64), [[GV5]](p0) :: (store (s64) into @var3_64)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: $x0 = COPY [[C4]](s64)
+ ; CHECK-NEXT: G_STORE [[C]](f64), [[GV5]](p0) :: (store (f64) into @var3_64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY [[C4]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = load i64, ptr @var1_64, align 4
@@ -291,40 +291,40 @@ define i64 @f64_imm_cheap(double %a) {
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s64) from @var1_64, align 4)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s64), [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (i64) from @var1_64, align 4)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[LOAD]](i64), [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
- ; CHECK-NEXT: G_STORE [[C4]](s64), [[GV3]](p0) :: (store (s64) into @var2_64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; CHECK-NEXT: G_STORE [[C4]](f64), [[GV3]](p0) :: (store (f64) into @var2_64)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: G_STORE [[C5]](s64), [[GV4]](p0) :: (store (s64) into @var1_64)
+ ; CHECK-NEXT: G_STORE [[C5]](f64), [[GV4]](p0) :: (store (f64) into @var1_64)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
- ; CHECK-NEXT: G_STORE [[C6]](s64), [[GV5]](p0) :: (store (s64) into @var3_64)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: $x0 = COPY [[C7]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; CHECK-NEXT: G_STORE [[C6]](f64), [[GV5]](p0) :: (store (f64) into @var3_64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY [[C7]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = load i64, ptr @var1_64, align 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll b/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll
index 4aaa58e8dab2e..9ff99dae65fa2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/phi-with-empty-type.ll
@@ -9,8 +9,8 @@ define %zero @test(%zero %x, %zero %y) {
; CHECK: bb.1.b1:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: G_BRCOND [[DEF]](s1), %bb.3
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: G_BRCOND [[DEF]](i1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.b2:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
index acfbec0dd0ef2..0b533ff85fe86 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
@@ -73,10 +73,10 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[DUPLANE64_:%[0-9]+]]:_(<2 x s64>) = G_DUPLANE64 [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C2]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DUPLANE64_]](<2 x s64>), [[C2]](i64)
; CHECK-NEXT: $d0 = COPY [[EVEC]](s64)
; CHECK-NEXT: $d1 = COPY [[EVEC1]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
index 22d1ccc056eb4..d7690085ae693 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
@@ -43,10 +43,10 @@ body: |
; LOWER-NEXT: %r:_(s32) = COPY $w0
; LOWER-NEXT: %q:_(s32) = COPY $w1
; LOWER-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
- ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; LOWER-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %r(s32), [[C]](s64)
- ; LOWER-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; LOWER-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %q(s32), [[C1]](s64)
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %r(s32), [[C]](i64)
+ ; LOWER-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %q(s32), [[C1]](i64)
; LOWER-NEXT: %build_vector:_(<2 x s32>) = COPY [[IVEC1]](<2 x s32>)
; LOWER-NEXT: $d0 = COPY %build_vector(<2 x s32>)
; LOWER-NEXT: RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
index 80eda3db6e04a..0474e7312f16c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
@@ -22,10 +22,10 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -52,10 +52,10 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -83,10 +83,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -115,10 +115,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -146,10 +146,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -204,10 +204,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -235,10 +235,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -266,10 +266,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%left:_(<2 x s32>) = COPY $d0
@@ -296,10 +296,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %left:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: %right:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<4 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](i64)
; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%left:_(<4 x s32>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
index f11396ee6c330..3906bbe94c620 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
@@ -354,14 +354,14 @@ body: |
; CHECK-NEXT: %c:_(s32) = COPY $w2
; CHECK-NEXT: %d:_(s32) = COPY $w3
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane(s32), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(s32), [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(s32), [[C2]](s64)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane(s32), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(s32), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(s32), [[C2]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](i64)
; CHECK-NEXT: %buildvec:_(<4 x s32>) = COPY [[IVEC3]](<4 x s32>)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %shuf:_(<4 x s32>) = G_DUPLANE32 %buildvec, [[C4]](s64)
@@ -397,24 +397,24 @@ body: |
; CHECK-NEXT: %c:_(s32) = COPY $w3
; CHECK-NEXT: %d:_(s32) = COPY $w4
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane_0(s32), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(s32), [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(s32), [[C2]](s64)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %lane_0(s32), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %b(s32), [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], %c(s32), [[C2]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](i64)
; CHECK-NEXT: %buildvec0:_(<4 x s32>) = COPY [[IVEC3]](<4 x s32>)
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], %lane_1(s32), [[C4]](s64)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC4]], %b(s32), [[C5]](s64)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC5]], %c(s32), [[C6]](s64)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC6]], %d(s32), [[C7]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], %lane_1(s32), [[C4]](i64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC4]], %b(s32), [[C5]](i64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC5]], %c(s32), [[C6]](i64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC6]], %d(s32), [[C7]](i64)
; CHECK-NEXT: %buildvec1:_(<4 x s32>) = COPY [[IVEC7]](<4 x s32>)
; CHECK-NEXT: %shuf:_(<4 x s32>) = G_SHUFFLE_VECTOR %buildvec0(<4 x s32>), %buildvec1, shufflemask(4, 4, 4, 4)
; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll b/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
index c7ff34fd35935..5e88b22c345bb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
@@ -10,34 +10,34 @@ define <4 x ptr> @pr168872(<4 x ptr> %ptrs) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x i64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[C]](p0), [[C]](p0)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[BITCAST]](<2 x p0>), [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[BITCAST1]](<2 x p0>), [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), [[BITCAST]](<2 x p0>), [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), [[BITCAST1]](<2 x p0>), [[BUILD_VECTOR]]
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BITCAST]](<2 x p0>)
; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BITCAST1]](<2 x p0>)
; CHECK-NEXT: [[PTRTOINT2:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
; CHECK-NEXT: [[PTRTOINT3:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT]], [[ICMP]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT1]], [[ICMP1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT2]], [[XOR]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT3]], [[XOR1]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C1]](i64), [[C1]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[PTRTOINT]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[PTRTOINT1]], [[ICMP1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[PTRTOINT2]], [[XOR]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[PTRTOINT3]], [[XOR1]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR]](<2 x s64>)
; CHECK-NEXT: [[INTTOPTR1:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR1]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[INTTOPTR]](<2 x p0>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[INTTOPTR1]](<2 x p0>)
- ; CHECK-NEXT: $q0 = COPY [[BITCAST2]](<2 x s64>)
- ; CHECK-NEXT: $q1 = COPY [[BITCAST3]](<2 x s64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[INTTOPTR]](<2 x p0>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[INTTOPTR1]](<2 x p0>)
+ ; CHECK-NEXT: $q0 = COPY [[BITCAST2]](<2 x i64>)
+ ; CHECK-NEXT: $q1 = COPY [[BITCAST3]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
entry:
%cmp = icmp ugt <4 x ptr> %ptrs, zeroinitializer
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
index 4bc3b5de3ffae..d59ffff8e5629 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
@@ -41,7 +41,7 @@ body: |
%0:gpr(s32) = G_IMPLICIT_DEF
%4:gpr(p0) = G_IMPLICIT_DEF
- %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
+ %8:fpr(f32) = G_FCONSTANT float 0x7FF8000000000000
bb.1:
successors: %bb.2(0x80000000)
@@ -54,7 +54,7 @@ body: |
successors: %bb.2(0x80000000)
%3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.2
- %5:fpr(s16) = G_FPTRUNC %8(s32)
+ %5:fpr(f16) = G_FPTRUNC %8(s32)
G_STORE %3(s16), %4(p0) :: (store (s16) into `ptr undef`)
G_BR %bb.2
@@ -100,7 +100,7 @@ body: |
%0:gpr(s32) = G_IMPLICIT_DEF
%4:gpr(p0) = G_IMPLICIT_DEF
- %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
+ %8:fpr(f32) = G_FCONSTANT float 0x7FF8000000000000
bb.1:
successors: %bb.2(0x80000000)
@@ -113,7 +113,7 @@ body: |
successors: %bb.2(0x80000000)
%3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1
- %5:fpr(s16) = G_FPTRUNC %8(s32)
+ %5:fpr(f16) = G_FPTRUNC %8(s32)
G_STORE %3(s16), %4(p0) :: (store (s16) into `ptr undef`)
G_BR %bb.2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
index 496e01e8f39c4..88ecbd6bb9341 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
@@ -204,7 +204,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
@@ -257,7 +257,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
index 06c221adee123..16ab28f4bd46a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
@@ -204,7 +204,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
@@ -257,7 +257,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll b/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll
index 1758856a9722a..8a47bd8a062a4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll
@@ -6,11 +6,12 @@ define <1 x float> @ret_v1f32(<1 x float> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[DEF]](s32)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f32>) = G_BITCAST [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[BITCAST]](<2 x f32>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(f32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[UV]](f32), [[DEF]](f32)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <1 x float> %v
}
@@ -42,11 +43,11 @@ define <1 x i16> @ret_v1i16(<1 x i16> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i16>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[COPY]](<4 x i16>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i16>) = G_BUILD_VECTOR [[UV]](i16), [[DEF]](i16), [[DEF]](i16), [[DEF]](i16)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <1 x i16> %v
}
@@ -56,11 +57,11 @@ define <1 x i8> @ret_v1i8(<1 x i8> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<8 x s8>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[UV]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<8 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i8), [[UV1:%[0-9]+]]:_(i8), [[UV2:%[0-9]+]]:_(i8), [[UV3:%[0-9]+]]:_(i8), [[UV4:%[0-9]+]]:_(i8), [[UV5:%[0-9]+]]:_(i8), [[UV6:%[0-9]+]]:_(i8), [[UV7:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[COPY]](<8 x i8>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[UV]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8), [[DEF]](i8)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <1 x i8> %v
}
@@ -70,11 +71,11 @@ define <1 x i32> @ret_v1i32(<1 x i32> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[DEF]](s32)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[UV]](i32), [[DEF]](i32)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <1 x i32> %v
}
@@ -84,8 +85,8 @@ define <1 x i64> @ret_v1i64(<1 x i64> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $d0
+ ; CHECK-NEXT: $d0 = COPY [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <1 x i64> %v
}
@@ -94,11 +95,11 @@ define <1 x i1> @ret_v1i1(<1 x i1> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC]](s1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i8) = G_ZEXT [[TRUNC]](i1)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ZEXT]](i8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
ret <1 x i1> %v
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll b/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
index 04734caf01ef7..241a71105f115 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
@@ -8,9 +8,9 @@ define <4 x i1> @ret_v4i1(ptr %v) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s1>) = G_LOAD [[COPY]](p0) :: (load (<4 x s1>) from %ir.v)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[LOAD]](<4 x s1>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<4 x s16>)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x i1>) = G_LOAD [[COPY]](p0) :: (load (<4 x i1>) from %ir.v)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x i16>) = G_ANYEXT [[LOAD]](<4 x i1>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%v2 = load <4 x i1>, ptr %v
ret <4 x i1> %v2
@@ -21,12 +21,12 @@ define <1 x i12> @ret_v1i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%a = insertelement <1 x i12> poison, i12 %v1, i32 0
ret <1 x i12> %a
@@ -37,17 +37,17 @@ define <2 x i12> @ret_v2i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[IVEC1]](<2 x s12>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x i32>) = G_ANYEXT [[IVEC1]](<2 x i12>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%a = insertelement <2 x i12> poison, i12 %v1, i32 0
%b = insertelement <2 x i12> %a, i12 %v2, i32 1
@@ -59,24 +59,24 @@ define <3 x i12> @ret_v3i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC1]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s12), [[UV1:%[0-9]+]]:_(s12), [[UV2:%[0-9]+]]:_(s12) = G_UNMERGE_VALUES [[IVEC2]](<3 x s12>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s12)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s12)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](s32)
- ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC1]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i12), [[UV1:%[0-9]+]]:_(i12), [[UV2:%[0-9]+]]:_(i12) = G_UNMERGE_VALUES [[IVEC2]](<3 x i12>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UV]](i12)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[UV1]](i12)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[UV2]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2
%a = insertelement <3 x i12> poison, i12 %v1, i32 0
%b = insertelement <3 x i12> %a, i12 %v2, i32 1
@@ -89,21 +89,21 @@ define <4 x i12> @ret_v4i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[IVEC3]](<4 x s12>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<4 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x i16>) = G_ANYEXT [[IVEC3]](<4 x i12>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%a = insertelement <4 x i12> poison, i12 %v1, i32 0
%b = insertelement <4 x i12> %a, i12 %v2, i32 1
@@ -117,32 +117,32 @@ define <5 x i12> @ret_v5i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<5 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<5 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<5 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<5 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<5 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<5 x s12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](s12), [[C4]](s64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s12), [[UV1:%[0-9]+]]:_(s12), [[UV2:%[0-9]+]]:_(s12), [[UV3:%[0-9]+]]:_(s12), [[UV4:%[0-9]+]]:_(s12) = G_UNMERGE_VALUES [[IVEC4]](<5 x s12>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s12)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s12)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s12)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s12)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](s32)
- ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](s32)
- ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](s32)
- ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<5 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<5 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<5 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<5 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<5 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<5 x i12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](i12), [[C4]](i64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i12), [[UV1:%[0-9]+]]:_(i12), [[UV2:%[0-9]+]]:_(i12), [[UV3:%[0-9]+]]:_(i12), [[UV4:%[0-9]+]]:_(i12) = G_UNMERGE_VALUES [[IVEC4]](<5 x i12>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UV]](i12)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[UV1]](i12)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[UV2]](i12)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[UV3]](i12)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[UV4]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](i32)
+ ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](i32)
+ ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4
%a = insertelement <5 x i12> poison, i12 %v2, i32 0
%b = insertelement <5 x i12> %a, i12 %v1, i32 1
@@ -157,36 +157,36 @@ define <6 x i12> @ret_v6i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<6 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](s12), [[C4]](s64)
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<6 x s12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](s12), [[C5]](s64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s12), [[UV1:%[0-9]+]]:_(s12), [[UV2:%[0-9]+]]:_(s12), [[UV3:%[0-9]+]]:_(s12), [[UV4:%[0-9]+]]:_(s12), [[UV5:%[0-9]+]]:_(s12) = G_UNMERGE_VALUES [[IVEC5]](<6 x s12>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s12)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s12)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s12)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s12)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s12)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](s32)
- ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](s32)
- ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](s32)
- ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](s32)
- ; CHECK-NEXT: $w5 = COPY [[ANYEXT5]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<6 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](i12), [[C4]](i64)
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<6 x i12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](i12), [[C5]](i64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i12), [[UV1:%[0-9]+]]:_(i12), [[UV2:%[0-9]+]]:_(i12), [[UV3:%[0-9]+]]:_(i12), [[UV4:%[0-9]+]]:_(i12), [[UV5:%[0-9]+]]:_(i12) = G_UNMERGE_VALUES [[IVEC5]](<6 x i12>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UV]](i12)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[UV1]](i12)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[UV2]](i12)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[UV3]](i12)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[UV4]](i12)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[UV5]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](i32)
+ ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](i32)
+ ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](i32)
+ ; CHECK-NEXT: $w5 = COPY [[ANYEXT5]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5
%a = insertelement <6 x i12> poison, i12 %v2, i32 0
%b = insertelement <6 x i12> %a, i12 %v1, i32 1
@@ -202,40 +202,40 @@ define <7 x i12> @ret_v7i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<7 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](s12), [[C4]](s64)
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](s12), [[C5]](s64)
- ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<7 x s12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](s12), [[C6]](s64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s12), [[UV1:%[0-9]+]]:_(s12), [[UV2:%[0-9]+]]:_(s12), [[UV3:%[0-9]+]]:_(s12), [[UV4:%[0-9]+]]:_(s12), [[UV5:%[0-9]+]]:_(s12), [[UV6:%[0-9]+]]:_(s12) = G_UNMERGE_VALUES [[IVEC6]](<7 x s12>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s12)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s12)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s12)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s12)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s12)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s12)
- ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](s32)
- ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](s32)
- ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](s32)
- ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](s32)
- ; CHECK-NEXT: $w5 = COPY [[ANYEXT5]](s32)
- ; CHECK-NEXT: $w6 = COPY [[ANYEXT6]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<7 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](i12), [[C4]](i64)
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](i12), [[C5]](i64)
+ ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<7 x i12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](i12), [[C6]](i64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i12), [[UV1:%[0-9]+]]:_(i12), [[UV2:%[0-9]+]]:_(i12), [[UV3:%[0-9]+]]:_(i12), [[UV4:%[0-9]+]]:_(i12), [[UV5:%[0-9]+]]:_(i12), [[UV6:%[0-9]+]]:_(i12) = G_UNMERGE_VALUES [[IVEC6]](<7 x i12>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[UV]](i12)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[UV1]](i12)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[UV2]](i12)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[UV3]](i12)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[UV4]](i12)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[UV5]](i12)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[UV6]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: $w1 = COPY [[ANYEXT1]](i32)
+ ; CHECK-NEXT: $w2 = COPY [[ANYEXT2]](i32)
+ ; CHECK-NEXT: $w3 = COPY [[ANYEXT3]](i32)
+ ; CHECK-NEXT: $w4 = COPY [[ANYEXT4]](i32)
+ ; CHECK-NEXT: $w5 = COPY [[ANYEXT5]](i32)
+ ; CHECK-NEXT: $w6 = COPY [[ANYEXT6]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1, implicit $w2, implicit $w3, implicit $w4, implicit $w5, implicit $w6
%a = insertelement <7 x i12> poison, i12 %v2, i32 0
%b = insertelement <7 x i12> %a, i12 %v1, i32 1
@@ -252,29 +252,29 @@ define <8 x i12> @ret_v8i12(i12 %v1, i12 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](s12), [[C4]](s64)
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](s12), [[C5]](s64)
- ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](s12), [[C6]](s64)
- ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<8 x s12>) = G_INSERT_VECTOR_ELT [[IVEC6]], [[TRUNC]](s12), [[C7]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[IVEC7]](<8 x s12>)
- ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](i12), [[C4]](i64)
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](i12), [[C5]](i64)
+ ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](i12), [[C6]](i64)
+ ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<8 x i12>) = G_INSERT_VECTOR_ELT [[IVEC6]], [[TRUNC]](i12), [[C7]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x i16>) = G_ANYEXT [[IVEC7]](<8 x i12>)
+ ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<8 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%a = insertelement <8 x i12> poison, i12 %v2, i32 0
%b = insertelement <8 x i12> %a, i12 %v1, i32 1
@@ -293,36 +293,36 @@ define <12 x i12> @ret_v12i12(i12 %v1, i12 %v2) {
; CHECK-NEXT: liveins: $w0, $w1, $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY2]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<12 x s12>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 9
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 11
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](s12), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](s12), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s12), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s12), [[C3]](s64)
- ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](s12), [[C4]](s64)
- ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](s12), [[C5]](s64)
- ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](s12), [[C6]](s64)
- ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC6]], [[TRUNC]](s12), [[C7]](s64)
- ; CHECK-NEXT: [[IVEC8:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC7]], [[TRUNC]](s12), [[C8]](s64)
- ; CHECK-NEXT: [[IVEC9:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC8]], [[TRUNC]](s12), [[C9]](s64)
- ; CHECK-NEXT: [[IVEC10:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC9]], [[TRUNC]](s12), [[C10]](s64)
- ; CHECK-NEXT: [[IVEC11:%[0-9]+]]:_(<12 x s12>) = G_INSERT_VECTOR_ELT [[IVEC10]], [[TRUNC]](s12), [[C11]](s64)
- ; CHECK-NEXT: G_STORE [[IVEC11]](<12 x s12>), [[COPY]](p0) :: (store (<12 x s12>), align 32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i12) = G_TRUNC [[COPY2]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<12 x i12>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 9
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i64) = G_CONSTANT i64 10
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i64) = G_CONSTANT i64 11
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC1]](i12), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC]](i12), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i12), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i12), [[C3]](i64)
+ ; CHECK-NEXT: [[IVEC4:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC3]], [[TRUNC1]](i12), [[C4]](i64)
+ ; CHECK-NEXT: [[IVEC5:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC4]], [[TRUNC]](i12), [[C5]](i64)
+ ; CHECK-NEXT: [[IVEC6:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC5]], [[TRUNC]](i12), [[C6]](i64)
+ ; CHECK-NEXT: [[IVEC7:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC6]], [[TRUNC]](i12), [[C7]](i64)
+ ; CHECK-NEXT: [[IVEC8:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC7]], [[TRUNC]](i12), [[C8]](i64)
+ ; CHECK-NEXT: [[IVEC9:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC8]], [[TRUNC]](i12), [[C9]](i64)
+ ; CHECK-NEXT: [[IVEC10:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC9]], [[TRUNC]](i12), [[C10]](i64)
+ ; CHECK-NEXT: [[IVEC11:%[0-9]+]]:_(<12 x i12>) = G_INSERT_VECTOR_ELT [[IVEC10]], [[TRUNC]](i12), [[C11]](i64)
+ ; CHECK-NEXT: G_STORE [[IVEC11]](<12 x i12>), [[COPY]](p0) :: (store (<12 x i12>), align 32)
; CHECK-NEXT: RET_ReallyLR
%a = insertelement <12 x i12> poison, i12 %v2, i32 0
%b = insertelement <12 x i12> %a, i12 %v1, i32 1
@@ -345,18 +345,18 @@ define <1 x i100> @ret_v1i100(i100 %v1, i100 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%a = insertelement <1 x i100> poison, i100 %v1, i32 0
ret <1 x i100> %a
@@ -367,25 +367,25 @@ define <2 x i100> @ret_v2i100(i100 %v1, i100 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s100>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s100), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s100), [[C1]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s128>) = G_ANYEXT [[IVEC1]](<2 x s100>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](<2 x s128>)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i100>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i100), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x i100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i100), [[C1]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s128>) = G_ANYEXT [[IVEC1]](<2 x i100>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<2 x s128>)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2, implicit $x3
%a = insertelement <2 x i100> poison, i100 %v1, i32 0
%b = insertelement <2 x i100> %a, i100 %v2, i32 1
@@ -397,29 +397,29 @@ define <3 x i100> @ret_v3i100(i100 %v1, i100 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x s100>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s100), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x s100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s100), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x s100>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC1]](s100), [[C2]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<3 x s128>) = G_ANYEXT [[IVEC2]](<3 x s100>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](<3 x s128>)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
- ; CHECK-NEXT: $x4 = COPY [[UV4]](s64)
- ; CHECK-NEXT: $x5 = COPY [[UV5]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x i100>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x i100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i100), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x i100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i100), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x i100>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC1]](i100), [[C2]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<3 x s128>) = G_ANYEXT [[IVEC2]](<3 x i100>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64), [[UV4:%[0-9]+]]:_(i64), [[UV5:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<3 x s128>)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
+ ; CHECK-NEXT: $x4 = COPY [[UV4]](i64)
+ ; CHECK-NEXT: $x5 = COPY [[UV5]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5
%a = insertelement <3 x i100> poison, i100 %v1, i32 0
%b = insertelement <3 x i100> %a, i100 %v2, i32 1
@@ -432,33 +432,33 @@ define <4 x i100> @ret_v4i100(i100 %v1, i100 %v2) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s100>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s100), [[C]](s64)
- ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x s100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s100), [[C1]](s64)
- ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x s100>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](s100), [[C2]](s64)
- ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s100>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](s100), [[C3]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s128>) = G_ANYEXT [[IVEC3]](<4 x s100>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64), [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](<4 x s128>)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
- ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
- ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
- ; CHECK-NEXT: $x4 = COPY [[UV4]](s64)
- ; CHECK-NEXT: $x5 = COPY [[UV5]](s64)
- ; CHECK-NEXT: $x6 = COPY [[UV6]](s64)
- ; CHECK-NEXT: $x7 = COPY [[UV7]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i100>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i100), [[C]](i64)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i100), [[C1]](i64)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i100), [[C2]](i64)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i100), [[C3]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s128>) = G_ANYEXT [[IVEC3]](<4 x i100>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64), [[UV4:%[0-9]+]]:_(i64), [[UV5:%[0-9]+]]:_(i64), [[UV6:%[0-9]+]]:_(i64), [[UV7:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<4 x s128>)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[UV3]](i64)
+ ; CHECK-NEXT: $x4 = COPY [[UV4]](i64)
+ ; CHECK-NEXT: $x5 = COPY [[UV5]](i64)
+ ; CHECK-NEXT: $x6 = COPY [[UV6]](i64)
+ ; CHECK-NEXT: $x7 = COPY [[UV7]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7
%a = insertelement <4 x i100> poison, i100 %v1, i32 0
%b = insertelement <4 x i100> %a, i100 %v2, i32 1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
index 41231eae78195..9f43e1a1ab42a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
@@ -917,10 +917,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FADDSrr]]
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = G_FADD %0, %1
- $s0 = COPY %2(s32)
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = G_FADD %0, %1
+ $s0 = COPY %2(f32)
...
---
@@ -944,10 +944,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FADDDrr]]
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
- %2(s64) = G_FADD %0, %1
- $d0 = COPY %2(s64)
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
+ %2(f64) = G_FADD %0, %1
+ $d0 = COPY %2(f64)
...
---
@@ -971,10 +971,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FSUBSrr]]
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = G_FSUB %0, %1
- $s0 = COPY %2(s32)
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = G_FSUB %0, %1
+ $s0 = COPY %2(f32)
...
---
@@ -998,10 +998,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FSUBDrr]]
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
- %2(s64) = G_FSUB %0, %1
- $d0 = COPY %2(s64)
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
+ %2(f64) = G_FSUB %0, %1
+ $d0 = COPY %2(f64)
...
---
@@ -1025,10 +1025,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FMULSrr]]
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = G_FMUL %0, %1
- $s0 = COPY %2(s32)
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = G_FMUL %0, %1
+ $s0 = COPY %2(f32)
...
---
@@ -1052,10 +1052,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FMULDrr]]
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
- %2(s64) = G_FMUL %0, %1
- $d0 = COPY %2(s64)
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
+ %2(f64) = G_FMUL %0, %1
+ $d0 = COPY %2(f64)
...
---
@@ -1079,10 +1079,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FDIVSrr]]
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = G_FDIV %0, %1
- $s0 = COPY %2(s32)
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = G_FDIV %0, %1
+ $s0 = COPY %2(f32)
...
---
@@ -1106,10 +1106,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FDIVDrr]]
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
- %2(s64) = G_FDIV %0, %1
- $d0 = COPY %2(s64)
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
+ %2(f64) = G_FDIV %0, %1
+ $d0 = COPY %2(f64)
...
---
name: add_v8i16
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
index c0150ae9f73f7..d6adac923f2d5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
@@ -15,9 +15,9 @@ body: |
; CHECK-LABEL: name: ceil_float
; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FRINTPSr %{{[0-9]+}}
liveins: $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FCEIL %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FCEIL %0
+ $s0 = COPY %1(f32)
...
---
@@ -33,9 +33,9 @@ body: |
; CHECK-LABEL: name: ceil_double
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPDr %{{[0-9]+}}
liveins: $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FCEIL %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FCEIL %0
+ $d0 = COPY %1(f64)
...
---
@@ -51,9 +51,9 @@ body: |
; CHECK-LABEL: name: ceil_v2f32
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPv2f32 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FCEIL %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FCEIL %0
+ $d0 = COPY %1(<2 x f32>)
...
---
@@ -69,9 +69,9 @@ body: |
; CHECK-LABEL: name: ceil_v4f32
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv4f32 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_FCEIL %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_FCEIL %0
+ $q0 = COPY %1(<4 x f32>)
...
---
@@ -87,9 +87,9 @@ body: |
; CHECK-LABEL: name: ceil_v2f64
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv2f64 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FCEIL %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FCEIL %0
+ $q0 = COPY %1(<2 x f64>)
...
---
@@ -105,9 +105,9 @@ body: |
; CHECK-LABEL: name: ceil_v4f16
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPv4f16 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FCEIL %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FCEIL %0
+ $d0 = COPY %1(<4 x f16>)
...
---
@@ -123,8 +123,8 @@ body: |
; CHECK-LABEL: name: ceil_v8f16
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv8f16 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FCEIL %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FCEIL %0
+ $q0 = COPY %1(<8 x f16>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
index 8ce47079d9e7e..de1775ef8369a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -140,8 +140,8 @@ body: |
; CHECK-LABEL: name: fconst_s32
; CHECK: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 12
; CHECK-NEXT: $s0 = COPY [[FMOVSi]]
- %0(s32) = G_FCONSTANT float 3.5
- $s0 = COPY %0(s32)
+ %0(f32) = G_FCONSTANT float 3.5
+ $s0 = COPY %0(f32)
...
---
@@ -156,8 +156,8 @@ body: |
; CHECK-LABEL: name: fconst_s64
; CHECK: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112
; CHECK-NEXT: $d0 = COPY [[FMOVDi]]
- %0(s64) = G_FCONSTANT double 1.0
- $d0 = COPY %0(s64)
+ %0(f64) = G_FCONSTANT double 1.0
+ $d0 = COPY %0(f64)
...
---
@@ -172,8 +172,8 @@ body: |
; CHECK-LABEL: name: fconst_s32_0
; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
; CHECK-NEXT: $s0 = COPY [[FMOVS0_]]
- %0(s32) = G_FCONSTANT float 0.0
- $s0 = COPY %0(s32)
+ %0(f32) = G_FCONSTANT float 0.0
+ $s0 = COPY %0(f32)
...
---
@@ -188,8 +188,8 @@ body: |
; CHECK-LABEL: name: fconst_s64_0
; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
; CHECK-NEXT: $x0 = COPY [[FMOVD0_]]
- %0(s64) = G_FCONSTANT double 0.0
- $x0 = COPY %0(s64)
+ %0(f64) = G_FCONSTANT double 0.0
+ $x0 = COPY %0(f64)
...
---
name: optnone_i64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
index 2007ff68e73c8..7c2fcb568754d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
@@ -19,9 +19,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv4i32gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<4 x s32>) = G_DUP %copy(s32)
- $q0 = COPY %dup(<4 x s32>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<4 x i32>) = G_DUP %copy(i32)
+ $q0 = COPY %dup(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -41,9 +41,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv2i64gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s64) = COPY $x0
- %dup:fpr(<2 x s64>) = G_DUP %copy(s64)
- $q0 = COPY %dup(<2 x s64>)
+ %copy:gpr(i64) = COPY $x0
+ %dup:fpr(<2 x i64>) = G_DUP %copy(i64)
+ $q0 = COPY %dup(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -63,9 +63,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv2i32gpr %copy
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<2 x s32>) = G_DUP %copy(s32)
- $d0 = COPY %dup(<2 x s32>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<2 x i32>) = G_DUP %copy(i32)
+ $d0 = COPY %dup(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -88,9 +88,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv4i32lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(s32) = COPY $s0
- %dup:fpr(<4 x s32>) = G_DUP %copy(s32)
- $q0 = COPY %dup(<4 x s32>)
+ %copy:fpr(i32) = COPY $s0
+ %dup:fpr(<4 x i32>) = G_DUP %copy(i32)
+ $q0 = COPY %dup(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -112,9 +112,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv2i64lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(s64) = COPY $d0
- %dup:fpr(<2 x s64>) = G_DUP %copy(s64)
- $q0 = COPY %dup(<2 x s64>)
+ %copy:fpr(i64) = COPY $d0
+ %dup:fpr(<2 x i64>) = G_DUP %copy(i64)
+ $q0 = COPY %dup(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -136,9 +136,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(s32) = COPY $s0
- %dup:fpr(<2 x s32>) = G_DUP %copy(s32)
- $d0 = COPY %dup(<2 x s32>)
+ %copy:fpr(i32) = COPY $s0
+ %dup:fpr(<2 x i32>) = G_DUP %copy(i32)
+ $d0 = COPY %dup(<2 x i32>)
RET_ReallyLR implicit $d0
@@ -161,9 +161,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(s16) = COPY $h0
- %dup:fpr(<4 x s16>) = G_DUP %copy(s16)
- $d0 = COPY %dup(<4 x s16>)
+ %copy:fpr(i16) = COPY $h0
+ %dup:fpr(<4 x i16>) = G_DUP %copy(i16)
+ $d0 = COPY %dup(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -182,9 +182,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<4 x s16>) = G_DUP %copy(s32)
- $d0 = COPY %dup(<4 x s16>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<4 x i16>) = G_DUP %copy(i32)
+ $d0 = COPY %dup(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -206,9 +206,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv8i16lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(s16) = COPY $h0
- %dup:fpr(<8 x s16>) = G_DUP %copy(s16)
- $q0 = COPY %dup(<8 x s16>)
+ %copy:fpr(i16) = COPY $h0
+ %dup:fpr(<8 x i16>) = G_DUP %copy(i16)
+ $q0 = COPY %dup(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -228,9 +228,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<8 x s16>) = G_DUP %copy(s32)
- $q0 = COPY %dup(<8 x s16>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<8 x i16>) = G_DUP %copy(i32)
+ $q0 = COPY %dup(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -250,10 +250,10 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s32) = COPY $w0
- %trunc:gpr(s16) = G_TRUNC %copy
- %dup:fpr(<8 x s16>) = G_DUP %trunc(s16)
- $q0 = COPY %dup(<8 x s16>)
+ %copy:gpr(i32) = COPY $w0
+ %trunc:gpr(i16) = G_TRUNC %copy
+ %dup:fpr(<8 x i16>) = G_DUP %trunc(i16)
+ $q0 = COPY %dup(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -273,10 +273,10 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:gpr(s32) = COPY $w0
- %trunc:gpr(s16) = G_TRUNC %copy
- %dup:fpr(<4 x s16>) = G_DUP %trunc(s16)
- $d0 = COPY %dup(<4 x s16>)
+ %copy:gpr(i32) = COPY $w0
+ %trunc:gpr(i16) = G_TRUNC %copy
+ %dup:fpr(<4 x i16>) = G_DUP %trunc(i16)
+ $d0 = COPY %dup(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -296,9 +296,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<8 x s8>) = G_DUP %copy(s32)
- $d0 = COPY %dup(<8 x s8>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<8 x i8>) = G_DUP %copy(i32)
+ $d0 = COPY %dup(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -318,10 +318,10 @@ body: |
; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:gpr(s32) = COPY $w0
- %trunc:gpr(s8) = G_TRUNC %copy(s32)
- %dup:fpr(<8 x s8>) = G_DUP %trunc(s8)
- $d0 = COPY %dup(<8 x s8>)
+ %copy:gpr(i32) = COPY $w0
+ %trunc:gpr(i8) = G_TRUNC %copy(i32)
+ %dup:fpr(<8 x i8>) = G_DUP %trunc(i8)
+ $d0 = COPY %dup(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -341,9 +341,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s32) = COPY $w0
- %dup:fpr(<16 x s8>) = G_DUP %copy(s32)
- $q0 = COPY %dup(<16 x s8>)
+ %copy:gpr(i32) = COPY $w0
+ %dup:fpr(<16 x i8>) = G_DUP %copy(i32)
+ $q0 = COPY %dup(<16 x i8>)
RET_ReallyLR implicit $q0
...
---
@@ -362,10 +362,10 @@ body: |
; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:gpr(s32) = COPY $w0
- %trunc:gpr(s8) = G_TRUNC %copy
- %dup:fpr(<16 x s8>) = G_DUP %trunc(s8)
- $q0 = COPY %dup(<16 x s8>)
+ %copy:gpr(i32) = COPY $w0
+ %trunc:gpr(i8) = G_TRUNC %copy
+ %dup:fpr(<16 x i8>) = G_DUP %trunc(i8)
+ $q0 = COPY %dup(<16 x i8>)
RET_ReallyLR implicit $q0
...
---
@@ -408,9 +408,9 @@ body: |
; CHECK-NEXT: %dup:fpr128 = MOVIv4i32 3, 0
; CHECK-NEXT: $q0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %cst:gpr(s32) = G_CONSTANT i32 3
- %dup:fpr(<4 x s32>) = G_DUP %cst(s32)
- $q0 = COPY %dup(<4 x s32>)
+ %cst:gpr(i32) = G_CONSTANT i32 3
+ %dup:fpr(<4 x i32>) = G_DUP %cst(i32)
+ $q0 = COPY %dup(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -428,9 +428,9 @@ body: |
; CHECK-NEXT: %dup:fpr64 = MOVIv8b_ns 3
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %cst:gpr(s8) = G_CONSTANT i8 3
- %dup:fpr(<8 x s8>) = G_DUP %cst(s8)
- $d0 = COPY %dup(<8 x s8>)
+ %cst:gpr(i8) = G_CONSTANT i8 3
+ %dup:fpr(<8 x i8>) = G_DUP %cst(i8)
+ $d0 = COPY %dup(<8 x i8>)
RET_ReallyLR implicit $d0
...
---
@@ -445,7 +445,7 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
- ; CHECK-NEXT: %cst:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
+ ; CHECK-NEXT: %cst:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %cst
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
@@ -468,9 +468,9 @@ body: |
; CHECK: %dup:fpr64 = MOVIv4i16 3, 0
; CHECK-NEXT: $d0 = COPY %dup
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %cst:gpr(s32) = G_CONSTANT i32 3
- %dup:fpr(<4 x s16>) = G_DUP %cst(s32)
- $d0 = COPY %dup(<4 x s16>)
+ %cst:gpr(i32) = G_CONSTANT i32 3
+ %dup:fpr(<4 x i16>) = G_DUP %cst(i32)
+ $d0 = COPY %dup(<4 x i16>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fabs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fabs.mir
index e7d74cc4baa60..f538431d9052a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fabs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fabs.mir
@@ -15,9 +15,9 @@ body: |
; CHECK-LABEL: name: fabs_float
; CHECK: %{{[0-9]+}}:fpr32 = FABSSr %{{[0-9]+}}
liveins: $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FABS %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FABS %0
+ $s0 = COPY %1(f32)
...
---
@@ -33,9 +33,9 @@ body: |
; CHECK-LABEL: name: fabs_double
; CHECK: %{{[0-9]+}}:fpr64 = FABSDr %{{[0-9]+}}
liveins: $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FABS %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FABS %0
+ $d0 = COPY %1(f64)
...
---
@@ -51,9 +51,9 @@ body: |
; CHECK-LABEL: name: fabs_v2f32
; CHECK: %{{[0-9]+}}:fpr64 = FABSv2f32 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FABS %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FABS %0
+ $d0 = COPY %1(<2 x f32>)
...
---
@@ -69,9 +69,9 @@ body: |
; CHECK-LABEL: name: fabs_v4f32
; CHECK: %{{[0-9]+}}:fpr128 = FABSv4f32 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_FABS %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_FABS %0
+ $q0 = COPY %1(<4 x f32>)
...
---
@@ -87,9 +87,9 @@ body: |
; CHECK-LABEL: name: fabs_v2f64
; CHECK: %{{[0-9]+}}:fpr128 = FABSv2f64 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FABS %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FABS %0
+ $q0 = COPY %1(<2 x f64>)
...
---
@@ -105,9 +105,9 @@ body: |
; CHECK-LABEL: name: fabs_v4f16
; CHECK: %{{[0-9]+}}:fpr64 = FABSv4f16 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FABS %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FABS %0
+ $d0 = COPY %1(<4 x f16>)
...
---
@@ -123,8 +123,8 @@ body: |
; CHECK-LABEL: name: fabs_v8f16
; CHECK: %{{[0-9]+}}:fpr128 = FABSv8f16 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FABS %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FABS %0
+ $q0 = COPY %1(<8 x f16>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
index 20a37f2573569..f3004fb652a7a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
@@ -21,13 +21,13 @@ body: |
; CHECK-NEXT: [[FADDPv2i64p:%[0-9]+]]:fpr64 = nofpexcept FADDPv2i64p [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FADDPv2i64p]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %6:gpr(s64) = G_CONSTANT i64 0
- %7:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %6(s64)
- %8:gpr(s64) = G_CONSTANT i64 1
- %9:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %8(s64)
- %4:fpr(s64) = G_FADD %7, %9
- $d0 = COPY %4(s64)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %6:gpr(i64) = G_CONSTANT i64 0
+ %7:fpr(f64) = G_EXTRACT_VECTOR_ELT %0(<2 x f64>), %6(i64)
+ %8:gpr(i64) = G_CONSTANT i64 1
+ %9:fpr(f64) = G_EXTRACT_VECTOR_ELT %0(<2 x f64>), %8(i64)
+ %4:fpr(f64) = G_FADD %7, %9
+ $d0 = COPY %4(f64)
RET_ReallyLR implicit $d0
...
@@ -52,13 +52,13 @@ body: |
; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nofpexcept FADDPv2i32p [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(<2 x s32>) = COPY $d0
- %6:gpr(s64) = G_CONSTANT i64 0
- %7:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %6(s64)
- %8:gpr(s64) = G_CONSTANT i64 1
- %9:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %8(s64)
- %4:fpr(s32) = G_FADD %7, %9
- $s0 = COPY %4(s32)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %6:gpr(i64) = G_CONSTANT i64 0
+ %7:fpr(f32) = G_EXTRACT_VECTOR_ELT %0(<2 x f32>), %6(i64)
+ %8:gpr(i64) = G_CONSTANT i64 1
+ %9:fpr(f32) = G_EXTRACT_VECTOR_ELT %0(<2 x f32>), %8(i64)
+ %4:fpr(f32) = G_FADD %7, %9
+ $s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
index 62d55a270b5e2..e2d8dfa63abeb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
@@ -50,11 +50,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 1.000000e+00
- %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
- $s0 = COPY %3(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 1.000000e+00
+ %3:gpr(f32) = G_FCMP floatpred(oeq), %0(f32), %2
+ $s0 = COPY %3(f32)
RET_ReallyLR implicit $s0
...
@@ -78,11 +78,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 1.000000e+00
- %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
- $s0 = COPY %3(s32)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 1.000000e+00
+ %3:gpr(i32) = G_FCMP floatpred(oeq), %0(f64), %2
+ $s0 = COPY %3(i32)
RET_ReallyLR implicit $s0
@@ -105,11 +105,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = COPY $d1
- %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
- %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
- $s0 = COPY %3(s32)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = COPY $d1
+ %2:fpr(f64) = G_FCONSTANT double 0.000000e+00
+ %3:gpr(i32) = G_FCMP floatpred(oeq), %0(f64), %2
+ $s0 = COPY %3(i32)
RET_ReallyLR implicit $s0
...
@@ -131,11 +131,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %3:gpr(s32) = G_FCMP floatpred(oeq), %2(s32), %0
- $s0 = COPY %3(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %3:gpr(i32) = G_FCMP floatpred(oeq), %2(f32), %0
+ $s0 = COPY %3(i32)
RET_ReallyLR implicit $s0
...
@@ -158,11 +158,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = COPY $s1
- %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
- %3:gpr(s32) = G_FCMP floatpred(olt), %2(s32), %0
- $s0 = COPY %3(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = COPY $s1
+ %2:fpr(f32) = G_FCONSTANT float 0.000000e+00
+ %3:gpr(i32) = G_FCMP floatpred(olt), %2(f32), %0
+ $s0 = COPY %3(i32)
RET_ReallyLR implicit $s0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
index af2478393f3f2..360369416191b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
@@ -15,9 +15,9 @@ body: |
; CHECK-LABEL: name: floor_float
; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FRINTMSr %{{[0-9]+}}
liveins: $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FFLOOR %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FFLOOR %0
+ $s0 = COPY %1(f32)
...
---
@@ -33,9 +33,9 @@ body: |
; CHECK-LABEL: name: floor_double
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMDr %{{[0-9]+}}
liveins: $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FFLOOR %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FFLOOR %0
+ $d0 = COPY %1(f64)
...
---
@@ -51,9 +51,9 @@ body: |
; CHECK-LABEL: name: floor_v2f32
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMv2f32 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FFLOOR %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FFLOOR %0
+ $d0 = COPY %1(<2 x f32>)
...
---
@@ -69,9 +69,9 @@ body: |
; CHECK-LABEL: name: floor_v4f32
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv4f32 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_FFLOOR %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_FFLOOR %0
+ $q0 = COPY %1(<4 x f32>)
...
---
@@ -87,9 +87,9 @@ body: |
; CHECK-LABEL: name: floor_v2f64
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv2f64 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FFLOOR %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FFLOOR %0
+ $q0 = COPY %1(<2 x f64>)
...
---
@@ -105,9 +105,9 @@ body: |
; CHECK-LABEL: name: floor_v4f16
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMv4f16 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FFLOOR %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FFLOOR %0
+ $d0 = COPY %1(<4 x f16>)
...
---
@@ -123,8 +123,8 @@ body: |
; CHECK-LABEL: name: floor_v8f16
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv8f16 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FFLOOR %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FFLOOR %0
+ $q0 = COPY %1(<8 x f16>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir
index fb04eff54e041..072346df06bc3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmaximum.mir
@@ -19,10 +19,10 @@ body: |
; CHECK-NEXT: %select_me:fpr16 = nofpexcept FMAXHrr %a, %b, implicit $fpcr
; CHECK-NEXT: $h0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %a:fpr(s16) = COPY $h0
- %b:fpr(s16) = COPY $h1
- %select_me:fpr(s16) = G_FMAXIMUM %a, %b
- $h0 = COPY %select_me(s16)
+ %a:fpr(f16) = COPY $h0
+ %b:fpr(f16) = COPY $h1
+ %select_me:fpr(f16) = G_FMAXIMUM %a, %b
+ $h0 = COPY %select_me(f16)
RET_ReallyLR implicit $h0
...
@@ -43,10 +43,10 @@ body: |
; CHECK-NEXT: %select_me:fpr32 = nofpexcept FMAXSrr %a, %b, implicit $fpcr
; CHECK-NEXT: $s0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %a:fpr(s32) = COPY $s0
- %b:fpr(s32) = COPY $s1
- %select_me:fpr(s32) = G_FMAXIMUM %a, %b
- $s0 = COPY %select_me(s32)
+ %a:fpr(f32) = COPY $s0
+ %b:fpr(f32) = COPY $s1
+ %select_me:fpr(f32) = G_FMAXIMUM %a, %b
+ $s0 = COPY %select_me(f32)
RET_ReallyLR implicit $s0
...
@@ -67,8 +67,8 @@ body: |
; CHECK-NEXT: %select_me:fpr64 = nofpexcept FMAXDrr %a, %b, implicit $fpcr
; CHECK-NEXT: $d0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:fpr(s64) = COPY $d0
- %b:fpr(s64) = COPY $d1
- %select_me:fpr(s64) = G_FMAXIMUM %a, %b
- $d0 = COPY %select_me(s64)
+ %a:fpr(f64) = COPY $d0
+ %b:fpr(f64) = COPY $d1
+ %select_me:fpr(f64) = G_FMAXIMUM %a, %b
+ $d0 = COPY %select_me(f64)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir
index 457a6ef1d123f..453e8669864d5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fminimum.mir
@@ -19,10 +19,10 @@ body: |
; CHECK-NEXT: %select_me:fpr16 = nofpexcept FMINHrr %a, %b, implicit $fpcr
; CHECK-NEXT: $h0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %a:fpr(s16) = COPY $h0
- %b:fpr(s16) = COPY $h1
- %select_me:fpr(s16) = G_FMINIMUM %a, %b
- $h0 = COPY %select_me(s16)
+ %a:fpr(f16) = COPY $h0
+ %b:fpr(f16) = COPY $h1
+ %select_me:fpr(f16) = G_FMINIMUM %a, %b
+ $h0 = COPY %select_me(f16)
RET_ReallyLR implicit $h0
...
@@ -43,10 +43,10 @@ body: |
; CHECK-NEXT: %select_me:fpr32 = nofpexcept FMINSrr %a, %b, implicit $fpcr
; CHECK-NEXT: $s0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %a:fpr(s32) = COPY $s0
- %b:fpr(s32) = COPY $s1
- %select_me:fpr(s32) = G_FMINIMUM %a, %b
- $s0 = COPY %select_me(s32)
+ %a:fpr(f32) = COPY $s0
+ %b:fpr(f32) = COPY $s1
+ %select_me:fpr(f32) = G_FMINIMUM %a, %b
+ $s0 = COPY %select_me(f32)
RET_ReallyLR implicit $s0
...
@@ -67,8 +67,8 @@ body: |
; CHECK-NEXT: %select_me:fpr64 = nofpexcept FMINDrr %a, %b, implicit $fpcr
; CHECK-NEXT: $d0 = COPY %select_me
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %a:fpr(s64) = COPY $d0
- %b:fpr(s64) = COPY $d1
- %select_me:fpr(s64) = G_FMINIMUM %a, %b
- $d0 = COPY %select_me(s64)
+ %a:fpr(f64) = COPY $d0
+ %b:fpr(f64) = COPY $d1
+ %select_me:fpr(f64) = G_FMINIMUM %a, %b
+ $d0 = COPY %select_me(f64)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
index 491835a5079d7..5bee4c06670aa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
@@ -21,21 +21,21 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<2 x s32>), align 4)
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<2 x f32>), align 4)
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRDui]], %subreg.dsub
; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = nofpexcept FMULv2i32_indexed [[COPY]], [[INSERT_SUBREG]], 0, implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FMULv2i32_indexed]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
+ %0:fpr(<2 x f32>) = COPY $d0
%1:gpr(p0) = COPY $x0
- %2:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>), align 4)
- %9:fpr(<2 x s32>) = G_IMPLICIT_DEF
- %10:fpr(<4 x s32>) = G_CONCAT_VECTORS %2(<2 x s32>), %9(<2 x s32>)
- %8:gpr(s64) = G_CONSTANT i64 0
- %5:fpr(<2 x s32>) = G_DUPLANE32 %10, %8(s64)
- %7:fpr(<2 x s32>) = G_FMUL %0, %5
- $d0 = COPY %7(<2 x s32>)
+ %2:fpr(<2 x f32>) = G_LOAD %1(p0) :: (load (<2 x f32>), align 4)
+ %9:fpr(<2 x f32>) = G_IMPLICIT_DEF
+ %10:fpr(<4 x f32>) = G_CONCAT_VECTORS %2(<2 x f32>), %9(<2 x f32>)
+ %8:gpr(i64) = G_CONSTANT i64 0
+ %5:fpr(<2 x f32>) = G_DUPLANE32 %10, %8(i64)
+ %7:fpr(<2 x f32>) = G_FMUL %0, %5
+ $d0 = COPY %7(<2 x f32>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
index a58492114003a..9bc66bbdcb6b0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FCVTHSr]]
- %0(s32) = COPY $s0
- %1(s16) = G_FPTRUNC %0
- $h0 = COPY %1(s16)
+ %0(f32) = COPY $s0
+ %1(f16) = G_FPTRUNC %0
+ $h0 = COPY %1(f16)
...
---
@@ -44,9 +44,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTHDr:%[0-9]+]]:fpr16 = nofpexcept FCVTHDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FCVTHDr]]
- %0(s64) = COPY $d0
- %1(s16) = G_FPTRUNC %0
- $h0 = COPY %1(s16)
+ %0(f64) = COPY $d0
+ %1(f16) = G_FPTRUNC %0
+ $h0 = COPY %1(f16)
...
---
@@ -68,9 +68,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTSDr:%[0-9]+]]:fpr32 = nofpexcept FCVTSDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FCVTSDr]]
- %0(s64) = COPY $d0
- %1(s32) = G_FPTRUNC %0
- $s0 = COPY %1(s32)
+ %0(f64) = COPY $d0
+ %1(f32) = G_FPTRUNC %0
+ $s0 = COPY %1(f32)
...
---
@@ -91,9 +91,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTNv4i16_]]
- %0(<4 x s32>) = COPY $q0
- %1(<4 x s16>) = G_FPTRUNC %0
- $d0 = COPY %1(<4 x s16>)
+ %0(<4 x f32>) = COPY $q0
+ %1(<4 x f16>) = G_FPTRUNC %0
+ $d0 = COPY %1(<4 x f16>)
...
---
@@ -114,9 +114,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTNv2i32_]]
- %0(<2 x s64>) = COPY $q0
- %1(<2 x s32>) = G_FPTRUNC %0
- $d0 = COPY %1(<2 x s32>)
+ %0(<2 x f64>) = COPY $q0
+ %1(<2 x f32>) = G_FPTRUNC %0
+ $d0 = COPY %1(<2 x f32>)
...
---
@@ -138,9 +138,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FCVTSHr]]
- %0(s16) = COPY $h0
- %1(s32) = G_FPEXT %0
- $s0 = COPY %1(s32)
+ %0(f16) = COPY $h0
+ %1(f32) = G_FPEXT %0
+ $s0 = COPY %1(f32)
...
---
@@ -162,9 +162,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
; CHECK-NEXT: [[FCVTDHr:%[0-9]+]]:fpr64 = nofpexcept FCVTDHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTDHr]]
- %0(s16) = COPY $h0
- %1(s64) = G_FPEXT %0
- $d0 = COPY %1(s64)
+ %0(f16) = COPY $h0
+ %1(f64) = G_FPEXT %0
+ $d0 = COPY %1(f64)
...
---
@@ -186,9 +186,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTDSr:%[0-9]+]]:fpr64 = nofpexcept FCVTDSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FCVTDSr]]
- %0(s32) = COPY $s0
- %1(s64) = G_FPEXT %0
- $d0 = COPY %1(s64)
+ %0(f32) = COPY $s0
+ %1(f64) = G_FPEXT %0
+ $d0 = COPY %1(f64)
...
---
@@ -209,9 +209,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FCVTLv4i16_]]
- %0(<4 x s16>) = COPY $d0
- %1(<4 x s32>) = G_FPEXT %0
- $q0 = COPY %1(<4 x s32>)
+ %0(<4 x f16>) = COPY $d0
+ %1(<4 x f32>) = G_FPEXT %0
+ $q0 = COPY %1(<4 x f32>)
...
---
@@ -232,9 +232,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FCVTLv2i32_]]
- %0(<2 x s32>) = COPY $d0
- %1(<2 x s64>) = G_FPEXT %0
- $q0 = COPY %1(<2 x s64>)
+ %0(<2 x f32>) = COPY $d0
+ %1(<2 x f64>) = G_FPEXT %0
+ $q0 = COPY %1(<2 x f64>)
...
---
@@ -256,9 +256,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SCVTFUWSri:%[0-9]+]]:fpr32 = nofpexcept SCVTFUWSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[SCVTFUWSri]]
- %0(s32) = COPY $w0
- %1(s32) = G_SITOFP %0
- $s0 = COPY %1(s32)
+ %0(i32) = COPY $w0
+ %1(f32) = G_SITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -280,9 +280,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[SCVTFv1i32_:%[0-9]+]]:fpr32 = nofpexcept SCVTFv1i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[SCVTFv1i32_]]
- %0(s32) = COPY $s0
- %1(s32) = G_SITOFP %0
- $s0 = COPY %1(s32)
+ %0(i32) = COPY $s0
+ %1(f32) = G_SITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -304,9 +304,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[UCVTFv1i32_:%[0-9]+]]:fpr32 = nofpexcept UCVTFv1i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[UCVTFv1i32_]]
- %0(s32) = COPY $s0
- %1(s32) = G_UITOFP %0
- $s0 = COPY %1(s32)
+ %0(i32) = COPY $s0
+ %1(f32) = G_UITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -328,9 +328,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[SCVTFUXSri:%[0-9]+]]:fpr32 = nofpexcept SCVTFUXSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[SCVTFUXSri]]
- %0(s64) = COPY $x0
- %1(s32) = G_SITOFP %0
- $s0 = COPY %1(s32)
+ %0(i64) = COPY $x0
+ %1(f32) = G_SITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -352,9 +352,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUWDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[SCVTFUWDri]]
- %0(s32) = COPY $w0
- %1(s64) = G_SITOFP %0
- $d0 = COPY %1(s64)
+ %0(i32) = COPY $w0
+ %1(f64) = G_SITOFP %0
+ $d0 = COPY %1(f64)
...
---
@@ -376,9 +376,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[SCVTFUXDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUXDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[SCVTFUXDri]]
- %0(s64) = COPY $x0
- %1(s64) = G_SITOFP %0
- $d0 = COPY %1(s64)
+ %0(i64) = COPY $x0
+ %1(f64) = G_SITOFP %0
+ $d0 = COPY %1(f64)
...
---
@@ -400,9 +400,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UCVTFUWSri:%[0-9]+]]:fpr32 = nofpexcept UCVTFUWSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[UCVTFUWSri]]
- %0(s32) = COPY $w0
- %1(s32) = G_UITOFP %0
- $s0 = COPY %1(s32)
+ %0(i32) = COPY $w0
+ %1(f32) = G_UITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -424,9 +424,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[UCVTFUXSri:%[0-9]+]]:fpr32 = nofpexcept UCVTFUXSri [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[UCVTFUXSri]]
- %0(s64) = COPY $x0
- %1(s32) = G_UITOFP %0
- $s0 = COPY %1(s32)
+ %0(i64) = COPY $x0
+ %1(f32) = G_UITOFP %0
+ $s0 = COPY %1(f32)
...
---
@@ -448,9 +448,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept UCVTFUWDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[UCVTFUWDri]]
- %0(s32) = COPY $w0
- %1(s64) = G_UITOFP %0
- $d0 = COPY %1(s64)
+ %0(i32) = COPY $w0
+ %1(f64) = G_UITOFP %0
+ $d0 = COPY %1(f64)
...
---
@@ -472,9 +472,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[UCVTFUXDri:%[0-9]+]]:fpr64 = nofpexcept UCVTFUXDri [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[UCVTFUXDri]]
- %0(s64) = COPY $x0
- %1(s64) = G_UITOFP %0
- $d0 = COPY %1(s64)
+ %0(i64) = COPY $x0
+ %1(f64) = G_UITOFP %0
+ $d0 = COPY %1(f64)
...
---
@@ -496,9 +496,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = nofpexcept FCVTZSUWSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZSUWSr]]
- %0(s32) = COPY $s0
- %1(s32) = G_FPTOSI %0
- $w0 = COPY %1(s32)
+ %0(f32) = COPY $s0
+ %1(i32) = G_FPTOSI %0
+ $w0 = COPY %1(i32)
...
---
@@ -520,9 +520,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = nofpexcept FCVTZSUWDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZSUWDr]]
- %0(s64) = COPY $d0
- %1(s32) = G_FPTOSI %0
- $w0 = COPY %1(s32)
+ %0(f64) = COPY $d0
+ %1(i32) = G_FPTOSI %0
+ $w0 = COPY %1(i32)
...
---
@@ -544,9 +544,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = nofpexcept FCVTZSUXSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZSUXSr]]
- %0(s32) = COPY $s0
- %1(s64) = G_FPTOSI %0
- $x0 = COPY %1(s64)
+ %0(f32) = COPY $s0
+ %1(i64) = G_FPTOSI %0
+ $x0 = COPY %1(i64)
...
---
@@ -568,9 +568,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = nofpexcept FCVTZSUXDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZSUXDr]]
- %0(s64) = COPY $d0
- %1(s64) = G_FPTOSI %0
- $x0 = COPY %1(s64)
+ %0(f64) = COPY $d0
+ %1(i64) = G_FPTOSI %0
+ $x0 = COPY %1(i64)
...
---
@@ -592,9 +592,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = nofpexcept FCVTZUUWSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZUUWSr]]
- %0(s32) = COPY $s0
- %1(s32) = G_FPTOUI %0
- $w0 = COPY %1(s32)
+ %0(f32) = COPY $s0
+ %1(i32) = G_FPTOUI %0
+ $w0 = COPY %1(i32)
...
---
@@ -616,9 +616,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = nofpexcept FCVTZUUWDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FCVTZUUWDr]]
- %0(s64) = COPY $d0
- %1(s32) = G_FPTOUI %0
- $w0 = COPY %1(s32)
+ %0(f64) = COPY $d0
+ %1(i32) = G_FPTOUI %0
+ $w0 = COPY %1(i32)
...
---
@@ -640,9 +640,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = nofpexcept FCVTZUUXSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZUUXSr]]
- %0(s32) = COPY $s0
- %1(s64) = G_FPTOUI %0
- $x0 = COPY %1(s64)
+ %0(f32) = COPY $s0
+ %1(i64) = G_FPTOUI %0
+ $x0 = COPY %1(i64)
...
---
@@ -664,7 +664,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = nofpexcept FCVTZUUXDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FCVTZUUXDr]]
- %0(s64) = COPY $d0
- %1(s64) = G_FPTOUI %0
- $x0 = COPY %1(s64)
+ %0(f64) = COPY $d0
+ %1(i64) = G_FPTOUI %0
+ $x0 = COPY %1(i64)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp16-fconstant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp16-fconstant.mir
index 5b6726d6e5bf3..7c7a9cee81ba4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp16-fconstant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp16-fconstant.mir
@@ -12,8 +12,8 @@ body: |
; CHECK: [[FMOVH0_:%[0-9]+]]:fpr16 = FMOVH0
; CHECK-NEXT: $h0 = COPY [[FMOVH0_]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = G_FCONSTANT half 0.0
- $h0 = COPY %0(s16)
+ %0:fpr(f16) = G_FCONSTANT half 0.0
+ $h0 = COPY %0(f16)
RET_ReallyLR implicit $h0
...
---
@@ -27,8 +27,8 @@ body: |
; CHECK: [[FMOVHi:%[0-9]+]]:fpr16 = FMOVHi 112
; CHECK-NEXT: $h0 = COPY [[FMOVHi]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = G_FCONSTANT half 1.0
- $h0 = COPY %0(s16)
+ %0:fpr(f16) = G_FCONSTANT half 1.0
+ $h0 = COPY %0(f16)
RET_ReallyLR implicit $h0
...
---
@@ -43,6 +43,6 @@ body: |
; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s16) from constant-pool)
; CHECK-NEXT: $h0 = COPY [[LDRHui]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = G_FCONSTANT half 0xH000B
- $h0 = COPY %0(s16)
+ %0:fpr(f16) = G_FCONSTANT half 0xH000B
+ $h0 = COPY %0(f16)
RET_ReallyLR implicit $h0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
index fe4adfac8e721..1ca06aa2c70ea 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
@@ -22,11 +22,11 @@ body: |
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FCVTHSr]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = COPY $h0
- %2:fpr(s32) = G_FPEXT %0(s16)
- %3:fpr(s32) = G_FRINT %2
- %1:fpr(s16) = G_FPTRUNC %3(s32)
- $h0 = COPY %1(s16)
+ %0:fpr(f16) = COPY $h0
+ %2:fpr(f32) = G_FPEXT %0(f16)
+ %3:fpr(f32) = G_FRINT %2
+ %1:fpr(f16) = G_FPTRUNC %3(f32)
+ $h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
...
@@ -81,22 +81,22 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
- %16:fpr(s32) = G_FPEXT %2(s16)
- %17:fpr(s32) = G_FRINT %16
- %6:fpr(s16) = G_FPTRUNC %17(s32)
- %14:fpr(s32) = G_FPEXT %3(s16)
- %15:fpr(s32) = G_FRINT %14
- %7:fpr(s16) = G_FPTRUNC %15(s32)
- %12:fpr(s32) = G_FPEXT %4(s16)
- %13:fpr(s32) = G_FRINT %12
- %8:fpr(s16) = G_FPTRUNC %13(s32)
- %10:fpr(s32) = G_FPEXT %5(s16)
- %11:fpr(s32) = G_FRINT %10
- %9:fpr(s16) = G_FPTRUNC %11(s32)
- %1:fpr(<4 x s16>) = G_BUILD_VECTOR %6(s16), %7(s16), %8(s16), %9(s16)
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %2:fpr(f16), %3:fpr(f16), %4:fpr(f16), %5:fpr(f16) = G_UNMERGE_VALUES %0(<4 x f16>)
+ %16:fpr(f32) = G_FPEXT %2(f16)
+ %17:fpr(f32) = G_FRINT %16
+ %6:fpr(f16) = G_FPTRUNC %17(f32)
+ %14:fpr(f32) = G_FPEXT %3(f16)
+ %15:fpr(f32) = G_FRINT %14
+ %7:fpr(f16) = G_FPTRUNC %15(f32)
+ %12:fpr(f32) = G_FPEXT %4(f16)
+ %13:fpr(f32) = G_FRINT %12
+ %8:fpr(f16) = G_FPTRUNC %13(f32)
+ %10:fpr(f32) = G_FPEXT %5(f16)
+ %11:fpr(f32) = G_FRINT %10
+ %9:fpr(f16) = G_FPTRUNC %11(f32)
+ %1:fpr(<4 x f16>) = G_BUILD_VECTOR %6(f16), %7(f16), %8(f16), %9(f16)
+ $d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
@@ -172,32 +172,32 @@ body: |
; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
- %32:fpr(s32) = G_FPEXT %2(s16)
- %33:fpr(s32) = G_FRINT %32
- %10:fpr(s16) = G_FPTRUNC %33(s32)
- %30:fpr(s32) = G_FPEXT %3(s16)
- %31:fpr(s32) = G_FRINT %30
- %11:fpr(s16) = G_FPTRUNC %31(s32)
- %28:fpr(s32) = G_FPEXT %4(s16)
- %29:fpr(s32) = G_FRINT %28
- %12:fpr(s16) = G_FPTRUNC %29(s32)
- %26:fpr(s32) = G_FPEXT %5(s16)
- %27:fpr(s32) = G_FRINT %26
- %13:fpr(s16) = G_FPTRUNC %27(s32)
- %24:fpr(s32) = G_FPEXT %6(s16)
- %25:fpr(s32) = G_FRINT %24
- %14:fpr(s16) = G_FPTRUNC %25(s32)
- %22:fpr(s32) = G_FPEXT %7(s16)
- %23:fpr(s32) = G_FRINT %22
- %15:fpr(s16) = G_FPTRUNC %23(s32)
- %20:fpr(s32) = G_FPEXT %8(s16)
- %21:fpr(s32) = G_FRINT %20
- %16:fpr(s16) = G_FPTRUNC %21(s32)
- %18:fpr(s32) = G_FPEXT %9(s16)
- %19:fpr(s32) = G_FRINT %18
- %17:fpr(s16) = G_FPTRUNC %19(s32)
- %1:fpr(<8 x s16>) = G_BUILD_VECTOR %10(s16), %11(s16), %12(s16), %13(s16), %14(s16), %15(s16), %16(s16), %17(s16)
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %2:fpr(f16), %3:fpr(f16), %4:fpr(f16), %5:fpr(f16), %6:fpr(f16), %7:fpr(f16), %8:fpr(f16), %9:fpr(f16) = G_UNMERGE_VALUES %0(<8 x s16>)
+ %32:fpr(f32) = G_FPEXT %2(f16)
+ %33:fpr(f32) = G_FRINT %32
+ %10:fpr(f16) = G_FPTRUNC %33(f32)
+ %30:fpr(f32) = G_FPEXT %3(f16)
+ %31:fpr(f32) = G_FRINT %30
+ %11:fpr(f16) = G_FPTRUNC %31(f32)
+ %28:fpr(f32) = G_FPEXT %4(f16)
+ %29:fpr(f32) = G_FRINT %28
+ %12:fpr(f16) = G_FPTRUNC %29(f32)
+ %26:fpr(f32) = G_FPEXT %5(f16)
+ %27:fpr(f32) = G_FRINT %26
+ %13:fpr(f16) = G_FPTRUNC %27(f32)
+ %24:fpr(f32) = G_FPEXT %6(f16)
+ %25:fpr(f32) = G_FRINT %24
+ %14:fpr(f16) = G_FPTRUNC %25(f32)
+ %22:fpr(f32) = G_FPEXT %7(f16)
+ %23:fpr(f32) = G_FRINT %22
+ %15:fpr(f16) = G_FPTRUNC %23(f32)
+ %20:fpr(f32) = G_FPEXT %8(f16)
+ %21:fpr(f32) = G_FRINT %20
+ %16:fpr(f16) = G_FPTRUNC %21(f32)
+ %18:fpr(f32) = G_FPEXT %9(f16)
+ %19:fpr(f32) = G_FRINT %18
+ %17:fpr(f16) = G_FPTRUNC %19(f32)
+ %1:fpr(<8 x f16>) = G_BUILD_VECTOR %10(f16), %11(f16), %12(f16), %13(f16), %14(f16), %15(f16), %16(f16), %17(f16)
+ $q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
index 737c31cd81796..dd83cfa9d6320 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[FRINTXHr:%[0-9]+]]:fpr16 = nofpexcept FRINTXHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FRINTXHr]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = COPY $h0
- %1:fpr(s16) = G_FRINT %0
- $h0 = COPY %1(s16)
+ %0:fpr(f16) = COPY $h0
+ %1:fpr(f16) = G_FRINT %0
+ $h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
...
@@ -44,9 +44,9 @@ body: |
; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FRINTXSr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FRINT %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FRINT %0
+ $s0 = COPY %1(f32)
RET_ReallyLR implicit $s0
...
@@ -68,9 +68,9 @@ body: |
; CHECK-NEXT: [[FRINTXDr:%[0-9]+]]:fpr64 = nofpexcept FRINTXDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTXDr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FRINT %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FRINT %0
+ $d0 = COPY %1(f64)
RET_ReallyLR implicit $d0
...
@@ -92,9 +92,9 @@ body: |
; CHECK-NEXT: [[FRINTXv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTXv4f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_FRINT %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_FRINT %0
+ $q0 = COPY %1(<4 x f32>)
RET_ReallyLR implicit $q0
...
@@ -116,9 +116,9 @@ body: |
; CHECK-NEXT: [[FRINTXv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTXv2f64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FRINT %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FRINT %0
+ $q0 = COPY %1(<2 x f64>)
RET_ReallyLR implicit $q0
...
@@ -140,9 +140,9 @@ body: |
; CHECK-NEXT: [[FRINTXv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTXv4f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTXv4f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FRINT %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FRINT %0
+ $d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
@@ -164,9 +164,9 @@ body: |
; CHECK-NEXT: [[FRINTXv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv8f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTXv8f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FRINT %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FRINT %0
+ $q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
...
@@ -188,9 +188,9 @@ body: |
; CHECK-NEXT: [[FRINTXv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTXv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTXv2f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FRINT %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FRINT %0
+ $d0 = COPY %1(<2 x f32>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
index ce7dc4feb187c..07e2e189b4c03 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
@@ -104,10 +104,10 @@ body: |
; CHECK-TINY-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[LDRDl]], implicit $fpcr
; CHECK-TINY-NEXT: $d0 = COPY [[FADDDrr]]
; CHECK-TINY-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FCONSTANT double 0x3FEFF7CED916872B
- %2:fpr(s64) = G_FADD %0, %1
- $d0 = COPY %2(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FCONSTANT double 0x3FEFF7CED916872B
+ %2:fpr(f64) = G_FADD %0, %1
+ $d0 = COPY %2(f64)
RET_ReallyLR implicit $d0
...
@@ -140,10 +140,10 @@ body: |
; CHECK-TINY-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSl]], implicit $fpcr
; CHECK-TINY-NEXT: $s0 = COPY [[FADDSrr]]
; CHECK-TINY-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000
- %2:fpr(s32) = G_FADD %0, %1
- $s0 = COPY %2(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FCONSTANT float 0x3FDB267DE0000000
+ %2:fpr(f32) = G_FADD %0, %1
+ $s0 = COPY %2(f32)
RET_ReallyLR implicit $s0
...
@@ -176,10 +176,10 @@ body: |
; CHECK-TINY-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSl]], implicit $fpcr
; CHECK-TINY-NEXT: $s0 = COPY [[FADDSrr]]
; CHECK-TINY-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000
- %2:fpr(s32) = G_FADD %0, %1
- $s0 = COPY %2(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FCONSTANT float 0x3FDB267DE0000000
+ %2:fpr(f32) = G_FADD %0, %1
+ $s0 = COPY %2(f32)
RET_ReallyLR implicit $s0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
index 33f7e58804f14..ed665271472cb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
@@ -107,11 +107,11 @@ body: |
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi16lane]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(s16) = COPY $h0
- %1:fpr(<8 x s16>) = COPY $q1
- %3:gpr(s64) = G_CONSTANT i64 1
- %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s64)
- $q0 = COPY %2(<8 x s16>)
+ %0:fpr(f16) = COPY $h0
+ %1:fpr(<8 x f16>) = COPY $q1
+ %3:gpr(i64) = G_CONSTANT i64 1
+ %2:fpr(<8 x f16>) = G_INSERT_VECTOR_ELT %1, %0(f16), %3(i64)
+ $q0 = COPY %2(<8 x f16>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
index 53f2fbb328460..dca4ebdaab165 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[FRINTADr:%[0-9]+]]:fpr64 = nofpexcept FRINTADr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTADr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_INTRINSIC_ROUND %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_INTRINSIC_ROUND %0
+ $d0 = COPY %1(f64)
RET_ReallyLR implicit $d0
...
@@ -44,9 +44,9 @@ body: |
; CHECK-NEXT: [[FRINTASr:%[0-9]+]]:fpr32 = nofpexcept FRINTASr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FRINTASr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_INTRINSIC_ROUND %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_INTRINSIC_ROUND %0
+ $s0 = COPY %1(f32)
RET_ReallyLR implicit $s0
...
@@ -70,9 +70,9 @@ body: |
; CHECK-NEXT: [[FRINTAHr:%[0-9]+]]:fpr16 = nofpexcept FRINTAHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FRINTAHr]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = COPY $h0
- %1:fpr(s16) = G_INTRINSIC_ROUND %0
- $h0 = COPY %1(s16)
+ %0:fpr(f16) = COPY $h0
+ %1:fpr(f16) = G_INTRINSIC_ROUND %0
+ $h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
...
@@ -96,9 +96,9 @@ body: |
; CHECK-NEXT: [[FRINTAv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv4f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTAv4f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_INTRINSIC_ROUND %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_INTRINSIC_ROUND %0
+ $d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
@@ -122,9 +122,9 @@ body: |
; CHECK-NEXT: [[FRINTAv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv8f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTAv8f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_INTRINSIC_ROUND %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_INTRINSIC_ROUND %0
+ $q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
...
@@ -148,9 +148,9 @@ body: |
; CHECK-NEXT: [[FRINTAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTAv2f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_INTRINSIC_ROUND %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_INTRINSIC_ROUND %0
+ $d0 = COPY %1(<2 x f32>)
RET_ReallyLR implicit $d0
...
@@ -174,9 +174,9 @@ body: |
; CHECK-NEXT: [[FRINTAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTAv4f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_INTRINSIC_ROUND %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_INTRINSIC_ROUND %0
+ $q0 = COPY %1(<4 x f32>)
RET_ReallyLR implicit $q0
...
@@ -200,7 +200,7 @@ body: |
; CHECK-NEXT: [[FRINTAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTAv2f64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_INTRINSIC_ROUND %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_INTRINSIC_ROUND %0
+ $q0 = COPY %1(<2 x f64>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
index 57f8ed8b459fc..aa833ede3bda5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[FRINTZDr:%[0-9]+]]:fpr64 = nofpexcept FRINTZDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTZDr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_INTRINSIC_TRUNC %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_INTRINSIC_TRUNC %0
+ $d0 = COPY %1(f64)
RET_ReallyLR implicit $d0
...
@@ -44,9 +44,9 @@ body: |
; CHECK-NEXT: [[FRINTZSr:%[0-9]+]]:fpr32 = nofpexcept FRINTZSr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FRINTZSr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_INTRINSIC_TRUNC %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_INTRINSIC_TRUNC %0
+ $s0 = COPY %1(f32)
RET_ReallyLR implicit $s0
...
@@ -70,9 +70,9 @@ body: |
; CHECK-NEXT: [[FRINTZHr:%[0-9]+]]:fpr16 = nofpexcept FRINTZHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FRINTZHr]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = COPY $h0
- %1:fpr(s16) = G_INTRINSIC_TRUNC %0
- $h0 = COPY %1(s16)
+ %0:fpr(f16) = COPY $h0
+ %1:fpr(f16) = G_INTRINSIC_TRUNC %0
+ $h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
...
@@ -96,9 +96,9 @@ body: |
; CHECK-NEXT: [[FRINTZv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTZv4f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTZv4f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_INTRINSIC_TRUNC %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_INTRINSIC_TRUNC %0
+ $d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
@@ -122,9 +122,9 @@ body: |
; CHECK-NEXT: [[FRINTZv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv8f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTZv8f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_INTRINSIC_TRUNC %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_INTRINSIC_TRUNC %0
+ $q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
...
@@ -148,9 +148,9 @@ body: |
; CHECK-NEXT: [[FRINTZv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTZv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTZv2f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_INTRINSIC_TRUNC %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_INTRINSIC_TRUNC %0
+ $d0 = COPY %1(<2 x f32>)
RET_ReallyLR implicit $d0
...
@@ -174,9 +174,9 @@ body: |
; CHECK-NEXT: [[FRINTZv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTZv4f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_INTRINSIC_TRUNC %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_INTRINSIC_TRUNC %0
+ $q0 = COPY %1(<4 x f32>)
RET_ReallyLR implicit $q0
...
@@ -200,7 +200,7 @@ body: |
; CHECK-NEXT: [[FRINTZv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTZv2f64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_INTRINSIC_TRUNC %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_INTRINSIC_TRUNC %0
+ $q0 = COPY %1(<2 x f64>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
index 9a181adfc0b31..19b1c43d605b7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
@@ -20,9 +20,9 @@ body: |
; CHECK-NEXT: [[FRINTIv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTIv4f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTIv4f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FNEARBYINT %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FNEARBYINT %0
+ $d0 = COPY %1(<4 x f16>)
RET_ReallyLR implicit $d0
...
@@ -44,9 +44,9 @@ body: |
; CHECK-NEXT: [[FRINTIv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTIv8f16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTIv8f16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FNEARBYINT %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FNEARBYINT %0
+ $q0 = COPY %1(<8 x f16>)
RET_ReallyLR implicit $q0
...
@@ -68,9 +68,9 @@ body: |
; CHECK-NEXT: [[FRINTIv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTIv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTIv2f32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FNEARBYINT %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FNEARBYINT %0
+ $d0 = COPY %1(<2 x f32>)
RET_ReallyLR implicit $d0
...
@@ -92,9 +92,9 @@ body: |
; CHECK-NEXT: [[FRINTIv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTIv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $q0 = COPY [[FRINTIv2f64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FNEARBYINT %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FNEARBYINT %0
+ $q0 = COPY %1(<2 x f64>)
RET_ReallyLR implicit $q0
...
@@ -116,9 +116,9 @@ body: |
; CHECK-NEXT: [[FRINTISr:%[0-9]+]]:fpr32 = nofpexcept FRINTISr [[COPY]], implicit $fpcr
; CHECK-NEXT: $s0 = COPY [[FRINTISr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FNEARBYINT %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FNEARBYINT %0
+ $s0 = COPY %1(f32)
RET_ReallyLR implicit $s0
...
@@ -140,9 +140,9 @@ body: |
; CHECK-NEXT: [[FRINTIDr:%[0-9]+]]:fpr64 = nofpexcept FRINTIDr [[COPY]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FRINTIDr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FNEARBYINT %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FNEARBYINT %0
+ $d0 = COPY %1(f64)
RET_ReallyLR implicit $d0
...
@@ -164,9 +164,9 @@ body: |
; CHECK-NEXT: [[FRINTIHr:%[0-9]+]]:fpr16 = nofpexcept FRINTIHr [[COPY]], implicit $fpcr
; CHECK-NEXT: $h0 = COPY [[FRINTIHr]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
- %0:fpr(s16) = COPY $h0
- %1:fpr(s16) = G_FNEARBYINT %0
- $h0 = COPY %1(s16)
+ %0:fpr(f16) = COPY $h0
+ %1:fpr(f16) = G_FNEARBYINT %0
+ $h0 = COPY %1(f16)
RET_ReallyLR implicit $h0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir
index 85d9e1ca85a33..f3339542c510a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir
@@ -16,9 +16,9 @@ body: |
; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nofpexcept FADDPv2i32p [[COPY]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FADDPv2i32p]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(s32) = G_VECREDUCE_FADD %0(<2 x s32>)
- $w0 = COPY %1(s32)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(f32) = G_VECREDUCE_FADD %0(<2 x f32>)
+ $w0 = COPY %1(f32)
RET_ReallyLR implicit $w0
...
@@ -38,9 +38,9 @@ body: |
; CHECK-NEXT: [[FADDPv2i64p:%[0-9]+]]:fpr64 = nofpexcept FADDPv2i64p [[COPY]], implicit $fpcr
; CHECK-NEXT: $x0 = COPY [[FADDPv2i64p]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:fpr(<2 x s64>) = COPY $q0
- %2:fpr(s64) = G_VECREDUCE_FADD %0(<2 x s64>)
- $x0 = COPY %2(s64)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %2:fpr(f64) = G_VECREDUCE_FADD %0(<2 x f64>)
+ $x0 = COPY %2(f64)
RET_ReallyLR implicit $x0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
index 13ce9f9966b42..daf552b401c7e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
@@ -15,9 +15,9 @@ body: |
; CHECK-LABEL: name: sqrt_float
; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FSQRTSr %{{[0-9]+}}
liveins: $s0
- %0:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FSQRT %0
- $s0 = COPY %1(s32)
+ %0:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FSQRT %0
+ $s0 = COPY %1(f32)
...
---
@@ -33,9 +33,9 @@ body: |
; CHECK-LABEL: name: sqrt_double
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTDr %{{[0-9]+}}
liveins: $d0
- %0:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FSQRT %0
- $d0 = COPY %1(s64)
+ %0:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FSQRT %0
+ $d0 = COPY %1(f64)
...
---
@@ -51,9 +51,9 @@ body: |
; CHECK-LABEL: name: sqrt_v2f32
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTv2f32 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_FSQRT %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x f32>) = COPY $d0
+ %1:fpr(<2 x f32>) = G_FSQRT %0
+ $d0 = COPY %1(<2 x f32>)
...
---
@@ -69,9 +69,9 @@ body: |
; CHECK-LABEL: name: sqrt_v4f32
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv4f32 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_FSQRT %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x f32>) = COPY $q0
+ %1:fpr(<4 x f32>) = G_FSQRT %0
+ $q0 = COPY %1(<4 x f32>)
...
---
@@ -87,9 +87,9 @@ body: |
; CHECK-LABEL: name: sqrt_v2f64
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv2f64 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_FSQRT %0
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x f64>) = COPY $q0
+ %1:fpr(<2 x f64>) = G_FSQRT %0
+ $q0 = COPY %1(<2 x f64>)
...
---
@@ -105,9 +105,9 @@ body: |
; CHECK-LABEL: name: sqrt_v4f16
; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTv4f16 %{{[0-9]+}}
liveins: $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_FSQRT %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x f16>) = COPY $d0
+ %1:fpr(<4 x f16>) = G_FSQRT %0
+ $d0 = COPY %1(<4 x f16>)
...
---
@@ -123,8 +123,8 @@ body: |
; CHECK-LABEL: name: sqrt_v8f16
; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv8f16 %{{[0-9]+}}
liveins: $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_FSQRT %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x f16>) = COPY $q0
+ %1:fpr(<8 x f16>) = G_FSQRT %0
+ $q0 = COPY %1(<8 x f16>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
index f49d8e733156d..603ded2030b8e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
@@ -22,11 +22,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128))
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (f128))
; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
- %0:fpr(s128) = G_LOAD %1(p0) :: (load (s128))
- $noreg = PATCHABLE_RET %0(s128)
+ %0:fpr(f128) = G_LOAD %1(p0) :: (load (f128))
+ $noreg = PATCHABLE_RET %0(f128)
...
---
@@ -231,11 +231,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (s128))
+ ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (f128))
; CHECK-NEXT: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
- %0:fpr(s128) = COPY $q0
- G_STORE %0(s128), %1(p0) :: (store (s128))
+ %0:fpr(f128) = COPY $q0
+ G_STORE %0(f128), %1(p0) :: (store (f128))
$noreg = PATCHABLE_RET
...
@@ -489,13 +489,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
- %5:fpr(s32) = COPY $s2
- %4:fpr(s32) = COPY $s1
- %3:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FNEG %5
- %0:fpr(s32) = G_FNEG %4
- %2:fpr(s32) = G_FMA %0, %3, %1
- $noreg = PATCHABLE_RET %2(s32)
+ %5:fpr(f32) = COPY $s2
+ %4:fpr(f32) = COPY $s1
+ %3:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FNEG %5
+ %0:fpr(f32) = G_FNEG %4
+ %2:fpr(f32) = G_FMA %0, %3, %1
+ $noreg = PATCHABLE_RET %2(f32)
...
---
@@ -527,13 +527,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
- %5:fpr(s64) = COPY $d2
- %4:fpr(s64) = COPY $d1
- %3:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FNEG %5
- %0:fpr(s64) = G_FNEG %4
- %2:fpr(s64) = G_FMA %0, %3, %1
- $noreg = PATCHABLE_RET %2(s64)
+ %5:fpr(f64) = COPY $d2
+ %4:fpr(f64) = COPY $d1
+ %3:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FNEG %5
+ %0:fpr(f64) = G_FNEG %4
+ %2:fpr(f64) = G_FMA %0, %3, %1
+ $noreg = PATCHABLE_RET %2(f64)
...
---
@@ -565,13 +565,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
- %5:fpr(s32) = COPY $s2
- %4:fpr(s32) = COPY $s1
- %3:fpr(s32) = COPY $s0
- %1:fpr(s32) = G_FNEG %5
- %0:fpr(s32) = G_FNEG %4
- %2:fpr(s32) = G_FMA %3, %0, %1
- $noreg = PATCHABLE_RET %2(s32)
+ %5:fpr(f32) = COPY $s2
+ %4:fpr(f32) = COPY $s1
+ %3:fpr(f32) = COPY $s0
+ %1:fpr(f32) = G_FNEG %5
+ %0:fpr(f32) = G_FNEG %4
+ %2:fpr(f32) = G_FMA %3, %0, %1
+ $noreg = PATCHABLE_RET %2(f32)
...
---
@@ -603,13 +603,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
- %5:fpr(s64) = COPY $d2
- %4:fpr(s64) = COPY $d1
- %3:fpr(s64) = COPY $d0
- %1:fpr(s64) = G_FNEG %5
- %0:fpr(s64) = G_FNEG %4
- %2:fpr(s64) = G_FMA %3, %0, %1
- $noreg = PATCHABLE_RET %2(s64)
+ %5:fpr(f64) = COPY $d2
+ %4:fpr(f64) = COPY $d1
+ %3:fpr(f64) = COPY $d0
+ %1:fpr(f64) = G_FNEG %5
+ %0:fpr(f64) = G_FNEG %4
+ %2:fpr(f64) = G_FMA %3, %0, %1
+ $noreg = PATCHABLE_RET %2(f64)
...
---
@@ -638,12 +638,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDLv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDLv8i8_v8i16_]]
- %4:fpr(<8 x s8>) = COPY $d1
- %3:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
- %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
- %2:fpr(<8 x s16>) = G_ADD %0, %1
- $noreg = PATCHABLE_RET %2(<8 x s16>)
+ %4:fpr(<8 x i8>) = COPY $d1
+ %3:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i16>) = G_SEXT %4(<8 x i8>)
+ %0:fpr(<8 x i16>) = G_SEXT %3(<8 x i8>)
+ %2:fpr(<8 x i16>) = G_ADD %0, %1
+ $noreg = PATCHABLE_RET %2(<8 x i16>)
...
---
@@ -1048,12 +1048,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
- %4:fpr(s32) = COPY $s2
- %3:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FNEG %4
- %1:fpr(s32) = G_FMA %0, %2, %3
- $noreg = PATCHABLE_RET %1(s32)
+ %4:fpr(f32) = COPY $s2
+ %3:fpr(f32) = COPY $s1
+ %2:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FNEG %4
+ %1:fpr(f32) = G_FMA %0, %2, %3
+ $noreg = PATCHABLE_RET %1(f32)
...
---
@@ -1084,12 +1084,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
- %4:fpr(s64) = COPY $d2
- %3:fpr(s64) = COPY $d1
- %2:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FNEG %4
- %1:fpr(s64) = G_FMA %0, %2, %3
- $noreg = PATCHABLE_RET %1(s64)
+ %4:fpr(f64) = COPY $d2
+ %3:fpr(f64) = COPY $d1
+ %2:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FNEG %4
+ %1:fpr(f64) = G_FMA %0, %2, %3
+ $noreg = PATCHABLE_RET %1(f64)
...
---
@@ -1120,12 +1120,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
- %4:fpr(<2 x s32>) = COPY $d2
- %3:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FNEG %4
- %1:fpr(<2 x s32>) = G_FMA %0, %2, %3
- $noreg = PATCHABLE_RET %1(<2 x s32>)
+ %4:fpr(<2 x f32>) = COPY $d2
+ %3:fpr(<2 x f32>) = COPY $d1
+ %2:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FNEG %4
+ %1:fpr(<2 x f32>) = G_FMA %0, %2, %3
+ $noreg = PATCHABLE_RET %1(<2 x f32>)
...
---
@@ -1156,12 +1156,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
- %4:fpr(<4 x s32>) = COPY $q2
- %3:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FNEG %4
- %1:fpr(<4 x s32>) = G_FMA %0, %2, %3
- $noreg = PATCHABLE_RET %1(<4 x s32>)
+ %4:fpr(<4 x f32>) = COPY $q2
+ %3:fpr(<4 x f32>) = COPY $q1
+ %2:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FNEG %4
+ %1:fpr(<4 x f32>) = G_FMA %0, %2, %3
+ $noreg = PATCHABLE_RET %1(<4 x f32>)
...
---
@@ -1192,12 +1192,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
- %4:fpr(<2 x s64>) = COPY $q2
- %3:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FNEG %4
- %1:fpr(<2 x s64>) = G_FMA %0, %2, %3
- $noreg = PATCHABLE_RET %1(<2 x s64>)
+ %4:fpr(<2 x f64>) = COPY $q2
+ %3:fpr(<2 x f64>) = COPY $q1
+ %2:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FNEG %4
+ %1:fpr(<2 x f64>) = G_FMA %0, %2, %3
+ $noreg = PATCHABLE_RET %1(<2 x f64>)
...
---
@@ -1228,12 +1228,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
- %4:fpr(s32) = COPY $s2
- %3:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FNEG %4
- %1:fpr(s32) = G_FMA %2, %0, %3
- $noreg = PATCHABLE_RET %1(s32)
+ %4:fpr(f32) = COPY $s2
+ %3:fpr(f32) = COPY $s1
+ %2:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FNEG %4
+ %1:fpr(f32) = G_FMA %2, %0, %3
+ $noreg = PATCHABLE_RET %1(f32)
...
---
@@ -1264,12 +1264,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
- %4:fpr(s64) = COPY $d2
- %3:fpr(s64) = COPY $d1
- %2:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FNEG %4
- %1:fpr(s64) = G_FMA %2, %0, %3
- $noreg = PATCHABLE_RET %1(s64)
+ %4:fpr(f64) = COPY $d2
+ %3:fpr(f64) = COPY $d1
+ %2:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FNEG %4
+ %1:fpr(f64) = G_FMA %2, %0, %3
+ $noreg = PATCHABLE_RET %1(f64)
...
---
@@ -1300,12 +1300,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
- %4:fpr(<2 x s32>) = COPY $d2
- %3:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FNEG %4
- %1:fpr(<2 x s32>) = G_FMA %2, %0, %3
- $noreg = PATCHABLE_RET %1(<2 x s32>)
+ %4:fpr(<2 x f32>) = COPY $d2
+ %3:fpr(<2 x f32>) = COPY $d1
+ %2:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FNEG %4
+ %1:fpr(<2 x f32>) = G_FMA %2, %0, %3
+ $noreg = PATCHABLE_RET %1(<2 x f32>)
...
---
@@ -1336,12 +1336,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
- %4:fpr(<4 x s32>) = COPY $q2
- %3:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FNEG %4
- %1:fpr(<4 x s32>) = G_FMA %2, %0, %3
- $noreg = PATCHABLE_RET %1(<4 x s32>)
+ %4:fpr(<4 x f32>) = COPY $q2
+ %3:fpr(<4 x f32>) = COPY $q1
+ %2:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FNEG %4
+ %1:fpr(<4 x f32>) = G_FMA %2, %0, %3
+ $noreg = PATCHABLE_RET %1(<4 x f32>)
...
---
@@ -1372,12 +1372,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
- %4:fpr(<2 x s64>) = COPY $q2
- %3:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FNEG %4
- %1:fpr(<2 x s64>) = G_FMA %2, %0, %3
- $noreg = PATCHABLE_RET %1(<2 x s64>)
+ %4:fpr(<2 x f64>) = COPY $q2
+ %3:fpr(<2 x f64>) = COPY $q1
+ %2:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FNEG %4
+ %1:fpr(<2 x f64>) = G_FMA %2, %0, %3
+ $noreg = PATCHABLE_RET %1(<2 x f64>)
...
---
@@ -1408,12 +1408,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMSUBSrrr]]
- %4:fpr(s32) = COPY $s2
- %3:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FNEG %4
- %1:fpr(s32) = G_FMA %2, %3, %0
- $noreg = PATCHABLE_RET %1(s32)
+ %4:fpr(f32) = COPY $s2
+ %3:fpr(f32) = COPY $s1
+ %2:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FNEG %4
+ %1:fpr(f32) = G_FMA %2, %3, %0
+ $noreg = PATCHABLE_RET %1(f32)
...
---
@@ -1444,12 +1444,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMSUBDrrr]]
- %4:fpr(s64) = COPY $d2
- %3:fpr(s64) = COPY $d1
- %2:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FNEG %4
- %1:fpr(s64) = G_FMA %2, %3, %0
- $noreg = PATCHABLE_RET %1(s64)
+ %4:fpr(f64) = COPY $d2
+ %3:fpr(f64) = COPY $d1
+ %2:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FNEG %4
+ %1:fpr(f64) = G_FMA %2, %3, %0
+ $noreg = PATCHABLE_RET %1(f64)
...
---
@@ -2500,12 +2500,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
- %4:fpr(s32) = COPY $s2
- %3:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FMA %2, %3, %4
- %1:fpr(s32) = G_FNEG %0
- $noreg = PATCHABLE_RET %1(s32)
+ %4:fpr(f32) = COPY $s2
+ %3:fpr(f32) = COPY $s1
+ %2:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FMA %2, %3, %4
+ %1:fpr(f32) = G_FNEG %0
+ $noreg = PATCHABLE_RET %1(f32)
...
---
@@ -2536,12 +2536,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
- %4:fpr(s64) = COPY $d2
- %3:fpr(s64) = COPY $d1
- %2:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FMA %2, %3, %4
- %1:fpr(s64) = G_FNEG %0
- $noreg = PATCHABLE_RET %1(s64)
+ %4:fpr(f64) = COPY $d2
+ %3:fpr(f64) = COPY $d1
+ %2:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FMA %2, %3, %4
+ %1:fpr(f64) = G_FNEG %0
+ $noreg = PATCHABLE_RET %1(f64)
...
---
@@ -2569,11 +2569,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNMULSrr:%[0-9]+]]:fpr32 = nofpexcept FNMULSrr [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMULSrr]]
- %3:fpr(s32) = COPY $s1
- %2:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FMUL %2, %3
- %1:fpr(s32) = G_FNEG %0
- $noreg = PATCHABLE_RET %1(s32)
+ %3:fpr(f32) = COPY $s1
+ %2:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FMUL %2, %3
+ %1:fpr(f32) = G_FNEG %0
+ $noreg = PATCHABLE_RET %1(f32)
...
---
@@ -2601,11 +2601,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNMULDrr:%[0-9]+]]:fpr64 = nofpexcept FNMULDrr [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNMULDrr]]
- %3:fpr(s64) = COPY $d1
- %2:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FMUL %2, %3
- %1:fpr(s64) = G_FNEG %0
- $noreg = PATCHABLE_RET %1(s64)
+ %3:fpr(f64) = COPY $d1
+ %2:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FMUL %2, %3
+ %1:fpr(f64) = G_FNEG %0
+ $noreg = PATCHABLE_RET %1(f64)
...
---
@@ -2695,11 +2695,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMLAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLAv2f32_]]
- %3:fpr(<2 x s32>) = COPY $d2
- %2:fpr(<2 x s32>) = COPY $d1
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FMA %1, %2, %3
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %3:fpr(<2 x f32>) = COPY $d2
+ %2:fpr(<2 x f32>) = COPY $d1
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FMA %1, %2, %3
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -2729,11 +2729,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLAv4f32_]]
- %3:fpr(<4 x s32>) = COPY $q2
- %2:fpr(<4 x s32>) = COPY $q1
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FMA %1, %2, %3
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %3:fpr(<4 x f32>) = COPY $q2
+ %2:fpr(<4 x f32>) = COPY $q1
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FMA %1, %2, %3
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -2763,11 +2763,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMLAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMLAv2f64_]]
- %3:fpr(<2 x s64>) = COPY $q2
- %2:fpr(<2 x s64>) = COPY $q1
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FMA %1, %2, %3
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %3:fpr(<2 x f64>) = COPY $q2
+ %2:fpr(<2 x f64>) = COPY $q1
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FMA %1, %2, %3
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -3034,10 +3034,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = nofpexcept FADDv2f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FADDv2f32_]]
- %2:fpr(<2 x s32>) = COPY $d1
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FADD %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %2:fpr(<2 x f32>) = COPY $d1
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FADD %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -3064,10 +3064,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDv4f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FADDv4f32_]]
- %2:fpr(<4 x s32>) = COPY $q1
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FADD %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %2:fpr(<4 x f32>) = COPY $q1
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FADD %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -3094,10 +3094,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FADDv2f64_:%[0-9]+]]:fpr128 = nofpexcept FADDv2f64 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FADDv2f64_]]
- %2:fpr(<2 x s64>) = COPY $q1
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FADD %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %2:fpr(<2 x f64>) = COPY $q1
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FADD %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -3124,10 +3124,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FDIVv2f32_:%[0-9]+]]:fpr64 = nofpexcept FDIVv2f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FDIVv2f32_]]
- %2:fpr(<2 x s32>) = COPY $d1
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FDIV %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %2:fpr(<2 x f32>) = COPY $d1
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FDIV %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -3154,10 +3154,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FDIVv4f32_:%[0-9]+]]:fpr128 = nofpexcept FDIVv4f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FDIVv4f32_]]
- %2:fpr(<4 x s32>) = COPY $q1
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FDIV %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %2:fpr(<4 x f32>) = COPY $q1
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FDIV %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -3184,10 +3184,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FDIVv2f64_:%[0-9]+]]:fpr128 = nofpexcept FDIVv2f64 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FDIVv2f64_]]
- %2:fpr(<2 x s64>) = COPY $q1
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FDIV %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %2:fpr(<2 x f64>) = COPY $q1
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FDIV %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -3214,10 +3214,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FMULv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMULv2f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMULv2f32_]]
- %2:fpr(<2 x s32>) = COPY $d1
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FMUL %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %2:fpr(<2 x f32>) = COPY $d1
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FMUL %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -3244,10 +3244,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMULv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMULv4f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMULv4f32_]]
- %2:fpr(<4 x s32>) = COPY $q1
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FMUL %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %2:fpr(<4 x f32>) = COPY $q1
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FMUL %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -3274,10 +3274,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FMULv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMULv2f64 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FMULv2f64_]]
- %2:fpr(<2 x s64>) = COPY $q1
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FMUL %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %2:fpr(<2 x f64>) = COPY $q1
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FMUL %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -3304,10 +3304,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FSUBv2f32_:%[0-9]+]]:fpr64 = nofpexcept FSUBv2f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FSUBv2f32_]]
- %2:fpr(<2 x s32>) = COPY $d1
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FSUB %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %2:fpr(<2 x f32>) = COPY $d1
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FSUB %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -3334,10 +3334,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FSUBv4f32_:%[0-9]+]]:fpr128 = nofpexcept FSUBv4f32 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FSUBv4f32_]]
- %2:fpr(<4 x s32>) = COPY $q1
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FSUB %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %2:fpr(<4 x f32>) = COPY $q1
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FSUB %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -3364,10 +3364,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FSUBv2f64_:%[0-9]+]]:fpr128 = nofpexcept FSUBv2f64 [[COPY1]], [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FSUBv2f64_]]
- %2:fpr(<2 x s64>) = COPY $q1
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FSUB %1, %2
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %2:fpr(<2 x f64>) = COPY $q1
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FSUB %1, %2
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -3949,9 +3949,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[FNEGSr:%[0-9]+]]:fpr32 = FNEGSr [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGSr]]
- %1:fpr(s32) = COPY $s0
- %0:fpr(s32) = G_FNEG %1
- $noreg = PATCHABLE_RET %0(s32)
+ %1:fpr(f32) = COPY $s0
+ %0:fpr(f32) = G_FNEG %1
+ $noreg = PATCHABLE_RET %0(f32)
...
---
@@ -3975,9 +3975,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGDr]]
- %1:fpr(s64) = COPY $d0
- %0:fpr(s64) = G_FNEG %1
- $noreg = PATCHABLE_RET %0(s64)
+ %1:fpr(f64) = COPY $d0
+ %0:fpr(f64) = G_FNEG %1
+ $noreg = PATCHABLE_RET %0(f64)
...
---
@@ -4001,9 +4001,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FNEGv2f32_:%[0-9]+]]:fpr64 = FNEGv2f32 [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGv2f32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FNEG %1
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_FNEG %1
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -4027,9 +4027,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FNEGv4f32_:%[0-9]+]]:fpr128 = FNEGv4f32 [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGv4f32_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FNEG %1
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_FNEG %1
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -4053,9 +4053,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FNEGv2f64_:%[0-9]+]]:fpr128 = FNEGv2f64 [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FNEGv2f64_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FNEG %1
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_FNEG %1
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -4079,9 +4079,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTLv2i32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x f64>) = G_FPEXT %1(<2 x f32>)
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -4105,9 +4105,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTLv4i16_]]
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x f16>) = COPY $d0
+ %0:fpr(<4 x f32>) = G_FPEXT %1(<4 x f16>)
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -4131,9 +4131,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZSv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZSv2f32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x i32>) = G_FPTOSI %1(<2 x f32>)
+ $noreg = PATCHABLE_RET %0(<2 x i32>)
...
---
@@ -4157,9 +4157,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZSv4f32_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x i32>) = G_FPTOSI %1(<4 x f32>)
+ $noreg = PATCHABLE_RET %0(<4 x i32>)
...
---
@@ -4183,9 +4183,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZSv2f64_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x i64>) = G_FPTOSI %1(<2 x f64>)
+ $noreg = PATCHABLE_RET %0(<2 x i64>)
...
---
@@ -4209,9 +4209,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZUv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZUv2f32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x f32>) = COPY $d0
+ %0:fpr(<2 x i32>) = G_FPTOUI %1(<2 x f32>)
+ $noreg = PATCHABLE_RET %0(<2 x i32>)
...
---
@@ -4235,9 +4235,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZUv4f32_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x i32>) = G_FPTOUI %1(<4 x f32>)
+ $noreg = PATCHABLE_RET %0(<4 x i32>)
...
---
@@ -4261,9 +4261,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTZUv2f64_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x i64>) = G_FPTOUI %1(<2 x f64>)
+ $noreg = PATCHABLE_RET %0(<2 x i64>)
...
---
@@ -4287,9 +4287,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTNv2i32_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x f64>) = COPY $q0
+ %0:fpr(<2 x f32>) = G_FPTRUNC %1(<2 x f64>)
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -4313,9 +4313,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[FCVTNv4i16_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s16>)
+ %1:fpr(<4 x f32>) = COPY $q0
+ %0:fpr(<4 x f16>) = G_FPTRUNC %1(<4 x f32>)
+ $noreg = PATCHABLE_RET %0(<4 x f16>)
...
---
@@ -4417,9 +4417,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept SCVTFv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SCVTFv2f32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x i32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_SITOFP %1(<2 x i32>)
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -4443,9 +4443,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SCVTFv4f32_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_SITOFP %1(<4 x i32>)
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -4469,9 +4469,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SCVTFv2f64_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_SITOFP %1(<2 x i64>)
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
@@ -4573,9 +4573,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept UCVTFv2f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UCVTFv2f32_]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x i32>) = COPY $d0
+ %0:fpr(<2 x f32>) = G_UITOFP %1(<2 x i32>)
+ $noreg = PATCHABLE_RET %0(<2 x f32>)
...
---
@@ -4599,9 +4599,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UCVTFv4f32_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x f32>) = G_UITOFP %1(<4 x i32>)
+ $noreg = PATCHABLE_RET %0(<4 x f32>)
...
---
@@ -4625,9 +4625,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[COPY]], implicit $fpcr
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UCVTFv2f64_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x f64>) = G_UITOFP %1(<2 x i64>)
+ $noreg = PATCHABLE_RET %0(<2 x f64>)
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
index 94af12a91ae97..894cf33aa182a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
@@ -124,10 +124,11 @@ body: |
; CHECK-LABEL: name: strsrox
; CHECK: liveins: $x0, $x1, $s2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: %ptr:gpr64common = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s2
- ; CHECK-NEXT: STRSroX [[COPY2]], [[COPY]], [[COPY1]], 0, 0 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: STRSui [[COPY2]], %ptr, 0 :: (store (s32) into %ir.addr)
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = COPY $x1
%ptr:gpr(p0) = G_PTR_ADD %0, %1
@@ -147,10 +148,11 @@ body: |
; CHECK-LABEL: name: strhrox
; CHECK: liveins: $x0, $x1, $h0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: %ptr:gpr64common = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK-NEXT: STRHroX [[COPY2]], [[COPY]], [[COPY1]], 0, 0 :: (store (s16) into %ir.addr)
+ ; CHECK-NEXT: STRHui [[COPY2]], %ptr, 0 :: (store (s16) into %ir.addr)
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = COPY $x1
%ptr:gpr(p0) = G_PTR_ADD %0, %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
index 9a025aa35b874..e7592fe49c863 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
@@ -6,28 +6,29 @@
define void @test_const(ptr %dst) {
; CHECK-LABEL: name: test_const
; CHECK: bb.1.entry:
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (s8) into %ir.dst)
- ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 20
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (s8) into %ir.dst + 1)
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (s8) into %ir.dst + 2)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (s8) into %ir.dst + 3)
- ; CHECK: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 50
- ; CHECK: STRBBui [[MOVi32imm2]], [[COPY]], 4 :: (store (s8) into %ir.dst + 4)
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (s8) into %ir.dst + 5)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (s8) into %ir.dst + 6)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 7 :: (store (s8) into %ir.dst + 7)
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (s8) into %ir.dst)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (s8) into %ir.dst + 1)
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (s8) into %ir.dst + 2)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (s8) into %ir.dst + 3)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 4 :: (store (s8) into %ir.dst + 4)
- ; CHECK: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (s8) into %ir.dst + 5)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (s8) into %ir.dst + 6)
- ; CHECK: STRBBui [[MOVi32imm1]], [[COPY]], 7 :: (store (s8) into %ir.dst + 7)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (i8) into %ir.dst)
+ ; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 20
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (i8) into %ir.dst + 1)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (i8) into %ir.dst + 2)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (i8) into %ir.dst + 3)
+ ; CHECK-NEXT: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 50
+ ; CHECK-NEXT: STRBBui [[MOVi32imm2]], [[COPY]], 4 :: (store (i8) into %ir.dst + 4)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (i8) into %ir.dst + 5)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (i8) into %ir.dst + 6)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 7 :: (store (i8) into %ir.dst + 7)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (i8) into %ir.dst)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (i8) into %ir.dst + 1)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (i8) into %ir.dst + 2)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (i8) into %ir.dst + 3)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 4 :: (store (i8) into %ir.dst + 4)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (i8) into %ir.dst + 5)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (i8) into %ir.dst + 6)
+ ; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 7 :: (store (i8) into %ir.dst + 7)
+ ; CHECK-NEXT: RET_ReallyLR
entry:
%updated = insertvalue
; Check that we're visiting constants with shared parts
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
index dca947100b31e..06b9359d0078b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
@@ -8,9 +8,9 @@ define ptr @translate_element_size1(i64 %arg) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[C]], [[COPY]](s64)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[C]], [[COPY]](i64)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -25,8 +25,8 @@ define ptr @first_offset_const(ptr %addr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type, ptr %addr, i32 1
@@ -54,10 +54,10 @@ define ptr @first_offset_variable(ptr %addr, i64 %idx) {
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY1]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -72,11 +72,11 @@ define ptr @first_offset_ext(ptr %addr, i32 %idx) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[COPY1]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[SEXT]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -92,12 +92,12 @@ define ptr @const_then_var(ptr %addr, i64 %idx) {
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 272
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 272
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[MUL]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD1]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -112,12 +112,12 @@ define ptr @var_then_const(ptr %addr, i64 %idx) {
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY1]], [[C]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C1]](i64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type1, ptr %addr, i64 %idx, i32 2, i32 2
@@ -131,13 +131,13 @@ define <2 x ptr> @vec_gep_scalar_base(<2 x i64> %offs) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @arr
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[GV]](p0), [[GV]](p0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x s64>) = nsw G_MUL [[COPY]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p0>) = nusw inbounds G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x i64>) = nsw G_MUL [[COPY]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<2 x p0>) = nusw inbounds G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x i64>)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY [[PTR_ADD]](<2 x p0>)
; CHECK-NEXT: $q0 = COPY [[COPY1]](<2 x p0>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -151,18 +151,18 @@ define <4 x ptr> @vector_gep_v4i32(<4 x ptr> %b, <4 x i32> %off) {
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0, $q1, $q2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i64>) = COPY $q1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[COPY1]](<2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<2 x p0>), [[BITCAST1]](<2 x p0>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<4 x s64>) = G_SEXT [[COPY2]](<4 x s32>)
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<4 x p0>) = G_PTR_ADD [[CONCAT_VECTORS]], [[SEXT]](<4 x s64>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x i32>) = COPY $q2
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<4 x i64>) = G_SEXT [[COPY2]](<4 x i32>)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<4 x p0>) = G_PTR_ADD [[CONCAT_VECTORS]], [[SEXT]](<4 x i64>)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x p0>) = COPY [[PTR_ADD]](<4 x p0>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[COPY3]](<4 x p0>)
- ; CHECK-NEXT: $q0 = COPY [[UV]](<2 x s64>)
- ; CHECK-NEXT: $q1 = COPY [[UV1]](<2 x s64>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i64>), [[UV1:%[0-9]+]]:_(<2 x i64>) = G_UNMERGE_VALUES [[COPY3]](<4 x p0>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<2 x i64>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
entry:
%g = getelementptr i8, <4 x ptr> %b, <4 x i32> %off
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
index cf620cc52b906..c5748c83bb88a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
@@ -8,10 +8,10 @@ define i128 @func_i128(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.ptr)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i128) = G_LOAD [[COPY]](p0) :: (load (i128) from %ir.ptr)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](i128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%val = load i128, ptr %ptr
ret i128 %val
@@ -24,10 +24,10 @@ define <8 x float> @func_v8f32(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p0) :: (load (<8 x s32>) from %ir.ptr)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[LOAD]](<8 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
- ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x f32>) = G_LOAD [[COPY]](p0) :: (load (<8 x f32>) from %ir.ptr)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x f32>), [[UV1:%[0-9]+]]:_(<4 x f32>) = G_UNMERGE_VALUES [[LOAD]](<8 x f32>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x f32>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x f32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%val = load <8 x float>, ptr %ptr
ret <8 x float> %val
@@ -41,14 +41,14 @@ define <6 x float> @func_v6f32(ptr %ptr) {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<6 x s32>) = G_LOAD [[COPY]](p0) :: (load (<6 x s32>) from %ir.ptr, align 32)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<6 x s32>)
- ; CHECK-NEXT: $s0 = COPY [[UV]](s32)
- ; CHECK-NEXT: $s1 = COPY [[UV1]](s32)
- ; CHECK-NEXT: $s2 = COPY [[UV2]](s32)
- ; CHECK-NEXT: $s3 = COPY [[UV3]](s32)
- ; CHECK-NEXT: $s4 = COPY [[UV4]](s32)
- ; CHECK-NEXT: $s5 = COPY [[UV5]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<6 x f32>) = G_LOAD [[COPY]](p0) :: (load (<6 x f32>) from %ir.ptr, align 32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[LOAD]](<6 x f32>)
+ ; CHECK-NEXT: $s0 = COPY [[UV]](f32)
+ ; CHECK-NEXT: $s1 = COPY [[UV1]](f32)
+ ; CHECK-NEXT: $s2 = COPY [[UV2]](f32)
+ ; CHECK-NEXT: $s3 = COPY [[UV3]](f32)
+ ; CHECK-NEXT: $s4 = COPY [[UV4]](f32)
+ ; CHECK-NEXT: $s5 = COPY [[UV5]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0, implicit $s1, implicit $s2, implicit $s3, implicit $s4, implicit $s5
%val = load <6 x float>, ptr %ptr
ret <6 x float> %val
@@ -59,13 +59,14 @@ define i128 @ABIi128(i128 %arg1) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(s128) = G_FPTOUI [[MV]](s128)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[FPTOUI]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f128) = G_BITCAST [[MV]](i128)
+ ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(i128) = G_FPTOUI [[BITCAST]](f128)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[FPTOUI]](i128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%farg1 = bitcast i128 %arg1 to fp128
%res = fptoui fp128 %farg1 to i128
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
index 06616510119e0..255b2c6505e79 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
@@ -11,19 +11,19 @@ define void @formal_argument_mix_sve(
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY1]](<vscale x 4 x f32>), [[COPY2]](<vscale x 4 x f32>)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>), [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
<vscale x 8 x i16> %0, <vscale x 8 x float> %1, <vscale x 16 x i8> %2, <vscale x 8 x ptr> %3
@@ -38,8 +38,8 @@ define void @formal_argument_mix_sve_double(
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $d1, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $d1
; CHECK-NEXT: RET_ReallyLR
<vscale x 8 x i16> %0, double %1
) {
@@ -51,10 +51,10 @@ define void @formal_argument_mix_sve_int_double(
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $d0, $w0, $z1, $z2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
; CHECK-NEXT: RET_ReallyLR
double %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i16> %3
) {
@@ -70,14 +70,14 @@ define void @formal_argument_nxv2i64_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3,
<vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7
@@ -90,14 +90,14 @@ define void @formal_argument_nxv2f64_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3,
<vscale x 2 x double> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %6, <vscale x 2 x double> %7
@@ -131,14 +131,14 @@ define void @formal_argument_nxv4i32_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3,
<vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7
@@ -151,14 +151,14 @@ define void @formal_argument_nxv4f32_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3,
<vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7
@@ -171,18 +171,18 @@ define void @formal_argument_nxv4i64_4(<vscale x 4 x i64> %0, <vscale x 4 x i64>
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 4 x i64>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 2 x i64>), [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 4 x i64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x i64>), [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 4 x i64>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 2 x i64>), [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -192,25 +192,25 @@ define void @formal_argument_nxv4p0_4(<vscale x 4 x ptr> %0, <vscale x 4 x ptr>
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[BITCAST4]](<vscale x 2 x p0>), [[BITCAST5]](<vscale x 2 x p0>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[BITCAST6]](<vscale x 2 x p0>), [[BITCAST7]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
@@ -222,14 +222,14 @@ define void @formal_argument_nxv8i16_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3,
<vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7
@@ -242,18 +242,18 @@ define void @formal_argument_nxv8i32_4(<vscale x 8 x i32> %0, <vscale x 8 x i32>
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x i32>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 4 x i32>), [[COPY3]](<vscale x 4 x i32>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z5
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 8 x i32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x i32>), [[COPY5]](<vscale x 4 x i32>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 8 x i32>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 4 x i32>), [[COPY7]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -263,18 +263,18 @@ define void @formal_argument_nxv8f32_4(<vscale x 8 x float> %0, <vscale x 8 x fl
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 4 x f32>), [[COPY3]](<vscale x 4 x f32>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z5
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x f32>), [[COPY5]](<vscale x 4 x f32>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 4 x f32>), [[COPY7]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -284,16 +284,16 @@ define void @formal_argument_nxv8i64_2(<vscale x 8 x i64> %0, <vscale x 8 x i64>
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>), [[COPY2]](<vscale x 2 x i64>), [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x i64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x i64>), [[COPY5]](<vscale x 2 x i64>), [[COPY6]](<vscale x 2 x i64>), [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -303,16 +303,16 @@ define void @formal_argument_nxv8f64_2(<vscale x 8 x double> %0, <vscale x 8 x d
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x f64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x f64>), [[COPY1]](<vscale x 2 x f64>), [[COPY2]](<vscale x 2 x f64>), [[COPY3]](<vscale x 2 x f64>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x f64>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 2 x f64>), [[COPY5]](<vscale x 2 x f64>), [[COPY6]](<vscale x 2 x f64>), [[COPY7]](<vscale x 2 x f64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -322,23 +322,23 @@ define void @formal_argument_nxv8p0_2(<vscale x 8 x ptr> %0, <vscale x 8 x ptr>
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>), [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[BITCAST4]](<vscale x 2 x p0>), [[BITCAST5]](<vscale x 2 x p0>), [[BITCAST6]](<vscale x 2 x p0>), [[BITCAST7]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
@@ -351,14 +351,14 @@ define void @formal_argument_nxv16i8_8(
; CHECK: bb.1 (%ir-block.8):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z7
; CHECK-NEXT: RET_ReallyLR
<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3,
<vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7
@@ -371,18 +371,18 @@ define void @formal_argument_nxv16i16_4(<vscale x 16 x i16> %0, <vscale x 16 x i
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x s16>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 8 x s16>), [[COPY3]](<vscale x 8 x s16>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 16 x s16>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 8 x s16>), [[COPY5]](<vscale x 8 x s16>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 16 x s16>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 8 x s16>), [[COPY7]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x i16>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 8 x i16>), [[COPY3]](<vscale x 8 x i16>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z5
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 16 x i16>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 8 x i16>), [[COPY5]](<vscale x 8 x i16>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 16 x i16>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 8 x i16>), [[COPY7]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -392,16 +392,16 @@ define void @formal_argument_nxv16i32_2(<vscale x 16 x i32> %0, <vscale x 16 x i
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>), [[COPY2]](<vscale x 4 x i32>), [[COPY3]](<vscale x 4 x i32>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x i32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x i32>), [[COPY5]](<vscale x 4 x i32>), [[COPY6]](<vscale x 4 x i32>), [[COPY7]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -411,16 +411,16 @@ define void @formal_argument_nxv16f32_2(<vscale x 16 x float> %0, <vscale x 16 x
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>), [[COPY2]](<vscale x 4 x f32>), [[COPY3]](<vscale x 4 x f32>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 16 x f32>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 4 x f32>), [[COPY5]](<vscale x 4 x f32>), [[COPY6]](<vscale x 4 x f32>), [[COPY7]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -430,15 +430,15 @@ define void @formal_argument_nxv16i64_1(<vscale x 16 x i64> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>), [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>), [[COPY2]](<vscale x 2 x i64>), [[COPY3]](<vscale x 2 x i64>), [[COPY4]](<vscale x 2 x i64>), [[COPY5]](<vscale x 2 x i64>), [[COPY6]](<vscale x 2 x i64>), [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -448,22 +448,22 @@ define void @formal_argument_nxv16p0_1(<vscale x 16 x ptr> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>), [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>), [[BITCAST4]](<vscale x 2 x p0>), [[BITCAST5]](<vscale x 2 x p0>), [[BITCAST6]](<vscale x 2 x p0>), [[BITCAST7]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
@@ -476,18 +476,18 @@ define void @formal_argument_nxv32i8_4(<vscale x 32 x i8> %0, <vscale x 32 x i8>
; CHECK: bb.1 (%ir-block.4):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x s8>), [[COPY1]](<vscale x 16 x s8>)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 16 x s8>), [[COPY3]](<vscale x 16 x s8>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z5
- ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 32 x s8>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 16 x s8>), [[COPY5]](<vscale x 16 x s8>)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 32 x s8>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 16 x s8>), [[COPY7]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x i8>), [[COPY1]](<vscale x 16 x i8>)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 32 x i8>) = G_CONCAT_VECTORS [[COPY2]](<vscale x 16 x i8>), [[COPY3]](<vscale x 16 x i8>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z5
+ ; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<vscale x 32 x i8>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 16 x i8>), [[COPY5]](<vscale x 16 x i8>)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<vscale x 32 x i8>) = G_CONCAT_VECTORS [[COPY6]](<vscale x 16 x i8>), [[COPY7]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -497,16 +497,16 @@ define void @formal_argument_nxv32i16_2(<vscale x 32 x i16> %0, <vscale x 32 x i
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>), [[COPY2]](<vscale x 8 x s16>), [[COPY3]](<vscale x 8 x s16>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 32 x s16>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 8 x s16>), [[COPY5]](<vscale x 8 x s16>), [[COPY6]](<vscale x 8 x s16>), [[COPY7]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>), [[COPY2]](<vscale x 8 x i16>), [[COPY3]](<vscale x 8 x i16>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 32 x i16>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 8 x i16>), [[COPY5]](<vscale x 8 x i16>), [[COPY6]](<vscale x 8 x i16>), [[COPY7]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -516,15 +516,15 @@ define void @formal_argument_nxv32i32_1(<vscale x 32 x i32> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>), [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>), [[COPY2]](<vscale x 4 x i32>), [[COPY3]](<vscale x 4 x i32>), [[COPY4]](<vscale x 4 x i32>), [[COPY5]](<vscale x 4 x i32>), [[COPY6]](<vscale x 4 x i32>), [[COPY7]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -534,15 +534,15 @@ define void @formal_argument_nxv32f32_1(<vscale x 32 x float> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>), [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>), [[COPY2]](<vscale x 4 x f32>), [[COPY3]](<vscale x 4 x f32>), [[COPY4]](<vscale x 4 x f32>), [[COPY5]](<vscale x 4 x f32>), [[COPY6]](<vscale x 4 x f32>), [[COPY7]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -554,16 +554,16 @@ define void @formal_argument_nxv64i8_2(<vscale x 64 x i8> %0, <vscale x 64 x i8>
; CHECK: bb.1 (%ir-block.2):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x s8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x s8>), [[COPY1]](<vscale x 16 x s8>), [[COPY2]](<vscale x 16 x s8>), [[COPY3]](<vscale x 16 x s8>)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 16 x s8>), [[COPY5]](<vscale x 16 x s8>), [[COPY6]](<vscale x 16 x s8>), [[COPY7]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x i8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x i8>), [[COPY1]](<vscale x 16 x i8>), [[COPY2]](<vscale x 16 x i8>), [[COPY3]](<vscale x 16 x i8>)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<vscale x 64 x i8>) = G_CONCAT_VECTORS [[COPY4]](<vscale x 16 x i8>), [[COPY5]](<vscale x 16 x i8>), [[COPY6]](<vscale x 16 x i8>), [[COPY7]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -573,15 +573,15 @@ define void @formal_argument_nxv64i16_1(<vscale x 64 x i16> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>), [[COPY2]](<vscale x 8 x s16>), [[COPY3]](<vscale x 8 x s16>), [[COPY4]](<vscale x 8 x s16>), [[COPY5]](<vscale x 8 x s16>), [[COPY6]](<vscale x 8 x s16>), [[COPY7]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>), [[COPY2]](<vscale x 8 x i16>), [[COPY3]](<vscale x 8 x i16>), [[COPY4]](<vscale x 8 x i16>), [[COPY5]](<vscale x 8 x i16>), [[COPY6]](<vscale x 8 x i16>), [[COPY7]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
index e6476ae726540..4e96cc0d9b08f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
@@ -9,7 +9,7 @@ define void @formal_argument_nxv16i8(<vscale x 16 x i8> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -19,7 +19,7 @@ define void @formal_argument_nxv8i16(<vscale x 8 x i16> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -29,7 +29,7 @@ define void @formal_argument_nxv4i32(<vscale x 4 x i32> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -39,7 +39,7 @@ define void @formal_argument_nxv2i64(<vscale x 2 x i64> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -49,7 +49,7 @@ define void @formal_argument_nxv4f32(<vscale x 4 x float> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -59,7 +59,7 @@ define void @formal_argument_nxv2f64(<vscale x 2 x double> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -81,9 +81,9 @@ define void @formal_argument_nxv32i8(<vscale x 32 x i8> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x s8>), [[COPY1]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x i8>), [[COPY1]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -93,9 +93,9 @@ define void @formal_argument_nxv16i16(<vscale x 16 x i16> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -105,9 +105,9 @@ define void @formal_argument_nxv8i32(<vscale x 8 x i32> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -117,9 +117,9 @@ define void @formal_argument_nxv4i64(<vscale x 4 x i64> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -129,9 +129,9 @@ define void @formal_argument_nxv8f32(<vscale x 8 x float> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -141,9 +141,9 @@ define void @formal_argument_nxv4f64(<vscale x 4 x double> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z1
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x f64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x f64>), [[COPY1]](<vscale x 2 x f64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -153,10 +153,10 @@ define void @formal_argument_nxv4p0(<vscale x 4 x ptr> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 4 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
@@ -169,11 +169,11 @@ define void @formal_argument_nxv64i8(<vscale x 64 x i8> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x s8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x s8>), [[COPY1]](<vscale x 16 x s8>), [[COPY2]](<vscale x 16 x s8>), [[COPY3]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x i8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x i8>), [[COPY1]](<vscale x 16 x i8>), [[COPY2]](<vscale x 16 x i8>), [[COPY3]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -183,11 +183,11 @@ define void @formal_argument_nxv32i16(<vscale x 32 x i16> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>), [[COPY2]](<vscale x 8 x s16>), [[COPY3]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>), [[COPY2]](<vscale x 8 x i16>), [[COPY3]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -197,11 +197,11 @@ define void @formal_argument_nxv16i32(<vscale x 16 x i32> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>), [[COPY2]](<vscale x 4 x i32>), [[COPY3]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -211,11 +211,11 @@ define void @formal_argument_nxv8i64(<vscale x 8 x i64> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>), [[COPY2]](<vscale x 2 x i64>), [[COPY3]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -225,11 +225,11 @@ define void @formal_argument_nxv16f32(<vscale x 16 x float> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>), [[COPY2]](<vscale x 4 x f32>), [[COPY3]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -239,11 +239,11 @@ define void @formal_argument_nxv8f64(<vscale x 8 x double> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z3
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x f64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x f64>), [[COPY1]](<vscale x 2 x f64>), [[COPY2]](<vscale x 2 x f64>), [[COPY3]](<vscale x 2 x f64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -253,14 +253,14 @@ define void @formal_argument_nxv8p0(<vscale x 8 x ptr> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 8 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>), [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
@@ -273,15 +273,15 @@ define void @formal_argument_nxv128i8(<vscale x 128 x i8> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 128 x s8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x s8>), [[COPY1]](<vscale x 16 x s8>), [[COPY2]](<vscale x 16 x s8>), [[COPY3]](<vscale x 16 x s8>), [[COPY4]](<vscale x 16 x s8>), [[COPY5]](<vscale x 16 x s8>), [[COPY6]](<vscale x 16 x s8>), [[COPY7]](<vscale x 16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 16 x i8>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 128 x i8>) = G_CONCAT_VECTORS [[COPY]](<vscale x 16 x i8>), [[COPY1]](<vscale x 16 x i8>), [[COPY2]](<vscale x 16 x i8>), [[COPY3]](<vscale x 16 x i8>), [[COPY4]](<vscale x 16 x i8>), [[COPY5]](<vscale x 16 x i8>), [[COPY6]](<vscale x 16 x i8>), [[COPY7]](<vscale x 16 x i8>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -291,15 +291,15 @@ define void @formal_argument_nxv64i16(<vscale x 64 x i16> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x s16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s16>), [[COPY1]](<vscale x 8 x s16>), [[COPY2]](<vscale x 8 x s16>), [[COPY3]](<vscale x 8 x s16>), [[COPY4]](<vscale x 8 x s16>), [[COPY5]](<vscale x 8 x s16>), [[COPY6]](<vscale x 8 x s16>), [[COPY7]](<vscale x 8 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 8 x i16>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 64 x i16>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x i16>), [[COPY1]](<vscale x 8 x i16>), [[COPY2]](<vscale x 8 x i16>), [[COPY3]](<vscale x 8 x i16>), [[COPY4]](<vscale x 8 x i16>), [[COPY5]](<vscale x 8 x i16>), [[COPY6]](<vscale x 8 x i16>), [[COPY7]](<vscale x 8 x i16>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -309,15 +309,15 @@ define void @formal_argument_nxv32i32(<vscale x 32 x i32> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>), [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x i32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x i32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x i32>), [[COPY1]](<vscale x 4 x i32>), [[COPY2]](<vscale x 4 x i32>), [[COPY3]](<vscale x 4 x i32>), [[COPY4]](<vscale x 4 x i32>), [[COPY5]](<vscale x 4 x i32>), [[COPY6]](<vscale x 4 x i32>), [[COPY7]](<vscale x 4 x i32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -327,15 +327,15 @@ define void @formal_argument_nxv16i64(<vscale x 16 x i64> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>), [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x i64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x i64>), [[COPY1]](<vscale x 2 x i64>), [[COPY2]](<vscale x 2 x i64>), [[COPY3]](<vscale x 2 x i64>), [[COPY4]](<vscale x 2 x i64>), [[COPY5]](<vscale x 2 x i64>), [[COPY6]](<vscale x 2 x i64>), [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -345,15 +345,15 @@ define void @formal_argument_nxv32f32(<vscale x 32 x float> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x s32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x s32>), [[COPY1]](<vscale x 4 x s32>), [[COPY2]](<vscale x 4 x s32>), [[COPY3]](<vscale x 4 x s32>), [[COPY4]](<vscale x 4 x s32>), [[COPY5]](<vscale x 4 x s32>), [[COPY6]](<vscale x 4 x s32>), [[COPY7]](<vscale x 4 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 4 x f32>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 32 x f32>) = G_CONCAT_VECTORS [[COPY]](<vscale x 4 x f32>), [[COPY1]](<vscale x 4 x f32>), [[COPY2]](<vscale x 4 x f32>), [[COPY3]](<vscale x 4 x f32>), [[COPY4]](<vscale x 4 x f32>), [[COPY5]](<vscale x 4 x f32>), [[COPY6]](<vscale x 4 x f32>), [[COPY7]](<vscale x 4 x f32>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -363,15 +363,15 @@ define void @formal_argument_nxv16f64(<vscale x 16 x double> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x s64>), [[COPY1]](<vscale x 2 x s64>), [[COPY2]](<vscale x 2 x s64>), [[COPY3]](<vscale x 2 x s64>), [[COPY4]](<vscale x 2 x s64>), [[COPY5]](<vscale x 2 x s64>), [[COPY6]](<vscale x 2 x s64>), [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x f64>) = COPY $z7
+ ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x f64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 2 x f64>), [[COPY1]](<vscale x 2 x f64>), [[COPY2]](<vscale x 2 x f64>), [[COPY3]](<vscale x 2 x f64>), [[COPY4]](<vscale x 2 x f64>), [[COPY5]](<vscale x 2 x f64>), [[COPY6]](<vscale x 2 x f64>), [[COPY7]](<vscale x 2 x f64>)
; CHECK-NEXT: RET_ReallyLR
ret void
}
@@ -381,22 +381,22 @@ define void @formal_argument_nxv16p0(<vscale x 16 x ptr> %0) {
; CHECK: bb.1 (%ir-block.1):
; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $z4, $z5, $z6, $z7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z7
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x s64>)
- ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(<vscale x 2 x i64>) = COPY $z7
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY1]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY2]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY3]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY4]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY5]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY6]](<vscale x 2 x i64>)
+ ; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<vscale x 2 x p0>) = G_BITCAST [[COPY7]](<vscale x 2 x i64>)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x p0>) = G_CONCAT_VECTORS [[BITCAST]](<vscale x 2 x p0>), [[BITCAST1]](<vscale x 2 x p0>), [[BITCAST2]](<vscale x 2 x p0>), [[BITCAST3]](<vscale x 2 x p0>), [[BITCAST4]](<vscale x 2 x p0>), [[BITCAST5]](<vscale x 2 x p0>), [[BITCAST6]](<vscale x 2 x p0>), [[BITCAST7]](<vscale x 2 x p0>)
; CHECK-NEXT: RET_ReallyLR
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll b/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
index 40bb8a89ca5e4..9274680c93824 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
@@ -6,10 +6,10 @@ define i12 @v1i12(<1 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i12) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <1 x i12> %v, i32 0
ret i12 %r
@@ -20,12 +20,12 @@ define i12 @v2i12(<2 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s12>) = G_TRUNC [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<2 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i12>) = G_TRUNC [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<2 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <2 x i12> %v, i32 1
ret i12 %r
@@ -36,15 +36,15 @@ define i12 @v3i12(<3 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x s12>) = G_TRUNC [[BUILD_VECTOR]](<3 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<3 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x i12>) = G_TRUNC [[BUILD_VECTOR]](<3 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<3 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <3 x i12> %v, i32 1
ret i12 %r
@@ -55,12 +55,12 @@ define i12 @v4i12(<4 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s12>) = G_TRUNC [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<4 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i16>) = COPY $d0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x i12>) = G_TRUNC [[COPY]](<4 x i16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<4 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <4 x i12> %v, i32 1
ret i12 %r
@@ -71,17 +71,17 @@ define i12 @v5i12(<5 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2, $w3, $w4
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<5 x s12>) = G_TRUNC [[BUILD_VECTOR]](<5 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<5 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<5 x i12>) = G_TRUNC [[BUILD_VECTOR]](<5 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<5 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <5 x i12> %v, i32 1
ret i12 %r
@@ -92,18 +92,18 @@ define i12 @v6i12(<6 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2, $w3, $w4, $w5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w5
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<6 x s12>) = G_TRUNC [[BUILD_VECTOR]](<6 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<6 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $w5
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<6 x i12>) = G_TRUNC [[BUILD_VECTOR]](<6 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<6 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <6 x i12> %v, i32 1
ret i12 %r
@@ -114,19 +114,19 @@ define i12 @v7i12(<7 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2, $w3, $w4, $w5, $w6
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $w6
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<7 x s12>) = G_TRUNC [[BUILD_VECTOR]](<7 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<7 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $w5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $w6
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<7 x i12>) = G_TRUNC [[BUILD_VECTOR]](<7 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<7 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <7 x i12> %v, i32 1
ret i12 %r
@@ -137,12 +137,12 @@ define i12 @v8i12(<8 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s12>) = G_TRUNC [[COPY]](<8 x s16>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<8 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i16>) = COPY $q0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x i12>) = G_TRUNC [[COPY]](<8 x i16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<8 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <8 x i12> %v, i32 1
ret i12 %r
@@ -153,28 +153,28 @@ define i12 @v12i12(<12 x i12> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $w0, $w1, $w2, $w3, $w4, $w5, $w6, $w7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $w6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $w7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $w2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $w3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $w4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $w5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $w6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $w7
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s32) from %fixed-stack.3, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i32) from %fixed-stack.3, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s32) from %fixed-stack.2, align 8)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (i32) from %fixed-stack.2, align 8)
; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (s32) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (i32) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load (s32) from %fixed-stack.0, align 8)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<12 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<12 x s12>) = G_TRUNC [[BUILD_VECTOR]](<12 x s32>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<12 x s12>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s12)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load (i32) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<12 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32), [[LOAD]](i32), [[LOAD1]](i32), [[LOAD2]](i32), [[LOAD3]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<12 x i12>) = G_TRUNC [[BUILD_VECTOR]](<12 x i32>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i12) = G_EXTRACT_VECTOR_ELT [[TRUNC]](<12 x i12>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[EVEC]](i12)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = extractelement <12 x i12> %v, i32 1
ret i12 %r
@@ -186,14 +186,14 @@ define i100 @v1i100(<1 x i100> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%r = extractelement <1 x i100> %v, i32 0
ret i100 %r
@@ -204,21 +204,21 @@ define i100 @v2i100(<2 x i100> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s100>) = G_BUILD_VECTOR [[TRUNC]](s100), [[TRUNC1]](s100)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s100>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x i100>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%r = extractelement <2 x i100> %v, i32 1
ret i100 %r
@@ -229,25 +229,25 @@ define i100 @v3i100(<3 x i100> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](s64), [[COPY5]](s64)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s100) = G_TRUNC [[MV2]](s128)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s100>) = G_BUILD_VECTOR [[TRUNC]](s100), [[TRUNC1]](s100), [[TRUNC2]](s100)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s100>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](s128)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100), [[TRUNC2]](i100)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x i100>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%r = extractelement <3 x i100> %v, i32 1
ret i100 %r
@@ -258,29 +258,29 @@ define i100 @v4i100(<4 x i100> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](s64), [[COPY5]](s64)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s100) = G_TRUNC [[MV2]](s128)
- ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](s64), [[COPY7]](s64)
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s100) = G_TRUNC [[MV3]](s128)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s100>) = G_BUILD_VECTOR [[TRUNC]](s100), [[TRUNC1]](s100), [[TRUNC2]](s100), [[TRUNC3]](s100)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<4 x s100>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](s128)
+ ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](i64), [[COPY7]](i64)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i100) = G_TRUNC [[MV3]](s128)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100), [[TRUNC2]](i100), [[TRUNC3]](i100)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<4 x i100>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%r = extractelement <4 x i100> %v, i32 1
ret i100 %r
@@ -291,53 +291,53 @@ define i100 @v8i100(<8 x i100> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.7, align 16)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (i64) from %fixed-stack.7, align 16)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s64) from %fixed-stack.6)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (i64) from %fixed-stack.6)
; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (s64) from %fixed-stack.5, align 16)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load (i64) from %fixed-stack.5, align 16)
; CHECK-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load (s64) from %fixed-stack.4)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load (i64) from %fixed-stack.4)
; CHECK-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load (s64) from %fixed-stack.3, align 16)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load (i64) from %fixed-stack.3, align 16)
; CHECK-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load (s64) from %fixed-stack.2)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load (i64) from %fixed-stack.2)
; CHECK-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load (s64) from %fixed-stack.0)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](s64), [[COPY5]](s64)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s100) = G_TRUNC [[MV2]](s128)
- ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](s64), [[COPY7]](s64)
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s100) = G_TRUNC [[MV3]](s128)
- ; CHECK-NEXT: [[MV4:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD]](s64), [[LOAD1]](s64)
- ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s100) = G_TRUNC [[MV4]](s128)
- ; CHECK-NEXT: [[MV5:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD2]](s64), [[LOAD3]](s64)
- ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s100) = G_TRUNC [[MV5]](s128)
- ; CHECK-NEXT: [[MV6:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD4]](s64), [[LOAD5]](s64)
- ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s100) = G_TRUNC [[MV6]](s128)
- ; CHECK-NEXT: [[MV7:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD6]](s64), [[LOAD7]](s64)
- ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s100) = G_TRUNC [[MV7]](s128)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s100>) = G_BUILD_VECTOR [[TRUNC]](s100), [[TRUNC1]](s100), [[TRUNC2]](s100), [[TRUNC3]](s100), [[TRUNC4]](s100), [[TRUNC5]](s100), [[TRUNC6]](s100), [[TRUNC7]](s100)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<8 x s100>), [[C]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](s100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
- ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
- ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+ ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load (i64) from %fixed-stack.0)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](s128)
+ ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](i64), [[COPY7]](i64)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i100) = G_TRUNC [[MV3]](s128)
+ ; CHECK-NEXT: [[MV4:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD]](i64), [[LOAD1]](i64)
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i100) = G_TRUNC [[MV4]](s128)
+ ; CHECK-NEXT: [[MV5:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD2]](i64), [[LOAD3]](i64)
+ ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(i100) = G_TRUNC [[MV5]](s128)
+ ; CHECK-NEXT: [[MV6:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD4]](i64), [[LOAD5]](i64)
+ ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(i100) = G_TRUNC [[MV6]](s128)
+ ; CHECK-NEXT: [[MV7:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD6]](i64), [[LOAD7]](i64)
+ ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(i100) = G_TRUNC [[MV7]](s128)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100), [[TRUNC2]](i100), [[TRUNC3]](i100), [[TRUNC4]](i100), [[TRUNC5]](i100), [[TRUNC6]](i100), [[TRUNC7]](i100)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<8 x i100>), [[C]](i64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%r = extractelement <8 x i100> %v, i32 1
ret i100 %r
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll b/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll
index c79093e37101d..50517866173f5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/vec-s16-param.ll
@@ -6,12 +6,12 @@ define <2 x half> @f16_vec_param(<2 x half> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[UV]](<2 x s16>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV2]](s16), [[UV3]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f16), [[UV3:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[UV]](<2 x f16>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f16>) = G_BUILD_VECTOR [[UV2]](f16), [[UV3]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<4 x f16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <2 x half> %v
}
@@ -21,10 +21,10 @@ define <2 x i16> @i16_vec_param(<2 x i16> %v) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[TRUNC]](<2 x s16>)
- ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x i16>) = G_TRUNC [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x i32>) = G_ANYEXT [[TRUNC]](<2 x i16>)
+ ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
ret <2 x i16> %v
}
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll b/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
index bccb70ccd5c03..22f89a78c6eeb 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
@@ -10,9 +10,10 @@ define ptr @memset_tagged_0_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_0_zeroval:
; GISel-O0: // %bb.0: // %entry
; GISel-O0-NEXT: mov x8, xzr
-; GISel-O0-NEXT: setgp [x0]!, x8!, x8
-; GISel-O0-NEXT: setgm [x0]!, x8!, x8
-; GISel-O0-NEXT: setge [x0]!, x8!, x8
+; GISel-O0-NEXT: mov x9, xzr
+; GISel-O0-NEXT: setgp [x0]!, x8!, x9
+; GISel-O0-NEXT: setgm [x0]!, x8!, x9
+; GISel-O0-NEXT: setge [x0]!, x8!, x9
; GISel-O0-NEXT: ret
;
; GISel-LABEL: memset_tagged_0_zeroval:
@@ -38,7 +39,7 @@ entry:
define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_1_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #1
+; GISel-O0-NEXT: mov w8, #1 // =0x1
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
@@ -48,7 +49,7 @@ define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
;
; GISel-LABEL: memset_tagged_1_zeroval:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #1
+; GISel-NEXT: mov w8, #1 // =0x1
; GISel-NEXT: setgp [x0]!, x8!, xzr
; GISel-NEXT: setgm [x0]!, x8!, xzr
; GISel-NEXT: setge [x0]!, x8!, xzr
@@ -56,7 +57,7 @@ define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
;
; SDAG-LABEL: memset_tagged_1_zeroval:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #1
+; SDAG-NEXT: mov w8, #1 // =0x1
; SDAG-NEXT: setgp [x0]!, x8!, xzr
; SDAG-NEXT: setgm [x0]!, x8!, xzr
; SDAG-NEXT: setge [x0]!, x8!, xzr
@@ -69,7 +70,7 @@ entry:
define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_10_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10
+; GISel-O0-NEXT: mov w8, #10 // =0xa
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
@@ -79,7 +80,7 @@ define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
;
; GISel-LABEL: memset_tagged_10_zeroval:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10
+; GISel-NEXT: mov w8, #10 // =0xa
; GISel-NEXT: setgp [x0]!, x8!, xzr
; GISel-NEXT: setgm [x0]!, x8!, xzr
; GISel-NEXT: setge [x0]!, x8!, xzr
@@ -87,7 +88,7 @@ define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
;
; SDAG-LABEL: memset_tagged_10_zeroval:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10
+; SDAG-NEXT: mov w8, #10 // =0xa
; SDAG-NEXT: setgp [x0]!, x8!, xzr
; SDAG-NEXT: setgm [x0]!, x8!, xzr
; SDAG-NEXT: setge [x0]!, x8!, xzr
@@ -100,7 +101,7 @@ entry:
define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_10000_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10000
+; GISel-O0-NEXT: mov w8, #10000 // =0x2710
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
@@ -110,7 +111,7 @@ define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
;
; GISel-LABEL: memset_tagged_10000_zeroval:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10000
+; GISel-NEXT: mov w8, #10000 // =0x2710
; GISel-NEXT: setgp [x0]!, x8!, xzr
; GISel-NEXT: setgm [x0]!, x8!, xzr
; GISel-NEXT: setge [x0]!, x8!, xzr
@@ -118,7 +119,7 @@ define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
;
; SDAG-LABEL: memset_tagged_10000_zeroval:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10000
+; SDAG-NEXT: mov w8, #10000 // =0x2710
; SDAG-NEXT: setgp [x0]!, x8!, xzr
; SDAG-NEXT: setgm [x0]!, x8!, xzr
; SDAG-NEXT: setge [x0]!, x8!, xzr
@@ -192,7 +193,7 @@ entry:
define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_1:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #1
+; GISel-O0-NEXT: mov w8, #1 // =0x1
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
@@ -203,7 +204,7 @@ define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
;
; GISel-LABEL: memset_tagged_1:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #1
+; GISel-NEXT: mov w8, #1 // =0x1
; GISel-NEXT: // kill: def $w2 killed $w2 def $x2
; GISel-NEXT: setgp [x0]!, x8!, x2
; GISel-NEXT: setgm [x0]!, x8!, x2
@@ -212,7 +213,7 @@ define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
;
; SDAG-LABEL: memset_tagged_1:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #1
+; SDAG-NEXT: mov w8, #1 // =0x1
; SDAG-NEXT: // kill: def $w2 killed $w2 def $x2
; SDAG-NEXT: setgp [x0]!, x8!, x2
; SDAG-NEXT: setgm [x0]!, x8!, x2
@@ -227,7 +228,7 @@ entry:
define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_10:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10
+; GISel-O0-NEXT: mov w8, #10 // =0xa
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
@@ -238,7 +239,7 @@ define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
;
; GISel-LABEL: memset_tagged_10:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10
+; GISel-NEXT: mov w8, #10 // =0xa
; GISel-NEXT: // kill: def $w2 killed $w2 def $x2
; GISel-NEXT: setgp [x0]!, x8!, x2
; GISel-NEXT: setgm [x0]!, x8!, x2
@@ -247,7 +248,7 @@ define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
;
; SDAG-LABEL: memset_tagged_10:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10
+; SDAG-NEXT: mov w8, #10 // =0xa
; SDAG-NEXT: // kill: def $w2 killed $w2 def $x2
; SDAG-NEXT: setgp [x0]!, x8!, x2
; SDAG-NEXT: setgm [x0]!, x8!, x2
@@ -262,7 +263,7 @@ entry:
define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_10000:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10000
+; GISel-O0-NEXT: mov w8, #10000 // =0x2710
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
@@ -273,7 +274,7 @@ define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
;
; GISel-LABEL: memset_tagged_10000:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10000
+; GISel-NEXT: mov w8, #10000 // =0x2710
; GISel-NEXT: // kill: def $w2 killed $w2 def $x2
; GISel-NEXT: setgp [x0]!, x8!, x2
; GISel-NEXT: setgm [x0]!, x8!, x2
@@ -282,7 +283,7 @@ define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
;
; SDAG-LABEL: memset_tagged_10000:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10000
+; SDAG-NEXT: mov w8, #10000 // =0x2710
; SDAG-NEXT: // kill: def $w2 killed $w2 def $x2
; SDAG-NEXT: setgp [x0]!, x8!, x2
; SDAG-NEXT: setgm [x0]!, x8!, x2
diff --git a/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll b/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll
index 07c4dbcf41096..16a53fa089857 100644
--- a/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll
@@ -208,7 +208,8 @@ define <4 x i32> @sqxtn_ins(<4 x i32> noundef %a, i64 %c) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d1, x0
; CHECK-NEXT: sqxtn s1, d1
-; CHECK-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret
entry:
%vqmovnd_s64.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64 %c)
@@ -221,7 +222,8 @@ define <4 x i32> @sqxtun_insext(<4 x i32> noundef %a, <2 x i64> %e) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: sqxtun s1, d1
-; CHECK-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret
entry:
%c = extractelement <2 x i64> %e, i64 1
@@ -235,7 +237,8 @@ define <4 x i32> @saddluse(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 %c, f
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: saddlv d1, v1.4s
; CHECK-NEXT: sqxtn s1, d1
-; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: ret
entry:
%vaddlvq_s32.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> %b)
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
index 2925b18dd4a1b..df6cbaf47b846 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFPRCVT
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sme,+neon,+fullfp16,+fprcvt -force-streaming | FileCheck %s --check-prefixes=CHECK-SME
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sve,+neon,+fullfp16,+fprcvt -force-streaming-compatible | FileCheck %s --check-prefixes=CHECK-SVE
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFPRCVT
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT,CHECK-SD-FPRCVT
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sme,+neon,+fullfp16,+fprcvt -force-streaming | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT,CHECK-SME
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sve,+neon,+fullfp16,+fprcvt -force-streaming-compatible | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT,CHECK-SVE
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT,CHECK-GI-FPRCVT
;
; FPTOI
@@ -114,11 +114,6 @@ define double @test_fptosi_f32_i64_simd(float %a) {
}
define double @test_fptosi_f64_i64_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: test_fptosi_f64_i64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -140,11 +135,6 @@ define double @test_fptosi_f64_i64_simd(double %a) {
define float @test_fptosi_f32_i32_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: test_fptosi_f32_i32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -269,11 +259,6 @@ define double @test_fptoui_f32_i64_simd(float %a) {
}
define double @test_fptoui_f64_i64_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: test_fptoui_f64_i64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
@@ -295,11 +280,6 @@ define double @test_fptoui_f64_i64_simd(double %a) {
define float @test_fptoui_f32_i32_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: test_fptoui_f32_i32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
@@ -379,11 +359,6 @@ define float @fcvtas_sd_round_simd(double %a) {
}
define float @fcvtas_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtas_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
@@ -405,11 +380,6 @@ define float @fcvtas_ss_round_simd(float %a) {
}
define double @fcvtas_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtas_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
@@ -486,11 +456,6 @@ define float @fcvtau_sd_round_simd(double %a) {
}
define float @fcvtau_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtau_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
@@ -512,11 +477,6 @@ define float @fcvtau_ss_round_simd(float %a) {
}
define double @fcvtau_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtau_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
@@ -805,11 +765,6 @@ define float @fcvtms_sd_round_simd(double %a) {
}
define float @fcvtms_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtms_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
@@ -831,11 +786,6 @@ define float @fcvtms_ss_round_simd(float %a) {
}
define double @fcvtms_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtms_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
@@ -913,11 +863,6 @@ define float @fcvtmu_sd_round_simd(double %a) {
}
define float @fcvtmu_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtmu_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
@@ -939,11 +884,6 @@ define float @fcvtmu_ss_round_simd(float %a) {
}
define double @fcvtmu_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtmu_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
@@ -1020,11 +960,6 @@ define float @fcvtps_sd_round_simd(double %a) {
}
define float @fcvtps_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtps_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
@@ -1046,11 +981,6 @@ define float @fcvtps_ss_round_simd(float %a) {
}
define double @fcvtps_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtps_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
@@ -1127,11 +1057,6 @@ define float @fcvtpu_sd_round_simd(double %a) {
}
define float @fcvtpu_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtpu_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
@@ -1153,11 +1078,6 @@ define float @fcvtpu_ss_round_simd(float %a) {
}
define double @fcvtpu_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtpu_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
@@ -1234,11 +1154,6 @@ define float @fcvtzs_sd_round_simd(double %a) {
}
define float @fcvtzs_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -1260,11 +1175,6 @@ define float @fcvtzs_ss_round_simd(float %a) {
}
define double @fcvtzs_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -1340,11 +1250,6 @@ define float @fcvtzu_sd_round_simd(double %a) {
}
define float @fcvtzu_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -1366,11 +1271,6 @@ define float @fcvtzu_ss_round_simd(float %a) {
}
define double @fcvtzu_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -1501,11 +1401,6 @@ define float @fcvtzs_sd_sat_simd(double %a) {
}
define float @fcvtzs_ss_sat_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_ss_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -1526,11 +1421,6 @@ define float @fcvtzs_ss_sat_simd(float %a) {
}
define double @fcvtzs_dd_sat_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_dd_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -1655,11 +1545,6 @@ define float @fcvtzu_sd_sat_simd(double %a) {
}
define float @fcvtzu_ss_sat_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_ss_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -1680,11 +1565,6 @@ define float @fcvtzu_ss_sat_simd(float %a) {
}
define double @fcvtzu_dd_sat_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_dd_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -1817,11 +1697,6 @@ define float @fcvtas_sd_simd(double %a) {
}
define float @fcvtas_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtas_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
@@ -1843,11 +1718,6 @@ define float @fcvtas_ss_simd(float %a) {
}
define double @fcvtas_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtas_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
@@ -1977,11 +1847,6 @@ define float @fcvtau_sd_simd(double %a) {
}
define float @fcvtau_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtau_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
@@ -2003,11 +1868,6 @@ define float @fcvtau_ss_simd(float %a) {
}
define double @fcvtau_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtau_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
@@ -2457,11 +2317,6 @@ define float @fcvtms_sd_simd(double %a) {
}
define float @fcvtms_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtms_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
@@ -2483,11 +2338,6 @@ define float @fcvtms_ss_simd(float %a) {
}
define double @fcvtms_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtms_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
@@ -2617,11 +2467,6 @@ define float @fcvtmu_sd_simd(double %a) {
}
define float @fcvtmu_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtmu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
@@ -2643,11 +2488,6 @@ define float @fcvtmu_ss_simd(float %a) {
}
define double @fcvtmu_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtmu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
@@ -2777,11 +2617,6 @@ define float @fcvtps_sd_simd(double %a) {
}
define float @fcvtps_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtps_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
@@ -2803,11 +2638,6 @@ define float @fcvtps_ss_simd(float %a) {
}
define double @fcvtps_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtps_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
@@ -2937,11 +2767,6 @@ define float @fcvtpu_sd_simd(double %a) {
}
define float @fcvtpu_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtpu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
@@ -2963,11 +2788,6 @@ define float @fcvtpu_ss_simd(float %a) {
}
define double @fcvtpu_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtpu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
@@ -3097,11 +2917,6 @@ define float @fcvtzs_sd_simd(double %a) {
}
define float @fcvtzs_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
@@ -3123,11 +2938,6 @@ define float @fcvtzs_ss_simd(float %a) {
}
define double @fcvtzs_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzs_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
@@ -3257,11 +3067,6 @@ define float @fcvtzu_sd_simd(double %a) {
}
define float @fcvtzu_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
@@ -3283,11 +3088,6 @@ define float @fcvtzu_ss_simd(float %a) {
}
define double @fcvtzu_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtzu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
@@ -3307,3 +3107,6 @@ define double @fcvtzu_dd_simd(double %a) {
%bc = bitcast i64 %i to double
ret double %bc
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI-FPRCVT: {{.*}}
+; CHECK-SD-FPRCVT: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index 4f3666c58d317..8d2980a922593 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -2,11 +2,6 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for test_bitcastv2f32tov1f64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_bitcastv1f64tov2f32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_v1i32_undef
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_diff_v1i32_v1i32
-
define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
; CHECK-LABEL: ins16bw:
; CHECK: // %bb.0:
diff --git a/llvm/test/CodeGen/AArch64/arm64-smaxv.ll b/llvm/test/CodeGen/AArch64/arm64-smaxv.ll
index 1bed8df916ea2..981c4d2aeecbb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-smaxv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-smaxv.ll
@@ -1,11 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
; RUN: llc < %s -global-isel=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define signext i8 @test_vmaxv_s8(<8 x i8> %a1) {
-; CHECK: test_vmaxv_s8
-; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vmaxv_s8:
+; CHECK: smaxv.8b b0, v0
+; CHECK-NEXT: smov.b w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
%0 = trunc i32 %vmaxv.i to i8
@@ -13,10 +14,10 @@ entry:
}
define signext i16 @test_vmaxv_s16(<4 x i16> %a1) {
-; CHECK: test_vmaxv_s16
-; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vmaxv_s16:
+; CHECK: smaxv.4h h0, v0
+; CHECK-NEXT: smov.h w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a1)
%0 = trunc i32 %vmaxv.i to i16
@@ -24,21 +25,21 @@ entry:
}
define i32 @test_vmaxv_s32(<2 x i32> %a1) {
-; CHECK: test_vmaxv_s32
+; CHECK-LABEL: test_vmaxv_s32:
+; CHECK: smaxp.2s v0, v0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
; 2 x i32 is not supported by the ISA, thus, this is a special case
-; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v0, v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a1)
ret i32 %vmaxv.i
}
define signext i8 @test_vmaxvq_s8(<16 x i8> %a1) {
-; CHECK: test_vmaxvq_s8
-; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vmaxvq_s8:
+; CHECK: smaxv.16b b0, v0
+; CHECK-NEXT: smov.b w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a1)
%0 = trunc i32 %vmaxv.i to i8
@@ -46,10 +47,10 @@ entry:
}
define signext i16 @test_vmaxvq_s16(<8 x i16> %a1) {
-; CHECK: test_vmaxvq_s16
-; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vmaxvq_s16:
+; CHECK: smaxv.8h h0, v0
+; CHECK-NEXT: smov.h w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a1)
%0 = trunc i32 %vmaxv.i to i16
@@ -57,10 +58,10 @@ entry:
}
define i32 @test_vmaxvq_s32(<4 x i32> %a1) {
-; CHECK: test_vmaxvq_s32
-; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v0
-; CHECK-NEXT: fmov w0, [[REGNUM]]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vmaxvq_s32:
+; CHECK: smaxv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a1)
ret i32 %vmaxv.i
@@ -68,9 +69,9 @@ entry:
define <8 x i8> @test_vmaxv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
; CHECK-LABEL: test_vmaxv_s8_used_by_laneop:
-; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.8b b1, v1
+; CHECK-NEXT: mov.b v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -80,9 +81,9 @@ entry:
define <4 x i16> @test_vmaxv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: test_vmaxv_s16_used_by_laneop:
-; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.4h h1, v1
+; CHECK-NEXT: mov.h v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -92,9 +93,9 @@ entry:
define <2 x i32> @test_vmaxv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
; CHECK-LABEL: test_vmaxv_s32_used_by_laneop:
-; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxp.2s v1, v1, v1
+; CHECK-NEXT: mov.s v0[1], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a2)
%1 = insertelement <2 x i32> %a1, i32 %0, i32 1
@@ -103,9 +104,9 @@ entry:
define <16 x i8> @test_vmaxvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
; CHECK-LABEL: test_vmaxvq_s8_used_by_laneop:
-; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.16b b1, v1
+; CHECK-NEXT: mov.b v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -115,9 +116,9 @@ entry:
define <8 x i16> @test_vmaxvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
; CHECK-LABEL: test_vmaxvq_s16_used_by_laneop:
-; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.8h h1, v1
+; CHECK-NEXT: mov.h v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -127,9 +128,9 @@ entry:
define <4 x i32> @test_vmaxvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
; CHECK-LABEL: test_vmaxvq_s32_used_by_laneop:
-; CHECK: smaxv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.4s s1, v1
+; CHECK-NEXT: mov.s v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a2)
%1 = insertelement <4 x i32> %a1, i32 %0, i32 3
diff --git a/llvm/test/CodeGen/AArch64/arm64-sminv.ll b/llvm/test/CodeGen/AArch64/arm64-sminv.ll
index 683044c9e8e0b..6d27249c32432 100644
--- a/llvm/test/CodeGen/AArch64/arm64-sminv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-sminv.ll
@@ -1,11 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
; RUN: llc < %s -global-isel=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define signext i8 @test_vminv_s8(<8 x i8> %a1) {
-; CHECK: test_vminv_s8
-; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vminv_s8:
+; CHECK: sminv.8b b0, v0
+; CHECK-NEXT: smov.b w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)
%0 = trunc i32 %vminv.i to i8
@@ -13,10 +14,10 @@ entry:
}
define signext i16 @test_vminv_s16(<4 x i16> %a1) {
-; CHECK: test_vminv_s16
-; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vminv_s16:
+; CHECK: sminv.4h h0, v0
+; CHECK-NEXT: smov.h w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a1)
%0 = trunc i32 %vminv.i to i16
@@ -24,21 +25,21 @@ entry:
}
define i32 @test_vminv_s32(<2 x i32> %a1) {
-; CHECK: test_vminv_s32
+; CHECK-LABEL: test_vminv_s32:
+; CHECK: sminp.2s v0, v0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
; 2 x i32 is not supported by the ISA, thus, this is a special case
-; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a1)
ret i32 %vminv.i
}
define signext i8 @test_vminvq_s8(<16 x i8> %a1) {
-; CHECK: test_vminvq_s8
-; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vminvq_s8:
+; CHECK: sminv.16b b0, v0
+; CHECK-NEXT: smov.b w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a1)
%0 = trunc i32 %vminv.i to i8
@@ -46,10 +47,10 @@ entry:
}
define signext i16 @test_vminvq_s16(<8 x i16> %a1) {
-; CHECK: test_vminvq_s16
-; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vminvq_s16:
+; CHECK: sminv.8h h0, v0
+; CHECK-NEXT: smov.h w0, v0[0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a1)
%0 = trunc i32 %vminv.i to i16
@@ -57,10 +58,10 @@ entry:
}
define i32 @test_vminvq_s32(<4 x i32> %a1) {
-; CHECK: test_vminvq_s32
-; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
-; CHECK-NEXT: fmov w0, [[REGNUM]]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_vminvq_s32:
+; CHECK: sminv.4s s0, v0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a1)
ret i32 %vminv.i
@@ -68,9 +69,9 @@ entry:
define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
; CHECK-LABEL: test_vminv_s8_used_by_laneop:
-; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminv.8b b1, v1
+; CHECK-NEXT: mov.b v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -80,9 +81,9 @@ entry:
define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: test_vminv_s16_used_by_laneop:
-; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminv.4h h1, v1
+; CHECK-NEXT: mov.h v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -92,9 +93,9 @@ entry:
define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
; CHECK-LABEL: test_vminv_s32_used_by_laneop:
-; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminp.2s v1, v1, v1
+; CHECK-NEXT: mov.s v0[1], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)
%1 = insertelement <2 x i32> %a1, i32 %0, i32 1
@@ -103,9 +104,9 @@ entry:
define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
; CHECK-LABEL: test_vminvq_s8_used_by_laneop:
-; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminv.16b b1, v1
+; CHECK-NEXT: mov.b v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -115,9 +116,9 @@ entry:
define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
; CHECK-LABEL: test_vminvq_s16_used_by_laneop:
-; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminv.8h h1, v1
+; CHECK-NEXT: mov.h v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -127,9 +128,9 @@ entry:
define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
; CHECK-LABEL: test_vminvq_s32_used_by_laneop:
-; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
-; CHECK-NEXT: ret
+; CHECK: sminv.4s s1, v1
+; CHECK-NEXT: mov.s v0[3], v1[0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)
%1 = insertelement <4 x i32> %a1, i32 %0, i32 3
diff --git a/llvm/test/CodeGen/AArch64/arm64-vaddv.ll b/llvm/test/CodeGen/AArch64/arm64-vaddv.ll
index d60b6d7097308..6d6484a584d81 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vaddv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vaddv.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define signext i8 @test_vaddv_s8(<8 x i8> %a1) {
; CHECK-LABEL: test_vaddv_s8:
@@ -451,3 +451,6 @@ declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
declare float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)
declare float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)
declare double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
+; CHECK-SD: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/bitcast-extend.ll b/llvm/test/CodeGen/AArch64/bitcast-extend.ll
index c68e55d7a8aef..b4c77aa76a9fa 100644
--- a/llvm/test/CodeGen/AArch64/bitcast-extend.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast-extend.ll
@@ -2,10 +2,6 @@
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for load_zext_i8_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for load_zext_i16_v4bf16
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for load_zext_i32_v4bf16
-
define <4 x i16> @z_i32_v4i16(i32 %x) {
; CHECK-SD-LABEL: z_i32_v4i16:
; CHECK-SD: // %bb.0:
@@ -574,11 +570,16 @@ define <2 x float> @load_zext_i32_v2f32(ptr %p) {
}
define <1 x double> @load_zext_i8_v1f64(ptr %p) {
-; CHECK-LABEL: load_zext_i8_v1f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: load_zext_i8_v1f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldrb w8, [x0]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: load_zext_i8_v1f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr b0, [x0]
+; CHECK-GI-NEXT: ret
%l = load i8, ptr %p
%z = zext i8 %l to i64
%b = bitcast i64 %z to <1 x double>
@@ -586,11 +587,16 @@ define <1 x double> @load_zext_i8_v1f64(ptr %p) {
}
define <1 x double> @load_zext_i16_v1f64(ptr %p) {
-; CHECK-LABEL: load_zext_i16_v1f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldrh w8, [x0]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: load_zext_i16_v1f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldrh w8, [x0]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: load_zext_i16_v1f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr h0, [x0]
+; CHECK-GI-NEXT: ret
%l = load i16, ptr %p
%z = zext i16 %l to i64
%b = bitcast i64 %z to <1 x double>
@@ -598,11 +604,16 @@ define <1 x double> @load_zext_i16_v1f64(ptr %p) {
}
define <1 x double> @load_zext_i32_v1f64(ptr %p) {
-; CHECK-LABEL: load_zext_i32_v1f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr w8, [x0]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: load_zext_i32_v1f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr w8, [x0]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: load_zext_i32_v1f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr s0, [x0]
+; CHECK-GI-NEXT: ret
%l = load i32, ptr %p
%z = zext i32 %l to i64
%b = bitcast i64 %z to <1 x double>
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index d360a9da7d966..2c76de454a39a 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -843,19 +843,19 @@ define <3 x double> @v3f64_double(<3 x double> %a, <3 x double> %b, <3 x double>
; CHECK-GI-NEXT: // kill: def $d6 killed $d6 def $q6
; CHECK-GI-NEXT: // kill: def $d7 killed $d7 def $q7
; CHECK-GI-NEXT: fcmp d2, d5
-; CHECK-GI-NEXT: ldr x8, [sp]
+; CHECK-GI-NEXT: ldr x9, [sp]
; CHECK-GI-NEXT: ldr x10, [sp, #24]
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]
; CHECK-GI-NEXT: mov v6.d[1], v7.d[0]
; CHECK-GI-NEXT: ldp d1, d4, [sp, #8]
-; CHECK-GI-NEXT: cset w9, mi
-; CHECK-GI-NEXT: sbfx x9, x9, #0, #1
+; CHECK-GI-NEXT: cset w8, mi
+; CHECK-GI-NEXT: sbfx x8, x8, #0, #1
; CHECK-GI-NEXT: fcmgt v0.2d, v3.2d, v0.2d
; CHECK-GI-NEXT: mov v1.d[1], v4.d[0]
-; CHECK-GI-NEXT: and x8, x8, x9
-; CHECK-GI-NEXT: bic x9, x10, x9
-; CHECK-GI-NEXT: orr x8, x8, x9
+; CHECK-GI-NEXT: and x9, x9, x8
+; CHECK-GI-NEXT: bic x8, x10, x8
+; CHECK-GI-NEXT: orr x8, x9, x8
; CHECK-GI-NEXT: fmov d2, x8
; CHECK-GI-NEXT: bsl v0.16b, v6.16b, v1.16b
; CHECK-GI-NEXT: mov d1, v0.d[1]
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
index b6cbe9eb46389..099a5732992d5 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
@@ -968,35 +968,44 @@ define i32 @test_signed_f128_i32(fp128 %f) {
;
; CHECK-GI-LABEL: test_signed_f128_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-GI-NEXT: sub sp, sp, #64
+; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: .cfi_offset w30, -16
+; CHECK-GI-NEXT: .cfi_offset b8, -24
+; CHECK-GI-NEXT: .cfi_offset b9, -32
+; CHECK-GI-NEXT: .cfi_offset b10, -48
+; CHECK-GI-NEXT: adrp x8, .LCPI30_2
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_2]
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x9, #-4603241769126068224 // =0xc01e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x9, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI30_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
+; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: fcsel d10, d0, d1, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: adrp x8, .LCPI30_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
-; CHECK-GI-NEXT: movk x8, #16413, lsl #48
-; CHECK-GI-NEXT: csel x8, x20, x8, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
@@ -1004,10 +1013,11 @@ define i32 @test_signed_f128_i32(fp128 %f) {
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel w0, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-GI-NEXT: add sp, sp, #48
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call i32 @llvm.fptosi.sat.i32.f128(fp128 %f)
ret i32 %x
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 6a06d99689df9..218e3ea1da3bc 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -517,35 +517,44 @@ define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v1f128_v1i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-GI-NEXT: sub sp, sp, #64
+; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: .cfi_offset w30, -16
+; CHECK-GI-NEXT: .cfi_offset b8, -24
+; CHECK-GI-NEXT: .cfi_offset b9, -32
+; CHECK-GI-NEXT: .cfi_offset b10, -48
+; CHECK-GI-NEXT: adrp x8, .LCPI14_2
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_2]
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x9, #-4603241769126068224 // =0xc01e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x9, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
+; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: fcsel d10, d0, d1, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: adrp x8, .LCPI14_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
-; CHECK-GI-NEXT: movk x8, #16413, lsl #48
-; CHECK-GI-NEXT: csel x8, x20, x8, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
@@ -553,11 +562,12 @@ define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: add sp, sp, #48
+; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f128.v1i32(<1 x fp128> %f)
ret <1 x i32> %x
@@ -631,42 +641,51 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #112
-; CHECK-GI-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
+; CHECK-GI-NEXT: sub sp, sp, #128
+; CHECK-GI-NEXT: stp d11, d10, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -56
+; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: adrp x8, .LCPI15_2
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_1]
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
; CHECK-GI-NEXT: str q2, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fmov d10, x8
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d11, d0, d10, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x22, #16413, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI15_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
@@ -676,37 +695,41 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w21, wzr, w19, ne
+; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d10, d0, d10, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w21
+; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #64] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #112
+; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x
@@ -799,43 +822,54 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v3f128_v3i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: stp x30, x23, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
+; CHECK-GI-NEXT: sub sp, sp, #160
+; CHECK-GI-NEXT: str d12, [sp, #80] // 8-byte Spill
+; CHECK-GI-NEXT: stp d11, d10, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x21, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w30, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI16_1
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -56
+; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: .cfi_offset b12, -80
+; CHECK-GI-NEXT: adrp x8, .LCPI16_2
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_2]
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-GI-NEXT: str q2, [sp, #64] // 16-byte Spill
; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
+; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d11, d0, d9, gt
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI16_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x22, #16413, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI16_0
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI16_0]
+; CHECK-GI-NEXT: fcsel d1, d11, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
@@ -844,22 +878,25 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w21, wzr, w19, ne
+; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x23, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d12
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
@@ -869,37 +906,42 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w23, wzr, w19, ne
+; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d9, d0, d9, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d9, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w21
+; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: ldr d12, [sp, #80] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: mov v0.s[1], w23
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.s[1], w21
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #128] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #96] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: add sp, sp, #128
+; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x
@@ -1014,44 +1056,55 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v4f128_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #160
-; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
-; CHECK-GI-NEXT: stp x24, x23, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
+; CHECK-GI-NEXT: sub sp, sp, #176
+; CHECK-GI-NEXT: str d12, [sp, #96] // 8-byte Spill
+; CHECK-GI-NEXT: stp d11, d10, [sp, #104] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #120] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #136] // 8-byte Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #160] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 176
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w24, -48
-; CHECK-GI-NEXT: .cfi_offset w30, -64
-; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: .cfi_offset w30, -40
+; CHECK-GI-NEXT: .cfi_offset b8, -48
+; CHECK-GI-NEXT: .cfi_offset b9, -56
+; CHECK-GI-NEXT: .cfi_offset b10, -64
+; CHECK-GI-NEXT: .cfi_offset b11, -72
+; CHECK-GI-NEXT: .cfi_offset b12, -80
+; CHECK-GI-NEXT: adrp x8, .LCPI17_2
; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_2]
; CHECK-GI-NEXT: str q2, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: stp q1, q3, [sp, #64] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d11, d0, d9, gt
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x22, #16413, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI17_0
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: fcsel d1, d11, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
@@ -1061,22 +1114,25 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w21, wzr, w19, ne
+; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x23, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d12
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
@@ -1086,21 +1142,24 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w23, wzr, w19, ne
+; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q4, q1, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x24, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x24
+; CHECK-GI-NEXT: mov d0, v4.d[1]
+; CHECK-GI-NEXT: fcsel d11, d4, d8, gt
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d12
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x24, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
@@ -1109,39 +1168,44 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w24, wzr, w19, ne
+; CHECK-GI-NEXT: csel w22, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: fcsel d9, d0, d9, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d9, d10, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w21
+; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #136] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #128] // 16-byte Folded Reload
-; CHECK-GI-NEXT: mov v0.s[1], w23
-; CHECK-GI-NEXT: mov v0.s[2], w24
-; CHECK-GI-NEXT: ldp x24, x23, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #120] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d12, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: mov v0.s[1], w21
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #104] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.s[2], w22
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #144] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: add sp, sp, #160
+; CHECK-GI-NEXT: add sp, sp, #176
; CHECK-GI-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x
@@ -5126,17 +5190,21 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #112
-; CHECK-GI-NEXT: stp x30, x23, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
+; CHECK-GI-NEXT: sub sp, sp, #128
+; CHECK-GI-NEXT: str d12, [sp, #64] // 8-byte Spill
+; CHECK-GI-NEXT: stp d11, d10, [sp, #72] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #88] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #104] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: .cfi_offset b9, -40
+; CHECK-GI-NEXT: .cfi_offset b10, -48
+; CHECK-GI-NEXT: .cfi_offset b11, -56
+; CHECK-GI-NEXT: .cfi_offset b12, -64
; CHECK-GI-NEXT: adrp x8, .LCPI86_1
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
@@ -5144,25 +5212,35 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: mov v1.16b, v2.16b
; CHECK-GI-NEXT: str q2, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x20, #-4594234569871327232 // =0xc03e000000000000
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x21, x8, x20, gt
+; CHECK-GI-NEXT: mov x8, #8521215115264 // =0x7c000000000
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: movk x8, #17384, lsl #48
+; CHECK-GI-NEXT: fmov d10, x8
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d11, d0, d10, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
-; CHECK-GI-NEXT: mov v0.d[1], x21
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: mov x22, #-1125899906842624 // =0xfffc000000000000
+; CHECK-GI-NEXT: mov x8, #280925220896768 // =0xff8000000000
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x23, #4629137466983448575 // =0x403dffffffffffff
-; CHECK-GI-NEXT: csel x8, x19, x22, mi
+; CHECK-GI-NEXT: movk x8, #17391, lsl #48
+; CHECK-GI-NEXT: fmov d12, x8
+; CHECK-GI-NEXT: mov x8, #-264432546480129 // =0xffff0f7fffffffff
+; CHECK-GI-NEXT: movk x8, #17360, lsl #48
+; CHECK-GI-NEXT: fcsel d0, d9, d12, mi
+; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x23, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfdi
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
@@ -5172,36 +5250,41 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x21, xzr, x19, ne
+; CHECK-GI-NEXT: csel x20, xzr, x19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d8, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, x20, gt
-; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: fmov x8, d8
+; CHECK-GI-NEXT: fcsel d10, d0, d10, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, x22, mi
+; CHECK-GI-NEXT: fcsel d0, d8, d12, mi
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x23, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfdi
; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov d0, x21
+; CHECK-GI-NEXT: fmov d0, x20
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: ldr x30, [sp, #104] // 8-byte Reload
; CHECK-GI-NEXT: csel x8, xzr, x19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #88] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d12, [sp, #64] // 8-byte Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #72] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: add sp, sp, #112
+; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
%x = call <2 x i64> @llvm.fptosi.sat.v2f128.v2i64(<2 x fp128> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
index 7a5fe0f4222bc..9c9f91ec26008 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
@@ -784,34 +784,42 @@ define i32 @test_unsigned_f128_i32(fp128 %f) {
; CHECK-GI-LABEL: test_unsigned_f128_i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
-; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: .cfi_offset w30, -8
+; CHECK-GI-NEXT: .cfi_offset b8, -16
+; CHECK-GI-NEXT: .cfi_offset b9, -24
+; CHECK-GI-NEXT: .cfi_offset b10, -32
+; CHECK-GI-NEXT: adrp x8, .LCPI30_2
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_2]
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI30_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: adrp x8, .LCPI30_0
+; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
+; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
+; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
-; CHECK-GI-NEXT: movk x8, #16414, lsl #48
-; CHECK-GI-NEXT: csel x8, x20, x8, mi
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: b __fixunstfsi
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index d4feab2ea5d9b..e41a0c4918803 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -474,37 +474,45 @@ define <1 x i32> @test_unsigned_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-GI-LABEL: test_unsigned_v1f128_v1i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
-; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: .cfi_offset w30, -8
+; CHECK-GI-NEXT: .cfi_offset b8, -16
+; CHECK-GI-NEXT: .cfi_offset b9, -24
+; CHECK-GI-NEXT: .cfi_offset b10, -32
+; CHECK-GI-NEXT: adrp x8, .LCPI14_2
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_2]
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: adrp x8, .LCPI14_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
-; CHECK-GI-NEXT: movk x8, #16414, lsl #48
-; CHECK-GI-NEXT: csel x8, x20, x8, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-GI-NEXT: fmov s0, w0
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
%x = call <1 x i32> @llvm.fptoui.sat.v1f128.v1i32(<1 x fp128> %f)
@@ -563,62 +571,74 @@ define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #80
-; CHECK-GI-NEXT: str x30, [sp, #32] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
+; CHECK-GI-NEXT: sub sp, sp, #96
+; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -48
-; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: .cfi_offset w30, -16
+; CHECK-GI-NEXT: .cfi_offset b8, -24
+; CHECK-GI-NEXT: .cfi_offset b9, -32
+; CHECK-GI-NEXT: .cfi_offset b10, -40
+; CHECK-GI-NEXT: .cfi_offset b11, -48
+; CHECK-GI-NEXT: adrp x8, .LCPI15_2
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
+; CHECK-GI-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill
+; CHECK-GI-NEXT: mov v1.16b, v2.16b
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x21, #281474976579584 // =0xfffffffe0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x21, #16414, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI15_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x22, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x22
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x20, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x22, x21, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: add sp, sp, #80
@@ -692,86 +712,101 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v3f128_v3i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #96
-; CHECK-GI-NEXT: stp x30, x23, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
+; CHECK-GI-NEXT: sub sp, sp, #128
+; CHECK-GI-NEXT: stp d11, d10, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -56
+; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: adrp x8, .LCPI16_2
; CHECK-GI-NEXT: stp q1, q0, [sp] // 32-byte Folded Spill
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: str q2, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_2]
+; CHECK-GI-NEXT: stp q1, q2, [sp, #32] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI16_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x21, #281474976579584 // =0xfffffffe0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x21, #16414, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI16_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI16_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q3, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x22, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x22
+; CHECK-GI-NEXT: mov d0, v3.d[1]
+; CHECK-GI-NEXT: fcsel d10, d3, d8, gt
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x20, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x22, x21, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w20, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x22, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x22
-; CHECK-GI-NEXT: csel x23, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x22, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x21, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w0
-; CHECK-GI-NEXT: add sp, sp, #96
+; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
%x = call <3 x i32> @llvm.fptoui.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x
@@ -860,109 +895,126 @@ define <4 x i32> @test_unsigned_v4f128_v4i32(<4 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v4f128_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-GI-NEXT: stp x24, x23, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
+; CHECK-GI-NEXT: sub sp, sp, #144
+; CHECK-GI-NEXT: stp d11, d10, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x21, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 144
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w24, -48
-; CHECK-GI-NEXT: .cfi_offset w30, -64
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -56
+; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: adrp x8, .LCPI17_2
; CHECK-GI-NEXT: stp q1, q2, [sp] // 32-byte Folded Spill
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: stp q3, q0, [sp, #32] // 32-byte Folded Spill
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_2]
+; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q3, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #281474976579584 // =0xfffffffe0000
-; CHECK-GI-NEXT: csel x8, x19, xzr, mi
-; CHECK-GI-NEXT: movk x22, #16414, lsl #48
+; CHECK-GI-NEXT: adrp x8, .LCPI17_0
+; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
+; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x21, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x21
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x20, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: mov w20, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x21, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x21
-; CHECK-GI-NEXT: csel x23, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x21, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w21, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q4, q1, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x23, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x23
-; CHECK-GI-NEXT: csel x24, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x24
+; CHECK-GI-NEXT: mov d0, v4.d[1]
+; CHECK-GI-NEXT: fcsel d10, d4, d8, gt
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d11
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x23, xzr, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x24, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp x24, x23, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr x30, [sp, #64] // 8-byte Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w21
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[3], w0
; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
@@ -4124,12 +4176,27 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
+<<<<<<< HEAD
; CHECK-GI-NEXT: sub sp, sp, #80
; CHECK-GI-NEXT: stp x30, x23, [sp, #32] // 16-byte Folded Spill
; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
; CHECK-GI-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
+||||||| parent of 25bc4b2b4034 (Update tests)
+; CHECK-GI-NEXT: sub sp, sp, #96
+; CHECK-GI-NEXT: stp x30, x23, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
+=======
+; CHECK-GI-NEXT: sub sp, sp, #96
+; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
+>>>>>>> 25bc4b2b4034 (Update tests)
; CHECK-GI-NEXT: .cfi_offset w19, -8
+<<<<<<< HEAD
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w22, -32
@@ -4137,50 +4204,118 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: .cfi_offset w30, -48
; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+||||||| parent of 25bc4b2b4034 (Update tests)
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w21, -24
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w23, -40
+; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: adrp x8, .LCPI86_1
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
+; CHECK-GI-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill
+; CHECK-GI-NEXT: mov v1.16b, v2.16b
+=======
+; CHECK-GI-NEXT: .cfi_offset w30, -16
+; CHECK-GI-NEXT: .cfi_offset b8, -24
+; CHECK-GI-NEXT: .cfi_offset b9, -32
+; CHECK-GI-NEXT: .cfi_offset b10, -40
+; CHECK-GI-NEXT: .cfi_offset b11, -48
+; CHECK-GI-NEXT: adrp x8, .LCPI86_1
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
+; CHECK-GI-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill
+; CHECK-GI-NEXT: mov v1.16b, v2.16b
+>>>>>>> 25bc4b2b4034 (Update tests)
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: movi d8, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x19, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x19
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
+; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
+; CHECK-GI-NEXT: fmov x8, d9
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
-; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: mov x21, #-562949953421312 // =0xfffe000000000000
+; CHECK-GI-NEXT: mov x8, #281200098803712 // =0xffc000000000
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x22, #4629418941960159231 // =0x403effffffffffff
-; CHECK-GI-NEXT: csel x8, x19, x21, mi
+; CHECK-GI-NEXT: movk x8, #17391, lsl #48
+; CHECK-GI-NEXT: fmov d11, x8
+; CHECK-GI-NEXT: mov x8, #-264157668573185 // =0xffff0fbfffffffff
+; CHECK-GI-NEXT: movk x8, #17360, lsl #48
+; CHECK-GI-NEXT: fcsel d0, d9, d11, mi
+; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfdi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: bl __gttf2
+<<<<<<< HEAD
; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload
+||||||| parent of 25bc4b2b4034 (Update tests)
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+=======
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+>>>>>>> 25bc4b2b4034 (Update tests)
; CHECK-GI-NEXT: cmp w0, #0
+<<<<<<< HEAD
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: csel x20, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x20
; CHECK-GI-NEXT: csel x23, x8, xzr, gt
; CHECK-GI-NEXT: mov v0.d[1], x23
+||||||| parent of 25bc4b2b4034 (Update tests)
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x20
+; CHECK-GI-NEXT: csel x23, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x23
+=======
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d8, d0, d8, gt
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d8
+; CHECK-GI-NEXT: mov v0.d[1], x8
+>>>>>>> 25bc4b2b4034 (Update tests)
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: fcsel d0, d10, d11, mi
+; CHECK-GI-NEXT: fcsel d1, d8, d9, mi
+; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: fmov x8, d1
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfdi
; CHECK-GI-NEXT: fmov d0, x19
+<<<<<<< HEAD
; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp x30, x23, [sp, #32] // 16-byte Folded Reload
+||||||| parent of 25bc4b2b4034 (Update tests)
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x23, [sp, #48] // 16-byte Folded Reload
+=======
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
+>>>>>>> 25bc4b2b4034 (Update tests)
; CHECK-GI-NEXT: mov v0.d[1], x0
; CHECK-GI-NEXT: add sp, sp, #80
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/insertextract.ll b/llvm/test/CodeGen/AArch64/insertextract.ll
index 641701beeda43..49e87de5ab6f9 100644
--- a/llvm/test/CodeGen/AArch64/insertextract.ll
+++ b/llvm/test/CodeGen/AArch64/insertextract.ll
@@ -1390,7 +1390,7 @@ define <2 x i128> @insert_v2i128_c(<2 x i128> %a, i128 %b, i32 %c) {
; CHECK-GI-NEXT: .cfi_offset w30, -8
; CHECK-GI-NEXT: .cfi_offset w29, -16
; CHECK-GI-NEXT: adds x8, x0, x0
-; CHECK-GI-NEXT: mov v2.d[0], x4
+; CHECK-GI-NEXT: fmov d2, x4
; CHECK-GI-NEXT: adc x9, x1, x1
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: adds x8, x2, x2
@@ -2887,18 +2887,20 @@ define i128 @extract_v2i128_c(<2 x i128> %a, i32 %c) {
; CHECK-GI-NEXT: .cfi_offset w30, -8
; CHECK-GI-NEXT: .cfi_offset w29, -16
; CHECK-GI-NEXT: adds x8, x0, x0
+; CHECK-GI-NEXT: mov x10, sp
; CHECK-GI-NEXT: adc x9, x1, x1
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: adds x8, x2, x2
; CHECK-GI-NEXT: mov v1.d[0], x8
; CHECK-GI-NEXT: adc x8, x3, x3
; CHECK-GI-NEXT: mov v0.d[1], x9
-; CHECK-GI-NEXT: mov x9, sp
+; CHECK-GI-NEXT: mov w9, #16 // =0x10
; CHECK-GI-NEXT: mov v1.d[1], x8
; CHECK-GI-NEXT: mov w8, w4
; CHECK-GI-NEXT: and x8, x8, #0x1
+; CHECK-GI-NEXT: umaddl x8, w8, w9, x10
; CHECK-GI-NEXT: stp q0, q1, [sp]
-; CHECK-GI-NEXT: ldr q0, [x9, x8, lsl #4]
+; CHECK-GI-NEXT: ldr q0, [x8]
; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: fmov x0, d0
; CHECK-GI-NEXT: fmov x1, d1
diff --git a/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll b/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
index d9cdbc2f92aca..2191b67fc816a 100644
--- a/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
+++ b/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
@@ -4,8 +4,8 @@
define <4 x i32> @test_vins_v4i32(<4 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v4i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: ret
entry:
%c = bitcast float %b to i32
@@ -16,8 +16,8 @@ entry:
define <4 x i32> @test_vins_v4i32_0(<4 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v4i32_0:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-NEXT: mov v0.s[0], v1.s[0]
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.s[0], w8
; CHECK-NEXT: ret
entry:
%c = bitcast float %b to i32
@@ -28,9 +28,9 @@ entry:
define <2 x i32> @test_vins_v2i32(<2 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v2i32:
; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
@@ -42,9 +42,9 @@ entry:
define <2 x i32> @test_vins_v2i32_0(<2 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v2i32_0:
; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-NEXT: mov v0.s[0], v1.s[0]
+; CHECK-NEXT: mov v0.s[0], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
@@ -56,8 +56,8 @@ entry:
define <2 x i64> @test_vins_v2i64(<2 x i64> %a, double %b) {
; CHECK-LABEL: test_vins_v2i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: fmov x8, d1
+; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret
entry:
%c = bitcast double %b to i64
@@ -68,8 +68,8 @@ entry:
define <2 x i64> @test_vins_v2i64_0(<2 x i64> %a, double %b) {
; CHECK-LABEL: test_vins_v2i64_0:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT: mov v0.d[0], v1.d[0]
+; CHECK-NEXT: fmov x8, d1
+; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret
entry:
%c = bitcast double %b to i64
diff --git a/llvm/test/CodeGen/AArch64/popcount.ll b/llvm/test/CodeGen/AArch64/popcount.ll
index bb81776a7f6d6..d0a24b9cd287b 100644
--- a/llvm/test/CodeGen/AArch64/popcount.ll
+++ b/llvm/test/CodeGen/AArch64/popcount.ll
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+neon,+dotprod | FileCheck %s --check-prefixes=CHECK,DOT
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+sve | FileCheck %s --check-prefixes=CHECK,SVE
; RUN: llc < %s -mtriple=aarch64_be-unknown-unknown | FileCheck %s --check-prefixes=BE
-; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefix=GISEL
+; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefixes=GISEL,GISELO3
; RUN: llc < %s -O0 -global-isel -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefix=GISELO0
; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown -mattr=+neon | FileCheck %s --check-prefixes=GISEL,NEON-GISEL
; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown -mattr=+neon,+dotprod | FileCheck %s --check-prefixes=GISEL,DOT-GISEL
@@ -397,6 +397,14 @@ define <2 x i64> @popcount2x64(<2 x i64> %0) {
; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; BE-NEXT: ret
;
+; GISELO3-LABEL: popcount2x64:
+; GISELO3: // %bb.0: // %Entry
+; GISELO3-NEXT: cnt v0.16b, v0.16b
+; GISELO3-NEXT: uaddlp v0.8h, v0.16b
+; GISELO3-NEXT: uaddlp v0.4s, v0.8h
+; GISELO3-NEXT: uaddlp v0.2d, v0.4s
+; GISELO3-NEXT: ret
+;
; GISELO0-LABEL: popcount2x64:
; GISELO0: // %bb.0: // %Entry
; GISELO0-NEXT: cnt v0.16b, v0.16b
@@ -429,6 +437,13 @@ define <2 x i64> @popcount2x64(<2 x i64> %0) {
; SVE-GISEL-NEXT: uaddlp v0.4s, v0.8h
; SVE-GISEL-NEXT: uaddlp v0.2d, v0.4s
; SVE-GISEL-NEXT: ret
+; GISEL-O3-LABEL: popcount2x64:
+; GISEL-O3: // %bb.0: // %Entry
+; GISEL-O3-NEXT: cnt v0.16b, v0.16b
+; GISEL-O3-NEXT: uaddlp v0.8h, v0.16b
+; GISEL-O3-NEXT: uaddlp v0.4s, v0.8h
+; GISEL-O3-NEXT: uaddlp v0.2d, v0.4s
+; GISEL-O3-NEXT: ret
Entry:
%1 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
ret <2 x i64> %1
@@ -546,6 +561,13 @@ define <4 x i32> @popcount4x32(<4 x i32> %0) {
; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; BE-NEXT: ret
;
+; GISELO3-LABEL: popcount4x32:
+; GISELO3: // %bb.0: // %Entry
+; GISELO3-NEXT: cnt v0.16b, v0.16b
+; GISELO3-NEXT: uaddlp v0.8h, v0.16b
+; GISELO3-NEXT: uaddlp v0.4s, v0.8h
+; GISELO3-NEXT: ret
+;
; GISELO0-LABEL: popcount4x32:
; GISELO0: // %bb.0: // %Entry
; GISELO0-NEXT: cnt v0.16b, v0.16b
@@ -575,6 +597,12 @@ define <4 x i32> @popcount4x32(<4 x i32> %0) {
; SVE-GISEL-NEXT: uaddlp v0.8h, v0.16b
; SVE-GISEL-NEXT: uaddlp v0.4s, v0.8h
; SVE-GISEL-NEXT: ret
+; GISEL-O3-LABEL: popcount4x32:
+; GISEL-O3: // %bb.0: // %Entry
+; GISEL-O3-NEXT: cnt v0.16b, v0.16b
+; GISEL-O3-NEXT: uaddlp v0.8h, v0.16b
+; GISEL-O3-NEXT: uaddlp v0.4s, v0.8h
+; GISEL-O3-NEXT: ret
Entry:
%1 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
ret <4 x i32> %1
@@ -623,6 +651,13 @@ define <2 x i32> @popcount2x32(<2 x i32> %0) {
; BE-NEXT: rev64 v0.2s, v0.2s
; BE-NEXT: ret
;
+; GISELO3-LABEL: popcount2x32:
+; GISELO3: // %bb.0: // %Entry
+; GISELO3-NEXT: cnt v0.8b, v0.8b
+; GISELO3-NEXT: uaddlp v0.4h, v0.8b
+; GISELO3-NEXT: uaddlp v0.2s, v0.4h
+; GISELO3-NEXT: ret
+;
; GISELO0-LABEL: popcount2x32:
; GISELO0: // %bb.0: // %Entry
; GISELO0-NEXT: cnt v0.8b, v0.8b
@@ -652,6 +687,12 @@ define <2 x i32> @popcount2x32(<2 x i32> %0) {
; SVE-GISEL-NEXT: uaddlp v0.4h, v0.8b
; SVE-GISEL-NEXT: uaddlp v0.2s, v0.4h
; SVE-GISEL-NEXT: ret
+; GISEL-O3-LABEL: popcount2x32:
+; GISEL-O3: // %bb.0: // %Entry
+; GISEL-O3-NEXT: cnt v0.8b, v0.8b
+; GISEL-O3-NEXT: uaddlp v0.4h, v0.8b
+; GISEL-O3-NEXT: uaddlp v0.2s, v0.4h
+; GISEL-O3-NEXT: ret
Entry:
%1 = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %0)
ret <2 x i32> %1
diff --git a/llvm/test/CodeGen/AArch64/ptrauth-isel.ll b/llvm/test/CodeGen/AArch64/ptrauth-isel.ll
index 91e8be706ba38..df99341826d31 100644
--- a/llvm/test/CodeGen/AArch64/ptrauth-isel.ll
+++ b/llvm/test/CodeGen/AArch64/ptrauth-isel.ll
@@ -185,7 +185,7 @@ define i64 @blend_and_sign_same_bb(i64 %addr) {
; GISEL-NEXT: {{ $}}
; GISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; GISEL-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @discvar
- ; GISEL-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @discvar :: (dereferenceable load (s64) from @discvar)
+ ; GISEL-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @discvar :: (dereferenceable load (i64) from @discvar)
; GISEL-NEXT: [[MOVKXi:%[0-9]+]]:gpr64noip = MOVKXi [[LDRXui]], 42, 48
; GISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64noip = COPY [[LDRXui]]
; GISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 42, [[COPY1]], implicit-def dead $x16, implicit-def dead $x17
@@ -237,7 +237,7 @@ define i64 @blend_and_sign_different_bbs(i64 %addr, i64 %cond) {
; GISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; GISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; GISEL-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @discvar
- ; GISEL-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @discvar :: (dereferenceable load (s64) from @discvar)
+ ; GISEL-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @discvar :: (dereferenceable load (i64) from @discvar)
; GISEL-NEXT: [[MOVKXi:%[0-9]+]]:gpr64noip = MOVKXi [[LDRXui]], 42, 48
; GISEL-NEXT: CBZX [[COPY1]], %bb.3
; GISEL-NEXT: B %bb.2
>From a39176717aecdc532e3a0ebe2df8a3962deb5147 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Wed, 8 Apr 2026 09:02:14 +0100
Subject: [PATCH 11/30] Repair load pattern
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 098b86b195988..1b5920a7b6c06 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4434,6 +4434,7 @@ defm : LoadInsertPatterns<extloadi16, v8i16, v4i16, nxv8i16, i32,
LDRHui, LDURHi, LDRHroW, LDRHroX,
ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
defm : LoadInsertPatterns<load, v8i16, v4i16, nxv8i16, i16,
+ vec_ins_or_scal_vec, vec_ins_or_scal_vec,
LDRHui, LDURHi, LDRHroW, LDRHroX,
ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
defm : LoadInsertPatterns<load, v4i32, v2i32, nxv4i32, i32,
>From 97c454cc2c2da745069431652fefce46a72afdfc Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 31 Dec 2025 10:30:26 +0000
Subject: [PATCH 12/30] Merge should not force values onto GPR if the operands
are on FPR registers
---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 5 +-
llvm/test/CodeGen/AArch64/arm64-fp128.ll | 26 +-
llvm/test/CodeGen/AArch64/fcmp.ll | 68 +-
.../test/CodeGen/AArch64/fptosi-sat-scalar.ll | 53 +-
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 580 +++++++++---------
.../test/CodeGen/AArch64/fptoui-sat-scalar.ll | 37 +-
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 511 ++++++++-------
llvm/test/CodeGen/AArch64/phi.ll | 18 +-
8 files changed, 638 insertions(+), 660 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 3da5b3486e62d..5c2e7b7ce5988 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -1253,14 +1253,17 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
break;
}
- case TargetOpcode::G_UNMERGE_VALUES: {
+ case TargetOpcode::G_UNMERGE_VALUES:
// If the first operand belongs to a FPR register bank, then make sure that
// we preserve that.
if (OpRegBankIdx[0] != PMI_FirstGPR)
break;
+ [[fallthrough]];
+ case TargetOpcode::G_MERGE_VALUES: {
LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
// UNMERGE into scalars from a vector should always use FPR.
+ // MERGE into a vector should use FPR if the operands are already on FPR.
// Likewise if any of the uses are FP instructions.
if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
diff --git a/llvm/test/CodeGen/AArch64/arm64-fp128.ll b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
index c4f91c66fb9a6..42ff4bdfc1d3e 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
@@ -302,10 +302,8 @@ define fp128 @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: fcsel d0, d0, d1, ne
; CHECK-GI-NEXT: fcsel d1, d2, d3, ne
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
%val = select i1 %cond, fp128 %lhs, fp128 %rhs
ret fp128 %val
@@ -1156,18 +1154,14 @@ define <2 x fp128> @vec_select(<2 x i1> %cond, <2 x fp128> %lhs, <2 x fp128> %rh
; CHECK-GI-NEXT: fcsel d0, d1, d3, ne
; CHECK-GI-NEXT: fcsel d3, d5, d6, ne
; CHECK-GI-NEXT: tst w8, #0x1
-; CHECK-GI-NEXT: mov d1, v2.d[1]
-; CHECK-GI-NEXT: mov d5, v4.d[1]
-; CHECK-GI-NEXT: fcsel d2, d2, d4, ne
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: fmov x9, d2
-; CHECK-GI-NEXT: fcsel d2, d1, d5, ne
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d3
-; CHECK-GI-NEXT: mov v1.d[0], x9
-; CHECK-GI-NEXT: fmov x9, d2
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
+; CHECK-GI-NEXT: mov d5, v2.d[1]
+; CHECK-GI-NEXT: mov d6, v4.d[1]
+; CHECK-GI-NEXT: fcsel d1, d2, d4, ne
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
+; CHECK-GI-NEXT: fcsel d2, d5, d6, ne
+; CHECK-GI-NEXT: mov v0.d[1], v3.d[0]
+; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
; CHECK-GI-NEXT: ret
%val = select <2 x i1> %cond, <2 x fp128> %lhs, <2 x fp128> %rhs
ret <2 x fp128> %val
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index 2c76de454a39a..450a121d8b6a6 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -31,17 +31,15 @@ define fp128 @f128_fp128(fp128 %a, fp128 %b, fp128 %d, fp128 %e) {
; CHECK-GI-NEXT: .cfi_offset w30, -16
; CHECK-GI-NEXT: stp q3, q2, [sp] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q3, q2, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q3, q0, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload
-; CHECK-GI-NEXT: mov d0, v2.d[1]
-; CHECK-GI-NEXT: mov d1, v3.d[1]
-; CHECK-GI-NEXT: fcsel d2, d2, d3, mi
-; CHECK-GI-NEXT: fmov x8, d2
-; CHECK-GI-NEXT: fcsel d1, d0, d1, mi
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: mov d2, v3.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d3, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d2, mi
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
entry:
@@ -477,21 +475,17 @@ define <2 x fp128> @v2f128_fp128(<2 x fp128> %a, <2 x fp128> %b, <2 x fp128> %d,
; CHECK-GI-NEXT: mov d0, v2.d[1]
; CHECK-GI-NEXT: mov d1, v3.d[1]
; CHECK-GI-NEXT: fcsel d2, d2, d3, mi
-; CHECK-GI-NEXT: fmov x8, d2
; CHECK-GI-NEXT: fcsel d3, d0, d1, mi
-; CHECK-GI-NEXT: ldp q5, q0, [sp, #64] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: mov d4, v5.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d5, mi
-; CHECK-GI-NEXT: fmov x9, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d3
-; CHECK-GI-NEXT: fcsel d2, d1, d4, mi
-; CHECK-GI-NEXT: mov v1.d[0], x9
-; CHECK-GI-NEXT: fmov x9, d2
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
+; CHECK-GI-NEXT: mov d4, v0.d[1]
+; CHECK-GI-NEXT: mov d5, v1.d[1]
+; CHECK-GI-NEXT: fcsel d1, d0, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], v2.d[0]
+; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
+; CHECK-GI-NEXT: fcsel d2, d4, d5, mi
+; CHECK-GI-NEXT: mov v0.d[1], v3.d[0]
+; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
; CHECK-GI-NEXT: add sp, sp, #112
; CHECK-GI-NEXT: ret
entry:
@@ -574,29 +568,23 @@ define <3 x fp128> @v3f128_fp128(<3 x fp128> %a, <3 x fp128> %b, <3 x fp128> %d,
; CHECK-GI-NEXT: fcsel d4, d4, d5, mi
; CHECK-GI-NEXT: mov d2, v7.d[1]
; CHECK-GI-NEXT: mov d3, v6.d[1]
-; CHECK-GI-NEXT: fmov x8, d4
; CHECK-GI-NEXT: fcsel d5, d0, d1, mi
; CHECK-GI-NEXT: cmp w20, #0
-; CHECK-GI-NEXT: fcsel d1, d7, d6, mi
-; CHECK-GI-NEXT: ldp q7, q0, [sp, #128] // 32-byte Folded Reload
; CHECK-GI-NEXT: fcsel d3, d2, d3, mi
+; CHECK-GI-NEXT: ldp q2, q0, [sp, #128] // 32-byte Folded Reload
+; CHECK-GI-NEXT: fcsel d1, d7, d6, mi
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d6, v7.d[1]
-; CHECK-GI-NEXT: fcsel d7, d0, d7, mi
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: fmov x9, d7
-; CHECK-GI-NEXT: fcsel d4, d2, d6, mi
-; CHECK-GI-NEXT: mov v1.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d5
-; CHECK-GI-NEXT: mov v2.d[0], x9
-; CHECK-GI-NEXT: fmov x9, d3
-; CHECK-GI-NEXT: fmov x10, d4
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
-; CHECK-GI-NEXT: mov v2.d[1], x10
+; CHECK-GI-NEXT: mov d6, v0.d[1]
+; CHECK-GI-NEXT: mov d7, v2.d[1]
+; CHECK-GI-NEXT: fcsel d2, d0, d2, mi
+; CHECK-GI-NEXT: mov v0.d[0], v4.d[0]
+; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
+; CHECK-GI-NEXT: mov v2.d[0], v2.d[0]
+; CHECK-GI-NEXT: fcsel d4, d6, d7, mi
+; CHECK-GI-NEXT: mov v0.d[1], v5.d[0]
+; CHECK-GI-NEXT: mov v1.d[1], v3.d[0]
+; CHECK-GI-NEXT: mov v2.d[1], v4.d[0]
; CHECK-GI-NEXT: add sp, sp, #192
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
index 099a5732992d5..7d527f6b6464e 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
@@ -968,56 +968,51 @@ define i32 @test_signed_f128_i32(fp128 %f) {
;
; CHECK-GI-LABEL: test_signed_f128_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #64
-; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #32] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
+; CHECK-GI-NEXT: sub sp, sp, #80
+; CHECK-GI-NEXT: str d8, [sp, #48] // 8-byte Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: .cfi_offset b8, -24
-; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: .cfi_offset b10, -48
+; CHECK-GI-NEXT: .cfi_offset b8, -32
; CHECK-GI-NEXT: adrp x8, .LCPI30_2
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_2]
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: fcsel d10, d0, d1, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d2, x8
; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d2, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI30_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d8, [sp, #48] // 8-byte Reload
; CHECK-GI-NEXT: csel w0, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: add sp, sp, #64
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: add sp, sp, #80
; CHECK-GI-NEXT: ret
%x = call i32 @llvm.fptosi.sat.i32.f128(fp128 %f)
ret i32 %x
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 218e3ea1da3bc..5783a961e2161 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -517,57 +517,52 @@ define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v1f128_v1i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #64
-; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #32] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 64
+; CHECK-GI-NEXT: sub sp, sp, #80
+; CHECK-GI-NEXT: str d8, [sp, #48] // 8-byte Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: .cfi_offset b8, -24
-; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: .cfi_offset b10, -48
+; CHECK-GI-NEXT: .cfi_offset b8, -32
; CHECK-GI-NEXT: adrp x8, .LCPI14_2
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_2]
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fmov d1, x8
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: fcsel d10, d0, d1, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d2, x8
; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d2, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d8, [sp, #48] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: add sp, sp, #64
+; CHECK-GI-NEXT: add sp, sp, #80
; CHECK-GI-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f128.v1i32(<1 x fp128> %f)
ret <1 x i32> %x
@@ -641,95 +636,92 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: stp d11, d10, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
+; CHECK-GI-NEXT: sub sp, sp, #144
+; CHECK-GI-NEXT: str d10, [sp, #96] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #104] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #120] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 144
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: .cfi_offset b8, -40
-; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: .cfi_offset b10, -56
-; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: .cfi_offset b9, -40
+; CHECK-GI-NEXT: .cfi_offset b10, -48
; CHECK-GI-NEXT: adrp x8, .LCPI15_2
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
-; CHECK-GI-NEXT: str q2, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: str q2, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fmov d10, x8
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d11, d0, d10, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d9, x8
; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
-; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
-; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI15_0]
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d10, d0, d10, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #120] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #104] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #96] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #128
+; CHECK-GI-NEXT: add sp, sp, #144
; CHECK-GI-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x
@@ -822,126 +814,119 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v3f128_v3i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #160
-; CHECK-GI-NEXT: str d12, [sp, #80] // 8-byte Spill
-; CHECK-GI-NEXT: stp d11, d10, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x21, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
+; CHECK-GI-NEXT: sub sp, sp, #176
+; CHECK-GI-NEXT: str d10, [sp, #112] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x21, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #160] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 176
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: .cfi_offset b8, -40
; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: .cfi_offset b10, -56
-; CHECK-GI-NEXT: .cfi_offset b11, -64
-; CHECK-GI-NEXT: .cfi_offset b12, -80
+; CHECK-GI-NEXT: .cfi_offset b10, -64
; CHECK-GI-NEXT: adrp x8, .LCPI16_2
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_2]
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: str q2, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q2, [sp, #96] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
; CHECK-GI-NEXT: fmov d9, x8
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d11, d0, d9, gt
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI16_1
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI16_0]
-; CHECK-GI-NEXT: fcsel d1, d11, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d12
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d9, d0, d9, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d9, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr d12, [sp, #80] // 8-byte Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #112] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #128] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w21
-; CHECK-GI-NEXT: ldp x30, x21, [sp, #128] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #144] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: add sp, sp, #160
+; CHECK-GI-NEXT: add sp, sp, #176
; CHECK-GI-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x
@@ -1056,14 +1041,13 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v4f128_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #176
-; CHECK-GI-NEXT: str d12, [sp, #96] // 8-byte Spill
-; CHECK-GI-NEXT: stp d11, d10, [sp, #104] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #120] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #136] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #160] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 176
+; CHECK-GI-NEXT: sub sp, sp, #192
+; CHECK-GI-NEXT: str d10, [sp, #128] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #136] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #152] // 8-byte Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #160] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 192
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
@@ -1072,140 +1056,135 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-GI-NEXT: .cfi_offset b8, -48
; CHECK-GI-NEXT: .cfi_offset b9, -56
; CHECK-GI-NEXT: .cfi_offset b10, -64
-; CHECK-GI-NEXT: .cfi_offset b11, -72
-; CHECK-GI-NEXT: .cfi_offset b12, -80
; CHECK-GI-NEXT: adrp x8, .LCPI17_2
-; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q0, q1, [sp, #32] // 32-byte Folded Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_2]
-; CHECK-GI-NEXT: str q2, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: stp q1, q3, [sp, #64] // 32-byte Folded Spill
+; CHECK-GI-NEXT: str q2, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: stp q1, q3, [sp, #96] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
; CHECK-GI-NEXT: fmov d9, x8
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d11, d0, d9, gt
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI17_0]
-; CHECK-GI-NEXT: fcsel d1, d11, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w20, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d12
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q4, q1, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v4.d[1]
-; CHECK-GI-NEXT: fcsel d11, d4, d8, gt
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d12, d0, d9, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d12
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d12, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #96] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel w22, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d11, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: fcsel d9, d0, d9, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d11, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d9, d10, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: fmov s0, w20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #136] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #152] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #120] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d12, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #136] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #128] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w21
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #104] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w22
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: add sp, sp, #176
+; CHECK-GI-NEXT: add sp, sp, #192
; CHECK-GI-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x
@@ -5190,101 +5169,96 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: str d12, [sp, #64] // 8-byte Spill
-; CHECK-GI-NEXT: stp d11, d10, [sp, #72] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #88] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #104] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
+; CHECK-GI-NEXT: sub sp, sp, #160
+; CHECK-GI-NEXT: stp d11, d10, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #128] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -24
-; CHECK-GI-NEXT: .cfi_offset b8, -32
-; CHECK-GI-NEXT: .cfi_offset b9, -40
-; CHECK-GI-NEXT: .cfi_offset b10, -48
-; CHECK-GI-NEXT: .cfi_offset b11, -56
-; CHECK-GI-NEXT: .cfi_offset b12, -64
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: .cfi_offset b8, -40
+; CHECK-GI-NEXT: .cfi_offset b9, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -56
+; CHECK-GI-NEXT: .cfi_offset b11, -64
; CHECK-GI-NEXT: adrp x8, .LCPI86_1
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
-; CHECK-GI-NEXT: str q2, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: str q2, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x8, #8521215115264 // =0x7c000000000
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fmov d10, x8
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d11, d0, d10, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d9, x8
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
-; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: mov x8, #280925220896768 // =0xff8000000000
-; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: movk x8, #17391, lsl #48
-; CHECK-GI-NEXT: fmov d12, x8
+; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: fmov d10, x8
; CHECK-GI-NEXT: mov x8, #-264432546480129 // =0xffff0f7fffffffff
; CHECK-GI-NEXT: movk x8, #17360, lsl #48
-; CHECK-GI-NEXT: fcsel d0, d9, d12, mi
-; CHECK-GI-NEXT: fmov d9, x8
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d11, x8
+; CHECK-GI-NEXT: fcsel d0, d0, d10, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d11, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfdi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel x20, xzr, x19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d8, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d8
-; CHECK-GI-NEXT: fcsel d10, d0, d10, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d8, d12, mi
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d10, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d11, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixtfdi
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: fmov d0, x20
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #104] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #128] // 8-byte Reload
; CHECK-GI-NEXT: csel x8, xzr, x19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #88] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d12, [sp, #64] // 8-byte Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #72] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #96] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: add sp, sp, #128
+; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
%x = call <2 x i64> @llvm.fptosi.sat.v2f128.v2i64(<2 x fp128> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
index 9c9f91ec26008..038ac9f97e6ea 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
@@ -784,43 +784,38 @@ define i32 @test_unsigned_f128_i32(fp128 %f) {
; CHECK-GI-LABEL: test_unsigned_f128_i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str d8, [sp, #32] // 8-byte Spill
; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
; CHECK-GI-NEXT: .cfi_offset w30, -8
; CHECK-GI-NEXT: .cfi_offset b8, -16
-; CHECK-GI-NEXT: .cfi_offset b9, -24
-; CHECK-GI-NEXT: .cfi_offset b10, -32
; CHECK-GI-NEXT: adrp x8, .LCPI30_2
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_2]
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI30_0
; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
-; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
-; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: ldr d8, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: b __fixunstfsi
%x = call i32 @llvm.fptoui.sat.i32.f128(fp128 %f)
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index e41a0c4918803..ead181d4a86a0 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -474,45 +474,40 @@ define <1 x i32> @test_unsigned_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-GI-LABEL: test_unsigned_v1f128_v1i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str d10, [sp, #16] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str d8, [sp, #32] // 8-byte Spill
; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
; CHECK-GI-NEXT: .cfi_offset w30, -8
; CHECK-GI-NEXT: .cfi_offset b8, -16
-; CHECK-GI-NEXT: .cfi_offset b9, -24
-; CHECK-GI-NEXT: .cfi_offset b10, -32
; CHECK-GI-NEXT: adrp x8, .LCPI14_2
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_2]
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI14_1
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d1, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
-; CHECK-GI-NEXT: fmov s0, w0
; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
-; CHECK-GI-NEXT: ldr d10, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: ldr d8, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: fmov s0, w0
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
%x = call <1 x i32> @llvm.fptoui.sat.v1f128.v1i32(<1 x fp128> %f)
@@ -571,77 +566,70 @@ define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #96
-; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
+; CHECK-GI-NEXT: sub sp, sp, #112
+; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w30, -16
; CHECK-GI-NEXT: .cfi_offset b8, -24
; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: .cfi_offset b10, -40
-; CHECK-GI-NEXT: .cfi_offset b11, -48
; CHECK-GI-NEXT: adrp x8, .LCPI15_2
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
-; CHECK-GI-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q2, q1, [sp, #48] // 32-byte Folded Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
-; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI15_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #80
+; CHECK-GI-NEXT: add sp, sp, #112
; CHECK-GI-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x
@@ -712,101 +700,94 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v3f128_v3i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: stp d11, d10, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
+; CHECK-GI-NEXT: sub sp, sp, #144
+; CHECK-GI-NEXT: stp d9, d8, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #112] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 144
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: .cfi_offset b8, -40
; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: .cfi_offset b10, -56
-; CHECK-GI-NEXT: .cfi_offset b11, -64
; CHECK-GI-NEXT: adrp x8, .LCPI16_2
-; CHECK-GI-NEXT: stp q1, q0, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_2]
-; CHECK-GI-NEXT: stp q1, q2, [sp, #32] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q1, q2, [sp, #64] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI16_1
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI16_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q3, q1, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v3.d[1]
-; CHECK-GI-NEXT: fcsel d10, d3, d8, gt
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: mov w20, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #112] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w0
-; CHECK-GI-NEXT: add sp, sp, #128
+; CHECK-GI-NEXT: add sp, sp, #144
; CHECK-GI-NEXT: ret
%x = call <3 x i32> @llvm.fptoui.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x
@@ -895,128 +876,123 @@ define <4 x i32> @test_unsigned_v4f128_v4i32(<4 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v4f128_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #144
-; CHECK-GI-NEXT: stp d11, d10, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x21, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 144
+; CHECK-GI-NEXT: sub sp, sp, #160
+; CHECK-GI-NEXT: stp d9, d8, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x21, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: .cfi_offset b8, -40
; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: .cfi_offset b10, -56
-; CHECK-GI-NEXT: .cfi_offset b11, -64
; CHECK-GI-NEXT: adrp x8, .LCPI17_2
-; CHECK-GI-NEXT: stp q1, q2, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q1, q2, [sp, #32] // 32-byte Folded Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_2]
-; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: str q3, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: str q3, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #96] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI17_1
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: fcsel d0, d9, d8, mi
; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI17_0]
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: mov w20, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: mov w21, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldp q4, q1, [sp, #32] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v4.d[1]
-; CHECK-GI-NEXT: fcsel d10, d4, d8, gt
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d11, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d11
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d11, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w21
-; CHECK-GI-NEXT: ldp x30, x21, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #128] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[3], w0
-; CHECK-GI-NEXT: add sp, sp, #128
+; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
%x = call <4 x i32> @llvm.fptoui.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x
@@ -4177,6 +4153,7 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
<<<<<<< HEAD
+<<<<<<< HEAD
; CHECK-GI-NEXT: sub sp, sp, #80
; CHECK-GI-NEXT: stp x30, x23, [sp, #32] // 16-byte Folded Spill
; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
@@ -4195,6 +4172,19 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
>>>>>>> 25bc4b2b4034 (Update tests)
+||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
+; CHECK-GI-NEXT: sub sp, sp, #96
+; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
+=======
+; CHECK-GI-NEXT: sub sp, sp, #128
+; CHECK-GI-NEXT: str d10, [sp, #80] // 8-byte Spill
+; CHECK-GI-NEXT: stp d9, d8, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x30, x19, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
+>>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
; CHECK-GI-NEXT: .cfi_offset w19, -8
<<<<<<< HEAD
; CHECK-GI-NEXT: .cfi_offset w20, -16
@@ -4219,53 +4209,71 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: .cfi_offset w30, -16
; CHECK-GI-NEXT: .cfi_offset b8, -24
; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: .cfi_offset b10, -40
-; CHECK-GI-NEXT: .cfi_offset b11, -48
+; CHECK-GI-NEXT: .cfi_offset b10, -48
; CHECK-GI-NEXT: adrp x8, .LCPI86_1
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
-; CHECK-GI-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q2, q1, [sp, #48] // 32-byte Folded Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
>>>>>>> 25bc4b2b4034 (Update tests)
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d9, d1, d8, gt
-; CHECK-GI-NEXT: fcsel d10, d0, d8, gt
-; CHECK-GI-NEXT: fmov x8, d9
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
-; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: mov x8, #281200098803712 // =0xffc000000000
-; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: movk x8, #17391, lsl #48
-; CHECK-GI-NEXT: fmov d11, x8
+; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: fmov d9, x8
; CHECK-GI-NEXT: mov x8, #-264157668573185 // =0xffff0fbfffffffff
; CHECK-GI-NEXT: movk x8, #17360, lsl #48
-; CHECK-GI-NEXT: fcsel d0, d9, d11, mi
-; CHECK-GI-NEXT: fmov d9, x8
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: fcsel d1, d10, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: fmov d10, x8
+; CHECK-GI-NEXT: fcsel d0, d0, d9, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfdi
+<<<<<<< HEAD
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
+=======
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
+>>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: bl __gttf2
<<<<<<< HEAD
+<<<<<<< HEAD
; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload
||||||| parent of 25bc4b2b4034 (Update tests)
; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
=======
+||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
+=======
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+>>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+<<<<<<< HEAD
>>>>>>> 25bc4b2b4034 (Update tests)
; CHECK-GI-NEXT: cmp w0, #0
<<<<<<< HEAD
@@ -4293,17 +4301,29 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: fmov x8, d8
; CHECK-GI-NEXT: mov v0.d[1], x8
>>>>>>> 25bc4b2b4034 (Update tests)
-; CHECK-GI-NEXT: bl __lttf2
+||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d10, d11, mi
-; CHECK-GI-NEXT: fcsel d1, d8, d9, mi
-; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d10
+; CHECK-GI-NEXT: fcsel d8, d0, d8, gt
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d1
+; CHECK-GI-NEXT: fmov x8, d8
; CHECK-GI-NEXT: mov v0.d[1], x8
+=======
+>>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
+; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
+; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: fcsel d0, d0, d9, mi
+; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
+; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfdi
; CHECK-GI-NEXT: fmov d0, x19
<<<<<<< HEAD
+<<<<<<< HEAD
; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp x30, x23, [sp, #32] // 16-byte Folded Reload
@@ -4316,8 +4336,23 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
>>>>>>> 25bc4b2b4034 (Update tests)
+||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
+=======
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp d9, d8, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr d10, [sp, #80] // 8-byte Reload
+>>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
; CHECK-GI-NEXT: mov v0.d[1], x0
+<<<<<<< HEAD
; CHECK-GI-NEXT: add sp, sp, #80
+||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
+; CHECK-GI-NEXT: add sp, sp, #96
+=======
+; CHECK-GI-NEXT: add sp, sp, #128
+>>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
; CHECK-GI-NEXT: ret
%x = call <2 x i64> @llvm.fptoui.sat.v2f128.v2i64(<2 x fp128> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/phi.ll b/llvm/test/CodeGen/AArch64/phi.ll
index 02842c04bf7bf..a7ca9ed8a8165 100644
--- a/llvm/test/CodeGen/AArch64/phi.ll
+++ b/llvm/test/CodeGen/AArch64/phi.ll
@@ -274,10 +274,8 @@ define fp128 @tf128(i1 %c, ptr %p, fp128 %a, fp128 %b) {
; CHECK-GI-NEXT: .LBB9_2:
; CHECK-GI-NEXT: mov d2, v1.d[1]
; CHECK-GI-NEXT: .LBB9_3: // %e
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d2
-; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v0.d[0], v1.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v2.d[0]
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -1303,14 +1301,10 @@ define <2 x fp128> @tv2f128(i1 %c, ptr %p, <2 x fp128> %a, <2 x fp128> %b) {
; CHECK-GI-NEXT: mov d4, v3.d[1]
; CHECK-GI-NEXT: mov d5, v2.d[1]
; CHECK-GI-NEXT: .LBB44_3: // %e
-; CHECK-GI-NEXT: fmov x8, d2
-; CHECK-GI-NEXT: fmov x9, d3
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov v1.d[0], x9
-; CHECK-GI-NEXT: fmov x8, d5
-; CHECK-GI-NEXT: fmov x9, d4
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: mov v1.d[1], x9
+; CHECK-GI-NEXT: mov v0.d[0], v2.d[0]
+; CHECK-GI-NEXT: mov v1.d[0], v3.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], v5.d[0]
+; CHECK-GI-NEXT: mov v1.d[1], v4.d[0]
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
>From 9ed5bcceb87acfecee738fab80f524eb864e2ca2 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 2 Feb 2026 11:24:28 +0000
Subject: [PATCH 13/30] Modify type constructors to use wrapper constructor to
allow scalar fallback in AArch64
---
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 8 ++++----
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp | 11 ++++++-----
.../AArch64/GISel/AArch64InstructionSelector.cpp | 4 ++--
.../lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +-
.../AArch64/GISel/AArch64PostLegalizerCombiner.cpp | 4 ++--
.../AArch64/GISel/AArch64PostLegalizerLowering.cpp | 8 ++++----
.../AArch64/GISel/AArch64PreLegalizerCombiner.cpp | 2 +-
7 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 923bea3379913..5bb15b7fee954 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18966,14 +18966,14 @@ LLT AArch64TargetLowering::getOptimalMemOpLLT(
// NEON dup + scalar store works for any alignment and is efficient.
if (CanUseNEON && Op.isMemset() && !IsSmallZeroMemset &&
AlignmentIsAcceptable(MVT::v16i8, Align(1)))
- return LLT::fixed_vector(2, LLT::integer(64));
+ return LLT::fixed_vector(2, LLT::buildInteger(64));
if (CanUseFP && !IsSmallZeroMemset &&
AlignmentIsAcceptable(MVT::f128, Align(16)))
- return LLT::floatIEEE(128);
+ return LLT::buildFloatingIEEE(128);
if (Op.size() >= 8 && AlignmentIsAcceptable(MVT::i64, Align(8)))
- return LLT::integer(64);
+ return LLT::buildInteger(64);
if (Op.size() >= 4 && AlignmentIsAcceptable(MVT::i32, Align(4)))
- return LLT::integer(32);
+ return LLT::buildInteger(32);
return LLT();
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index f4229235e9743..dcbfe01d8b337 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -259,7 +259,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
ISD::ArgFlagsTy Flags) override {
MachineFunction &MF = MIRBuilder.getMF();
LLT p0 = LLT::pointer(0, 64);
- LLT s64 = LLT::integer(64);
+ LLT s64 = LLT::buildInteger(64);
if (IsTailCall) {
assert(!Flags.isByVal() && "byval unhandled with tail calls");
@@ -446,7 +446,7 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
auto &Flags = CurArgInfo.Flags[0];
if (MRI.getType(CurVReg).getSizeInBits() == TypeSize::getFixed(1) &&
!Flags.isSExt() && !Flags.isZExt()) {
- CurVReg = MIRBuilder.buildZExt(LLT::integer(8), CurVReg).getReg(0);
+ CurVReg = MIRBuilder.buildZExt(LLT::buildInteger(8), CurVReg).getReg(0);
} else if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) ==
1) {
// Some types will need extending as specified by the CC.
@@ -629,7 +629,7 @@ void AArch64CallLowering::saveVarArgRegisters(
bool IsWin64CC = Subtarget.isCallingConvWin64(CCInfo.getCallingConv(),
MF.getFunction().isVarArg());
const LLT p0 = LLT::pointer(0, 64);
- const LLT s64 = LLT::integer(64);
+ const LLT s64 = LLT::buildInteger(64);
unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
unsigned NumVariadicGPRArgRegs = GPRArgRegs.size() - FirstVariadicGPR + 1;
@@ -753,7 +753,8 @@ bool AArch64CallLowering::lowerFormalArguments(
if (!Flags.isZExt() && !Flags.isSExt()) {
// Lower i1 argument as i8, and insert AssertZExt + Trunc later.
Register OrigReg = OrigArg.Regs[0];
- Register WideReg = MRI.createGenericVirtualRegister(LLT::integer(8));
+ Register WideReg =
+ MRI.createGenericVirtualRegister(LLT::buildInteger(8));
OrigArg.Regs[0] = WideReg;
BoolArgs.push_back({OrigReg, WideReg});
}
@@ -1359,7 +1360,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// We cannot use a ZExt ArgInfo flag here, because it will
// zero-extend the argument to i32 instead of just i8.
OutArg.Regs[0] =
- MIRBuilder.buildZExt(LLT::integer(8), OutArg.Regs[0]).getReg(0);
+ MIRBuilder.buildZExt(LLT::buildInteger(8), OutArg.Regs[0]).getReg(0);
LLVMContext &Ctx = MF.getFunction().getContext();
OutArg.Ty = Type::getInt8Ty(Ctx);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index dbaa056bb7b58..4308b7ae71335 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2258,8 +2258,8 @@ bool AArch64InstructionSelector::convertPtrAddToAdd(
return false;
const LLT CastPtrTy = PtrTy.isVector()
- ? LLT::fixed_vector(2, LLT::integer(64))
- : LLT::integer(64);
+ ? LLT::fixed_vector(2, LLT::buildInteger(64))
+ : LLT::buildInteger(64);
auto PtrToInt = MIB.buildPtrToInt(CastPtrTy, AddOp1Reg);
// Set regbanks on the registers.
if (PtrTy.isVector())
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index ccac85e854636..6355a81de64ed 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -2412,7 +2412,7 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
bool AArch64LegalizerInfo::legalizeAtomicCmpxchg128(
MachineInstr &MI, MachineRegisterInfo &MRI, LegalizerHelper &Helper) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
- LLT i64 = LLT::integer(64);
+ LLT i64 = LLT::buildInteger(64);
auto Addr = MI.getOperand(1).getReg();
auto DesiredI = MIRBuilder.buildUnmerge({i64, i64}, MI.getOperand(2));
auto NewI = MIRBuilder.buildUnmerge({i64, i64}, MI.getOperand(3));
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index ba0d9b542d1e9..a4572c6efd55f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -222,7 +222,7 @@ bool matchAArch64MulConstCombine(
return false;
ApplyFn = [=](MachineIRBuilder &B, Register DstReg) {
- auto Shift = B.buildConstant(LLT::integer(64), ShiftAmt);
+ auto Shift = B.buildConstant(LLT::buildInteger(64), ShiftAmt);
auto ShiftedVal = B.buildShl(Ty, LHS, Shift);
Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS;
@@ -238,7 +238,7 @@ bool matchAArch64MulConstCombine(
// Shift the result.
if (TrailingZeroes) {
B.buildShl(DstReg, Res,
- B.buildConstant(LLT::integer(64), TrailingZeroes));
+ B.buildConstant(LLT::buildInteger(64), TrailingZeroes));
return;
}
B.buildCopy(DstReg, Res.getReg(0));
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 263c1e58fe6f3..d282bf202e2b7 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -556,9 +556,9 @@ void applyINS(MachineInstr &MI, MachineRegisterInfo &MRI,
Register DstVec, SrcVec;
int DstLane, SrcLane;
std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo;
- auto SrcCst = Builder.buildConstant(LLT::integer(64), SrcLane);
+ auto SrcCst = Builder.buildConstant(LLT::buildInteger(64), SrcLane);
auto Extract = Builder.buildExtractVectorElement(ScalarTy, SrcVec, SrcCst);
- auto DstCst = Builder.buildConstant(LLT::integer(64), DstLane);
+ auto DstCst = Builder.buildConstant(LLT::buildInteger(64), DstLane);
Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst);
MI.eraseFromParent();
}
@@ -781,7 +781,7 @@ void applyStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI,
auto *Merge = getOpcodeDef<GMerge>(ValReg, MRI);
auto BV =
- MIB.buildBuildVector(LLT::fixed_vector(2, LLT::integer(64)),
+ MIB.buildBuildVector(LLT::fixed_vector(2, LLT::buildInteger(64)),
{Merge->getSourceReg(0), Merge->getSourceReg(1)})
.getReg(0);
MI.getOperand(0).setReg(BV);
@@ -1185,7 +1185,7 @@ void applyLowerBuildToInsertVecElt(MachineInstr &MI, MachineRegisterInfo &MRI,
Register SrcReg = GBuildVec->getSourceReg(I);
if (mi_match(SrcReg, MRI, m_GImplicitDef()))
continue;
- auto IdxReg = B.buildConstant(LLT::integer(64), I);
+ auto IdxReg = B.buildConstant(LLT::buildInteger(64), I);
DstReg =
B.buildInsertVectorElement(DstTy, DstReg, SrcReg, IdxReg).getReg(0);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index abfac82ce5a86..29fef5f64f574 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -502,7 +502,7 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
unsigned MidScalarSize = MainTy.getScalarSizeInBits() * 2;
LLT MidScalarLLT =
MainTy.changeElementSize(MidScalarSize).changeElementCount(1);
- Register ZeroReg = B.buildConstant(LLT::integer(64), 0).getReg(0);
+ Register ZeroReg = B.buildConstant(LLT::buildInteger(64), 0).getReg(0);
for (unsigned I = 0; I < WorkingRegisters.size(); I++) {
// If the number of elements is too small to build an instruction, extend
// its size before applying addlv
>From 83200bc8486805554be1f17d9f05fe280bc6f911 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 21 Jan 2026 11:13:13 +0000
Subject: [PATCH 14/30] Update tests
---
.../AArch64/GlobalISel/combine-unmerge.mir | 8 +-
.../AArch64/GlobalISel/legalize-fcopysign.mir | 10 +-
.../GlobalISel/legalize-fp-arith-fp16.mir | 9 +-
.../AMDGPU/GlobalISel/legalize-fcopysign.mir | 216 +++++++++---------
.../MIR/AArch64/deactivation-symbols.mir | 2 +-
.../print-parse-overloaded-intrinsics.mir | 8 +-
.../GlobalISel/LegalizerHelperTest.cpp | 52 ++---
.../CodeGen/GlobalISel/LegalizerTest.cpp | 8 +-
8 files changed, 155 insertions(+), 158 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
index e5e6517f6391f..f427f8648a301 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
@@ -266,10 +266,10 @@ name: test_combine_unmerge_fpcst
body: |
bb.1:
; CHECK-LABEL: name: test_combine_unmerge_fpcst
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4000
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4400
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK-NEXT: $h0 = COPY [[C]](s16)
; CHECK-NEXT: $h1 = COPY [[C1]](s16)
; CHECK-NEXT: $h2 = COPY [[C2]](s16)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
index 4f036d275b24d..3c1a6822e7428 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
@@ -22,9 +22,8 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i32>) = disjoint G_OR [[AND]], [[AND1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[OR]](<2 x i32>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](<2 x s32>)
; CHECK-NEXT: %fcopysign:_(s32) = COPY [[UV]](s32)
; CHECK-NEXT: $s0 = COPY %fcopysign(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
@@ -55,9 +54,8 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C1]](i64), [[C1]](i64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR3]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i64>) = disjoint G_OR [[AND]], [[AND1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[OR]](<2 x i64>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = disjoint G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[OR]](<2 x s64>)
; CHECK-NEXT: %fcopysign:_(s64) = COPY [[UV]](s64)
; CHECK-NEXT: $d0 = COPY %fcopysign(s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
index e3c0d4989fc2c..42538d58c87bf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
@@ -150,11 +150,10 @@ body: |
; NO-FP16: liveins: $h0
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %x:_(s16) = COPY $h0
- ; NO-FP16-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT %x(s16)
- ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -32768
- ; NO-FP16-NEXT: [[XOR:%[0-9]+]]:_(i32) = G_XOR [[ANYEXT]], [[C]]
- ; NO-FP16-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[XOR]](i32)
- ; NO-FP16-NEXT: %op:_(s16) = G_BITCAST [[TRUNC]](i16)
+ ; NO-FP16-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %x(s16)
+ ; NO-FP16-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; NO-FP16-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ANYEXT]], [[C]]
+ ; NO-FP16-NEXT: %op:_(s16) = G_TRUNC [[XOR]](s32)
; NO-FP16-NEXT: $h0 = COPY %op(s16)
; NO-FP16-NEXT: RET_ReallyLR implicit $h0
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
index 60ccd20c095cd..1a7cad7886635 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
@@ -22,8 +22,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: %4:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %4(s16)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s16
@@ -37,8 +37,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: %4:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %4(s16)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s16
@@ -52,8 +52,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: %4:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %4(s16)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -79,8 +79,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY %2(s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; VI-LABEL: name: test_copysign_s32_s32
; VI: liveins: $vgpr0, $vgpr1
@@ -91,8 +91,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY %2(s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; GFX9-LABEL: name: test_copysign_s32_s32
; GFX9: liveins: $vgpr0, $vgpr1
@@ -103,8 +103,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY %2(s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_FCOPYSIGN %0, %1
@@ -126,8 +126,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; SI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; VI-LABEL: name: test_copysign_s64_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -138,8 +138,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; GFX9-LABEL: name: test_copysign_s64_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -150,8 +150,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_FCOPYSIGN %0, %1
@@ -176,8 +176,8 @@ body: |
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; VI-LABEL: name: test_copysign_s64_s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2
@@ -191,8 +191,8 @@ body: |
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; GFX9-LABEL: name: test_copysign_s64_s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
@@ -206,8 +206,8 @@ body: |
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_FCOPYSIGN %0, %1
@@ -232,8 +232,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; SI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY %2(s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; VI-LABEL: name: test_copysign_s32_s64
; VI: liveins: $vgpr0, $vgpr1_vgpr2
@@ -247,8 +247,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; VI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY %2(s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; GFX9-LABEL: name: test_copysign_s32_s64
; GFX9: liveins: $vgpr0, $vgpr1_vgpr2
@@ -262,8 +262,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; GFX9-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY %2(s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = COPY $vgpr1_vgpr2
%2:_(s32) = G_FCOPYSIGN %0, %1
@@ -289,8 +289,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s32
@@ -306,8 +306,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s32
@@ -323,8 +323,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -353,8 +353,8 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: %3:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0 = COPY %3(s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; VI-LABEL: name: test_copysign_s32_s16
; VI: liveins: $vgpr0, $vgpr1
@@ -369,8 +369,8 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: %3:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0 = COPY %3(s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; GFX9-LABEL: name: test_copysign_s32_s16
; GFX9: liveins: $vgpr0, $vgpr1
@@ -385,8 +385,8 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: %3:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0 = COPY %3(s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
@@ -414,8 +414,8 @@ body: |
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: %3:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY %3(s64)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; VI-LABEL: name: test_copysign_s64_s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2
@@ -431,8 +431,8 @@ body: |
; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: %3:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY %3(s64)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
;
; GFX9-LABEL: name: test_copysign_s64_s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
@@ -448,8 +448,8 @@ body: |
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: %3:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %3(s64)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
@@ -476,8 +476,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s64
@@ -493,8 +493,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s64
@@ -510,8 +510,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = COPY $vgpr1_vgpr2
@@ -543,8 +543,8 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BITCAST1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BITCAST]]
- ; SI-NEXT: %2:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY %2(<2 x s16>)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR2]](<2 x s16>)
;
; VI-LABEL: name: test_copysign_v2s16_v2s16
; VI: liveins: $vgpr0, $vgpr1
@@ -562,8 +562,8 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BITCAST1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BITCAST]]
- ; VI-NEXT: %2:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY %2(<2 x s16>)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR2]](<2 x s16>)
;
; GFX9-LABEL: name: test_copysign_v2s16_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
@@ -576,8 +576,8 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C1]](s16)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: %2:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY %2(<2 x s16>)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_FCOPYSIGN %0, %1
@@ -601,8 +601,8 @@ body: |
; SI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; SI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
;
; VI-LABEL: name: test_copysign_v2s32_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -615,8 +615,8 @@ body: |
; VI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; VI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
;
; GFX9-LABEL: name: test_copysign_v2s32_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -629,8 +629,8 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = G_FCOPYSIGN %0, %1
@@ -656,9 +656,9 @@ body: |
; SI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
- ; SI-NEXT: %13:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: %14:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %13(s64), %14(s64)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; VI-LABEL: name: test_copysign_v2s64_v2s64
@@ -674,9 +674,9 @@ body: |
; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
- ; VI-NEXT: %13:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: %14:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %13(s64), %14(s64)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; GFX9-LABEL: name: test_copysign_v2s64_v2s64
@@ -692,9 +692,9 @@ body: |
; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
- ; GFX9-NEXT: %13:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: %14:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %13(s64), %14(s64)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
@@ -727,9 +727,9 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[C2]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; SI-NEXT: %17:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: %18:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %17(s64), %18(s64)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; VI-LABEL: name: test_copysign_v2s64_v2s32
@@ -751,9 +751,9 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[C2]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; VI-NEXT: %17:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: %18:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %17(s64), %18(s64)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; GFX9-LABEL: name: test_copysign_v2s64_v2s32
@@ -775,9 +775,9 @@ body: |
; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; GFX9-NEXT: %17:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: %18:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %17(s64), %18(s64)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s32>) = COPY $vgpr4_vgpr5
@@ -811,8 +811,8 @@ body: |
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64)
; SI-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; SI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
;
; VI-LABEL: name: test_copysign_v2s32_v2s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
@@ -833,8 +833,8 @@ body: |
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64)
; VI-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; VI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
;
; GFX9-LABEL: name: test_copysign_v2s32_v2s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
@@ -855,8 +855,8 @@ body: |
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64)
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
%2:_(<2 x s32>) = G_FCOPYSIGN %0, %1
@@ -878,8 +878,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: %2:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY %2(s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; VI-LABEL: name: test_copysign_s32_s32_flagss
; VI: liveins: $vgpr0, $vgpr1
@@ -890,8 +890,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: %2:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY %2(s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; GFX9-LABEL: name: test_copysign_s32_s32_flagss
; GFX9: liveins: $vgpr0, $vgpr1
@@ -902,8 +902,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: %2:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY %2(s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = nnan G_FCOPYSIGN %0, %1
@@ -929,8 +929,8 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: %3:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0 = COPY %3(s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; VI-LABEL: name: test_copysign_s32_s16_flags
; VI: liveins: $vgpr0, $vgpr1
@@ -945,8 +945,8 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: %3:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0 = COPY %3(s32)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
; GFX9-LABEL: name: test_copysign_s32_s16_flags
; GFX9: liveins: $vgpr0, $vgpr1
@@ -961,8 +961,8 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: %3:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0 = COPY %3(s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
@@ -990,8 +990,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: %3:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s32_flags
@@ -1007,8 +1007,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: %3:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s32_flags
@@ -1024,8 +1024,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: %3:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
diff --git a/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir b/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
index 6542508ede116..f99d41e98f06c 100644
--- a/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
@@ -5,7 +5,7 @@
@ds = external global i8
define i64 @pauth_sign_zero(i64 %p) {
- ; CHECK: G_INTRINSIC intrinsic(@llvm.ptrauth.sign), %0(s64), 0, %2(s64), deactivation-symbol @ds
+ ; CHECK: G_INTRINSIC intrinsic(@llvm.ptrauth.sign), %0(i64), 0, %2(i64), deactivation-symbol @ds
%signed = call i64 @llvm.ptrauth.sign(i64 %p, i32 0, i64 0) [ "deactivation-symbol"(ptr @ds) ]
ret i64 %signed
}
diff --git a/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir b/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
index 7f4ed054f78f2..953a13389f9d8 100644
--- a/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
@@ -10,10 +10,10 @@
define i32 @int_aarch64_sdiv(i32 %a, i32 %b) nounwind readnone ssp {
; CHECK-LABEL: name: int_aarch64_sdiv
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv), [[COPY]](s32), [[COPY1]](s32)
- ; CHECK: $w0 = COPY [[INT]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
+ ; CHECK: [[INT:%[0-9]+]]:_(i32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv), [[COPY]](i32), [[COPY1]](i32)
+ ; CHECK: $w0 = COPY [[INT]](i32)
; CHECK: RET_ReallyLR implicit $w0
entry:
%sdiv = call i32 @llvm.aarch64.sdiv.i32(i32 %a, i32 %b)
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
index 95497766e74f4..21f59753fb478 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
@@ -1607,9 +1607,9 @@ TEST_F(AArch64GISelMITest, LowerFNEG) {
auto CheckStr = R"(
CHECK: [[FADD:%[0-9]+]]:_(s64) = nsz G_FADD %0:_, %1:_
- CHECK: [[CONST0:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
+ CHECK: [[CONST0:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
CHECK: [[FSUB0:%[0-9]+]]:_(s64) = G_XOR [[FADD]]:_, [[CONST0]]:_
- CHECK: [[CONST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
+ CHECK: [[CONST1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
CHECK: [[FSUB1:%[0-9]+]]:_(s64) = G_XOR %0:_, [[CONST1]]:_
)";
@@ -1673,32 +1673,32 @@ TEST_F(AArch64GISelMITest, LowerMinMax) {
Helper.lower(*UMaxV, 0, v2s32));
auto CheckStr = R"(
- CHECK: [[CMP0:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), %0:_(s64), %1:_
- CHECK: [[SMIN:%[0-9]+]]:_(s64) = G_SELECT [[CMP0]]:_(s1), %0:_, %1:_
+ CHECK: [[CMP0:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), %0:_(s64), %1:_
+ CHECK: [[SMIN:%[0-9]+]]:_(s64) = G_SELECT [[CMP0]]:_(i1), %0:_, %1:_
- CHECK: [[CMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), %0:_(s64), %1:_
- CHECK: [[SMAX:%[0-9]+]]:_(s64) = G_SELECT [[CMP1]]:_(s1), %0:_, %1:_
+ CHECK: [[CMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(sgt), %0:_(s64), %1:_
+ CHECK: [[SMAX:%[0-9]+]]:_(s64) = G_SELECT [[CMP1]]:_(i1), %0:_, %1:_
- CHECK: [[CMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), %0:_(s64), %1:_
- CHECK: [[UMIN:%[0-9]+]]:_(s64) = G_SELECT [[CMP2]]:_(s1), %0:_, %1:_
+ CHECK: [[CMP2:%[0-9]+]]:_(i1) = G_ICMP intpred(ult), %0:_(s64), %1:_
+ CHECK: [[UMIN:%[0-9]+]]:_(s64) = G_SELECT [[CMP2]]:_(i1), %0:_, %1:_
- CHECK: [[CMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), %0:_(s64), %1:_
- CHECK: [[UMAX:%[0-9]+]]:_(s64) = G_SELECT [[CMP3]]:_(s1), %0:_, %1:_
+ CHECK: [[CMP3:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), %0:_(s64), %1:_
+ CHECK: [[UMAX:%[0-9]+]]:_(s64) = G_SELECT [[CMP3]]:_(i1), %0:_, %1:_
CHECK: [[VEC0:%[0-9]+]]:_(<2 x s32>) = G_BITCAST %0:_(s64)
CHECK: [[VEC1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST %1:_(s64)
- CHECK: [[VCMP0:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(slt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
- CHECK: [[SMINV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP0]]:_(<2 x s1>), [[VEC0]]:_, [[VEC1]]:_
+ CHECK: [[VCMP0:%[0-9]+]]:_(<2 x i1>) = G_ICMP intpred(slt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
+ CHECK: [[SMINV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP0]]:_(<2 x i1>), [[VEC0]]:_, [[VEC1]]:_
- CHECK: [[VCMP1:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(sgt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
- CHECK: [[SMAXV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP1]]:_(<2 x s1>), [[VEC0]]:_, [[VEC1]]:_
+ CHECK: [[VCMP1:%[0-9]+]]:_(<2 x i1>) = G_ICMP intpred(sgt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
+ CHECK: [[SMAXV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP1]]:_(<2 x i1>), [[VEC0]]:_, [[VEC1]]:_
- CHECK: [[VCMP2:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(ult), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
- CHECK: [[UMINV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP2]]:_(<2 x s1>), [[VEC0]]:_, [[VEC1]]:_
+ CHECK: [[VCMP2:%[0-9]+]]:_(<2 x i1>) = G_ICMP intpred(ult), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
+ CHECK: [[UMINV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP2]]:_(<2 x i1>), [[VEC0]]:_, [[VEC1]]:_
- CHECK: [[VCMP3:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(ugt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
- CHECK: [[UMAXV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP3]]:_(<2 x s1>), [[VEC0]]:_, [[VEC1]]:_
+ CHECK: [[VCMP3:%[0-9]+]]:_(<2 x i1>) = G_ICMP intpred(ugt), [[VEC0]]:_(<2 x s32>), [[VEC1]]:_
+ CHECK: [[UMAXV:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[VCMP3]]:_(<2 x i1>), [[VEC0]]:_, [[VEC1]]:_
)";
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
@@ -2181,8 +2181,8 @@ TEST_F(AArch64GISelMITest, LibcallMul) {
CHECK: $x0 = COPY [[COPY]]
CHECK: $x1 = COPY [[COPY]]
CHECK: BL &__muldi3
- CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
- CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x0 = COPY [[UV]]
CHECK: $x1 = COPY [[UV1]]
CHECK: $x2 = COPY [[UV2]]
@@ -2239,8 +2239,8 @@ TEST_F(AArch64GISelMITest, LibcallSRem) {
CHECK: $x0 = COPY [[COPY]]
CHECK: $x1 = COPY [[COPY]]
CHECK: BL &__moddi3
- CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
- CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x0 = COPY [[UV]]
CHECK: $x1 = COPY [[UV1]]
CHECK: $x2 = COPY [[UV2]]
@@ -2297,8 +2297,8 @@ TEST_F(AArch64GISelMITest, LibcallURem) {
CHECK: $x0 = COPY [[COPY]]
CHECK: $x1 = COPY [[COPY]]
CHECK: BL &__umoddi3
- CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
- CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x0 = COPY [[UV]]
CHECK: $x1 = COPY [[UV1]]
CHECK: $x2 = COPY [[UV2]]
@@ -2354,7 +2354,7 @@ TEST_F(AArch64GISelMITest, LibcallCtlzZeroUndef) {
CHECK: BL &__clzsi2
CHECK: $x0 = COPY [[COPY]]
CHECK: BL &__clzdi2
- CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]]
+ CHECK: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]]
CHECK: $x0 = COPY [[UV]]
CHECK: $x1 = COPY [[UV1]]
CHECK: BL &__clzti2
@@ -4271,7 +4271,7 @@ TEST_F(AArch64GISelMITest, MoreElementsSelect) {
CHECK: [[ZERO0:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
CHECK: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), %{{[0-9]+}}:_(s64), [[ZERO0]]
CHECK: [[IMPDEF:%[0-9]+]]:_(<2 x s1>) = G_IMPLICIT_DEF
- CHECK: [[ZERO1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ CHECK: [[ZERO1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
CHECK: [[INSERT:%[0-9]+]]:_(<2 x s1>) = G_INSERT_VECTOR_ELT [[IMPDEF]]:_, [[CMP]]:_(s1), [[ZERO1]]
CHECK: [[SHUFFLE:%[0-9]+]]:_(<2 x s1>) = G_SHUFFLE_VECTOR [[INSERT]]:_(<2 x s1>), [[IMPDEF]]:_, shufflemask(0, 0)
CHECK: [[SELECT:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[SHUFFLE]]:_(<2 x s1>), [[BITCAST0]]:_, [[BITCAST1]]:_
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
index 1c90267ed28aa..4cd6437fade71 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
@@ -77,8 +77,8 @@ TEST_F(AArch64GISelMITest, BasicLegalizerTest) {
StringRef CheckString = R"(
CHECK: %vptr:_(p0) = COPY $x4
CHECK-NEXT: [[LOAD_0:%[0-9]+]]:_(s16) = G_LOAD %vptr:_(p0) :: (load (s8))
- CHECK-NEXT: [[OFFSET_1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- CHECK-NEXT: [[VPTR_1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %vptr:_, [[OFFSET_1]]:_(s64)
+ CHECK-NEXT: [[OFFSET_1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ CHECK-NEXT: [[VPTR_1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %vptr:_, [[OFFSET_1]]:_(i64)
CHECK-NEXT: [[LOAD_1:%[0-9]+]]:_(s16) = G_LOAD [[VPTR_1]]:_(p0) :: (load (s8) from unknown-address + 1)
CHECK-NEXT: %v:_(<2 x s8>) = G_BUILD_VECTOR_TRUNC [[LOAD_0]]:_(s16), [[LOAD_1]]:_(s16)
CHECK-NEXT: $h4 = COPY %v:_(<2 x s8>)
@@ -209,8 +209,8 @@ TEST_F(AArch64GISelMITest, UnorderedArtifactCombiningManyCopiesTest) {
StringRef CheckString = R"(
CHECK: %vptr:_(p0) = COPY $x4
CHECK-NEXT: [[LOAD_0:%[0-9]+]]:_(s16) = G_LOAD %vptr:_(p0) :: (load (s8))
- CHECK-NEXT: [[OFFSET_1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- CHECK-NEXT: [[VPTR_1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %vptr:_, [[OFFSET_1]]:_(s64)
+ CHECK-NEXT: [[OFFSET_1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ CHECK-NEXT: [[VPTR_1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %vptr:_, [[OFFSET_1]]:_(i64)
CHECK-NEXT: [[LOAD_1:%[0-9]+]]:_(s16) = G_LOAD [[VPTR_1]]:_(p0) :: (load (s8) from unknown-address + 1)
CHECK-NEXT: [[V0_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD_0]]:_(s16)
CHECK-NEXT: [[FF_MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
>From 1ed9158b7dfbaf3628c89d7a8092fa0d1be57973 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 2 Feb 2026 10:40:28 +0000
Subject: [PATCH 15/30] Update tests post rebase
---
.../AArch64/GlobalISel/arm64-pcsections.ll | 4 -
.../AArch64/GlobalISel/inline-memset.mir | 32 +-
.../irtranslator-convert-fp16-intrinsics.ll | 8 +-
.../GlobalISel/irtranslator-inline-asm.ll | 7 +-
.../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 1890 +++--------------
5 files changed, 327 insertions(+), 1614 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
index d48077c606e04..7bbec99a16bf9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
@@ -1239,17 +1239,14 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
- ; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: early-clobber renamable $w10 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: renamable $w9 = MOVZWi 1, 0
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
; CHECK-NEXT: B %bb.4
- ; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.cmpxchg.nostore:
- ; CHECK-NEXT: bb.3.cmpxchg.nostore:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
@@ -1285,7 +1282,6 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
- ; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: early-clobber renamable $w10 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (i16) into %ir.ptr)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
index e5f444154f5fd..8f76472fb323c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
@@ -98,10 +98,8 @@ body: |
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK-NEXT: G_STORE [[MUL]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[MUL]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MUL]](i64), [[MUL]](i64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
@@ -158,10 +156,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4629771061636907072
- ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 64
@@ -220,14 +216,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4629771061636907072
- ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 16448
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.dst + 16, align 1)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 16448
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-NEXT: G_STORE [[C1]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.dst + 16, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 64
@@ -252,10 +246,8 @@ body: |
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[TRUNC]](s8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 72340172838076673
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i64) = G_MUL [[ZEXT]], [[C]]
- ; CHECK-NEXT: G_STORE [[MUL]](i64), [[COPY]](p0) :: (store (i64) into %ir.dst, align 1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[MUL]](i64), [[PTR_ADD]](p0) :: (store (i64) into %ir.dst + 8, align 1)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[MUL]](i64), [[MUL]](i64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
index c153d08a3ebdb..524be2c59536c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
@@ -7,8 +7,9 @@ define i16 @convert_to_fp16(float %src) {
; CHECK-NEXT: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
- ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(i16) = G_FPTRUNC [[COPY]](f32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](i16)
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY]](f32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i16) = G_BITCAST [[FPTRUNC]](f16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](i16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%cvt = call i16 @llvm.convert.to.fp16.f32(float %src)
@@ -22,7 +23,8 @@ define float @convert_from_fp16(i16 %src) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[BITCAST]](f16)
; CHECK-NEXT: $s0 = COPY [[FPEXT]](f32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%cvt = call float @llvm.convert.from.fp16.f32(i16 %src)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
index 18574893ce133..94bf7e646c063 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
@@ -270,9 +270,10 @@ define i64 @test_input_with_matching_constraint_to_physical_register() {
; CHECK-LABEL: name: test_input_with_matching_constraint_to_physical_register
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, [[C]](tied-def 3)(i64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x2
- ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64arg = COPY [[C]](i64)
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x2
+ ; CHECK-NEXT: $x0 = COPY [[COPY1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%1 = tail call i64 asm "", "={x2},0"(i64 0)
ret i64 %1
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
index df6cbaf47b846..8f2eaaf860d81 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
@@ -16,20 +16,10 @@ define float @test_fptosi_f16_i32_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptosi_f16_i32_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptosi_f16_i32_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptosi_f16_i32_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptosi_f16_i32_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = fptosi half %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -42,20 +32,10 @@ define double @test_fptosi_f16_i64_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptosi_f16_i64_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptosi_f16_i64_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptosi_f16_i64_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptosi_f16_i64_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = fptosi half %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -68,20 +48,10 @@ define float @test_fptosi_f64_i32_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptosi_f64_i32_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptosi_f64_i32_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptosi_f64_i32_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptosi_f64_i32_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = fptosi double %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -94,20 +64,10 @@ define double @test_fptosi_f32_i64_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptosi_f32_i64_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptosi_f32_i64_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptosi_f32_i64_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptosi_f32_i64_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = fptosi float %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -118,16 +78,6 @@ define double @test_fptosi_f64_i64_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptosi_f64_i64_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptosi_f64_i64_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, d0
-; CHECK-SVE-NEXT: ret
%r = fptosi double %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -139,16 +89,6 @@ define float @test_fptosi_f32_i32_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptosi_f32_i32_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptosi_f32_i32_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, s0
-; CHECK-SVE-NEXT: ret
%r = fptosi float %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -161,20 +101,10 @@ define float @test_fptoui_f16_i32_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptoui_f16_i32_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptoui_f16_i32_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptoui_f16_i32_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptoui_f16_i32_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = fptoui half %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -187,20 +117,10 @@ define double @test_fptoui_f16_i64_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptoui_f16_i64_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptoui_f16_i64_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptoui_f16_i64_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptoui_f16_i64_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = fptoui half %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -213,20 +133,10 @@ define float @test_fptoui_f64_i32_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptoui_f64_i32_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptoui_f64_i32_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptoui_f64_i32_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptoui_f64_i32_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = fptoui double %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -239,20 +149,10 @@ define double @test_fptoui_f32_i64_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: test_fptoui_f32_i64_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptoui_f32_i64_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptoui_f32_i64_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: test_fptoui_f32_i64_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = fptoui float %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -263,16 +163,6 @@ define double @test_fptoui_f64_i64_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptoui_f64_i64_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptoui_f64_i64_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu d0, d0
-; CHECK-SVE-NEXT: ret
%r = fptoui double %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -284,16 +174,6 @@ define float @test_fptoui_f32_i32_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: test_fptoui_f32_i32_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: test_fptoui_f32_i32_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu s0, s0
-; CHECK-SVE-NEXT: ret
%r = fptoui float %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -311,20 +191,10 @@ define double @fcvtas_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtas_ds_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtas_ds_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -338,20 +208,10 @@ define float @fcvtas_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtas_sd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtas_sd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -363,16 +223,6 @@ define float @fcvtas_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtas_ss_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtas_ss_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -384,16 +234,6 @@ define double @fcvtas_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtas_dd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtas_dd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -408,20 +248,10 @@ define double @fcvtau_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtau_ds_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtau d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtau_ds_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtau d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -435,20 +265,10 @@ define float @fcvtau_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtau_sd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtau s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtau_sd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtau s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -460,16 +280,6 @@ define float @fcvtau_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtau_ss_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtau_ss_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -481,16 +291,6 @@ define double @fcvtau_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtau_dd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtau_dd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -504,20 +304,10 @@ define double @fcvtns_ds_roundeven_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtns_ds_roundeven_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtns d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtns_ds_roundeven_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtns d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtns_ds_roundeven_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtns d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtns_ds_roundeven_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtns d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -531,20 +321,10 @@ define float @fcvtns_sd_roundeven_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtns_sd_roundeven_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtns s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtns_sd_roundeven_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtns s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtns_sd_roundeven_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtns s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtns_sd_roundeven_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtns s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -552,25 +332,10 @@ define float @fcvtns_sd_roundeven_simd(double %a) {
}
define float @fcvtns_ss_roundeven_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtns_ss_roundeven_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtns s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtns_ss_roundeven_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtns_ss_roundeven_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtns s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtns_ss_roundeven_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtns s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -578,25 +343,10 @@ define float @fcvtns_ss_roundeven_simd(float %a) {
}
define double @fcvtns_dd_roundeven_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtns_dd_roundeven_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtns d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtns_dd_roundeven_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtns_dd_roundeven_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtns d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtns_dd_roundeven_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtns d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -611,20 +361,10 @@ define double @fcvtnu_ds_roundeven_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtnu_ds_roundeven_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtnu d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtnu_ds_roundeven_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtnu d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtnu_ds_roundeven_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtnu d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtnu_ds_roundeven_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtnu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -638,20 +378,10 @@ define float @fcvtnu_sd_roundeven_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtnu_sd_roundeven_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtnu s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtnu_sd_roundeven_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtnu s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtnu_sd_roundeven_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtnu s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtnu_sd_roundeven_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtnu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -659,25 +389,10 @@ define float @fcvtnu_sd_roundeven_simd(double %a) {
}
define float @fcvtnu_ss_roundeven_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtnu_ss_roundeven_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtnu s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtnu_ss_roundeven_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtnu_ss_roundeven_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtnu s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtnu_ss_roundeven_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtnu s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptoui float %r to i32
%bc = bitcast i32 %i to float
@@ -685,25 +400,10 @@ define float @fcvtnu_ss_roundeven_simd(float %a) {
}
define double @fcvtnu_dd_roundeven_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtnu_dd_roundeven_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtnu d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtnu_dd_roundeven_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtnu_dd_roundeven_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtnu d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtnu_dd_roundeven_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtnu d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptoui double %r to i64
%bc = bitcast i64 %i to double
@@ -717,20 +417,10 @@ define double @fcvtms_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtms_ds_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtms_ds_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -744,20 +434,10 @@ define float @fcvtms_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtms_sd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtms_sd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -769,16 +449,6 @@ define float @fcvtms_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtms_ss_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtms_ss_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -790,16 +460,6 @@ define double @fcvtms_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtms_dd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtms_dd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -815,20 +475,10 @@ define double @fcvtmu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtmu_ds_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtmu d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtmu_ds_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtmu d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -842,20 +492,10 @@ define float @fcvtmu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtmu_sd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtmu s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtmu_sd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtmu s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -867,16 +507,6 @@ define float @fcvtmu_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtmu_ss_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtmu_ss_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -888,16 +518,6 @@ define double @fcvtmu_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtmu_dd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtmu_dd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -912,20 +532,10 @@ define double @fcvtps_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtps_ds_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtps_ds_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -939,20 +549,10 @@ define float @fcvtps_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtps_sd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtps_sd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -964,16 +564,6 @@ define float @fcvtps_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtps_ss_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtps_ss_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -985,16 +575,6 @@ define double @fcvtps_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtps_dd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtps_dd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -1009,20 +589,10 @@ define double @fcvtpu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtpu_ds_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtpu d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtpu_ds_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtpu d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -1036,20 +606,10 @@ define float @fcvtpu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtpu_sd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtpu s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtpu_sd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtpu s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -1061,16 +621,6 @@ define float @fcvtpu_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtpu_ss_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtpu_ss_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -1082,16 +632,6 @@ define double @fcvtpu_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtpu_dd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtpu_dd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -1106,20 +646,10 @@ define double @fcvtzs_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_ds_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_ds_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -1133,20 +663,10 @@ define float @fcvtzs_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_sd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_sd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -1158,16 +678,6 @@ define float @fcvtzs_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_ss_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_ss_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -1179,16 +689,6 @@ define double @fcvtzs_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_dd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_dd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -1202,20 +702,10 @@ define double @fcvtzu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_ds_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_ds_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_ds_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_ds_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -1229,20 +719,10 @@ define float @fcvtzu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_sd_round_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_sd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_sd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_sd_round_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -1254,16 +734,6 @@ define float @fcvtzu_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_ss_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_ss_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -1275,16 +745,6 @@ define double @fcvtzu_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_dd_round_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_dd_round_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -1303,20 +763,10 @@ define float @fcvtzs_sh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_sh_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_sh_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_sh_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_sh_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
+; CHECK-FPRCVT-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f16(half %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1329,20 +779,10 @@ define double @fcvtzs_dh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_dh_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_dh_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_dh_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_dh_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
+; CHECK-FPRCVT-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f16(half %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1355,20 +795,10 @@ define double @fcvtzs_ds_sat_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_ds_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_ds_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_ds_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_ds_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
+; CHECK-FPRCVT-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f32(float %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1381,20 +811,10 @@ define float @fcvtzs_sd_sat_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_sd_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_sd_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_sd_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_sd_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
+; CHECK-FPRCVT-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f64(double %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1405,16 +825,6 @@ define float @fcvtzs_ss_sat_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_ss_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_ss_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, s0
-; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f32(float %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1425,16 +835,6 @@ define double @fcvtzs_dd_sat_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_dd_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_dd_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, d0
-; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f64(double %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1447,20 +847,10 @@ define float @fcvtzu_sh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_sh_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_sh_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_sh_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_sh_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%i = call i32 @llvm.fptoui.sat.i32.f16(half %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1473,20 +863,10 @@ define double @fcvtzu_dh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_dh_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_dh_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_dh_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_dh_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%i = call i64 @llvm.fptoui.sat.i64.f16(half %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1499,20 +879,10 @@ define double @fcvtzu_ds_sat_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_ds_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_ds_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_ds_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_ds_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%i = call i64 @llvm.fptoui.sat.i64.f32(float %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1525,20 +895,10 @@ define float @fcvtzu_sd_sat_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_sd_sat_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_sd_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_sd_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_sd_sat_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%i = call i32 @llvm.fptoui.sat.i32.f64(double %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1549,16 +909,6 @@ define float @fcvtzu_ss_sat_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_ss_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_ss_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, s0
-; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f32(float %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1569,16 +919,6 @@ define double @fcvtzu_dd_sat_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_dd_sat_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_dd_sat_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, d0
-; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f64(double %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1595,20 +935,10 @@ define float @fcvtas_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtas_sh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtas_sh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1622,20 +952,10 @@ define double @fcvtas_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtas_dh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtas_dh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1649,20 +969,10 @@ define double @fcvtas_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtas_ds_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtas_ds_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1676,20 +986,10 @@ define float @fcvtas_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtas_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtas s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtas_sd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtas_sd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtas_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtas s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1701,16 +1001,6 @@ define float @fcvtas_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtas_ss_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtas_ss_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1722,16 +1012,6 @@ define double @fcvtas_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtas_dd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtas_dd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1745,20 +1025,10 @@ define float @fcvtau_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtau_sh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtau s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtau_sh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtau s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1772,20 +1042,10 @@ define double @fcvtau_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtau_dh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtau d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtau_dh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtau d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1799,20 +1059,10 @@ define double @fcvtau_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtau_ds_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtau d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtau_ds_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtau d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1826,20 +1076,10 @@ define float @fcvtau_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtau_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtau s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtau_sd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtau s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtau_sd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtau s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtau_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtau s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1851,16 +1091,6 @@ define float @fcvtau_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtau_ss_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtau_ss_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1872,16 +1102,6 @@ define double @fcvtau_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtau_dd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtas d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtau_dd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtas d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1895,20 +1115,10 @@ define float @fcvtns_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtns_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtns s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtns_sh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtns s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtns_sh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtns s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtns_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtns s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1922,20 +1132,10 @@ define double @fcvtns_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtns_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtns d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtns_dh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtns d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtns_dh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtns d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtns_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtns d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1949,20 +1149,10 @@ define double @fcvtns_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtns_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtns d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtns_ds_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtns d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtns_ds_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtns d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtns_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtns d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1976,20 +1166,10 @@ define float @fcvtns_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtns_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtns s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtns_sd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtns s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtns_sd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtns s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtns_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtns s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1997,25 +1177,10 @@ define float @fcvtns_sd_simd(double %a) {
}
define float @fcvtns_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtns_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtns s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtns_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtns_ss_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtns s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtns_ss_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtns s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -2023,25 +1188,10 @@ define float @fcvtns_ss_simd(float %a) {
}
define double @fcvtns_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtns_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtns d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtns_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtns_dd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtns d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtns_dd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtns d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -2055,20 +1205,10 @@ define float @fcvtnu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtnu_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtnu s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtnu_sh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtnu s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtnu_sh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtnu s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtnu_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtnu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -2082,20 +1222,10 @@ define double @fcvtnu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtnu_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtnu d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtnu_dh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtnu d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtnu_dh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtnu d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtnu_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtnu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -2109,20 +1239,10 @@ define double @fcvtnu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtnu_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtnu d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtnu_ds_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtnu d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtnu_ds_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtnu d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtnu_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtnu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -2136,20 +1256,10 @@ define float @fcvtnu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtnu_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtnu s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtnu_sd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtnu s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtnu_sd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtnu s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtnu_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtnu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -2157,25 +1267,10 @@ define float @fcvtnu_sd_simd(double %a) {
}
define float @fcvtnu_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtnu_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtnu s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtnu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtnu_ss_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtnu s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtnu_ss_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtnu s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -2183,25 +1278,10 @@ define float @fcvtnu_ss_simd(float %a) {
}
define double @fcvtnu_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtnu_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtnu d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
-;
; CHECK-LABEL: fcvtnu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtnu_dd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtnu d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtnu_dd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtnu d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -2215,20 +1295,10 @@ define float @fcvtms_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtms_sh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtms_sh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -2242,20 +1312,10 @@ define double @fcvtms_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtms_dh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtms_dh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -2269,20 +1329,10 @@ define double @fcvtms_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtms_ds_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtms_ds_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -2296,20 +1346,10 @@ define float @fcvtms_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtms_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtms s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtms_sd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtms_sd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtms_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtms s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -2321,16 +1361,6 @@ define float @fcvtms_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtms_ss_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtms_ss_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -2342,16 +1372,6 @@ define double @fcvtms_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtms_dd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtms_dd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -2365,20 +1385,10 @@ define float @fcvtmu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtmu_sh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtmu s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtmu_sh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtmu s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -2392,20 +1402,10 @@ define double @fcvtmu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtmu_dh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtmu d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtmu_dh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtmu d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -2419,20 +1419,10 @@ define double @fcvtmu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtmu_ds_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtmu d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtmu_ds_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtmu d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -2446,20 +1436,10 @@ define float @fcvtmu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtmu_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtmu s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtmu_sd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtmu s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtmu_sd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtmu s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtmu_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtmu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -2471,16 +1451,6 @@ define float @fcvtmu_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtmu_ss_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtmu_ss_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -2492,16 +1462,6 @@ define double @fcvtmu_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtmu_dd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtms d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtmu_dd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtms d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -2515,20 +1475,10 @@ define float @fcvtps_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtps_sh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtps_sh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -2542,20 +1492,10 @@ define double @fcvtps_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtps_dh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtps_dh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -2569,20 +1509,10 @@ define double @fcvtps_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtps_ds_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtps_ds_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -2596,20 +1526,10 @@ define float @fcvtps_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtps_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtps s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtps_sd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtps_sd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtps_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtps s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -2621,16 +1541,6 @@ define float @fcvtps_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtps_ss_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtps_ss_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -2642,16 +1552,6 @@ define double @fcvtps_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtps_dd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtps_dd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -2665,20 +1565,10 @@ define float @fcvtpu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtpu_sh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtpu s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtpu_sh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtpu s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -2692,20 +1582,10 @@ define double @fcvtpu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtpu_dh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtpu d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtpu_dh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtpu d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -2719,20 +1599,10 @@ define double @fcvtpu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtpu_ds_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtpu d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtpu_ds_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtpu d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -2746,20 +1616,10 @@ define float @fcvtpu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtpu_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtpu s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtpu_sd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtpu s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtpu_sd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtpu s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtpu_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtpu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -2771,16 +1631,6 @@ define float @fcvtpu_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtpu_ss_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtpu_ss_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -2792,16 +1642,6 @@ define double @fcvtpu_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtpu_dd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtps d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtpu_dd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtps d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -2815,20 +1655,10 @@ define float @fcvtzs_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_sh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_sh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -2842,20 +1672,10 @@ define double @fcvtzs_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_dh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_dh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -2869,20 +1689,10 @@ define double @fcvtzs_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_ds_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_ds_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -2896,20 +1706,10 @@ define float @fcvtzs_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzs_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_sd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_sd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzs_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -2921,16 +1721,6 @@ define float @fcvtzs_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_ss_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_ss_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -2942,16 +1732,6 @@ define double @fcvtzs_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzs_dd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzs d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzs_dd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzs d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -2965,20 +1745,10 @@ define float @fcvtzu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_sh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_sh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu s0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_sh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu s0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_sh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -2992,20 +1762,10 @@ define double @fcvtzu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_dh_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, h0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_dh_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu d0, h0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_dh_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu d0, h0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_dh_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, h0
+; CHECK-FPRCVT-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -3019,20 +1779,10 @@ define double @fcvtzu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_ds_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu d0, s0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_ds_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu d0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_ds_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu d0, s0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_ds_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
+; CHECK-FPRCVT-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -3046,20 +1796,10 @@ define float @fcvtzu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-LABEL: fcvtzu_sd_simd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu s0, d0
-; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_sd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu s0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_sd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu s0, d0
-; CHECK-SVE-NEXT: ret
+; CHECK-FPRCVT-LABEL: fcvtzu_sd_simd:
+; CHECK-FPRCVT: // %bb.0:
+; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
+; CHECK-FPRCVT-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -3071,16 +1811,6 @@ define float @fcvtzu_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_ss_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu s0, s0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_ss_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu s0, s0
-; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -3092,16 +1822,6 @@ define double @fcvtzu_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ret
-;
-; CHECK-SME-LABEL: fcvtzu_dd_simd:
-; CHECK-SME: // %bb.0:
-; CHECK-SME-NEXT: fcvtzu d0, d0
-; CHECK-SME-NEXT: ret
-;
-; CHECK-SVE-LABEL: fcvtzu_dd_simd:
-; CHECK-SVE: // %bb.0:
-; CHECK-SVE-NEXT: fcvtzu d0, d0
-; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -3110,3 +1830,5 @@ define double @fcvtzu_dd_simd(double %a) {
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-GI-FPRCVT: {{.*}}
; CHECK-SD-FPRCVT: {{.*}}
+; CHECK-SME: {{.*}}
+; CHECK-SVE: {{.*}}
>From aad202f934f2c874b1355f21de96851d8e36ad3f Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 2 Feb 2026 11:05:30 +0000
Subject: [PATCH 16/30] Fix crash when trying to extend a float to an integer
---
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index dcbfe01d8b337..8f805e8baf72c 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -490,7 +490,8 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
// If the split EVT was a <1 x T> vector, and NewVT is T, then we
// don't have to do anything since we don't distinguish between the
// two.
- if (NewLLT != MRI.getType(CurVReg)) {
+ if (NewLLT.getScalarSizeInBits() !=
+ MRI.getType(CurVReg).getScalarSizeInBits()) {
// A scalar extend.
CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
.getReg(0);
>From c94b5cdec585bd616202a0e1219f26c6f477f0a2 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 2 Feb 2026 11:43:59 +0000
Subject: [PATCH 17/30] Remove extra semicolons.
---
.../lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index d282bf202e2b7..3b487f55193c1 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -771,7 +771,7 @@ bool matchStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI) {
return false;
return isPointerRoX(MRI, Store);
-};
+}
void applyStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI,
MachineIRBuilder &MIB) {
@@ -785,7 +785,7 @@ void applyStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI,
{Merge->getSourceReg(0), Merge->getSourceReg(1)})
.getReg(0);
MI.getOperand(0).setReg(BV);
-};
+}
/// Determine whether or not it is possible to update the RHS and predicate of
/// a G_ICMP instruction such that the RHS will be selected as an arithmetic
>From 349693363a005a85d08ed0f156c3a699b3ee194b Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Thu, 19 Feb 2026 13:44:02 +0000
Subject: [PATCH 18/30] Add GIM_SwitchTypeShape to match based on element count
and element size.
Add new field to opcode definitions to allow for matching generic types.
Allow Switch based matchers to group similar checks together in a non-greedy fashion to reduce tablesize.
---
.../CodeGen/GlobalISel/GIMatchTableExecutor.h | 14 ++-
.../GlobalISel/GIMatchTableExecutorImpl.h | 76 +++++++++++++--
llvm/include/llvm/Target/GenericOpcodes.td | 17 ++++
llvm/include/llvm/Target/Target.td | 4 +
.../GlobalISelEmitter/GlobalISelEmitter.td | 4 +-
.../GlobalISel/GlobalISelMatchTable.cpp | 95 ++++++++++++++-----
.../Common/GlobalISel/GlobalISelMatchTable.h | 66 ++++++++++---
llvm/utils/TableGen/GlobalISelEmitter.cpp | 55 +++++++++--
8 files changed, 274 insertions(+), 57 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
index 3a2509345b776..a87615fd4e2d4 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
@@ -18,6 +18,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/Bitset.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -108,6 +109,15 @@ enum {
/// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
GIM_SwitchType,
+ /// Switch over the shape of an LLT on the specified instruction operand
+ /// - InsnID(ULEB128) - Instruction ID
+ /// - OpIdx(ULEB128) - Operand index
+ /// - LowerBound(2) - numerically minimum Type ID supported
+ /// - UpperBound(2) - numerically maximum + 1 Type ID supported
+ /// - Default(4) - failure jump target
+ /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets
+ GIM_SwitchTypeShape,
+
/// Record the specified instruction.
/// The IgnoreCopies variant ignores COPY instructions.
/// - NewInsnID(ULEB128) - Instruction ID to define
@@ -664,14 +674,14 @@ class GIMatchTableExecutor {
CustomRenderers(CustomRenderers) {
for (size_t I = 0; I < NumTypeObjects; ++I)
- TypeIDMap[TypeObjects[I]] = I;
+ TypeIDMap[TypeObjects[I].getUniqueRAWLLTData()] = I;
}
const LLT *TypeObjects;
const PredicateBitset *FeatureBitsets;
const ComplexMatcherMemFn *ComplexPredicates;
const CustomRendererFn *CustomRenderers;
- SmallDenseMap<LLT, unsigned, 64> TypeIDMap;
+ SmallDenseMap<uint64_t, unsigned, 64> TypeIDMap;
};
protected:
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index de605d833a460..344686309d5d2 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -259,7 +259,6 @@ bool GIMatchTableExecutor::executeMatchTable(
OnFailResumeAt.push_back(Default);
break;
}
-
case GIM_SwitchType: {
uint64_t InsnID = readULEB();
uint64_t OpIdx = readULEB();
@@ -278,7 +277,7 @@ bool GIMatchTableExecutor::executeMatchTable(
if (!MO.isReg())
dbgs() << "Not a VReg\n";
else
- dbgs() << MRI.getType(MO.getReg()) << "\n";
+ dbgs() << MRI.getType(MO.getReg());
});
if (!MO.isReg()) {
CurrentIdx = Default;
@@ -291,25 +290,33 @@ bool GIMatchTableExecutor::executeMatchTable(
// Always try the integer patterns as we now consider that to be generic
// (to an extent)
- if (LLT::getUseExtended() && !Ty.getScalarType().isInteger())
+ if (LLT::getUseExtended() && Ty.getScalarType().isAnyScalar()) {
TypesToTry.push_back(
Ty.changeElementType(LLT::integer(Ty.getScalarSizeInBits())));
- if (LLT::getUseExtended() && Ty.isAnyScalar() &&
- Ty.getScalarSizeInBits() > 8)
- TypesToTry.push_back(
- Ty.changeElementType(LLT::floatIEEE(Ty.getScalarSizeInBits())));
+ if (Ty.getScalarSizeInBits() > 8)
+ TypesToTry.push_back(
+ Ty.changeElementType(LLT::floatIEEE(Ty.getScalarSizeInBits())));
+ }
const auto JumpTableBase = CurrentIdx;
bool Matched = false;
for (LLT Type : TypesToTry) {
- const auto TyI = ExecInfo.TypeIDMap.find(Type);
+ const auto TyI = ExecInfo.TypeIDMap.find(Type.getUniqueRAWLLTData());
if (TyI == ExecInfo.TypeIDMap.end())
continue;
const int64_t TypeID = TyI->second;
if (TypeID < LowerBound || UpperBound <= TypeID)
continue;
const auto NumEntry = (TypeID - LowerBound);
+ if (Matched) {
+ auto Idx = readBytesAs<uint32_t>(MatchTable + JumpTableBase +
+ (NumEntry * 4));
+ if (Idx)
+ OnFailResumeAt.push_back(Idx);
+
+ continue;
+ }
// Each entry is 4 bytes
CurrentIdx =
readBytesAs<uint32_t>(MatchTable + JumpTableBase + (NumEntry * 4));
@@ -318,7 +325,9 @@ bool GIMatchTableExecutor::executeMatchTable(
continue;
}
Matched = true;
- break;
+
+ DEBUG_WITH_TYPE(TgtExecutor::getName(),
+ { dbgs() << ", matched as=" << Type << "\n"; });
}
if (!Matched) {
CurrentIdx = Default;
@@ -328,6 +337,55 @@ bool GIMatchTableExecutor::executeMatchTable(
OnFailResumeAt.push_back(Default);
break;
}
+ case GIM_SwitchTypeShape: {
+ uint64_t InsnID = readULEB();
+ uint64_t OpIdx = readULEB();
+ uint16_t LowerBound = readU16();
+ uint16_t UpperBound = readU16();
+ int64_t Default = readU32();
+
+ assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
+ MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
+
+ DEBUG_WITH_TYPE(TgtExecutor::getName(), {
+ dbgs() << CurrentIdx << ": GIM_SwitchTypeShape(MIs[" << InsnID
+ << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", "
+ << UpperBound << "), Default=" << Default
+ << ", JumpTable...) // Got=";
+ if (!MO.isReg())
+ dbgs() << "Not a VReg\n";
+ else
+ dbgs() << MRI.getType(MO.getReg()) << "\n";
+ });
+ if (!MO.isReg()) {
+ CurrentIdx = Default;
+ break;
+ }
+
+ LLT Ty = MRI.getType(MO.getReg());
+ Ty = Ty.changeElementType(LLT::scalar(Ty.getScalarSizeInBits()));
+
+ const auto TyI = ExecInfo.TypeIDMap.find(Ty.getUniqueRAWLLTData());
+ if (TyI == ExecInfo.TypeIDMap.end()) {
+ CurrentIdx = Default;
+ break;
+ }
+ const int64_t TypeID = TyI->second;
+ if (TypeID < LowerBound || UpperBound <= TypeID) {
+ CurrentIdx = Default;
+ break;
+ }
+ const auto NumEntry = (TypeID - LowerBound);
+ // Each entry is 4 bytes
+ CurrentIdx =
+ readBytesAs<uint32_t>(MatchTable + CurrentIdx + (NumEntry * 4));
+ if (!CurrentIdx) {
+ CurrentIdx = Default;
+ break;
+ }
+ OnFailResumeAt.push_back(Default);
+ break;
+ }
case GIM_CheckNumOperandsGE:
case GIM_CheckNumOperandsLE: {
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 7f6d868c44006..cfd6f5dbba9a6 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -159,6 +159,7 @@ def G_BITCAST : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Only supports scalar result types
@@ -278,6 +279,7 @@ def G_FREEZE : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
def G_LROUND: GenericInstruction {
@@ -1334,6 +1336,7 @@ def G_LOAD : GenericInstruction {
let InOperandList = (ins ptype1:$addr);
let hasSideEffects = false;
let mayLoad = true;
+ let GISelMatchGenericTypes = 1;
}
// Generic sign-extended load. Expects a MachineMemOperand in addition to explicit operands.
@@ -1360,6 +1363,7 @@ def G_INDEXED_LOAD : GenericInstruction {
let InOperandList = (ins ptype1:$base, type2:$offset, unknown:$am);
let hasSideEffects = false;
let mayLoad = true;
+ let GISelMatchGenericTypes = 1;
}
// Same as G_INDEXED_LOAD except that the load performed is sign-extending, as with G_SEXTLOAD.
@@ -1384,6 +1388,7 @@ def G_STORE : GenericInstruction {
let InOperandList = (ins type0:$src, ptype1:$addr);
let hasSideEffects = false;
let mayStore = true;
+ let GISelMatchGenericTypes = 1;
}
// Combines a store with a GEP. See description of G_INDEXED_LOAD for indexing behaviour.
@@ -1393,6 +1398,7 @@ def G_INDEXED_STORE : GenericInstruction {
unknown:$am);
let hasSideEffects = false;
let mayStore = true;
+ let GISelMatchGenericTypes = 1;
}
// Generic atomic cmpxchg with internal success check. Expects a
@@ -1475,6 +1481,7 @@ def G_EXTRACT : GenericInstruction {
let OutOperandList = (outs type0:$res);
let InOperandList = (ins type1:$src, untyped_imm_0:$offset);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Extract multiple registers specified size, starting from blocks given by
@@ -1488,6 +1495,7 @@ def G_UNMERGE_VALUES : GenericInstruction {
let InOperandList = (ins type1:$src);
let hasSideEffects = false;
let variadicOpsType = type0;
+ let GISelMatchGenericTypes = 1;
}
// Insert a smaller register into a larger one at the specified bit-index.
@@ -1506,6 +1514,7 @@ def G_MERGE_VALUES : GenericInstruction {
let InOperandList = (ins type1:$src0, variable_ops);
let hasSideEffects = false;
let variadicOpsType = type1;
+ let GISelMatchGenericTypes = 1;
}
// Generic vscale.
@@ -1525,6 +1534,7 @@ def G_BUILD_VECTOR : GenericInstruction {
let InOperandList = (ins type1:$src0, variable_ops);
let hasSideEffects = false;
let variadicOpsType = type1;
+ let GISelMatchGenericTypes = 1;
}
/// Like G_BUILD_VECTOR, but truncates the larger operand types to fit the
@@ -1540,6 +1550,7 @@ def G_CONCAT_VECTORS : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src0, variable_ops);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Intrinsic without side effects.
@@ -1659,6 +1670,7 @@ def G_INSERT_SUBVECTOR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type1:$src1, untyped_imm_0:$idx);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Generic extract subvector.
@@ -1666,6 +1678,7 @@ def G_EXTRACT_SUBVECTOR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src, untyped_imm_0:$idx);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Generic insertelement.
@@ -1673,6 +1686,7 @@ def G_INSERT_VECTOR_ELT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src, type1:$elt, type2:$idx);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Generic extractelement.
@@ -1680,6 +1694,7 @@ def G_EXTRACT_VECTOR_ELT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src, type2:$idx);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Generic shufflevector.
@@ -1690,6 +1705,7 @@ def G_SHUFFLE_VECTOR: GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$v1, type1:$v2, unknown:$mask);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Generic splatvector.
@@ -1697,6 +1713,7 @@ def G_SPLAT_VECTOR: GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$val);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Generic stepvector.
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index cf4e6498b8551..6b80d2d1f4267 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -849,6 +849,10 @@ class Instruction : InstructionEncoding {
/// ID, so that instruction that is defined earlier can be sorted earlier
/// in the assembly matching table.
bit HasPositionOrder = false;
+
+ // If set, GlobalISel match-table type checks for this instruction should
+ // ignore scalar int/float distinctions and match by size/shape only.
+ bit GISelMatchGenericTypes = 0;
}
/// Defines a Pat match between compressed and uncompressed instruction.
diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
index d69f7af096c31..8d110ab955dc8 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
@@ -111,12 +111,14 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// EXTENDED-LABEL: // LLT Objects.
// EXTENDED-NEXT: enum {
+// EXTENDED-NEXT: GILLT_s32,
// EXTENDED-NEXT: GILLT_i32,
// EXTENDED-NEXT: GILLT_f32,
// EXTENDED-NEXT: GILLT_p0s32,
// EXTENDED-NEXT: };
-// EXTENDED-NEXT: const static size_t NumTypeObjects = 3;
+// EXTENDED-NEXT: const static size_t NumTypeObjects = 4;
// EXTENDED-NEXT: const static LLT TypeObjects[] = {
+// EXTENDED-NEXT: LLT(LLT::Kind::SCALAR, ElementCount::getFixed(0), 32),
// EXTENDED-NEXT: LLT(LLT::Kind::INTEGER, ElementCount::getFixed(0), 32),
// EXTENDED-NEXT: LLT(LLT::Kind::FLOAT, ElementCount::getFixed(0), 32, LLT::FpSemantics::S_IEEEsingle),
// EXTENDED-NEXT: LLT::pointer(0, 32),
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 9d692c2b63a1d..3ec7a3483f5cd 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -481,6 +481,19 @@ std::optional<LLTCodeGen> llvm::gi::MVTToLLT(MVT VT) {
return std::nullopt;
}
+std::optional<LLTCodeGen> llvm::gi::MVTToGenericLLT(MVT VT) {
+ if (VT.isVector() && !VT.getVectorElementCount().isScalar()) {
+ unsigned ElemBits = VT.getVectorElementType().getSizeInBits();
+ return LLTCodeGen(
+ LLT::vector(VT.getVectorElementCount(), LLT::scalar(ElemBits)));
+ }
+
+ if (VT.isInteger() || VT.isFloatingPoint())
+ return LLTCodeGen(LLT::scalar(VT.getSizeInBits()));
+
+ return std::nullopt;
+}
+
//===- Matcher ------------------------------------------------------------===//
void Matcher::optimize() {}
@@ -622,7 +635,8 @@ bool SwitchMatcher::recordsOperand() const {
}
bool SwitchMatcher::isSupportedPredicateType(const PredicateMatcher &P) {
- return isa<InstructionOpcodeMatcher>(P) || isa<LLTOperandMatcher>(P);
+ return isa<InstructionOpcodeMatcher>(P) || isa<LLTOperandShapeMatcher>(P) ||
+ isa<LLTOperandMatcher>(P);
}
bool SwitchMatcher::candidateConditionMatches(
@@ -654,9 +668,7 @@ bool SwitchMatcher::candidateConditionMatches(
if (!Predicate.isIdenticalDownToValue(RepresentativeCondition))
return false;
- const auto Value = Predicate.getValue();
- // ... but be unique with respect to the actual value they check:
- return Values.count(Value) == 0;
+ return true;
}
bool SwitchMatcher::addMatcher(Matcher &Candidate) {
@@ -667,25 +679,43 @@ bool SwitchMatcher::addMatcher(Matcher &Candidate) {
if (!candidateConditionMatches(Predicate))
return false;
const auto Value = Predicate.getValue();
- Values.insert(Value);
-
+ auto It = Buckets.find(Value.RawValue);
+ if (It == Buckets.end())
+ It = Buckets.emplace(Value.RawValue, Bucket(Value)).first;
+#ifndef NDEBUG
+ else
+ assert(It->second.Value.Record.EmitStr == Value.Record.EmitStr &&
+ "Mismatched records for identical switch value");
+#endif
+ It->second.Matchers.push_back(&Candidate);
Matchers.push_back(&Candidate);
return true;
}
void SwitchMatcher::finalize() {
assert(Condition == nullptr && "Already finalized");
- assert(Values.size() == Matchers.size() && "Broken SwitchMatcher");
+ unsigned NumBucketedMatchers = 0;
+ for (const auto &Entry : Buckets)
+ NumBucketedMatchers += Entry.second.Matchers.size();
+ assert(NumBucketedMatchers == Matchers.size() && "Broken SwitchMatcher");
if (empty())
return;
- llvm::stable_sort(Matchers, [](const Matcher *L, const Matcher *R) {
- return L->getFirstCondition().getValue() <
- R->getFirstCondition().getValue();
- });
- Condition = Matchers[0]->popFirstCondition();
- for (unsigned I = 1, E = Values.size(); I < E; ++I)
+ Condition = Matchers.front()->popFirstCondition();
+ for (unsigned I = 1, E = Matchers.size(); I < E; ++I)
Matchers[I]->popFirstCondition();
+
+ // After removing the switch condition, try to hoist any shared predicates
+ // within each switch bucket.
+ for (auto &Entry : Buckets) {
+ auto &BucketMatchers = Entry.second.Matchers;
+ BucketMatchers =
+ optimizeRules<GroupMatcher>(BucketMatchers, MatcherStorage);
+ }
+
+ Matchers.clear();
+ for (auto &Entry : Buckets)
+ append_range(Matchers, Entry.second.Matchers);
}
void SwitchMatcher::emitPredicateSpecificOpcodes(const PredicateMatcher &P,
@@ -697,6 +727,14 @@ void SwitchMatcher::emitPredicateSpecificOpcodes(const PredicateMatcher &P,
<< MatchTable::ULEB128Value(Condition->getInsnVarID());
return;
}
+ if (const auto *Condition = dyn_cast<LLTOperandShapeMatcher>(&P)) {
+ Table << MatchTable::Opcode("GIM_SwitchTypeShape")
+ << MatchTable::Comment("MI")
+ << MatchTable::ULEB128Value(Condition->getInsnVarID())
+ << MatchTable::Comment("Op")
+ << MatchTable::ULEB128Value(Condition->getOpIdx());
+ return;
+ }
if (const auto *Condition = dyn_cast<LLTOperandMatcher>(&P)) {
Table << MatchTable::Opcode("GIM_SwitchType") << MatchTable::Comment("MI")
<< MatchTable::ULEB128Value(Condition->getInsnVarID())
@@ -710,19 +748,22 @@ void SwitchMatcher::emitPredicateSpecificOpcodes(const PredicateMatcher &P,
}
void SwitchMatcher::emit(MatchTable &Table) {
- assert(Values.size() == Matchers.size() && "Broken SwitchMatcher");
+ unsigned NumBucketedMatchers = 0;
+ for (const auto &Entry : Buckets)
+ NumBucketedMatchers += Entry.second.Matchers.size();
+ assert(NumBucketedMatchers == Matchers.size() && "Broken SwitchMatcher");
if (empty())
return;
assert(Condition != nullptr &&
"Broken SwitchMatcher, hasn't been finalized?");
- std::vector<unsigned> LabelIDs(Values.size());
+ std::vector<unsigned> LabelIDs(Buckets.size());
std::generate(LabelIDs.begin(), LabelIDs.end(),
[&Table]() { return Table.allocateLabelID(); });
const unsigned Default = Table.allocateLabelID();
- const int64_t LowerBound = Values.begin()->RawValue;
- const int64_t UpperBound = Values.rbegin()->RawValue + 1;
+ const int64_t LowerBound = Buckets.begin()->second.Value.RawValue;
+ const int64_t UpperBound = Buckets.rbegin()->second.Value.RawValue + 1;
emitPredicateSpecificOpcodes(*Condition, Table);
@@ -731,21 +772,25 @@ void SwitchMatcher::emit(MatchTable &Table) {
<< MatchTable::Comment("default:") << MatchTable::JumpTarget(Default);
int64_t J = LowerBound;
- auto VI = Values.begin();
- for (unsigned I = 0, E = Values.size(); I < E; ++I) {
- auto V = *VI++;
+ unsigned CaseIdx = 0;
+ for (auto &Entry : Buckets) {
+ auto &V = Entry.second.Value;
while (J++ < V.RawValue)
Table << MatchTable::IntValue(4, 0);
V.Record.turnIntoComment();
Table << MatchTable::LineBreak << V.Record
- << MatchTable::JumpTarget(LabelIDs[I]);
+ << MatchTable::JumpTarget(LabelIDs[CaseIdx]);
+ ++CaseIdx;
}
Table << MatchTable::LineBreak;
- for (unsigned I = 0, E = Values.size(); I < E; ++I) {
- Table << MatchTable::Label(LabelIDs[I]);
- Matchers[I]->emit(Table);
+ CaseIdx = 0;
+ for (auto &Entry : Buckets) {
+ Table << MatchTable::Label(LabelIDs[CaseIdx]);
+ for (Matcher *M : Entry.second.Matchers)
+ M->emit(Table);
Table << MatchTable::Opcode("GIM_Reject") << MatchTable::LineBreak;
+ ++CaseIdx;
}
Table << MatchTable::Label(Default);
}
@@ -1925,7 +1970,7 @@ void InstructionMatcher::optimize() {
}
for (auto &OM : Operands) {
for (auto &OP : OM->predicates())
- if (isa<LLTOperandMatcher>(OP))
+ if (isa<LLTOperandMatcher>(OP) || isa<LLTOperandShapeMatcher>(OP))
Stash.push_back(std::move(OP));
OM->eraseNullPredicates();
}
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
index 4749139049861..77eabb0e1f73c 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
@@ -268,6 +268,7 @@ extern std::set<LLTCodeGen> KnownTypes;
/// Convert an MVT to an equivalent LLT if possible, or the invalid LLT() for
/// MVTs that don't map cleanly to an LLT (e.g., iPTR, *any, ...).
std::optional<LLTCodeGen> MVTToLLT(MVT VT);
+std::optional<LLTCodeGen> MVTToGenericLLT(MVT VT);
using TempTypeIdx = int64_t;
class LLTCodeGenOrTempType {
@@ -418,20 +419,26 @@ struct RecordAndValue {
};
class SwitchMatcher : public Matcher {
- /// All the nested matchers, representing distinct switch-cases. The first
- /// conditions (as Matcher::getFirstCondition() reports) of all the nested
- /// matchers must share the same type and path to a value they check, in other
- /// words, be isIdenticalDownToValue, but have different values they check
- /// against.
+ /// All the nested matchers, representing switch-cases. The first conditions
+ /// (as Matcher::getFirstCondition() reports) of all the nested matchers must
+ /// share the same type and path to a value they check, in other words, be
+ /// isIdenticalDownToValue. Multiple matchers can share the same value and are
+ /// bucketed together.
std::vector<Matcher *> Matchers;
/// The representative condition, with a type and a path (InsnVarID and OpIdx
- /// in most cases) shared by all the matchers contained.
+ /// in most cases) shared by all the matchers contained.
std::unique_ptr<PredicateMatcher> Condition;
- /// Temporary set used to check that the case values don't repeat within the
- /// same switch.
- std::set<RecordAndValue> Values;
+ struct Bucket {
+ RecordAndValue Value;
+ std::vector<Matcher *> Matchers;
+
+ explicit Bucket(RecordAndValue Value) : Value(std::move(Value)) {}
+ };
+
+ /// Buckets of matchers keyed by their case value.
+ std::map<int64_t, Bucket> Buckets;
/// An owning collection for any auxiliary matchers created while optimizing
/// nested matchers contained.
@@ -855,6 +862,7 @@ class PredicateMatcher {
OPM_Int,
OPM_LiteralInt,
OPM_LLT,
+ OPM_LLTShape,
OPM_PointerToAny,
OPM_RegBank,
OPM_MBB,
@@ -974,6 +982,12 @@ class LLTOperandMatcher : public OperandPredicateMatcher {
protected:
LLTCodeGen Ty;
+ LLTOperandMatcher(PredicateKind Kind, unsigned InsnVarID, unsigned OpIdx,
+ const LLTCodeGen &Ty)
+ : OperandPredicateMatcher(Kind, InsnVarID, OpIdx), Ty(Ty) {
+ KnownTypes.insert(Ty);
+ }
+
public:
static std::map<LLTCodeGen, unsigned> TypeIDValues;
@@ -986,9 +1000,7 @@ class LLTOperandMatcher : public OperandPredicateMatcher {
}
LLTOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const LLTCodeGen &Ty)
- : OperandPredicateMatcher(OPM_LLT, InsnVarID, OpIdx), Ty(Ty) {
- KnownTypes.insert(Ty);
- }
+ : LLTOperandMatcher(OPM_LLT, InsnVarID, OpIdx, Ty) {}
static bool classof(const PredicateMatcher *P) {
return P->getKind() == OPM_LLT;
@@ -1008,6 +1020,36 @@ class LLTOperandMatcher : public OperandPredicateMatcher {
RuleMatcher &Rule) const override;
};
+/// Generates code to check that the size of an MMO is exactly N bytes.
+class LLTOperandShapeMatcher : public LLTOperandMatcher {
+ static ElementCount getShapeElementCount(const LLT &Ty) {
+ return Ty.isVector() ? Ty.getElementCount() : ElementCount::getFixed(1);
+ }
+
+ static unsigned getShapeScalarSizeInBits(const LLT &Ty) {
+ return Ty.getScalarSizeInBits();
+ }
+
+public:
+ LLTOperandShapeMatcher(unsigned InsnVarID, unsigned OpIdx,
+ const LLTCodeGen &Ty)
+ : LLTOperandMatcher(OPM_LLTShape, InsnVarID, OpIdx, Ty) {}
+
+ static bool classof(const PredicateMatcher *P) {
+ return P->getKind() == OPM_LLTShape;
+ }
+
+ bool isIdentical(const PredicateMatcher &B) const override {
+ return OperandPredicateMatcher::isIdentical(B) &&
+ getShapeElementCount(Ty.get()) ==
+ getShapeElementCount(
+ cast<LLTOperandShapeMatcher>(&B)->Ty.get()) &&
+ getShapeScalarSizeInBits(Ty.get()) ==
+ getShapeScalarSizeInBits(
+ cast<LLTOperandShapeMatcher>(&B)->Ty.get());
+ }
+};
+
/// Generates code to check that an operand is a pointer to any address space.
///
/// In SelectionDAG, the types did not describe pointers or address spaces. As a
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index db5b1ebdb4219..7e585c1e74b69 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -275,6 +275,16 @@ static std::string getMangledRootDefName(StringRef DefOperandName) {
return ("DstI[" + DefOperandName + "]").str();
}
+static bool shouldUseGenericTypeForInstruction(const CodeGenInstruction *GI) {
+ if (!GI)
+ return false;
+
+ bool Unset = false;
+ bool ShouldMatchGeneric =
+ GI->TheDef->getValueAsBitOrUnset("GISelMatchGenericTypes", Unset);
+ return Unset ? false : ShouldMatchGeneric;
+}
+
//===- GlobalISelEmitter class --------------------------------------------===//
static Expected<LLTCodeGen> getInstResultType(const TreePatternNode &Dst,
@@ -379,12 +389,17 @@ class GlobalISelEmitter final : public GlobalISelMatchTableExecutorEmitter {
createAndImportSelDAGMatcher(RuleMatcher &Rule,
InstructionMatcher &InsnMatcher,
const TreePatternNode &Src, unsigned &TempOpIdx);
+ Error addTypeCheckPredicateForOpcode(OperandMatcher &OM,
+ const TypeSetByHwMode &VTy,
+ bool OperandIsAPointer,
+ const CodeGenInstruction *GI) const;
Error importComplexPatternOperandMatcher(OperandMatcher &OM, const Record *R,
unsigned &TempOpIdx) const;
Error importChildMatcher(RuleMatcher &Rule, InstructionMatcher &InsnMatcher,
const TreePatternNode &SrcChild,
bool OperandIsAPointer, bool OperandIsImmArg,
- unsigned OpIdx, unsigned &TempOpIdx);
+ const CodeGenInstruction *GI, unsigned OpIdx,
+ unsigned &TempOpIdx);
Expected<BuildMIAction &>
createAndImportInstructionRenderer(RuleMatcher &M,
@@ -738,6 +753,28 @@ Expected<InstructionMatcher &> GlobalISelEmitter::addBuiltinPredicates(
return InsnMatcher;
}
+Error GlobalISelEmitter::addTypeCheckPredicateForOpcode(
+ OperandMatcher &OM, const TypeSetByHwMode &VTy, bool OperandIsAPointer,
+ const CodeGenInstruction *GI) const {
+ // Pointer information is separate from the underlying MVT. Avoid losing it by
+ // forcing the regular path.
+ if (OperandIsAPointer || VTy.isPointer())
+ return OM.addTypeCheckPredicate(VTy, OperandIsAPointer);
+
+ if (LLT::getUseExtended() && shouldUseGenericTypeForInstruction(GI)) {
+ if (!VTy.isMachineValueType())
+ return failedImport("unsupported typeset");
+
+ auto GenericLLT = MVTToGenericLLT(VTy.getMachineValueType().SimpleTy);
+ if (GenericLLT) {
+ OM.addPredicate<LLTOperandShapeMatcher>(*GenericLLT);
+ return Error::success();
+ }
+ }
+
+ return OM.addTypeCheckPredicate(VTy, OperandIsAPointer);
+}
+
Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
RuleMatcher &Rule, InstructionMatcher &InsnMatcher,
const TreePatternNode &Src, unsigned &TempOpIdx) {
@@ -786,7 +823,8 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
const bool OperandIsAPointer =
SrcGIOrNull && SrcGIOrNull->isOutOperandAPointer(OpIdx);
OperandMatcher &OM = InsnMatcher.addOperand(OpIdx++, "", TempOpIdx);
- if (auto Error = OM.addTypeCheckPredicate(VTy, OperandIsAPointer))
+ if (auto Error = addTypeCheckPredicateForOpcode(OM, VTy, OperandIsAPointer,
+ SrcGIOrNull))
return failedImport(toString(std::move(Error)) +
" for result of Src pattern operator");
}
@@ -939,9 +977,9 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
OperandIsImmArg |= II->isParamImmArg(I - 1);
}
- if (auto Error =
- importChildMatcher(Rule, InsnMatcher, SrcChild, OperandIsAPointer,
- OperandIsImmArg, OpIdx++, TempOpIdx))
+ if (auto Error = importChildMatcher(Rule, InsnMatcher, SrcChild,
+ OperandIsAPointer, OperandIsImmArg,
+ SrcGIOrNull, OpIdx++, TempOpIdx))
return std::move(Error);
}
}
@@ -982,7 +1020,8 @@ static StringRef getSrcChildName(const TreePatternNode &SrcChild,
Error GlobalISelEmitter::importChildMatcher(
RuleMatcher &Rule, InstructionMatcher &InsnMatcher,
const TreePatternNode &SrcChild, bool OperandIsAPointer,
- bool OperandIsImmArg, unsigned OpIdx, unsigned &TempOpIdx) {
+ bool OperandIsImmArg, const CodeGenInstruction *GI, unsigned OpIdx,
+ unsigned &TempOpIdx) {
const Record *PhysReg = nullptr;
std::string SrcChildName = getSrcChildName(SrcChild, PhysReg).str();
@@ -1043,8 +1082,8 @@ Error GlobalISelEmitter::importChildMatcher(
// Immediate arguments have no meaningful type to check as they don't have
// registers.
if (!OperandIsImmArg) {
- if (auto Error =
- OM.addTypeCheckPredicate(ChildTypes.front(), OperandIsAPointer))
+ if (auto Error = addTypeCheckPredicateForOpcode(OM, ChildTypes.front(),
+ OperandIsAPointer, GI))
return failedImport(toString(std::move(Error)) + " for Src operand (" +
to_string(SrcChild) + ")");
}
>From 34e5736660faf11003c3be63c35629683f92ed1a Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Thu, 19 Feb 2026 13:45:04 +0000
Subject: [PATCH 19/30] Remove unused patterns post GIM_SwitchTypeShape change
& create generically types constants when converting an fconstant to a
constant
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 4 -
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 11 +--
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 91 ++-----------------
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 10 --
.../GISel/AArch64PostLegalizerLowering.cpp | 5 +-
.../AArch64/GlobalISel/inttoptr_add.ll | 4 +-
.../GlobalISel/load-addressing-modes.mir | 7 +-
.../CodeGen/AArch64/GlobalISel/select-dup.mir | 4 +-
.../GlobalISel/store-addressing-modes.mir | 10 +-
.../CodeGen/AArch64/arm64-arith-saturating.ll | 9 +-
llvm/test/CodeGen/AArch64/insertextract.ll | 6 +-
.../CodeGen/AArch64/neon-extadd-extract.ll | 2 +-
.../CodeGen/AArch64/neon-insextbitcast.ll | 24 ++---
13 files changed, 39 insertions(+), 148 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index c2e1e883a0039..406ac2fa62df2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -174,10 +174,6 @@ def extract_high_v4f32 :
def extract_high_v2f64 :
ComplexPattern<v1f64, 1, "SelectExtractHigh", [extract_subvector, bitconvert]>;
-def gi_extract_high_v8bf16 :
- GIComplexOperandMatcher<v4s16, "selectExtractHigh">,
- GIComplexPatternEquiv<extract_high_v8bf16>;
-
def gi_extract_high_v8f16 :
GIComplexOperandMatcher<v4s16, "selectExtractHigh">,
GIComplexPatternEquiv<extract_high_v8f16>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 63d9a37514fa6..47f89090352b5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -79,6 +79,7 @@ def G_DUP: AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$lane);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Represents a lane duplicate operation.
@@ -551,18 +552,10 @@ let AddedComplexity = 19 in {
defm : VecStoreLane64_0Pat<am_indexed16, store, v4i16, i16, hsub, uimm12s2, STRHui>;
defm : VecStoreLane64_0Pat<am_indexed32, store, v2i32, i32, ssub, uimm12s4, STRSui>;
- defm : VecStoreLane64_0Pat<am_indexed16, store, v4f16, f16, hsub, uimm12s2, STRHui>;
- defm : VecStoreLane64_0Pat<am_indexed32, store, v2f32, f32, ssub, uimm12s4, STRSui>;
-
defm : VecStoreULane64_0Pat<store, v4i16, i16, hsub, STURHi>;
defm : VecStoreULane64_0Pat<store, v2i32, i32, ssub, STURSi>;
defm : VecROStoreLane64_0Pat<ro16, store, v4i16, i16, hsub, STRHroW, STRHroX>;
defm : VecROStoreLane64_0Pat<ro32, store, v2i32, i32, ssub, STRSroW, STRSroX>;
-
- defm : VecStoreULane64_0Pat<store, v4f16, f16, hsub, STURHi>;
- defm : VecStoreULane64_0Pat<store, v2f32, f32, ssub, STURSi>;
- defm : VecROStoreLane64_0Pat<ro16, store, v4f16, f16, hsub, STRHroW, STRHroX>;
- defm : VecROStoreLane64_0Pat<ro32, store, v2f32, f32, ssub, STRSroW, STRSroX>;
}
def : Pat<(v8i8 (AArch64dup (i8 (load GPR64sp:$Rn)))),
@@ -581,5 +574,3 @@ def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
(LD1Rv2d GPR64sp:$Rn)>;
def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
(LD1Rv1d GPR64sp:$Rn)>;
-
-def : Pat<(f64 (bitconvert (i64 0))), (FMOVD0)>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 1b5920a7b6c06..ab304744087f9 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4433,10 +4433,6 @@ defm : LoadInsertPatterns<extloadi16, v8i16, v4i16, nxv8i16, i32,
vec_ins_or_scal_vec, vec_ins_or_scal_vec,
LDRHui, LDURHi, LDRHroW, LDRHroX,
ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
-defm : LoadInsertPatterns<load, v8i16, v4i16, nxv8i16, i16,
- vec_ins_or_scal_vec, vec_ins_or_scal_vec,
- LDRHui, LDURHi, LDRHroW, LDRHroX,
- ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
defm : LoadInsertPatterns<load, v4i32, v2i32, nxv4i32, i32,
vec_ins_or_scal_vec_v4f32, vec_ins_or_scal_vec_v2f32,
LDRSui, LDURSi, LDRSroW, LDRSroX,
@@ -4719,15 +4715,6 @@ let Predicates = [UseSTRQro], AddedComplexity = 10 in {
(ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
ro_Xextend128:$extend)),
(STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>;
-
- def : Pat<(store (v2i64 FPR128:$Rt),
- (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
- ro_Wextend128:$extend)),
- (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>;
- def : Pat<(store (v2i64 FPR128:$Rt),
- (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
- ro_Xextend128:$extend)),
- (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>;
}
multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
@@ -4811,7 +4798,6 @@ multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
let AddedComplexity = 19 in {
defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, f16, hsub, STRHroW, STRHroX>;
- defm : VecROStoreLane0Pat<ro16, store, v8i16, i16, f16, hsub, STRHroW, STRHroX>;
defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, f16, hsub, STRHroW, STRHroX>;
defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, i32, ssub, STRSroW, STRSroX>;
defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, i32, ssub, STRSroW, STRSroX>;
@@ -4968,7 +4954,6 @@ multiclass VecStoreLane0Pat<ComplexPattern UIAddrMode, SDPatternOperator storeop
let AddedComplexity = 19 in {
defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, f16, hsub, uimm12s2, STRHui>;
- defm : VecStoreLane0Pat<am_indexed16, store, v8i16, i16, f16, hsub, uimm12s2, STRHui>;
defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, f16, hsub, uimm12s2, STRHui>;
defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, i32, ssub, uimm12s4, STRSui>;
defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, i32, ssub, uimm12s4, STRSui>;
@@ -5122,7 +5107,6 @@ multiclass VecStoreULane0Pat<SDPatternOperator StoreOp,
let AddedComplexity = 19 in {
defm : VecStoreULane0Pat<truncstorei16, v8i16, i32, f16, hsub, STURHi>;
- defm : VecStoreULane0Pat<store, v8i16, i16, f16, hsub, STURHi>;
defm : VecStoreULane0Pat<store, v8f16, f16, f16, hsub, STURHi>;
defm : VecStoreULane0Pat<store, v4i32, i32, i32, ssub, STURSi>;
defm : VecStoreULane0Pat<store, v4f32, f32, i32, ssub, STURSi>;
@@ -7849,31 +7833,6 @@ def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
-def : Pat<(v4i32 (AArch64dup (i32 FPR32:$src))),
- (v4i32 (DUPv4i32lane
- (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$src, ssub),
- (i64 0)))>;
-
-def : Pat<(v2i64 (AArch64dup (i64 FPR64:$Rn))),
- (v2i64 (DUPv2i64lane
- (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
- (i64 0)))>;
-
-def : Pat<(v2i32 (AArch64dup (i32 FPR32:$Rn))),
- (v2i32 (DUPv2i32lane
- (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
- (i64 0)))>;
-
-def : Pat<(v4i16 (AArch64dup (i16 FPR16:$Rn))),
- (v4i16 (DUPv4i16lane
- (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
- (i64 0)))>;
-
-def : Pat<(v8i16 (AArch64dup (i16 FPR16:$Rn))),
- (v8i16 (DUPv8i16lane
- (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
- (i64 0)))>;
-
// DUP from a 64-bit register to a 64-bit register is just a copy
def : Pat<(v1i64 (AArch64dup (i64 GPR64:$Rn))),
(COPY_TO_REGCLASS GPR64:$Rn, FPR64)>;
@@ -8054,11 +8013,6 @@ def : Pat<(v4i32 (vec_ins_or_scal_vec GPR32:$Rn)),
def : Pat<(v2i64 (vec_ins_or_scal_vec GPR64:$Rn)),
(INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GPR64:$Rn, dsub)>;
-def : Pat<(v2i32 (vec_ins_or_scal_vec i32:$Rn)),
- (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GPR32:$Rn, ssub)>;
-def : Pat<(v2i64 (vec_ins_or_scal_vec i64:$Rn)),
- (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GPR64:$Rn, dsub)>;
-
def : Pat<(v4f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),
(INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
def : Pat<(v8f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),
@@ -8084,9 +8038,6 @@ def : Pat<(v4f32 (vec_ins_or_scal_vec (f32 FPR32:$Rn))),
def : Pat<(v2f32 (vec_ins_or_scal_vec (f32 FPR32:$Rn))),
(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
-def : Pat<(v4i32 (vec_ins_or_scal_vec (i32 FPR32:$Rn))),
- (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
-
def : Pat<(v2f64 (vec_ins_or_scal_vec (f64 FPR64:$Rn))),
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
@@ -8113,29 +8064,6 @@ def : Pat<(vector_insert v2f64:$Rn, (f64 fpimm0), (i64 VectorIndexD:$imm)),
(INSvi64gpr V128:$Rn, VectorIndexS:$imm, XZR)>;
}
-def : Pat<(v8i16 (vector_insert (v8i16 V128:$Rn),
- (i16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
- (INSvi16lane
- V128:$Rn, VectorIndexH:$imm,
- (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
- (i64 0))>;
-
-def : Pat<(v4i16 (vector_insert (v4i16 V64:$Rn),
- (i16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
- (EXTRACT_SUBREG
- (INSvi16lane
- (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
- VectorIndexH:$imm,
- (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
- (i64 0)),
- dsub)>;
-
-def : Pat<(v4i16 (vector_insert (v4i16 V64:$Rn), (i32 GPR32:$Rm), (i64 VectorIndexH:$imm))),
- (EXTRACT_SUBREG
- (INSvi16gpr (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
- VectorIndexH:$imm, GPR32:$Rm),
- dsub)>;
-
def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
(f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
(INSvi16lane
@@ -8300,24 +8228,21 @@ defm : Neon_INS_elt_pattern<v2f64, v1f64, nxv2f64, f64, VectorIndexD, INSvi6
// Accept i8 scalar argument in GlobalISel.
defm : Neon_INS_elt_pattern<v16i8, v8i8, nxv16i8, i8, VectorIndexB, INSvi8lane, DUPi8, bsub>;
defm : Neon_INS_elt_pattern<v16i8, v8i8, nxv16i8, i32, VectorIndexB, INSvi8lane, DUPi8, bsub>;
-defm : Neon_INS_elt_pattern<v8i16, v4i16, nxv8i16, i16, VectorIndexH, INSvi16lane, DUPi16, hsub>;
defm : Neon_INS_elt_pattern<v8i16, v4i16, nxv8i16, i32, VectorIndexH, INSvi16lane, DUPi16, hsub>;
defm : Neon_INS_elt_pattern<v4i32, v2i32, nxv4i32, i32, VectorIndexS, INSvi32lane, DUPi32, ssub>;
defm : Neon_INS_elt_pattern<v2i64, v1i64, nxv2i64, i64, VectorIndexD, INSvi64lane, DUPi64, dsub>;
// Insert from bitcast
-// vector_insert(i32, n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)
-def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 FPR32:$Sn), (i64 imm:$Immd))),
- (INSvi32lane V128:$src, imm:$Immd,
- (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>;
-def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 FPR32:$Sn), (i64 imm:$Immd))),
+// vector_insert(bitcast(f32 src), n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)
+def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),
+ (INSvi32lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>;
+def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),
(EXTRACT_SUBREG
(INSvi32lane (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$src, dsub)),
imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0),
dsub)>;
-def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 FPR64:$Sn), (i64 imm:$Immd))),
- (INSvi64lane V128:$src, imm:$Immd,
- (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>;
+def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), (i64 imm:$Immd))),
+ (INSvi64lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>;
// Patterns for i8/i16 -> v2i32/v4i16 lane moves via insert and extract that go via i32.
multiclass Neon_INS_elt_ext_pattern<ValueType VT128, ValueType VT64, ValueType OutVT,
@@ -9924,7 +9849,6 @@ class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
// Accept i8 scalar argument in GlobalISel.
def : Ld1Lane128Pat<load, VectorIndexB, v16i8, i8, LD1i8>;
def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
-def : Ld1Lane128Pat<load, VectorIndexH, v8i16, i16, LD1i16>;
def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
@@ -10001,7 +9925,6 @@ class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
// Accept i8 scalar argument in GlobalISel.
def : Ld1Lane64Pat<load, VectorIndexB, v8i8, i8, LD1i8>;
def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
-def : Ld1Lane64Pat<load, VectorIndexH, v4i16, i16, LD1i16>;
def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
@@ -10030,7 +9953,6 @@ class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
-def : St1Lane128Pat<store, VectorIndexH, v8i16, i16, ST1i16>;
def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
@@ -10049,7 +9971,6 @@ class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
-def : St1Lane64Pat<store, VectorIndexH, v4i16, i16, ST1i16>;
def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index d71ce27a145a9..436f50fe451be 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3612,14 +3612,6 @@ let Predicates = [HasSVE_or_SME] in {
def : Pat<(f64 (vector_extract nxv2f64:$vec, GPR64:$index)),
(LASTB_VPZ_D (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>;
- // LASTB_RPZ_* expect a GPR destination register, LASTB_VPZ_* expect FPR destination registers
- def : Pat<(i16 (vector_extract nxv8i16:$vec, GPR64:$index)),
- (LASTB_VPZ_H (WHILELS_PXX_H XZR, GPR64:$index), ZPR:$vec)>;
- def : Pat<(i32 (vector_extract nxv4i32:$vec, GPR64:$index)),
- (LASTB_VPZ_S (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>;
- def : Pat<(i64 (vector_extract nxv2i64:$vec, GPR64:$index)),
- (LASTB_VPZ_D (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>;
-
// Extract element from vector with immediate index
def : Pat<(i32 (vector_extract nxv16i8:$vec, sve_elm_idx_extdup_b:$index)),
(EXTRACT_SUBREG (DUP_ZZI_B ZPR:$vec, sve_elm_idx_extdup_b:$index), ssub)>;
@@ -3716,8 +3708,6 @@ let Predicates = [HasSVE_or_SME] in {
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
def : Pat<(i32 (vector_extract nxv8i16:$Zs, (i64 0))),
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
- def : Pat<(i16 (vector_extract nxv8i16:$Zs, (i64 0))),
- (EXTRACT_SUBREG ZPR:$Zs, hsub)>;
def : Pat<(i32 (vector_extract nxv4i32:$Zs, (i64 0))),
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
def : Pat<(i64 (vector_extract nxv2i64:$Zs, (i64 0))),
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 3b487f55193c1..df3bf59305385 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -96,7 +96,10 @@ void applyFConstantToConstant(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT);
MachineIRBuilder MIB(MI);
const APFloat &ImmValAPF = MI.getOperand(1).getFPImm()->getValueAPF();
- MIB.buildConstant(MI.getOperand(0).getReg(), ImmValAPF.bitcastToAPInt());
+ const Register DstReg = MI.getOperand(0).getReg();
+ const LLT DstTy = MIB.getMRI()->getType(DstReg);
+ MIB.getMRI()->setType(DstReg, LLT::scalar(DstTy.getSizeInBits()));
+ MIB.buildConstant(DstReg, ImmValAPF.bitcastToAPInt());
MI.eraseFromParent();
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll b/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
index 21402fade53dd..a7b555745d149 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
@@ -4,9 +4,9 @@
define dso_local void @fn() {
; CHECK-LABEL: fn:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #4132 // =0x1024
+; CHECK-NEXT: mov x8, #4132 // =0x1024
; CHECK-NEXT: mov w9, #1 // =0x1
-; CHECK-NEXT: movk w8, #65489, lsl #16
+; CHECK-NEXT: movk x8, #65489, lsl #16
; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
index 140543c4ea390..2aee1bbc8ddd4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
@@ -884,11 +884,10 @@ body: |
; CHECK-LABEL: name: ldrsrox
; CHECK: liveins: $d0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $d0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADDXrr]], 0 :: (load (s32) from %ir.addr)
- ; CHECK-NEXT: $s2 = COPY [[LDRSui]]
+ ; CHECK-NEXT: [[LDRSroX:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], [[COPY1]], 0, 0 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: $s2 = COPY [[LDRSroX]]
; CHECK-NEXT: RET_ReallyLR implicit $h2
%0:gpr(p0) = COPY $d0
%1:gpr(s64) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
index 7c2fcb568754d..2a7a50a5597a7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
@@ -444,9 +444,7 @@ body: |
; CHECK-LABEL: name: cst_v2p0
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
- ; CHECK-NEXT: %cst:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %cst
+ ; CHECK-NEXT: %cst:gpr64 = MOVi64imm 3
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
index 894cf33aa182a..94af12a91ae97 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
@@ -124,11 +124,10 @@ body: |
; CHECK-LABEL: name: strsrox
; CHECK: liveins: $x0, $x1, $s2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK-NEXT: %ptr:gpr64common = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s2
- ; CHECK-NEXT: STRSui [[COPY2]], %ptr, 0 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: STRSroX [[COPY2]], [[COPY]], [[COPY1]], 0, 0 :: (store (s32) into %ir.addr)
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = COPY $x1
%ptr:gpr(p0) = G_PTR_ADD %0, %1
@@ -148,11 +147,10 @@ body: |
; CHECK-LABEL: name: strhrox
; CHECK: liveins: $x0, $x1, $h0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK-NEXT: %ptr:gpr64common = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK-NEXT: STRHui [[COPY2]], %ptr, 0 :: (store (s16) into %ir.addr)
+ ; CHECK-NEXT: STRHroX [[COPY2]], [[COPY]], [[COPY1]], 0, 0 :: (store (s16) into %ir.addr)
%0:gpr(p0) = COPY $x0
%1:gpr(s64) = COPY $x1
%ptr:gpr(p0) = G_PTR_ADD %0, %1
diff --git a/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll b/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll
index 16a53fa089857..07c4dbcf41096 100644
--- a/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-arith-saturating.ll
@@ -208,8 +208,7 @@ define <4 x i32> @sqxtn_ins(<4 x i32> noundef %a, i64 %c) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d1, x0
; CHECK-NEXT: sqxtn s1, d1
-; CHECK-NEXT: fmov w8, s1
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: mov v0.s[3], v1.s[0]
; CHECK-NEXT: ret
entry:
%vqmovnd_s64.i = tail call i32 @llvm.aarch64.neon.scalar.sqxtn.i32.i64(i64 %c)
@@ -222,8 +221,7 @@ define <4 x i32> @sqxtun_insext(<4 x i32> noundef %a, <2 x i64> %e) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: sqxtun s1, d1
-; CHECK-NEXT: fmov w8, s1
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: mov v0.s[3], v1.s[0]
; CHECK-NEXT: ret
entry:
%c = extractelement <2 x i64> %e, i64 1
@@ -237,8 +235,7 @@ define <4 x i32> @saddluse(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 %c, f
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: saddlv d1, v1.4s
; CHECK-NEXT: sqxtn s1, d1
-; CHECK-NEXT: fmov w8, s1
-; CHECK-NEXT: mov v0.s[1], w8
+; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: ret
entry:
%vaddlvq_s32.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> %b)
diff --git a/llvm/test/CodeGen/AArch64/insertextract.ll b/llvm/test/CodeGen/AArch64/insertextract.ll
index 49e87de5ab6f9..977b31569d7d7 100644
--- a/llvm/test/CodeGen/AArch64/insertextract.ll
+++ b/llvm/test/CodeGen/AArch64/insertextract.ll
@@ -2887,20 +2887,18 @@ define i128 @extract_v2i128_c(<2 x i128> %a, i32 %c) {
; CHECK-GI-NEXT: .cfi_offset w30, -8
; CHECK-GI-NEXT: .cfi_offset w29, -16
; CHECK-GI-NEXT: adds x8, x0, x0
-; CHECK-GI-NEXT: mov x10, sp
; CHECK-GI-NEXT: adc x9, x1, x1
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: adds x8, x2, x2
; CHECK-GI-NEXT: mov v1.d[0], x8
; CHECK-GI-NEXT: adc x8, x3, x3
; CHECK-GI-NEXT: mov v0.d[1], x9
-; CHECK-GI-NEXT: mov w9, #16 // =0x10
+; CHECK-GI-NEXT: mov x9, sp
; CHECK-GI-NEXT: mov v1.d[1], x8
; CHECK-GI-NEXT: mov w8, w4
; CHECK-GI-NEXT: and x8, x8, #0x1
-; CHECK-GI-NEXT: umaddl x8, w8, w9, x10
; CHECK-GI-NEXT: stp q0, q1, [sp]
-; CHECK-GI-NEXT: ldr q0, [x8]
+; CHECK-GI-NEXT: ldr q0, [x9, x8, lsl #4]
; CHECK-GI-NEXT: mov d1, v0.d[1]
; CHECK-GI-NEXT: fmov x0, d0
; CHECK-GI-NEXT: fmov x1, d1
diff --git a/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll b/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
index b35511dd4ab69..5753798e87512 100644
--- a/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
+++ b/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
@@ -786,7 +786,7 @@ define <2 x i8> @extract_scalable_vec() vscale_range(1,16) "target-features"="+s
; CHECK-GI-LABEL: extract_scalable_vec:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov x8, xzr
-; CHECK-GI-NEXT: mov w9, #1 // =0x1
+; CHECK-GI-NEXT: mov x9, #1 // =0x1
; CHECK-GI-NEXT: ld1 { v0.b }[0], [x8]
; CHECK-GI-NEXT: ldr b1, [x9]
; CHECK-GI-NEXT: adrp x8, .LCPI36_0
diff --git a/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll b/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
index 2191b67fc816a..d9cdbc2f92aca 100644
--- a/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
+++ b/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
@@ -4,8 +4,8 @@
define <4 x i32> @test_vins_v4i32(<4 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v4i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov w8, s1
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: mov v0.s[3], v1.s[0]
; CHECK-NEXT: ret
entry:
%c = bitcast float %b to i32
@@ -16,8 +16,8 @@ entry:
define <4 x i32> @test_vins_v4i32_0(<4 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v4i32_0:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov w8, s1
-; CHECK-NEXT: mov v0.s[0], w8
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: mov v0.s[0], v1.s[0]
; CHECK-NEXT: ret
entry:
%c = bitcast float %b to i32
@@ -28,9 +28,9 @@ entry:
define <2 x i32> @test_vins_v2i32(<2 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v2i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov v0.s[1], w8
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
@@ -42,9 +42,9 @@ entry:
define <2 x i32> @test_vins_v2i32_0(<2 x i32> %a, float %b) {
; CHECK-LABEL: test_vins_v2i32_0:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov v0.s[0], w8
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: mov v0.s[0], v1.s[0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
@@ -56,8 +56,8 @@ entry:
define <2 x i64> @test_vins_v2i64(<2 x i64> %a, double %b) {
; CHECK-LABEL: test_vins_v2i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov x8, d1
-; CHECK-NEXT: mov v0.d[1], x8
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: ret
entry:
%c = bitcast double %b to i64
@@ -68,8 +68,8 @@ entry:
define <2 x i64> @test_vins_v2i64_0(<2 x i64> %a, double %b) {
; CHECK-LABEL: test_vins_v2i64_0:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fmov x8, d1
-; CHECK-NEXT: mov v0.d[0], x8
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[0], v1.d[0]
; CHECK-NEXT: ret
entry:
%c = bitcast double %b to i64
>From 510aa0fc3f776b9153a096e22c45462fb0a08529 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Thu, 19 Feb 2026 16:25:42 +0000
Subject: [PATCH 20/30] Revert "Add combine to store an i128 as a v2i64 when
selecting a store that can use register-indirect-offset addressing mode."
This reverts commit b491f2ea92e819db660a4665f6f8d41051be7b5f.
---
llvm/lib/Target/AArch64/AArch64Combine.td | 9 +--
.../GISel/AArch64PostLegalizerLowering.cpp | 81 -------------------
llvm/test/CodeGen/AArch64/insertextract.ll | 2 +-
3 files changed, 2 insertions(+), 90 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 7905f93a32d62..fe953a627939d 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -200,13 +200,6 @@ def vector_unmerge_lowering : GICombineRule <
(apply [{ applyScalarizeVectorUnmerge(*${root}, MRI, B); }])
>;
-def store_i128_as_v2i64 : GICombineRule <
- (defs root:$root),
- (match (wip_match_opcode G_STORE):$root,
- [{ return matchStorei128AsV2i64(*${root}, MRI); }]),
- (apply [{ applyStorei128AsV2i64(*${root}, MRI, B); }])
->;
-
def adjust_icmp_imm_matchdata :
GIDefMatchData<"std::pair<uint64_t, CmpInst::Predicate>">;
def adjust_icmp_imm : GICombineRule <
@@ -359,7 +352,7 @@ def AArch64PostLegalizerLowering
lower_vector_fcmp, form_truncstore, fconstant_to_constant,
vector_sext_inreg_to_shift,
unmerge_ext_to_unmerge, lower_mulv2s64,
- vector_unmerge_lowering, insertelt_nonconst, store_i128_as_v2i64,
+ vector_unmerge_lowering, insertelt_nonconst,
unmerge_duplanes]> {
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index df3bf59305385..c15e735912f91 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -709,87 +709,6 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
return std::nullopt;
}
-// Helper function for matchStorei128AsV2i64. This aids in finding pointers that
-// can use the register-indirect-offset addressing mode
-bool isPointerRoX(const MachineRegisterInfo &MRI, llvm::GStore *&Store) {
- auto Ptr = Store->getPointerReg();
- auto *PtrAdd = getOpcodeDef<GPtrAdd>(Ptr, MRI);
- if (!PtrAdd || !MRI.hasOneNonDBGUse(Ptr))
- return false;
-
- Register Offset = PtrAdd->getOperand(2).getReg();
- if (auto C = getIConstantVRegValWithLookThrough(Offset, MRI))
- return false;
-
- auto *OffsetDef = getDefIgnoringCopies(Offset, MRI);
- if (!OffsetDef)
- return false;
-
- if (OffsetDef->getOpcode() == TargetOpcode::G_SHL ||
- OffsetDef->getOpcode() == TargetOpcode::G_MUL) {
- auto MaybeImm = getIConstantVRegValWithLookThrough(
- OffsetDef->getOperand(2).getReg(), MRI);
-
- if (!MaybeImm)
- return false;
-
- uint64_t Shift = OffsetDef->getOpcode() == TargetOpcode::G_SHL
- ? MaybeImm->Value.getZExtValue()
- : Log2_64(MaybeImm->Value.getZExtValue());
-
- if (Shift != Log2_32(16))
- return false;
- }
- return true;
-}
-
-// FPR128 doesn't allow i128 but it does allow v2i64. This means we can't
-// duplicate the pattern for f128 used here (AArch64InstrInfo.td:4617 STRQroX).
-// Instead, we can detect when this instruction would be used and force the
-// types to be a v2i64 thus allowing matching.
-bool matchStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI) {
- assert(MI.getOpcode() == TargetOpcode::G_STORE &&
- "Expected a store instruction");
-
- auto *Store = cast<GStore>(&MI);
- Register ValReg = Store->getValueReg();
- LLT ValTy = MRI.getType(ValReg);
-
- if (!ValTy.isInteger() && ValTy.getScalarSizeInBits() != 128)
- return false;
-
- auto *Merge = getOpcodeDef<GMerge>(ValReg, MRI);
- if (!Merge || Merge->getNumSources() != 2)
- return false;
-
- if (!MRI.hasOneNonDBGUse(ValReg))
- return false;
-
- auto MergeUser = MRI.use_instr_nodbg_begin(ValReg);
- if (MergeUser == MRI.use_instr_nodbg_end() || &*MergeUser != &MI)
- return false;
-
- if (MRI.getType(Merge->getSourceReg(0)).getScalarSizeInBits() != 64 ||
- MRI.getType(Merge->getSourceReg(1)).getScalarSizeInBits() != 64)
- return false;
-
- return isPointerRoX(MRI, Store);
-}
-
-void applyStorei128AsV2i64(MachineInstr &MI, const MachineRegisterInfo &MRI,
- MachineIRBuilder &MIB) {
- auto *Store = cast<GStore>(&MI);
- Register ValReg = Store->getValueReg();
-
- auto *Merge = getOpcodeDef<GMerge>(ValReg, MRI);
-
- auto BV =
- MIB.buildBuildVector(LLT::fixed_vector(2, LLT::buildInteger(64)),
- {Merge->getSourceReg(0), Merge->getSourceReg(1)})
- .getReg(0);
- MI.getOperand(0).setReg(BV);
-}
-
/// Determine whether or not it is possible to update the RHS and predicate of
/// a G_ICMP instruction such that the RHS will be selected as an arithmetic
/// immediate.
diff --git a/llvm/test/CodeGen/AArch64/insertextract.ll b/llvm/test/CodeGen/AArch64/insertextract.ll
index 977b31569d7d7..641701beeda43 100644
--- a/llvm/test/CodeGen/AArch64/insertextract.ll
+++ b/llvm/test/CodeGen/AArch64/insertextract.ll
@@ -1390,7 +1390,7 @@ define <2 x i128> @insert_v2i128_c(<2 x i128> %a, i128 %b, i32 %c) {
; CHECK-GI-NEXT: .cfi_offset w30, -8
; CHECK-GI-NEXT: .cfi_offset w29, -16
; CHECK-GI-NEXT: adds x8, x0, x0
-; CHECK-GI-NEXT: fmov d2, x4
+; CHECK-GI-NEXT: mov v2.d[0], x4
; CHECK-GI-NEXT: adc x9, x1, x1
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: adds x8, x2, x2
>From 391575dedeec528a74221f3fe7661815ee694609 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 23 Feb 2026 10:29:05 +0000
Subject: [PATCH 21/30] Fix incorrect matching of generic scalars in
convertBF16 & avoid calling markAllIdxsAsCovered
---
llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index 98b1106ff337e..438076440efa2 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -879,13 +879,16 @@ class LegalizeRuleSet {
"convertBF16 expects a floating-point scalar promotion type");
typeIdx(TypeIdx);
const LLT BF16Ty = LLT::bfloat16();
- return widenScalarIf(
+ return actionIf(
+ LegalizeAction::WidenScalar,
[=](const LegalityQuery &Query) {
if (TypeIdx >= Query.Types.size())
return false;
const LLT Ty = Query.Types[TypeIdx];
if (!Ty.isValid())
return false;
+ if (Ty.isAnyScalar() || Ty.isAnyVector())
+ return false;
if (Ty == BF16Ty)
return true;
if (Ty.isVector() && Ty.getElementType() == BF16Ty)
>From 61b1b433776bb9d74c728eb04e12cb44224a9114 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 23 Feb 2026 11:48:25 +0000
Subject: [PATCH 22/30] Add GISelMatchGenericTypes to additional opcodes
---
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 47f89090352b5..7c02a7437ba68 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -31,6 +31,7 @@ def G_REV32 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Pseudo for a rev64 instruction. Produced post-legalization from
@@ -39,6 +40,7 @@ def G_REV64 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Represents an uzp1 instruction. Produced post-legalization from
@@ -47,6 +49,7 @@ def G_UZP1 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$v1, type0:$v2);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Represents an uzp2 instruction. Produced post-legalization from
@@ -55,6 +58,7 @@ def G_UZP2 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$v1, type0:$v2);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Represents a zip1 instruction. Produced post-legalization from
@@ -63,6 +67,7 @@ def G_ZIP1 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$v1, type0:$v2);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Represents a zip2 instruction. Produced post-legalization from
@@ -71,6 +76,7 @@ def G_ZIP2 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$v1, type0:$v2);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Represents a dup instruction. Produced post-legalization from
@@ -110,6 +116,7 @@ def G_TRN1 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$v1, type0:$v2);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Represents a trn2 instruction. Produced post-legalization from
@@ -118,6 +125,7 @@ def G_TRN2 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$v1, type0:$v2);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Represents an ext instruction. Produced post-legalization from
@@ -126,6 +134,7 @@ def G_EXT: AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$v1, type0:$v2, untyped_imm_0:$imm);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Represents a vector G_ASHR with an immediate.
@@ -287,6 +296,7 @@ def G_BSP : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
def : GINodeEquiv<G_REV32, AArch64rev32>;
>From d19fce7a4583d347a9ee43dad7423bae04568d73 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 23 Feb 2026 11:49:22 +0000
Subject: [PATCH 23/30] Update type references, remove HasBF16 check from
convertBF16 & remove unnecessary legalFor.
---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 185 +++++++++---------
1 file changed, 93 insertions(+), 92 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 6355a81de64ed..930af91eb9cfa 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -67,20 +67,32 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
const LLT bf16 = LLT::bfloat16();
const LLT v4bf16 = LLT::fixed_vector(4, bf16);
- const LLT v8bf16 = LLT::fixed_vector(8, bf16);
- const LLT fp16 = LLT::float16();
- const LLT v4fp16 = LLT::fixed_vector(4, fp16);
- const LLT v8fp16 = LLT::fixed_vector(8, fp16);
+ const LLT f16 = LLT::float16();
+ const LLT v4f16 = LLT::fixed_vector(4, f16);
+ const LLT v8f16 = LLT::fixed_vector(8, f16);
- const LLT fp32 = LLT::float32();
- const LLT v2fp32 = LLT::fixed_vector(2, fp32);
- const LLT v4fp32 = LLT::fixed_vector(4, fp32);
+ const LLT f32 = LLT::float32();
+ const LLT v2f32 = LLT::fixed_vector(2, f32);
+ const LLT v4f32 = LLT::fixed_vector(4, f32);
- const LLT fp64 = LLT::float64();
- const LLT v2fp64 = LLT::fixed_vector(2, fp64);
+ const LLT f64 = LLT::float64();
+ const LLT v2f64 = LLT::fixed_vector(2, f64);
- const LLT fp128 = LLT::float128();
+ const LLT f128 = LLT::float128();
+
+ const LLT i16 = LLT::integer(16);
+ const LLT v8i16 = LLT::fixed_vector(8, i16);
+ const LLT v4i16 = LLT::fixed_vector(4, i16);
+
+ const LLT i32 = LLT::integer(32);
+ const LLT v2i32 = LLT::fixed_vector(2, i32);
+ const LLT v4i32 = LLT::fixed_vector(4, i32);
+
+ const LLT i64 = LLT::integer(64);
+ const LLT v2i64 = LLT::fixed_vector(2, i64);
+
+ const LLT i128 = LLT::integer(128);
std::initializer_list<LLT> PackedVectorAllTypeList = {/* Begin 128bit types */
v16s8, v8s16, v4s32,
@@ -103,7 +115,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// Some instructions only support s16 if the subtarget has full 16-bit FP
// support.
const bool HasFP16 = ST.hasFullFP16();
- const LLT &MinFPScalar = HasFP16 ? fp16 : fp32;
+ const LLT &MinFPScalar = HasFP16 ? f16 : f32;
const bool HasBF16 = ST.hasBF16();
@@ -116,8 +128,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalFor({p0, s8, s16, s32, s64})
.legalFor({v2s8, v4s8, v8s8, v16s8, v2s16, v4s16, v8s16, v2s32, v4s32,
v2s64, v2p0})
- .legalFor(HasBF16, {bf16})
- .legalFor(HasBF16, {v4bf16})
.widenScalarToNextPow2(0)
.clampScalar(0, s8, s64)
.moreElementsToNextPow2(0)
@@ -429,10 +439,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FSQRT, G_FMAXNUM, G_FMINNUM,
G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR, G_FRINT, G_FNEARBYINT,
G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN})
- .legalFor({fp32, fp64, v2fp32, v4fp32, v2fp64})
- .convertBF16(HasBF16)
- .legalFor(HasFP16, {fp16, s16, v4s16, v8s16})
- .libcallFor({fp128})
+ .legalFor({f32, f64, v2f32, v4f32, v2f64})
+ .convertBF16()
+ .legalFor(HasFP16, {f16, s16, v4s16, v8s16})
+ .libcallFor({f128})
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.minScalarOrElt(0, MinFPScalar)
.clampNumElements(0, v4s16, v8s16)
@@ -441,20 +451,21 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.moreElementsToNextPow2(0);
getActionDefinitionsBuilder({G_FABS, G_FNEG})
- .legalFor({fp32, fp64, v2fp32, v4fp32, v2fp64})
- .legalFor(HasFP16, {fp16, v4fp16, v8fp16})
+ .legalFor({f32, f64, v2f32, v4f32, v2f64})
+ .legalFor(HasFP16, {f16, v4f16, v8f16})
+ .convertBF16()
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.lowerIf(scalarOrEltWiderThan(0, 64))
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.moreElementsToNextPow2(0)
- .lowerFor({fp16, v4fp16, v8fp16});
+ .lowerFor({f16, v4f16, v8f16});
getActionDefinitionsBuilder(G_FREM)
- .libcallFor({fp32, fp64, fp128})
- .convertBF16(HasBF16)
- .minScalar(0, fp32)
+ .libcallFor({f32, f64, f128})
+ .convertBF16()
+ .minScalar(0, f32)
.scalarize(0);
getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FPOW, G_FLOG, G_FLOG2,
@@ -463,15 +474,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
G_FSINH, G_FTANH, G_FMODF})
// We need a call for these, so we always need to scalarize.
.scalarize(0)
- .convertBF16(HasBF16)
+ .convertBF16()
// Regardless of FP16 support, widen 16-bit elements to 32-bits.
- .minScalar(0, fp32)
- .libcallFor({fp32, fp64, fp128});
+ .minScalar(0, f32)
+ .libcallFor({f32, f64, f128});
getActionDefinitionsBuilder({G_FPOWI, G_FLDEXP})
.scalarize(0)
- .convertBF16(HasBF16)
- .minScalar(0, fp32)
- .libcallFor({{s32, s32}, {s64, s32}, {s128, s32}});
+ .convertBF16()
+ .minScalar(0, f32)
+ .libcallFor({{f32, i32}, {f64, i32}, {f128, i32}});
getActionDefinitionsBuilder({G_LROUND, G_INTRINSIC_LRINT})
.legalFor({{s32, s32}, {s32, s64}, {s64, s32}, {s64, s64}})
@@ -716,7 +727,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampScalar(0, s8, s64);
getActionDefinitionsBuilder(G_FCONSTANT)
// Always legalize s16 to prevent G_FCONSTANT being widened to G_CONSTANT
- .legalFor({s16, s32, s64, s128, bf16, fp16, fp32, fp64, fp128})
+ .legalFor({s16, s32, s64, s128})
.clampScalar(0, MinFPScalar, s128);
// FIXME: fix moreElementsToNextPow2
@@ -751,14 +762,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.customIf(isVector(0));
getActionDefinitionsBuilder(G_FCMP)
- .legalFor({{s32, s32},
- {s32, s64},
- {v4s32, v4s32},
- {v2s32, v2s32},
- {v2s64, v2s64}})
- .legalFor(HasFP16, {{s32, s16}, {v4s16, v4s16}, {v8s16, v8s16}})
+ .legalFor({{s32, f32},
+ {s32, f64},
+ {v4s32, v4f32},
+ {v2s32, v2f32},
+ {v2s64, v2f64}})
+ .legalFor(HasFP16, {{s32, f16}, {v4s16, v4f16}, {v8s16, v8f16}})
.widenScalarOrEltToNextPow2(1)
- .convertBF16(HasBF16, 1)
+ .convertBF16(1, f32)
.clampScalar(0, s32, s32)
.minScalarOrElt(1, MinFPScalar)
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
@@ -854,9 +865,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// FP conversions
getActionDefinitionsBuilder(G_FPTRUNC)
.legalFor(
- {{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
- .legalFor(HasBF16, {{bf16, fp32}, {bf16, fp64}, {v4bf16, v4fp32}})
- .libcallFor({{s16, s128}, {s32, s128}, {s64, s128}})
+ {{f16, f32}, {f16, f64}, {f32, f64}, {v4f16, v4f32}, {v2f32, v2f64}})
+ .legalFor(HasBF16, {{bf16, f32}, {bf16, f64}, {v4bf16, v4f32}})
+ .libcallFor({{f16, f128}, {f32, f128}, {f64, f128}})
.moreElementsToNextPow2(1)
.customIf([](const LegalityQuery &Q) {
LLT DstTy = Q.Types[0];
@@ -871,49 +882,43 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.scalarize(0);
getActionDefinitionsBuilder(G_FPEXT)
- .legalFor({{fp32, fp16},
- {fp64, fp16},
- {fp64, fp32},
- {v4fp32, v4fp16},
- {v2fp64, v2fp32}})
- .legalFor(HasBF16, {{fp32, bf16}, {v4fp32, v4bf16}})
+ .legalFor(
+ {{f32, f16}, {f64, f16}, {f64, f32}, {v4f32, v4f16}, {v2f64, v2f32}})
+ .legalFor(HasBF16, {{f32, bf16}, {v4f32, v4bf16}})
.libcallFor({{s128, s64}, {s128, s32}, {s128, s16}})
.moreElementsToNextPow2(0)
.widenScalarIf(
[](const LegalityQuery &Q) {
LLT DstTy = Q.Types[0];
LLT SrcTy = Q.Types[1];
- return SrcTy.isVector() && DstTy.isVector() &&
- SrcTy.getScalarSizeInBits() == 16 &&
+ return SrcTy.getScalarSizeInBits() == 16 &&
DstTy.getScalarSizeInBits() == 64;
},
- changeElementTo(1, fp32))
+ changeElementTo(1, f32))
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
- // bf16 -> fp32
- .convertBF16(HasBF16, 1)
.scalarize(0);
// Conversions
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
- .legalFor({{s32, s32},
- {s64, s32},
- {s32, s64},
- {s64, s64},
- {v2s32, v2s32},
- {v4s32, v4s32},
- {v2s64, v2s64}})
+ .legalFor({{i32, f32},
+ {i64, f32},
+ {i32, f64},
+ {i64, f64},
+ {v2i32, v2f32},
+ {v4i32, v4f32},
+ {v2i64, v2f64}})
.legalFor(HasFP16,
- {{s32, s16}, {s64, s16}, {v4s16, v4s16}, {v8s16, v8s16}})
+ {{i32, f16}, {i64, f16}, {v4i16, v4f16}, {v8i16, v8f16}})
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
// The range of a fp16 value fits into an i17, so we can lower the width
// to i64.
.narrowScalarIf(
[=](const LegalityQuery &Query) {
- return Query.Types[1] == s16 && Query.Types[0].getSizeInBits() > 64;
+ return Query.Types[1] == f16 && Query.Types[0].getSizeInBits() > 64;
},
- changeTo(0, s64))
+ changeTo(0, i64))
.moreElementsToNextPow2(0)
.widenScalarOrEltToNextPow2OrMinSize(0)
.minScalar(0, s32)
@@ -936,19 +941,19 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(0, v2s32, v4s32)
.clampMaxNumElements(0, s64, 2)
.libcallFor(
- {{s32, s128}, {s64, s128}, {s128, s128}, {s128, s32}, {s128, s64}});
+ {{i32, f128}, {i64, f128}, {i128, f128}, {i128, f32}, {i128, f64}});
getActionDefinitionsBuilder({G_FPTOSI_SAT, G_FPTOUI_SAT})
- .legalFor({{s32, s32},
- {s64, s32},
- {s32, s64},
- {s64, s64},
- {v2s32, v2s32},
- {v4s32, v4s32},
- {v2s64, v2s64}})
+ .legalFor({{i32, f32},
+ {i64, f32},
+ {i32, f64},
+ {i64, f64},
+ {v2i32, v2f32},
+ {v4i32, v4f32},
+ {v2i64, v2f64}})
.legalFor(
HasFP16,
- {{s16, s16}, {s32, s16}, {s64, s16}, {v4s16, v4s16}, {v8s16, v8s16}})
+ {{i16, f16}, {i32, f16}, {i64, f16}, {v4i16, v4f16}, {v8i16, v8f16}})
// Handle types larger than i64 by scalarizing/lowering.
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
@@ -956,9 +961,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// to i64.
.narrowScalarIf(
[=](const LegalityQuery &Query) {
- return Query.Types[1] == s16 && Query.Types[0].getSizeInBits() > 64;
+ return Query.Types[1] == f16 && Query.Types[0].getSizeInBits() > 64;
},
- changeTo(0, s64))
+ changeTo(0, i64))
.lowerIf(::any(scalarWiderThan(0, 64), scalarWiderThan(1, 64)), 0)
.moreElementsToNextPow2(0)
.widenScalarToNextPow2(0, /*MinSize=*/32)
@@ -984,21 +989,21 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampMaxNumElements(0, s64, 2);
getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
- .legalFor({{s32, s32},
- {s64, s32},
- {s32, s64},
- {s64, s64},
- {v2s32, v2s32},
- {v4s32, v4s32},
- {v2s64, v2s64}})
- .convertBF16(HasBF16)
+ .legalFor({{f32, i32},
+ {f64, i32},
+ {f32, i64},
+ {f64, i64},
+ {v2f32, v2i32},
+ {v4f32, v4i32},
+ {v2f64, v2i64}})
+ .convertBF16()
.legalFor(HasFP16,
- {{s16, s32}, {s16, s64}, {v4s16, v4s16}, {v8s16, v8s16}})
+ {{f16, i32}, {f16, i64}, {v4f16, v4i16}, {v8f16, v8i16}})
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.moreElementsToNextPow2(1)
.widenScalarOrEltToNextPow2OrMinSize(1)
- .minScalar(1, fp32)
+ .minScalar(1, f32)
.lowerIf([](const LegalityQuery &Query) {
return Query.Types[1].isVector() &&
Query.Types[1].getScalarSizeInBits() == 64 &&
@@ -1029,12 +1034,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
.clampMaxNumElements(0, s64, 2)
- .libcallFor({{s16, s128},
- {s32, s128},
- {s64, s128},
- {s128, s128},
- {s128, s32},
- {s128, s64}});
+ .libcallFor({{f16, i128},
+ {f32, i128},
+ {f64, i128},
+ {f128, i128},
+ {f128, i32},
+ {f128, i64}});
// Control-flow
getActionDefinitionsBuilder(G_BR).alwaysLegal();
@@ -1176,7 +1181,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{s16, nxv8s16, s64},
{s32, nxv4s32, s64},
{s64, nxv2s64, s64}})
- .legalFor(HasBF16, {{bf16, v8bf16, s64}, {bf16, v4bf16, s64}})
.unsupportedIf([=](const LegalityQuery &Query) {
const LLT &EltTy = Query.Types[1].getElementType();
if (Query.Types[1].isScalableVector())
@@ -1228,7 +1232,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
.legalIf(
typeInSet(0, {v8s8, v16s8, v4s16, v8s16, v2s32, v4s32, v2s64, v2p0}))
- .legalFor(HasBF16, {{v4bf16}, {v8bf16}})
.legalFor(HasSVE, {{nxv16s8, s32, s64},
{nxv8s16, s32, s64},
{nxv4s32, s32, s64},
@@ -1251,7 +1254,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{v4s32, s32},
{v2s64, s64},
{v2p0, p0}})
- .legalFor(HasBF16, {{v4bf16, bf16}, {v8bf16, bf16}})
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.minScalarOrElt(0, s8)
@@ -1299,7 +1301,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_CONCAT_VECTORS)
.legalFor({{v16s8, v8s8}, {v8s16, v4s16}, {v4s32, v2s32}})
- .legalFor(HasBF16, {{v8bf16, v4bf16}})
.bitcastIf(
[=](const LegalityQuery &Query) {
return Query.Types[0].isFixedVector() &&
>From 59a463a5d43d60f2e7d4332db0d1f79f82287cda Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 23 Feb 2026 11:49:29 +0000
Subject: [PATCH 24/30] Combine tests
---
.../AArch64/GlobalISel/bf16-fpext-fptrunc.ll | 127 -----------
.../AArch64/GlobalISel/bf16-promote.ll | 200 ------------------
2 files changed, 327 deletions(-)
delete mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll
delete mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll
deleted file mode 100644
index 2fd07dc2fa729..0000000000000
--- a/llvm/test/CodeGen/AArch64/GlobalISel/bf16-fpext-fptrunc.ll
+++ /dev/null
@@ -1,127 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -O3 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-SD
-; RUN: llc < %s -O3 -global-isel -global-isel-abort=1 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-GIS
-
-define bfloat @scalar_fptrunc_float(float %a) {
-; SCALAR-LABEL: scalar_fptrunc_float:
-; SCALAR: // %bb.0: // %entry
-; SCALAR-NEXT: bfcvt h0, s0
-; SCALAR-NEXT: ret
-entry:
- %res = fptrunc float %a to bfloat
- ret bfloat %res
-}
-
-define float @scalar_fpext(bfloat %a) {
-; SCALAR-LABEL: scalar_fpext:
-; SCALAR: // %bb.0: // %entry
-; SCALAR-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-NEXT: // kill: def $s0 killed $s0 killed $q0
-; SCALAR-NEXT: ret
-entry:
- %res = fpext bfloat %a to float
- ret float %res
-}
-
-define double @scalar_fpext_double(bfloat %a) {
-; SCALAR-LABEL: scalar_fpext_double:
-; SCALAR: // %bb.0: // %entry
-; SCALAR-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-NEXT: fcvt d0, s0
-; SCALAR-NEXT: ret
-entry:
- %res = fpext bfloat %a to double
- ret double %res
-}
-
-define <2 x bfloat> @v2bf16_fptrunc_float(<2 x float> %a) {
-; SCALAR-LABEL: v2bf16_fptrunc_float:
-; SCALAR: // %bb.0: // %entry
-; SCALAR-NEXT: // kill: def $d0 killed $d0 def $q0
-; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
-; SCALAR-NEXT: ret
-entry:
- %res = fptrunc <2 x float> %a to <2 x bfloat>
- ret <2 x bfloat> %res
-}
-
-define <3 x bfloat> @v3bf16_fptrunc_float(<3 x float> %a) {
-; SCALAR-LABEL: v3bf16_fptrunc_float:
-; SCALAR: // %bb.0: // %entry
-; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
-; SCALAR-NEXT: ret
-entry:
- %res = fptrunc <3 x float> %a to <3 x bfloat>
- ret <3 x bfloat> %res
-}
-
-define <4 x bfloat> @v4bf16_fptrunc_float(<4 x float> %a) {
-; SCALAR-LABEL: v4bf16_fptrunc_float:
-; SCALAR: // %bb.0: // %entry
-; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
-; SCALAR-NEXT: ret
-entry:
- %res = fptrunc <4 x float> %a to <4 x bfloat>
- ret <4 x bfloat> %res
-}
-
-define <4 x bfloat> @v4bf16_fptrunc_double(<4 x double> %a) {
-; SCALAR-SD-LABEL: v4bf16_fptrunc_double:
-; SCALAR-SD: // %bb.0: // %entry
-; SCALAR-SD-NEXT: fcvtxn v0.2s, v0.2d
-; SCALAR-SD-NEXT: fcvtxn2 v0.4s, v1.2d
-; SCALAR-SD-NEXT: bfcvtn v0.4h, v0.4s
-; SCALAR-SD-NEXT: ret
-;
-; SCALAR-GIS-LABEL: v4bf16_fptrunc_double:
-; SCALAR-GIS: // %bb.0: // %entry
-; SCALAR-GIS-NEXT: fcvtxn v0.2s, v0.2d
-; SCALAR-GIS-NEXT: fcvtxn2 v0.4s, v1.2d
-; SCALAR-GIS-NEXT: bfcvtn v0.4h, v0.4s
-; SCALAR-GIS-NEXT: ret
-entry:
- %res = fptrunc <4 x double> %a to <4 x bfloat>
- ret <4 x bfloat> %res
-}
-
-define <2 x float> @v2bf16_fpext_float(<2 x bfloat> %a) {
-; SCALAR-LABEL: v2bf16_fpext_float:
-; SCALAR: // %bb.0: // %entry
-; SCALAR-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-NEXT: // kill: def $d0 killed $d0 killed $q0
-; SCALAR-NEXT: ret
-entry:
- %res = fpext <2 x bfloat> %a to <2 x float>
- ret <2 x float> %res
-}
-
-define <4 x float> @v4bf16_fpext_float(<4 x bfloat> %a) {
-; SCALAR-LABEL: v4bf16_fpext_float:
-; SCALAR: // %bb.0: // %entry
-; SCALAR-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-NEXT: ret
-entry:
- %res = fpext <4 x bfloat> %a to <4 x float>
- ret <4 x float> %res
-}
-
-define <4 x double> @v4bf16_fpext_double(<4 x bfloat> %a) {
-; SCALAR-SD-LABEL: v4bf16_fpext_double:
-; SCALAR-SD: // %bb.0: // %entry
-; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-SD-NEXT: fcvtl2 v1.2d, v0.4s
-; SCALAR-SD-NEXT: fcvtl v0.2d, v0.2s
-; SCALAR-SD-NEXT: ret
-;
-; SCALAR-GIS-LABEL: v4bf16_fpext_double:
-; SCALAR-GIS: // %bb.0: // %entry
-; SCALAR-GIS-NEXT: shll v1.4s, v0.4h, #16
-; SCALAR-GIS-NEXT: fcvtl v0.2d, v1.2s
-; SCALAR-GIS-NEXT: fcvtl2 v1.2d, v1.4s
-; SCALAR-GIS-NEXT: ret
-entry:
- %res = fpext <4 x bfloat> %a to <4 x double>
- ret <4 x double> %res
-}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll b/llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll
deleted file mode 100644
index 75f5f68aa1904..0000000000000
--- a/llvm/test/CodeGen/AArch64/GlobalISel/bf16-promote.ll
+++ /dev/null
@@ -1,200 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -O3 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-SD
-; RUN: llc < %s -O3 -global-isel -global-isel-abort=1 -mtriple=aarch64-unknown-unknown -mattr=+bf16 | FileCheck %s --check-prefixes=SCALAR,SCALAR-GIS
-
-define bfloat @scalar_fadd(bfloat %a, bfloat %b) {
-; SCALAR-SD-LABEL: scalar_fadd:
-; SCALAR-SD: // %bb.0: // %entry
-; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
-; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-SD-NEXT: fadd s0, s0, s1
-; SCALAR-SD-NEXT: bfcvt h0, s0
-; SCALAR-SD-NEXT: ret
-;
-; SCALAR-GIS-LABEL: scalar_fadd:
-; SCALAR-GIS: // %bb.0: // %entry
-; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
-; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-GIS-NEXT: fadd s0, s0, s1
-; SCALAR-GIS-NEXT: bfcvt h0, s0
-; SCALAR-GIS-NEXT: ret
-entry:
- %res = fadd bfloat %a, %b
- ret bfloat %res
-}
-
-define <2 x bfloat> @v2bf16_fadd(<2 x bfloat> %a, <2 x bfloat> %b) {
-; SCALAR-SD-LABEL: v2bf16_fadd:
-; SCALAR-SD: // %bb.0: // %entry
-; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-SD-NEXT: fadd v0.4s, v0.4s, v1.4s
-; SCALAR-SD-NEXT: bfcvtn v0.4h, v0.4s
-; SCALAR-SD-NEXT: ret
-;
-; SCALAR-GIS-LABEL: v2bf16_fadd:
-; SCALAR-GIS: // %bb.0: // %entry
-; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-GIS-NEXT: fadd v0.2s, v0.2s, v1.2s
-; SCALAR-GIS-NEXT: bfcvtn v0.4h, v0.4s
-; SCALAR-GIS-NEXT: ret
-entry:
- %res = fadd <2 x bfloat> %a, %b
- ret <2 x bfloat> %res
-}
-
-
-define <4 x bfloat> @v4bf16_fadd(<4 x bfloat> %a, <4 x bfloat> %b) {
-; SCALAR-SD-LABEL: v4bf16_fadd:
-; SCALAR-SD: // %bb.0: // %entry
-; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-SD-NEXT: fadd v0.4s, v0.4s, v1.4s
-; SCALAR-SD-NEXT: bfcvtn v0.4h, v0.4s
-; SCALAR-SD-NEXT: ret
-;
-; SCALAR-GIS-LABEL: v4bf16_fadd:
-; SCALAR-GIS: // %bb.0: // %entry
-; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-GIS-NEXT: fadd v0.4s, v0.4s, v1.4s
-; SCALAR-GIS-NEXT: bfcvtn v0.4h, v0.4s
-; SCALAR-GIS-NEXT: ret
-entry:
- %res = fadd <4 x bfloat> %a, %b
- ret <4 x bfloat> %res
-}
-
-define bfloat @scalar_fsub(bfloat %a, bfloat %b) {
-; SCALAR-SD-LABEL: scalar_fsub:
-; SCALAR-SD: // %bb.0: // %entry
-; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
-; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-SD-NEXT: fsub s0, s0, s1
-; SCALAR-SD-NEXT: bfcvt h0, s0
-; SCALAR-SD-NEXT: ret
-;
-; SCALAR-GIS-LABEL: scalar_fsub:
-; SCALAR-GIS: // %bb.0: // %entry
-; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
-; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-GIS-NEXT: fsub s0, s0, s1
-; SCALAR-GIS-NEXT: bfcvt h0, s0
-; SCALAR-GIS-NEXT: ret
-entry:
- %res = fsub bfloat %a, %b
- ret bfloat %res
-}
-
-define bfloat @scalar_fmul(bfloat %a, bfloat %b) {
-; SCALAR-SD-LABEL: scalar_fmul:
-; SCALAR-SD: // %bb.0: // %entry
-; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
-; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-SD-NEXT: fmul s0, s0, s1
-; SCALAR-SD-NEXT: bfcvt h0, s0
-; SCALAR-SD-NEXT: ret
-;
-; SCALAR-GIS-LABEL: scalar_fmul:
-; SCALAR-GIS: // %bb.0: // %entry
-; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
-; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-GIS-NEXT: fmul s0, s0, s1
-; SCALAR-GIS-NEXT: bfcvt h0, s0
-; SCALAR-GIS-NEXT: ret
-entry:
- %res = fmul bfloat %a, %b
- ret bfloat %res
-}
-
-define bfloat @scalar_fdiv(bfloat %a, bfloat %b) {
-; SCALAR-SD-LABEL: scalar_fdiv:
-; SCALAR-SD: // %bb.0: // %entry
-; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
-; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-SD-NEXT: fdiv s0, s0, s1
-; SCALAR-SD-NEXT: bfcvt h0, s0
-; SCALAR-SD-NEXT: ret
-;
-; SCALAR-GIS-LABEL: scalar_fdiv:
-; SCALAR-GIS: // %bb.0: // %entry
-; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
-; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-GIS-NEXT: fdiv s0, s0, s1
-; SCALAR-GIS-NEXT: bfcvt h0, s0
-; SCALAR-GIS-NEXT: ret
-entry:
- %res = fdiv bfloat %a, %b
- ret bfloat %res
-}
-
-define i1 @scalar_fcmp(bfloat %a, bfloat %b) {
-; SCALAR-SD-LABEL: scalar_fcmp:
-; SCALAR-SD: // %bb.0: // %entry
-; SCALAR-SD-NEXT: // kill: def $h1 killed $h1 def $d1
-; SCALAR-SD-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-SD-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-SD-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-SD-NEXT: fcmp s0, s1
-; SCALAR-SD-NEXT: cset w0, gt
-; SCALAR-SD-NEXT: ret
-;
-; SCALAR-GIS-LABEL: scalar_fcmp:
-; SCALAR-GIS: // %bb.0: // %entry
-; SCALAR-GIS-NEXT: // kill: def $h0 killed $h0 def $d0
-; SCALAR-GIS-NEXT: // kill: def $h1 killed $h1 def $d1
-; SCALAR-GIS-NEXT: shll v0.4s, v0.4h, #16
-; SCALAR-GIS-NEXT: shll v1.4s, v1.4h, #16
-; SCALAR-GIS-NEXT: fcmp s0, s1
-; SCALAR-GIS-NEXT: cset w0, gt
-; SCALAR-GIS-NEXT: ret
-entry:
- %cmp = fcmp ogt bfloat %a, %b
- ret i1 %cmp
-}
-
-define bfloat @scalar_sitofp(i32 %a) {
-; SCALAR-SD-LABEL: scalar_sitofp:
-; SCALAR-SD: // %bb.0: // %entry
-; SCALAR-SD-NEXT: scvtf d0, w0
-; SCALAR-SD-NEXT: fcvtxn s0, d0
-; SCALAR-SD-NEXT: bfcvt h0, s0
-; SCALAR-SD-NEXT: ret
-;
-; SCALAR-GIS-LABEL: scalar_sitofp:
-; SCALAR-GIS: // %bb.0: // %entry
-; SCALAR-GIS-NEXT: scvtf s0, w0
-; SCALAR-GIS-NEXT: bfcvt h0, s0
-; SCALAR-GIS-NEXT: ret
-entry:
- %res = sitofp i32 %a to bfloat
- ret bfloat %res
-}
-
-define <4 x bfloat> @v4i32_sitofp(<4 x i32> %a) {
-; SCALAR-LABEL: v4i32_sitofp:
-; SCALAR: // %bb.0: // %entry
-; SCALAR-NEXT: scvtf v0.4s, v0.4s
-; SCALAR-NEXT: bfcvtn v0.4h, v0.4s
-; SCALAR-NEXT: ret
-entry:
- %res = sitofp <4 x i32> %a to <4 x bfloat>
- ret <4 x bfloat> %res
-}
>From 616d0f4802d07013ca4d12e735fc5f7bbea73c5a Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 23 Feb 2026 11:53:30 +0000
Subject: [PATCH 25/30] Remove incorrect update line
---
.../AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
index 524be2c59536c..03c5a3764bff3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=aarch64-- -mcpu=falkor -mattr=+lse -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
define i16 @convert_to_fp16(float %src) {
>From 947bd4caaeda3c6756f1d5b4cf98eca52b3e46a8 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Mon, 23 Feb 2026 12:26:01 +0000
Subject: [PATCH 26/30] Correct LLTOperandShapeMatcher comment
---
llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
index 77eabb0e1f73c..5fb3ef1a87c88 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
@@ -1020,7 +1020,7 @@ class LLTOperandMatcher : public OperandPredicateMatcher {
RuleMatcher &Rule) const override;
};
-/// Generates code to check that the size of an MMO is exactly N bytes.
+/// Generates code to check that the element count & element sizes are the same.
class LLTOperandShapeMatcher : public LLTOperandMatcher {
static ElementCount getShapeElementCount(const LLT &Ty) {
return Ty.isVector() ? Ty.getElementCount() : ElementCount::getFixed(1);
>From 9e8db43f90f8770e1a7e4bc24d5a0151b8d23448 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 25 Feb 2026 14:10:57 +0000
Subject: [PATCH 27/30] Tighten types in the legalizer and construct types
where possible over mutating
---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 168 ++++++++--------
.../AArch64/GlobalISel/fold-fp-select.mir | 6 +-
.../AArch64/GlobalISel/legalize-ctpop.mir | 181 +++++++++---------
.../AArch64/GlobalISel/legalize-cttz.mir | 12 +-
4 files changed, 186 insertions(+), 181 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 930af91eb9cfa..c38268f3666dc 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -81,6 +81,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
const LLT f128 = LLT::float128();
+ const LLT i8 = LLT::integer(8);
+ const LLT v8i8 = LLT::fixed_vector(8, i8);
+ const LLT v16i8 = LLT::fixed_vector(16, i8);
+
const LLT i16 = LLT::integer(16);
const LLT v8i16 = LLT::fixed_vector(8, i16);
const LLT v4i16 = LLT::fixed_vector(4, i16);
@@ -174,7 +178,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.maxScalarIf(typeInSet(1, {s128}), 0, s64);
getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
- .legalFor({s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32, v2s64})
+ .legalFor({i32, i64, v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64})
.legalFor(HasSVE, {nxv16s8, nxv8s16, nxv4s32, nxv2s64})
.widenScalarToNextPow2(0)
.clampScalar(0, s32, s64)
@@ -201,7 +205,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.moreElementsToNextPow2(0);
getActionDefinitionsBuilder(G_MUL)
- .legalFor({s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32, v2s64})
+ .legalFor({i32, i64, v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64})
.widenScalarToNextPow2(0)
.clampScalar(0, s32, s64)
.clampMaxNumElements(0, s8, 16)
@@ -234,16 +238,16 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
AmtTy.getSizeInBits() == 32;
})
.legalFor({
- {s32, s32},
- {s32, s64},
- {s64, s64},
- {v8s8, v8s8},
- {v16s8, v16s8},
- {v4s16, v4s16},
- {v8s16, v8s16},
- {v2s32, v2s32},
- {v4s32, v4s32},
- {v2s64, v2s64},
+ {i32, i32},
+ {i32, i64},
+ {i64, i64},
+ {v8i8, v8i8},
+ {v16i8, v16i8},
+ {v4i16, v4i16},
+ {v8i16, v8i16},
+ {v2i32, v2i32},
+ {v4i32, v4i32},
+ {v2i64, v2i64},
})
.widenScalarToNextPow2(0)
.clampScalar(1, s32, s64)
@@ -259,22 +263,22 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.maxScalarEltSameAsIf(isVector(0), 1, 0);
getActionDefinitionsBuilder(G_PTR_ADD)
- .legalFor({{p0, s64}, {v2p0, v2s64}})
+ .legalFor({{p0, i64}, {v2p0, v2i64}})
.clampScalarOrElt(1, s64, s64)
.clampNumElements(0, v2p0, v2p0);
getActionDefinitionsBuilder(G_PTRMASK).legalFor({{p0, s64}});
getActionDefinitionsBuilder({G_SDIV, G_UDIV})
- .legalFor({s32, s64})
- .libcallFor({s128})
+ .legalFor({i32, i64})
+ .libcallFor({i128})
.clampScalar(0, s32, s64)
.widenScalarToNextPow2(0)
.scalarize(0);
getActionDefinitionsBuilder({G_SREM, G_UREM, G_SDIVREM, G_UDIVREM})
- .lowerFor({s8, s16, s32, s64, v2s32, v4s32, v2s64})
- .libcallFor({s128})
+ .lowerFor({i8, i16, i32, i64, v2i32, v4i32, v2i64})
+ .libcallFor({i128})
.widenScalarOrEltToNextPow2(0)
.minScalarOrElt(0, s32)
.clampNumElements(0, v2s32, v4s32)
@@ -291,8 +295,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.lower();
getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
- .legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
- .legalFor(HasCSSC, {s32, s64})
+ .legalFor({v8i8, v16i8, v4i16, v8i16, v2i32, v4i32})
+ .legalFor(HasCSSC, {i32, i64})
.minScalar(HasCSSC, 0, s32)
.clampNumElements(0, v8s8, v16s8)
.clampNumElements(0, v4s16, v8s16)
@@ -334,11 +338,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.widenScalarToNextPow2(0);
getActionDefinitionsBuilder({G_FSHL, G_FSHR})
- .customFor({{s32, s32}, {s32, s64}, {s64, s64}})
+ .customFor({{i32, i32}, {i32, i64}, {i64, i64}})
.lower();
getActionDefinitionsBuilder(G_ROTR)
- .legalFor({{s32, s64}, {s64, s64}})
+ .legalFor({{i32, i64}, {i64, i64}})
.customIf([=](const LegalityQuery &Q) {
return Q.Types[0].isScalar() && Q.Types[1].getScalarSizeInBits() < 64;
})
@@ -441,7 +445,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN})
.legalFor({f32, f64, v2f32, v4f32, v2f64})
.convertBF16()
- .legalFor(HasFP16, {f16, s16, v4s16, v8s16})
+ .legalFor(HasFP16, {f16, v4f16, v8f16})
.libcallFor({f128})
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.minScalarOrElt(0, MinFPScalar)
@@ -722,17 +726,17 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// Constants
getActionDefinitionsBuilder(G_CONSTANT)
- .legalFor({p0, s8, s16, s32, s64})
+ .legalFor({p0, i8, i16, i32, i64})
.widenScalarToNextPow2(0)
.clampScalar(0, s8, s64);
getActionDefinitionsBuilder(G_FCONSTANT)
- // Always legalize s16 to prevent G_FCONSTANT being widened to G_CONSTANT
- .legalFor({s16, s32, s64, s128})
+ // Always legalize f16 to prevent G_FCONSTANT being widened to G_CONSTANT
+ .legalFor({bf16, f16, f32, f64, f128})
.clampScalar(0, MinFPScalar, s128);
// FIXME: fix moreElementsToNextPow2
getActionDefinitionsBuilder(G_ICMP)
- .legalFor({{s32, s32}, {s32, s64}, {s32, p0}})
+ .legalFor({{i32, i32}, {i32, i64}, {i32, p0}})
.widenScalarOrEltToNextPow2(1)
.clampScalar(1, s32, s64)
.clampScalar(0, s32, s32)
@@ -885,7 +889,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalFor(
{{f32, f16}, {f64, f16}, {f64, f32}, {v4f32, v4f16}, {v2f64, v2f32}})
.legalFor(HasBF16, {{f32, bf16}, {v4f32, v4bf16}})
- .libcallFor({{s128, s64}, {s128, s32}, {s128, s16}})
+ .libcallFor({{f128, f64}, {f128, f32}, {f128, f16}})
.moreElementsToNextPow2(0)
.widenScalarIf(
[](const LegalityQuery &Q) {
@@ -1069,7 +1073,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalIf(all(typeIs(0, p0), typeIs(1, p0)));
getActionDefinitionsBuilder(G_PTRTOINT)
- .legalFor({{s64, p0}, {v2s64, v2p0}})
+ .legalFor({{i64, p0}, {v2i64, v2p0}})
.widenScalarToNextPow2(0, 64)
.clampScalar(0, s64, s64)
.clampMaxNumElements(0, s64, 2);
@@ -1078,7 +1082,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.unsupportedIf([&](const LegalityQuery &Query) {
return Query.Types[0].getSizeInBits() != Query.Types[1].getSizeInBits();
})
- .legalFor({{p0, s64}, {v2p0, v2s64}})
+ .legalFor({{p0, i64}, {v2p0, v2i64}})
.clampMaxNumElements(1, s64, 2);
// Casts for 32 and 64-bit width type are just copies.
@@ -1366,8 +1370,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// usual legal types as legal and handle the lowering to pairwise instructions
// later.
getActionDefinitionsBuilder(G_VECREDUCE_FADD)
- .legalFor({{s32, v2s32}, {s32, v4s32}, {s64, v2s64}})
- .legalFor(HasFP16, {{s16, v4s16}, {s16, v8s16}})
+ .legalFor({{f32, v2f32}, {f32, v4f32}, {f64, v2f64}})
+ .legalFor(HasFP16, {{f16, v4f16}, {f16, v8f16}})
.minScalarOrElt(0, MinFPScalar)
.clampMaxNumElements(1, s64, 2)
.clampMaxNumElements(1, s32, 4)
@@ -1394,13 +1398,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.lower();
getActionDefinitionsBuilder(G_VECREDUCE_ADD)
- .legalFor({{s8, v8s8},
- {s8, v16s8},
- {s16, v4s16},
- {s16, v8s16},
- {s32, v2s32},
- {s32, v4s32},
- {s64, v2s64}})
+ .legalFor({{i8, v8i8},
+ {i8, v16i8},
+ {i16, v4i16},
+ {i16, v8i16},
+ {i32, v2i32},
+ {i32, v4i32},
+ {i64, v2i64}})
.moreElementsToNextPow2(1)
.clampMaxNumElements(1, s64, 2)
.clampMaxNumElements(1, s32, 4)
@@ -1411,8 +1415,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder({G_VECREDUCE_FMIN, G_VECREDUCE_FMAX,
G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM})
- .legalFor({{s32, v2s32}, {s32, v4s32}, {s64, v2s64}})
- .legalFor(HasFP16, {{s16, v4s16}, {s16, v8s16}})
+ .legalFor({{f32, v2f32}, {f32, v4f32}, {f64, v2f64}})
+ .legalFor(HasFP16, {{f16, v4f16}, {f16, v8f16}})
.minScalarOrElt(0, MinFPScalar)
.clampMaxNumElements(1, s64, 2)
.clampMaxNumElements(1, s32, 4)
@@ -1429,12 +1433,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(
{G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX})
- .legalFor({{s8, v8s8},
- {s8, v16s8},
- {s16, v4s16},
- {s16, v8s16},
- {s32, v2s32},
- {s32, v4s32}})
+ .legalFor({{i8, v8i8},
+ {i8, v16i8},
+ {i16, v4i16},
+ {i16, v8i16},
+ {i32, v2i32},
+ {i32, v4i32}})
.moreElementsIf(
[=](const LegalityQuery &Query) {
return Query.Types[1].isVector() &&
@@ -1867,22 +1871,20 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(2).getReg();
LLT DstTy = MRI.getType(DstReg);
- LLT DstTyScalar = DstTy.getScalarType();
LLT MidTy, ExtTy;
if (DstTy.isScalar() && DstTy.getScalarSizeInBits() <= 32) {
- ExtTy = DstTyScalar.changeElementSize(32);
+ ExtTy = LLT::integer(32);
MidTy = LLT::fixed_vector(4, ExtTy);
} else {
- ExtTy = DstTy.changeElementSize(64);
+ ExtTy = LLT::integer(64);
MidTy = LLT::fixed_vector(2, ExtTy);
}
Register MidReg =
MIB.buildInstr(Opc, {MidTy}, {SrcReg})->getOperand(0).getReg();
- Register ZeroReg = MIB.buildConstant(DstTyScalar.changeElementSize(64), 0)
- ->getOperand(0)
- .getReg();
+ Register ZeroReg =
+ MIB.buildConstant(LLT::integer(64), 0)->getOperand(0).getReg();
Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy},
{MidReg, ZeroReg})
.getReg(0);
@@ -2298,18 +2300,22 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
Register Dst = MI.getOperand(0).getReg();
Register Val = MI.getOperand(1).getReg();
LLT Ty = MRI.getType(Val);
+
+ LLT i64 = LLT::integer(64);
+ LLT i32 = LLT::integer(32);
+ LLT i16 = LLT::integer(16);
+ LLT i8 = LLT::integer(8);
unsigned Size = Ty.getSizeInBits();
assert(Ty == MRI.getType(Dst) &&
"Expected src and dst to have the same type!");
if (ST->hasCSSC() && Ty.isScalar() && Size == 128) {
- LLT s64 = Ty.changeElementSize(64);
- auto Split = MIRBuilder.buildUnmerge(s64, Val);
- auto CTPOP1 = MIRBuilder.buildCTPOP(s64, Split->getOperand(0));
- auto CTPOP2 = MIRBuilder.buildCTPOP(s64, Split->getOperand(1));
- auto Add = MIRBuilder.buildAdd(s64, CTPOP1, CTPOP2);
+ auto Split = MIRBuilder.buildUnmerge(i64, Val);
+ auto CTPOP1 = MIRBuilder.buildCTPOP(i64, Split->getOperand(0));
+ auto CTPOP2 = MIRBuilder.buildCTPOP(i64, Split->getOperand(1));
+ auto Add = MIRBuilder.buildAdd(i64, CTPOP1, CTPOP2);
MIRBuilder.buildZExt(Dst, Add);
MI.eraseFromParent();
@@ -2327,13 +2333,11 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
// Pre-conditioning: widen Val up to the nearest vector type.
// s32,s64,v4s16,v2s32 -> v8i8
// v8s16,v4s32,v2s64 -> v16i8
- LLT ScalarTy = Ty.getScalarType();
- LLT VTy = Size == 128 ? LLT::fixed_vector(16, ScalarTy.changeElementSize(8))
- : LLT::fixed_vector(8, ScalarTy.changeElementSize(8));
+ LLT VTy = Size == 128 ? LLT::fixed_vector(16, i8) : LLT::fixed_vector(8, i8);
if (Ty.isScalar()) {
assert((Size == 32 || Size == 64 || Size == 128) && "Expected only 32, 64, or 128 bit scalars!");
if (Size == 32) {
- Val = MIRBuilder.buildZExt(ScalarTy.changeElementSize(64), Val).getReg(0);
+ Val = MIRBuilder.buildZExt(i64, Val).getReg(0);
}
}
Val = MIRBuilder.buildBitcast(VTy, Val).getReg(0);
@@ -2344,20 +2348,18 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
// Sum across lanes.
if (ST->hasDotProd() && Ty.isVector() && Ty.getNumElements() >= 2 &&
Ty.getScalarSizeInBits() != 16) {
- LLT Dt = Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(64))
- ? LLT::fixed_vector(4, ScalarTy.changeElementSize(32))
- : Ty;
+ LLT Dt = Ty == LLT::fixed_vector(2, i64) ? LLT::fixed_vector(4, i32) : Ty;
auto Zeros = MIRBuilder.buildConstant(Dt, 0);
auto Ones = MIRBuilder.buildConstant(VTy, 1);
MachineInstrBuilder Sum;
- if (Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(64))) {
+ if (Ty == LLT::fixed_vector(2, i64)) {
auto UDOT =
MIRBuilder.buildInstr(AArch64::G_UDOT, {Dt}, {Zeros, Ones, CTPOP});
Sum = MIRBuilder.buildInstr(AArch64::G_UADDLP, {Ty}, {UDOT});
- } else if (Ty == LLT::fixed_vector(4, 32)) {
+ } else if (Ty == LLT::fixed_vector(4, i32)) {
Sum = MIRBuilder.buildInstr(AArch64::G_UDOT, {Dt}, {Zeros, Ones, CTPOP});
- } else if (Ty == LLT::fixed_vector(2, 32)) {
+ } else if (Ty == LLT::fixed_vector(2, i32)) {
Sum = MIRBuilder.buildInstr(AArch64::G_UDOT, {Dt}, {Zeros, Ones, CTPOP});
} else {
llvm_unreachable("unexpected vector shape");
@@ -2373,26 +2375,26 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
SmallVector<LLT> HAddTys;
if (Ty.isScalar()) {
Opc = Intrinsic::aarch64_neon_uaddlv;
- HAddTys.push_back(ScalarTy.changeElementSize(32));
- } else if (Ty == LLT::fixed_vector(8, ScalarTy.changeElementSize(16))) {
+ HAddTys.push_back(i32);
+ } else if (Ty == LLT::fixed_vector(8, i16)) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(8, ScalarTy.changeElementSize(16)));
- } else if (Ty == LLT::fixed_vector(4, ScalarTy.changeElementSize(32))) {
+ HAddTys.push_back(LLT::fixed_vector(8, i16));
+ } else if (Ty == LLT::fixed_vector(4, i32)) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(8, ScalarTy.changeElementSize(16)));
- HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(32)));
- } else if (Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(64))) {
+ HAddTys.push_back(LLT::fixed_vector(8, i16));
+ HAddTys.push_back(LLT::fixed_vector(4, i32));
+ } else if (Ty == LLT::fixed_vector(2, i64)) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(8, ScalarTy.changeElementSize(16)));
- HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(32)));
- HAddTys.push_back(LLT::fixed_vector(2, ScalarTy.changeElementSize(64)));
- } else if (Ty == LLT::fixed_vector(4, ScalarTy.changeElementSize(16))) {
+ HAddTys.push_back(LLT::fixed_vector(8, i16));
+ HAddTys.push_back(LLT::fixed_vector(4, i32));
+ HAddTys.push_back(LLT::fixed_vector(2, i64));
+ } else if (Ty == LLT::fixed_vector(4, i16)) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(16)));
- } else if (Ty == LLT::fixed_vector(2, ScalarTy.changeElementSize(32))) {
+ HAddTys.push_back(LLT::fixed_vector(4, i16));
+ } else if (Ty == LLT::fixed_vector(2, i32)) {
Opc = Intrinsic::aarch64_neon_uaddlp;
- HAddTys.push_back(LLT::fixed_vector(4, ScalarTy.changeElementSize(16)));
- HAddTys.push_back(LLT::fixed_vector(2, ScalarTy.changeElementSize(32)));
+ HAddTys.push_back(LLT::fixed_vector(4, i16));
+ HAddTys.push_back(LLT::fixed_vector(2, i32));
} else
llvm_unreachable("unexpected vector shape");
MachineInstrBuilder UADD;
@@ -2621,6 +2623,8 @@ bool AArch64LegalizerInfo::legalizeFptrunc(MachineInstr &MI,
assert(SrcTy.isFixedVector() && isPowerOf2_32(SrcTy.getNumElements()) &&
"Expected a power of 2 elements");
+ // We must mutate types here as FPTrunc may be used on a IEEE floating point
+ // or a brainfloat.
LLT v2s16 = DstTy.changeElementCount(2);
LLT v4s16 = DstTy.changeElementCount(4);
LLT v2s32 = SrcTy.changeElementCount(2).changeElementSize(32);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
index c499984775e89..71ae290bf28d6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
@@ -99,11 +99,11 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:gpr(f32) = COPY $w0
+ %0:gpr(i32) = COPY $w0
%1:fpr(f32) = COPY $s0
- %2:gpr(f32) = G_CONSTANT i32 0
+ %2:gpr(i32) = G_CONSTANT i32 0
%5:fpr(f32) = G_FCONSTANT float 0.000000e+00
- %6:gpr(f32) = G_ICMP intpred(eq), %0(f32), %2
+ %6:gpr(i32) = G_ICMP intpred(eq), %0(i32), %2
%4:fpr(f32) = G_SELECT %6, %1, %5
$s0 = COPY %4(f32)
RET_ReallyLR implicit $s0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
index fe28c3a47ad5e..e4490d3a82e8d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
@@ -66,13 +66,13 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT %copy(s32)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[ZEXT]](s64)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
- ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x s32>) = G_UADDLV [[CTPOP]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: %ctpop:_(s32) = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT %copy(s32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[ZEXT]](i64)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x i8>) = G_CTPOP [[BITCAST]](<8 x i8>)
+ ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x i32>) = G_UADDLV [[CTPOP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x i32>), [[C]](i64)
+ ; CHECK-NEXT: %ctpop:_(s32) = COPY [[EVEC]](i32)
; CHECK-NEXT: $w0 = COPY %ctpop(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
;
@@ -99,13 +99,13 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:_(s64) = COPY $x0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST %copy(s64)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
- ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x s32>) = G_UADDLV [[CTPOP]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
- ; CHECK-NEXT: %ctpop:_(s64) = G_ZEXT [[COPY]](s32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST %copy(s64)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x i8>) = G_CTPOP [[BITCAST]](<8 x i8>)
+ ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x i32>) = G_UADDLV [[CTPOP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x i32>), [[C]](i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY [[EVEC]](i32)
+ ; CHECK-NEXT: %ctpop:_(s64) = G_ZEXT [[COPY]](i32)
; CHECK-NEXT: $x0 = COPY %ctpop(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
;
@@ -135,16 +135,17 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[MV]](s128)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
- ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x s32>) = G_UADDLV [[CTPOP]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[MV]](s128)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x i8>) = G_CTPOP [[BITCAST]](<16 x i8>)
+ ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x i32>) = G_UADDLV [[CTPOP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x i32>), [[C]](i64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[EVEC]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[C1]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](i32), [[C1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: $x0 = COPY [[MV1]](s64)
- ; CHECK-NEXT: $x1 = COPY [[C]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[C2]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
;
; CHECK-CSSC-LABEL: name: s128_lower
@@ -152,11 +153,11 @@ body: |
; CHECK-CSSC-NEXT: {{ $}}
; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-CSSC-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[COPY]](s64)
- ; CHECK-CSSC-NEXT: [[CTPOP1:%[0-9]+]]:_(s64) = G_CTPOP [[COPY1]](s64)
- ; CHECK-CSSC-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[CTPOP]], [[CTPOP1]]
+ ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(i64) = G_CTPOP [[COPY]](s64)
+ ; CHECK-CSSC-NEXT: [[CTPOP1:%[0-9]+]]:_(i64) = G_CTPOP [[COPY1]](s64)
+ ; CHECK-CSSC-NEXT: [[ADD:%[0-9]+]]:_(i64) = G_ADD [[CTPOP]], [[CTPOP1]]
; CHECK-CSSC-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-CSSC-NEXT: $x0 = COPY [[ADD]](s64)
+ ; CHECK-CSSC-NEXT: $x0 = COPY [[ADD]](i64)
; CHECK-CSSC-NEXT: $x1 = COPY [[C]](s64)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%1:_(s64) = COPY $x0
@@ -180,15 +181,15 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[AND]](s64)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
- ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x s32>) = G_UADDLV [[CTPOP]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x s32>), [[C1]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT %copy(s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[AND]](i64)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x i8>) = G_CTPOP [[BITCAST]](<8 x i8>)
+ ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x i32>) = G_UADDLV [[CTPOP]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x i32>), [[C1]](i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -222,15 +223,15 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[AND]](s64)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
- ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x s32>) = G_UADDLV [[CTPOP]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x s32>), [[C1]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT %copy(s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[AND]](i64)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x i8>) = G_CTPOP [[BITCAST]](<8 x i8>)
+ ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x i32>) = G_UADDLV [[CTPOP]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x i32>), [[C1]](i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -264,15 +265,15 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[AND]](s64)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
- ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x s32>) = G_UADDLV [[CTPOP]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x s32>), [[C1]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT %copy(s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[AND]](i64)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x i8>) = G_CTPOP [[BITCAST]](<8 x i8>)
+ ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x i32>) = G_UADDLV [[CTPOP]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x i32>), [[C1]](i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -305,15 +306,15 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[AND]](s64)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
- ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x s32>) = G_UADDLV [[CTPOP]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x s32>), [[C1]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT %copy(s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[AND]](i64)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x i8>) = G_CTPOP [[BITCAST]](<8 x i8>)
+ ; CHECK-NEXT: [[UADDLV:%[0-9]+]]:_(<4 x i32>) = G_UADDLV [[CTPOP]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x i32>), [[C1]](i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](i32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -347,8 +348,8 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[COPY]](<8 x s16>)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[COPY]](<8 x s16>)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x i8>) = G_CTPOP [[BITCAST]](<16 x i8>)
; CHECK-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x s16>) = G_UADDLP [[CTPOP]]
; CHECK-NEXT: $q0 = COPY [[UADDLP]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -357,8 +358,8 @@ body: |
; CHECK-CSSC: liveins: $q0
; CHECK-CSSC-NEXT: {{ $}}
; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[COPY]](<8 x s16>)
- ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
+ ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[COPY]](<8 x s16>)
+ ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x i8>) = G_CTPOP [[BITCAST]](<16 x i8>)
; CHECK-CSSC-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x s16>) = G_UADDLP [[CTPOP]]
; CHECK-CSSC-NEXT: $q0 = COPY [[UADDLP]](<8 x s16>)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $q0
@@ -379,9 +380,9 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[COPY]](<4 x s32>)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
- ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x s16>) = G_UADDLP [[CTPOP]]
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x i8>) = G_CTPOP [[BITCAST]](<16 x i8>)
+ ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x i16>) = G_UADDLP [[CTPOP]]
; CHECK-NEXT: [[UADDLP1:%[0-9]+]]:_(<4 x s32>) = G_UADDLP [[UADDLP]]
; CHECK-NEXT: $q0 = COPY [[UADDLP1]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -390,9 +391,9 @@ body: |
; CHECK-CSSC: liveins: $q0
; CHECK-CSSC-NEXT: {{ $}}
; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[COPY]](<4 x s32>)
- ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
- ; CHECK-CSSC-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x s16>) = G_UADDLP [[CTPOP]]
+ ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[COPY]](<4 x s32>)
+ ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x i8>) = G_CTPOP [[BITCAST]](<16 x i8>)
+ ; CHECK-CSSC-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x i16>) = G_UADDLP [[CTPOP]]
; CHECK-CSSC-NEXT: [[UADDLP1:%[0-9]+]]:_(<4 x s32>) = G_UADDLP [[UADDLP]]
; CHECK-CSSC-NEXT: $q0 = COPY [[UADDLP1]](<4 x s32>)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $q0
@@ -413,10 +414,10 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
- ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x s16>) = G_UADDLP [[CTPOP]]
- ; CHECK-NEXT: [[UADDLP1:%[0-9]+]]:_(<4 x s32>) = G_UADDLP [[UADDLP]]
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[COPY]](<2 x s64>)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x i8>) = G_CTPOP [[BITCAST]](<16 x i8>)
+ ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x i16>) = G_UADDLP [[CTPOP]]
+ ; CHECK-NEXT: [[UADDLP1:%[0-9]+]]:_(<4 x i32>) = G_UADDLP [[UADDLP]]
; CHECK-NEXT: [[UADDLP2:%[0-9]+]]:_(<2 x s64>) = G_UADDLP [[UADDLP1]]
; CHECK-NEXT: $q0 = COPY [[UADDLP2]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -425,10 +426,10 @@ body: |
; CHECK-CSSC: liveins: $q0
; CHECK-CSSC-NEXT: {{ $}}
; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[COPY]](<2 x s64>)
- ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
- ; CHECK-CSSC-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x s16>) = G_UADDLP [[CTPOP]]
- ; CHECK-CSSC-NEXT: [[UADDLP1:%[0-9]+]]:_(<4 x s32>) = G_UADDLP [[UADDLP]]
+ ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[COPY]](<2 x s64>)
+ ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x i8>) = G_CTPOP [[BITCAST]](<16 x i8>)
+ ; CHECK-CSSC-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x i16>) = G_UADDLP [[CTPOP]]
+ ; CHECK-CSSC-NEXT: [[UADDLP1:%[0-9]+]]:_(<4 x i32>) = G_UADDLP [[UADDLP]]
; CHECK-CSSC-NEXT: [[UADDLP2:%[0-9]+]]:_(<2 x s64>) = G_UADDLP [[UADDLP1]]
; CHECK-CSSC-NEXT: $q0 = COPY [[UADDLP2]](<2 x s64>)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $q0
@@ -449,8 +450,8 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[COPY]](<4 x s16>)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x i8>) = G_CTPOP [[BITCAST]](<8 x i8>)
; CHECK-NEXT: [[UADDLP:%[0-9]+]]:_(<4 x s16>) = G_UADDLP [[CTPOP]]
; CHECK-NEXT: $d0 = COPY [[UADDLP]](<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -459,8 +460,8 @@ body: |
; CHECK-CSSC: liveins: $d0
; CHECK-CSSC-NEXT: {{ $}}
; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[COPY]](<4 x s16>)
- ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
+ ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[COPY]](<4 x s16>)
+ ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x i8>) = G_CTPOP [[BITCAST]](<8 x i8>)
; CHECK-CSSC-NEXT: [[UADDLP:%[0-9]+]]:_(<4 x s16>) = G_UADDLP [[CTPOP]]
; CHECK-CSSC-NEXT: $d0 = COPY [[UADDLP]](<4 x s16>)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $d0
@@ -481,9 +482,9 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
- ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:_(<4 x s16>) = G_UADDLP [[CTPOP]]
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x i8>) = G_CTPOP [[BITCAST]](<8 x i8>)
+ ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:_(<4 x i16>) = G_UADDLP [[CTPOP]]
; CHECK-NEXT: [[UADDLP1:%[0-9]+]]:_(<2 x s32>) = G_UADDLP [[UADDLP]]
; CHECK-NEXT: $d0 = COPY [[UADDLP1]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -492,9 +493,9 @@ body: |
; CHECK-CSSC: liveins: $d0
; CHECK-CSSC-NEXT: {{ $}}
; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[COPY]](<2 x s32>)
- ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
- ; CHECK-CSSC-NEXT: [[UADDLP:%[0-9]+]]:_(<4 x s16>) = G_UADDLP [[CTPOP]]
+ ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[COPY]](<2 x s32>)
+ ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x i8>) = G_CTPOP [[BITCAST]](<8 x i8>)
+ ; CHECK-CSSC-NEXT: [[UADDLP:%[0-9]+]]:_(<4 x i16>) = G_UADDLP [[CTPOP]]
; CHECK-CSSC-NEXT: [[UADDLP1:%[0-9]+]]:_(<2 x s32>) = G_UADDLP [[UADDLP]]
; CHECK-CSSC-NEXT: $d0 = COPY [[UADDLP1]](<2 x s32>)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
index 8b39ebd986dd7..e35b6a790eb54 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
@@ -145,9 +145,9 @@ body: |
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR %val, [[BUILD_VECTOR]]
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD %val, [[BUILD_VECTOR]]
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[XOR]], [[ADD]]
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[AND]](<4 x s32>)
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
- ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x s16>) = G_UADDLP [[CTPOP]]
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[AND]](<4 x s32>)
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x i8>) = G_CTPOP [[BITCAST]](<16 x i8>)
+ ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x i16>) = G_UADDLP [[CTPOP]]
; CHECK-NEXT: [[UADDLP1:%[0-9]+]]:_(<4 x s32>) = G_UADDLP [[UADDLP]]
; CHECK-NEXT: $q0 = COPY [[UADDLP1]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -161,9 +161,9 @@ body: |
; CHECK-CSSC-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR %val, [[BUILD_VECTOR]]
; CHECK-CSSC-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD %val, [[BUILD_VECTOR]]
; CHECK-CSSC-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[XOR]], [[ADD]]
- ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[AND]](<4 x s32>)
- ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
- ; CHECK-CSSC-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x s16>) = G_UADDLP [[CTPOP]]
+ ; CHECK-CSSC-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[AND]](<4 x s32>)
+ ; CHECK-CSSC-NEXT: [[CTPOP:%[0-9]+]]:_(<16 x i8>) = G_CTPOP [[BITCAST]](<16 x i8>)
+ ; CHECK-CSSC-NEXT: [[UADDLP:%[0-9]+]]:_(<8 x i16>) = G_UADDLP [[CTPOP]]
; CHECK-CSSC-NEXT: [[UADDLP1:%[0-9]+]]:_(<4 x s32>) = G_UADDLP [[UADDLP]]
; CHECK-CSSC-NEXT: $q0 = COPY [[UADDLP1]](<4 x s32>)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $q0
>From 0f0ec6c4d1b11aea11e442288a23ac1cf9ff41e5 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 25 Feb 2026 16:18:52 +0000
Subject: [PATCH 28/30] Build types instead of mutating in
AArch64PreLegalizerCombiner
---
.../GISel/AArch64PreLegalizerCombiner.cpp | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 29fef5f64f574..8725fdb4fcc5b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -479,13 +479,13 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
SmallVector<Register, 4> LeftoverRegs;
if (SrcScalSize == 8)
MainTy =
- LLT::fixed_vector(16, SrcTy.getScalarType().changeElementSize(8));
+ LLT::fixed_vector(16, LLT::buildInteger(8));
else if (SrcScalSize == 16)
MainTy =
- LLT::fixed_vector(8, SrcTy.getScalarType().changeElementSize(16));
+ LLT::fixed_vector(8, LLT::buildInteger(16));
else if (SrcScalSize == 32)
MainTy =
- LLT::fixed_vector(4, SrcTy.getScalarType().changeElementSize(32));
+ LLT::fixed_vector(4, LLT::buildInteger(32));
else
llvm_unreachable("Source's Scalar Size not supported");
@@ -500,8 +500,7 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
}
unsigned MidScalarSize = MainTy.getScalarSizeInBits() * 2;
- LLT MidScalarLLT =
- MainTy.changeElementSize(MidScalarSize).changeElementCount(1);
+ LLT MidScalarLLT = LLT::buildInteger(MidScalarSize);
Register ZeroReg = B.buildConstant(LLT::buildInteger(64), 0).getReg(0);
for (unsigned I = 0; I < WorkingRegisters.size(); I++) {
// If the number of elements is too small to build an instruction, extend
@@ -518,9 +517,8 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
// Generate the {U/S}ADDLV instruction, whose output is always double of the
// Src's Scalar size
- LLT AddlvTy = MidScalarSize <= 32
- ? MainTy.changeElementSize(32).changeElementCount(4)
- : MainTy.changeElementSize(64).changeElementCount(2);
+ LLT AddlvTy = MidScalarSize <= 32 ? LLT::fixed_vector(4, LLT::buildInteger(32))
+ : LLT::fixed_vector(2, LLT::buildInteger(64));
Register AddlvReg =
B.buildInstr(Opc, {AddlvTy}, {WorkingRegisters[I]}).getReg(0);
@@ -536,7 +534,7 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
} else {
Register ExtractReg =
B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT,
- {DstTy.changeElementSize(32)}, {AddlvReg, ZeroReg})
+ {LLT::buildInteger(32)}, {AddlvReg, ZeroReg})
.getReg(0);
WorkingRegisters[I] =
B.buildTrunc({MidScalarLLT}, {ExtractReg}).getReg(0);
>From b50192ef23ae3f973da03fd8ea665df936fb0456 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Wed, 8 Apr 2026 09:13:29 +0100
Subject: [PATCH 29/30] Fix buildInteger -> integer
---
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 8 ++++----
.../Target/AArch64/GISel/AArch64CallLowering.cpp | 10 +++++-----
.../AArch64/GISel/AArch64InstructionSelector.cpp | 4 ++--
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +-
.../GISel/AArch64PostLegalizerCombiner.cpp | 4 ++--
.../GISel/AArch64PostLegalizerLowering.cpp | 6 +++---
.../GISel/AArch64PreLegalizerCombiner.cpp | 16 ++++++++--------
7 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 5bb15b7fee954..923bea3379913 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18966,14 +18966,14 @@ LLT AArch64TargetLowering::getOptimalMemOpLLT(
// NEON dup + scalar store works for any alignment and is efficient.
if (CanUseNEON && Op.isMemset() && !IsSmallZeroMemset &&
AlignmentIsAcceptable(MVT::v16i8, Align(1)))
- return LLT::fixed_vector(2, LLT::buildInteger(64));
+ return LLT::fixed_vector(2, LLT::integer(64));
if (CanUseFP && !IsSmallZeroMemset &&
AlignmentIsAcceptable(MVT::f128, Align(16)))
- return LLT::buildFloatingIEEE(128);
+ return LLT::floatIEEE(128);
if (Op.size() >= 8 && AlignmentIsAcceptable(MVT::i64, Align(8)))
- return LLT::buildInteger(64);
+ return LLT::integer(64);
if (Op.size() >= 4 && AlignmentIsAcceptable(MVT::i32, Align(4)))
- return LLT::buildInteger(32);
+ return LLT::integer(32);
return LLT();
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 8f805e8baf72c..128baae4e6cda 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -259,7 +259,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
ISD::ArgFlagsTy Flags) override {
MachineFunction &MF = MIRBuilder.getMF();
LLT p0 = LLT::pointer(0, 64);
- LLT s64 = LLT::buildInteger(64);
+ LLT s64 = LLT::integer(64);
if (IsTailCall) {
assert(!Flags.isByVal() && "byval unhandled with tail calls");
@@ -446,7 +446,7 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
auto &Flags = CurArgInfo.Flags[0];
if (MRI.getType(CurVReg).getSizeInBits() == TypeSize::getFixed(1) &&
!Flags.isSExt() && !Flags.isZExt()) {
- CurVReg = MIRBuilder.buildZExt(LLT::buildInteger(8), CurVReg).getReg(0);
+ CurVReg = MIRBuilder.buildZExt(LLT::integer(8), CurVReg).getReg(0);
} else if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) ==
1) {
// Some types will need extending as specified by the CC.
@@ -630,7 +630,7 @@ void AArch64CallLowering::saveVarArgRegisters(
bool IsWin64CC = Subtarget.isCallingConvWin64(CCInfo.getCallingConv(),
MF.getFunction().isVarArg());
const LLT p0 = LLT::pointer(0, 64);
- const LLT s64 = LLT::buildInteger(64);
+ const LLT s64 = LLT::integer(64);
unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
unsigned NumVariadicGPRArgRegs = GPRArgRegs.size() - FirstVariadicGPR + 1;
@@ -755,7 +755,7 @@ bool AArch64CallLowering::lowerFormalArguments(
// Lower i1 argument as i8, and insert AssertZExt + Trunc later.
Register OrigReg = OrigArg.Regs[0];
Register WideReg =
- MRI.createGenericVirtualRegister(LLT::buildInteger(8));
+ MRI.createGenericVirtualRegister(LLT::integer(8));
OrigArg.Regs[0] = WideReg;
BoolArgs.push_back({OrigReg, WideReg});
}
@@ -1361,7 +1361,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// We cannot use a ZExt ArgInfo flag here, because it will
// zero-extend the argument to i32 instead of just i8.
OutArg.Regs[0] =
- MIRBuilder.buildZExt(LLT::buildInteger(8), OutArg.Regs[0]).getReg(0);
+ MIRBuilder.buildZExt(LLT::integer(8), OutArg.Regs[0]).getReg(0);
LLVMContext &Ctx = MF.getFunction().getContext();
OutArg.Ty = Type::getInt8Ty(Ctx);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 4308b7ae71335..dbaa056bb7b58 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2258,8 +2258,8 @@ bool AArch64InstructionSelector::convertPtrAddToAdd(
return false;
const LLT CastPtrTy = PtrTy.isVector()
- ? LLT::fixed_vector(2, LLT::buildInteger(64))
- : LLT::buildInteger(64);
+ ? LLT::fixed_vector(2, LLT::integer(64))
+ : LLT::integer(64);
auto PtrToInt = MIB.buildPtrToInt(CastPtrTy, AddOp1Reg);
// Set regbanks on the registers.
if (PtrTy.isVector())
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index c38268f3666dc..7b2563fceed1a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -2415,7 +2415,7 @@ bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
bool AArch64LegalizerInfo::legalizeAtomicCmpxchg128(
MachineInstr &MI, MachineRegisterInfo &MRI, LegalizerHelper &Helper) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
- LLT i64 = LLT::buildInteger(64);
+ LLT i64 = LLT::integer(64);
auto Addr = MI.getOperand(1).getReg();
auto DesiredI = MIRBuilder.buildUnmerge({i64, i64}, MI.getOperand(2));
auto NewI = MIRBuilder.buildUnmerge({i64, i64}, MI.getOperand(3));
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index a4572c6efd55f..ba0d9b542d1e9 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -222,7 +222,7 @@ bool matchAArch64MulConstCombine(
return false;
ApplyFn = [=](MachineIRBuilder &B, Register DstReg) {
- auto Shift = B.buildConstant(LLT::buildInteger(64), ShiftAmt);
+ auto Shift = B.buildConstant(LLT::integer(64), ShiftAmt);
auto ShiftedVal = B.buildShl(Ty, LHS, Shift);
Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS;
@@ -238,7 +238,7 @@ bool matchAArch64MulConstCombine(
// Shift the result.
if (TrailingZeroes) {
B.buildShl(DstReg, Res,
- B.buildConstant(LLT::buildInteger(64), TrailingZeroes));
+ B.buildConstant(LLT::integer(64), TrailingZeroes));
return;
}
B.buildCopy(DstReg, Res.getReg(0));
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index c15e735912f91..7f234192fdf74 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -559,9 +559,9 @@ void applyINS(MachineInstr &MI, MachineRegisterInfo &MRI,
Register DstVec, SrcVec;
int DstLane, SrcLane;
std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo;
- auto SrcCst = Builder.buildConstant(LLT::buildInteger(64), SrcLane);
+ auto SrcCst = Builder.buildConstant(LLT::integer(64), SrcLane);
auto Extract = Builder.buildExtractVectorElement(ScalarTy, SrcVec, SrcCst);
- auto DstCst = Builder.buildConstant(LLT::buildInteger(64), DstLane);
+ auto DstCst = Builder.buildConstant(LLT::integer(64), DstLane);
Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst);
MI.eraseFromParent();
}
@@ -1107,7 +1107,7 @@ void applyLowerBuildToInsertVecElt(MachineInstr &MI, MachineRegisterInfo &MRI,
Register SrcReg = GBuildVec->getSourceReg(I);
if (mi_match(SrcReg, MRI, m_GImplicitDef()))
continue;
- auto IdxReg = B.buildConstant(LLT::buildInteger(64), I);
+ auto IdxReg = B.buildConstant(LLT::integer(64), I);
DstReg =
B.buildInsertVectorElement(DstTy, DstReg, SrcReg, IdxReg).getReg(0);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 8725fdb4fcc5b..bfd6738bee688 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -479,13 +479,13 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
SmallVector<Register, 4> LeftoverRegs;
if (SrcScalSize == 8)
MainTy =
- LLT::fixed_vector(16, LLT::buildInteger(8));
+ LLT::fixed_vector(16, LLT::integer(8));
else if (SrcScalSize == 16)
MainTy =
- LLT::fixed_vector(8, LLT::buildInteger(16));
+ LLT::fixed_vector(8, LLT::integer(16));
else if (SrcScalSize == 32)
MainTy =
- LLT::fixed_vector(4, LLT::buildInteger(32));
+ LLT::fixed_vector(4, LLT::integer(32));
else
llvm_unreachable("Source's Scalar Size not supported");
@@ -500,8 +500,8 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
}
unsigned MidScalarSize = MainTy.getScalarSizeInBits() * 2;
- LLT MidScalarLLT = LLT::buildInteger(MidScalarSize);
- Register ZeroReg = B.buildConstant(LLT::buildInteger(64), 0).getReg(0);
+ LLT MidScalarLLT = LLT::integer(MidScalarSize);
+ Register ZeroReg = B.buildConstant(LLT::integer(64), 0).getReg(0);
for (unsigned I = 0; I < WorkingRegisters.size(); I++) {
// If the number of elements is too small to build an instruction, extend
// its size before applying addlv
@@ -517,8 +517,8 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
// Generate the {U/S}ADDLV instruction, whose output is always double of the
// Src's Scalar size
- LLT AddlvTy = MidScalarSize <= 32 ? LLT::fixed_vector(4, LLT::buildInteger(32))
- : LLT::fixed_vector(2, LLT::buildInteger(64));
+ LLT AddlvTy = MidScalarSize <= 32 ? LLT::fixed_vector(4, LLT::integer(32))
+ : LLT::fixed_vector(2, LLT::integer(64));
Register AddlvReg =
B.buildInstr(Opc, {AddlvTy}, {WorkingRegisters[I]}).getReg(0);
@@ -534,7 +534,7 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
} else {
Register ExtractReg =
B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT,
- {LLT::buildInteger(32)}, {AddlvReg, ZeroReg})
+ {LLT::integer(32)}, {AddlvReg, ZeroReg})
.getReg(0);
WorkingRegisters[I] =
B.buildTrunc({MidScalarLLT}, {ExtractReg}).getReg(0);
>From 1bf074dc63b3bb3dfd3b6e3a8a180bd657323ea2 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Thu, 9 Apr 2026 07:21:44 +0100
Subject: [PATCH 30/30] Rebase and updates. Remove all BF16 lowering for the
time being.
---
.../GlobalISel/GIMatchTableExecutorImpl.h | 88 +-
.../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 36 -
llvm/include/llvm/Target/GenericOpcodes.td | 9 +
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 28 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 +-
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 69 +-
llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp | 9 +-
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 4 +-
llvm/lib/CodeGen/RegisterBankInfo.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 4 +
.../AArch64/GISel/AArch64CallLowering.cpp | 3 +-
.../GISel/AArch64InstructionSelector.cpp | 2 +-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 47 +-
.../GISel/AArch64PostLegalizerCombiner.cpp | 11 +-
.../GISel/AArch64PostLegalizerLowering.cpp | 20 +-
.../GISel/AArch64PreLegalizerCombiner.cpp | 42 +-
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 23 +-
.../Atomics/aarch64-atomic-store-rcpc_immo.ll | 2 +-
.../AArch64/Atomics/aarch64-atomicrmw-lsfe.ll | 100 +-
.../Atomics/aarch64-atomicrmw-v8a_fp.ll | 600 ++---
.../CodeGen/AArch64/GlobalISel/166563.mir | 88 +-
.../AArch64/GlobalISel/arm64-atomic.ll | 194 +-
.../AArch64/GlobalISel/arm64-fallback.ll | 1 -
.../GlobalISel/arm64-irtranslator-switch.ll | 8 +-
.../AArch64/GlobalISel/arm64-irtranslator.ll | 56 +-
.../GlobalISel/arm64-regbankselect.mir | 22 +-
.../AArch64/GlobalISel/arm64-this-return.ll | 32 +-
.../AArch64/GlobalISel/combine-udiv.mir | 16 +-
.../GlobalISel/inline-memcpy-forced.mir | 48 +-
.../AArch64/GlobalISel/inline-memcpy.mir | 132 +-
.../AArch64/GlobalISel/inline-memmove.mir | 4 +-
.../AArch64/GlobalISel/inline-memset.mir | 4 +-
.../GlobalISel/inline-small-memcpy.mir | 6 +-
.../AArch64/GlobalISel/inttoptr_add.ll | 4 +-
.../irtranslator-constrained-fcmp.ll | 64 +-
.../irtranslator-convert-fp16-intrinsics.ll | 34 -
.../GlobalISel/irtranslator-inline-asm.ll | 34 +-
.../GlobalISel/irtranslator-switch-bittest.ll | 20 +-
.../irtranslator-unwind-inline-asm.ll | 2 +-
.../AArch64/GlobalISel/legalize-add.mir | 18 +-
.../AArch64/GlobalISel/legalize-and.mir | 352 +--
.../GlobalISel/legalize-bitreverse.mir | 30 +-
.../AArch64/GlobalISel/legalize-bswap.mir | 16 +-
.../AArch64/GlobalISel/legalize-constant.mir | 68 +-
.../AArch64/GlobalISel/legalize-ctlz.mir | 14 +-
.../AArch64/GlobalISel/legalize-ctpop.mir | 4 +-
.../AArch64/GlobalISel/legalize-cttz.mir | 8 +-
.../GlobalISel/legalize-dyn-alloca.mir | 44 +-
.../legalize-extract-vector-elt.mir | 12 +-
.../AArch64/GlobalISel/legalize-fp-class.mir | 48 +-
.../AArch64/GlobalISel/legalize-fpenv.mir | 4 +-
.../AArch64/GlobalISel/legalize-fpmode.mir | 4 +-
.../AArch64/GlobalISel/legalize-fshl.mir | 16 +-
.../AArch64/GlobalISel/legalize-fshr.mir | 12 +-
.../AArch64/GlobalISel/legalize-inserts.mir | 311 +--
...lize-load-store-vector-of-ptr-debugloc.mir | 4 +-
.../legalize-load-store-vector-of-ptr.mir | 8 +-
.../GlobalISel/legalize-load-store.mir | 42 +-
.../legalize-non-pow2-load-store.mir | 98 +-
.../AArch64/GlobalISel/legalize-or.mir | 24 +-
.../AArch64/GlobalISel/legalize-phi.mir | 16 +-
.../AArch64/GlobalISel/legalize-rotr-rotl.mir | 8 +-
.../AArch64/GlobalISel/legalize-sadde.mir | 18 +-
.../AArch64/GlobalISel/legalize-saddo.mir | 6 +-
.../AArch64/GlobalISel/legalize-saddsat.mir | 29 +-
.../AArch64/GlobalISel/legalize-select.mir | 140 +-
.../GlobalISel/legalize-sext-zext-128.mir | 10 +-
.../AArch64/GlobalISel/legalize-shift.mir | 74 +-
.../GlobalISel/legalize-shuffle-vector.mir | 8 +-
.../AArch64/GlobalISel/legalize-ssube.mir | 18 +-
.../AArch64/GlobalISel/legalize-ssubo.mir | 6 +-
.../AArch64/GlobalISel/legalize-ssubsat.mir | 29 +-
.../AArch64/GlobalISel/legalize-sub.mir | 10 +-
.../AArch64/GlobalISel/legalize-uadde.mir | 18 +-
.../AArch64/GlobalISel/legalize-uaddo.mir | 6 +-
.../AArch64/GlobalISel/legalize-usube.mir | 18 +-
.../AArch64/GlobalISel/legalize-usubo.mir | 6 +-
.../AArch64/GlobalISel/legalize-xor.mir | 70 +-
.../GlobalISel/load-addressing-modes.mir | 336 +--
.../GlobalISel/load-wro-addressing-modes.mir | 146 +-
.../GlobalISel/lower-neon-vector-fcmp.mir | 118 +-
.../GlobalISel/merge-stores-truncating.mir | 4 +-
.../AArch64/GlobalISel/opt-and-tbnz-tbz.mir | 80 +-
.../GlobalISel/opt-fold-and-tbz-tbnz.mir | 42 +-
.../AArch64/GlobalISel/opt-fold-compare.mir | 306 +--
.../GlobalISel/opt-fold-shift-tbz-tbnz.mir | 160 +-
.../GlobalISel/opt-fold-xor-tbz-tbnz.mir | 84 +-
...stlegalizer-combiner-split-zero-stores.mir | 30 +-
...legalizer-lowering-build-vector-to-dup.mir | 106 +-
.../GlobalISel/postlegalizer-lowering-ext.mir | 56 +-
.../GlobalISel/postlegalizer-lowering-rev.mir | 4 +-
...postlegalizer-lowering-shuffle-duplane.mir | 20 +-
.../postlegalizer-lowering-shuffle-splat.mir | 4 +-
...galizer-lowering-swap-compare-operands.mir | 492 ++--
.../GlobalISel/postlegalizer-lowering-zip.mir | 4 +-
...postlegalizercombiner-extractvec-faddp.mir | 32 +-
.../CodeGen/AArch64/GlobalISel/pr168872.ll | 16 +-
...izer-combiner-narrow-binop-feeding-add.mir | 48 +-
.../GlobalISel/regbank-assert-sext.mir | 16 +-
.../GlobalISel/regbank-assert-zext.mir | 16 +-
.../AArch64/GlobalISel/regbank-dup.mir | 4 +-
.../AArch64/GlobalISel/regbank-fmaximum.mir | 4 +-
.../AArch64/GlobalISel/regbank-fminimum.mir | 4 +-
.../AArch64/GlobalISel/regbank-fp-use-def.mir | 14 +-
.../AArch64/GlobalISel/regbank-llround.mir | 4 +-
.../AArch64/GlobalISel/regbank-lround.mir | 4 +-
.../AArch64/GlobalISel/regbank-maxnum.mir | 4 +-
.../AArch64/GlobalISel/regbank-minnum.mir | 4 +-
.../AArch64/GlobalISel/regbank-select.mir | 4 +-
.../GlobalISel/regbankselect-build-vector.mir | 54 +-
.../CodeGen/AArch64/GlobalISel/select-abs.mir | 36 +-
.../GlobalISel/select-arith-extended-reg.mir | 348 +--
.../GlobalISel/select-arith-shifted-reg.mir | 192 +-
.../AArch64/GlobalISel/select-binop.mir | 316 +--
.../AArch64/GlobalISel/select-bitreverse.mir | 24 +-
.../GlobalISel/select-brcond-of-binop.mir | 52 +-
.../CodeGen/AArch64/GlobalISel/select-cmp.mir | 194 +-
.../GlobalISel/select-constbarrier.mir | 12 +-
.../AArch64/GlobalISel/select-ctlz.mir | 52 +-
.../AArch64/GlobalISel/select-ctpop.mir | 12 +-
.../AArch64/GlobalISel/select-cttz.mir | 12 +-
.../AArch64/GlobalISel/select-dbg-value.mir | 14 +-
.../CodeGen/AArch64/GlobalISel/select-dup.mir | 4 +-
.../CodeGen/AArch64/GlobalISel/select-fma.mir | 8 +-
.../GlobalISel/select-gv-cmodel-large.mir | 8 +-
.../GlobalISel/select-gv-cmodel-tiny.mir | 8 +-
.../GlobalISel/select-implicit-def.mir | 12 +-
.../AArch64/GlobalISel/select-int-ext.mir | 128 +-
.../GlobalISel/select-int-ptr-casts.mir | 24 +-
.../GlobalISel/select-jump-table-brjt.mir | 36 +-
.../AArch64/GlobalISel/select-logical-imm.mir | 48 +-
.../GlobalISel/select-logical-shifted-reg.mir | 42 +-
.../CodeGen/AArch64/GlobalISel/select-mul.mir | 58 +-
.../AArch64/GlobalISel/select-muladd.mir | 14 +-
.../GlobalISel/select-neon-vector-fcmp.mir | 74 +-
.../CodeGen/AArch64/GlobalISel/select-phi.mir | 20 +-
.../AArch64/GlobalISel/select-pr32733.mir | 12 +-
.../AArch64/GlobalISel/select-reduce-add.mir | 38 +-
.../GlobalISel/select-redundant-zext.mir | 62 +-
.../AArch64/GlobalISel/select-rotate.mir | 26 +-
.../GlobalISel/select-scalar-shift-imm.mir | 84 +-
.../AArch64/GlobalISel/select-select.mir | 330 +--
.../AArch64/GlobalISel/select-sextload.mir | 10 +-
.../GlobalISel/select-stlxr-intrin.mir | 38 +-
.../CodeGen/AArch64/GlobalISel/select-stx.mir | 38 +-
.../AArch64/GlobalISel/select-trunc.mir | 30 +-
.../GlobalISel/select-unreachable-blocks.mir | 18 +-
.../AArch64/GlobalISel/select-vector-icmp.mir | 844 +++----
.../GlobalISel/select-vector-shift.mir | 172 +-
.../select-with-no-legality-check.mir | 804 +++----
.../CodeGen/AArch64/GlobalISel/select-xor.mir | 40 +-
.../GlobalISel/select-zext-as-copy.mir | 8 +-
.../AArch64/GlobalISel/select-zextload.mir | 44 +-
.../GlobalISel/sext-inreg-ldrow-16b.mir | 20 +-
.../AArch64/GlobalISel/store-merging.ll | 13 +
.../CodeGen/AArch64/GlobalISel/tbz-sgt.mir | 36 +-
llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll | 43 +-
.../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 2103 ++++++++++++++---
llvm/test/CodeGen/AArch64/arm64-fp128.ll | 26 +-
llvm/test/CodeGen/AArch64/arm64-neon-copy.ll | 5 +
llvm/test/CodeGen/AArch64/arm64-smaxv.ll | 85 +-
llvm/test/CodeGen/AArch64/arm64-sminv.ll | 85 +-
llvm/test/CodeGen/AArch64/arm64-vaddv.ll | 7 +-
.../test/CodeGen/AArch64/bf16-instructions.ll | 72 +-
llvm/test/CodeGen/AArch64/bitcast-extend.ll | 45 +-
llvm/test/CodeGen/AArch64/fcmp.ll | 80 +-
.../test/CodeGen/AArch64/fptosi-sat-scalar.ll | 61 +-
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 623 +++--
.../test/CodeGen/AArch64/fptoui-sat-scalar.ll | 51 +-
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 602 ++---
.../CodeGen/AArch64/neon-extadd-extract.ll | 2 +-
llvm/test/CodeGen/AArch64/phi.ll | 18 +-
llvm/test/CodeGen/AArch64/popcount.ll | 43 +-
llvm/test/CodeGen/AArch64/select_const.ll | 24 +
llvm/test/CodeGen/AArch64/store.ll | 23 +
.../AMDGPU/GlobalISel/legalize-fcopysign.mir | 216 +-
.../GlobalISelEmitter/GlobalISelEmitter.td | 6 +-
.../GlobalISel/LegalizerHelperTest.cpp | 80 +-
llvm/utils/TableGen/GlobalISelEmitter.cpp | 2 +-
179 files changed, 7779 insertions(+), 6659 deletions(-)
delete mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index 344686309d5d2..4576dff67db0c 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -259,98 +259,23 @@ bool GIMatchTableExecutor::executeMatchTable(
OnFailResumeAt.push_back(Default);
break;
}
- case GIM_SwitchType: {
- uint64_t InsnID = readULEB();
- uint64_t OpIdx = readULEB();
- uint16_t LowerBound = readU16();
- uint16_t UpperBound = readU16();
- int64_t Default = readU32();
- assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
- MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
-
- DEBUG_WITH_TYPE(TgtExecutor::getName(), {
- dbgs() << CurrentIdx << ": GIM_SwitchType(MIs[" << InsnID
- << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", "
- << UpperBound << "), Default=" << Default
- << ", JumpTable...) // Got=";
- if (!MO.isReg())
- dbgs() << "Not a VReg\n";
- else
- dbgs() << MRI.getType(MO.getReg());
- });
- if (!MO.isReg()) {
- CurrentIdx = Default;
- break;
- }
- const LLT Ty = MRI.getType(MO.getReg());
-
- SmallVector<LLT> TypesToTry;
- TypesToTry.push_back(Ty);
-
- // Always try the integer patterns as we now consider that to be generic
- // (to an extent)
- if (LLT::getUseExtended() && Ty.getScalarType().isAnyScalar()) {
- TypesToTry.push_back(
- Ty.changeElementType(LLT::integer(Ty.getScalarSizeInBits())));
-
- if (Ty.getScalarSizeInBits() > 8)
- TypesToTry.push_back(
- Ty.changeElementType(LLT::floatIEEE(Ty.getScalarSizeInBits())));
- }
-
- const auto JumpTableBase = CurrentIdx;
- bool Matched = false;
- for (LLT Type : TypesToTry) {
- const auto TyI = ExecInfo.TypeIDMap.find(Type.getUniqueRAWLLTData());
- if (TyI == ExecInfo.TypeIDMap.end())
- continue;
- const int64_t TypeID = TyI->second;
- if (TypeID < LowerBound || UpperBound <= TypeID)
- continue;
- const auto NumEntry = (TypeID - LowerBound);
- if (Matched) {
- auto Idx = readBytesAs<uint32_t>(MatchTable + JumpTableBase +
- (NumEntry * 4));
- if (Idx)
- OnFailResumeAt.push_back(Idx);
-
- continue;
- }
- // Each entry is 4 bytes
- CurrentIdx =
- readBytesAs<uint32_t>(MatchTable + JumpTableBase + (NumEntry * 4));
- if (!CurrentIdx) {
- CurrentIdx = Default;
- continue;
- }
- Matched = true;
-
- DEBUG_WITH_TYPE(TgtExecutor::getName(),
- { dbgs() << ", matched as=" << Type << "\n"; });
- }
- if (!Matched) {
- CurrentIdx = Default;
- break;
- }
-
- OnFailResumeAt.push_back(Default);
- break;
- }
+ case GIM_SwitchType:
case GIM_SwitchTypeShape: {
uint64_t InsnID = readULEB();
uint64_t OpIdx = readULEB();
uint16_t LowerBound = readU16();
uint16_t UpperBound = readU16();
int64_t Default = readU32();
+ bool IsShape = MatcherOpcode == GIM_SwitchTypeShape;
assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
DEBUG_WITH_TYPE(TgtExecutor::getName(), {
- dbgs() << CurrentIdx << ": GIM_SwitchTypeShape(MIs[" << InsnID
- << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", "
- << UpperBound << "), Default=" << Default
+ dbgs() << CurrentIdx << ": GIM_SwitchType" << (IsShape ? "Shape" : "")
+ << "(MIs[" << InsnID << "]->getOperand(" << OpIdx << "), ["
+ << LowerBound << ", " << UpperBound << "), Default=" << Default
<< ", JumpTable...) // Got=";
if (!MO.isReg())
dbgs() << "Not a VReg\n";
@@ -363,7 +288,8 @@ bool GIMatchTableExecutor::executeMatchTable(
}
LLT Ty = MRI.getType(MO.getReg());
- Ty = Ty.changeElementType(LLT::scalar(Ty.getScalarSizeInBits()));
+ if (IsShape)
+ Ty = Ty.changeElementType(LLT::scalar(Ty.getScalarSizeInBits()));
const auto TyI = ExecInfo.TypeIDMap.find(Ty.getUniqueRAWLLTData());
if (TyI == ExecInfo.TypeIDMap.end()) {
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index 438076440efa2..8d27f85c04b87 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -870,42 +870,6 @@ class LegalizeRuleSet {
return actionFor(LegalizeAction::NarrowScalar, Types, Mutation);
}
- /// Promote bf16 operands/results to \p PromoteEltTy so the operation executes
- /// in that wider type before truncating back to bf16.
- LegalizeRuleSet &convertBF16(unsigned TypeIdx = 0,
- LLT PromoteEltTy = LLT::float32()) {
- assert(!PromoteEltTy.isVector() && PromoteEltTy.isScalar() &&
- PromoteEltTy.isFloat() &&
- "convertBF16 expects a floating-point scalar promotion type");
- typeIdx(TypeIdx);
- const LLT BF16Ty = LLT::bfloat16();
- return actionIf(
- LegalizeAction::WidenScalar,
- [=](const LegalityQuery &Query) {
- if (TypeIdx >= Query.Types.size())
- return false;
- const LLT Ty = Query.Types[TypeIdx];
- if (!Ty.isValid())
- return false;
- if (Ty.isAnyScalar() || Ty.isAnyVector())
- return false;
- if (Ty == BF16Ty)
- return true;
- if (Ty.isVector() && Ty.getElementType() == BF16Ty)
- return true;
- return false;
- },
- LegalizeMutations::changeElementTo(TypeIdx, PromoteEltTy));
- }
-
- /// Conditionally promote bf16 operands/results to \p PromoteEltTy.
- LegalizeRuleSet &convertBF16(bool Enable, unsigned TypeIdx = 0,
- LLT PromoteEltTy = LLT::float32()) {
- if (!Enable)
- return *this;
- return convertBF16(TypeIdx, PromoteEltTy);
- }
-
/// Add more elements to reach the type selected by the mutation if the
/// predicate is true.
LegalizeRuleSet &moreElementsIf(LegalityPredicate Predicate,
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index cfd6f5dbba9a6..20f97eb7f9169 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -84,6 +84,7 @@ def G_TRUNC : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Truncate the signed operand to a signed result with saturation.
@@ -111,12 +112,14 @@ def G_IMPLICIT_DEF : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
def G_PHI : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins variable_ops);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
def G_FRAME_INDEX : GenericInstruction {
@@ -167,6 +170,7 @@ def G_CONSTANT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$imm);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
// Only supports scalar result types
@@ -174,6 +178,7 @@ def G_FCONSTANT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$imm);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
def G_VASTART : GenericInstruction {
@@ -231,6 +236,7 @@ def G_BSWAP : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
let hasSideEffects = false;
+ let GISelMatchGenericTypes = 1;
}
def G_BITREVERSE : GenericInstruction {
@@ -1409,6 +1415,7 @@ def G_ATOMIC_CMPXCHG_WITH_SUCCESS : GenericInstruction {
let hasSideEffects = false;
let mayLoad = true;
let mayStore = true;
+ let GISelMatchGenericTypes = 1;
}
// Generic atomic cmpxchg. Expects a MachineMemOperand in addition to explicit
@@ -1419,6 +1426,7 @@ def G_ATOMIC_CMPXCHG : GenericInstruction {
let hasSideEffects = false;
let mayLoad = true;
let mayStore = true;
+ let GISelMatchGenericTypes = 1;
}
// Generic atomicrmw. Expects a MachineMemOperand in addition to explicit
@@ -1429,6 +1437,7 @@ class G_ATOMICRMW_OP : GenericInstruction {
let hasSideEffects = false;
let mayLoad = true;
let mayStore = true;
+ let GISelMatchGenericTypes = 1;
}
def G_ATOMICRMW_XCHG : G_ATOMICRMW_OP;
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 0a7d682c44049..9a9ba9b6b33f0 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2358,22 +2358,9 @@ void CombinerHelper::applyCombineUnmergeConstant(
assert((MI.getNumOperands() - 1 == Csts.size()) &&
"Not enough operands to replace all defs");
unsigned NumElems = MI.getNumOperands() - 1;
-
- Register SrcReg = MI.getOperand(NumElems).getReg();
-
- if (MRI.getType(SrcReg).isFloat()) {
- APFloat Val(getFltSemanticForLLT(MRI.getType(MI.getOperand(0).getReg())));
-
- for (unsigned Idx = 0; Idx < NumElems; ++Idx) {
- Register DstReg = MI.getOperand(Idx).getReg();
- Val.convertFromAPInt(Csts[Idx], false, detail::rmTowardZero);
- Builder.buildFConstant(DstReg, Val);
- }
- } else {
- for (unsigned Idx = 0; Idx < NumElems; ++Idx) {
- Register DstReg = MI.getOperand(Idx).getReg();
- Builder.buildConstant(DstReg, Csts[Idx]);
- }
+ for (unsigned Idx = 0; Idx < NumElems; ++Idx) {
+ Register DstReg = MI.getOperand(Idx).getReg();
+ Builder.buildConstant(DstReg, Csts[Idx]);
}
MI.eraseFromParent();
@@ -5445,7 +5432,7 @@ bool CombinerHelper::matchNarrowBinopFeedingAnd(
unsigned NarrowWidth = Mask.countr_one();
if (NarrowWidth == WideTy.getSizeInBits())
return false;
- LLT NarrowTy = LLT::scalar(NarrowWidth);
+ LLT NarrowTy = LLT::integer(NarrowWidth);
// Check if adding the zext + truncates could be harmful.
auto &MF = *MI.getMF();
@@ -5746,7 +5733,8 @@ MachineInstr *CombinerHelper::buildUDivOrURemUsingMul(MachineInstr &MI) const {
auto One = MIB.buildConstant(Ty, 1);
auto IsOne = MIB.buildICmp(
CmpInst::Predicate::ICMP_EQ,
- Ty.isScalar() ? LLT::scalar(1) : Ty.changeElementSize(1), RHS, One);
+ Ty.isScalar() ? LLT::integer(1) : Ty.changeElementType(LLT::integer(1)),
+ RHS, One);
auto ret = MIB.buildSelect(Ty, IsOne, LHS, Q);
if (Opcode == TargetOpcode::G_UREM) {
@@ -6033,8 +6021,8 @@ void CombinerHelper::applySDivByPow2(MachineInstr &MI) const {
Register RHS = SDiv.getReg(2);
LLT Ty = MRI.getType(Dst);
LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty);
- LLT CCVT =
- Ty.isVector() ? LLT::vector(Ty.getElementCount(), 1) : LLT::scalar(1);
+ LLT CCVT = Ty.isVector() ? LLT::vector(Ty.getElementCount(), LLT::integer(1))
+ : LLT::integer(1);
// Effectively we want to lower G_SDIV %lhs, %rhs, where %rhs is a power of 2,
// to the following version:
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 89daec05f7135..0ea59a38db40f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -887,7 +887,7 @@ bool IRTranslator::emitJumpTableHeader(SwitchCG::JumpTable &JT,
// This value may be smaller or larger than the target's pointer type, and
// therefore require extension or truncating.
auto *PtrIRTy = PointerType::getUnqual(SValue.getContext());
- const LLT PtrScalarTy = LLT::scalar(DL->getTypeSizeInBits(PtrIRTy));
+ const LLT PtrScalarTy = LLT::integer(DL->getTypeSizeInBits(PtrIRTy));
Sub = MIB.buildZExtOrTrunc(PtrScalarTy, Sub);
JT.Reg = Sub.getReg(0);
@@ -1117,14 +1117,14 @@ void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
LLT MaskTy = SwitchOpTy;
if (MaskTy.getSizeInBits() > PtrTy.getSizeInBits() ||
!llvm::has_single_bit<uint32_t>(MaskTy.getSizeInBits()))
- MaskTy = LLT::scalar(PtrTy.getSizeInBits());
+ MaskTy = LLT::integer(PtrTy.getSizeInBits());
else {
// Ensure that the type will fit the mask value.
for (const SwitchCG::BitTestCase &Case : B.Cases) {
if (!isUIntN(SwitchOpTy.getSizeInBits(), Case.Mask)) {
// Switch table case range are encoded into series of masks.
// Just use pointer type, it's guaranteed to fit.
- MaskTy = LLT::scalar(PtrTy.getSizeInBits());
+ MaskTy = LLT::integer(PtrTy.getSizeInBits());
break;
}
}
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index e78dfb0565439..66c2fee776a08 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -73,7 +73,7 @@ getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
LeftoverTy = OrigTy.changeElementCount(
ElementCount::getFixed(LeftoverSize / EltSize));
} else {
- LeftoverTy = LLT::scalar(LeftoverSize);
+ LeftoverTy = LLT::integer(LeftoverSize);
}
int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
@@ -280,7 +280,7 @@ LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy,
// Shift the sign bit of the low register through the high register.
auto ShiftAmt =
- MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1);
+ MIRBuilder.buildConstant(LLT::integer(64), GCDTy.getSizeInBits() - 1);
PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0);
}
}
@@ -1296,7 +1296,7 @@ LegalizerHelper::createResetStateLibcall(MachineInstr &MI,
Type *StatePtrTy = PointerType::get(Ctx, AddrSpace);
unsigned PtrSize = DL.getPointerSizeInBits(AddrSpace);
LLT MemTy = LLT::pointer(AddrSpace, PtrSize);
- auto DefValue = MIRBuilder.buildConstant(LLT::scalar(PtrSize), -1LL);
+ auto DefValue = MIRBuilder.buildConstant(LLT::integer(PtrSize), -1LL);
DstOp Dest(MRI.createGenericVirtualRegister(MemTy));
MIRBuilder.buildIntToPtr(Dest, DefValue);
@@ -4330,7 +4330,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerStore(GStore &StoreMI) {
// Promote to a byte-sized store with upper bits zero if not
// storing an integral number of bytes. For example, promote
// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
- LLT WideTy = LLT::scalar(StoreSizeInBits);
+ LLT WideTy = LLT::integer(StoreSizeInBits);
if (StoreSizeInBits > SrcTy.getSizeInBits()) {
// Avoid creating a store with a narrower source than result.
@@ -4374,10 +4374,10 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerStore(GStore &StoreMI) {
// e.g. an s56 store being broken into s32 + s24, we might have a stored type
// that's wider than the stored size.
unsigned AnyExtSize = PowerOf2Ceil(MemTy.getSizeInBits());
- const LLT NewSrcTy = LLT::scalar(AnyExtSize);
+ const LLT NewSrcTy = LLT::integer(AnyExtSize);
if (SrcTy.isPointer()) {
- const LLT IntPtrTy = LLT::scalar(SrcTy.getSizeInBits());
+ const LLT IntPtrTy = LLT::integer(SrcTy.getSizeInBits());
SrcReg = MIRBuilder.buildPtrToInt(IntPtrTy, SrcReg).getReg(0);
}
@@ -4389,8 +4389,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerStore(GStore &StoreMI) {
// Generate the PtrAdd and truncating stores.
LLT PtrTy = MRI.getType(PtrReg);
- auto OffsetCst = MIRBuilder.buildConstant(
- LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8);
+ auto OffsetCst = MIRBuilder.buildConstant(LLT::integer(PtrTy.getSizeInBits()),
+ LargeSplitSize / 8);
auto SmallPtr = MIRBuilder.buildObjectPtrOffset(PtrTy, PtrReg, OffsetCst);
MachineMemOperand *LargeMMO =
@@ -6190,7 +6190,7 @@ LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
// legalized.
const unsigned NewBitSize = DstEltSize / 2;
const LLT HalfTy = DstTy.getScalarType().changeElementSize(NewBitSize);
- const LLT CondTy = LLT::scalar(1);
+ const LLT CondTy = LLT::integer(1);
if (auto VRegAndVal = getIConstantVRegValWithLookThrough(Amt, MRI)) {
return narrowScalarShiftByConstant(MI, VRegAndVal->Value, HalfTy,
@@ -7101,12 +7101,12 @@ void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
// Add all factors and accumulate all carries into CarrySum.
if (DstIdx != DstParts - 1) {
MachineInstrBuilder Uaddo =
- B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
+ B.buildUAddo(NarrowTy, LLT::integer(1), Factors[0], Factors[1]);
FactorSum = Uaddo.getReg(0);
CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
for (unsigned i = 2; i < Factors.size(); ++i) {
MachineInstrBuilder Uaddo =
- B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
+ B.buildUAddo(NarrowTy, LLT::integer(1), FactorSum, Factors[i]);
FactorSum = Uaddo.getReg(0);
MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
@@ -7196,7 +7196,7 @@ LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx,
if (i == e - 1 && CarryDst)
CarryOut = CarryDst;
else
- CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
+ CarryOut = MRI.createGenericVirtualRegister(LLT::integer(1));
if (!CarryIn) {
MIRBuilder.buildInstr(OpO, {DstReg, CarryOut},
@@ -7548,7 +7548,7 @@ LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx,
auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg);
// ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi)
auto C_0 = B.buildConstant(NarrowTy, 0);
- auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
+ auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::integer(1),
UnmergeSrc.getReg(1), C_0);
auto LoCTLZ = IsUndef ?
B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) :
@@ -9407,7 +9407,7 @@ Register LegalizerHelper::getDynStackAllocTargetPtr(Register SPReg,
Register AllocSize,
Align Alignment,
LLT PtrTy) {
- LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
+ LLT IntPtrTy = LLT::integer(PtrTy.getSizeInBits());
auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp);
@@ -9954,12 +9954,12 @@ LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
if (Size >= 8) {
if (SrcTy.isVector() && (VSize % 8 == 0) &&
(LI.isLegal({TargetOpcode::G_BITREVERSE,
- {LLT::fixed_vector(VSize / 8, 8),
- LLT::fixed_vector(VSize / 8, 8)}}))) {
+ {LLT::fixed_vector(VSize / 8, LLT::integer(8)),
+ LLT::fixed_vector(VSize / 8, LLT::integer(8))}}))) {
// If bitreverse is legal for i8 vector of the same size, then cast
// to i8 vector type.
// e.g. v4s32 -> v16s8
- LLT VTy = LLT::fixed_vector(VSize / 8, 8);
+ LLT VTy = LLT::fixed_vector(VSize / 8, LLT::integer(8));
auto BSWAP = MIRBuilder.buildBSwap(SrcTy, Src);
auto Cast = MIRBuilder.buildBitcast(VTy, BSWAP);
auto RBIT = MIRBuilder.buildBitReverse(VTy, Cast);
@@ -10093,8 +10093,9 @@ LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) {
unsigned BitSize = SrcTy.getScalarSizeInBits();
const fltSemantics &Semantics = getFltSemanticForLLT(SrcTy.getScalarType());
- LLT IntTy = SrcTy.changeElementType(LLT::scalar(BitSize));
- auto AsInt = MIRBuilder.buildCopy(IntTy, SrcReg);
+ LLT IntTy = SrcTy.changeElementType(LLT::integer(BitSize));
+ auto AsInt = SrcTy == IntTy ? MIRBuilder.buildCopy(IntTy, SrcReg)
+ : MIRBuilder.buildBitcast(IntTy, SrcReg);
// Various masks.
APInt SignBit = APInt::getSignMask(BitSize);
@@ -10253,7 +10254,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
bool IsEltPtr = DstTy.isPointerOrPointerVector();
if (IsEltPtr) {
- LLT ScalarPtrTy = LLT::scalar(DstTy.getScalarSizeInBits());
+ LLT ScalarPtrTy = LLT::integer(DstTy.getScalarSizeInBits());
LLT NewTy = DstTy.changeElementType(ScalarPtrTy);
Op1Reg = MIRBuilder.buildPtrToInt(NewTy, Op1Reg).getReg(0);
Op1Ty = MRI.getType(Op1Reg);
@@ -10273,17 +10274,17 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
MaskElt = MIRBuilder.buildSExtInReg(MaskTy, MaskElt, 1).getReg(0);
// Continue the sign extension (or truncate) to match the data type.
+ MaskTy = DstTy.changeElementType(LLT::integer(DstTy.getScalarSizeInBits()));
MaskElt =
- MIRBuilder.buildSExtOrTrunc(DstTy.getScalarType(), MaskElt).getReg(0);
+ MIRBuilder.buildSExtOrTrunc(MaskTy.getScalarType(), MaskElt).getReg(0);
if (DstTy.isVector()) {
// Generate a vector splat idiom.
- auto ShufSplat = MIRBuilder.buildShuffleSplat(DstTy, MaskElt);
+ auto ShufSplat = MIRBuilder.buildShuffleSplat(MaskTy, MaskElt);
MaskReg = ShufSplat.getReg(0);
} else {
MaskReg = MaskElt;
}
- MaskTy = DstTy;
} else if (!DstTy.isVector()) {
// Cannot handle the case that mask is a vector and dst is a scalar.
return UnableToLegalize;
@@ -10293,12 +10294,12 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
return UnableToLegalize;
}
- if (!(Op1Ty.getScalarType().isAnyScalar() ||
- Op1Ty.getScalarType().isInteger()))
+ if (!Op1Ty.getScalarType().isAnyScalar() &&
+ !Op1Ty.getScalarType().isInteger())
Op1Reg = MIRBuilder.buildBitcast(Op1TyInt, Op1Reg).getReg(0);
- if (!(Op2Ty.getScalarType().isAnyScalar() ||
- Op2Ty.getScalarType().isInteger())) {
+ if (!Op2Ty.getScalarType().isAnyScalar() &&
+ !Op2Ty.getScalarType().isInteger()) {
auto Op2TyInt =
Op2Ty.changeElementType(LLT::integer(Op2Ty.getScalarSizeInBits()));
Op2Reg = MIRBuilder.buildBitcast(Op2TyInt, Op2Reg).getReg(0);
@@ -10558,11 +10559,11 @@ static bool findGISelOptimalMemOpLowering(std::vector<LLT> &MemOps,
// Use the largest scalar type whose alignment constraints are satisfied.
// We only need to check DstAlign here as SrcAlign is always greater or
// equal to DstAlign (or zero).
- Ty = LLT::scalar(64);
+ Ty = LLT::integer(64);
if (Op.isFixedDstAlign())
while (Op.getDstAlign() < Ty.getSizeInBytes() &&
!TLI.allowsMisalignedMemoryAccesses(Ty, DstAS, Op.getDstAlign()))
- Ty = LLT::scalar(Ty.getSizeInBytes());
+ Ty = LLT::integer(Ty.getSizeInBytes());
assert(Ty.getSizeInBits() > 0 && "Could not find valid type");
// FIXME: check for the largest legal type we can load/store to.
}
@@ -10577,8 +10578,9 @@ static bool findGISelOptimalMemOpLowering(std::vector<LLT> &MemOps,
// FIXME: check for mem op safety and legality of the types. Not all of
// SDAGisms map cleanly to GISel concepts.
if (NewTy.isVector())
- NewTy = NewTy.getSizeInBits() > 64 ? LLT::scalar(64) : LLT::scalar(32);
- NewTy = LLT::scalar(llvm::bit_floor(NewTy.getSizeInBits() - 1));
+ NewTy =
+ NewTy.getSizeInBits() > 64 ? LLT::integer(64) : LLT::integer(32);
+ NewTy = LLT::integer(llvm::bit_floor(NewTy.getSizeInBits() - 1));
unsigned NewTySize = NewTy.getSizeInBytes();
assert(NewTySize > 0 && "Could not find appropriate type");
@@ -10881,8 +10883,9 @@ LegalizerHelper::lowerMemcpy(MachineInstr &MI, Register Dst, Register Src,
Register Offset;
if (CurrOffset != 0) {
LLT SrcTy = MRI.getType(Src);
- Offset = MIB.buildConstant(LLT::scalar(SrcTy.getSizeInBits()), CurrOffset)
- .getReg(0);
+ Offset =
+ MIB.buildConstant(LLT::integer(SrcTy.getSizeInBits()), CurrOffset)
+ .getReg(0);
LoadPtr = MIB.buildObjectPtrOffset(SrcTy, Src, Offset).getReg(0);
}
auto LdVal = MIB.buildLoad(CopyTy, LoadPtr, *LoadMMO);
diff --git a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
index 1dbba820b3dea..365a927a4612f 100644
--- a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
@@ -310,10 +310,10 @@ bool LoadStoreOpt::mergeStores(SmallVectorImpl<GStore *> &StoresToMerge) {
initializeStoreMergeTargetInfo(AS);
const auto &LegalSizes = LegalStoreSizes[AS];
-#ifndef NDEBUG
+ // FIXME: Support mismatching types (i16 + f16).
for (auto *StoreMI : StoresToMerge)
- assert(MRI->getType(StoreMI->getValueReg()) == OrigTy);
-#endif
+ if (MRI->getType(StoreMI->getValueReg()) != OrigTy)
+ return false;
bool AnyMerged = false;
do {
@@ -819,7 +819,8 @@ bool LoadStoreOpt::mergeTruncStore(GStore &StoreMI,
// We didn't find enough stores to merge into the size of the original
// source value, but we may be able to generate a smaller store if we
// truncate the source value.
- WideStoreTy = LLT::scalar(FoundStores.size() * MemTy.getScalarSizeInBits());
+ WideStoreTy =
+ LLT::integer(FoundStores.size() * MemTy.getScalarSizeInBits());
}
unsigned NumStoresFound = FoundStores.size();
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index ee0aaf9a49994..72b99d06c21bc 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -589,7 +589,7 @@ bool llvm::extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy,
return true;
}
- LeftoverTy = LLT::scalar(LeftoverSize);
+ LeftoverTy = LLT::integer(LeftoverSize);
// For irregular sizes, extract the individual parts.
for (unsigned I = 0; I != NumParts; ++I) {
Register NewReg = MRI.createGenericVirtualRegister(MainTy);
@@ -1266,7 +1266,7 @@ LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
LLT TargetScalar = TargetTy.getScalarType();
unsigned GCD = std::gcd(OrigScalar.getSizeInBits().getFixedValue(),
TargetScalar.getSizeInBits().getFixedValue());
- return LLT::scalar(GCD);
+ return LLT::integer(GCD);
}
std::optional<int> llvm::getSplatIndex(MachineInstr &MI) {
diff --git a/llvm/lib/CodeGen/RegisterBankInfo.cpp b/llvm/lib/CodeGen/RegisterBankInfo.cpp
index 79b3c73ea34f1..1049aa979ce81 100644
--- a/llvm/lib/CodeGen/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterBankInfo.cpp
@@ -721,7 +721,7 @@ void RegisterBankInfo::OperandsMapper::createVRegs(unsigned OpIdx) {
// of the instruction.
// The rationale is that this generic code cannot guess how the
// target plans to split the input type.
- NewVReg = MRI.createGenericVirtualRegister(LLT::scalar(PartMap->Length));
+ NewVReg = MRI.createGenericVirtualRegister(LLT::integer(PartMap->Length));
MRI.setRegBank(NewVReg, *PartMap->RegBank);
++PartMap;
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 7c02a7437ba68..ec95448f61043 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -93,21 +93,25 @@ def G_DUPLANE8 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src, type1:$lane);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
def G_DUPLANE16 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src, type1:$lane);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
def G_DUPLANE32 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src, type1:$lane);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
def G_DUPLANE64 : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src, type1:$lane);
let hasSideEffects = 0;
+ let GISelMatchGenericTypes = 1;
}
// Represents a trn1 instruction. Produced post-legalization from
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 128baae4e6cda..6cbfc1f2fbb98 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -754,8 +754,7 @@ bool AArch64CallLowering::lowerFormalArguments(
if (!Flags.isZExt() && !Flags.isSExt()) {
// Lower i1 argument as i8, and insert AssertZExt + Trunc later.
Register OrigReg = OrigArg.Regs[0];
- Register WideReg =
- MRI.createGenericVirtualRegister(LLT::integer(8));
+ Register WideReg = MRI.createGenericVirtualRegister(LLT::integer(8));
OrigArg.Regs[0] = WideReg;
BoolArgs.push_back({OrigReg, WideReg});
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index dbaa056bb7b58..4e099c4e827f3 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2140,7 +2140,7 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
if (PtrSize != 32 && PtrSize != 64)
return false;
// Convert pointer typed constants to integers so TableGen can select.
- MRI.setType(DefReg, LLT::scalar(PtrSize));
+ MRI.setType(DefReg, LLT::integer(PtrSize));
return true;
}
case TargetOpcode::G_STORE: {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 7b2563fceed1a..fe49bc25a4d97 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -66,7 +66,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
const LLT nxv2s64 = LLT::scalable_vector(2, s64);
const LLT bf16 = LLT::bfloat16();
- const LLT v4bf16 = LLT::fixed_vector(4, bf16);
const LLT f16 = LLT::float16();
const LLT v4f16 = LLT::fixed_vector(4, f16);
@@ -121,8 +120,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
const bool HasFP16 = ST.hasFullFP16();
const LLT &MinFPScalar = HasFP16 ? f16 : f32;
- const bool HasBF16 = ST.hasBF16();
-
const bool HasCSSC = ST.hasCSSC();
const bool HasRCPC3 = ST.hasRCPC3();
const bool HasSVE = ST.hasSVE();
@@ -306,7 +303,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// FIXME: Legal vector types are only legal with NEON.
getActionDefinitionsBuilder(G_ABS)
.legalFor(HasCSSC, {s32, s64})
- .legalFor(PackedVectorAllTypeList)
+ .legalFor({v16i8, v8i16, v4i32, v2i64, v2p0, v8i8, v4i16, v2i32})
.customIf([=](const LegalityQuery &Q) {
// TODO: Fix suboptimal codegen for 128+ bit types.
LLT SrcTy = Q.Types[0];
@@ -314,10 +311,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
})
.widenScalarIf(
[=](const LegalityQuery &Query) { return Query.Types[0] == v4s8; },
- [=](const LegalityQuery &Query) { return std::make_pair(0, v4s16); })
+ [=](const LegalityQuery &Query) { return std::make_pair(0, v4i16); })
.widenScalarIf(
[=](const LegalityQuery &Query) { return Query.Types[0] == v2s16; },
- [=](const LegalityQuery &Query) { return std::make_pair(0, v2s32); })
+ [=](const LegalityQuery &Query) { return std::make_pair(0, v2i32); })
.clampNumElements(0, v8s8, v16s8)
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
@@ -444,7 +441,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR, G_FRINT, G_FNEARBYINT,
G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN})
.legalFor({f32, f64, v2f32, v4f32, v2f64})
- .convertBF16()
.legalFor(HasFP16, {f16, v4f16, v8f16})
.libcallFor({f128})
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
@@ -457,7 +453,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder({G_FABS, G_FNEG})
.legalFor({f32, f64, v2f32, v4f32, v2f64})
.legalFor(HasFP16, {f16, v4f16, v8f16})
- .convertBF16()
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.lowerIf(scalarOrEltWiderThan(0, 64))
.clampNumElements(0, v4s16, v8s16)
@@ -468,7 +463,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_FREM)
.libcallFor({f32, f64, f128})
- .convertBF16()
.minScalar(0, f32)
.scalarize(0);
@@ -478,13 +472,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
G_FSINH, G_FTANH, G_FMODF})
// We need a call for these, so we always need to scalarize.
.scalarize(0)
- .convertBF16()
// Regardless of FP16 support, widen 16-bit elements to 32-bits.
.minScalar(0, f32)
.libcallFor({f32, f64, f128});
getActionDefinitionsBuilder({G_FPOWI, G_FLDEXP})
.scalarize(0)
- .convertBF16()
.minScalar(0, f32)
.libcallFor({{f32, i32}, {f64, i32}, {f128, i32}});
@@ -597,7 +589,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.bitcastIf(typeInSet(0, {v4s8}),
[=](const LegalityQuery &Query) {
const LLT VecTy = Query.Types[0];
- return std::pair(0, LLT::scalar(VecTy.getSizeInBits()));
+ return std::pair(0, LLT::integer(VecTy.getSizeInBits()));
})
.customIf(IsPtrVecPred)
.scalarizeIf(typeInSet(0, {v2s16, v2s8}), 0)
@@ -658,7 +650,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
})),
[=](const LegalityQuery &Query) {
const LLT VecTy = Query.Types[0];
- return std::pair(0, LLT::scalar(VecTy.getSizeInBits()));
+ return std::pair(0, LLT::integer(VecTy.getSizeInBits()));
})
.customIf(IsPtrVecPred)
.scalarizeIf(typeInSet(0, {v2s16, v2s8}), 0)
@@ -726,7 +718,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// Constants
getActionDefinitionsBuilder(G_CONSTANT)
- .legalFor({p0, i8, i16, i32, i64})
+ .legalFor({p0, s8, s16, s32, s64})
.widenScalarToNextPow2(0)
.clampScalar(0, s8, s64);
getActionDefinitionsBuilder(G_FCONSTANT)
@@ -773,7 +765,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{v2s64, v2f64}})
.legalFor(HasFP16, {{s32, f16}, {v4s16, v4f16}, {v8s16, v8f16}})
.widenScalarOrEltToNextPow2(1)
- .convertBF16(1, f32)
.clampScalar(0, s32, s32)
.minScalarOrElt(1, MinFPScalar)
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
@@ -870,7 +861,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_FPTRUNC)
.legalFor(
{{f16, f32}, {f16, f64}, {f32, f64}, {v4f16, v4f32}, {v2f32, v2f64}})
- .legalFor(HasBF16, {{bf16, f32}, {bf16, f64}, {v4bf16, v4f32}})
.libcallFor({{f16, f128}, {f32, f128}, {f64, f128}})
.moreElementsToNextPow2(1)
.customIf([](const LegalityQuery &Q) {
@@ -888,14 +878,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_FPEXT)
.legalFor(
{{f32, f16}, {f64, f16}, {f64, f32}, {v4f32, v4f16}, {v2f64, v2f32}})
- .legalFor(HasBF16, {{f32, bf16}, {v4f32, v4bf16}})
.libcallFor({{f128, f64}, {f128, f32}, {f128, f16}})
.moreElementsToNextPow2(0)
.widenScalarIf(
[](const LegalityQuery &Q) {
LLT DstTy = Q.Types[0];
LLT SrcTy = Q.Types[1];
- return SrcTy.getScalarSizeInBits() == 16 &&
+ return SrcTy.isVector() && DstTy.isVector() &&
+ SrcTy.getScalarSizeInBits() == 16 &&
DstTy.getScalarSizeInBits() == 64;
},
changeElementTo(1, f32))
@@ -1000,7 +990,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{v2f32, v2i32},
{v4f32, v4i32},
{v2f64, v2i64}})
- .convertBF16()
.legalFor(HasFP16,
{{f16, i32}, {f16, i64}, {v4f16, v4i16}, {v8f16, v8i16}})
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
@@ -1013,6 +1002,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
Query.Types[1].getScalarSizeInBits() == 64 &&
Query.Types[0].getScalarSizeInBits() == 16;
})
+ .widenScalarIf(
+ [=](const LegalityQuery &Query) {
+ return Query.Types[0].getScalarType() == bf16;
+ },
+ changeElementTo(0, f32))
.widenScalarOrEltToNextPow2OrMinSize(0, /*MinSize=*/HasFP16 ? 16 : 32)
.scalarizeIf(
// v2i64->v2f32 needs to scalarize to avoid double-rounding issues.
@@ -1300,7 +1294,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.bitcastIf(isPointerVector(0), [=](const LegalityQuery &Query) {
// Bitcast pointers vector to i64.
const LLT DstTy = Query.Types[0];
- return std::pair(0, LLT::vector(DstTy.getElementCount(), 64));
+ return std::pair(
+ 0, LLT::vector(DstTy.getElementCount(), LLT::integer(64)));
});
getActionDefinitionsBuilder(G_CONCAT_VECTORS)
@@ -1604,7 +1599,7 @@ bool AArch64LegalizerInfo::legalizeFunnelShift(MachineInstr &MI,
return true;
// Cast the ShiftNumber to a 64-bit type
- auto Cast64 = MIRBuilder.buildConstant(LLT::scalar(64), Amount.zext(64));
+ auto Cast64 = MIRBuilder.buildConstant(LLT::integer(64), Amount.zext(64));
if (MI.getOpcode() == TargetOpcode::G_FSHR) {
Observer.changingInstr(MI);
@@ -1662,7 +1657,7 @@ bool AArch64LegalizerInfo::legalizeRotate(MachineInstr &MI,
(void)AmtTy;
assert(AmtTy.isScalar() && "Expected a scalar rotate");
assert(AmtTy.getSizeInBits() < 64 && "Expected this rotate to be legal");
- auto NewAmt = Helper.MIRBuilder.buildZExt(LLT::scalar(64), AmtReg);
+ auto NewAmt = Helper.MIRBuilder.buildZExt(LLT::integer(64), AmtReg);
Helper.Observer.changingInstr(MI);
MI.getOperand(2).setReg(NewAmt.getReg(0));
Helper.Observer.changedInstr(MI);
@@ -1784,7 +1779,7 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
// Anyext the value being set to 64 bit (only the bottom 8 bits are read by
// the instruction).
auto &Value = MI.getOperand(3);
- Register ExtValueReg = MIB.buildAnyExt(LLT::scalar(64), Value).getReg(0);
+ Register ExtValueReg = MIB.buildAnyExt(LLT::integer(64), Value).getReg(0);
Value.setReg(ExtValueReg);
return true;
}
@@ -2151,7 +2146,7 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
bool IsRcpC3 =
ST->hasLSE2() && ST->hasRCPC3() && (IsLoadAcquire || IsStoreRelease);
- LLT s64 = LLT::scalar(64);
+ LLT s64 = LLT::integer(64);
unsigned Opcode;
if (IsRcpC3) {
@@ -2202,7 +2197,7 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
}
unsigned PtrSize = ValTy.getElementType().getSizeInBits();
- const LLT NewTy = LLT::vector(ValTy.getElementCount(), PtrSize);
+ const LLT NewTy = LLT::vector(ValTy.getElementCount(), LLT::integer(PtrSize));
auto &MMO = **MI.memoperands_begin();
MMO.setType(NewTy);
@@ -2530,7 +2525,7 @@ bool AArch64LegalizerInfo::legalizeMemOps(MachineInstr &MI,
// the instruction).
auto &Value = MI.getOperand(1);
Register ExtValueReg =
- MIRBuilder.buildAnyExt(LLT::scalar(64), Value).getReg(0);
+ MIRBuilder.buildAnyExt(LLT::integer(64), Value).getReg(0);
Value.setReg(ExtValueReg);
return true;
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index ba0d9b542d1e9..3a0c0e7494f41 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -113,7 +113,7 @@ void applyExtractVecEltPairwiseAdd(
// We want to generate two extracts of elements 0 and 1, and add them.
LLT Ty = std::get<1>(MatchInfo);
Register Src = std::get<2>(MatchInfo);
- LLT s64 = LLT::scalar(64);
+ LLT s64 = LLT::integer(64);
B.setInstrAndDebugLoc(MI);
auto Elt0 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 0));
auto Elt1 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 1));
@@ -329,11 +329,11 @@ void applySplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI,
GStore &Store = cast<GStore>(MI);
assert(MRI.getType(Store.getValueReg()).isVector() &&
"Expected a vector store value");
- LLT NewTy = LLT::scalar(64);
+ LLT NewTy = LLT::integer(64);
Register PtrReg = Store.getPointerReg();
auto Zero = B.buildConstant(NewTy, 0);
- auto HighPtr = B.buildPtrAdd(MRI.getType(PtrReg), PtrReg,
- B.buildConstant(LLT::scalar(64), 8));
+ auto HighPtr =
+ B.buildPtrAdd(MRI.getType(PtrReg), PtrReg, B.buildConstant(NewTy, 8));
auto &MF = *MI.getMF();
auto *LowMMO = MF.getMachineMemOperand(&Store.getMMO(), 0, NewTy);
auto *HighMMO = MF.getMachineMemOperand(&Store.getMMO(), 8, NewTy);
@@ -751,7 +751,8 @@ bool AArch64PostLegalizerCombiner::tryOptimizeConsecStores(
for (auto &SInfo : Stores) {
// Compute a new pointer with the new base ptr and adjusted offset.
MIB.setInstrAndDebugLoc(*SInfo.St);
- auto NewOff = MIB.buildConstant(LLT::scalar(64), SInfo.Offset - BaseOffset);
+ auto NewOff =
+ MIB.buildConstant(LLT::integer(64), SInfo.Offset - BaseOffset);
auto NewPtr = MIB.buildPtrAdd(MRI.getType(SInfo.St->getPointerReg()),
NewBase, NewOff);
if (MIB.getObserver())
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 7f234192fdf74..28450f036cd37 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -97,8 +97,6 @@ void applyFConstantToConstant(MachineInstr &MI) {
MachineIRBuilder MIB(MI);
const APFloat &ImmValAPF = MI.getOperand(1).getFPImm()->getValueAPF();
const Register DstReg = MI.getOperand(0).getReg();
- const LLT DstTy = MIB.getMRI()->getType(DstReg);
- MIB.getMRI()->setType(DstReg, LLT::scalar(DstTy.getSizeInBits()));
MIB.buildConstant(DstReg, ImmValAPF.bitcastToAPInt());
MI.eraseFromParent();
}
@@ -418,8 +416,9 @@ void applyShuffleVectorPseudo(MachineInstr &MI, MachineRegisterInfo &MRI,
LLT DstTy = MRI.getType(MatchInfo.Dst);
assert(DstTy == LLT::fixed_vector(8, 8) ||
DstTy == LLT::fixed_vector(16, 8));
- LLT BSTy = DstTy == LLT::fixed_vector(8, 8) ? LLT::fixed_vector(4, 16)
- : LLT::fixed_vector(8, 16);
+ LLT BSTy = DstTy == LLT::fixed_vector(8, 8)
+ ? LLT::fixed_vector(4, LLT::integer(16))
+ : LLT::fixed_vector(8, LLT::integer(16));
// FIXME: NVCAST
auto BS1 = MIRBuilder.buildInstr(TargetOpcode::G_BITCAST, {BSTy},
MatchInfo.SrcOps[0]);
@@ -439,8 +438,8 @@ void applyEXT(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
MIRBuilder.buildCopy(MatchInfo.Dst, MatchInfo.SrcOps[0]);
else {
// Tablegen patterns expect an i32 G_CONSTANT as the final op.
- auto Cst =
- MIRBuilder.buildConstant(LLT::scalar(32), MatchInfo.SrcOps[2].getImm());
+ auto Cst = MIRBuilder.buildConstant(LLT::integer(32),
+ MatchInfo.SrcOps[2].getImm());
MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst},
{MatchInfo.SrcOps[0], MatchInfo.SrcOps[1], Cst});
}
@@ -454,7 +453,7 @@ void applyFullRev(MachineInstr &MI, MachineRegisterInfo &MRI) {
assert(DstTy.getSizeInBits() == 128 &&
"Expected 128bit vector in applyFullRev");
MachineIRBuilder MIRBuilder(MI);
- auto Cst = MIRBuilder.buildConstant(LLT::scalar(32), 8);
+ auto Cst = MIRBuilder.buildConstant(LLT::integer(32), 8);
auto Rev = MIRBuilder.buildInstr(AArch64::G_REV64, {DstTy}, {Src});
MIRBuilder.buildInstr(AArch64::G_EXT, {Dst}, {Rev, Rev, Cst});
MI.eraseFromParent();
@@ -807,7 +806,7 @@ void applyDupLane(MachineInstr &MI, MachineRegisterInfo &MRI,
const LLT SrcTy = MRI.getType(Src1Reg);
B.setInstrAndDebugLoc(MI);
- auto Lane = B.buildConstant(LLT::scalar(64), MatchInfo.second);
+ auto Lane = B.buildConstant(LLT::integer(64), MatchInfo.second);
Register DupSrc = MI.getOperand(1).getReg();
// For types like <2 x s32>, we can use G_DUPLANE32, with a <4 x s32> source.
@@ -975,10 +974,9 @@ std::function<Register(MachineIRBuilder &)>
getVectorFCMP(AArch64CC::CondCode CC, Register LHS, Register RHS, bool NoNans,
MachineRegisterInfo &MRI) {
LLT OldTy = MRI.getType(LHS);
- LLT DstTy =
- LLT::fixed_vector(OldTy.getNumElements(), OldTy.getScalarSizeInBits());
+ LLT DstTy = LLT::fixed_vector(OldTy.getNumElements(),
+ LLT::integer(OldTy.getScalarSizeInBits()));
assert(DstTy.isVector() && "Expected vector types only?");
- assert(DstTy == MRI.getType(RHS) && "Src and Dst types must match!");
switch (CC) {
default:
llvm_unreachable("Unexpected condition code!");
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index bfd6738bee688..818f8c0c5f277 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -324,10 +324,10 @@ void applyExtAddvToDotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
unsigned NumOfDotMI;
if (SrcTy.getNumElements() % 16 == 0) {
NumOfDotMI = SrcTy.getNumElements() / 16;
- MidTy = LLT::fixed_vector(4, 32);
+ MidTy = LLT::fixed_vector(4, LLT::integer(32));
} else if (SrcTy.getNumElements() % 8 == 0) {
NumOfDotMI = SrcTy.getNumElements() / 8;
- MidTy = LLT::fixed_vector(2, 32);
+ MidTy = LLT::fixed_vector(2, LLT::integer(32));
} else {
llvm_unreachable("Source type number of elements is not multiple of 8");
}
@@ -347,7 +347,7 @@ void applyExtAddvToDotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
SmallVector<Register> Leftover2;
// Split the elements into v16i8 and v8i8
- LLT MainTy = LLT::fixed_vector(16, 8);
+ LLT MainTy = LLT::fixed_vector(16, LLT::integer(8));
LLT LeftoverTy1, LeftoverTy2;
if ((!extractParts(Ext1SrcReg, MRI.getType(Ext1SrcReg), MainTy,
LeftoverTy1, Ext1UnmergeReg, Leftover1, Builder,
@@ -365,22 +365,22 @@ void applyExtAddvToDotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
Ext1UnmergeReg.push_back(
Builder
- .buildMergeLikeInstr(LLT::fixed_vector(16, 8),
+ .buildMergeLikeInstr(LLT::fixed_vector(16, LLT::integer(8)),
{Leftover1[0], v8Zeroes})
.getReg(0));
Ext2UnmergeReg.push_back(
Builder
- .buildMergeLikeInstr(LLT::fixed_vector(16, 8),
+ .buildMergeLikeInstr(LLT::fixed_vector(16, LLT::integer(8)),
{Leftover2[0], v8Zeroes})
.getReg(0));
} else {
// Unmerge the source vectors to v16i8
unsigned SrcNumElts = SrcTy.getNumElements();
- extractParts(Ext1SrcReg, LLT::fixed_vector(16, 8), SrcNumElts / 16,
- Ext1UnmergeReg, Builder, MRI);
- extractParts(Ext2SrcReg, LLT::fixed_vector(16, 8), SrcNumElts / 16,
- Ext2UnmergeReg, Builder, MRI);
+ extractParts(Ext1SrcReg, LLT::fixed_vector(16, LLT::integer(8)),
+ SrcNumElts / 16, Ext1UnmergeReg, Builder, MRI);
+ extractParts(Ext2SrcReg, LLT::fixed_vector(16, LLT::integer(8)),
+ SrcNumElts / 16, Ext2UnmergeReg, Builder, MRI);
}
// Build the UDOT instructions
@@ -390,10 +390,10 @@ void applyExtAddvToDotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
LLT ZeroesLLT;
// Check if it is 16 or 8 elements. Set Zeroes to the according size
if (MRI.getType(Ext1UnmergeReg[i]).getNumElements() == 16) {
- ZeroesLLT = LLT::fixed_vector(4, 32);
+ ZeroesLLT = LLT::fixed_vector(4, LLT::integer(32));
NumElements += 4;
} else {
- ZeroesLLT = LLT::fixed_vector(2, 32);
+ ZeroesLLT = LLT::fixed_vector(2, LLT::integer(32));
NumElements += 2;
}
auto Zeroes = Builder.buildConstant(ZeroesLLT, 0)->getOperand(0).getReg();
@@ -405,8 +405,8 @@ void applyExtAddvToDotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
}
// Merge the output
- auto ConcatMI =
- Builder.buildConcatVectors(LLT::fixed_vector(NumElements, 32), DotReg);
+ auto ConcatMI = Builder.buildConcatVectors(
+ LLT::fixed_vector(NumElements, LLT::integer(32)), DotReg);
// Put it through a vector reduction
Builder.buildVecReduceAdd(MI.getOperand(0).getReg(),
@@ -478,14 +478,11 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
LLT LeftoverTy;
SmallVector<Register, 4> LeftoverRegs;
if (SrcScalSize == 8)
- MainTy =
- LLT::fixed_vector(16, LLT::integer(8));
+ MainTy = LLT::fixed_vector(16, LLT::integer(8));
else if (SrcScalSize == 16)
- MainTy =
- LLT::fixed_vector(8, LLT::integer(16));
+ MainTy = LLT::fixed_vector(8, LLT::integer(16));
else if (SrcScalSize == 32)
- MainTy =
- LLT::fixed_vector(4, LLT::integer(32));
+ MainTy = LLT::fixed_vector(4, LLT::integer(32));
else
llvm_unreachable("Source's Scalar Size not supported");
@@ -511,7 +508,8 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
WorkingRegisters[I] =
B.buildInstr(std::get<1>(MatchInfo) ? TargetOpcode::G_SEXT
: TargetOpcode::G_ZEXT,
- {LLT::fixed_vector(4, 16)}, {WorkingRegisters[I]})
+ {LLT::fixed_vector(4, LLT::integer(16))},
+ {WorkingRegisters[I]})
.getReg(0);
}
@@ -533,8 +531,8 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
.getReg(0);
} else {
Register ExtractReg =
- B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT,
- {LLT::integer(32)}, {AddlvReg, ZeroReg})
+ B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {LLT::integer(32)},
+ {AddlvReg, ZeroReg})
.getReg(0);
WorkingRegisters[I] =
B.buildTrunc({MidScalarLLT}, {ExtractReg}).getReg(0);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 5c2e7b7ce5988..5365d4f3ffd16 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -446,7 +446,7 @@ void AArch64RegisterBankInfo::applyMappingImpl(
DstTy.getSizeInBits() < 32 &&
"Expected a scalar smaller than 32 bits on a GPR.");
Builder.setInsertPt(*MI.getParent(), std::next(MI.getIterator()));
- Register ExtReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
+ Register ExtReg = MRI.createGenericVirtualRegister(LLT::integer(32));
Builder.buildTrunc(Dst, ExtReg);
APInt Val = MI.getOperand(1).getCImm()->getValue().zext(32);
@@ -465,7 +465,7 @@ void AArch64RegisterBankInfo::applyMappingImpl(
APInt Bits = Imm.bitcastToAPInt();
Builder.setInsertPt(*MI.getParent(), MI.getIterator());
if (Bits.getBitWidth() < 32) {
- Register ExtReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
+ Register ExtReg = MRI.createGenericVirtualRegister(LLT::integer(32));
Builder.buildConstant(ExtReg, Bits.zext(32));
Builder.buildTrunc(Dst, ExtReg);
MRI.setRegBank(ExtReg, AArch64::GPRRegBank);
@@ -486,7 +486,7 @@ void AArch64RegisterBankInfo::applyMappingImpl(
return applyDefaultMapping(OpdMapper);
Builder.setInsertPt(*MI.getParent(), MI.getIterator());
- auto Ext = Builder.buildAnyExt(LLT::scalar(32), Dst);
+ auto Ext = Builder.buildAnyExt(LLT::integer(32), Dst);
MI.getOperand(0).setReg(Ext.getReg(0));
MRI.setRegBank(Ext.getReg(0), AArch64::GPRRegBank);
}
@@ -498,7 +498,7 @@ void AArch64RegisterBankInfo::applyMappingImpl(
if (MRI.getRegBank(Dst) == &AArch64::GPRRegBank && Ty.isScalar() &&
Ty.getSizeInBits() < 32) {
Builder.setInsertPt(*MI.getParent(), std::next(MI.getIterator()));
- Register ExtReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
+ Register ExtReg = MRI.createGenericVirtualRegister(LLT::integer(32));
Builder.buildTrunc(Dst, ExtReg);
MI.getOperand(0).setReg(ExtReg);
MRI.setRegBank(ExtReg, AArch64::GPRRegBank);
@@ -535,7 +535,7 @@ void AArch64RegisterBankInfo::applyMappingImpl(
Builder.setInsertPt(*MI.getParent(), MI.getIterator());
Register ConstReg =
- Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(1).getReg())
+ Builder.buildAnyExt(LLT::integer(32), MI.getOperand(1).getReg())
.getReg(0);
MRI.setRegBank(ConstReg, getRegBank(AArch64::GPRRegBankID));
MI.getOperand(1).setReg(ConstReg);
@@ -947,12 +947,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
TypeSize Size = DstTy.getSizeInBits();
- bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64 &&
- DstTy.getScalarType().isInteger() &&
- !(SrcTy.getSizeInBits() <= 16);
- bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64 &&
- SrcTy.getScalarType().isInteger() &&
- !(SrcTy.getSizeInBits() <= 16);
+ bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64;
+ bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64;
const RegisterBank &DstRB =
DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
const RegisterBank &SrcRB =
@@ -1253,17 +1249,14 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
break;
}
- case TargetOpcode::G_UNMERGE_VALUES:
+ case TargetOpcode::G_UNMERGE_VALUES: {
// If the first operand belongs to a FPR register bank, then make sure that
// we preserve that.
if (OpRegBankIdx[0] != PMI_FirstGPR)
break;
- [[fallthrough]];
- case TargetOpcode::G_MERGE_VALUES: {
LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
// UNMERGE into scalars from a vector should always use FPR.
- // MERGE into a vector should use FPR if the operands are already on FPR.
// Likewise if any of the uses are FP instructions.
if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll
index eedae44e68798..8c958459d93e8 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-rcpc_immo.ll
@@ -421,7 +421,7 @@ define void @store_atomic_i128_from_gep() {
; GISEL-LABEL: store_atomic_i128_from_gep:
; GISEL: bl init
; GISEL: dmb ish
-; GISEL: stp x8, x9, [x10, #16]
+; GISEL: stp x8, x8, [x9, #16]
;
; SDAG-LABEL: store_atomic_i128_from_gep:
; SDAG: bl init
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
index b18271dfd412c..e0f2dd728c5e6 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
@@ -379,10 +379,10 @@ define dso_local double @atomicrmw_fadd_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_monotonic:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -393,10 +393,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acquire:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -407,10 +407,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_release:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -421,10 +421,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -435,10 +435,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -539,9 +539,9 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_monotonic:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_monotonic:
@@ -553,9 +553,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acquire:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acquire:
@@ -567,9 +567,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_release:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_release:
@@ -581,9 +581,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
@@ -595,9 +595,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
@@ -609,9 +609,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_monotonic:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_monotonic:
@@ -623,9 +623,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acquire:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acquire:
@@ -637,9 +637,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_release:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_release:
@@ -651,9 +651,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
@@ -665,9 +665,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
index e56442e690645..4a1b7642eff4c 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
@@ -5,10 +5,10 @@
define dso_local half @atomicrmw_fadd_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_monotonic:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -19,10 +19,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fadd_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_acquire:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -33,10 +33,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fadd_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_release:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -47,10 +47,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fadd_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_acq_rel:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -61,10 +61,10 @@ define dso_local half @atomicrmw_fadd_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fadd_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fadd_half_aligned_seq_cst:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fadd_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -165,9 +165,9 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fadd_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_monotonic:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_monotonic:
@@ -179,9 +179,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fadd_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_acquire:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_acquire:
@@ -193,9 +193,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fadd_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_release:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_release:
@@ -207,9 +207,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fadd_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_acq_rel:
@@ -221,9 +221,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fadd_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fadd_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_seq_cst:
@@ -235,9 +235,9 @@ define dso_local float @atomicrmw_fadd_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fadd_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_monotonic:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_monotonic:
@@ -249,9 +249,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fadd_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_acquire:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_acquire:
@@ -263,9 +263,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fadd_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_release:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_release:
@@ -277,9 +277,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fadd_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_acq_rel:
@@ -291,9 +291,9 @@ define dso_local double @atomicrmw_fadd_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fadd_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fadd_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_seq_cst:
@@ -480,10 +480,10 @@ define dso_local double @atomicrmw_fadd_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_monotonic:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -494,10 +494,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acquire:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -508,10 +508,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_release:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -522,10 +522,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -536,10 +536,10 @@ define dso_local half @atomicrmw_fsub_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fsub_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fsub_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -640,9 +640,9 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_monotonic:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_monotonic:
@@ -654,9 +654,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acquire:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acquire:
@@ -668,9 +668,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_release:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_release:
@@ -682,9 +682,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
@@ -696,9 +696,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
@@ -710,9 +710,9 @@ define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_monotonic:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_monotonic:
@@ -724,9 +724,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acquire:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acquire:
@@ -738,9 +738,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_release:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_release:
@@ -752,9 +752,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
@@ -766,9 +766,9 @@ define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fsub_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
@@ -955,10 +955,10 @@ define dso_local double @atomicrmw_fsub_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fmax_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_monotonic:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -969,10 +969,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fmax_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_acquire:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -983,10 +983,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fmax_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_release:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -997,10 +997,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fmax_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_acq_rel:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1011,10 +1011,10 @@ define dso_local half @atomicrmw_fmax_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fmax_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmax_half_aligned_seq_cst:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmax_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -1115,9 +1115,9 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fmax_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_monotonic:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_monotonic:
@@ -1129,9 +1129,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fmax_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_acquire:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_acquire:
@@ -1143,9 +1143,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fmax_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_release:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_release:
@@ -1157,9 +1157,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fmax_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_acq_rel:
@@ -1171,9 +1171,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fmax_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmax_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_seq_cst:
@@ -1185,9 +1185,9 @@ define dso_local float @atomicrmw_fmax_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fmax_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_monotonic:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_monotonic:
@@ -1199,9 +1199,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fmax_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_acquire:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_acquire:
@@ -1213,9 +1213,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fmax_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_release:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_release:
@@ -1227,9 +1227,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fmax_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_acq_rel:
@@ -1241,9 +1241,9 @@ define dso_local double @atomicrmw_fmax_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fmax_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmax_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_seq_cst:
@@ -1430,10 +1430,10 @@ define dso_local double @atomicrmw_fmax_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fmin_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_monotonic:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -1444,10 +1444,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_monotonic(ptr %ptr, half %val
define dso_local half @atomicrmw_fmin_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_acquire:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -1458,10 +1458,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_acquire(ptr %ptr, half %value
define dso_local half @atomicrmw_fmin_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_release:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -1472,10 +1472,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_release(ptr %ptr, half %value
define dso_local half @atomicrmw_fmin_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_acq_rel:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1486,10 +1486,10 @@ define dso_local half @atomicrmw_fmin_half_aligned_acq_rel(ptr %ptr, half %value
define dso_local half @atomicrmw_fmin_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmin_half_aligned_seq_cst:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmin_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -1590,9 +1590,9 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_aligned_seq_cst(ptr %ptr, bfloat
define dso_local float @atomicrmw_fmin_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_monotonic:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_monotonic:
@@ -1604,9 +1604,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_monotonic(ptr %ptr, float %
define dso_local float @atomicrmw_fmin_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_acquire:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_acquire:
@@ -1618,9 +1618,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_acquire(ptr %ptr, float %va
define dso_local float @atomicrmw_fmin_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_release:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_release:
@@ -1632,9 +1632,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_release(ptr %ptr, float %va
define dso_local float @atomicrmw_fmin_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_acq_rel:
@@ -1646,9 +1646,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_acq_rel(ptr %ptr, float %va
define dso_local float @atomicrmw_fmin_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmin_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_seq_cst:
@@ -1660,9 +1660,9 @@ define dso_local float @atomicrmw_fmin_float_aligned_seq_cst(ptr %ptr, float %va
define dso_local double @atomicrmw_fmin_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_monotonic:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_monotonic:
@@ -1674,9 +1674,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_monotonic(ptr %ptr, doubl
define dso_local double @atomicrmw_fmin_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_acquire:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_acquire:
@@ -1688,9 +1688,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_acquire(ptr %ptr, double
define dso_local double @atomicrmw_fmin_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_release:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_release:
@@ -1702,9 +1702,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_release(ptr %ptr, double
define dso_local double @atomicrmw_fmin_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_acq_rel:
@@ -1716,9 +1716,9 @@ define dso_local double @atomicrmw_fmin_double_aligned_acq_rel(ptr %ptr, double
define dso_local double @atomicrmw_fmin_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmin_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_seq_cst:
@@ -1905,10 +1905,10 @@ define dso_local double @atomicrmw_fmin_double_unaligned_seq_cst(ptr %ptr, doubl
define dso_local half @atomicrmw_fmaximum_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -1919,10 +1919,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_monotonic(ptr %ptr, half
define dso_local half @atomicrmw_fmaximum_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_acquire:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -1933,10 +1933,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_acquire(ptr %ptr, half %v
define dso_local half @atomicrmw_fmaximum_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_release:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -1947,10 +1947,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_release(ptr %ptr, half %v
define dso_local half @atomicrmw_fmaximum_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_acq_rel:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1961,10 +1961,10 @@ define dso_local half @atomicrmw_fmaximum_half_aligned_acq_rel(ptr %ptr, half %v
define dso_local half @atomicrmw_fmaximum_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fmaximum_half_aligned_seq_cst:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fmaximum_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2065,9 +2065,9 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_aligned_seq_cst(ptr %ptr, bfl
define dso_local float @atomicrmw_fmaximum_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_monotonic:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_monotonic:
@@ -2079,9 +2079,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_monotonic(ptr %ptr, flo
define dso_local float @atomicrmw_fmaximum_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_acquire:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_acquire:
@@ -2093,9 +2093,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_acquire(ptr %ptr, float
define dso_local float @atomicrmw_fmaximum_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_release:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_release:
@@ -2107,9 +2107,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_release(ptr %ptr, float
define dso_local float @atomicrmw_fmaximum_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_acq_rel:
@@ -2121,9 +2121,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_acq_rel(ptr %ptr, float
define dso_local float @atomicrmw_fmaximum_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fmaximum_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_seq_cst:
@@ -2135,9 +2135,9 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_seq_cst(ptr %ptr, float
define dso_local double @atomicrmw_fmaximum_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_monotonic:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_monotonic:
@@ -2149,9 +2149,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_monotonic(ptr %ptr, d
define dso_local double @atomicrmw_fmaximum_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_acquire:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_acquire:
@@ -2163,9 +2163,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_acquire(ptr %ptr, dou
define dso_local double @atomicrmw_fmaximum_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_release:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_release:
@@ -2177,9 +2177,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_release(ptr %ptr, dou
define dso_local double @atomicrmw_fmaximum_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_acq_rel:
@@ -2191,9 +2191,9 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_acq_rel(ptr %ptr, dou
define dso_local double @atomicrmw_fmaximum_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fmaximum_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_seq_cst:
@@ -2380,10 +2380,10 @@ define dso_local double @atomicrmw_fmaximum_double_unaligned_seq_cst(ptr %ptr, d
define dso_local half @atomicrmw_fminimum_half_aligned_monotonic(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_monotonic:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -2394,10 +2394,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_monotonic(ptr %ptr, half
define dso_local half @atomicrmw_fminimum_half_aligned_acquire(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_acquire:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -2408,10 +2408,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_acquire(ptr %ptr, half %v
define dso_local half @atomicrmw_fminimum_half_aligned_release(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_release:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -2422,10 +2422,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_release(ptr %ptr, half %v
define dso_local half @atomicrmw_fminimum_half_aligned_acq_rel(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_acq_rel:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -2436,10 +2436,10 @@ define dso_local half @atomicrmw_fminimum_half_aligned_acq_rel(ptr %ptr, half %v
define dso_local half @atomicrmw_fminimum_half_aligned_seq_cst(ptr %ptr, half %value) {
; -O0-LABEL: atomicrmw_fminimum_half_aligned_seq_cst:
-; -O0: ldaxrh w9, [x10]
-; -O0: cmp w9, w11, uxth
-; -O0: stlxrh w8, w12, [x10]
-; -O0: subs w8, w8, w9, uxth
+; -O0: ldaxrh w0, [x9]
+; -O0: cmp w0, w10, uxth
+; -O0: stlxrh w8, w11, [x9]
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_fminimum_half_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2540,9 +2540,9 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_aligned_seq_cst(ptr %ptr, bfl
define dso_local float @atomicrmw_fminimum_float_aligned_monotonic(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_monotonic:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_monotonic:
@@ -2554,9 +2554,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_monotonic(ptr %ptr, flo
define dso_local float @atomicrmw_fminimum_float_aligned_acquire(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_acquire:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_acquire:
@@ -2568,9 +2568,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_acquire(ptr %ptr, float
define dso_local float @atomicrmw_fminimum_float_aligned_release(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_release:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_release:
@@ -2582,9 +2582,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_release(ptr %ptr, float
define dso_local float @atomicrmw_fminimum_float_aligned_acq_rel(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_acq_rel:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_acq_rel:
@@ -2596,9 +2596,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_acq_rel(ptr %ptr, float
define dso_local float @atomicrmw_fminimum_float_aligned_seq_cst(ptr %ptr, float %value) {
; -O0-LABEL: atomicrmw_fminimum_float_aligned_seq_cst:
-; -O0: ldaxr w0, [x10]
-; -O0: cmp w0, w8
-; -O0: stlxr w9, w11, [x10]
+; -O0: ldaxr w0, [x9]
+; -O0: cmp w0, w10
+; -O0: stlxr w8, w11, [x9]
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_seq_cst:
@@ -2610,9 +2610,9 @@ define dso_local float @atomicrmw_fminimum_float_aligned_seq_cst(ptr %ptr, float
define dso_local double @atomicrmw_fminimum_double_aligned_monotonic(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_monotonic:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_monotonic:
@@ -2624,9 +2624,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_monotonic(ptr %ptr, d
define dso_local double @atomicrmw_fminimum_double_aligned_acquire(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_acquire:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_acquire:
@@ -2638,9 +2638,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_acquire(ptr %ptr, dou
define dso_local double @atomicrmw_fminimum_double_aligned_release(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_release:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_release:
@@ -2652,9 +2652,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_release(ptr %ptr, dou
define dso_local double @atomicrmw_fminimum_double_aligned_acq_rel(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_acq_rel:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_acq_rel:
@@ -2666,9 +2666,9 @@ define dso_local double @atomicrmw_fminimum_double_aligned_acq_rel(ptr %ptr, dou
define dso_local double @atomicrmw_fminimum_double_aligned_seq_cst(ptr %ptr, double %value) {
; -O0-LABEL: atomicrmw_fminimum_double_aligned_seq_cst:
-; -O0: ldaxr x0, [x10]
-; -O0: cmp x0, x8
-; -O0: stlxr w9, x11, [x10]
+; -O0: ldaxr x0, [x9]
+; -O0: cmp x0, x10
+; -O0: stlxr w8, x11, [x9]
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_seq_cst:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir b/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir
index b2bb44e551f81..474a7db32afd2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir
@@ -64,48 +64,48 @@ body: |
successors: %bb.3(0x30000000), %bb.2(0x50000000)
liveins: $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s64) = G_CONSTANT i64 457873110
- %2:gpr(s32) = G_CONSTANT i32 1
- G_BRCOND %2(s32), %bb.3
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i64) = G_CONSTANT i64 457873110
+ %2:gpr(i32) = G_CONSTANT i32 1
+ G_BRCOND %2(i32), %bb.3
G_BR %bb.2
bb.2:
successors: %bb.7(0x80000000)
- %3:gpr(s64) = G_CONSTANT_FOLD_BARRIER %1
+ %3:gpr(i64) = G_CONSTANT_FOLD_BARRIER %1
G_BR %bb.7
bb.3:
successors: %bb.4(0x40000000), %bb.5(0x40000000)
- %4:gpr(s32) = G_CONSTANT i32 1
- %5:gpr(s32) = G_XOR %0, %4
- %6:gpr(s32) = G_AND %5, %4
- G_BRCOND %6(s32), %bb.5
+ %4:gpr(i32) = G_CONSTANT i32 1
+ %5:gpr(i32) = G_XOR %0, %4
+ %6:gpr(i32) = G_AND %5, %4
+ G_BRCOND %6(i32), %bb.5
G_BR %bb.4
bb.4:
successors: %bb.6(0x80000000)
- %7:gpr(s64) = G_CONSTANT_FOLD_BARRIER %1
- %8:gpr(s64) = G_CONSTANT i64 -2
- %9:gpr(s64) = G_ADD %7, %8
+ %7:gpr(i64) = G_CONSTANT_FOLD_BARRIER %1
+ %8:gpr(i64) = G_CONSTANT i64 -2
+ %9:gpr(i64) = G_ADD %7, %8
G_BR %bb.6
bb.5:
- %10:gpr(s64) = G_CONSTANT_FOLD_BARRIER %1
- %11:gpr(s64) = G_CONSTANT i64 0
- %12:gpr(s64) = G_AND %11, %10
- $x0 = COPY %12(s64)
+ %10:gpr(i64) = G_CONSTANT_FOLD_BARRIER %1
+ %11:gpr(i64) = G_CONSTANT i64 0
+ %12:gpr(i64) = G_AND %11, %10
+ $x0 = COPY %12(i64)
RET_ReallyLR implicit $x0
bb.6:
successors: %bb.6(0x80000000)
- %13:gpr(s64) = G_PHI %9(s64), %bb.4, %15(s64), %bb.6
- %14:gpr(s64) = G_CONSTANT i64 -1
- %15:gpr(s64) = G_ADD %13, %14
+ %13:gpr(i64) = G_PHI %9(i64), %bb.4, %15(i64), %bb.6
+ %14:gpr(i64) = G_CONSTANT i64 -1
+ %15:gpr(i64) = G_ADD %13, %14
G_BR %bb.6
bb.7:
@@ -114,9 +114,9 @@ body: |
bb.8:
successors: %bb.8(0x7c000000), %bb.7(0x04000000)
- %16:gpr(s64) = G_CONSTANT i64 0
- %17:gpr(s32) = G_ICMP intpred(ugt), %3(s64), %16
- G_BRCOND %17(s32), %bb.8
+ %16:gpr(i64) = G_CONSTANT i64 0
+ %17:gpr(i32) = G_ICMP intpred(ugt), %3(i64), %16
+ G_BRCOND %17(i32), %bb.8
G_BR %bb.7
...
---
@@ -180,48 +180,48 @@ body: |
successors: %bb.3(0x30000000), %bb.2(0x50000000)
liveins: $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s64) = G_CONSTANT i64 457873110
- %2:gpr(s32) = G_CONSTANT i32 1
- G_BRCOND %2(s32), %bb.3
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i64) = G_CONSTANT i64 457873110
+ %2:gpr(i32) = G_CONSTANT i32 1
+ G_BRCOND %2(i32), %bb.3
G_BR %bb.2
bb.2:
successors: %bb.7(0x80000000)
- %3:gpr(s64) = G_CONSTANT_FOLD_BARRIER %1
+ %3:gpr(i64) = G_CONSTANT_FOLD_BARRIER %1
G_BR %bb.7
bb.3:
successors: %bb.4(0x40000000), %bb.5(0x40000000)
- %4:gpr(s32) = G_CONSTANT i32 1
- %5:gpr(s32) = G_XOR %0, %4
- %6:gpr(s32) = G_AND %5, %4
- G_BRCOND %6(s32), %bb.5
+ %4:gpr(i32) = G_CONSTANT i32 1
+ %5:gpr(i32) = G_XOR %0, %4
+ %6:gpr(i32) = G_AND %5, %4
+ G_BRCOND %6(i32), %bb.5
G_BR %bb.4
bb.4:
successors: %bb.6(0x80000000)
- %7:gpr(s64) = G_CONSTANT_FOLD_BARRIER %1
- %8:gpr(s64) = G_CONSTANT i64 -2
- %9:gpr(s64) = G_ADD %7, %8
+ %7:gpr(i64) = G_CONSTANT_FOLD_BARRIER %1
+ %8:gpr(i64) = G_CONSTANT i64 -2
+ %9:gpr(i64) = G_ADD %7, %8
G_BR %bb.6
bb.5:
- %10:gpr(s64) = G_CONSTANT_FOLD_BARRIER %1
- %11:gpr(s64) = G_CONSTANT i64 0
- %12:gpr(s64) = G_AND %10, %11
- $x0 = COPY %12(s64)
+ %10:gpr(i64) = G_CONSTANT_FOLD_BARRIER %1
+ %11:gpr(i64) = G_CONSTANT i64 0
+ %12:gpr(i64) = G_AND %10, %11
+ $x0 = COPY %12(i64)
RET_ReallyLR implicit $x0
bb.6:
successors: %bb.6(0x80000000)
- %13:gpr(s64) = G_PHI %9(s64), %bb.4, %15(s64), %bb.6
- %14:gpr(s64) = G_CONSTANT i64 -1
- %15:gpr(s64) = G_ADD %13, %14
+ %13:gpr(i64) = G_PHI %9(i64), %bb.4, %15(i64), %bb.6
+ %14:gpr(i64) = G_CONSTANT i64 -1
+ %15:gpr(i64) = G_ADD %13, %14
G_BR %bb.6
bb.7:
@@ -230,8 +230,8 @@ body: |
bb.8:
successors: %bb.8(0x7c000000), %bb.7(0x04000000)
- %16:gpr(s64) = G_CONSTANT i64 0
- %17:gpr(s32) = G_ICMP intpred(ugt), %3(s64), %16
- G_BRCOND %17(s32), %bb.8
+ %16:gpr(i64) = G_CONSTANT i64 0
+ %17:gpr(i32) = G_ICMP intpred(ugt), %3(i64), %16
+ G_BRCOND %17(i32), %bb.8
G_BR %bb.7
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index 4bc82a3719ae0..55d3de162eb8a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -2947,10 +2947,6 @@ define i16 @atomicrmw_add_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
-; CHECK-NOLSE-O0-NEXT: fmov s0, w9
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB37_1
; CHECK-NOLSE-O0-NEXT: b LBB37_5
@@ -3043,10 +3039,6 @@ define i16 @atomicrmw_xchg_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
-; CHECK-NOLSE-O0-NEXT: fmov s0, w9
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB38_1
; CHECK-NOLSE-O0-NEXT: b LBB38_5
@@ -3141,10 +3133,6 @@ define i16 @atomicrmw_sub_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
-; CHECK-NOLSE-O0-NEXT: fmov s0, w9
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB39_1
; CHECK-NOLSE-O0-NEXT: b LBB39_5
@@ -3243,10 +3231,6 @@ define i16 @atomicrmw_and_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
-; CHECK-NOLSE-O0-NEXT: fmov s0, w9
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB40_1
; CHECK-NOLSE-O0-NEXT: b LBB40_5
@@ -3345,10 +3329,6 @@ define i16 @atomicrmw_or_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
-; CHECK-NOLSE-O0-NEXT: fmov s0, w9
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB41_1
; CHECK-NOLSE-O0-NEXT: b LBB41_5
@@ -3443,10 +3423,6 @@ define i16 @atomicrmw_xor_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
-; CHECK-NOLSE-O0-NEXT: fmov s0, w9
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB42_1
; CHECK-NOLSE-O0-NEXT: b LBB42_5
@@ -3546,10 +3522,6 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
-; CHECK-NOLSE-O0-NEXT: fmov s0, w9
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB43_1
; CHECK-NOLSE-O0-NEXT: b LBB43_5
@@ -3567,8 +3539,8 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB43_1
; CHECK-OUTLINE-O0-NEXT: LBB43_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3585,11 +3557,7 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
-; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
-; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB43_1
; CHECK-OUTLINE-O0-NEXT: b LBB43_2
; CHECK-OUTLINE-O0-NEXT: LBB43_2: ; %atomicrmw.end
@@ -3674,10 +3642,6 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
-; CHECK-NOLSE-O0-NEXT: fmov s0, w9
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB44_1
; CHECK-NOLSE-O0-NEXT: b LBB44_5
@@ -3695,8 +3659,8 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB44_1
; CHECK-OUTLINE-O0-NEXT: LBB44_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3713,11 +3677,7 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
-; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
-; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB44_1
; CHECK-OUTLINE-O0-NEXT: b LBB44_2
; CHECK-OUTLINE-O0-NEXT: LBB44_2: ; %atomicrmw.end
@@ -3804,10 +3764,6 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
-; CHECK-NOLSE-O0-NEXT: fmov s0, w9
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB45_1
; CHECK-NOLSE-O0-NEXT: b LBB45_5
@@ -3825,8 +3781,8 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB45_1
; CHECK-OUTLINE-O0-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3843,11 +3799,7 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
-; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
-; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB45_1
; CHECK-OUTLINE-O0-NEXT: b LBB45_2
; CHECK-OUTLINE-O0-NEXT: LBB45_2: ; %atomicrmw.end
@@ -3934,10 +3886,6 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: uxth w8, w8
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: cset w8, eq
-; CHECK-NOLSE-O0-NEXT: fmov s0, w9
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-NOLSE-O0-NEXT: fmov w9, s0
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB46_1
; CHECK-NOLSE-O0-NEXT: b LBB46_5
@@ -3955,8 +3903,8 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldrh w8, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b LBB46_1
; CHECK-OUTLINE-O0-NEXT: LBB46_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -3973,11 +3921,7 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: cset w8, eq
-; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
-; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-OUTLINE-O0-NEXT: ; kill: def $s0 killed $h0
-; CHECK-OUTLINE-O0-NEXT: fmov w9, s0
-; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: tbz w8, #0, LBB46_1
; CHECK-OUTLINE-O0-NEXT: b LBB46_2
; CHECK-OUTLINE-O0-NEXT: LBB46_2: ; %atomicrmw.end
@@ -6559,17 +6503,29 @@ define { ptr, i1 } @cmpxchg_ptr(ptr %ptr, ptr %desired, ptr %new) {
}
define internal double @bitcast_to_double(ptr %ptr) {
-; CHECK-NOLSE-LABEL: bitcast_to_double:
-; CHECK-NOLSE: ; %bb.0:
-; CHECK-NOLSE-NEXT: ldar x8, [x0]
-; CHECK-NOLSE-NEXT: fmov d0, x8
-; CHECK-NOLSE-NEXT: ret
+; CHECK-NOLSE-O1-LABEL: bitcast_to_double:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: ldar x8, [x0]
+; CHECK-NOLSE-O1-NEXT: fmov d0, x8
+; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-LABEL: bitcast_to_double:
-; CHECK-OUTLINE: ; %bb.0:
-; CHECK-OUTLINE-NEXT: ldar x8, [x0]
-; CHECK-OUTLINE-NEXT: fmov d0, x8
-; CHECK-OUTLINE-NEXT: ret
+; CHECK-OUTLINE-O1-LABEL: bitcast_to_double:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: ldar x8, [x0]
+; CHECK-OUTLINE-O1-NEXT: fmov d0, x8
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: bitcast_to_double:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: ldar x0, [x0]
+; CHECK-NOLSE-O0-NEXT: fmov d0, x0
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: bitcast_to_double:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: ldar x0, [x0]
+; CHECK-OUTLINE-O0-NEXT: fmov d0, x0
+; CHECK-OUTLINE-O0-NEXT: ret
;
; CHECK-LSE-O1-LABEL: bitcast_to_double:
; CHECK-LSE-O1: ; %bb.0:
@@ -6579,8 +6535,8 @@ define internal double @bitcast_to_double(ptr %ptr) {
;
; CHECK-LSE-O0-LABEL: bitcast_to_double:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldar x8, [x0]
-; CHECK-LSE-O0-NEXT: fmov d0, x8
+; CHECK-LSE-O0-NEXT: ldar x0, [x0]
+; CHECK-LSE-O0-NEXT: fmov d0, x0
; CHECK-LSE-O0-NEXT: ret
%load = load atomic i64, ptr %ptr seq_cst, align 8
%bitcast = bitcast i64 %load to double
@@ -6588,17 +6544,29 @@ define internal double @bitcast_to_double(ptr %ptr) {
}
define internal float @bitcast_to_float(ptr %ptr) {
-; CHECK-NOLSE-LABEL: bitcast_to_float:
-; CHECK-NOLSE: ; %bb.0:
-; CHECK-NOLSE-NEXT: ldar w8, [x0]
-; CHECK-NOLSE-NEXT: fmov s0, w8
-; CHECK-NOLSE-NEXT: ret
+; CHECK-NOLSE-O1-LABEL: bitcast_to_float:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: ldar w8, [x0]
+; CHECK-NOLSE-O1-NEXT: fmov s0, w8
+; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-LABEL: bitcast_to_float:
-; CHECK-OUTLINE: ; %bb.0:
-; CHECK-OUTLINE-NEXT: ldar w8, [x0]
-; CHECK-OUTLINE-NEXT: fmov s0, w8
-; CHECK-OUTLINE-NEXT: ret
+; CHECK-OUTLINE-O1-LABEL: bitcast_to_float:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: ldar w8, [x0]
+; CHECK-OUTLINE-O1-NEXT: fmov s0, w8
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: bitcast_to_float:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: ldar w0, [x0]
+; CHECK-NOLSE-O0-NEXT: fmov s0, w0
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: bitcast_to_float:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: ldar w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
+; CHECK-OUTLINE-O0-NEXT: ret
;
; CHECK-LSE-O1-LABEL: bitcast_to_float:
; CHECK-LSE-O1: ; %bb.0:
@@ -6608,8 +6576,8 @@ define internal float @bitcast_to_float(ptr %ptr) {
;
; CHECK-LSE-O0-LABEL: bitcast_to_float:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldar w8, [x0]
-; CHECK-LSE-O0-NEXT: fmov s0, w8
+; CHECK-LSE-O0-NEXT: ldar w0, [x0]
+; CHECK-LSE-O0-NEXT: fmov s0, w0
; CHECK-LSE-O0-NEXT: ret
%load = load atomic i32, ptr %ptr seq_cst, align 8
%bitcast = bitcast i32 %load to float
@@ -6617,19 +6585,33 @@ define internal float @bitcast_to_float(ptr %ptr) {
}
define internal half @bitcast_to_half(ptr %ptr) {
-; CHECK-NOLSE-LABEL: bitcast_to_half:
-; CHECK-NOLSE: ; %bb.0:
-; CHECK-NOLSE-NEXT: ldarh w8, [x0]
-; CHECK-NOLSE-NEXT: fmov s0, w8
-; CHECK-NOLSE-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-NEXT: ret
+; CHECK-NOLSE-O1-LABEL: bitcast_to_half:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: ldarh w8, [x0]
+; CHECK-NOLSE-O1-NEXT: fmov s0, w8
+; CHECK-NOLSE-O1-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-LABEL: bitcast_to_half:
-; CHECK-OUTLINE: ; %bb.0:
-; CHECK-OUTLINE-NEXT: ldarh w8, [x0]
-; CHECK-OUTLINE-NEXT: fmov s0, w8
-; CHECK-OUTLINE-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-OUTLINE-NEXT: ret
+; CHECK-OUTLINE-O1-LABEL: bitcast_to_half:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: ldarh w8, [x0]
+; CHECK-OUTLINE-O1-NEXT: fmov s0, w8
+; CHECK-OUTLINE-O1-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: bitcast_to_half:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: ldarh w0, [x0]
+; CHECK-NOLSE-O0-NEXT: fmov s0, w0
+; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: bitcast_to_half:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: ldarh w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
+; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-O0-NEXT: ret
;
; CHECK-LSE-O1-LABEL: bitcast_to_half:
; CHECK-LSE-O1: ; %bb.0:
@@ -6640,8 +6622,8 @@ define internal half @bitcast_to_half(ptr %ptr) {
;
; CHECK-LSE-O0-LABEL: bitcast_to_half:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldarh w8, [x0]
-; CHECK-LSE-O0-NEXT: fmov s0, w8
+; CHECK-LSE-O0-NEXT: ldarh w0, [x0]
+; CHECK-LSE-O0-NEXT: fmov s0, w0
; CHECK-LSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
; CHECK-LSE-O0-NEXT: ret
%load = load atomic i16, ptr %ptr seq_cst, align 8
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
index 3b56d062ffc5c..bffce0e5d0161 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err
; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
index 46efce8004c9c..4b957877034ac 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
@@ -179,16 +179,16 @@ define i32 @jt_test(i32 %x) {
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[C4]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](i32)
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C]](i32)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[ZEXT]](s64), [[ZEXT1]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[SUB]](i32)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[C]](i32)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[ZEXT]](i64), [[ZEXT1]]
; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.entry:
; CHECK-NEXT: successors: %bb.3, %bb.4, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
- ; CHECK-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[ZEXT]](s64)
+ ; CHECK-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[ZEXT]](i64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.sw.bb:
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = nsw G_ADD [[COPY]], [[C2]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index d54a0581ceac8..41f12729664f5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat=false 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CV
; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CI
; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
@@ -286,22 +285,23 @@ define ptr @trivial_bitcast(ptr %a) {
}
; CHECK-LABEL: name: trivial_bitcast_with_copy
-; CHECK: [[A:%[0-9]+]]:_(i64) = COPY $x0
+; CHECK: [[A:%[0-9]+]]:_(f64) = COPY $d0
; CHECK: G_BR %[[CAST:bb\.[0-9]+]]
; CHECK: [[END:bb\.[0-9]+]].{{[a-zA-Z0-9.]+}}:
-; CHECK: $x0 = COPY [[A]]
+; CHECK: $x0 = COPY [[B:%[0-9]+]]
; CHECK: [[CAST]].{{[a-zA-Z0-9.]+}}:
+; CHECK: [[B]]:_(i64) = G_BITCAST [[A]](f64)
; CHECK: G_BR %[[END]]
-define i64 @trivial_bitcast_with_copy(i64 %a) {
+define i64 @trivial_bitcast_with_copy(double %a) {
br label %cast
end:
ret i64 %val
cast:
- %val = bitcast i64 %a to i64
+ %val = bitcast double %a to i64
br label %end
}
@@ -1689,8 +1689,8 @@ define <2 x double> @test_constantdatavector_v2f64() {
ret <2 x double> <double 1.0, double 2.0>
}
-define i32 @test_constantaggzerovector_v1i32(i32 %arg){
-; CHECK-LABEL: name: test_constantaggzerovector_v1i32
+define i32 @test_constantaggzerovector_v1s32(i32 %arg){
+; CHECK-LABEL: name: test_constantaggzerovector_v1s32
; CHECK: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
; CHECK: [[C0:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NOT: G_MERGE_VALUES
@@ -1703,8 +1703,8 @@ define i32 @test_constantaggzerovector_v1i32(i32 %arg){
ret i32 %res
}
-define i32 @test_constantdatavector_v1i32(i32 %arg){
-; CHECK-CV-LABEL: name: test_constantdatavector_v1i32
+define i32 @test_constantdatavector_v1s32(i32 %arg){
+; CHECK-CV-LABEL: name: test_constantdatavector_v1s32
; CHECK-CV: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-CV: [[C0:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-CV-NOT: G_MERGE_VALUES
@@ -1712,7 +1712,7 @@ define i32 @test_constantdatavector_v1i32(i32 %arg){
; CHECK-CV-NOT: G_MERGE_VALUES
; CHECK-CV: G_ADD [[ARG]], [[COPY]]
;
-; CHECK-CI-LABEL: name: test_constantdatavector_v1i32
+; CHECK-CI-LABEL: name: test_constantdatavector_v1s32
; CHECK-CI: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
; CHECK-CI: [[C0:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; CHECK-CI-NOT: G_MERGE_VALUES
@@ -1733,8 +1733,8 @@ define float @test_different_call_conv_target(float %x) {
ret float %res
}
-define <2 x i32> @test_shufflevector_i32_v2i32(i32 %arg) {
-; CHECK-LABEL: name: test_shufflevector_i32_v2i32
+define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
+; CHECK-LABEL: name: test_shufflevector_s32_v2s32
; CHECK: [[ARG:%[0-9]+]]:_(i32) = COPY $w0
; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[ARG]](i32), [[ARG]](i32)
; CHECK: $d0 = COPY [[VEC]](<2 x i32>)
@@ -1743,8 +1743,8 @@ define <2 x i32> @test_shufflevector_i32_v2i32(i32 %arg) {
ret <2 x i32> %res
}
-define i32 @test_shufflevector_v2i32_i32(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2i32_i32
+define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2s32_s32
; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
; CHECK: [[IDX:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK: [[RES:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[ARG]](<2 x i32>), [[IDX]](i64)
@@ -1754,8 +1754,8 @@ define i32 @test_shufflevector_v2i32_i32(<2 x i32> %arg) {
ret i32 %res
}
-define <2 x i32> @test_shufflevector_v2i32_v2i32_undef(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2i32_v2i32_undef
+define <2 x i32> @test_shufflevector_v2s32_v2s32_undef(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_undef
; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(undef, undef)
@@ -1764,8 +1764,8 @@ define <2 x i32> @test_shufflevector_v2i32_v2i32_undef(<2 x i32> %arg) {
ret <2 x i32> %res
}
-define <2 x i32> @test_shufflevector_v2i32_v2i32_undef_0(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2i32_v2i32_undef_0
+define <2 x i32> @test_shufflevector_v2s32_v2s32_undef_0(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_undef_0
; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(undef, 0)
@@ -1774,8 +1774,8 @@ define <2 x i32> @test_shufflevector_v2i32_v2i32_undef_0(<2 x i32> %arg) {
ret <2 x i32> %res
}
-define <2 x i32> @test_shufflevector_v2i32_v2i32_0_undef(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2i32_v2i32_0_undef
+define <2 x i32> @test_shufflevector_v2s32_v2s32_0_undef(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_0_undef
; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(0, undef)
@@ -1784,8 +1784,8 @@ define <2 x i32> @test_shufflevector_v2i32_v2i32_0_undef(<2 x i32> %arg) {
ret <2 x i32> %res
}
-define i32 @test_shufflevector_v2i32_v3i32(<2 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v2i32_v3i32
+define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
; CHECK: [[ARG:%[0-9]+]]:_(<2 x i32>) = COPY $d0
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
; CHECK: [[VEC:%[0-9]+]]:_(<3 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x i32>), [[UNDEF]], shufflemask(1, 0, 1)
@@ -1795,8 +1795,8 @@ define i32 @test_shufflevector_v2i32_v3i32(<2 x i32> %arg) {
ret i32 %res
}
-define <4 x i32> @test_shufflevector_v2i32_v4i32(<2 x i32> %arg1, <2 x i32> %arg2) {
-; CHECK-LABEL: name: test_shufflevector_v2i32_v4i32
+define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) {
+; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
; CHECK: [[ARG1:%[0-9]+]]:_(<2 x i32>) = COPY $d0
; CHECK: [[ARG2:%[0-9]+]]:_(<2 x i32>) = COPY $d1
; CHECK: [[VEC:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x i32>), [[ARG2]], shufflemask(0, 1, 2, 3)
@@ -1805,8 +1805,8 @@ define <4 x i32> @test_shufflevector_v2i32_v4i32(<2 x i32> %arg1, <2 x i32> %arg
ret <4 x i32> %res
}
-define <2 x i32> @test_shufflevector_v4i32_v2i32(<4 x i32> %arg) {
-; CHECK-LABEL: name: test_shufflevector_v4i32_v2i32
+define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
+; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
; CHECK: [[ARG:%[0-9]+]]:_(<4 x i32>) = COPY $q0
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
; CHECK: [[VEC:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x i32>), [[UNDEF]], shufflemask(1, 3)
@@ -1816,8 +1816,8 @@ define <2 x i32> @test_shufflevector_v4i32_v2i32(<4 x i32> %arg) {
}
-define <16 x i8> @test_shufflevector_v8i8_v16i8(<8 x i8> %arg1, <8 x i8> %arg2) {
-; CHECK-LABEL: name: test_shufflevector_v8i8_v16i8
+define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) {
+; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8
; CHECK: [[ARG1:%[0-9]+]]:_(<8 x i8>) = COPY $d0
; CHECK: [[ARG2:%[0-9]+]]:_(<8 x i8>) = COPY $d1
; CHECK: [[VEC:%[0-9]+]]:_(<16 x i8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x i8>), [[ARG2]], shufflemask(0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
index b1eded3d40387..7232c36a1affc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
@@ -164,7 +164,7 @@ body: |
; CHECK-LABEL: name: defaultMapping1Repair
; CHECK: %0:fpr(s32) = COPY $s0
; CHECK-NEXT: %1:gpr(s32) = COPY $w0
- ; CHECK-NEXT: %3:gpr(s32) = COPY %0
+ ; CHECK-NEXT: %3:gpr(i32) = COPY %0
; CHECK-NEXT: %2:gpr(s32) = G_ADD %3, %1
%0(s32) = COPY $s0
%1(s32) = COPY $w0
@@ -182,8 +182,8 @@ body: |
liveins: $s0, $x0
; CHECK-LABEL: name: defaultMapping2Repairs
; CHECK: %0:fpr(s32) = COPY $s0
- ; CHECK-NEXT: %2:gpr(s32) = COPY %0
- ; CHECK-NEXT: %3:gpr(s32) = COPY %0
+ ; CHECK-NEXT: %2:gpr(i32) = COPY %0
+ ; CHECK-NEXT: %3:gpr(i32) = COPY %0
; CHECK-NEXT: %1:gpr(s32) = G_ADD %2, %3
%0(s32) = COPY $s0
%1(s32) = G_ADD %0, %0
@@ -204,7 +204,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: defaultMappingDefRepair
; CHECK: %0:gpr(s32) = COPY $w0
- ; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %0
+ ; CHECK-NEXT: %2:gpr(i32) = G_ADD %0, %0
; CHECK-NEXT: %1:fpr(s32) = COPY %2
%0(s32) = COPY $w0
%1(s32) = G_ADD %0, %0
@@ -263,7 +263,7 @@ body: |
; CHECK-LABEL: name: defaultMappingUseRepairPhysReg
; CHECK: %0:gpr(s32) = COPY $w0
; CHECK-NEXT: %1:fpr(s32) = COPY $s0
- ; CHECK-NEXT: %3:gpr(s32) = COPY %1
+ ; CHECK-NEXT: %3:gpr(i32) = COPY %1
; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %3
%0(s32) = COPY $w0
%1(s32) = COPY $s0
@@ -730,7 +730,7 @@ registers:
# CHECK-NEXT: %1:gpr(p0) = COPY $x1
# CHECK-NEXT: %2:fpr(s64) = G_LOAD %1(p0) :: (load (s64) from %ir.addr)
# %0 has been mapped to GPR, we need to repair to match FPR.
-# CHECK-NEXT: %4:fpr(s64) = COPY %0
+# CHECK-NEXT: %4:fpr(i64) = COPY %0
# CHECK-NEXT: %3:fpr(s64) = G_FADD %4, %2
# CHECK-NEXT: $x0 = COPY %3(s64)
# CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -769,8 +769,8 @@ registers:
# CHECK: %0:gpr(s64) = COPY $x0
# CHECK-NEXT: %1:gpr(p0) = COPY $x1
# %0 has been mapped to GPR, we need to repair to match FPR.
-# CHECK-NEXT: %3:fpr(s64) = COPY %0
-# CHECK-NEXT: %4:fpr(s64) = COPY %0
+# CHECK-NEXT: %3:fpr(i64) = COPY %0
+# CHECK-NEXT: %4:fpr(i64) = COPY %0
# CHECK-NEXT: %2:fpr(s64) = G_FADD %3, %4
# CHECK-NEXT: G_STORE %2(s64), %1(p0) :: (store (s64) into %ir.addr)
# CHECK-NEXT: RET_ReallyLR
@@ -805,7 +805,7 @@ registers:
# CHECK: %1:gpr(s32) = COPY $w0
# CHECK-NEXT: %0:gpr(s16) = G_TRUNC %1
# %0 has been mapped to GPR, we need to repair to match FPR.
-# CHECK-NEXT: %3:fpr(s16) = COPY %0
+# CHECK-NEXT: %3:fpr(i16) = COPY %0
# CHECK-NEXT: %2:fpr(s32) = G_FPEXT %3
# CHECK-NEXT: $s0 = COPY %2
# CHECK-NEXT: RET_ReallyLR
@@ -840,7 +840,7 @@ registers:
# CHECK: %1:gpr(s32) = COPY $w0
# CHECK-NEXT: %0:gpr(s16) = G_TRUNC %1
# %0 has been mapped to GPR, we need to repair to match FPR.
-# CHECK-NEXT: %3:fpr(s16) = COPY %0
+# CHECK-NEXT: %3:fpr(i16) = COPY %0
# CHECK-NEXT: %2:fpr(s64) = G_FPEXT %3
# CHECK-NEXT: $d0 = COPY %2
# CHECK-NEXT: RET_ReallyLR
@@ -872,7 +872,7 @@ registers:
- { id: 1, class: _ }
# CHECK: %0:gpr(s32) = COPY $w0
# %0 has been mapped to GPR, we need to repair to match FPR.
-# CHECK-NEXT: %2:fpr(s32) = COPY %0
+# CHECK-NEXT: %2:fpr(i32) = COPY %0
# CHECK-NEXT: %1:fpr(s64) = G_FPEXT %2
# CHECK-NEXT: $d0 = COPY %1
# CHECK-NEXT: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
index 00abaeb6e66ba..47a974f95165f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
@@ -21,14 +21,14 @@ define ptr @C_ctor_base(ptr returned %this, i32 %x) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
; CHECK-NEXT: BL @A_ctor_base, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
- ; CHECK-NEXT: $w1 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[COPY1]](i32)
; CHECK-NEXT: TCRETURNdi @B_ctor_base, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
entry:
%call = tail call ptr @A_ctor_base(ptr returned %this)
@@ -42,7 +42,7 @@ define ptr @C_ctor_base_nothisret(ptr %this, i32 %x) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
; CHECK-NEXT: BL @A_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def $x0
@@ -50,7 +50,7 @@ define ptr @C_ctor_base_nothisret(ptr %this, i32 %x) {
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
- ; CHECK-NEXT: $w1 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[COPY1]](i32)
; CHECK-NEXT: BL @B_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
@@ -68,9 +68,9 @@ define ptr @C_ctor_complete(ptr %this, i32 %x) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
- ; CHECK-NEXT: $w1 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[COPY1]](i32)
; CHECK-NEXT: TCRETURNdi @C_ctor_base, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
entry:
%call = tail call ptr @C_ctor_base(ptr returned %this, i32 %x)
@@ -83,10 +83,10 @@ define ptr @C_ctor_complete_nothisret(ptr %this, i32 %x) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
- ; CHECK-NEXT: $w1 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[COPY1]](i32)
; CHECK-NEXT: BL @C_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
@@ -103,15 +103,15 @@ define ptr @D_ctor_base(ptr %this, i32 %x) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
- ; CHECK-NEXT: $w1 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[COPY1]](i32)
; CHECK-NEXT: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
- ; CHECK-NEXT: $w1 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[COPY1]](i32)
; CHECK-NEXT: TCRETURNdi @B_ctor_complete, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
entry:
%call = tail call ptr @B_ctor_complete(ptr returned %this, i32 %x)
@@ -125,18 +125,18 @@ define ptr @E_ctor_base(ptr %this, i32 %x) {
; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $w1
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
- ; CHECK-NEXT: $w1 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[COPY1]](i32)
; CHECK-NEXT: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
- ; CHECK-NEXT: $w1 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[COPY1]](i32)
; CHECK-NEXT: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
index f8578a694e2d4..53a3552a8b2f0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
@@ -235,10 +235,10 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<16 x s8>) = G_UMULH [[COPY]], [[BUILD_VECTOR]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<16 x s8>) = G_LSHR [[UMULH]], [[BUILD_VECTOR1]](<16 x s8>)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s1>) = G_BUILD_VECTOR [[C3]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(<16 x s8>) = G_SELECT [[BUILD_VECTOR2]](<16 x s1>), [[COPY]], [[LSHR]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x i1>) = G_BUILD_VECTOR [[C3]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1), [[C4]](i1)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(<16 x s8>) = G_SELECT [[BUILD_VECTOR2]](<16 x i1>), [[COPY]], [[LSHR]]
; CHECK-NEXT: $q0 = COPY [[SELECT]](<16 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
@@ -285,10 +285,10 @@ body: |
; CHECK-NEXT: [[UMULH1:%[0-9]+]]:_(<8 x s16>) = G_UMULH [[SUB]], [[BUILD_VECTOR1]]
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UMULH1]], [[UMULH]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[ADD]], [[BUILD_VECTOR2]](<8 x s16>)
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
- ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<8 x s1>) = G_BUILD_VECTOR [[C13]](s1), [[C14]](s1), [[C14]](s1), [[C14]](s1), [[C14]](s1), [[C14]](s1), [[C14]](s1), [[C14]](s1)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(<8 x s16>) = G_SELECT [[BUILD_VECTOR3]](<8 x s1>), [[COPY]], [[LSHR]]
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i1) = G_CONSTANT i1 true
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i1) = G_CONSTANT i1 false
+ ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<8 x i1>) = G_BUILD_VECTOR [[C13]](i1), [[C14]](i1), [[C14]](i1), [[C14]](i1), [[C14]](i1), [[C14]](i1), [[C14]](i1), [[C14]](i1)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(<8 x s16>) = G_SELECT [[BUILD_VECTOR3]](<8 x i1>), [[COPY]], [[LSHR]]
; CHECK-NEXT: $q0 = COPY [[SELECT]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
index 1e3855cf534a4..2dd0a721b8c8c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
@@ -37,45 +37,45 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](i64)
; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
; CHECK-NEXT: G_STORE [[LOAD4]](f128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 80
- ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 80
+ ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](i64)
; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
- ; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
+ ; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](i64)
; CHECK-NEXT: G_STORE [[LOAD5]](f128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 96
- ; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 96
+ ; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](i64)
; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
- ; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
+ ; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](i64)
; CHECK-NEXT: G_STORE [[LOAD6]](f128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 112
- ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C6]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 112
+ ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C6]](i64)
; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
- ; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64)
+ ; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](i64)
; CHECK-NEXT: G_STORE [[LOAD7]](f128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 127
- ; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C7]](s64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 127
+ ; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C7]](i64)
; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
- ; CHECK-NEXT: [[PTR_ADD15:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](s64)
+ ; CHECK-NEXT: [[PTR_ADD15:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](i64)
; CHECK-NEXT: G_STORE [[LOAD8]](f128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
index c33e5641b1acb..48a6088e41f0e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
@@ -110,26 +110,26 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %ir.1 + 64, align 4)
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD4]](s64), [[PTR_ADD7]](p0) :: (store (s64) into %ir.0 + 64, align 4)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](i64)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %ir.1 + 64, align 4)
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; CHECK-NEXT: G_STORE [[LOAD4]](i64), [[PTR_ADD7]](p0) :: (store (s64) into %ir.0 + 64, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
@@ -158,26 +158,26 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %ir.1 + 64, align 4)
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD4]](s64), [[PTR_ADD7]](p0) :: (store (s64) into %ir.0 + 64, align 4)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](i64)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s64) from %ir.1 + 64, align 4)
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; CHECK-NEXT: G_STORE [[LOAD4]](i64), [[PTR_ADD7]](p0) :: (store (s64) into %ir.0 + 64, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
@@ -234,45 +234,45 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p0) :: (load (s128) from %ir.1 + 32, align 4)
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p0) :: (load (s128) from %ir.1 + 48, align 4)
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p0) :: (store (s128) into %ir.0 + 48, align 4)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](i64)
; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD6]](p0) :: (load (s128) from %ir.1 + 64, align 4)
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
; CHECK-NEXT: G_STORE [[LOAD4]](f128), [[PTR_ADD7]](p0) :: (store (s128) into %ir.0 + 64, align 4)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 80
- ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 80
+ ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](i64)
; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD8]](p0) :: (load (s128) from %ir.1 + 80, align 4)
- ; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64)
+ ; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](i64)
; CHECK-NEXT: G_STORE [[LOAD5]](f128), [[PTR_ADD9]](p0) :: (store (s128) into %ir.0 + 80, align 4)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 96
- ; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](s64)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 96
+ ; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](i64)
; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD10]](p0) :: (load (s128) from %ir.1 + 96, align 4)
- ; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
+ ; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](i64)
; CHECK-NEXT: G_STORE [[LOAD6]](f128), [[PTR_ADD11]](p0) :: (store (s128) into %ir.0 + 96, align 4)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 112
- ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C6]](s64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 112
+ ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C6]](i64)
; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD12]](p0) :: (load (s128) from %ir.1 + 112, align 4)
- ; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64)
+ ; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](i64)
; CHECK-NEXT: G_STORE [[LOAD7]](f128), [[PTR_ADD13]](p0) :: (store (s128) into %ir.0 + 112, align 4)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 127
- ; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C7]](s64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 127
+ ; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C7]](i64)
; CHECK-NEXT: [[LOAD8:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD14]](p0) :: (load (s128) from %ir.1 + 127, align 1, basealign 4)
- ; CHECK-NEXT: [[PTR_ADD15:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](s64)
+ ; CHECK-NEXT: [[PTR_ADD15:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C7]](i64)
; CHECK-NEXT: G_STORE [[LOAD8]](f128), [[PTR_ADD15]](p0) :: (store (s128) into %ir.0 + 127, align 1, basealign 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
@@ -302,26 +302,26 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p2) = COPY $x1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](i64)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD2]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](i64)
; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 48
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](i64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD4]](p2) :: (load (s128) from %ir.1 + 48, align 4, addrspace 2)
- ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[LOAD3]](f128), [[PTR_ADD5]](p1) :: (store (s128) into %ir.0 + 48, align 4, addrspace 1)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](s64)
- ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p2) :: (load (s64) from %ir.1 + 64, align 4, addrspace 2)
- ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD4]](s64), [[PTR_ADD7]](p1) :: (store (s64) into %ir.0 + 64, align 4, addrspace 1)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p2) = nuw inbounds G_PTR_ADD [[COPY1]], [[C3]](i64)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(i64) = G_LOAD [[PTR_ADD6]](p2) :: (load (s64) from %ir.1 + 64, align 4, addrspace 2)
+ ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
+ ; CHECK-NEXT: G_STORE [[LOAD4]](i64), [[PTR_ADD7]](p1) :: (store (s64) into %ir.0 + 64, align 4, addrspace 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p1) = COPY $x0
%1:_(p2) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
index b06b064b361de..1613fe255f044 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
@@ -184,7 +184,7 @@ body: |
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.1 + 48)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.1 + 48)
; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)
@@ -194,7 +194,7 @@ body: |
; CHECK-NEXT: G_STORE [[LOAD2]](f128), [[PTR_ADD4]](p0) :: (store (s128) into %ir.0 + 32, align 4)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64)
- ; CHECK-NEXT: G_STORE [[LOAD3]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %ir.0 + 48)
+ ; CHECK-NEXT: G_STORE [[LOAD3]](i32), [[PTR_ADD5]](p0) :: (store (s32) into %ir.0 + 48)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
index 8f76472fb323c..0fdb388200cee 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
@@ -218,10 +218,10 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 4629771061636907072
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i64>), [[COPY]](p0) :: (store (<2 x i64>) into %ir.dst, align 1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 16448
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i16) = G_CONSTANT i16 16448
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[C1]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.dst + 16, align 1)
+ ; CHECK-NEXT: G_STORE [[C1]](i16), [[PTR_ADD]](p0) :: (store (i16) into %ir.dst + 16, align 1)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
index bd73e6870a14e..b10e273eb265b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
@@ -45,10 +45,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
; CHECK-NEXT: G_STORE [[LOAD]](f128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](i64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
; CHECK-NEXT: G_STORE [[LOAD1]](f128), [[PTR_ADD1]](p0) :: (store (s128) into %ir.0 + 16, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll b/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
index a7b555745d149..21402fade53dd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
@@ -4,9 +4,9 @@
define dso_local void @fn() {
; CHECK-LABEL: fn:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x8, #4132 // =0x1024
+; CHECK-NEXT: mov w8, #4132 // =0x1024
; CHECK-NEXT: mov w9, #1 // =0x1
-; CHECK-NEXT: movk x8, #65489, lsl #16
+; CHECK-NEXT: movk w8, #65489, lsl #16
; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-constrained-fcmp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-constrained-fcmp.ll
index 015508c2ece24..bb9c9caefabc1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-constrained-fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-constrained-fcmp.ll
@@ -6,22 +6,22 @@ define void @test_strict_fcmp(float %a, float %b) strictfp {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK-NEXT: [[STRICT_FCMP:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP1:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(ogt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP2:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(oge), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP3:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(olt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP4:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(ole), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP5:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(one), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP6:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP7:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(uno), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP8:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(ueq), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP9:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(ugt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP10:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(uge), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP11:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(ult), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP12:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(ule), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMP13:%[0-9]+]]:_(s1) = G_STRICT_FCMP floatpred(une), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[STRICT_FCMP:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(oeq), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP1:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(ogt), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP2:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(oge), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP3:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(olt), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP4:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(ole), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP5:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(one), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP6:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(ord), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP7:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(uno), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP8:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(ueq), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP9:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(ugt), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP10:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(uge), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP11:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(ult), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP12:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(ule), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMP13:%[0-9]+]]:_(i1) = G_STRICT_FCMP floatpred(une), [[COPY]](f32), [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%r0 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"oeq", metadata !"fpexcept.strict")
%r1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict")
@@ -45,22 +45,22 @@ define void @test_strict_fcmps(float %a, float %b) strictfp {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
- ; CHECK-NEXT: [[STRICT_FCMPS:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(oeq), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS1:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(ogt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS2:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(oge), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS3:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(olt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS4:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(ole), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS5:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(one), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS6:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(ord), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS7:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(uno), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS8:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(ueq), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS9:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(ugt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS10:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(uge), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS11:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(ult), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS12:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(ule), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[STRICT_FCMPS13:%[0-9]+]]:_(s1) = G_STRICT_FCMPS floatpred(une), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[STRICT_FCMPS:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(oeq), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS1:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(ogt), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS2:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(oge), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS3:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(olt), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS4:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(ole), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS5:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(one), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS6:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(ord), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS7:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(uno), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS8:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(ueq), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS9:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(ugt), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS10:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(uge), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS11:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(ult), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS12:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(ule), [[COPY]](f32), [[COPY1]]
+ ; CHECK-NEXT: [[STRICT_FCMPS13:%[0-9]+]]:_(i1) = G_STRICT_FCMPS floatpred(une), [[COPY]](f32), [[COPY1]]
; CHECK-NEXT: RET_ReallyLR
%r0 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"oeq", metadata !"fpexcept.strict")
%r1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
deleted file mode 100644
index 03c5a3764bff3..0000000000000
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-convert-fp16-intrinsics.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: llc -mtriple=aarch64-- -mcpu=falkor -mattr=+lse -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
-
-define i16 @convert_to_fp16(float %src) {
- ; CHECK-LABEL: name: convert_to_fp16
- ; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: liveins: $s0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
- ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[COPY]](f32)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i16) = G_BITCAST [[FPTRUNC]](f16)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[BITCAST]](i16)
- ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](i32)
- ; CHECK-NEXT: RET_ReallyLR implicit $w0
- %cvt = call i16 @llvm.convert.to.fp16.f32(float %src)
- ret i16 %cvt
-}
-
-define float @convert_from_fp16(i16 %src) {
- ; CHECK-LABEL: name: convert_from_fp16
- ; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: liveins: $w0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $w0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16)
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[BITCAST]](f16)
- ; CHECK-NEXT: $s0 = COPY [[FPEXT]](f32)
- ; CHECK-NEXT: RET_ReallyLR implicit $s0
- %cvt = call float @llvm.convert.from.fp16.f32(i16 %src)
- ret float %cvt
-}
-
-declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
-declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
index 94bf7e646c063..a7b8dec329481 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
@@ -26,7 +26,7 @@ define void @asm_simple_register_clobber() {
define i64 @asm_register_early_clobber() {
; CHECK-LABEL: name: asm_register_early_clobber
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 3866635 /* regdef-ec:GPR64common */, def early-clobber %0, 3866635 /* regdef-ec:GPR64common */, def early-clobber %1, !0
+ ; CHECK-NEXT: INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef-ec:GPR64common */, def early-clobber %0, {{[0-9]+}} /* regdef-ec:GPR64common */, def early-clobber %1, !0
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY %0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY %1
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i64) = G_ADD [[COPY]], [[COPY1]]
@@ -54,7 +54,7 @@ entry:
define i32 @test_single_register_output() nounwind ssp {
; CHECK-LABEL: name: test_single_register_output
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %0
+ ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY %0
; CHECK-NEXT: $w0 = COPY [[COPY]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -66,7 +66,7 @@ entry:
define i64 @test_single_register_output_s64() nounwind ssp {
; CHECK-LABEL: name: test_single_register_output_s64
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"mov $0, 7", 0 /* attdialect */, 3866634 /* regdef:GPR64common */, def %0
+ ; CHECK-NEXT: INLINEASM &"mov $0, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR64common */, def %0
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY %0
; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -79,7 +79,7 @@ entry:
define float @test_multiple_register_outputs_same() #0 {
; CHECK-LABEL: name: test_multiple_register_outputs_same
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %0, 2818058 /* regdef:GPR32common */, def %1
+ ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:GPR32common */, def %1
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY %0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY %1
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[COPY1]]
@@ -96,7 +96,7 @@ define float @test_multiple_register_outputs_same() #0 {
define double @test_multiple_register_outputs_mixed() #0 {
; CHECK-LABEL: name: test_multiple_register_outputs_mixed
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %0, 3670026 /* regdef:FPR64 */, def %1
+ ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:FPR64 */, def %1
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY %0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY %1
; CHECK-NEXT: $d0 = COPY [[COPY1]](f64)
@@ -125,7 +125,7 @@ define zeroext i8 @test_register_output_trunc(ptr %src) nounwind {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %1
+ ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i8)
@@ -155,7 +155,7 @@ define void @test_input_register_imm() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](i64)
- ; CHECK-NEXT: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 3866633 /* reguse:GPR64common */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:GPR64common */, [[COPY]]
; CHECK-NEXT: RET_ReallyLR
call void asm sideeffect "mov x0, $0", "r"(i64 42)
ret void
@@ -209,7 +209,7 @@ define zeroext i8 @test_input_register(ptr %src) nounwind {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0)
- ; CHECK-NEXT: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 2818058 /* regdef:GPR32common */, def %1, 3866633 /* reguse:GPR64common */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, {{[0-9]+}} /* reguse:GPR64common */, [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY2]](s32)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i8)
@@ -226,7 +226,7 @@ define i32 @test_memory_constraint(ptr %a) nounwind {
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 2818058 /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
+ ; CHECK-NEXT: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, {{[0-9]+}} /* mem:m */, [[COPY]](p0)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY %1
; CHECK-NEXT: $w0 = COPY [[COPY1]](i32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -240,7 +240,7 @@ define i16 @test_anyext_input() {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](i16)
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2818058 /* regdef:GPR32common */, def %0, 2818057 /* reguse:GPR32common */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* reguse:GPR32common */, [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i16)
@@ -256,7 +256,7 @@ define i16 @test_anyext_input_with_matching_constraint() {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 1
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](i16)
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2818058 /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[TRUNC]](i16)
@@ -290,7 +290,7 @@ define void @test_indirectify_i32_value(i32 %x, i32 %y) {
; CHECK-NEXT: G_STORE [[COPY]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %stack.0)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1
; CHECK-NEXT: G_STORE [[COPY1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %stack.1)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0), {{[0-9]+}} /* mem:m */, [[FRAME_INDEX1]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 %x, i32 %y)
@@ -306,7 +306,7 @@ define void @test_indirectify_i32_constant() {
; CHECK-NEXT: G_STORE [[C]](i32), [[FRAME_INDEX]](p0) :: (store (i32) into %stack.0)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1
; CHECK-NEXT: G_STORE [[C1]](i32), [[FRAME_INDEX1]](p0) :: (store (i32) into %stack.1)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0), {{[0-9]+}} /* mem:m */, [[FRAME_INDEX1]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 42, i32 0)
@@ -322,7 +322,7 @@ define void @test_indirectify_i16_value(i16 %val) {
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[TRUNC]](i16), [[FRAME_INDEX]](p0) :: (store (i16) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i16 %val)
@@ -335,7 +335,7 @@ define void @test_indirectify_i16_constant() {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i16) = G_CONSTANT i16 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[C]](i16), [[FRAME_INDEX]](p0) :: (store (i16) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i16 42)
@@ -350,7 +350,7 @@ define void @test_indirectify_i64_value(i64 %val) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[COPY]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i64 %val)
@@ -363,7 +363,7 @@ define void @test_indirectify_i64_constant() {
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: G_STORE [[C]](i64), [[FRAME_INDEX]](p0) :: (store (i64) into %stack.0)
- ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)
; CHECK-NEXT: RET_ReallyLR
entry:
tail call void asm sideeffect "", "imr,~{memory}"(i64 42)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
index d39fa9ecc3a42..e2a594c221e57 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
@@ -15,7 +15,7 @@ define i32 @test_bittest(i16 %p) {
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[ZEXT]], [[C3]]
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](i32)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[SUB]](i32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 59
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i32), [[C4]]
; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
@@ -32,7 +32,7 @@ define i32 @test_bittest(i16 %p) {
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[ZEXT1]](s64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[ZEXT1]](i64)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C6]]
; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
@@ -84,7 +84,7 @@ define void @test_bittest_2_bt(i32 %p) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[C2]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB1]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[SUB1]](i32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 38
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB1]](i32), [[C3]]
; CHECK-NEXT: G_BRCOND [[ICMP1]](i1), %bb.4
@@ -106,7 +106,7 @@ define void @test_bittest_2_bt(i32 %p) {
; CHECK-NEXT: successors: %bb.3(0x71c71c72), %bb.4(0x0e38e38e)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i64) = G_SHL [[C7]], [[ZEXT]](s64)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i64) = G_SHL [[C7]], [[ZEXT]](i64)
; CHECK-NEXT: [[C8:%[0-9]+]]:_(i64) = G_CONSTANT i64 365072220160
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[SHL1]], [[C8]]
; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
@@ -161,7 +161,7 @@ define i32 @test_bittest_single_bt_only_with_fallthrough(i16 %p) {
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[ZEXT]], [[C2]]
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](i32)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i64) = G_ZEXT [[SUB]](i32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 59
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i32), [[C3]]
; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.2
@@ -170,7 +170,7 @@ define i32 @test_bittest_single_bt_only_with_fallthrough(i16 %p) {
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.2(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C4]], [[ZEXT1]](s64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C4]], [[ZEXT1]](i64)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C5]]
; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
@@ -282,7 +282,7 @@ define i32 @test_odd_type(i328 %p) {
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i328) = G_CONSTANT i328 0
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i328) = G_SUB [[TRUNC]], [[C3]]
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[SUB]](i328)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i64) = G_TRUNC [[SUB]](i328)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i328) = G_CONSTANT i328 59
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i328), [[C4]]
; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
@@ -299,7 +299,7 @@ define i32 @test_odd_type(i328 %p) {
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[TRUNC1]](s64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[TRUNC1]](i64)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C6]]
; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
@@ -344,7 +344,7 @@ define i32 @test_large_pow2_type(i256 %p) {
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i256) = G_CONSTANT i256 0
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i256) = G_SUB [[MV]], [[C3]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[SUB]](i256)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i64) = G_TRUNC [[SUB]](i256)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i256) = G_CONSTANT i256 59
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i1) = G_ICMP intpred(ugt), [[SUB]](i256), [[C4]]
; CHECK-NEXT: G_BRCOND [[ICMP]](i1), %bb.4
@@ -361,7 +361,7 @@ define i32 @test_large_pow2_type(i256 %p) {
; CHECK-NEXT: successors: %bb.3(0x745d1746), %bb.4(0x0ba2e8ba)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[TRUNC]](s64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i64) = G_SHL [[C5]], [[TRUNC]](i64)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 866239240827043840
; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SHL]], [[C6]]
; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
index c28894b746f5e..9301e1aa05d9e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
@@ -71,7 +71,7 @@ define void @test2() #0 personality ptr @__gcc_personality_v0 {
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[DEF]](p0)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3866633 /* reguse:GPR64common */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:GPR64common */, [[COPY]]
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
index ceddb4bca7255..96f1da26bebc5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
@@ -9,8 +9,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
%0:_(s64) = COPY $x0
@@ -34,9 +34,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
- ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(i32) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
; CHECK-NEXT: $x2 = COPY [[UADDE2]](s64)
@@ -83,8 +83,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
%0:_(s64) = COPY $x0
@@ -111,8 +111,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
%0:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index da37555a4ef37..252960568fe94 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -5,22 +5,22 @@ name: test_scalar_and_small
body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_and_small
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
- ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
- %0:_(s64) = COPY $x0
- %1:_(s64) = COPY $x1
- %2:_(s8) = G_TRUNC %0(s64)
- %3:_(s8) = G_TRUNC %1(s64)
- %4:_(s8) = G_AND %2, %3
- %6:_(s32) = G_ANYEXT %4(s8)
- $w0 = COPY %6(s32)
- %5:_(s64) = G_ANYEXT %2(s8)
- $x0 = COPY %5(s64)
+ ; CHECK: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[COPY1]](i64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](i32)
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](i64)
+ %0:_(i64) = COPY $x0
+ %1:_(i64) = COPY $x1
+ %2:_(i8) = G_TRUNC %0(i64)
+ %3:_(i8) = G_TRUNC %1(i64)
+ %4:_(i8) = G_AND %2, %3
+ %6:_(i32) = G_ANYEXT %4(i8)
+ $w0 = COPY %6(i32)
+ %5:_(i64) = G_ANYEXT %2(i8)
+ $x0 = COPY %5(i64)
...
---
@@ -38,38 +38,40 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 10, align 2)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[DEF]](i32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C3]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[C]], [[LOAD]]
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR]], [[C]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i64) = G_OR [[C]], [[LOAD]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i64) = G_OR [[OR]], [[C]]
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64), align 16)
; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 8, align 8)
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 10, align 2)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD3]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD3]](s32), [[DEF]](i32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C3]](s64)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD1]]
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[C]], [[LOAD2]]
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[C]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[OR4]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[OR5]]
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64)
- ; CHECK-NEXT: G_STORE [[COPY1]](s64), %ptr(p0) :: (store (s64), align 16)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i64) = G_OR [[C]], [[LOAD2]]
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i64) = G_OR [[OR3]], [[C]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[OR1]], [[OR4]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[OR2]], [[OR5]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[AND]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[AND1]](i64)
+ ; CHECK-NEXT: G_STORE [[COPY1]](i64), %ptr(p0) :: (store (i64), align 16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
- ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD3]](p0) :: (store (s16) into unknown-address + 8, align 8)
- ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD4]](p0) :: (store (s8) into unknown-address + 10, align 2)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[TRUNC]], [[C5]](i64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C6]](i64)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[PTR_ADD3]](p0) :: (store (s16) into unknown-address + 8, align 8)
+ ; CHECK-NEXT: G_STORE [[LSHR]](i32), [[PTR_ADD4]](p0) :: (store (s8) into unknown-address + 10, align 2)
%ptr:_(p0) = COPY $x0
- %a:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
- %b:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
- %and:_(s88) = G_AND %a, %b
- G_STORE %and(s88), %ptr(p0) :: (store (s88))
+ %a:_(i88) = G_LOAD %ptr(p0) :: (load (s88))
+ %b:_(i88) = G_LOAD %ptr(p0) :: (load (s88))
+ %and:_(i88) = G_AND %a, %b
+ G_STORE %and(i88), %ptr(p0) :: (store (s88))
...
---
name: test_s318_and
@@ -88,26 +90,26 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]]
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C]]
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[AND2]], [[C]]
- ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C]]
- ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]]
- ; CHECK-NEXT: G_STORE [[AND5]](s64), %ptr(p0) :: (store (s64), align 64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4611686018427387903
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i64) = G_AND [[AND]], [[C]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i64) = G_AND [[AND1]], [[C]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i64) = G_AND [[AND2]], [[C]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i64) = G_AND [[AND3]], [[C]]
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(i64) = G_AND [[AND4]], [[C1]]
+ ; CHECK-NEXT: G_STORE [[AND5]](i64), %ptr(p0) :: (store (i64), align 64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
- ; CHECK-NEXT: G_STORE [[AND6]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[AND6]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
- ; CHECK-NEXT: G_STORE [[AND7]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
+ ; CHECK-NEXT: G_STORE [[AND7]](i64), [[PTR_ADD1]](p0) :: (store (i64) into unknown-address + 16, align 16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: G_STORE [[AND8]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
+ ; CHECK-NEXT: G_STORE [[AND8]](i64), [[PTR_ADD2]](p0) :: (store (i64) into unknown-address + 24)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
- ; CHECK-NEXT: G_STORE [[AND9]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
+ ; CHECK-NEXT: G_STORE [[AND9]](i64), [[PTR_ADD3]](p0) :: (store (i64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
%b:_(s318) = G_IMPLICIT_DEF
@@ -132,26 +134,26 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]]
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C]]
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[AND2]], [[C]]
- ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C]]
- ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]]
- ; CHECK-NEXT: G_STORE [[AND5]](s64), %ptr(p0) :: (store (s64), align 64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4611686018427387903
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i64) = G_AND [[AND]], [[C]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i64) = G_AND [[AND1]], [[C]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i64) = G_AND [[AND2]], [[C]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i64) = G_AND [[AND3]], [[C]]
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(i64) = G_AND [[AND4]], [[C1]]
+ ; CHECK-NEXT: G_STORE [[AND5]](i64), %ptr(p0) :: (store (i64), align 64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
- ; CHECK-NEXT: G_STORE [[AND6]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[AND6]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
- ; CHECK-NEXT: G_STORE [[AND7]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
+ ; CHECK-NEXT: G_STORE [[AND7]](i64), [[PTR_ADD1]](p0) :: (store (i64) into unknown-address + 16, align 16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: G_STORE [[AND8]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
+ ; CHECK-NEXT: G_STORE [[AND8]](i64), [[PTR_ADD2]](p0) :: (store (i64) into unknown-address + 24)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
- ; CHECK-NEXT: G_STORE [[AND9]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
+ ; CHECK-NEXT: G_STORE [[AND9]](i64), [[PTR_ADD3]](p0) :: (store (i64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
%b:_(s318) = G_IMPLICIT_DEF
@@ -166,19 +168,19 @@ name: test_vector_and_v16s16
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_and_v16s16
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY]], [[COPY]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY1]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[AND]](<8 x s16>)
- ; CHECK-NEXT: $q1 = COPY [[AND1]](<8 x s16>)
- %1:_(<8 x s16>) = COPY $q0
- %2:_(<8 x s16>) = COPY $q1
- %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
- %3:_(<16 x s16>) = G_AND %0, %0
- %4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
- $q0 = COPY %4(<8 x s16>)
- $q1 = COPY %5(<8 x s16>)
+ ; CHECK: [[COPY:%[0-9]+]]:_(<8 x i16>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x i16>) = COPY $q1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x i16>) = G_AND [[COPY]], [[COPY]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<8 x i16>) = G_AND [[COPY1]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[AND]](<8 x i16>)
+ ; CHECK-NEXT: $q1 = COPY [[AND1]](<8 x i16>)
+ %1:_(<8 x i16>) = COPY $q0
+ %2:_(<8 x i16>) = COPY $q1
+ %0:_(<16 x i16>) = G_CONCAT_VECTORS %1(<8 x i16>), %2(<8 x i16>)
+ %3:_(<16 x i16>) = G_AND %0, %0
+ %4:_(<8 x i16>), %5:_(<8 x i16>) = G_UNMERGE_VALUES %3(<16 x i16>)
+ $q0 = COPY %4(<8 x i16>)
+ $q1 = COPY %5(<8 x i16>)
...
---
@@ -186,19 +188,19 @@ name: test_vector_and_v32s8
body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_and_v32s8
- ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY]], [[COPY]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY1]], [[COPY1]]
- ; CHECK-NEXT: $q0 = COPY [[AND]](<16 x s8>)
- ; CHECK-NEXT: $q1 = COPY [[AND1]](<16 x s8>)
- %0:_(<16 x s8>) = COPY $q0
- %1:_(<16 x s8>) = COPY $q1
- %2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
- %3:_(<32 x s8>) = G_AND %2, %2
- %7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
- $q0 = COPY %7(<16 x s8>)
- $q1 = COPY %8(<16 x s8>)
+ ; CHECK: [[COPY:%[0-9]+]]:_(<16 x i8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x i8>) = COPY $q1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x i8>) = G_AND [[COPY]], [[COPY]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<16 x i8>) = G_AND [[COPY1]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[AND]](<16 x i8>)
+ ; CHECK-NEXT: $q1 = COPY [[AND1]](<16 x i8>)
+ %0:_(<16 x i8>) = COPY $q0
+ %1:_(<16 x i8>) = COPY $q1
+ %2:_(<32 x i8>) = G_CONCAT_VECTORS %0, %1
+ %3:_(<32 x i8>) = G_AND %2, %2
+ %7:_(<16 x i8>), %8:_(<16 x i8>) = G_UNMERGE_VALUES %3(<32 x i8>)
+ $q0 = COPY %7(<16 x i8>)
+ $q1 = COPY %8(<16 x i8>)
...
---
@@ -211,24 +213,24 @@ body: |
; CHECK-LABEL: name: and_v2s1
; CHECK: liveins: $d0, $d1, $d2, $d3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[ICMP]], [[ICMP1]]
- ; CHECK-NEXT: $d0 = COPY [[AND]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x i32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x i32>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x i32>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i32>) = G_ICMP intpred(eq), [[COPY]](<2 x i32>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i32>) = G_ICMP intpred(eq), [[COPY2]](<2 x i32>), [[COPY3]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i32>) = G_AND [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[AND]](<2 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<2 x s32>) = COPY $d0
- %1:_(<2 x s32>) = COPY $d1
- %2:_(<2 x s32>) = COPY $d2
- %3:_(<2 x s32>) = COPY $d3
- %4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
- %5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
- %6:_(<2 x s1>) = G_AND %4, %5
- %7:_(<2 x s32>) = G_ANYEXT %6
- $d0 = COPY %7:_(<2 x s32>)
+ %0:_(<2 x i32>) = COPY $d0
+ %1:_(<2 x i32>) = COPY $d1
+ %2:_(<2 x i32>) = COPY $d2
+ %3:_(<2 x i32>) = COPY $d3
+ %4:_(<2 x i1>) = G_ICMP intpred(eq), %0(<2 x i32>), %1
+ %5:_(<2 x i1>) = G_ICMP intpred(eq), %2(<2 x i32>), %3
+ %6:_(<2 x i1>) = G_AND %4, %5
+ %7:_(<2 x i32>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<2 x i32>)
RET_ReallyLR implicit $d0
...
---
@@ -241,28 +243,28 @@ body: |
; CHECK-LABEL: name: and_v3s1
; CHECK: liveins: $b0, $b1, $b2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[DEF]](s16)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[AND]](<4 x s16>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
- ; CHECK-NEXT: $b0 = COPY [[TRUNC]](s8)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i8) = COPY $b0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i8) = COPY $b1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i8) = COPY $b2
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i16) = G_ANYEXT [[COPY]](i8)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(i16) = G_ANYEXT [[COPY1]](i8)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(i16) = G_ANYEXT [[COPY2]](i8)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i16>) = G_BUILD_VECTOR [[ANYEXT]](i16), [[ANYEXT1]](i16), [[ANYEXT2]](i16), [[DEF]](i16)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x i16>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[AND]](<4 x i16>)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[UV]](i16)
+ ; CHECK-NEXT: $b0 = COPY [[TRUNC]](i8)
; CHECK-NEXT: RET_ReallyLR implicit $b0
- %1:_(s8) = COPY $b0
- %2:_(s8) = COPY $b1
- %3:_(s8) = COPY $b2
- %4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
- %0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
- %5:_(<3 x s1>) = G_AND %0, %0
- %7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
- %8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
- $b0 = COPY %8:_(s8)
+ %1:_(i8) = COPY $b0
+ %2:_(i8) = COPY $b1
+ %3:_(i8) = COPY $b2
+ %4:_(<3 x i8>) = G_BUILD_VECTOR %1(i8), %2(i8), %3(i8)
+ %0:_(<3 x i1>) = G_TRUNC %4(<3 x i8>)
+ %5:_(<3 x i1>) = G_AND %0, %0
+ %7:_(<3 x i8>) = G_ANYEXT %5(<3 x i1>)
+ %8:_(i8), %9:_(i8), %10:_(i8) = G_UNMERGE_VALUES %7(<3 x i8>)
+ $b0 = COPY %8:_(i8)
RET_ReallyLR implicit $b0
...
---
@@ -275,24 +277,24 @@ body: |
; CHECK-LABEL: name: and_v4s1
; CHECK: liveins: $d0, $d1, $d2, $d3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[ICMP]], [[ICMP1]]
- ; CHECK-NEXT: $d0 = COPY [[AND]](<4 x s16>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i16>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x i16>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x i16>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x i16>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x i16>) = G_ICMP intpred(eq), [[COPY]](<4 x i16>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x i16>) = G_ICMP intpred(eq), [[COPY2]](<4 x i16>), [[COPY3]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x i16>) = G_AND [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[AND]](<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<4 x s16>) = COPY $d0
- %1:_(<4 x s16>) = COPY $d1
- %2:_(<4 x s16>) = COPY $d2
- %3:_(<4 x s16>) = COPY $d3
- %4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
- %5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
- %6:_(<4 x s1>) = G_AND %4, %5
- %7:_(<4 x s16>) = G_ANYEXT %6
- $d0 = COPY %7:_(<4 x s16>)
+ %0:_(<4 x i16>) = COPY $d0
+ %1:_(<4 x i16>) = COPY $d1
+ %2:_(<4 x i16>) = COPY $d2
+ %3:_(<4 x i16>) = COPY $d3
+ %4:_(<4 x i1>) = G_ICMP intpred(eq), %0(<4 x i16>), %1
+ %5:_(<4 x i1>) = G_ICMP intpred(eq), %2(<4 x i16>), %3
+ %6:_(<4 x i1>) = G_AND %4, %5
+ %7:_(<4 x i16>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -305,24 +307,24 @@ body: |
; CHECK-LABEL: name: and_v8s1
; CHECK: liveins: $d0, $d1, $d2, $d3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s8>) = G_AND [[ICMP]], [[ICMP1]]
- ; CHECK-NEXT: $d0 = COPY [[AND]](<8 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x i8>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x i8>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x i8>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x i8>) = G_ICMP intpred(eq), [[COPY]](<8 x i8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x i8>) = G_ICMP intpred(eq), [[COPY2]](<8 x i8>), [[COPY3]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x i8>) = G_AND [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[AND]](<8 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:_(<8 x s8>) = COPY $d0
- %1:_(<8 x s8>) = COPY $d1
- %2:_(<8 x s8>) = COPY $d2
- %3:_(<8 x s8>) = COPY $d3
- %4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
- %5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
- %6:_(<8 x s1>) = G_AND %4, %5
- %7:_(<8 x s8>) = G_ANYEXT %6
- $d0 = COPY %7:_(<8 x s8>)
+ %0:_(<8 x i8>) = COPY $d0
+ %1:_(<8 x i8>) = COPY $d1
+ %2:_(<8 x i8>) = COPY $d2
+ %3:_(<8 x i8>) = COPY $d3
+ %4:_(<8 x i1>) = G_ICMP intpred(eq), %0(<8 x i8>), %1
+ %5:_(<8 x i1>) = G_ICMP intpred(eq), %2(<8 x i8>), %3
+ %6:_(<8 x i1>) = G_AND %4, %5
+ %7:_(<8 x i8>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<8 x i8>)
RET_ReallyLR implicit $d0
...
---
@@ -335,23 +337,23 @@ body: |
; CHECK-LABEL: name: and_v16s1
; CHECK: liveins: $q0, $q1, $q2, $q3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[ICMP]], [[ICMP1]]
- ; CHECK-NEXT: $q0 = COPY [[AND]](<16 x s8>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x i8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x i8>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x i8>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x i8>) = COPY $q3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x i8>) = G_ICMP intpred(eq), [[COPY]](<16 x i8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x i8>) = G_ICMP intpred(eq), [[COPY2]](<16 x i8>), [[COPY3]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x i8>) = G_AND [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $q0 = COPY [[AND]](<16 x i8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:_(<16 x s8>) = COPY $q0
- %1:_(<16 x s8>) = COPY $q1
- %2:_(<16 x s8>) = COPY $q2
- %3:_(<16 x s8>) = COPY $q3
- %4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
- %5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
- %6:_(<16 x s1>) = G_AND %4, %5
- %7:_(<16 x s8>) = G_ANYEXT %6
- $q0 = COPY %7:_(<16 x s8>)
+ %0:_(<16 x i8>) = COPY $q0
+ %1:_(<16 x i8>) = COPY $q1
+ %2:_(<16 x i8>) = COPY $q2
+ %3:_(<16 x i8>) = COPY $q3
+ %4:_(<16 x i1>) = G_ICMP intpred(eq), %0(<16 x i8>), %1
+ %5:_(<16 x i1>) = G_ICMP intpred(eq), %2(<16 x i8>), %3
+ %6:_(<16 x i1>) = G_AND %4, %5
+ %7:_(<16 x i8>) = G_ANYEXT %6
+ $q0 = COPY %7:_(<16 x i8>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitreverse.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitreverse.mir
index dfd4dd8a43544..f973614752033 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitreverse.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitreverse.mir
@@ -152,9 +152,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<4 x s16>) = COPY $d0
; CHECK-NEXT: [[BSWAP:%[0-9]+]]:_(<4 x s16>) = G_BSWAP %vec
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[BSWAP]](<4 x s16>)
- ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(<8 x s8>) = G_BITREVERSE [[BITCAST]]
- ; CHECK-NEXT: %bitreverse:_(<4 x s16>) = G_BITCAST [[BITREVERSE]](<8 x s8>)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[BSWAP]](<4 x s16>)
+ ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(<8 x i8>) = G_BITREVERSE [[BITCAST]]
+ ; CHECK-NEXT: %bitreverse:_(<4 x s16>) = G_BITCAST [[BITREVERSE]](<8 x i8>)
; CHECK-NEXT: $d0 = COPY %bitreverse(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%vec:_(<4 x s16>) = COPY $d0
@@ -173,9 +173,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: [[BSWAP:%[0-9]+]]:_(<2 x s32>) = G_BSWAP %vec
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[BSWAP]](<2 x s32>)
- ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(<8 x s8>) = G_BITREVERSE [[BITCAST]]
- ; CHECK-NEXT: %bitreverse:_(<2 x s32>) = G_BITCAST [[BITREVERSE]](<8 x s8>)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x i8>) = G_BITCAST [[BSWAP]](<2 x s32>)
+ ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(<8 x i8>) = G_BITREVERSE [[BITCAST]]
+ ; CHECK-NEXT: %bitreverse:_(<2 x s32>) = G_BITCAST [[BITREVERSE]](<8 x i8>)
; CHECK-NEXT: $d0 = COPY %bitreverse(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%vec:_(<2 x s32>) = COPY $d0
@@ -194,9 +194,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[BSWAP:%[0-9]+]]:_(<2 x s64>) = G_BSWAP %vec
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[BSWAP]](<2 x s64>)
- ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(<16 x s8>) = G_BITREVERSE [[BITCAST]]
- ; CHECK-NEXT: %bitreverse:_(<2 x s64>) = G_BITCAST [[BITREVERSE]](<16 x s8>)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[BSWAP]](<2 x s64>)
+ ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(<16 x i8>) = G_BITREVERSE [[BITCAST]]
+ ; CHECK-NEXT: %bitreverse:_(<2 x s64>) = G_BITCAST [[BITREVERSE]](<16 x i8>)
; CHECK-NEXT: $q0 = COPY %bitreverse(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%vec:_(<2 x s64>) = COPY $q0
@@ -215,9 +215,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[BSWAP:%[0-9]+]]:_(<4 x s32>) = G_BSWAP %vec
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[BSWAP]](<4 x s32>)
- ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(<16 x s8>) = G_BITREVERSE [[BITCAST]]
- ; CHECK-NEXT: %bitreverse:_(<4 x s32>) = G_BITCAST [[BITREVERSE]](<16 x s8>)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[BSWAP]](<4 x s32>)
+ ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(<16 x i8>) = G_BITREVERSE [[BITCAST]]
+ ; CHECK-NEXT: %bitreverse:_(<4 x s32>) = G_BITCAST [[BITREVERSE]](<16 x i8>)
; CHECK-NEXT: $q0 = COPY %bitreverse(<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%vec:_(<4 x s32>) = COPY $q0
@@ -236,9 +236,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %vec:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[BSWAP:%[0-9]+]]:_(<8 x s16>) = G_BSWAP %vec
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s8>) = G_BITCAST [[BSWAP]](<8 x s16>)
- ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(<16 x s8>) = G_BITREVERSE [[BITCAST]]
- ; CHECK-NEXT: %bitreverse:_(<8 x s16>) = G_BITCAST [[BITREVERSE]](<16 x s8>)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x i8>) = G_BITCAST [[BSWAP]](<8 x s16>)
+ ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(<16 x i8>) = G_BITREVERSE [[BITCAST]]
+ ; CHECK-NEXT: %bitreverse:_(<8 x s16>) = G_BITCAST [[BITREVERSE]](<16 x i8>)
; CHECK-NEXT: $q0 = COPY %bitreverse(<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%vec:_(<8 x s16>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
index c220e14177bc9..8fda9a44f6382 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
@@ -192,18 +192,18 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<2 x s64>) = G_LSHR [[BSWAP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LSHR]](<2 x s64>)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i64) = G_LSHR [[UV]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[UV]](s64), [[COPY]](p0) :: (store (s32), align 16)
- ; CHECK-NEXT: G_STORE [[LSHR1]](s64), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4, align 4)
+ ; CHECK-NEXT: G_STORE [[LSHR1]](i64), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4, align 4)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](i64)
- ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C1]](s64)
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](s64)
+ ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(i64) = G_LSHR [[UV1]], [[C1]](i64)
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[UV1]](s64), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 6, align 2)
- ; CHECK-NEXT: G_STORE [[LSHR2]](s64), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 10)
+ ; CHECK-NEXT: G_STORE [[LSHR2]](i64), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 10)
; CHECK-NEXT: RET_ReallyLR
%1:_(p0) = COPY $x8
%2:_(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
index ba7b3b426fce4..ab9ab56e9697b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
@@ -89,26 +89,26 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1234
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C2]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C2]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C2]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C2]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C3]]
- ; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 4611686018427387903
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[C]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[C1]], [[C2]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[C1]], [[C2]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[C1]], [[C2]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i64) = G_AND [[C1]], [[C3]]
+ ; CHECK-NEXT: G_STORE [[AND]](i64), %ptr(p0) :: (store (i64), align 64)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[AND1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
- ; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
+ ; CHECK-NEXT: G_STORE [[AND2]](i64), [[PTR_ADD1]](p0) :: (store (i64) into unknown-address + 16, align 16)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C6]](i64)
- ; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
+ ; CHECK-NEXT: G_STORE [[AND3]](i64), [[PTR_ADD2]](p0) :: (store (i64) into unknown-address + 24)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C7]](i64)
- ; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
+ ; CHECK-NEXT: G_STORE [[AND4]](i64), [[PTR_ADD3]](p0) :: (store (i64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%cst:_(s318) = G_CONSTANT i318 1234
%ptr:_(p0) = COPY $x0
@@ -127,21 +127,21 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1234
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1073741823
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C2]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C2]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C3]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[AND2]](s64), 0
- ; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 1073741823
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[C]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[C1]], [[C2]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[C1]], [[C3]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY [[AND]](i64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[AND1]](i64)
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(i32) = G_EXTRACT [[AND2]](i64), 0
+ ; CHECK-NEXT: G_STORE [[COPY]](i64), %ptr(p0) :: (store (i64), align 32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[COPY1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
- ; CHECK-NEXT: G_STORE [[EXTRACT]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 16, align 16)
+ ; CHECK-NEXT: G_STORE [[EXTRACT]](i32), [[PTR_ADD1]](p0) :: (store (i32) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%cst:_(s158) = G_CONSTANT i158 1234
%ptr:_(p0) = COPY $x0
@@ -161,21 +161,21 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1234
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16383
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C2]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C2]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[C1]], [[C3]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[AND2]](s64), 0
- ; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16383
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[C]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[C1]], [[C2]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[C1]], [[C3]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY [[AND]](i64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[AND1]](i64)
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(i16) = G_EXTRACT [[AND2]](i64), 0
+ ; CHECK-NEXT: G_STORE [[COPY]](i64), %ptr(p0) :: (store (i64), align 32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[COPY1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
- ; CHECK-NEXT: G_STORE [[EXTRACT]](s16), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 16, align 16)
+ ; CHECK-NEXT: G_STORE [[EXTRACT]](i16), [[PTR_ADD1]](p0) :: (store (i16) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%cst:_(s142) = G_CONSTANT i142 1234
%ptr:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
index 33d5a58d11888..954adcf98d38a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
@@ -288,17 +288,17 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s64), [[C2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(eq), [[AND1]](s64), [[C2]]
; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[AND]](s64)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[CTLZ]], [[C3]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[C2]], [[C2]], [[UADDO1]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[CTLZ]], [[C3]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[C2]], [[C2]], [[UADDO1]]
; CHECK-NEXT: [[CTLZ1:%[0-9]+]]:_(s64) = G_CTLZ [[AND1]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO]], [[CTLZ1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDE]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[UADDO]], [[CTLZ1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[UADDE]], [[C2]]
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
- ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[SELECT]], [[C4]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[SELECT1]], [[C2]], [[USUBO1]]
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(i32) = G_USUBO [[SELECT]], [[C4]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(i32) = G_USUBE [[SELECT1]], [[C2]], [[USUBO1]]
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
index e4490d3a82e8d..19eb5a359ecae 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
@@ -141,8 +141,8 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[UADDLV]](<4 x i32>), [[C]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[EVEC]](i32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](i32), [[C1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](i32), [[C1]](i32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: $x0 = COPY [[MV1]](s64)
; CHECK-NEXT: $x1 = COPY [[C2]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
index e35b6a790eb54..7a9e59d509454 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
@@ -229,8 +229,8 @@ body: |
; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE [[OR1]]
; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE]](s64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[CTLZ]], [[C2]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[C]], [[C]], [[UADDO1]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[CTLZ]], [[C2]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[C]], [[C]], [[UADDO1]]
; CHECK-NEXT: [[BITREVERSE1:%[0-9]+]]:_(s64) = G_BITREVERSE [[OR]]
; CHECK-NEXT: [[CTLZ1:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE1]](s64)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO]], [[CTLZ1]]
@@ -251,8 +251,8 @@ body: |
; CHECK-CSSC-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C]]
; CHECK-CSSC-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[OR1]](s64)
; CHECK-CSSC-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-CSSC-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[CTTZ]], [[C2]]
- ; CHECK-CSSC-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[C]], [[C]], [[UADDO1]]
+ ; CHECK-CSSC-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[CTTZ]], [[C2]]
+ ; CHECK-CSSC-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[C]], [[C]], [[UADDO1]]
; CHECK-CSSC-NEXT: [[CTTZ1:%[0-9]+]]:_(s64) = G_CTTZ [[OR]](s64)
; CHECK-CSSC-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO]], [[CTTZ1]]
; CHECK-CSSC-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDE]], [[C]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir
index a1eb45e1b7991..2ec918b281914 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir
@@ -62,9 +62,9 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i64) = G_SUB [[PTRTOINT]], [[AND]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](i64)
; CHECK-NEXT: $sp = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
@@ -109,11 +109,11 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -32
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND1]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i64) = G_SUB [[PTRTOINT]], [[AND]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 -32
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[SUB]], [[C3]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND1]](i64)
; CHECK-NEXT: $sp = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
@@ -158,9 +158,9 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i64) = G_SUB [[PTRTOINT]], [[AND]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](i64)
; CHECK-NEXT: $sp = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
@@ -205,9 +205,9 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr64common(p0) = G_INTTOPTR [[SUB]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i64) = G_SUB [[PTRTOINT]], [[AND]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr64common(p0) = G_INTTOPTR [[SUB]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: PROBED_STACKALLOC_DYN [[INTTOPTR]](p0), implicit-def $sp, implicit-def $nzcv, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
@@ -252,11 +252,11 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -32
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr64common(p0) = G_INTTOPTR [[AND1]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i64) = G_SUB [[PTRTOINT]], [[AND]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 -32
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[SUB]], [[C3]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr64common(p0) = G_INTTOPTR [[AND1]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: PROBED_STACKALLOC_DYN [[INTTOPTR]](p0), implicit-def $sp, implicit-def $nzcv, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
@@ -301,9 +301,9 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr64common(p0) = G_INTTOPTR [[SUB]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY1]](p0)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i64) = G_SUB [[PTRTOINT]], [[AND]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr64common(p0) = G_INTTOPTR [[SUB]](i64)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: PROBED_STACKALLOC_DYN [[INTTOPTR]](p0), implicit-def $sp, implicit-def $nzcv, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
index fe0d46d47debd..e238582092b22 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
@@ -298,8 +298,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[COPY]](<2 x p0>)
- ; CHECK-NEXT: G_STORE [[BITCAST]](<2 x s64>), [[FRAME_INDEX]](p0) :: (store (<2 x s64>) into %stack.0)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY]](<2 x p0>)
+ ; CHECK-NEXT: G_STORE [[BITCAST]](<2 x i64>), [[FRAME_INDEX]](p0) :: (store (<2 x i64>) into %stack.0)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -492,12 +492,12 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x p0>) = G_IMPLICIT_DEF
; CHECK-NEXT: %idx:_(s64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<2 x p0>)
- ; CHECK-NEXT: G_STORE [[BITCAST]](<2 x s64>), [[FRAME_INDEX]](p0) :: (store (<2 x s64>) into %stack.0, align 32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[DEF]](<2 x p0>)
+ ; CHECK-NEXT: G_STORE [[BITCAST]](<2 x i64>), [[FRAME_INDEX]](p0) :: (store (<2 x i64>) into %stack.0, align 32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](i64)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<2 x p0>)
- ; CHECK-NEXT: G_STORE [[BITCAST1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %stack.0 + 16, basealign 32)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[DEF]](<2 x p0>)
+ ; CHECK-NEXT: G_STORE [[BITCAST1]](<2 x i64>), [[PTR_ADD]](p0) :: (store (<2 x i64>) into %stack.0 + 16, basealign 32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %idx, [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-class.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-class.mir
index bd9dc83fae59f..0cea2eda3cb00 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-class.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-class.mir
@@ -8,11 +8,11 @@ body: |
bb.0:
; CHECK-LABEL: name: isnan_32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2139095040
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[C1]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2139095040
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](i32), [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[ICMP]]
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
@@ -28,13 +28,13 @@ body: |
bb.0:
; CHECK-LABEL: name: isnormal_32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8388608
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2130706432
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 8388608
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[AND]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2130706432
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](i32), [[C2]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C3]], [[ICMP]]
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
@@ -50,13 +50,13 @@ body: |
bb.0:
; CHECK-LABEL: name: iszero_32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C1]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[ICMP]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](i32), [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[ICMP]]
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = nofpexcept G_IS_FPCLASS %0(s32), 96
@@ -70,11 +70,11 @@ body: |
bb.0:
; CHECK-LABEL: name: iszero_64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s64), [[C1]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](i64), [[C1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[ICMP]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir
index 936f839280c4d..dd0e569b0e498 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir
@@ -49,8 +49,8 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: func_reset
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
+ ; CHECK: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: TCRETURNdi &fesetenv, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0
G_RESET_FPENV
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpmode.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpmode.mir
index 2d72e5f55d983..97c0ffb642e21 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpmode.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpmode.mir
@@ -77,8 +77,8 @@ tracksRegLiveness: true
body: |
bb.1.entry:
; CHECK-LABEL: name: func_reset
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
+ ; CHECK: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[INTTOPTR]](p0)
; CHECK-NEXT: TCRETURNdi &fesetmode, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0
G_RESET_FPMODE
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
index 1e549fa9a833a..a7f1cb0da58b6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
@@ -379,8 +379,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
- ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 23
+ ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](i64)
; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -405,8 +405,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 22
- ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 22
+ ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](i64)
; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -462,8 +462,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
- ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 23
+ ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -488,8 +488,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
- ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 56
+ ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
index 9a9e5bb42c64f..388e92a60100a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
@@ -377,8 +377,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 9
- ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 9
+ ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](i64)
; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -403,8 +403,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
- ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 10
+ ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](i64)
; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -475,8 +475,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](i64)
; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
index eb9c3ff60c704..643e2d32f2582 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
@@ -37,10 +37,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](i32), [[UV1]](i32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s32), [[DEF]](i32)
; CHECK-NEXT: $x0 = COPY [[MV]](s64)
; CHECK-NEXT: $x1 = COPY [[MV1]](s64)
%0:_(s64) = COPY $x0
@@ -99,165 +99,174 @@ body: |
; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C7]](s64)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[OR6]](s32)
- ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C1]](s64)
- ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL7]]
- ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s64)
- ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C3]](s64)
- ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
- ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C4]](s64)
- ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C5]](s64)
- ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C6]](s64)
- ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
- ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C7]](s64)
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND8]], [[C9]](i64)
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[AND9]], [[SHL7]]
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(i32) = G_SHL [[AND10]], [[C10]](i64)
+ ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(i32) = G_OR [[OR7]], [[SHL8]]
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(i32) = G_SHL [[AND11]], [[C11]](i64)
+ ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(i32) = G_OR [[OR8]], [[SHL9]]
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(i32) = G_SHL [[AND12]], [[C12]](i64)
+ ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(i32) = G_OR [[OR9]], [[SHL10]]
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(i32) = G_SHL [[AND13]], [[C13]](i64)
+ ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(i32) = G_OR [[OR10]], [[SHL11]]
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(i32) = G_SHL [[AND14]], [[C14]](i64)
+ ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(i32) = G_OR [[OR11]], [[SHL12]]
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(i32) = G_SHL [[AND15]], [[C15]](i64)
; CHECK-NEXT: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR13]](s32)
- ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C1]](s64)
- ; CHECK-NEXT: [[AND17:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL14]]
- ; CHECK-NEXT: [[AND18:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C2]](s64)
- ; CHECK-NEXT: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
- ; CHECK-NEXT: [[AND19:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C3]](s64)
- ; CHECK-NEXT: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CHECK-NEXT: [[AND20:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C4]](s64)
- ; CHECK-NEXT: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; CHECK-NEXT: [[AND21:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C5]](s64)
- ; CHECK-NEXT: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
- ; CHECK-NEXT: [[AND22:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C6]](s64)
- ; CHECK-NEXT: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; CHECK-NEXT: [[AND23:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C7]](s64)
+ ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(i32) = G_SHL [[AND16]], [[C9]](i64)
+ ; CHECK-NEXT: [[AND17:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[OR14:%[0-9]+]]:_(i32) = G_OR [[AND17]], [[SHL14]]
+ ; CHECK-NEXT: [[AND18:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(i32) = G_SHL [[AND18]], [[C10]](i64)
+ ; CHECK-NEXT: [[OR15:%[0-9]+]]:_(i32) = G_OR [[OR14]], [[SHL15]]
+ ; CHECK-NEXT: [[AND19:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(i32) = G_SHL [[AND19]], [[C11]](i64)
+ ; CHECK-NEXT: [[OR16:%[0-9]+]]:_(i32) = G_OR [[OR15]], [[SHL16]]
+ ; CHECK-NEXT: [[AND20:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(i32) = G_SHL [[AND20]], [[C12]](i64)
+ ; CHECK-NEXT: [[OR17:%[0-9]+]]:_(i32) = G_OR [[OR16]], [[SHL17]]
+ ; CHECK-NEXT: [[AND21:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(i32) = G_SHL [[AND21]], [[C13]](i64)
+ ; CHECK-NEXT: [[OR18:%[0-9]+]]:_(i32) = G_OR [[OR17]], [[SHL18]]
+ ; CHECK-NEXT: [[AND22:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(i32) = G_SHL [[AND22]], [[C14]](i64)
+ ; CHECK-NEXT: [[OR19:%[0-9]+]]:_(i32) = G_OR [[OR18]], [[SHL19]]
+ ; CHECK-NEXT: [[AND23:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(i32) = G_SHL [[AND23]], [[C15]](i64)
; CHECK-NEXT: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR20]](s32)
- ; CHECK-NEXT: [[AND24:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C1]](s64)
- ; CHECK-NEXT: [[AND25:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL21]]
- ; CHECK-NEXT: [[AND26:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C2]](s64)
- ; CHECK-NEXT: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; CHECK-NEXT: [[AND27:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C3]](s64)
- ; CHECK-NEXT: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
- ; CHECK-NEXT: [[AND28:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C4]](s64)
- ; CHECK-NEXT: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
- ; CHECK-NEXT: [[AND29:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C5]](s64)
- ; CHECK-NEXT: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
- ; CHECK-NEXT: [[AND30:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C6]](s64)
- ; CHECK-NEXT: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
- ; CHECK-NEXT: [[AND31:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C7]](s64)
+ ; CHECK-NEXT: [[AND24:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(i32) = G_SHL [[AND24]], [[C9]](i64)
+ ; CHECK-NEXT: [[AND25:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[OR21:%[0-9]+]]:_(i32) = G_OR [[AND25]], [[SHL21]]
+ ; CHECK-NEXT: [[AND26:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(i32) = G_SHL [[AND26]], [[C10]](i64)
+ ; CHECK-NEXT: [[OR22:%[0-9]+]]:_(i32) = G_OR [[OR21]], [[SHL22]]
+ ; CHECK-NEXT: [[AND27:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(i32) = G_SHL [[AND27]], [[C11]](i64)
+ ; CHECK-NEXT: [[OR23:%[0-9]+]]:_(i32) = G_OR [[OR22]], [[SHL23]]
+ ; CHECK-NEXT: [[AND28:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(i32) = G_SHL [[AND28]], [[C12]](i64)
+ ; CHECK-NEXT: [[OR24:%[0-9]+]]:_(i32) = G_OR [[OR23]], [[SHL24]]
+ ; CHECK-NEXT: [[AND29:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(i32) = G_SHL [[AND29]], [[C13]](i64)
+ ; CHECK-NEXT: [[OR25:%[0-9]+]]:_(i32) = G_OR [[OR24]], [[SHL25]]
+ ; CHECK-NEXT: [[AND30:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(i32) = G_SHL [[AND30]], [[C14]](i64)
+ ; CHECK-NEXT: [[OR26:%[0-9]+]]:_(i32) = G_OR [[OR25]], [[SHL26]]
+ ; CHECK-NEXT: [[AND31:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(i32) = G_SHL [[AND31]], [[C15]](i64)
; CHECK-NEXT: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[OR27]](s32)
- ; CHECK-NEXT: [[AND32:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C1]](s64)
- ; CHECK-NEXT: [[AND33:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[OR28:%[0-9]+]]:_(s32) = G_OR [[AND33]], [[SHL28]]
- ; CHECK-NEXT: [[AND34:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C2]](s64)
- ; CHECK-NEXT: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
- ; CHECK-NEXT: [[AND35:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C3]](s64)
- ; CHECK-NEXT: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
- ; CHECK-NEXT: [[AND36:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C4]](s64)
- ; CHECK-NEXT: [[OR31:%[0-9]+]]:_(s32) = G_OR [[OR30]], [[SHL31]]
- ; CHECK-NEXT: [[AND37:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C5]](s64)
- ; CHECK-NEXT: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]]
- ; CHECK-NEXT: [[AND38:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C6]](s64)
- ; CHECK-NEXT: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]]
- ; CHECK-NEXT: [[AND39:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C7]](s64)
+ ; CHECK-NEXT: [[AND32:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(i32) = G_SHL [[AND32]], [[C9]](i64)
+ ; CHECK-NEXT: [[AND33:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[OR28:%[0-9]+]]:_(i32) = G_OR [[AND33]], [[SHL28]]
+ ; CHECK-NEXT: [[AND34:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(i32) = G_SHL [[AND34]], [[C10]](i64)
+ ; CHECK-NEXT: [[OR29:%[0-9]+]]:_(i32) = G_OR [[OR28]], [[SHL29]]
+ ; CHECK-NEXT: [[AND35:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(i32) = G_SHL [[AND35]], [[C11]](i64)
+ ; CHECK-NEXT: [[OR30:%[0-9]+]]:_(i32) = G_OR [[OR29]], [[SHL30]]
+ ; CHECK-NEXT: [[AND36:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL31:%[0-9]+]]:_(i32) = G_SHL [[AND36]], [[C12]](i64)
+ ; CHECK-NEXT: [[OR31:%[0-9]+]]:_(i32) = G_OR [[OR30]], [[SHL31]]
+ ; CHECK-NEXT: [[AND37:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL32:%[0-9]+]]:_(i32) = G_SHL [[AND37]], [[C13]](i64)
+ ; CHECK-NEXT: [[OR32:%[0-9]+]]:_(i32) = G_OR [[OR31]], [[SHL32]]
+ ; CHECK-NEXT: [[AND38:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL33:%[0-9]+]]:_(i32) = G_SHL [[AND38]], [[C14]](i64)
+ ; CHECK-NEXT: [[OR33:%[0-9]+]]:_(i32) = G_OR [[OR32]], [[SHL33]]
+ ; CHECK-NEXT: [[AND39:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL34:%[0-9]+]]:_(i32) = G_SHL [[AND39]], [[C15]](i64)
; CHECK-NEXT: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]]
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[OR34]](s32)
- ; CHECK-NEXT: [[AND40:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[C1]](s64)
- ; CHECK-NEXT: [[AND41:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[OR35:%[0-9]+]]:_(s32) = G_OR [[AND41]], [[SHL35]]
- ; CHECK-NEXT: [[AND42:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[C2]](s64)
- ; CHECK-NEXT: [[OR36:%[0-9]+]]:_(s32) = G_OR [[OR35]], [[SHL36]]
- ; CHECK-NEXT: [[AND43:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[C3]](s64)
- ; CHECK-NEXT: [[OR37:%[0-9]+]]:_(s32) = G_OR [[OR36]], [[SHL37]]
- ; CHECK-NEXT: [[AND44:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[C4]](s64)
- ; CHECK-NEXT: [[OR38:%[0-9]+]]:_(s32) = G_OR [[OR37]], [[SHL38]]
- ; CHECK-NEXT: [[AND45:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[C5]](s64)
- ; CHECK-NEXT: [[OR39:%[0-9]+]]:_(s32) = G_OR [[OR38]], [[SHL39]]
- ; CHECK-NEXT: [[AND46:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[AND46]], [[C6]](s64)
- ; CHECK-NEXT: [[OR40:%[0-9]+]]:_(s32) = G_OR [[OR39]], [[SHL40]]
- ; CHECK-NEXT: [[AND47:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[C7]](s64)
+ ; CHECK-NEXT: [[AND40:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL35:%[0-9]+]]:_(i32) = G_SHL [[AND40]], [[C9]](i64)
+ ; CHECK-NEXT: [[AND41:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[OR35:%[0-9]+]]:_(i32) = G_OR [[AND41]], [[SHL35]]
+ ; CHECK-NEXT: [[AND42:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL36:%[0-9]+]]:_(i32) = G_SHL [[AND42]], [[C10]](i64)
+ ; CHECK-NEXT: [[OR36:%[0-9]+]]:_(i32) = G_OR [[OR35]], [[SHL36]]
+ ; CHECK-NEXT: [[AND43:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL37:%[0-9]+]]:_(i32) = G_SHL [[AND43]], [[C11]](i64)
+ ; CHECK-NEXT: [[OR37:%[0-9]+]]:_(i32) = G_OR [[OR36]], [[SHL37]]
+ ; CHECK-NEXT: [[AND44:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL38:%[0-9]+]]:_(i32) = G_SHL [[AND44]], [[C12]](i64)
+ ; CHECK-NEXT: [[OR38:%[0-9]+]]:_(i32) = G_OR [[OR37]], [[SHL38]]
+ ; CHECK-NEXT: [[AND45:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL39:%[0-9]+]]:_(i32) = G_SHL [[AND45]], [[C13]](i64)
+ ; CHECK-NEXT: [[OR39:%[0-9]+]]:_(i32) = G_OR [[OR38]], [[SHL39]]
+ ; CHECK-NEXT: [[AND46:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL40:%[0-9]+]]:_(i32) = G_SHL [[AND46]], [[C14]](i64)
+ ; CHECK-NEXT: [[OR40:%[0-9]+]]:_(i32) = G_OR [[OR39]], [[SHL40]]
+ ; CHECK-NEXT: [[AND47:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL41:%[0-9]+]]:_(i32) = G_SHL [[AND47]], [[C15]](i64)
; CHECK-NEXT: [[OR41:%[0-9]+]]:_(s32) = G_OR [[OR40]], [[SHL41]]
; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[OR41]](s32)
- ; CHECK-NEXT: [[AND48:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C1]](s64)
- ; CHECK-NEXT: [[AND49:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[OR42:%[0-9]+]]:_(s32) = G_OR [[AND49]], [[SHL42]]
- ; CHECK-NEXT: [[AND50:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C2]](s64)
- ; CHECK-NEXT: [[OR43:%[0-9]+]]:_(s32) = G_OR [[OR42]], [[SHL43]]
- ; CHECK-NEXT: [[AND51:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[C3]](s64)
- ; CHECK-NEXT: [[OR44:%[0-9]+]]:_(s32) = G_OR [[OR43]], [[SHL44]]
- ; CHECK-NEXT: [[AND52:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[C4]](s64)
- ; CHECK-NEXT: [[OR45:%[0-9]+]]:_(s32) = G_OR [[OR44]], [[SHL45]]
- ; CHECK-NEXT: [[AND53:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C5]](s64)
- ; CHECK-NEXT: [[OR46:%[0-9]+]]:_(s32) = G_OR [[OR45]], [[SHL46]]
- ; CHECK-NEXT: [[AND54:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[C6]](s64)
- ; CHECK-NEXT: [[OR47:%[0-9]+]]:_(s32) = G_OR [[OR46]], [[SHL47]]
- ; CHECK-NEXT: [[AND55:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C7]](s64)
+ ; CHECK-NEXT: [[AND48:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL42:%[0-9]+]]:_(i32) = G_SHL [[AND48]], [[C9]](i64)
+ ; CHECK-NEXT: [[AND49:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[OR42:%[0-9]+]]:_(i32) = G_OR [[AND49]], [[SHL42]]
+ ; CHECK-NEXT: [[AND50:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL43:%[0-9]+]]:_(i32) = G_SHL [[AND50]], [[C10]](i64)
+ ; CHECK-NEXT: [[OR43:%[0-9]+]]:_(i32) = G_OR [[OR42]], [[SHL43]]
+ ; CHECK-NEXT: [[AND51:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL44:%[0-9]+]]:_(i32) = G_SHL [[AND51]], [[C11]](i64)
+ ; CHECK-NEXT: [[OR44:%[0-9]+]]:_(i32) = G_OR [[OR43]], [[SHL44]]
+ ; CHECK-NEXT: [[AND52:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL45:%[0-9]+]]:_(i32) = G_SHL [[AND52]], [[C12]](i64)
+ ; CHECK-NEXT: [[OR45:%[0-9]+]]:_(i32) = G_OR [[OR44]], [[SHL45]]
+ ; CHECK-NEXT: [[AND53:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL46:%[0-9]+]]:_(i32) = G_SHL [[AND53]], [[C13]](i64)
+ ; CHECK-NEXT: [[OR46:%[0-9]+]]:_(i32) = G_OR [[OR45]], [[SHL46]]
+ ; CHECK-NEXT: [[AND54:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL47:%[0-9]+]]:_(i32) = G_SHL [[AND54]], [[C14]](i64)
+ ; CHECK-NEXT: [[OR47:%[0-9]+]]:_(i32) = G_OR [[OR46]], [[SHL47]]
+ ; CHECK-NEXT: [[AND55:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL48:%[0-9]+]]:_(i32) = G_SHL [[AND55]], [[C15]](i64)
; CHECK-NEXT: [[OR48:%[0-9]+]]:_(s32) = G_OR [[OR47]], [[SHL48]]
; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[OR48]](s32)
- ; CHECK-NEXT: [[AND56:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C1]](s64)
- ; CHECK-NEXT: [[AND57:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[OR49:%[0-9]+]]:_(s32) = G_OR [[AND57]], [[SHL49]]
- ; CHECK-NEXT: [[AND58:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C2]](s64)
- ; CHECK-NEXT: [[OR50:%[0-9]+]]:_(s32) = G_OR [[OR49]], [[SHL50]]
- ; CHECK-NEXT: [[AND59:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[C3]](s64)
- ; CHECK-NEXT: [[OR51:%[0-9]+]]:_(s32) = G_OR [[OR50]], [[SHL51]]
- ; CHECK-NEXT: [[AND60:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[C4]](s64)
- ; CHECK-NEXT: [[OR52:%[0-9]+]]:_(s32) = G_OR [[OR51]], [[SHL52]]
- ; CHECK-NEXT: [[AND61:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[C5]](s64)
- ; CHECK-NEXT: [[OR53:%[0-9]+]]:_(s32) = G_OR [[OR52]], [[SHL53]]
- ; CHECK-NEXT: [[AND62:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND62]], [[C6]](s64)
- ; CHECK-NEXT: [[OR54:%[0-9]+]]:_(s32) = G_OR [[OR53]], [[SHL54]]
- ; CHECK-NEXT: [[AND63:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND63]], [[C7]](s64)
+ ; CHECK-NEXT: [[AND56:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL49:%[0-9]+]]:_(i32) = G_SHL [[AND56]], [[C9]](i64)
+ ; CHECK-NEXT: [[AND57:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[OR49:%[0-9]+]]:_(i32) = G_OR [[AND57]], [[SHL49]]
+ ; CHECK-NEXT: [[AND58:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL50:%[0-9]+]]:_(i32) = G_SHL [[AND58]], [[C10]](i64)
+ ; CHECK-NEXT: [[OR50:%[0-9]+]]:_(i32) = G_OR [[OR49]], [[SHL50]]
+ ; CHECK-NEXT: [[AND59:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL51:%[0-9]+]]:_(i32) = G_SHL [[AND59]], [[C11]](i64)
+ ; CHECK-NEXT: [[OR51:%[0-9]+]]:_(i32) = G_OR [[OR50]], [[SHL51]]
+ ; CHECK-NEXT: [[AND60:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL52:%[0-9]+]]:_(i32) = G_SHL [[AND60]], [[C12]](i64)
+ ; CHECK-NEXT: [[OR52:%[0-9]+]]:_(i32) = G_OR [[OR51]], [[SHL52]]
+ ; CHECK-NEXT: [[AND61:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL53:%[0-9]+]]:_(i32) = G_SHL [[AND61]], [[C13]](i64)
+ ; CHECK-NEXT: [[OR53:%[0-9]+]]:_(i32) = G_OR [[OR52]], [[SHL53]]
+ ; CHECK-NEXT: [[AND62:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL54:%[0-9]+]]:_(i32) = G_SHL [[AND62]], [[C14]](i64)
+ ; CHECK-NEXT: [[OR54:%[0-9]+]]:_(i32) = G_OR [[OR53]], [[SHL54]]
+ ; CHECK-NEXT: [[AND63:%[0-9]+]]:_(i32) = G_AND [[DEF1]], [[C8]]
+ ; CHECK-NEXT: [[SHL55:%[0-9]+]]:_(i32) = G_SHL [[AND63]], [[C15]](i64)
; CHECK-NEXT: [[OR55:%[0-9]+]]:_(s32) = G_OR [[OR54]], [[SHL55]]
; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[OR55]](s32)
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8), [[TRUNC8]](s8)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr-debugloc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr-debugloc.mir
index e8b4de0518519..4414a386d6a40 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr-debugloc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr-debugloc.mir
@@ -41,8 +41,8 @@ body: |
; CHECK: liveins: $q0, $x0
; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[COPY]](<2 x p0>), debug-location !DILocation(line: 4, column: 3
- ; CHECK: G_STORE [[BITCAST]](<2 x s64>), [[COPY1]](p0), debug-location !DILocation(line: 4, column: 3
+ ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY]](<2 x p0>), debug-location !DILocation(line: 4, column: 3
+ ; CHECK: G_STORE [[BITCAST]](<2 x i64>), [[COPY1]](p0), debug-location !DILocation(line: 4, column: 3
; CHECK: RET_ReallyLR debug-location !DILocation(line: 5, column: 1
%0:_(<2 x p0>) = COPY $q0
%1:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
index d6a2cd8c04b6e..e3b28263a8a7f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
@@ -32,8 +32,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[COPY]](<2 x p0>)
- ; CHECK-NEXT: G_STORE [[BITCAST]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.ptr)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[COPY]](<2 x p0>)
+ ; CHECK-NEXT: G_STORE [[BITCAST]](<2 x i64>), [[COPY1]](p0) :: (store (<2 x i64>) into %ir.ptr)
; CHECK-NEXT: RET_ReallyLR
%0:_(<2 x p0>) = COPY $q0
%1:_(p0) = COPY $x0
@@ -54,8 +54,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.ptr)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x i64>) = G_LOAD [[COPY]](p0) :: (load (<2 x i64>) from %ir.ptr)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x i64>)
; CHECK-NEXT: $q0 = COPY [[BITCAST]](<2 x p0>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index 92a82ba7bbf2b..ab4ecc5241a26 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -72,7 +72,7 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[AND1]](s32)
- ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (s8))
+ ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (i8))
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: G_STORE [[TRUNC1]](s8), [[COPY]](p0) :: (store (s8))
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
@@ -634,22 +634,24 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 10, align 2)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[DEF]](i32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C3]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[C]], [[LOAD]]
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR]], [[C]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[OR1]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[OR2]](s64)
; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
- ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD2]], [[C2]](s64)
- ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8)
- ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[TRUNC]], [[C5]](i64)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD2]], [[C6]](i64)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8)
+ ; CHECK-NEXT: G_STORE [[LSHR]](i32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%load:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
@@ -711,24 +713,24 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr(p0) :: (load (<2 x s64>), align 64)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x i64>) = G_LOAD %ptr(p0) :: (load (<2 x i64>), align 64)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x i64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x i64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x i64>) from unknown-address + 16)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x i64>)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](i64)
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 32, align 32)
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x s64>)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BITCAST]](<2 x p0>)
- ; CHECK-NEXT: G_STORE [[BITCAST3]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 64)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x i64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x i64>) from unknown-address + 32, align 32)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x i64>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[BITCAST]](<2 x p0>)
+ ; CHECK-NEXT: G_STORE [[BITCAST3]](<2 x i64>), %ptr(p0) :: (store (<2 x i64>), align 64)
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C]](i64)
- ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BITCAST1]](<2 x p0>)
- ; CHECK-NEXT: G_STORE [[BITCAST4]](<2 x s64>), [[PTR_ADD2]](p0) :: (store (<2 x s64>) into unknown-address + 16)
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[BITCAST1]](<2 x p0>)
+ ; CHECK-NEXT: G_STORE [[BITCAST4]](<2 x i64>), [[PTR_ADD2]](p0) :: (store (<2 x i64>) into unknown-address + 16)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C1]](i64)
- ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BITCAST2]](<2 x p0>)
- ; CHECK-NEXT: G_STORE [[BITCAST5]](<2 x s64>), [[PTR_ADD3]](p0) :: (store (<2 x s64>) into unknown-address + 32, align 32)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[BITCAST2]](<2 x p0>)
+ ; CHECK-NEXT: G_STORE [[BITCAST5]](<2 x i64>), [[PTR_ADD3]](p0) :: (store (<2 x i64>) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(<6 x p0>) = G_LOAD %ptr(p0) :: (load (<6 x p0>))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
index 28ecce778c741..49540a9239b54 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
@@ -21,10 +21,12 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C2]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s64)
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[OR]], [[C3]](i64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](i64)
; CHECK-NEXT: G_STORE [[OR]](s32), [[COPY1]](p0) :: (store (s16), align 4)
- ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 2, align 2)
+ ; CHECK-NEXT: G_STORE [[LSHR]](i32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 2, align 2)
; CHECK-NEXT: $w0 = COPY [[C]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
@@ -51,18 +53,18 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[C1]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i64) = G_LSHR [[C]], [[C1]](i64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](i64)
; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s32), align 8)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
- ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4, align 4)
- ; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 6, align 2)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[LSHR]](i64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[TRUNC]], [[C3]](i64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C4]](i64)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](i32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4, align 4)
+ ; CHECK-NEXT: G_STORE [[LSHR1]](i32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 6, align 2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s56) = G_CONSTANT i56 32
@@ -82,26 +84,26 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4611686018427387903
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: G_STORE [[AND]](i64), %ptr(p0) :: (store (i64))
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
- ; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[AND1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
- ; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16)
+ ; CHECK-NEXT: G_STORE [[AND2]](i64), [[PTR_ADD1]](p0) :: (store (i64) into unknown-address + 16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
+ ; CHECK-NEXT: G_STORE [[AND3]](i64), [[PTR_ADD2]](p0) :: (store (i64) into unknown-address + 24)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
- ; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32)
+ ; CHECK-NEXT: G_STORE [[AND4]](i64), [[PTR_ADD3]](p0) :: (store (i64) into unknown-address + 32)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(s318) = G_IMPLICIT_DEF
@@ -120,21 +122,21 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1073741823
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[AND2]](s64), 0
- ; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1073741823
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY [[AND]](i64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[AND1]](i64)
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(i32) = G_EXTRACT [[AND2]](i64), 0
+ ; CHECK-NEXT: G_STORE [[COPY]](i64), %ptr(p0) :: (store (i64))
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
- ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[COPY1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
- ; CHECK-NEXT: G_STORE [[EXTRACT]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 16, align 8)
+ ; CHECK-NEXT: G_STORE [[EXTRACT]](i32), [[PTR_ADD1]](p0) :: (store (i32) into unknown-address + 16, align 8)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(s158) = G_IMPLICIT_DEF
@@ -153,21 +155,21 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16383
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[AND2]](s64), 0
- ; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 16383
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY [[AND]](i64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[AND1]](i64)
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(i16) = G_EXTRACT [[AND2]](i64), 0
+ ; CHECK-NEXT: G_STORE [[COPY]](i64), %ptr(p0) :: (store (i64))
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
- ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[COPY1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
- ; CHECK-NEXT: G_STORE [[EXTRACT]](s16), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 16, align 8)
+ ; CHECK-NEXT: G_STORE [[EXTRACT]](i16), [[PTR_ADD1]](p0) :: (store (i16) into unknown-address + 16, align 8)
; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(s142) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
index a75c22fd74360..c28f91bc266b4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
@@ -75,26 +75,26 @@ body: |
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[C1]]
- ; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4611686018427387903
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[OR]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[OR1]], [[C]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[OR2]], [[C]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[OR3]], [[C]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i64) = G_AND [[OR4]], [[C1]]
+ ; CHECK-NEXT: G_STORE [[AND]](i64), %ptr(p0) :: (store (i64), align 64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
- ; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[AND1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
- ; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
+ ; CHECK-NEXT: G_STORE [[AND2]](i64), [[PTR_ADD1]](p0) :: (store (i64) into unknown-address + 16, align 16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
+ ; CHECK-NEXT: G_STORE [[AND3]](i64), [[PTR_ADD2]](p0) :: (store (i64) into unknown-address + 24)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
- ; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
+ ; CHECK-NEXT: G_STORE [[AND4]](i64), [[PTR_ADD3]](p0) :: (store (i64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
%b:_(s318) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
index 31d30126dd65d..a94d8cf3094f8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -900,12 +900,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr1:_(p0) = COPY $x1
; CHECK-NEXT: %ptr2:_(p0) = COPY $x0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x i64>) = G_LOAD %ptr1(p0) :: (load (<2 x i64>), align 32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x i64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr1, [[C]](i64)
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x i64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x i64>) from unknown-address + 16)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x i64>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C1]]
@@ -915,12 +915,12 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
- ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x s64>)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x i64>) = G_LOAD %ptr2(p0) :: (load (<2 x i64>), align 32)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x i64>)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr2, [[C2]](i64)
- ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
- ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD3]](<2 x s64>)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(<2 x i64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x i64>) from unknown-address + 16)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD3]](<2 x i64>)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<2 x p0>) = G_PHI [[BITCAST2]](<2 x p0>), %bb.1, [[BITCAST]](<2 x p0>), %bb.0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rotr-rotl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rotr-rotl.mir
index 2f0ac5ea76f2b..934755e65b78b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rotr-rotl.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rotr-rotl.mir
@@ -12,8 +12,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
- ; CHECK-NEXT: %rot:_(s32) = G_ROTR [[COPY]], [[ZEXT]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[COPY1]](s32)
+ ; CHECK-NEXT: %rot:_(s32) = G_ROTR [[COPY]], [[ZEXT]](i64)
; CHECK-NEXT: $w0 = COPY %rot(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -59,8 +59,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
- ; CHECK-NEXT: %rot:_(s32) = G_ROTR [[COPY]], [[ZEXT]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[SUB]](s32)
+ ; CHECK-NEXT: %rot:_(s32) = G_ROTR [[COPY]], [[ZEXT]](i64)
; CHECK-NEXT: $w0 = COPY %rot(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
index bbb6fda40dd51..3082c714fd53c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
@@ -11,10 +11,10 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY2]], [[AND]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[COPY]], [[COPY2]], [[AND]]
; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY1]], [[COPY3]], [[UADDE1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
@@ -46,11 +46,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY1]], [[AND]]
- ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[COPY]], [[COPY1]], [[AND]]
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(i32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY2]], [[COPY3]], [[UADDE3]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
index bf0af67e56f87..24f95509b1494 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
@@ -10,7 +10,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[COPY]], [[COPY2]]
; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY1]], [[COPY3]], [[UADDO1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
@@ -39,8 +39,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY2]], [[COPY3]], [[UADDE1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
index 737c66ce90d9c..608f85088e9a5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
@@ -210,23 +210,24 @@ body: |
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_1(s128)
; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT %copy_2(s128), 0
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_2(s128)
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[EXTRACT]], [[EXTRACT1]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[UADDO1]]
- ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 24
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
- ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UADDE]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[DEF]](s8)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[EXTRACT]], [[EXTRACT1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[UV1]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(i32) = G_SEXT_INREG [[TRUNC]], 24
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[UV3]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(i32) = G_SEXT_INREG [[TRUNC1]], 24
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(i32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[UADDO1]]
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(i32) = G_SEXT_INREG [[UADDE]], 24
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](i32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(i8), [[UV5:%[0-9]+]]:_(i8), [[UV6:%[0-9]+]]:_(i8), [[UV7:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[UADDE]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i32) = G_MERGE_VALUES [[UV4]](i8), [[UV5]](i8), [[UV6]](i8), [[DEF]](i8)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i32) = G_MERGE_VALUES [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](i32), [[MV1]](i32)
; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[MV2]], 24
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
- ; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(s64), [[UADDO3:%[0-9]+]]:_(s32) = G_UADDO [[ASHR]], [[C]]
+ ; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(s64), [[UADDO3:%[0-9]+]]:_(i32) = G_UADDO [[ASHR]], [[C]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO2]], [[UADDO]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
index 6705ee0d7f7c5..e3504a329c652 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
@@ -123,16 +123,16 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[SEXT_INREG]](s32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](i64)
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[SHUF]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[BUILD_VECTOR]], [[XOR]]
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](i32), [[C2]](i64)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x i32>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[C3]](i32), [[C3]](i32), [[C3]](i32), [[C3]](i32)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x i32>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x i32>) = G_AND [[COPY1]], [[SHUF]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x i32>) = G_AND [[BUILD_VECTOR]], [[XOR]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY [[OR]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -195,16 +195,16 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[SEXT_INREG]](s32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](i64)
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[SHUF]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[BUILD_VECTOR]], [[XOR]]
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](i32), [[C2]](i64)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x i32>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[C3]](i32), [[C3]](i32), [[C3]](i32), [[C3]](i32)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x i32>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x i32>) = G_AND [[COPY1]], [[SHUF]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x i32>) = G_AND [[BUILD_VECTOR]], [[XOR]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY [[OR]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -242,16 +242,16 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXT_INREG]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[SEXT_INREG]](s32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C2]](i64)
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C3]](s64), [[C3]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[COPY1]], [[SHUF]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[BUILD_VECTOR]], [[XOR]]
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](i64), [[C2]](i64)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x i64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x i64>), [[DEF]], shufflemask(0, 0)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C3]](i64), [[C3]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[COPY1]], [[SHUF]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[BUILD_VECTOR]], [[XOR]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: $q0 = COPY [[OR]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -289,37 +289,37 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4100
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %w0(s32), [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP2]], 1
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x i16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[DEF1]], [[TRUNC]](s16), [[C1]](i64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[IVEC]](<4 x s16>)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s16)
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s16)
- ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s16)
- ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8)
- ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s16)
- ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s16)
- ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s16)
- ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s16)
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8), [[TRUNC8]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8)
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<8 x s8>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<8 x s8>), [[BUILD_VECTOR1]], shufflemask(0, 0, 0, 0, undef, undef, undef, undef)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[SHUF]](<8 x s8>)
- ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<4 x s16>), [[UV5:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x s16>)
- ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[BUILD_VECTOR2]](<8 x s8>)
- ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(<4 x s16>), [[UV7:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT1]](<8 x s16>)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[UV4]], [[UV6]]
- ; CHECK-NEXT: [[TRUNC9:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[SHUF]](<8 x s8>)
- ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(<4 x s16>), [[UV9:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT2]](<8 x s16>)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[TRUNC9]], [[UV8]]
- ; CHECK-NEXT: [[TRUNC10:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s16>) = G_AND [[TRUNC10]], [[XOR]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[SEXT_INREG]](s32)
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i16>) = G_INSERT_VECTOR_ELT [[DEF1]], [[TRUNC]](i16), [[C1]](i64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i16), [[UV1:%[0-9]+]]:_(i16), [[UV2:%[0-9]+]]:_(i16), [[UV3:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[IVEC]](<4 x i16>)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[UV]](i16)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i8) = G_TRUNC [[UV1]](i16)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[UV2]](i16)
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i8) = G_TRUNC [[UV3]](i16)
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[TRUNC1]](i8), [[TRUNC2]](i8), [[TRUNC3]](i8), [[TRUNC4]](i8), [[DEF2]](i8), [[DEF2]](i8), [[DEF2]](i8), [[DEF2]](i8)
+ ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(i8) = G_TRUNC [[DEF]](i16)
+ ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(i8) = G_TRUNC [[DEF]](i16)
+ ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(i8) = G_TRUNC [[DEF]](i16)
+ ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(i8) = G_TRUNC [[DEF]](i16)
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[TRUNC5]](i8), [[TRUNC6]](i8), [[TRUNC7]](i8), [[TRUNC8]](i8), [[DEF2]](i8), [[DEF2]](i8), [[DEF2]](i8), [[DEF2]](i8)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<8 x i8>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<8 x i8>), [[BUILD_VECTOR1]], shufflemask(0, 0, 0, 0, undef, undef, undef, undef)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i8) = G_CONSTANT i8 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x i16>) = G_ANYEXT [[SHUF]](<8 x i8>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<4 x i16>), [[UV5:%[0-9]+]]:_(<4 x i16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x i16>)
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x i8>) = G_BUILD_VECTOR [[C2]](i8), [[C2]](i8), [[C2]](i8), [[C2]](i8), [[DEF2]](i8), [[DEF2]](i8), [[DEF2]](i8), [[DEF2]](i8)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(<8 x i16>) = G_ANYEXT [[BUILD_VECTOR2]](<8 x i8>)
+ ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(<4 x i16>), [[UV7:%[0-9]+]]:_(<4 x i16>) = G_UNMERGE_VALUES [[ANYEXT1]](<8 x i16>)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x i16>) = G_XOR [[UV4]], [[UV6]]
+ ; CHECK-NEXT: [[TRUNC9:%[0-9]+]]:_(<4 x i16>) = G_TRUNC [[ICMP]](<4 x s32>)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(<8 x i16>) = G_ANYEXT [[SHUF]](<8 x i8>)
+ ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(<4 x i16>), [[UV9:%[0-9]+]]:_(<4 x i16>) = G_UNMERGE_VALUES [[ANYEXT2]](<8 x i16>)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x i16>) = G_AND [[TRUNC9]], [[UV8]]
+ ; CHECK-NEXT: [[TRUNC10:%[0-9]+]]:_(<4 x i16>) = G_TRUNC [[ICMP1]](<4 x s32>)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x i16>) = G_AND [[TRUNC10]], [[XOR]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[AND]], [[AND1]]
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[OR]](<4 x s16>)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -360,21 +360,21 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[C]](p0), [[C]](p0)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[C]]
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[COPY1]](<2 x p0>)
- ; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x i64>) = G_PTRTOINT [[COPY1]](<2 x p0>)
+ ; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x i64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXT_INREG]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[SEXT_INREG]](s32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C1]](i64)
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT]], [[SHUF]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT1]], [[XOR]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR]](<2 x s64>)
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](i64), [[C1]](i64)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x i64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x i64>), [[DEF]], shufflemask(0, 0)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C2]](i64), [[C2]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x i64>) = G_AND [[PTRTOINT]], [[SHUF]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[PTRTOINT1]], [[XOR]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i64>) = G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR]](<2 x i64>)
; CHECK-NEXT: $q0 = COPY [[INTTOPTR]](<2 x p0>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
index 54614c13afb58..6dd548db69d94 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
@@ -12,9 +12,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i64) = G_ASHR [[COPY]], [[C]](i64)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](i64)
; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store (s128))
; CHECK-NEXT: RET_ReallyLR
%0:_(s64) = COPY $x0
@@ -59,8 +59,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64)
; CHECK-NEXT: G_STORE [[MV1]](s128), [[COPY1]](p0) :: (store (s128))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
index f1d345ff18f7e..9f316b5125c04 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
@@ -102,16 +102,16 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[TRUNC]], [[C]]
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], [[TRUNC]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[TRUNC]](s64)
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[SUB1]](s64)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[TRUNC]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[SHL]], [[C1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s32), [[UV1]], [[SELECT1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[SHL]], [[C1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[OR]], [[SHL2]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](i32), [[UV1]], [[SELECT1]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; CHECK-NEXT: $q0 = COPY [[MV]](s128)
%0:_(s128) = COPY $q0
@@ -134,16 +134,16 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[TRUNC]], [[C]]
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], [[TRUNC]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[TRUNC]](s64)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[TRUNC]](s64)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s32), [[UV]], [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[OR]], [[LSHR2]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](i32), [[UV]], [[SELECT]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[LSHR]], [[C1]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; CHECK-NEXT: $q0 = COPY [[MV]](s128)
%0:_(s128) = COPY $q0
@@ -166,8 +166,8 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[TRUNC]], [[C]]
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C]], [[TRUNC]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[TRUNC]](s64)
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[TRUNC]](s64)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s64)
@@ -175,9 +175,9 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C2]](s64)
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[OR]], [[ASHR2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s32), [[UV]], [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[ASHR]], [[ASHR1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[OR]], [[ASHR2]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](i32), [[UV]], [[SELECT]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[ASHR]], [[ASHR1]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; CHECK-NEXT: $q0 = COPY [[MV]](s128)
%0:_(s128) = COPY $q0
@@ -473,21 +473,21 @@ body: |
; CHECK-LABEL: name: test_lshr_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: %a:_(s32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), %a(s32)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), [[C]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[C1]]
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C1]], [[COPY]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[C2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[COPY]](s64), [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(eq), [[COPY]](s64), [[C2]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[COPY]](s64)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[SUB1]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[MV1]], [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s32), [[MV]], [[SELECT]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[OR]], [[LSHR1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](i32), [[MV]], [[SELECT]]
; CHECK-NEXT: %d1:_(s32), %d2:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64)
; CHECK-NEXT: $w0 = COPY %d2(s32)
%0:_(s64) = COPY $x0
@@ -505,43 +505,43 @@ body: |
; CHECK-LABEL: name: test_lshr_nonpow2_wide
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: %a:_(s32) = COPY $w1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), %a(s32)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), %a(s32)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), [[C]](s32)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES %a(s32), [[C]](i32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 128
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[C2]]
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C2]], [[COPY]]
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[C2]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[C1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[COPY]](s64), [[C2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(i32) = G_ICMP intpred(eq), [[COPY]](s64), [[C1]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[C3]]
; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s64) = G_SUB [[C3]], [[COPY]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[C3]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[C1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[COPY]](s64), [[C3]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(i32) = G_ICMP intpred(eq), [[COPY]](s64), [[C1]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[COPY]](s64)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[SUB3]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[MV1]], [[SUB2]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s32), [[OR]], [[LSHR1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s32), [[MV]], [[SELECT]]
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s64), [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](i32), [[OR]], [[LSHR1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](i32), [[MV]], [[SELECT]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[SUB1]](s64), [[C3]]
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV2]], [[SUB1]](s64)
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s32), [[SHL1]], [[C1]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](i32), [[SHL1]], [[C1]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[C3]]
; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C3]], [[SUB]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s64), [[C3]]
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB]](s64), [[C1]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(i32) = G_ICMP intpred(ult), [[SUB]](s64), [[C3]]
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(i32) = G_ICMP intpred(eq), [[SUB]](s64), [[C1]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[MV2]], [[SUB]](s64)
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[C1]], [[SUB5]](s64)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[SHL2]]
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[C1]], [[SUB4]](s64)
- ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s32), [[OR2]], [[LSHR3]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s32), [[MV2]], [[SELECT3]]
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[OR1]], [[SELECT4]]
- ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s32), [[MV]], [[SELECT5]]
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](i32), [[OR2]], [[LSHR3]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](i32), [[MV2]], [[SELECT3]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](i32), [[OR1]], [[SELECT4]]
+ ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](i32), [[MV]], [[SELECT5]]
; CHECK-NEXT: %d1:_(s32), %d2:_(s32) = G_UNMERGE_VALUES [[SELECT6]](s64)
; CHECK-NEXT: $w0 = COPY %d2(s32)
%0:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
index 364df8a7c8cc9..f9746712994c5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
@@ -59,10 +59,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $q1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[COPY]](<2 x p0>)
- ; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[COPY1]](<2 x p0>)
- ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[PTRTOINT]](<2 x s64>), [[PTRTOINT1]], shufflemask(0, 0)
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[SHUF]](<2 x s64>)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x i64>) = G_PTRTOINT [[COPY]](<2 x p0>)
+ ; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x i64>) = G_PTRTOINT [[COPY1]](<2 x p0>)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x i64>) = G_SHUFFLE_VECTOR [[PTRTOINT]](<2 x i64>), [[PTRTOINT1]], shufflemask(0, 0)
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[SHUF]](<2 x i64>)
; CHECK-NEXT: $q0 = COPY [[INTTOPTR]](<2 x p0>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x p0>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
index e7d1f8e7a50f9..54255dcc0b85b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
@@ -11,10 +11,10 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY2]], [[AND]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(i32) = G_USUBE [[COPY]], [[COPY2]], [[AND]]
; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY1]], [[COPY3]], [[USUBE1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
@@ -46,11 +46,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY1]], [[AND]]
- ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(i32) = G_USUBE [[COPY]], [[COPY1]], [[AND]]
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(i32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY2]], [[COPY3]], [[USUBE3]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
index 5e8d96a4b6d68..db8ebf7ae85fa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
@@ -10,7 +10,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(i32) = G_USUBO [[COPY]], [[COPY2]]
; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY1]], [[COPY3]], [[USUBO1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
@@ -39,8 +39,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(i32) = G_USUBO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(i32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY2]], [[COPY3]], [[USUBE1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
index abfaea06122d2..f0dad446e3728 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
@@ -210,23 +210,24 @@ body: |
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_1(s128)
; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT %copy_2(s128), 0
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_2(s128)
- ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[EXTRACT]], [[EXTRACT1]]
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[USUBO1]]
- ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 24
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
- ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[USUBE]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[DEF]](s8)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(i32) = G_USUBO [[EXTRACT]], [[EXTRACT1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[UV1]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(i32) = G_SEXT_INREG [[TRUNC]], 24
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[UV3]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(i32) = G_SEXT_INREG [[TRUNC1]], 24
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(i32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[USUBO1]]
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(i32) = G_SEXT_INREG [[USUBE]], 24
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](i32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(i8), [[UV5:%[0-9]+]]:_(i8), [[UV6:%[0-9]+]]:_(i8), [[UV7:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[USUBE]](i32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i32) = G_MERGE_VALUES [[UV4]](i8), [[UV5]](i8), [[UV6]](i8), [[DEF]](i8)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i32) = G_MERGE_VALUES [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](i32), [[MV1]](i32)
; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[MV2]], 24
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[ASHR]], [[C]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[ASHR]], [[C]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO]], [[USUBO]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
index 205c32f6971ac..ceea97297033e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
@@ -10,8 +10,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(i32) = G_USUBO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(i32) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
%0:_(s64) = COPY $x0
@@ -35,9 +35,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
- ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(i32) = G_USUBO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(i32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(i32) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
; CHECK-NEXT: $x2 = COPY [[USUBE2]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
index 11f1f09cbbe0f..9203746380603 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
@@ -11,10 +11,10 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY2]], [[AND]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[COPY]], [[COPY2]], [[AND]]
; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE3]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
@@ -46,11 +46,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY1]], [[AND]]
- ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[COPY]], [[COPY1]], [[AND]]
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(i32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
; CHECK-NEXT: [[UADDE4:%[0-9]+]]:_(s64), [[UADDE5:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE3]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE5]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
index 7628233a6addc..5f90837c60156 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
@@ -10,7 +10,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[COPY]], [[COPY2]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE1]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
@@ -39,8 +39,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(i32) = G_UADDO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(i32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE3]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
index a9c0f3135b420..7054c0de5df51 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
@@ -11,10 +11,10 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY2]], [[AND]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(i32) = G_USUBE [[COPY]], [[COPY2]], [[AND]]
; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], [[USUBE1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE3]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
@@ -46,11 +46,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY1]], [[AND]]
- ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(i32) = G_USUBE [[COPY]], [[COPY1]], [[AND]]
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(i32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
; CHECK-NEXT: [[USUBE4:%[0-9]+]]:_(s64), [[USUBE5:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE3]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE5]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
index 30faa53d89362..fcb11c6ca7533 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
@@ -10,7 +10,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(i32) = G_USUBO [[COPY]], [[COPY2]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE1]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
@@ -39,8 +39,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(i32) = G_USUBO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(i32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE3]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
index aadb873da633c..862ad0ccd2fa7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
@@ -37,26 +37,26 @@ body: |
; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
; CHECK-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR1]], [[C]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[XOR2]], [[C]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[XOR3]], [[C]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[XOR4]], [[C1]]
- ; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 4611686018427387903
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[XOR1]], [[C]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[XOR2]], [[C]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[XOR3]], [[C]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i64) = G_AND [[XOR4]], [[C1]]
+ ; CHECK-NEXT: G_STORE [[AND]](i64), %ptr(p0) :: (store (i64), align 64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
- ; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[AND1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
- ; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
+ ; CHECK-NEXT: G_STORE [[AND2]](i64), [[PTR_ADD1]](p0) :: (store (i64) into unknown-address + 16, align 16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
+ ; CHECK-NEXT: G_STORE [[AND3]](i64), [[PTR_ADD2]](p0) :: (store (i64) into unknown-address + 24)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
- ; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
+ ; CHECK-NEXT: G_STORE [[AND4]](i64), [[PTR_ADD3]](p0) :: (store (i64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s318) = G_IMPLICIT_DEF
%b:_(s318) = G_IMPLICIT_DEF
@@ -81,26 +81,26 @@ body: |
; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
; CHECK-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR1]], [[C]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[XOR2]], [[C]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[XOR3]], [[C]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[XOR4]], [[C1]]
- ; CHECK-NEXT: G_STORE [[AND]](s64), %ptr(p0) :: (store (s64), align 64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[XOR1]], [[C]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[XOR2]], [[C]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[XOR3]], [[C]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i64) = G_AND [[XOR4]], [[C1]]
+ ; CHECK-NEXT: G_STORE [[AND]](i64), %ptr(p0) :: (store (i64), align 64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
- ; CHECK-NEXT: G_STORE [[AND1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[AND1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
- ; CHECK-NEXT: G_STORE [[AND2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
+ ; CHECK-NEXT: G_STORE [[AND2]](i64), [[PTR_ADD1]](p0) :: (store (i64) into unknown-address + 16, align 16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 24
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C4]](i64)
- ; CHECK-NEXT: G_STORE [[AND3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
+ ; CHECK-NEXT: G_STORE [[AND3]](i64), [[PTR_ADD2]](p0) :: (store (i64) into unknown-address + 24)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(i64) = G_CONSTANT i64 32
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C5]](i64)
- ; CHECK-NEXT: G_STORE [[AND4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
+ ; CHECK-NEXT: G_STORE [[AND4]](i64), [[PTR_ADD3]](p0) :: (store (i64) into unknown-address + 32, align 32)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s319) = G_IMPLICIT_DEF
%b:_(s319) = G_IMPLICIT_DEF
@@ -123,21 +123,21 @@ body: |
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1073741823
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR1]], [[C]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[XOR2]], [[C1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
- ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[AND2]](s64), 0
- ; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1073741823
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[XOR1]], [[C]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[XOR2]], [[C1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY [[AND]](i64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY [[AND1]](i64)
+ ; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(i32) = G_EXTRACT [[AND2]](i64), 0
+ ; CHECK-NEXT: G_STORE [[COPY]](i64), %ptr(p0) :: (store (i64), align 32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C2]](i64)
- ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: G_STORE [[COPY1]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %ptr, [[C3]](i64)
- ; CHECK-NEXT: G_STORE [[EXTRACT]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 16, align 16)
+ ; CHECK-NEXT: G_STORE [[EXTRACT]](i32), [[PTR_ADD1]](p0) :: (store (i32) into unknown-address + 16, align 16)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s158) = G_IMPLICIT_DEF
%b:_(s158) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
index 2aee1bbc8ddd4..31e259ca940f0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
@@ -54,10 +54,10 @@ body: |
; CHECK-NEXT: $x0 = COPY [[LDRXroX]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = COPY $x1
+ %1:gpr(i64) = COPY $x1
%2:gpr(p0) = G_PTR_ADD %0, %1
- %4:gpr(s64) = G_LOAD %2(p0) :: (load (s64) from %ir.addr)
- $x0 = COPY %4(s64)
+ %4:gpr(i64) = G_LOAD %2(p0) :: (load (s64) from %ir.addr)
+ $x0 = COPY %4(i64)
RET_ReallyLR implicit $x0
...
@@ -80,10 +80,10 @@ body: |
; CHECK-NEXT: $d0 = COPY [[LDRDroX]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $d0
- %1:gpr(s64) = COPY $x1
+ %1:gpr(i64) = COPY $x1
%2:gpr(p0) = G_PTR_ADD %0, %1
- %4:fpr(s64) = G_LOAD %2(p0) :: (load (s64) from %ir.addr)
- $d0 = COPY %4(s64)
+ %4:fpr(i64) = G_LOAD %2(p0) :: (load (s64) from %ir.addr)
+ $d0 = COPY %4(i64)
RET_ReallyLR implicit $d0
...
---
@@ -111,12 +111,12 @@ body: |
; CHECK-NEXT: $x0 = COPY [[ADDXrr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = COPY $x1
+ %1:gpr(i64) = COPY $x1
%2:gpr(p0) = G_PTR_ADD %0, %1
- %4:gpr(s64) = G_LOAD %2(p0) :: (load (s64) from %ir.addr)
- %5:gpr(s64) = G_PTRTOINT %2
- %6:gpr(s64) = G_ADD %5, %4
- $x0 = COPY %6(s64)
+ %4:gpr(i64) = G_LOAD %2(p0) :: (load (s64) from %ir.addr)
+ %5:gpr(i64) = G_PTRTOINT %2
+ %6:gpr(i64) = G_ADD %5, %4
+ $x0 = COPY %6(i64)
RET_ReallyLR implicit $x0
...
@@ -144,16 +144,16 @@ body: |
; CHECK-NEXT: [[LDRHHroX:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16))
; CHECK-NEXT: RET_ReallyLR implicit [[LDRHHroX]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = COPY $w1
- %15:gpr(s64) = G_CONSTANT i64 9
- %3:gpr(s32) = G_LSHR %1, %15(s64)
- %4:gpr(s64) = G_ZEXT %3(s32)
- %5:gpr(s64) = G_CONSTANT i64 255
- %6:gpr(s64) = G_AND %4, %5
- %13:gpr(s64) = G_CONSTANT i64 1
- %8:gpr(s64) = G_SHL %6, %13(s64)
- %9:gpr(p0) = G_PTR_ADD %0, %8(s64)
- %12:gpr(s32) = G_LOAD %9(p0) :: (load (s16))
+ %1:gpr(i32) = COPY $w1
+ %15:gpr(i64) = G_CONSTANT i64 9
+ %3:gpr(i32) = G_LSHR %1, %15(i64)
+ %4:gpr(i64) = G_ZEXT %3(i32)
+ %5:gpr(i64) = G_CONSTANT i64 255
+ %6:gpr(i64) = G_AND %4, %5
+ %13:gpr(i64) = G_CONSTANT i64 1
+ %8:gpr(i64) = G_SHL %6, %13(i64)
+ %9:gpr(p0) = G_PTR_ADD %0, %8(i64)
+ %12:gpr(i32) = G_LOAD %9(p0) :: (load (s16))
RET_ReallyLR implicit %12
...
---
@@ -173,12 +173,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
; CHECK-NEXT: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[COPY1]], [[COPY]], 0, 1 :: (load (s32) from %ir.addr)
; CHECK-NEXT: RET_ReallyLR implicit [[LDRWroX]]
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 2
- %2:gpr(s64) = G_SHL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 2
+ %2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:gpr(s32) = G_LOAD %4(p0) :: (load (s32) from %ir.addr)
+ %5:gpr(i32) = G_LOAD %4(p0) :: (load (s32) from %ir.addr)
RET_ReallyLR implicit %5
...
---
@@ -199,13 +199,13 @@ body: |
; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)
; CHECK-NEXT: $x2 = COPY [[LDRXroX]]
; CHECK-NEXT: RET_ReallyLR implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 3
- %2:gpr(s64) = G_SHL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 3
+ %2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- $x2 = COPY %5(s64)
+ %5:gpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ $x2 = COPY %5(i64)
RET_ReallyLR implicit $x2
...
@@ -227,13 +227,13 @@ body: |
; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)
; CHECK-NEXT: $d2 = COPY [[LDRDroX]]
; CHECK-NEXT: RET_ReallyLR implicit $d2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 3
- %2:gpr(s64) = G_SHL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 3
+ %2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:fpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- $d2 = COPY %5(s64)
+ %5:fpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ $d2 = COPY %5(i64)
RET_ReallyLR implicit $d2
...
@@ -254,9 +254,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
; CHECK-NEXT: [[LDRQroX:%[0-9]+]]:fpr128 = LDRQroX [[COPY1]], [[COPY]], 0, 1 :: (load (s128) from %ir.addr)
; CHECK-NEXT: RET_ReallyLR implicit [[LDRQroX]]
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:gpr(s64) = G_SHL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
%5:fpr(s128) = G_LOAD %4(p0) :: (load (s128) from %ir.addr)
@@ -281,13 +281,13 @@ body: |
; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)
; CHECK-NEXT: $x2 = COPY [[LDRXroX]]
; CHECK-NEXT: RET_ReallyLR implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_MUL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_MUL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- $x2 = COPY %5(s64)
+ %5:gpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ $x2 = COPY %5(i64)
RET_ReallyLR implicit $x2
...
@@ -309,13 +309,13 @@ body: |
; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)
; CHECK-NEXT: $d2 = COPY [[LDRDroX]]
; CHECK-NEXT: RET_ReallyLR implicit $d2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_MUL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_MUL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:fpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- $d2 = COPY %5(s64)
+ %5:fpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ $d2 = COPY %5(i64)
RET_ReallyLR implicit $d2
...
@@ -337,13 +337,13 @@ body: |
; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)
; CHECK-NEXT: $x2 = COPY [[LDRXroX]]
; CHECK-NEXT: RET_ReallyLR implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_MUL %1, %0(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_MUL %1, %0(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- $x2 = COPY %5(s64)
+ %5:gpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ $x2 = COPY %5(i64)
RET_ReallyLR implicit $x2
...
@@ -365,13 +365,13 @@ body: |
; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)
; CHECK-NEXT: $d2 = COPY [[LDRDroX]]
; CHECK-NEXT: RET_ReallyLR implicit $d2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_MUL %1, %0(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_MUL %1, %0(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:fpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- $d2 = COPY %5(s64)
+ %5:fpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ $d2 = COPY %5(i64)
RET_ReallyLR implicit $d2
...
@@ -399,13 +399,13 @@ body: |
; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load (s64) from %ir.addr)
; CHECK-NEXT: $d2 = COPY [[LDRDroX]]
; CHECK-NEXT: RET_ReallyLR implicit $d2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 7
- %2:gpr(s64) = G_MUL %1, %0(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 7
+ %2:gpr(i64) = G_MUL %1, %0(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:fpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- $d2 = COPY %5(s64)
+ %5:fpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ $d2 = COPY %5(i64)
RET_ReallyLR implicit $d2
...
@@ -433,13 +433,13 @@ body: |
; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load (s64) from %ir.addr)
; CHECK-NEXT: $d2 = COPY [[LDRDroX]]
; CHECK-NEXT: RET_ReallyLR implicit $d2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 16
- %2:gpr(s64) = G_MUL %1, %0(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 16
+ %2:gpr(i64) = G_MUL %1, %0(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:fpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- $d2 = COPY %5(s64)
+ %5:fpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ $d2 = COPY %5(i64)
RET_ReallyLR implicit $d2
...
@@ -467,15 +467,15 @@ body: |
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[LDRXroX]], [[ADDXri]]
; CHECK-NEXT: $x2 = COPY [[ADDXrr]]
; CHECK-NEXT: RET_ReallyLR implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 2
- %2:gpr(s64) = G_SHL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 2
+ %2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- %6:gpr(s64) = G_ADD %2, %1
- %7:gpr(s64) = G_ADD %5, %6
- $x2 = COPY %7(s64)
+ %5:gpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ %6:gpr(i64) = G_ADD %2, %1
+ %7:gpr(i64) = G_ADD %5, %6
+ $x2 = COPY %7(i64)
RET_ReallyLR implicit $x2
...
@@ -503,18 +503,18 @@ body: |
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[LDRXroX]], [[LDRXroX1]]
; CHECK-NEXT: RET_ReallyLR implicit [[ADDXrr]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = COPY $w1
- %15:gpr(s64) = G_CONSTANT i64 9
- %3:gpr(s32) = G_LSHR %1, %15(s64)
- %4:gpr(s64) = G_ZEXT %3(s32)
- %5:gpr(s64) = G_CONSTANT i64 255
- %6:gpr(s64) = G_AND %4, %5
- %13:gpr(s64) = G_CONSTANT i64 3
- %8:gpr(s64) = G_SHL %6, %13(s64)
- %9:gpr(p0) = G_PTR_ADD %0, %8(s64)
- %12:gpr(s64) = G_LOAD %9(p0) :: (load (s64))
- %17:gpr(s64) = G_LOAD %9(p0) :: (load (s64))
- %18:gpr(s64) = G_ADD %12, %17
+ %1:gpr(i32) = COPY $w1
+ %15:gpr(i64) = G_CONSTANT i64 9
+ %3:gpr(i32) = G_LSHR %1, %15(i64)
+ %4:gpr(i64) = G_ZEXT %3(i32)
+ %5:gpr(i64) = G_CONSTANT i64 255
+ %6:gpr(i64) = G_AND %4, %5
+ %13:gpr(i64) = G_CONSTANT i64 3
+ %8:gpr(i64) = G_SHL %6, %13(i64)
+ %9:gpr(p0) = G_PTR_ADD %0, %8(i64)
+ %12:gpr(i64) = G_LOAD %9(p0) :: (load (s64))
+ %17:gpr(i64) = G_LOAD %9(p0) :: (load (s64))
+ %18:gpr(i64) = G_ADD %12, %17
RET_ReallyLR implicit %18
...
@@ -544,17 +544,17 @@ body: |
; CHECK-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[ADDXrr1]]
; CHECK-NEXT: $x2 = COPY [[ADDXrr2]]
; CHECK-NEXT: RET_ReallyLR implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 3
- %2:gpr(s64) = G_SHL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 3
+ %2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- %6:gpr(s64) = G_ADD %2, %1
- %7:gpr(s64) = G_ADD %5, %6
- %8:gpr(s64) = G_PTRTOINT %4
- %9:gpr(s64) = G_ADD %8, %7
- $x2 = COPY %9(s64)
+ %5:gpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ %6:gpr(i64) = G_ADD %2, %1
+ %7:gpr(i64) = G_ADD %5, %6
+ %8:gpr(i64) = G_PTRTOINT %4
+ %9:gpr(i64) = G_ADD %8, %7
+ $x2 = COPY %9(i64)
RET_ReallyLR implicit $x2
...
@@ -602,18 +602,18 @@ body: |
; CHECK-SLOW-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRHHui]], [[LDRHHui1]]
; CHECK-SLOW-NEXT: RET_ReallyLR implicit [[ADDWrr]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = COPY $w1
- %15:gpr(s64) = G_CONSTANT i64 9
- %3:gpr(s32) = G_LSHR %1, %15(s64)
- %4:gpr(s64) = G_ZEXT %3(s32)
- %5:gpr(s64) = G_CONSTANT i64 255
- %6:gpr(s64) = G_AND %4, %5
- %13:gpr(s64) = G_CONSTANT i64 1
- %8:gpr(s64) = G_SHL %6, %13(s64)
- %9:gpr(p0) = G_PTR_ADD %0, %8(s64)
- %12:gpr(s32) = G_LOAD %9(p0) :: (load (s16))
- %17:gpr(s32) = G_LOAD %9(p0) :: (load (s16))
- %18:gpr(s32) = G_ADD %12, %17
+ %1:gpr(i32) = COPY $w1
+ %15:gpr(i64) = G_CONSTANT i64 9
+ %3:gpr(i32) = G_LSHR %1, %15(i64)
+ %4:gpr(i64) = G_ZEXT %3(i32)
+ %5:gpr(i64) = G_CONSTANT i64 255
+ %6:gpr(i64) = G_AND %4, %5
+ %13:gpr(i64) = G_CONSTANT i64 1
+ %8:gpr(i64) = G_SHL %6, %13(i64)
+ %9:gpr(p0) = G_PTR_ADD %0, %8(i64)
+ %12:gpr(i32) = G_LOAD %9(p0) :: (load (s16))
+ %17:gpr(i32) = G_LOAD %9(p0) :: (load (s16))
+ %18:gpr(i32) = G_ADD %12, %17
RET_ReallyLR implicit %18
...
---
@@ -660,18 +660,18 @@ body: |
; CHECK-SLOW-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRHHui]], [[LDRHHui1]]
; CHECK-SLOW-NEXT: RET_ReallyLR implicit [[ADDWrr]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = COPY $w1
- %15:gpr(s64) = G_CONSTANT i64 9
- %3:gpr(s32) = G_LSHR %1, %15(s64)
- %4:gpr(s64) = G_ZEXT %3(s32)
- %5:gpr(s64) = G_CONSTANT i64 255
- %6:gpr(s64) = G_AND %4, %5
- %13:gpr(s64) = G_CONSTANT i64 1
- %8:gpr(s64) = G_SHL %6, %13(s64)
- %9:gpr(p0) = G_PTR_ADD %0, %8(s64)
- %12:gpr(s32) = G_LOAD %9(p0) :: (load (s16))
- %17:gpr(s32) = G_LOAD %9(p0) :: (load (s16))
- %18:gpr(s32) = G_ADD %12, %17
+ %1:gpr(i32) = COPY $w1
+ %15:gpr(i64) = G_CONSTANT i64 9
+ %3:gpr(i32) = G_LSHR %1, %15(i64)
+ %4:gpr(i64) = G_ZEXT %3(i32)
+ %5:gpr(i64) = G_CONSTANT i64 255
+ %6:gpr(i64) = G_AND %4, %5
+ %13:gpr(i64) = G_CONSTANT i64 1
+ %8:gpr(i64) = G_SHL %6, %13(i64)
+ %9:gpr(p0) = G_PTR_ADD %0, %8(i64)
+ %12:gpr(i32) = G_LOAD %9(p0) :: (load (s16))
+ %17:gpr(i32) = G_LOAD %9(p0) :: (load (s16))
+ %18:gpr(i32) = G_ADD %12, %17
RET_ReallyLR implicit %18
...
---
@@ -701,18 +701,18 @@ body: |
; CHECK-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[ADDXrr1]]
; CHECK-NEXT: $x2 = COPY [[ADDXrr2]]
; CHECK-NEXT: RET_ReallyLR implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 2
- %2:gpr(s64) = G_SHL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 2
+ %2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %20:gpr(s32) = G_LOAD %4(p0) :: (load (s32) from %ir.addr)
- %5:gpr(s64) = G_ZEXT %20
- %6:gpr(s64) = G_ADD %2, %1
- %7:gpr(s64) = G_ADD %5, %6
- %8:gpr(s64) = G_PTRTOINT %4
- %9:gpr(s64) = G_ADD %8, %7
- $x2 = COPY %9(s64)
+ %20:gpr(i32) = G_LOAD %4(p0) :: (load (s32) from %ir.addr)
+ %5:gpr(i64) = G_ZEXT %20
+ %6:gpr(i64) = G_ADD %2, %1
+ %7:gpr(i64) = G_ADD %5, %6
+ %8:gpr(i64) = G_PTRTOINT %4
+ %9:gpr(i64) = G_ADD %8, %7
+ $x2 = COPY %9(i64)
RET_ReallyLR implicit $x2
...
---
@@ -757,18 +757,18 @@ body: |
; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64 = COPY [[ADDXrr]]
; CHECK-SLOW-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[COPY4]], [[ADDXrr1]]
; CHECK-SLOW-NEXT: RET_ReallyLR implicit [[ADDXrr2]]
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %2:gpr(s64) = G_SHL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
%20:fpr(s128) = G_LOAD %4(p0) :: (load (s128) from %ir.addr)
- %6:gpr(s64) = G_ADD %2, %1
- %200:fpr(s64) = G_TRUNC %20
- %2000:gpr(s64) = COPY %200
- %7:gpr(s64) = G_ADD %2000, %6
- %8:gpr(s64) = G_PTRTOINT %4
- %9:gpr(s64) = G_ADD %8, %7
+ %6:gpr(i64) = G_ADD %2, %1
+ %200:fpr(i64) = G_TRUNC %20
+ %2000:gpr(i64) = COPY %200
+ %7:gpr(i64) = G_ADD %2000, %6
+ %8:gpr(i64) = G_PTRTOINT %4
+ %9:gpr(i64) = G_ADD %8, %7
RET_ReallyLR implicit %9
...
---
@@ -794,15 +794,15 @@ body: |
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[LDRXroX]], [[LDRXroX1]]
; CHECK-NEXT: $x2 = COPY [[ADDXrr]]
; CHECK-NEXT: RET_ReallyLR implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 3
- %2:gpr(s64) = G_SHL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 3
+ %2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- %6:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- %7:gpr(s64) = G_ADD %5, %6
- $x2 = COPY %7(s64)
+ %5:gpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ %6:gpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ %7:gpr(i64) = G_ADD %5, %6
+ $x2 = COPY %7(i64)
RET_ReallyLR implicit $x2
...
@@ -833,17 +833,17 @@ body: |
; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrs]], [[ADDXrr]]
; CHECK-NEXT: $x2 = COPY [[ADDXrr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x2
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 3
- %2:gpr(s64) = G_SHL %0, %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 3
+ %2:gpr(i64) = G_SHL %0, %1(i64)
%3:gpr(p0) = COPY $x1
%4:gpr(p0) = G_PTR_ADD %3, %2
- %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
- %6:gpr(s64) = G_ADD %2, %1
- %7:gpr(s64) = G_ADD %5, %6
- %8:gpr(s64) = G_PTRTOINT %4
- %9:gpr(s64) = G_ADD %8, %7
- $x2 = COPY %9(s64)
+ %5:gpr(i64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)
+ %6:gpr(i64) = G_ADD %2, %1
+ %7:gpr(i64) = G_ADD %5, %6
+ %8:gpr(i64) = G_PTRTOINT %4
+ %9:gpr(i64) = G_ADD %8, %7
+ $x2 = COPY %9(i64)
RET_ReallyLR implicit $x2
...
---
@@ -865,10 +865,10 @@ body: |
; CHECK-NEXT: $w2 = COPY [[LDRWroX]]
; CHECK-NEXT: RET_ReallyLR implicit $w2
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = COPY $x1
+ %1:gpr(i64) = COPY $x1
%2:gpr(p0) = G_PTR_ADD %0, %1
- %4:gpr(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.addr)
- $w2 = COPY %4(s32)
+ %4:gpr(i32) = G_LOAD %2(p0) :: (load (s32) from %ir.addr)
+ $w2 = COPY %4(i32)
RET_ReallyLR implicit $w2
...
---
@@ -890,10 +890,10 @@ body: |
; CHECK-NEXT: $s2 = COPY [[LDRSroX]]
; CHECK-NEXT: RET_ReallyLR implicit $h2
%0:gpr(p0) = COPY $d0
- %1:gpr(s64) = COPY $x1
+ %1:gpr(i64) = COPY $x1
%2:gpr(p0) = G_PTR_ADD %0, %1
- %4:fpr(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.addr)
- $s2 = COPY %4(s32)
+ %4:fpr(i32) = G_LOAD %2(p0) :: (load (s32) from %ir.addr)
+ $s2 = COPY %4(i32)
RET_ReallyLR implicit $h2
...
---
@@ -915,7 +915,7 @@ body: |
; CHECK-NEXT: $h2 = COPY [[LDRHroX]]
; CHECK-NEXT: RET_ReallyLR implicit $h2
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = COPY $x1
+ %1:gpr(i64) = COPY $x1
%2:gpr(p0) = G_PTR_ADD %0, %1
%4:fpr(s16) = G_LOAD %2(p0) :: (load (s16) from %ir.addr)
$h2 = COPY %4(s16)
@@ -940,10 +940,10 @@ body: |
; CHECK-NEXT: $w2 = COPY [[LDRBBroX]]
; CHECK-NEXT: RET_ReallyLR implicit $w2
%0:gpr(p0) = COPY $x0
- %1:gpr(s64) = COPY $x1
+ %1:gpr(i64) = COPY $x1
%2:gpr(p0) = G_PTR_ADD %0, %1
- %4:gpr(s32) = G_LOAD %2(p0) :: (load (s8) from %ir.addr)
- $w2 = COPY %4(s32)
+ %4:gpr(i32) = G_LOAD %2(p0) :: (load (s8) from %ir.addr)
+ $w2 = COPY %4(i32)
RET_ReallyLR implicit $w2
...
---
@@ -965,8 +965,8 @@ body: |
; CHECK-NEXT: $q0 = COPY [[LDRQroX]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:gpr(p0) = COPY $d0
- %1:gpr(s64) = COPY $x1
+ %1:gpr(i64) = COPY $x1
%2:gpr(p0) = G_PTR_ADD %0, %1
- %4:fpr(<2 x s64>) = G_LOAD %2(p0) :: (load (<2 x s64>) from %ir.addr)
- $q0 = COPY %4(<2 x s64>)
+ %4:fpr(<2 x i64>) = G_LOAD %2(p0) :: (load (<2 x s64>) from %ir.addr)
+ $q0 = COPY %4(<2 x i64>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
index 5bc7c3e6fe7fb..e3cea0dd5b033 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
@@ -27,11 +27,11 @@ body: |
; CHECK-NEXT: $w0 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $w0
%base:gpr(p0) = COPY $x0
- %foo:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_SEXT %foo(s32)
- %c:gpr(s64) = G_CONSTANT i64 2
- %offset:gpr(s64) = G_SHL %ext, %c
- %ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
+ %foo:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_SEXT %foo(i32)
+ %c:gpr(i64) = G_CONSTANT i64 2
+ %offset:gpr(i64) = G_SHL %ext, %c
+ %ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
$w0 = COPY %load(s32)
RET_ReallyLR implicit $w0
@@ -62,11 +62,11 @@ body: |
; CHECK-NEXT: $w0 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $w0
%base:gpr(p0) = COPY $x0
- %foo:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_ZEXT %foo(s32)
- %c:gpr(s64) = G_CONSTANT i64 2
- %offset:gpr(s64) = G_SHL %ext, %c
- %ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
+ %foo:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_ZEXT %foo(i32)
+ %c:gpr(i64) = G_CONSTANT i64 2
+ %offset:gpr(i64) = G_SHL %ext, %c
+ %ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
$w0 = COPY %load(s32)
RET_ReallyLR implicit $w0
@@ -97,11 +97,11 @@ body: |
; CHECK-NEXT: $w0 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $w0
%base:gpr(p0) = COPY $x0
- %foo:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_ANYEXT %foo(s32)
- %c:gpr(s64) = G_CONSTANT i64 2
- %offset:gpr(s64) = G_SHL %ext, %c
- %ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
+ %foo:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_ANYEXT %foo(i32)
+ %c:gpr(i64) = G_CONSTANT i64 2
+ %offset:gpr(i64) = G_SHL %ext, %c
+ %ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
$w0 = COPY %load(s32)
RET_ReallyLR implicit $w0
@@ -130,11 +130,11 @@ body: |
; CHECK-NEXT: $w0 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $w0
%base:gpr(p0) = COPY $x0
- %foo:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_SEXT %foo(s32)
- %c:gpr(s64) = G_CONSTANT i64 4
- %offset:gpr(s64) = G_MUL %c, %ext
- %ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
+ %foo:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_SEXT %foo(i32)
+ %c:gpr(i64) = G_CONSTANT i64 4
+ %offset:gpr(i64) = G_MUL %c, %ext
+ %ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
$w0 = COPY %load(s32)
RET_ReallyLR implicit $w0
@@ -163,11 +163,11 @@ body: |
; CHECK-NEXT: $w0 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $w0
%base:gpr(p0) = COPY $x0
- %foo:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_ZEXT %foo(s32)
- %c:gpr(s64) = G_CONSTANT i64 4
- %offset:gpr(s64) = G_MUL %c, %ext
- %ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
+ %foo:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_ZEXT %foo(i32)
+ %c:gpr(i64) = G_CONSTANT i64 4
+ %offset:gpr(i64) = G_MUL %c, %ext
+ %ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
$w0 = COPY %load(s32)
RET_ReallyLR implicit $w0
@@ -196,11 +196,11 @@ body: |
; CHECK-NEXT: $w0 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $w0
%base:gpr(p0) = COPY $x0
- %foo:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_ANYEXT %foo(s32)
- %c:gpr(s64) = G_CONSTANT i64 4
- %offset:gpr(s64) = G_MUL %c, %ext
- %ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
+ %foo:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_ANYEXT %foo(i32)
+ %c:gpr(i64) = G_CONSTANT i64 4
+ %offset:gpr(i64) = G_MUL %c, %ext
+ %ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
$w0 = COPY %load(s32)
RET_ReallyLR implicit $w0
@@ -229,11 +229,11 @@ body: |
; CHECK-NEXT: $x0 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $x0
%base:gpr(p0) = COPY $x0
- %foo:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_SEXT %foo(s32)
- %c:gpr(s64) = G_CONSTANT i64 8
- %offset:gpr(s64) = G_MUL %c, %ext
- %ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
+ %foo:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_SEXT %foo(i32)
+ %c:gpr(i64) = G_CONSTANT i64 8
+ %offset:gpr(i64) = G_MUL %c, %ext
+ %ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
%load:fpr(<2 x s32>) = G_LOAD %ptr(p0) :: (load (<2 x s32>))
$x0 = COPY %load(<2 x s32>)
RET_ReallyLR implicit $x0
@@ -262,11 +262,11 @@ body: |
; CHECK-NEXT: $x0 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $x0
%base:gpr(p0) = COPY $x0
- %foo:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_SEXT %foo(s32)
- %c:gpr(s64) = G_CONSTANT i64 8
- %offset:gpr(s64) = G_MUL %c, %ext
- %ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
+ %foo:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_SEXT %foo(i32)
+ %c:gpr(i64) = G_CONSTANT i64 8
+ %offset:gpr(i64) = G_MUL %c, %ext
+ %ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
%load:gpr(s64) = G_LOAD %ptr(p0) :: (load (s64))
$x0 = COPY %load(s64)
RET_ReallyLR implicit $x0
@@ -295,10 +295,10 @@ body: |
; CHECK-NEXT: %load:gpr32 = LDRBBroW %base, %val, 1, 0 :: (load (s8))
; CHECK-NEXT: $w0 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %val:gpr(s32) = COPY $w1
+ %val:gpr(i32) = COPY $w1
%base:gpr(p0) = COPY $x0
- %ext:gpr(s64) = G_SEXT %val(s32)
- %ptr:gpr(p0) = G_PTR_ADD %base, %ext(s64)
+ %ext:gpr(i64) = G_SEXT %val(i32)
+ %ptr:gpr(p0) = G_PTR_ADD %base, %ext(i64)
%load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s8))
$w0 = COPY %load(s32)
RET_ReallyLR implicit $w0
@@ -327,11 +327,11 @@ body: |
; CHECK-NEXT: $h0 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $h0
%base:gpr(p0) = COPY $x0
- %foo:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_SEXT %foo(s32)
- %c:gpr(s64) = G_CONSTANT i64 2
- %offset:gpr(s64) = G_MUL %c, %ext
- %ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
+ %foo:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_SEXT %foo(i32)
+ %c:gpr(i64) = G_CONSTANT i64 2
+ %offset:gpr(i64) = G_MUL %c, %ext
+ %ptr:gpr(p0) = G_PTR_ADD %base, %offset(i64)
%load:fpr(s16) = G_LOAD %ptr(p0) :: (load (s16))
$h0 = COPY %load(s16)
RET_ReallyLR implicit $h0
@@ -361,12 +361,12 @@ body: |
; CHECK-NEXT: $x1 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $x1
%base:gpr(p0) = COPY $x0
- %imp:gpr(s64) = G_IMPLICIT_DEF
- %bad_mask:gpr(s64) = G_CONSTANT i64 255
- %and:gpr(s64) = G_AND %imp, %bad_mask
- %c:gpr(s64) = G_CONSTANT i64 8
- %mul:gpr(s64) = G_MUL %c, %and
- %ptr:gpr(p0) = G_PTR_ADD %base, %mul(s64)
+ %imp:gpr(i64) = G_IMPLICIT_DEF
+ %bad_mask:gpr(i64) = G_CONSTANT i64 255
+ %and:gpr(i64) = G_AND %imp, %bad_mask
+ %c:gpr(i64) = G_CONSTANT i64 8
+ %mul:gpr(i64) = G_MUL %c, %and
+ %ptr:gpr(p0) = G_PTR_ADD %base, %mul(i64)
%load:gpr(s64) = G_LOAD %ptr(p0) :: (load (s64))
$x1 = COPY %load(s64)
RET_ReallyLR implicit $x1
@@ -396,12 +396,12 @@ body: |
; CHECK-NEXT: $x1 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $x1
%base:gpr(p0) = COPY $x0
- %imp:gpr(s64) = G_IMPLICIT_DEF
- %bad_mask:gpr(s64) = G_CONSTANT i64 65535
- %and:gpr(s64) = G_AND %imp, %bad_mask
- %c:gpr(s64) = G_CONSTANT i64 8
- %mul:gpr(s64) = G_MUL %c, %and
- %ptr:gpr(p0) = G_PTR_ADD %base, %mul(s64)
+ %imp:gpr(i64) = G_IMPLICIT_DEF
+ %bad_mask:gpr(i64) = G_CONSTANT i64 65535
+ %and:gpr(i64) = G_AND %imp, %bad_mask
+ %c:gpr(i64) = G_CONSTANT i64 8
+ %mul:gpr(i64) = G_MUL %c, %and
+ %ptr:gpr(p0) = G_PTR_ADD %base, %mul(i64)
%load:gpr(s64) = G_LOAD %ptr(p0) :: (load (s64))
$x1 = COPY %load(s64)
RET_ReallyLR implicit $x1
@@ -431,12 +431,12 @@ body: |
; CHECK-NEXT: $x1 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $x1
%base:gpr(p0) = COPY $x0
- %imp:gpr(s64) = G_IMPLICIT_DEF
- %mask:gpr(s64) = G_CONSTANT i64 4294967295
- %and:gpr(s64) = G_AND %imp, %mask
- %c:gpr(s64) = G_CONSTANT i64 8
- %mul:gpr(s64) = G_MUL %c, %and
- %ptr:gpr(p0) = G_PTR_ADD %base, %mul(s64)
+ %imp:gpr(i64) = G_IMPLICIT_DEF
+ %mask:gpr(i64) = G_CONSTANT i64 4294967295
+ %and:gpr(i64) = G_AND %imp, %mask
+ %c:gpr(i64) = G_CONSTANT i64 8
+ %mul:gpr(i64) = G_MUL %c, %and
+ %ptr:gpr(p0) = G_PTR_ADD %base, %mul(i64)
%load:gpr(s64) = G_LOAD %ptr(p0) :: (load (s64))
$x1 = COPY %load(s64)
RET_ReallyLR implicit $x1
@@ -465,14 +465,14 @@ body: |
; CHECK-NEXT: [[LDRWroW:%[0-9]+]]:gpr32 = LDRWroW [[COPY1]], [[ANDWri]], 0, 1 :: (load (s32))
; CHECK-NEXT: $w0 = COPY [[LDRWroW]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
+ %0:gpr(i32) = COPY $w0
%1:gpr(p0) = COPY $x1
- %2:gpr(s32) = G_CONSTANT i32 255
- %3:gpr(s32) = G_AND %0, %2
- %13:gpr(s64) = G_CONSTANT i64 2
- %12:gpr(s32) = G_SHL %3, %13(s64)
- %6:gpr(s64) = G_ZEXT %12(s32)
- %7:gpr(p0) = G_PTR_ADD %1, %6(s64)
+ %2:gpr(i32) = G_CONSTANT i32 255
+ %3:gpr(i32) = G_AND %0, %2
+ %13:gpr(i64) = G_CONSTANT i64 2
+ %12:gpr(i32) = G_SHL %3, %13(i64)
+ %6:gpr(i64) = G_ZEXT %12(i32)
+ %7:gpr(p0) = G_PTR_ADD %1, %6(i64)
%9:gpr(s32) = G_LOAD %7(p0) :: (load (s32))
$w0 = COPY %9(s32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
index 591dafc1ad098..5317e7c5c0dbf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
@@ -13,8 +13,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQ %lhs, %rhs(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x i64>) = G_FCMEQ %lhs, %rhs(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%rhs:_(<2 x s64>) = COPY $q1
@@ -39,8 +39,8 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQ %lhs, %zero_vec(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x i64>) = G_FCMEQ %lhs, %zero_vec(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%zero:_(s64) = G_CONSTANT i64 0
@@ -63,8 +63,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMGT]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMGT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%rhs:_(<2 x s64>) = COPY $q1
@@ -86,8 +86,8 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMGT]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMGT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%zero:_(s64) = G_CONSTANT i64 0
@@ -109,8 +109,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMGE]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x i64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMGE]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%rhs:_(<2 x s64>) = COPY $q1
@@ -135,8 +135,8 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %zero_vec(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMGE]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x i64>) = G_FCMGE %lhs, %zero_vec(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMGE]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%zero:_(s64) = G_CONSTANT i64 0
@@ -159,8 +159,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMGT]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMGT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%rhs:_(<2 x s64>) = COPY $q1
@@ -182,8 +182,8 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %zero_vec, %lhs(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMGT]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %zero_vec, %lhs(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMGT]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%zero:_(s64) = G_CONSTANT i64 0
@@ -205,8 +205,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %rhs, %lhs(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMGE]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x i64>) = G_FCMGE %rhs, %lhs(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMGE]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%rhs:_(<2 x s64>) = COPY $q1
@@ -228,8 +228,8 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %zero_vec, %lhs(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMGE]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x i64>) = G_FCMGE %zero_vec, %lhs(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMGE]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%zero:_(s64) = G_CONSTANT i64 0
@@ -254,8 +254,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
- ; CHECK-NEXT: [[FCMGT1:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT1:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMGT1]], [[FCMGT]]
; CHECK-NEXT: $q0 = COPY [[OR]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -282,8 +282,8 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
- ; CHECK-NEXT: [[FCMGT1:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %zero_vec, %lhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT1:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %zero_vec, %lhs(<2 x s64>)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMGT1]], [[FCMGT]]
; CHECK-NEXT: $q0 = COPY [[OR]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -310,8 +310,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x i64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMGT]], [[FCMGE]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
@@ -338,11 +338,11 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQ %lhs, %lhs(<2 x s64>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMEQ]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x i64>) = G_FCMEQ %lhs, %lhs(<2 x s64>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[FCMEQ]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%zero:_(s64) = G_CONSTANT i64 0
@@ -367,8 +367,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x i64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMGT]], [[FCMGE]]
; CHECK-NEXT: $q0 = COPY [[OR]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -393,8 +393,8 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQ %lhs, %lhs(<2 x s64>)
- ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x i64>) = G_FCMEQ %lhs, %lhs(<2 x s64>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%zero:_(s64) = G_CONSTANT i64 0
@@ -419,7 +419,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x i64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGE]], [[BUILD_VECTOR]]
@@ -448,7 +448,7 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %zero_vec(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x i64>) = G_FCMGE %lhs, %zero_vec(<2 x s64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGE]], [[BUILD_VECTOR]]
@@ -477,7 +477,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGT]], [[BUILD_VECTOR]]
@@ -506,7 +506,7 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGT]], [[BUILD_VECTOR]]
@@ -535,7 +535,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %rhs, %lhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x i64>) = G_FCMGE %rhs, %lhs(<2 x s64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGE]], [[BUILD_VECTOR]]
@@ -564,7 +564,7 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %zero_vec, %lhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x i64>) = G_FCMGE %zero_vec, %lhs(<2 x s64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGE]], [[BUILD_VECTOR]]
@@ -593,7 +593,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGT]], [[BUILD_VECTOR]]
@@ -622,7 +622,7 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %zero_vec, %lhs(<2 x s64>)
+ ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x i64>) = G_FCMGT %zero_vec, %lhs(<2 x s64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGT]], [[BUILD_VECTOR]]
@@ -651,11 +651,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %rhs:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQ %lhs, %rhs(<2 x s64>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMEQ]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x i64>) = G_FCMEQ %lhs, %rhs(<2 x s64>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[FCMEQ]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%rhs:_(<2 x s64>) = COPY $q1
@@ -680,11 +680,11 @@ body: |
; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQ %lhs, %zero_vec(<2 x s64>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMEQ]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x s64>)
+ ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x i64>) = G_FCMEQ %lhs, %zero_vec(<2 x s64>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C]](i64), [[C]](i64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[FCMEQ]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x i64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<2 x s64>) = COPY $q0
%zero:_(s64) = G_CONSTANT i64 0
@@ -707,8 +707,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: %rhs:_(<8 x s16>) = COPY $q1
- ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<8 x s16>) = G_FCMEQ %lhs, %rhs(<8 x s16>)
- ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<8 x s16>)
+ ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<8 x i16>) = G_FCMEQ %lhs, %rhs(<8 x s16>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<8 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<8 x s16>) = COPY $q0
%rhs:_(<8 x s16>) = COPY $q1
@@ -730,8 +730,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<4 x s16>) = COPY $d0
; CHECK-NEXT: %rhs:_(<4 x s16>) = COPY $d1
- ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<4 x s16>) = G_FCMEQ %lhs, %rhs(<4 x s16>)
- ; CHECK-NEXT: $d0 = COPY [[FCMEQ]](<4 x s16>)
+ ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<4 x i16>) = G_FCMEQ %lhs, %rhs(<4 x s16>)
+ ; CHECK-NEXT: $d0 = COPY [[FCMEQ]](<4 x i16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%lhs:_(<4 x s16>) = COPY $d0
%rhs:_(<4 x s16>) = COPY $d1
@@ -752,8 +752,8 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<4 x s32>) = G_FCMEQ %lhs, %lhs(<4 x s32>)
- ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<4 x s32>)
+ ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<4 x i32>) = G_FCMEQ %lhs, %lhs(<4 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<4 x i32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lhs:_(<4 x s32>) = COPY $q0
%zero:_(s32) = G_FCONSTANT float 0.000000e+00
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.mir b/llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.mir
index 62c15292b8cbf..18e5db5225091 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.mir
@@ -640,8 +640,8 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[LSHR]](s32)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[COPY1]](p0) :: (store (s16), align 1)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: G_STORE [[TRUNC1]](i16), [[COPY1]](p0) :: (store (i16), align 1)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[PTR_ADD]](p0) :: (store (s8))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
index a5b6ea487aac4..ae9de067d627c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
@@ -28,11 +28,11 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8589934592 ; Bit number 33 => TBNZX
- %3:gpr(s64) = G_CONSTANT i64 0
- %2:gpr(s64) = G_AND %0, %1
- %5:gpr(s32) = G_ICMP intpred(ne), %2(s64), %3
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8589934592 ; Bit number 33 => TBNZX
+ %3:gpr(i64) = G_CONSTANT i64 0
+ %2:gpr(i64) = G_AND %0, %1
+ %5:gpr(i32) = G_ICMP intpred(ne), %2(i64), %3
G_BRCOND %5, %bb.1
G_BR %bb.0
bb.1:
@@ -60,11 +60,11 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8589934592 ; Bit number 33 => TBNZX
- %3:gpr(s64) = G_CONSTANT i64 0
- %2:gpr(s64) = G_AND %0, %1
- %5:gpr(s32) = G_ICMP intpred(eq), %2(s64), %3
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8589934592 ; Bit number 33 => TBNZX
+ %3:gpr(i64) = G_CONSTANT i64 0
+ %2:gpr(i64) = G_AND %0, %1
+ %5:gpr(i32) = G_ICMP intpred(eq), %2(i64), %3
G_BRCOND %5, %bb.1
G_BR %bb.0
bb.1:
@@ -92,11 +92,11 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_CONSTANT i32 0
- %2:gpr(s32) = G_AND %0, %1
- %5:gpr(s32) = G_ICMP intpred(ne), %2(s32), %3
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_CONSTANT i32 0
+ %2:gpr(i32) = G_AND %0, %1
+ %5:gpr(i32) = G_ICMP intpred(ne), %2(i32), %3
G_BRCOND %5, %bb.1
G_BR %bb.0
bb.1:
@@ -124,11 +124,11 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_CONSTANT i32 0
- %2:gpr(s32) = G_AND %0, %1
- %5:gpr(s32) = G_ICMP intpred(eq), %2(s32), %3
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_CONSTANT i32 0
+ %2:gpr(i32) = G_AND %0, %1
+ %5:gpr(i32) = G_ICMP intpred(eq), %2(i32), %3
G_BRCOND %5, %bb.1
G_BR %bb.0
bb.1:
@@ -157,11 +157,11 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_CONSTANT i32 0
- %2:gpr(s32) = G_AND %0, %1
- %5:gpr(s32) = G_ICMP intpred(slt), %2(s32), %3
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_CONSTANT i32 0
+ %2:gpr(i32) = G_AND %0, %1
+ %5:gpr(i32) = G_ICMP intpred(slt), %2(i32), %3
G_BRCOND %5, %bb.1
G_BR %bb.0
bb.1:
@@ -190,11 +190,11 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_CONSTANT i32 0
- %2:gpr(s32) = G_AND %0, %1
- %5:gpr(s32) = G_ICMP intpred(sgt), %2(s32), %3
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_CONSTANT i32 0
+ %2:gpr(i32) = G_AND %0, %1
+ %5:gpr(i32) = G_ICMP intpred(sgt), %2(i32), %3
G_BRCOND %5, %bb.1
G_BR %bb.0
bb.1:
@@ -222,11 +222,11 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 7
- %3:gpr(s64) = G_CONSTANT i64 0
- %2:gpr(s64) = G_AND %0, %1
- %5:gpr(s32) = G_ICMP intpred(ne), %2(s64), %3
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 7
+ %3:gpr(i64) = G_CONSTANT i64 0
+ %2:gpr(i64) = G_AND %0, %1
+ %5:gpr(i32) = G_ICMP intpred(ne), %2(i64), %3
G_BRCOND %5, %bb.1
G_BR %bb.0
bb.1:
@@ -255,11 +255,11 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 4
- %3:gpr(s64) = G_CONSTANT i64 4
- %2:gpr(s64) = G_AND %0, %1
- %5:gpr(s32) = G_ICMP intpred(ne), %2(s64), %3
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 4
+ %3:gpr(i64) = G_CONSTANT i64 4
+ %2:gpr(i64) = G_AND %0, %1
+ %5:gpr(i32) = G_ICMP intpred(ne), %2(i64), %3
G_BRCOND %5, %bb.1
G_BR %bb.0
bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir
index 577bee3a9832b..8b127d7982870 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir
@@ -25,17 +25,17 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
- %fold_cst:gpr(s64) = G_CONSTANT i64 8
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %fold_cst:gpr(i64) = G_CONSTANT i64 8
; tbnz (and x, 8), 3 == tbnz x, 3 because the third bit of x & 8 is 1 when
; the third bit of x is 1.
- %fold_me:gpr(s64) = G_AND %copy, %fold_cst
+ %fold_me:gpr(i64) = G_AND %copy, %fold_cst
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -63,16 +63,16 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
- %fold_cst:gpr(s64) = G_CONSTANT i64 8
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %fold_cst:gpr(i64) = G_CONSTANT i64 8
; Same as above, but with the constant on the other side.
- %fold_me:gpr(s64) = G_AND %fold_cst, %copy
+ %fold_me:gpr(i64) = G_AND %fold_cst, %copy
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -101,17 +101,17 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
; tbnz (and x, 7), 3 != tbnz x, 3, because the third bit of x & 7 is always
; zero.
- %fold_cst:gpr(s64) = G_CONSTANT i64 7
+ %fold_cst:gpr(i64) = G_CONSTANT i64 7
- %fold_me:gpr(s64) = G_AND %copy, %fold_cst
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %fold_me:gpr(i64) = G_AND %copy, %fold_cst
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
index aca58b6d140d4..a24dcae90319d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
@@ -50,14 +50,14 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 0
- %6:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_SUB %2, %1
- %7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %3
- %5:gpr(s32) = G_SELECT %7, %6, %2
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 0
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_SUB %2, %1
+ %7:gpr(i32) = G_ICMP intpred(ne), %0(i32), %3
+ %5:gpr(i32) = G_SELECT %7, %6, %2
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -81,14 +81,14 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 0
- %6:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_SUB %2, %0
- %7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %1
- %5:gpr(s32) = G_SELECT %7, %6, %2
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 0
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_SUB %2, %0
+ %7:gpr(i32) = G_ICMP intpred(ne), %3(i32), %1
+ %5:gpr(i32) = G_SELECT %7, %6, %2
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -113,14 +113,14 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 10, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 0
- %6:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_SUB %2, %1
- %7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3
- %5:gpr(s32) = G_SELECT %7, %6, %2
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 0
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_SUB %2, %1
+ %7:gpr(i32) = G_ICMP intpred(slt), %0(i32), %3
+ %5:gpr(i32) = G_SELECT %7, %6, %2
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -145,14 +145,14 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 10, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 0
- %6:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_SUB %2, %0
- %7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1
- %5:gpr(s32) = G_SELECT %7, %6, %2
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 0
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_SUB %2, %0
+ %7:gpr(i32) = G_ICMP intpred(slt), %3(i32), %1
+ %5:gpr(i32) = G_SELECT %7, %6, %2
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -176,14 +176,14 @@ body: |
; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 0, implicit $nzcv
; CHECK-NEXT: $x0 = COPY [[CSINCXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = G_CONSTANT i64 0
- %6:gpr(s64) = G_CONSTANT i64 1
- %3:gpr(s64) = G_SUB %2, %1
- %7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3
- %5:gpr(s64) = G_SELECT %7, %6, %2
- $x0 = COPY %5(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = G_CONSTANT i64 0
+ %6:gpr(i64) = G_CONSTANT i64 1
+ %3:gpr(i64) = G_SUB %2, %1
+ %7:gpr(i32) = G_ICMP intpred(ne), %0(i64), %3
+ %5:gpr(i64) = G_SELECT %7, %6, %2
+ $x0 = COPY %5(i64)
RET_ReallyLR implicit $x0
...
@@ -207,14 +207,14 @@ body: |
; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 0, implicit $nzcv
; CHECK-NEXT: $x0 = COPY [[CSINCXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = G_CONSTANT i64 0
- %6:gpr(s64) = G_CONSTANT i64 1
- %3:gpr(s64) = G_SUB %2, %0
- %7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1
- %5:gpr(s64) = G_SELECT %7, %6, %2
- $x0 = COPY %5(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = G_CONSTANT i64 0
+ %6:gpr(i64) = G_CONSTANT i64 1
+ %3:gpr(i64) = G_SUB %2, %0
+ %7:gpr(i32) = G_ICMP intpred(ne), %3(i64), %1
+ %5:gpr(i64) = G_SELECT %7, %6, %2
+ $x0 = COPY %5(i64)
RET_ReallyLR implicit $x0
...
@@ -239,14 +239,14 @@ body: |
; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 10, implicit $nzcv
; CHECK-NEXT: $x0 = COPY [[CSINCXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = G_CONSTANT i64 0
- %6:gpr(s64) = G_CONSTANT i64 1
- %3:gpr(s64) = G_SUB %2, %1
- %7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3
- %5:gpr(s64) = G_SELECT %7, %6, %2
- $x0 = COPY %5(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = G_CONSTANT i64 0
+ %6:gpr(i64) = G_CONSTANT i64 1
+ %3:gpr(i64) = G_SUB %2, %1
+ %7:gpr(i32) = G_ICMP intpred(slt), %0(i64), %3
+ %5:gpr(i64) = G_SELECT %7, %6, %2
+ $x0 = COPY %5(i64)
RET_ReallyLR implicit $x0
...
@@ -271,14 +271,14 @@ body: |
; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 10, implicit $nzcv
; CHECK-NEXT: $x0 = COPY [[CSINCXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = G_CONSTANT i64 0
- %6:gpr(s64) = G_CONSTANT i64 1
- %3:gpr(s64) = G_SUB %2, %0
- %7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1
- %5:gpr(s64) = G_SELECT %7, %6, %2
- $x0 = COPY %5(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = G_CONSTANT i64 0
+ %6:gpr(i64) = G_CONSTANT i64 1
+ %3:gpr(i64) = G_SUB %2, %0
+ %7:gpr(i32) = G_ICMP intpred(slt), %3(i64), %1
+ %5:gpr(i64) = G_SELECT %7, %6, %2
+ $x0 = COPY %5(i64)
RET_ReallyLR implicit $x0
...
@@ -300,15 +300,15 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 0
- %6:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_AND %2, %1
- %8:gpr(s32) = G_CONSTANT i32 0
- %7:gpr(s32) = G_ICMP intpred(eq), %3(s32), %8
- %5:gpr(s32) = G_SELECT %7, %6, %2
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 0
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_AND %2, %1
+ %8:gpr(i32) = G_CONSTANT i32 0
+ %7:gpr(i32) = G_ICMP intpred(eq), %3(i32), %8
+ %5:gpr(i32) = G_SELECT %7, %6, %2
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -330,15 +330,15 @@ body: |
; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY1]], $xzr, 1, implicit $nzcv
; CHECK-NEXT: $x0 = COPY [[CSINCXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = G_CONSTANT i64 0
- %6:gpr(s64) = G_CONSTANT i64 1
- %3:gpr(s64) = G_AND %2, %1
- %8:gpr(s64) = G_CONSTANT i64 0
- %7:gpr(s32) = G_ICMP intpred(eq), %3(s64), %8
- %5:gpr(s64) = G_SELECT %7, %6, %2
- $x0 = COPY %5(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = G_CONSTANT i64 0
+ %6:gpr(i64) = G_CONSTANT i64 1
+ %3:gpr(i64) = G_AND %2, %1
+ %8:gpr(i64) = G_CONSTANT i64 0
+ %7:gpr(i32) = G_ICMP intpred(eq), %3(i64), %8
+ %5:gpr(i64) = G_SELECT %7, %6, %2
+ $x0 = COPY %5(i64)
RET_ReallyLR implicit $x0
...
@@ -361,15 +361,15 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 9, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 0
- %6:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_AND %2, %1
- %8:gpr(s32) = G_CONSTANT i32 0
- %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8
- %5:gpr(s32) = G_SELECT %7, %6, %2
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 0
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_AND %2, %1
+ %8:gpr(i32) = G_CONSTANT i32 0
+ %7:gpr(i32) = G_ICMP intpred(ugt), %3(i32), %8
+ %5:gpr(i32) = G_SELECT %7, %6, %2
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -392,15 +392,15 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 9, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 0
- %6:gpr(s32) = G_CONSTANT i32 1
- %3:gpr(s32) = G_AND %2, %1
- %8:gpr(s32) = G_CONSTANT i32 42
- %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8
- %5:gpr(s32) = G_SELECT %7, %6, %2
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 0
+ %6:gpr(i32) = G_CONSTANT i32 1
+ %3:gpr(i32) = G_AND %2, %1
+ %8:gpr(i32) = G_CONSTANT i32 42
+ %7:gpr(i32) = G_ICMP intpred(ugt), %3(i32), %8
+ %5:gpr(i32) = G_SELECT %7, %6, %2
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -421,18 +421,18 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 0
- %3:gpr(s32) = G_CONSTANT i32 1
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 0
+ %3:gpr(i32) = G_CONSTANT i32 1
; This can be represented as a logical immediate, so we can pull it into
; the ANDS. We should get ANDSWri.
- %4:gpr(s32) = G_CONSTANT i32 3
+ %4:gpr(i32) = G_CONSTANT i32 3
- %5:gpr(s32) = G_AND %1, %4
- %6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2
- $w0 = COPY %6(s32)
+ %5:gpr(i32) = G_AND %1, %4
+ %6:gpr(i32) = G_ICMP intpred(eq), %5(i32), %2
+ $w0 = COPY %6(i32)
RET_ReallyLR implicit $w0
@@ -455,18 +455,18 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_CONSTANT i32 0
- %3:gpr(s32) = G_CONSTANT i32 1
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_CONSTANT i32 0
+ %3:gpr(i32) = G_CONSTANT i32 1
; This immediate can't be represented as a logical immediate. We shouldn't
; select ANDSWri.
- %4:gpr(s32) = G_CONSTANT i32 -1
+ %4:gpr(i32) = G_CONSTANT i32 -1
- %5:gpr(s32) = G_AND %1, %4
- %6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2
- $w0 = COPY %6(s32)
+ %5:gpr(i32) = G_AND %1, %4
+ %6:gpr(i32) = G_ICMP intpred(eq), %5(i32), %2
+ $w0 = COPY %6(i32)
RET_ReallyLR implicit $w0
...
@@ -488,13 +488,13 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
; When we find the defs of the LHS and RHS of the compare, we walk over
; copies. Make sure that we don't crash when we hit a copy from a physical
; register.
- %7:gpr(s32) = G_ICMP intpred(eq), %0, %1
- $w0 = COPY %7(s32)
+ %7:gpr(i32) = G_ICMP intpred(eq), %0, %1
+ $w0 = COPY %7(i32)
RET_ReallyLR implicit $x0
...
@@ -517,15 +517,15 @@ body: |
; CHECK-NEXT: %select:gpr64 = CSINCXr %zero, $xzr, 1, implicit $nzcv
; CHECK-NEXT: $x0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %copy:gpr(s64) = COPY $x1
- %zero:gpr(s64) = G_CONSTANT i64 0
- %one:gpr(s64) = G_CONSTANT i64 1
- %cst:gpr(s64) = G_CONSTANT i64 16
- %shift:gpr(s64) = G_SHL %copy(s64), %cst(s64)
- %and:gpr(s64) = G_AND %zero, %shift
- %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
- %select:gpr(s64) = G_SELECT %cmp, %one, %zero
- $x0 = COPY %select(s64)
+ %copy:gpr(i64) = COPY $x1
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %one:gpr(i64) = G_CONSTANT i64 1
+ %cst:gpr(i64) = G_CONSTANT i64 16
+ %shift:gpr(i64) = G_SHL %copy(i64), %cst(i64)
+ %and:gpr(i64) = G_AND %zero, %shift
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %and(i64), %zero
+ %select:gpr(i64) = G_SELECT %cmp, %one, %zero
+ $x0 = COPY %select(i64)
RET_ReallyLR implicit $x0
...
@@ -548,15 +548,15 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINCWr %zero, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w1
- %zero:gpr(s32) = G_CONSTANT i32 0
- %one:gpr(s32) = G_CONSTANT i32 1
- %cst:gpr(s32) = G_CONSTANT i32 16
- %shift:gpr(s32) = G_SHL %copy(s32), %cst(s32)
- %and:gpr(s32) = G_AND %zero, %shift
- %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s32), %zero
- %select:gpr(s32) = G_SELECT %cmp, %one, %zero
- $w0 = COPY %select(s32)
+ %copy:gpr(i32) = COPY $w1
+ %zero:gpr(i32) = G_CONSTANT i32 0
+ %one:gpr(i32) = G_CONSTANT i32 1
+ %cst:gpr(i32) = G_CONSTANT i32 16
+ %shift:gpr(i32) = G_SHL %copy(i32), %cst(i32)
+ %and:gpr(i32) = G_AND %zero, %shift
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %and(i32), %zero
+ %select:gpr(i32) = G_SELECT %cmp, %one, %zero
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
@@ -578,12 +578,12 @@ body: |
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %cmp
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %negative_one:gpr(s32) = G_CONSTANT i32 -1
- %zero:gpr(s32) = G_CONSTANT i32 0
- %sub:gpr(s32) = G_SUB %zero, %negative_one
- %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %sub
- $w0 = COPY %cmp(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %negative_one:gpr(i32) = G_CONSTANT i32 -1
+ %zero:gpr(i32) = G_CONSTANT i32 0
+ %sub:gpr(i32) = G_SUB %zero, %negative_one
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %reg0(i32), %sub
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -607,15 +607,15 @@ body: |
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %cmp
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s64) = COPY $x0
- %zero:gpr(s64) = G_CONSTANT i64 0
- %sub:gpr(s64) = G_SUB %zero, %reg0
+ %reg0:gpr(i64) = COPY $x0
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %sub:gpr(i64) = G_SUB %zero, %reg0
- %reg1:gpr(s32) = COPY $w0
- %ext:gpr(s64) = G_SEXT %reg1(s32)
- %cst:gpr(s64) = G_CONSTANT i64 2
- %shift:gpr(s64) = G_SHL %ext, %cst(s64)
+ %reg1:gpr(i32) = COPY $w0
+ %ext:gpr(i64) = G_SEXT %reg1(i32)
+ %cst:gpr(i64) = G_CONSTANT i64 2
+ %shift:gpr(i64) = G_SHL %ext, %cst(i64)
- %cmp:gpr(s32) = G_ICMP intpred(ne), %sub(s64), %shift
- $w0 = COPY %cmp(s32)
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %sub(i64), %shift
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
index b32508ed12c60..217c3a57addb1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
@@ -25,16 +25,16 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
; tbnz (shl x, 1), 3 == tbnz x, 2
- %fold_cst:gpr(s64) = G_CONSTANT i64 1
- %fold_me:gpr(s64) = G_SHL %copy, %fold_cst
+ %fold_cst:gpr(i64) = G_CONSTANT i64 1
+ %fold_me:gpr(i64) = G_SHL %copy, %fold_cst
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -63,16 +63,16 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
; 5 > 3, so we cannot do the transformation as above.
- %fold_cst:gpr(s64) = G_CONSTANT i64 5
- %fold_me:gpr(s64) = G_SHL %copy, %fold_cst
+ %fold_cst:gpr(i64) = G_CONSTANT i64 5
+ %fold_me:gpr(i64) = G_SHL %copy, %fold_cst
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -102,16 +102,16 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
; Same case as above, except we wrap around.
- %fold_cst:gpr(s64) = G_CONSTANT i64 -5
- %fold_me:gpr(s64) = G_SHL %copy, %fold_cst
+ %fold_cst:gpr(i64) = G_CONSTANT i64 -5
+ %fold_me:gpr(i64) = G_SHL %copy, %fold_cst
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -143,20 +143,20 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
- %fold_cst:gpr(s64) = G_CONSTANT i64 2
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %fold_cst:gpr(i64) = G_CONSTANT i64 2
; Don't walk past the G_SHL when it's used more than once.
- %shl:gpr(s64) = G_SHL %copy, %fold_cst
- %and:gpr(s64) = G_AND %shl, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %shl:gpr(i64) = G_SHL %copy, %fold_cst
+ %and:gpr(i64) = G_AND %shl, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
- %second_use:gpr(s64) = G_OR %shl, %bit
+ %second_use:gpr(i64) = G_OR %shl, %bit
$x0 = COPY %second_use
RET_ReallyLR implicit $x0
@@ -183,17 +183,17 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
; tb(n)z (ashr x, c), b == tbz(x, b + c) when b+c <= the size of the type.
; In this case, we should get 1 + 3 = 4 as the bit number.
- %fold_cst:gpr(s64) = G_CONSTANT i64 1
- %fold_me:gpr(s64) = G_ASHR %copy, %fold_cst
+ %fold_cst:gpr(i64) = G_CONSTANT i64 1
+ %fold_me:gpr(i64) = G_ASHR %copy, %fold_cst
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -220,16 +220,16 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s32) = COPY $w0
- %bit:gpr(s32) = G_CONSTANT i32 8
- %zero:gpr(s32) = G_CONSTANT i32 0
+ %copy:gpr(i32) = COPY $w0
+ %bit:gpr(i32) = G_CONSTANT i32 8
+ %zero:gpr(i32) = G_CONSTANT i32 0
; We should get a TBNZW with a 31 as the bit.
- %fold_cst:gpr(s32) = G_CONSTANT i32 1234
- %fold_me:gpr(s32) = G_ASHR %copy, %fold_cst
+ %fold_cst:gpr(i32) = G_CONSTANT i32 1234
+ %fold_me:gpr(i32) = G_ASHR %copy, %fold_cst
- %and:gpr(s32) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero
+ %and:gpr(i32) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i32), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -256,16 +256,16 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
; We should get a TBNZX with a 63 as the bit.
- %fold_cst:gpr(s64) = G_CONSTANT i64 1234
- %fold_me:gpr(s64) = G_ASHR %copy, %fold_cst
+ %fold_cst:gpr(i64) = G_CONSTANT i64 1234
+ %fold_me:gpr(i64) = G_ASHR %copy, %fold_cst
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -292,16 +292,16 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s32) = COPY $w0
- %bit:gpr(s32) = G_CONSTANT i32 8
- %zero:gpr(s32) = G_CONSTANT i32 0
+ %copy:gpr(i32) = COPY $w0
+ %bit:gpr(i32) = G_CONSTANT i32 8
+ %zero:gpr(i32) = G_CONSTANT i32 0
; We should get 4 as the test bit.
- %fold_cst:gpr(s32) = G_CONSTANT i32 1
- %fold_me:gpr(s32) = G_LSHR %copy, %fold_cst
+ %fold_cst:gpr(i32) = G_CONSTANT i32 1
+ %fold_me:gpr(i32) = G_LSHR %copy, %fold_cst
- %and:gpr(s32) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero
+ %and:gpr(i32) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i32), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -328,17 +328,17 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
- ; We're testing a s64.
+ ; We're testing a i64.
; 3 + 29 = 32, which is less than 63, so we can fold.
- %fold_cst:gpr(s64) = G_CONSTANT i64 29
- %fold_me:gpr(s64) = G_LSHR %copy, %fold_cst
+ %fold_cst:gpr(i64) = G_CONSTANT i64 29
+ %fold_me:gpr(i64) = G_LSHR %copy, %fold_cst
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -367,17 +367,17 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s32) = COPY $w0
- %bit:gpr(s32) = G_CONSTANT i32 8
- %zero:gpr(s32) = G_CONSTANT i32 0
+ %copy:gpr(i32) = COPY $w0
+ %bit:gpr(i32) = G_CONSTANT i32 8
+ %zero:gpr(i32) = G_CONSTANT i32 0
- ; We're testing a s32.
+ ; We're testing a i32.
; 3 + 29 = 32, which is greater than 31, so we don't fold.
- %fold_cst:gpr(s32) = G_CONSTANT i32 29
- %fold_me:gpr(s32) = G_LSHR %copy, %fold_cst
+ %fold_cst:gpr(i32) = G_CONSTANT i32 29
+ %fold_me:gpr(i32) = G_LSHR %copy, %fold_cst
- %and:gpr(s32) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero
+ %and:gpr(i32) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i32), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -404,17 +404,17 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s32) = COPY $w0
- %bit:gpr(s32) = G_CONSTANT i32 8
- %zero:gpr(s32) = G_CONSTANT i32 0
+ %copy:gpr(i32) = COPY $w0
+ %bit:gpr(i32) = G_CONSTANT i32 8
+ %zero:gpr(i32) = G_CONSTANT i32 0
; Constant becomes very large and wraps around. Since it's larger than the
; bit width, that means the LSHR is poison, so we can still fold.
- %fold_cst:gpr(s32) = G_CONSTANT i32 -1
- %fold_me:gpr(s32) = G_LSHR %copy, %fold_cst
+ %fold_cst:gpr(i32) = G_CONSTANT i32 -1
+ %fold_me:gpr(i32) = G_LSHR %copy, %fold_cst
- %and:gpr(s32) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero
+ %and:gpr(i32) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i32), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
index 205064a851618..91f68858b8d36 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
@@ -23,21 +23,21 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
+ %copy:gpr(i64) = COPY $x0
; Check bit 3.
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
; 8 has the third bit set.
- %fold_cst:gpr(s64) = G_CONSTANT i64 8
+ %fold_cst:gpr(i64) = G_CONSTANT i64 8
; This only has the third bit set if %copy does not. So, to walk through
; this, we want to use a TBNZW on %copy.
- %fold_me:gpr(s64) = G_XOR %copy, %fold_cst
+ %fold_me:gpr(i64) = G_XOR %copy, %fold_cst
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -68,13 +68,13 @@ body: |
; Same as eq case, but we should get a TBZW instead.
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
- %fold_cst:gpr(s64) = G_CONSTANT i64 8
- %fold_me:gpr(s64) = G_XOR %copy, %fold_cst
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %fold_cst:gpr(i64) = G_CONSTANT i64 8
+ %fold_me:gpr(i64) = G_XOR %copy, %fold_cst
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -102,21 +102,21 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
+ %copy:gpr(i64) = COPY $x0
; Check bit 3.
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
; 7 does not have the third bit set.
- %fold_cst:gpr(s64) = G_CONSTANT i64 7
+ %fold_cst:gpr(i64) = G_CONSTANT i64 7
; This only has the third bit set if %copy does. So, to walk through this,
; we should have a TBZW on %copy.
- %fold_me:gpr(s64) = G_XOR %fold_cst, %copy
+ %fold_me:gpr(i64) = G_XOR %fold_cst, %copy
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -145,12 +145,12 @@ body: |
bb.0:
successors: %bb.0(0x40000000), %bb.1(0x40000000)
- %1:gpr(s32) = G_CONSTANT i32 0
- %3:gpr(s32) = G_CONSTANT i32 -1
- %4:gpr(s32) = G_XOR %1, %3
- %5:gpr(s64) = G_ZEXT %4(s32)
- %15:gpr(s64) = G_CONSTANT i64 0
- %13:gpr(s32) = G_ICMP intpred(slt), %5(s64), %15
+ %1:gpr(i32) = G_CONSTANT i32 0
+ %3:gpr(i32) = G_CONSTANT i32 -1
+ %4:gpr(i32) = G_XOR %1, %3
+ %5:gpr(i64) = G_ZEXT %4(i32)
+ %15:gpr(i64) = G_CONSTANT i64 0
+ %13:gpr(i32) = G_ICMP intpred(slt), %5(i64), %15
G_BRCOND %13, %bb.1
G_BR %bb.0
bb.1:
@@ -181,13 +181,13 @@ body: |
; Same as eq case, but we should get a TBNZW instead.
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
- %fold_cst:gpr(s64) = G_CONSTANT i64 7
- %fold_me:gpr(s64) = G_XOR %fold_cst, %copy
- %and:gpr(s64) = G_AND %fold_me, %bit
- %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %fold_cst:gpr(i64) = G_CONSTANT i64 7
+ %fold_me:gpr(i64) = G_XOR %fold_cst, %copy
+ %and:gpr(i64) = G_AND %fold_me, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -215,17 +215,17 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %zero:gpr(s64) = G_CONSTANT i64 0
- %fold_cst:gpr(s64) = G_CONSTANT i64 8
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %fold_cst:gpr(i64) = G_CONSTANT i64 8
; The G_XORs cancel each other out, so we should get a TBZW.
- %xor1:gpr(s64) = G_XOR %copy, %fold_cst
- %xor2:gpr(s64) = G_XOR %xor1, %fold_cst
+ %xor1:gpr(i64) = G_XOR %copy, %fold_cst
+ %xor2:gpr(i64) = G_XOR %xor1, %fold_cst
- %and:gpr(s64) = G_AND %xor2, %bit
- %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
+ %and:gpr(i64) = G_AND %xor2, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %and(i64), %zero
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-split-zero-stores.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-split-zero-stores.mir
index ba0d81474afd0..5c6f057a39317 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-split-zero-stores.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-split-zero-stores.mir
@@ -16,11 +16,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK-NEXT: G_STORE %zero(s64), [[COPY]](p0) :: (store (s64), align 16)
- ; CHECK-NEXT: G_STORE %zero(s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64), align 16)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%zero:_(s64) = G_CONSTANT i64 0
@@ -41,11 +41,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64), align 16)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64), align 16)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%zero:_(s32) = G_CONSTANT i32 0
@@ -66,11 +66,11 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64), align 16)
- ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](i64)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[COPY]](p0) :: (store (i64), align 16)
+ ; CHECK-NEXT: G_STORE [[C]](i64), [[PTR_ADD]](p0) :: (store (i64) into unknown-address + 8)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%zero:_(s16) = G_CONSTANT i16 0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
index d7690085ae693..2ee01b96f0d60 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
@@ -12,9 +12,9 @@ body: |
; LOWER-LABEL: name: same_reg
; LOWER: liveins: $d0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %r:_(s8) = G_IMPLICIT_DEF
- ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_DUP %r(s8)
- ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>)
+ ; LOWER-NEXT: %r:_(i8) = G_IMPLICIT_DEF
+ ; LOWER-NEXT: %build_vector:_(<8 x i8>) = G_DUP %r(i8)
+ ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x i8>)
; LOWER-NEXT: RET_ReallyLR implicit $d0
;
; SELECT-LABEL: name: same_reg
@@ -24,9 +24,9 @@ body: |
; SELECT-NEXT: %build_vector:fpr64 = DUPv8i8gpr %r
; SELECT-NEXT: $d0 = COPY %build_vector
; SELECT-NEXT: RET_ReallyLR implicit $d0
- %r:_(s8) = G_IMPLICIT_DEF
- %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
- $d0 = COPY %build_vector(<8 x s8>)
+ %r:_(i8) = G_IMPLICIT_DEF
+ %build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
+ $d0 = COPY %build_vector(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -40,15 +40,15 @@ body: |
; LOWER-LABEL: name: dont_combine_different_reg
; LOWER: liveins: $d0, $w0, $w1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %r:_(s32) = COPY $w0
- ; LOWER-NEXT: %q:_(s32) = COPY $w1
- ; LOWER-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+ ; LOWER-NEXT: %r:_(i32) = COPY $w0
+ ; LOWER-NEXT: %q:_(i32) = COPY $w1
+ ; LOWER-NEXT: [[DEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
; LOWER-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; LOWER-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %r(s32), [[C]](i64)
+ ; LOWER-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i32>) = G_INSERT_VECTOR_ELT [[DEF]], %r(i32), [[C]](i64)
; LOWER-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
- ; LOWER-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %q(s32), [[C1]](i64)
- ; LOWER-NEXT: %build_vector:_(<2 x s32>) = COPY [[IVEC1]](<2 x s32>)
- ; LOWER-NEXT: $d0 = COPY %build_vector(<2 x s32>)
+ ; LOWER-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x i32>) = G_INSERT_VECTOR_ELT [[IVEC]], %q(i32), [[C1]](i64)
+ ; LOWER-NEXT: %build_vector:_(<2 x i32>) = COPY [[IVEC1]](<2 x i32>)
+ ; LOWER-NEXT: $d0 = COPY %build_vector(<2 x i32>)
; LOWER-NEXT: RET_ReallyLR implicit $d0
;
; SELECT-LABEL: name: dont_combine_different_reg
@@ -64,10 +64,10 @@ body: |
; SELECT-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
; SELECT-NEXT: $d0 = COPY [[COPY]]
; SELECT-NEXT: RET_ReallyLR implicit $d0
- %r:_(s32) = COPY $w0
- %q:_(s32) = COPY $w1
- %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %r, %q
- $d0 = COPY %build_vector(<2 x s32>)
+ %r:_(i32) = COPY $w0
+ %q:_(i32) = COPY $w1
+ %build_vector:_(<2 x i32>) = G_BUILD_VECTOR %r, %q
+ $d0 = COPY %build_vector(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -82,9 +82,9 @@ body: |
; LOWER-LABEL: name: dont_combine_zero
; LOWER: liveins: $d0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %r:_(s8) = G_CONSTANT i8 0
- ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8)
- ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>)
+ ; LOWER-NEXT: %r:_(i8) = G_CONSTANT i8 0
+ ; LOWER-NEXT: %build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8)
+ ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x i8>)
; LOWER-NEXT: RET_ReallyLR implicit $d0
;
; SELECT-LABEL: name: dont_combine_zero
@@ -94,9 +94,9 @@ body: |
; SELECT-NEXT: %build_vector:fpr64 = COPY [[MOVIv2d_ns]].dsub
; SELECT-NEXT: $d0 = COPY %build_vector
; SELECT-NEXT: RET_ReallyLR implicit $d0
- %r:_(s8) = G_CONSTANT i8 0
- %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
- $d0 = COPY %build_vector(<8 x s8>)
+ %r:_(i8) = G_CONSTANT i8 0
+ %build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
+ $d0 = COPY %build_vector(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -111,9 +111,9 @@ body: |
; LOWER-LABEL: name: dont_combine_all_ones
; LOWER: liveins: $d0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %r:_(s8) = G_CONSTANT i8 -1
- ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8)
- ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>)
+ ; LOWER-NEXT: %r:_(i8) = G_CONSTANT i8 -1
+ ; LOWER-NEXT: %build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8), %r(i8)
+ ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x i8>)
; LOWER-NEXT: RET_ReallyLR implicit $d0
;
; SELECT-LABEL: name: dont_combine_all_ones
@@ -122,9 +122,9 @@ body: |
; SELECT-NEXT: %build_vector:fpr64 = MOVID 255
; SELECT-NEXT: $d0 = COPY %build_vector
; SELECT-NEXT: RET_ReallyLR implicit $d0
- %r:_(s8) = G_CONSTANT i8 -1
- %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
- $d0 = COPY %build_vector(<8 x s8>)
+ %r:_(i8) = G_CONSTANT i8 -1
+ %build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
+ $d0 = COPY %build_vector(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -139,11 +139,11 @@ body: |
; LOWER-LABEL: name: all_zeros_pat_example
; LOWER: liveins: $d0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %v:_(<2 x s32>) = COPY $d0
- ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 0
- ; LOWER-NEXT: %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst(s32), %cst(s32)
- ; LOWER-NEXT: %sub:_(<2 x s32>) = G_SUB %build_vector, %v
- ; LOWER-NEXT: $d0 = COPY %sub(<2 x s32>)
+ ; LOWER-NEXT: %v:_(<2 x i32>) = COPY $d0
+ ; LOWER-NEXT: %cst:_(i32) = G_CONSTANT i32 0
+ ; LOWER-NEXT: %build_vector:_(<2 x i32>) = G_BUILD_VECTOR %cst(i32), %cst(i32)
+ ; LOWER-NEXT: %sub:_(<2 x i32>) = G_SUB %build_vector, %v
+ ; LOWER-NEXT: $d0 = COPY %sub(<2 x i32>)
; LOWER-NEXT: RET_ReallyLR implicit $d0
;
; SELECT-LABEL: name: all_zeros_pat_example
@@ -153,11 +153,11 @@ body: |
; SELECT-NEXT: %sub:fpr64 = NEGv2i32 %v
; SELECT-NEXT: $d0 = COPY %sub
; SELECT-NEXT: RET_ReallyLR implicit $d0
- %v:_(<2 x s32>) = COPY $d0
- %cst:_(s32) = G_CONSTANT i32 0
- %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst
- %sub:_(<2 x s32>) = G_SUB %build_vector, %v
- $d0 = COPY %sub(<2 x s32>)
+ %v:_(<2 x i32>) = COPY $d0
+ %cst:_(i32) = G_CONSTANT i32 0
+ %build_vector:_(<2 x i32>) = G_BUILD_VECTOR %cst, %cst
+ %sub:_(<2 x i32>) = G_SUB %build_vector, %v
+ $d0 = COPY %sub(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -172,13 +172,13 @@ body: |
; LOWER-LABEL: name: all_ones_pat_example
; LOWER: liveins: $d0, $d1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %v0:_(<2 x s32>) = COPY $d0
- ; LOWER-NEXT: %v1:_(<2 x s32>) = COPY $d1
- ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 -1
- ; LOWER-NEXT: %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst(s32), %cst(s32)
- ; LOWER-NEXT: %xor:_(<2 x s32>) = G_XOR %v0, %build_vector
- ; LOWER-NEXT: %and:_(<2 x s32>) = G_AND %v1, %xor
- ; LOWER-NEXT: $d0 = COPY %and(<2 x s32>)
+ ; LOWER-NEXT: %v0:_(<2 x i32>) = COPY $d0
+ ; LOWER-NEXT: %v1:_(<2 x i32>) = COPY $d1
+ ; LOWER-NEXT: %cst:_(i32) = G_CONSTANT i32 -1
+ ; LOWER-NEXT: %build_vector:_(<2 x i32>) = G_BUILD_VECTOR %cst(i32), %cst(i32)
+ ; LOWER-NEXT: %xor:_(<2 x i32>) = G_XOR %v0, %build_vector
+ ; LOWER-NEXT: %and:_(<2 x i32>) = G_AND %v1, %xor
+ ; LOWER-NEXT: $d0 = COPY %and(<2 x i32>)
; LOWER-NEXT: RET_ReallyLR implicit $d0
;
; SELECT-LABEL: name: all_ones_pat_example
@@ -189,11 +189,11 @@ body: |
; SELECT-NEXT: %and:fpr64 = BICv8i8 %v1, %v0
; SELECT-NEXT: $d0 = COPY %and
; SELECT-NEXT: RET_ReallyLR implicit $d0
- %v0:_(<2 x s32>) = COPY $d0
- %v1:_(<2 x s32>) = COPY $d1
- %cst:_(s32) = G_CONSTANT i32 -1
- %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst
- %xor:_(<2 x s32>) = G_XOR %v0, %build_vector
- %and:_(<2 x s32>) = G_AND %v1, %xor
- $d0 = COPY %and(<2 x s32>)
+ %v0:_(<2 x i32>) = COPY $d0
+ %v1:_(<2 x i32>) = COPY $d1
+ %cst:_(i32) = G_CONSTANT i32 -1
+ %build_vector:_(<2 x i32>) = G_BUILD_VECTOR %cst, %cst
+ %xor:_(<2 x i32>) = G_XOR %v0, %build_vector
+ %and:_(<2 x i32>) = G_AND %v1, %xor
+ $d0 = COPY %and(<2 x i32>)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-ext.mir
index 8dedb26dac2e1..35cc62293200b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-ext.mir
@@ -17,8 +17,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<8 x s8>) = COPY $d0
; CHECK-NEXT: %v2:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v1, %v2, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v1, %v2, [[C]](i32)
; CHECK-NEXT: $d0 = COPY %shuf(<8 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%v1:_(<8 x s8>) = COPY $d0
@@ -40,8 +40,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<8 x s8>) = COPY $d0
; CHECK-NEXT: %v2:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v2, %v1, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v2, %v1, [[C]](i32)
; CHECK-NEXT: $d0 = COPY %shuf(<8 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%v1:_(<8 x s8>) = COPY $d0
@@ -63,8 +63,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: %v2:_(<16 x s8>) = COPY $q1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: %shuf:_(<16 x s8>) = G_EXT %v1, %v2, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: %shuf:_(<16 x s8>) = G_EXT %v1, %v2, [[C]](i32)
; CHECK-NEXT: $q0 = COPY %shuf(<16 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%v1:_(<16 x s8>) = COPY $q0
@@ -86,8 +86,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: %v2:_(<16 x s8>) = COPY $q1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: %shuf:_(<16 x s8>) = G_EXT %v2, %v1, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: %shuf:_(<16 x s8>) = G_EXT %v2, %v1, [[C]](i32)
; CHECK-NEXT: $q0 = COPY %shuf(<16 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%v1:_(<16 x s8>) = COPY $q0
@@ -109,8 +109,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<4 x s16>) = COPY $d0
; CHECK-NEXT: %v2:_(<4 x s16>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: %shuf:_(<4 x s16>) = G_EXT %v1, %v2, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: %shuf:_(<4 x s16>) = G_EXT %v1, %v2, [[C]](i32)
; CHECK-NEXT: $d0 = COPY %shuf(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%v1:_(<4 x s16>) = COPY $d0
@@ -132,8 +132,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: %v2:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_EXT %v1, %v2, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_EXT %v1, %v2, [[C]](i32)
; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%v1:_(<4 x s32>) = COPY $q0
@@ -157,8 +157,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<8 x s8>) = COPY $d0
; CHECK-NEXT: %v2:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v1, %v2, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v1, %v2, [[C]](i32)
; CHECK-NEXT: $d0 = COPY %shuf(<8 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%v1:_(<8 x s8>) = COPY $d0
@@ -182,8 +182,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<8 x s8>) = COPY $d0
; CHECK-NEXT: %v2:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v2, %v1, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v2, %v1, [[C]](i32)
; CHECK-NEXT: $d0 = COPY %shuf(<8 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%v1:_(<8 x s8>) = COPY $d0
@@ -207,8 +207,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: %v2:_(<16 x s8>) = COPY $q1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: %shuf:_(<16 x s8>) = G_EXT %v2, %v1, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: %shuf:_(<16 x s8>) = G_EXT %v2, %v1, [[C]](i32)
; CHECK-NEXT: $q0 = COPY %shuf(<16 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%v1:_(<16 x s8>) = COPY $q0
@@ -232,8 +232,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: %v2:_(<8 x s16>) = COPY $q1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: %shuf:_(<8 x s16>) = G_EXT %v2, %v1, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: %shuf:_(<8 x s16>) = G_EXT %v2, %v1, [[C]](i32)
; CHECK-NEXT: $q0 = COPY %shuf(<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%v1:_(<8 x s16>) = COPY $q0
@@ -255,8 +255,8 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<8 x s16>) = G_DUPLANE16 %v1, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<8 x s16>) = G_DUPLANE16 %v1, [[C]](i64)
; CHECK-NEXT: $q0 = COPY %shuf(<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%v1:_(<8 x s16>) = COPY $q0
@@ -277,8 +277,8 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: %shuf:_(<2 x s64>) = G_EXT %v1, %v1, [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: %shuf:_(<2 x s64>) = G_EXT %v1, %v1, [[C]](i32)
; CHECK-NEXT: $q0 = COPY %shuf(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%v1:_(<2 x s64>) = COPY $q0
@@ -299,8 +299,8 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<2 x s64>) = G_DUPLANE64 %v1, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<2 x s64>) = G_DUPLANE64 %v1, [[C]](i64)
; CHECK-NEXT: $q0 = COPY %shuf(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%v1:_(<2 x s64>) = COPY $q0
@@ -321,8 +321,8 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: %shuf:_(<2 x s64>) = G_DUPLANE64 %v1, [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: %shuf:_(<2 x s64>) = G_DUPLANE64 %v1, [[C]](i64)
; CHECK-NEXT: $q0 = COPY %shuf(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%v1:_(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir
index 1d24f8acfbc53..c387f1cc8d67c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-rev.mir
@@ -38,10 +38,10 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[COPY]](<2 x s32>), [[DEF]](<2 x s32>)
- ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[CONCAT_VECTORS]], [[C]](s64)
+ ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[CONCAT_VECTORS]], [[C]](i64)
; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-duplane.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-duplane.mir
index c0cfbb8efdb47..5297ecd7019bb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-duplane.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-duplane.mir
@@ -15,8 +15,8 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[DUPLANE64_:%[0-9]+]]:_(<2 x s64>) = G_DUPLANE64 [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[DUPLANE64_:%[0-9]+]]:_(<2 x s64>) = G_DUPLANE64 [[COPY]], [[C]](i64)
; CHECK-NEXT: $q0 = COPY [[DUPLANE64_]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
;
@@ -47,8 +47,8 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<4 x s32>) = G_DUPLANE32 [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<4 x s32>) = G_DUPLANE32 [[COPY]], [[C]](i64)
; CHECK-NEXT: $q0 = COPY [[DUPLANE32_]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
;
@@ -79,8 +79,8 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[DUPLANE16_:%[0-9]+]]:_(<8 x s16>) = G_DUPLANE16 [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[DUPLANE16_:%[0-9]+]]:_(<8 x s16>) = G_DUPLANE16 [[COPY]], [[C]](i64)
; CHECK-NEXT: $q0 = COPY [[DUPLANE16_]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
;
@@ -111,8 +111,8 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[DUPLANE8_:%[0-9]+]]:_(<16 x s8>) = G_DUPLANE8 [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[DUPLANE8_:%[0-9]+]]:_(<16 x s8>) = G_DUPLANE8 [[COPY]], [[C]](i64)
; CHECK-NEXT: $q0 = COPY [[DUPLANE8_]](<16 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
;
@@ -150,10 +150,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[COPY1]](<2 x s32>), [[DEF]](<2 x s32>)
- ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[CONCAT_VECTORS]], [[C]](s64)
+ ; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[CONCAT_VECTORS]], [[C]](i64)
; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
index 3906bbe94c620..650a4fb8a8232 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
@@ -363,8 +363,8 @@ body: |
; CHECK-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[IVEC2]], %d(s32), [[C3]](i64)
; CHECK-NEXT: %buildvec:_(<4 x s32>) = COPY [[IVEC3]](<4 x s32>)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_DUPLANE32 %buildvec, [[C4]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_DUPLANE32 %buildvec, [[C4]](i64)
; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%lane:_(s32) = COPY $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
index d083e49e1e596..315ca9360dca6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
@@ -22,11 +22,11 @@ body: |
; LOWER-LABEL: name: swap_sextinreg_lhs
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SEXT_INREG %reg, 8
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sle), %cmp_rhs(i64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: swap_sextinreg_lhs
@@ -40,11 +40,11 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
- %cmp_rhs:_(s64) = COPY $x1
- %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cmp_lhs:_(i64) = G_SEXT_INREG %reg, 8
+ %cmp_rhs:_(i64) = COPY $x1
+ %cmp:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -62,14 +62,14 @@ body: |
; LOWER-LABEL: name: dont_swap_more_than_one_use
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8
- ; LOWER-NEXT: %reg1:_(s64) = COPY $x1
- ; LOWER-NEXT: %cmp1:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %reg1
- ; LOWER-NEXT: %add:_(s64) = G_ADD %cmp_lhs, %reg0
- ; LOWER-NEXT: %cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add
- ; LOWER-NEXT: $w0 = COPY %cmp2(s32)
- ; LOWER-NEXT: $w1 = COPY %cmp1(s32)
+ ; LOWER-NEXT: %reg0:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SEXT_INREG %reg0, 8
+ ; LOWER-NEXT: %reg1:_(i64) = COPY $x1
+ ; LOWER-NEXT: %cmp1:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %reg1
+ ; LOWER-NEXT: %add:_(i64) = G_ADD %cmp_lhs, %reg0
+ ; LOWER-NEXT: %cmp2:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %add
+ ; LOWER-NEXT: $w0 = COPY %cmp2(i32)
+ ; LOWER-NEXT: $w1 = COPY %cmp1(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0, implicit $w1
;
; SELECT-LABEL: name: dont_swap_more_than_one_use
@@ -86,16 +86,16 @@ body: |
; SELECT-NEXT: $w0 = COPY %cmp2
; SELECT-NEXT: $w1 = COPY %cmp1
; SELECT-NEXT: RET_ReallyLR implicit $w0, implicit $w1
- %reg0:_(s64) = COPY $x0
- %cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8
- %reg1:_(s64) = COPY $x1
- %cmp1:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %reg1
+ %reg0:_(i64) = COPY $x0
+ %cmp_lhs:_(i64) = G_SEXT_INREG %reg0, 8
+ %reg1:_(i64) = COPY $x1
+ %cmp1:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %reg1
- %add:_(s64) = G_ADD %cmp_lhs(s64), %reg0
- %cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add
+ %add:_(i64) = G_ADD %cmp_lhs(i64), %reg0
+ %cmp2:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %add
- $w0 = COPY %cmp2(s32)
- $w1 = COPY %cmp1(s32)
+ $w0 = COPY %cmp2(i32)
+ $w1 = COPY %cmp1(i32)
RET_ReallyLR implicit $w0, implicit $w1
...
@@ -112,11 +112,11 @@ body: |
; LOWER-LABEL: name: dont_swap_legal_arith_immed_on_rhs
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
- ; LOWER-NEXT: %cmp_rhs:_(s64) = G_CONSTANT i64 12
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SEXT_INREG %reg, 8
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = G_CONSTANT i64 12
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: dont_swap_legal_arith_immed_on_rhs
@@ -128,11 +128,11 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
- %cmp_rhs:_(s64) = G_CONSTANT i64 12
- %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cmp_lhs:_(i64) = G_SEXT_INREG %reg, 8
+ %cmp_rhs:_(i64) = G_CONSTANT i64 12
+ %cmp:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -149,11 +149,11 @@ body: |
; LOWER-LABEL: name: swap_non_arith_immed_on_rhs
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg:_(s64) = COPY $x0
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
- ; LOWER-NEXT: %cmp_rhs:_(s64) = G_CONSTANT i64 1234567
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SEXT_INREG %reg, 8
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = G_CONSTANT i64 1234567
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sle), %cmp_rhs(i64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: swap_non_arith_immed_on_rhs
@@ -168,11 +168,11 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg:_(s64) = COPY $x0
- %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
- %cmp_rhs:_(s64) = G_CONSTANT i64 1234567
- %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %reg:_(i64) = COPY $x0
+ %cmp_lhs:_(i64) = G_SEXT_INREG %reg, 8
+ %cmp_rhs:_(i64) = G_CONSTANT i64 1234567
+ %cmp:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -186,12 +186,12 @@ body: |
; LOWER-LABEL: name: swap_and_lhs_0xFF
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
- ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 255
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %and_lhs:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(i64) = G_CONSTANT i64 255
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_AND %and_lhs, %cst
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sle), %cmp_rhs(i64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: swap_and_lhs_0xFF
@@ -205,14 +205,14 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s64) = COPY $x1
+ %cmp_rhs:_(i64) = COPY $x1
- %and_lhs:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 255
- %cmp_lhs:_(s64) = G_AND %and_lhs, %cst(s64)
+ %and_lhs:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 255
+ %cmp_lhs:_(i64) = G_AND %and_lhs, %cst(i64)
- %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -226,12 +226,12 @@ body: |
; LOWER-LABEL: name: swap_and_lhs_0xFFFF
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 65535
- ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %cst:_(i64) = G_CONSTANT i64 65535
+ ; LOWER-NEXT: %and_lhs:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_AND %and_lhs, %cst
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sle), %cmp_rhs(i64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: swap_and_lhs_0xFFFF
@@ -245,14 +245,14 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s64) = COPY $x1
+ %cmp_rhs:_(i64) = COPY $x1
- %cst:_(s64) = G_CONSTANT i64 65535
- %and_lhs:_(s64) = COPY $x0
- %cmp_lhs:_(s64) = G_AND %and_lhs, %cst(s64)
+ %cst:_(i64) = G_CONSTANT i64 65535
+ %and_lhs:_(i64) = COPY $x0
+ %cmp_lhs:_(i64) = G_AND %and_lhs, %cst(i64)
- %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -266,12 +266,12 @@ body: |
; LOWER-LABEL: name: swap_and_lhs_0xFFFFFFFF
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
- ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 4294967295
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %and_lhs:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(i64) = G_CONSTANT i64 4294967295
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_AND %and_lhs, %cst
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sle), %cmp_rhs(i64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: swap_and_lhs_0xFFFFFFFF
@@ -285,14 +285,14 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s64) = COPY $x1
+ %cmp_rhs:_(i64) = COPY $x1
- %and_lhs:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 4294967295
- %cmp_lhs:_(s64) = G_AND %and_lhs, %cst(s64)
+ %and_lhs:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 4294967295
+ %cmp_lhs:_(i64) = G_AND %and_lhs, %cst(i64)
- %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -308,12 +308,12 @@ body: |
; LOWER-LABEL: name: dont_swap_and_lhs_wrong_mask
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
- ; LOWER-NEXT: %not_an_extend_mask:_(s64) = G_CONSTANT i64 7
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %not_an_extend_mask
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %and_lhs:_(i64) = COPY $x0
+ ; LOWER-NEXT: %not_an_extend_mask:_(i64) = G_CONSTANT i64 7
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_AND %and_lhs, %not_an_extend_mask
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: dont_swap_and_lhs_wrong_mask
@@ -326,14 +326,14 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s64) = COPY $x1
+ %cmp_rhs:_(i64) = COPY $x1
- %and_lhs:_(s64) = COPY $x0
- %not_an_extend_mask:_(s64) = G_CONSTANT i64 7
- %cmp_lhs:_(s64) = G_AND %and_lhs, %not_an_extend_mask(s64)
+ %and_lhs:_(i64) = COPY $x0
+ %not_an_extend_mask:_(i64) = G_CONSTANT i64 7
+ %cmp_lhs:_(i64) = G_AND %and_lhs, %not_an_extend_mask(i64)
- %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(sge), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -348,12 +348,12 @@ body: |
; LOWER-LABEL: name: swap_shl_lhs
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
- ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %shl_lhs:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(i64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SHL %shl_lhs, %cst(i64)
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sgt), %cmp_rhs(i64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: swap_shl_lhs
@@ -365,14 +365,14 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s64) = COPY $x1
+ %cmp_rhs:_(i64) = COPY $x1
- %shl_lhs:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 1
- %cmp_lhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
+ %shl_lhs:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 1
+ %cmp_lhs:_(i64) = G_SHL %shl_lhs, %cst(i64)
- %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(slt), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -387,12 +387,12 @@ body: |
; LOWER-LABEL: name: swap_ashr_lhs
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %ashr_lhs:_(s64) = COPY $x0
- ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_ASHR %ashr_lhs, %cst(s64)
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %ashr_lhs:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(i64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_ASHR %ashr_lhs, %cst(i64)
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sgt), %cmp_rhs(i64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: swap_ashr_lhs
@@ -404,14 +404,14 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s64) = COPY $x1
+ %cmp_rhs:_(i64) = COPY $x1
- %ashr_lhs:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 1
- %cmp_lhs:_(s64) = G_ASHR %ashr_lhs, %cst(s64)
+ %ashr_lhs:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 1
+ %cmp_lhs:_(i64) = G_ASHR %ashr_lhs, %cst(i64)
- %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(slt), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -426,12 +426,12 @@ body: |
; LOWER-LABEL: name: swap_lshr_lhs
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %lshr_lhs:_(s64) = COPY $x0
- ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_LSHR %lshr_lhs, %cst(s64)
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %lshr_lhs:_(i64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(i64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_LSHR %lshr_lhs, %cst(i64)
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(sgt), %cmp_rhs(i64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: swap_lshr_lhs
@@ -443,14 +443,14 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s64) = COPY $x1
+ %cmp_rhs:_(i64) = COPY $x1
- %lshr_lhs:_(s64) = COPY $x0
- %cst:_(s64) = G_CONSTANT i64 1
- %cmp_lhs:_(s64) = G_LSHR %lshr_lhs, %cst(s64)
+ %lshr_lhs:_(i64) = COPY $x0
+ %cst:_(i64) = G_CONSTANT i64 1
+ %cmp_lhs:_(i64) = G_LSHR %lshr_lhs, %cst(i64)
- %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(slt), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -467,12 +467,12 @@ body: |
; LOWER-LABEL: name: dont_swap_shift_s64_cst_too_large
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
- ; LOWER-NEXT: %too_large:_(s64) = G_CONSTANT i64 64
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %too_large(s64)
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %shl_lhs:_(i64) = COPY $x0
+ ; LOWER-NEXT: %too_large:_(i64) = G_CONSTANT i64 64
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SHL %shl_lhs, %too_large(i64)
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(slt), %cmp_lhs(i64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: dont_swap_shift_s64_cst_too_large
@@ -487,14 +487,14 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s64) = COPY $x1
+ %cmp_rhs:_(i64) = COPY $x1
- %shl_lhs:_(s64) = COPY $x0
- %too_large:_(s64) = G_CONSTANT i64 64
- %cmp_lhs:_(s64) = G_SHL %shl_lhs, %too_large(s64)
+ %shl_lhs:_(i64) = COPY $x0
+ %too_large:_(i64) = G_CONSTANT i64 64
+ %cmp_lhs:_(i64) = G_SHL %shl_lhs, %too_large(i64)
- %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(slt), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
@@ -512,12 +512,12 @@ body: |
; LOWER-LABEL: name: dont_swap_shift_s32_cst_too_large
; LOWER: liveins: $w0, $w1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s32) = COPY $w1
- ; LOWER-NEXT: %shl_lhs:_(s32) = COPY $w0
- ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 32
- ; LOWER-NEXT: %cmp_lhs:_(s32) = G_SHL %shl_lhs, %cst(s32)
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s32), %cmp_rhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i32) = COPY $w1
+ ; LOWER-NEXT: %shl_lhs:_(i32) = COPY $w0
+ ; LOWER-NEXT: %cst:_(i32) = G_CONSTANT i32 32
+ ; LOWER-NEXT: %cmp_lhs:_(i32) = G_SHL %shl_lhs, %cst(i32)
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(slt), %cmp_lhs(i32), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: dont_swap_shift_s32_cst_too_large
@@ -531,14 +531,14 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s32) = COPY $w1
+ %cmp_rhs:_(i32) = COPY $w1
- %shl_lhs:_(s32) = COPY $w0
- %cst:_(s32) = G_CONSTANT i32 32
- %cmp_lhs:_(s32) = G_SHL %shl_lhs, %cst(s32)
+ %shl_lhs:_(i32) = COPY $w0
+ %cst:_(i32) = G_CONSTANT i32 32
+ %cmp_lhs:_(i32) = G_SHL %shl_lhs, %cst(i32)
- %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s32), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(slt), %cmp_lhs(i32), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -557,12 +557,12 @@ body: |
; LOWER-LABEL: name: dont_swap_cmn_lhs_no_folding_opportunities
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %sub_rhs:_(s64) = COPY $x0
- ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %sub_rhs:_(i64) = COPY $x0
+ ; LOWER-NEXT: %zero:_(i64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SUB %zero, %sub_rhs
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(ne), %cmp_lhs(i64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: dont_swap_cmn_lhs_no_folding_opportunities
@@ -574,14 +574,14 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s64) = COPY $x1
+ %cmp_rhs:_(i64) = COPY $x1
- %sub_rhs:_(s64) = COPY $x0
- %zero:_(s64) = G_CONSTANT i64 0
- %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
+ %sub_rhs:_(i64) = COPY $x0
+ %zero:_(i64) = G_CONSTANT i64 0
+ %cmp_lhs:_(i64) = G_SUB %zero, %sub_rhs
- %cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(ne), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -600,14 +600,14 @@ body: |
; LOWER-LABEL: name: swap_cmn_lhs
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
- ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
- ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 63
- ; LOWER-NEXT: %sub_rhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_rhs(s64), %cmp_lhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = COPY $x1
+ ; LOWER-NEXT: %shl_lhs:_(i64) = COPY $x0
+ ; LOWER-NEXT: %zero:_(i64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: %cst:_(i64) = G_CONSTANT i64 63
+ ; LOWER-NEXT: %sub_rhs:_(i64) = G_SHL %shl_lhs, %cst(i64)
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SUB %zero, %sub_rhs
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(ne), %cmp_rhs(i64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: swap_cmn_lhs
@@ -619,16 +619,16 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %cmp_rhs:_(s64) = COPY $x1
+ %cmp_rhs:_(i64) = COPY $x1
- %shl_lhs:_(s64) = COPY $x0
- %zero:_(s64) = G_CONSTANT i64 0
- %cst:_(s64) = G_CONSTANT i64 63
- %sub_rhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
- %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
+ %shl_lhs:_(i64) = COPY $x0
+ %zero:_(i64) = G_CONSTANT i64 0
+ %cst:_(i64) = G_CONSTANT i64 63
+ %sub_rhs:_(i64) = G_SHL %shl_lhs, %cst(i64)
+ %cmp_lhs:_(i64) = G_SUB %zero, %sub_rhs
- %cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(ne), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -648,18 +648,18 @@ body: |
; LOWER-LABEL: name: dont_swap_cmn_lhs_when_rhs_more_profitable
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
- ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
- ; LOWER-NEXT: %shl_cst:_(s64) = G_CONSTANT i64 63
- ; LOWER-NEXT: %shl:_(s64) = G_SHL %reg0, %shl_cst(s64)
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %shl
- ; LOWER-NEXT: %reg1:_(s64) = COPY $x1
- ; LOWER-NEXT: %sext_in_reg:_(s64) = G_SEXT_INREG %reg1, 1
- ; LOWER-NEXT: %ashr_cst:_(s64) = G_CONSTANT i64 3
- ; LOWER-NEXT: %ashr:_(s64) = G_ASHR %sext_in_reg, %ashr_cst(s64)
- ; LOWER-NEXT: %cmp_rhs:_(s64) = G_SUB %zero, %ashr
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %zero:_(i64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: %reg0:_(i64) = COPY $x0
+ ; LOWER-NEXT: %shl_cst:_(i64) = G_CONSTANT i64 63
+ ; LOWER-NEXT: %shl:_(i64) = G_SHL %reg0, %shl_cst(i64)
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SUB %zero, %shl
+ ; LOWER-NEXT: %reg1:_(i64) = COPY $x1
+ ; LOWER-NEXT: %sext_in_reg:_(i64) = G_SEXT_INREG %reg1, 1
+ ; LOWER-NEXT: %ashr_cst:_(i64) = G_CONSTANT i64 3
+ ; LOWER-NEXT: %ashr:_(i64) = G_ASHR %sext_in_reg, %ashr_cst(i64)
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = G_SUB %zero, %ashr
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(eq), %cmp_lhs(i64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: dont_swap_cmn_lhs_when_rhs_more_profitable
@@ -674,21 +674,21 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %zero:_(s64) = G_CONSTANT i64 0
+ %zero:_(i64) = G_CONSTANT i64 0
- %reg0:_(s64) = COPY $x0
- %shl_cst:_(s64) = G_CONSTANT i64 63
- %shl:_(s64) = G_SHL %reg0, %shl_cst(s64)
- %cmp_lhs:_(s64) = G_SUB %zero, %shl
+ %reg0:_(i64) = COPY $x0
+ %shl_cst:_(i64) = G_CONSTANT i64 63
+ %shl:_(i64) = G_SHL %reg0, %shl_cst(i64)
+ %cmp_lhs:_(i64) = G_SUB %zero, %shl
- %reg1:_(s64) = COPY $x1
- %sext_in_reg:_(s64) = G_SEXT_INREG %reg1, 1
- %ashr_cst:_(s64) = G_CONSTANT i64 3
- %ashr:_(s64) = G_ASHR %sext_in_reg, %ashr_cst(s64)
- %cmp_rhs:_(s64) = G_SUB %zero, %ashr
+ %reg1:_(i64) = COPY $x1
+ %sext_in_reg:_(i64) = G_SEXT_INREG %reg1, 1
+ %ashr_cst:_(i64) = G_CONSTANT i64 3
+ %ashr:_(i64) = G_ASHR %sext_in_reg, %ashr_cst(i64)
+ %cmp_rhs:_(i64) = G_SUB %zero, %ashr
- %cmp:_(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(eq), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -704,16 +704,16 @@ body: |
; LOWER-LABEL: name: dont_swap_rhs_with_supported_extend
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
- ; LOWER-NEXT: %lhs_cst:_(s64) = G_CONSTANT i64 1
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %reg0, %lhs_cst(s64)
- ; LOWER-NEXT: %reg1:_(s64) = COPY $x1
- ; LOWER-NEXT: %and_mask:_(s64) = G_CONSTANT i64 255
- ; LOWER-NEXT: %and:_(s64) = G_AND %reg1, %and_mask
- ; LOWER-NEXT: %rhs_cst:_(s64) = G_CONSTANT i64 1
- ; LOWER-NEXT: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg0:_(i64) = COPY $x0
+ ; LOWER-NEXT: %lhs_cst:_(i64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SHL %reg0, %lhs_cst(i64)
+ ; LOWER-NEXT: %reg1:_(i64) = COPY $x1
+ ; LOWER-NEXT: %and_mask:_(i64) = G_CONSTANT i64 255
+ ; LOWER-NEXT: %and:_(i64) = G_AND %reg1, %and_mask
+ ; LOWER-NEXT: %rhs_cst:_(i64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = G_ASHR %and, %rhs_cst(i64)
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(slt), %cmp_lhs(i64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: dont_swap_rhs_with_supported_extend
@@ -727,18 +727,18 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg0:_(s64) = COPY $x0
- %lhs_cst:_(s64) = G_CONSTANT i64 1
- %cmp_lhs:_(s64) = G_SHL %reg0, %lhs_cst(s64)
-
- %reg1:_(s64) = COPY $x1
- %and_mask:_(s64) = G_CONSTANT i64 255
- %and:_(s64) = G_AND %reg1, %and_mask(s64)
- %rhs_cst:_(s64) = G_CONSTANT i64 1
- %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
-
- %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %reg0:_(i64) = COPY $x0
+ %lhs_cst:_(i64) = G_CONSTANT i64 1
+ %cmp_lhs:_(i64) = G_SHL %reg0, %lhs_cst(i64)
+
+ %reg1:_(i64) = COPY $x1
+ %and_mask:_(i64) = G_CONSTANT i64 255
+ %and:_(i64) = G_AND %reg1, %and_mask(i64)
+ %rhs_cst:_(i64) = G_CONSTANT i64 1
+ %cmp_rhs:_(i64) = G_ASHR %and, %rhs_cst(i64)
+
+ %cmp:_(i32) = G_ICMP intpred(slt), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
@@ -758,15 +758,15 @@ body: |
; LOWER-LABEL: name: swap_rhs_with_supported_extend
; LOWER: liveins: $x0, $x1
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
- ; LOWER-NEXT: %and_mask:_(s64) = G_CONSTANT i64 255
- ; LOWER-NEXT: %and:_(s64) = G_AND %reg0, %and_mask
- ; LOWER-NEXT: %lhs_cst:_(s64) = G_CONSTANT i64 1
- ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %and, %lhs_cst(s64)
- ; LOWER-NEXT: %rhs_cst:_(s64) = G_CONSTANT i64 5
- ; LOWER-NEXT: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
- ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_rhs(s64), %cmp_lhs
- ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: %reg0:_(i64) = COPY $x0
+ ; LOWER-NEXT: %and_mask:_(i64) = G_CONSTANT i64 255
+ ; LOWER-NEXT: %and:_(i64) = G_AND %reg0, %and_mask
+ ; LOWER-NEXT: %lhs_cst:_(i64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_lhs:_(i64) = G_SHL %and, %lhs_cst(i64)
+ ; LOWER-NEXT: %rhs_cst:_(i64) = G_CONSTANT i64 5
+ ; LOWER-NEXT: %cmp_rhs:_(i64) = G_ASHR %and, %rhs_cst(i64)
+ ; LOWER-NEXT: %cmp:_(i32) = G_ICMP intpred(slt), %cmp_rhs(i64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(i32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
;
; SELECT-LABEL: name: swap_rhs_with_supported_extend
@@ -781,16 +781,16 @@ body: |
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
- %reg0:_(s64) = COPY $x0
- %and_mask:_(s64) = G_CONSTANT i64 255
- %and:_(s64) = G_AND %reg0, %and_mask(s64)
+ %reg0:_(i64) = COPY $x0
+ %and_mask:_(i64) = G_CONSTANT i64 255
+ %and:_(i64) = G_AND %reg0, %and_mask(i64)
- %lhs_cst:_(s64) = G_CONSTANT i64 1
- %cmp_lhs:_(s64) = G_SHL %and, %lhs_cst(s64)
+ %lhs_cst:_(i64) = G_CONSTANT i64 1
+ %cmp_lhs:_(i64) = G_SHL %and, %lhs_cst(i64)
- %rhs_cst:_(s64) = G_CONSTANT i64 5
- %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
+ %rhs_cst:_(i64) = G_CONSTANT i64 5
+ %cmp_rhs:_(i64) = G_ASHR %and, %rhs_cst(i64)
- %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_lhs(s64), %cmp_rhs
- $w0 = COPY %cmp(s32)
+ %cmp:_(i32) = G_ICMP intpred(sgt), %cmp_lhs(i64), %cmp_rhs
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir
index 2fc90e4bf05a1..0034f76d1af3c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-zip.mir
@@ -166,8 +166,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[EXT:%[0-9]+]]:_(<2 x s64>) = G_EXT [[COPY]], [[COPY1]], [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[EXT:%[0-9]+]]:_(<2 x s64>) = G_EXT [[COPY]], [[COPY1]], [[C]](i32)
; CHECK-NEXT: $q0 = COPY [[EXT]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir
index d6288d10b2b79..819a81a472788 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extractvec-faddp.mir
@@ -15,10 +15,10 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C1]](i64)
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[EVEC]], [[EVEC1]]
; CHECK-NEXT: $d0 = COPY [[FADD]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -47,10 +47,10 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C1]](i64)
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[EVEC]], [[EVEC1]]
; CHECK-NEXT: $d0 = COPY [[FADD]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -79,10 +79,10 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C1]](i64)
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[EVEC]], [[EVEC1]]
; CHECK-NEXT: $s0 = COPY [[FADD]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
@@ -111,10 +111,10 @@ body: |
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C1]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](i64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C1]](i64)
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[EVEC]], [[EVEC1]]
; CHECK-NEXT: $s0 = COPY [[FADD]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll b/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
index 5e88b22c345bb..736b0fa61c8cd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
@@ -18,10 +18,10 @@ define <4 x ptr> @pr168872(<4 x ptr> %ptrs) {
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[C]](p0), [[C]](p0)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), [[BITCAST]](<2 x p0>), [[BUILD_VECTOR]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x i64>) = G_ICMP intpred(ugt), [[BITCAST1]](<2 x p0>), [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BITCAST]](<2 x p0>)
- ; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BITCAST1]](<2 x p0>)
- ; CHECK-NEXT: [[PTRTOINT2:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
- ; CHECK-NEXT: [[PTRTOINT3:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x i64>) = G_PTRTOINT [[BITCAST]](<2 x p0>)
+ ; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x i64>) = G_PTRTOINT [[BITCAST1]](<2 x p0>)
+ ; CHECK-NEXT: [[PTRTOINT2:%[0-9]+]]:_(<2 x i64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
+ ; CHECK-NEXT: [[PTRTOINT3:%[0-9]+]]:_(<2 x i64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i64>) = G_BUILD_VECTOR [[C1]](i64), [[C1]](i64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x i64>) = G_XOR [[ICMP]], [[BUILD_VECTOR1]]
@@ -30,10 +30,10 @@ define <4 x ptr> @pr168872(<4 x ptr> %ptrs) {
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x i64>) = G_AND [[PTRTOINT1]], [[ICMP1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x i64>) = G_AND [[PTRTOINT2]], [[XOR]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x i64>) = G_AND [[PTRTOINT3]], [[XOR1]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
- ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR]](<2 x s64>)
- ; CHECK-NEXT: [[INTTOPTR1:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR1]](<2 x s64>)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x i64>) = G_OR [[AND]], [[AND2]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x i64>) = G_OR [[AND1]], [[AND3]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR]](<2 x i64>)
+ ; CHECK-NEXT: [[INTTOPTR1:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR1]](<2 x i64>)
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[INTTOPTR]](<2 x p0>)
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x i64>) = G_BITCAST [[INTTOPTR1]](<2 x p0>)
; CHECK-NEXT: $q0 = COPY [[BITCAST2]](<2 x i64>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
index 8f19649339823..7867d54b0727f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
@@ -13,10 +13,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %binop_lhs:_(s64) = COPY $x0
; CHECK-NEXT: %binop_rhs:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %binop_lhs(s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC %binop_rhs(s64)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ADD]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC %binop_lhs(s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC %binop_rhs(s64)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ADD]](i32)
; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%binop_lhs:_(s64) = COPY $x0
@@ -38,10 +38,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %binop_lhs:_(s64) = COPY $x0
; CHECK-NEXT: %binop_rhs:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %binop_lhs(s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC %binop_rhs(s64)
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC %binop_lhs(s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC %binop_rhs(s64)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](i32)
; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%binop_lhs:_(s64) = COPY $x0
@@ -63,10 +63,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %binop_lhs:_(s64) = COPY $x0
; CHECK-NEXT: %binop_rhs:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %binop_lhs(s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC %binop_rhs(s64)
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[MUL]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC %binop_lhs(s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC %binop_rhs(s64)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(i32) = G_MUL [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[MUL]](i32)
; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%binop_lhs:_(s64) = COPY $x0
@@ -88,10 +88,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %binop_lhs:_(s64) = COPY $x0
; CHECK-NEXT: %binop_rhs:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %binop_lhs(s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC %binop_rhs(s64)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC %binop_lhs(s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC %binop_rhs(s64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](i32)
; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%binop_lhs:_(s64) = COPY $x0
@@ -137,10 +137,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %binop_lhs:_(s64) = COPY $x0
; CHECK-NEXT: %binop_rhs:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %binop_lhs(s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC %binop_rhs(s64)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[XOR]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC %binop_lhs(s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC %binop_rhs(s64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(i32) = G_XOR [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[XOR]](i32)
; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%binop_lhs:_(s64) = COPY $x0
@@ -162,10 +162,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %binop_lhs:_(s64) = COPY $x0
; CHECK-NEXT: %binop_rhs:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %binop_lhs(s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC %binop_rhs(s64)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ADD]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC %binop_lhs(s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC %binop_rhs(s64)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ADD]](i32)
; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%binop_lhs:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
index 88ecbd6bb9341..651079f418ef6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
@@ -169,7 +169,7 @@ body: |
; CHECK-NEXT: %fpr:fpr(s64) = COPY $d0
; CHECK-NEXT: %fpr_assert_sext:fpr(s64) = G_ASSERT_SEXT %fpr, 32
; CHECK-NEXT: %gpr:gpr(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(i64) = COPY %gpr(s64)
; CHECK-NEXT: %select:fpr(s64) = G_SELECT %w0(s32), %fpr_assert_sext, [[COPY]]
; CHECK-NEXT: $d0 = COPY %select(s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -196,15 +196,15 @@ body: |
; CHECK-NEXT: %copy1:fpr(s32) = COPY $s0
; CHECK-NEXT: %copy2:gpr(s32) = COPY $w1
; CHECK-NEXT: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy1, 16
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
- ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), %copy2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(i32) = COPY %copy1(s32)
+ ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](i32), %copy2
; CHECK-NEXT: G_BRCOND %cmp(s32), %bb.1
; CHECK-NEXT: G_BR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
@@ -248,16 +248,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy1:fpr(s32) = COPY $s0
; CHECK-NEXT: %copy2:fpr(s32) = COPY $s1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %copy2(s32)
- ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(i32) = COPY %copy1(s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(i32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](i32), [[COPY1]]
; CHECK-NEXT: G_BRCOND %cmp(s32), %bb.1
; CHECK-NEXT: G_BR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
index 16ab28f4bd46a..ea811fa590f8e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
@@ -169,7 +169,7 @@ body: |
; CHECK-NEXT: %fpr:fpr(s64) = COPY $d0
; CHECK-NEXT: %fpr_assert_zext:fpr(s64) = G_ASSERT_ZEXT %fpr, 32
; CHECK-NEXT: %gpr:gpr(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(i64) = COPY %gpr(s64)
; CHECK-NEXT: %select:fpr(s64) = G_SELECT %w0(s32), %fpr_assert_zext, [[COPY]]
; CHECK-NEXT: $d0 = COPY %select(s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -196,15 +196,15 @@ body: |
; CHECK-NEXT: %copy1:fpr(s32) = COPY $s0
; CHECK-NEXT: %copy2:gpr(s32) = COPY $w1
; CHECK-NEXT: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy1, 16
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
- ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), %copy2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(i32) = COPY %copy1(s32)
+ ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](i32), %copy2
; CHECK-NEXT: G_BRCOND %cmp(s32), %bb.1
; CHECK-NEXT: G_BR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
@@ -248,16 +248,16 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy1:fpr(s32) = COPY $s0
; CHECK-NEXT: %copy2:fpr(s32) = COPY $s1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %copy2(s32)
- ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(i32) = COPY %copy1(s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(i32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](i32), [[COPY1]]
; CHECK-NEXT: G_BRCOND %cmp(s32), %bb.1
; CHECK-NEXT: G_BR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %bb1_val:fpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
index 66c8c2efda9bc..8b9957ba8dc49 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
@@ -173,8 +173,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK-NEXT: %trunc:gpr(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gpr(s32) = G_ANYEXT %trunc(s8)
- ; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<16 x s8>) = G_DUP [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gpr(i32) = G_ANYEXT %trunc(s8)
+ ; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<16 x s8>) = G_DUP [[ANYEXT]](i32)
; CHECK-NEXT: $q0 = COPY [[DUP]](<16 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(s32) = COPY $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir
index adc340df14e37..ccb833585c315 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fmaximum.mir
@@ -52,8 +52,8 @@ body: |
; CHECK-LABEL: name: create_copy
; CHECK: %a:gpr(s32) = COPY $w0
; CHECK-NEXT: %b:gpr(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY %a(s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s32) = COPY %b(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(i32) = COPY %a(s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(i32) = COPY %b(s32)
; CHECK-NEXT: %needs_fpr:fpr(s32) = G_FMAXIMUM [[COPY]], [[COPY1]]
; CHECK-NEXT: $s0 = COPY %needs_fpr(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir
index 6086c44b0bcc9..bbc03e52fc442 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fminimum.mir
@@ -52,8 +52,8 @@ body: |
; CHECK-LABEL: name: create_copy
; CHECK: %a:gpr(s32) = COPY $w0
; CHECK-NEXT: %b:gpr(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY %a(s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s32) = COPY %b(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(i32) = COPY %a(s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(i32) = COPY %b(s32)
; CHECK-NEXT: %needs_fpr:fpr(s32) = G_FMINIMUM [[COPY]], [[COPY1]]
; CHECK-NEXT: $s0 = COPY %needs_fpr(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
index 46dbc1556fb1d..bd33a589d9d5e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
@@ -48,8 +48,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY [[COPY]](s64)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:fpr(s32), [[UV1:%[0-9]+]]:fpr(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(i64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:fpr(s32), [[UV1:%[0-9]+]]:fpr(s32) = G_UNMERGE_VALUES [[COPY1]](i64)
; CHECK-NEXT: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(uno), [[UV]](s32), [[UV1]]
; CHECK-NEXT: $w0 = COPY [[FCMP]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -94,7 +94,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s32) = COPY $w2
; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[COPY1]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(s32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(i32) = COPY [[COPY2]](s32)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[COPY2]](s32), [[COPY3]], [[SITOFP]]
; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:fpr(s32) = G_FPTOSI [[SELECT]](s32)
%0:_(s32) = COPY $w0
@@ -256,7 +256,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY %gpr_copy(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(i32) = COPY %gpr_copy(s32)
; CHECK-NEXT: %select:fpr(s32) = G_SELECT %cond_wide(s32), %fpr_copy, [[COPY]]
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
@@ -302,7 +302,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %fpr_copy(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(i32) = COPY %fpr_copy(s32)
; CHECK-NEXT: %select:gpr(s32) = G_SELECT %cond_wide(s32), [[COPY]], %gpr_copy
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
@@ -349,8 +349,8 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %unmerge_src(s64)
- ; CHECK-NEXT: %unmerge_1:fpr(s32), %unmerge_2:fpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(i64) = COPY %unmerge_src(s64)
+ ; CHECK-NEXT: %unmerge_1:fpr(s32), %unmerge_2:fpr(s32) = G_UNMERGE_VALUES [[COPY]](i64)
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
index 16100f01017a6..8846195fc365c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
@@ -34,8 +34,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %gpr:gpr(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
- ; CHECK-NEXT: %llround:fpr(s64) = G_LLROUND [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(i64) = COPY %gpr(s64)
+ ; CHECK-NEXT: %llround:fpr(s64) = G_LLROUND [[COPY]](i64)
; CHECK-NEXT: $d0 = COPY %llround(s64)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%gpr:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
index 5cb93f7c4646d..e65ac4c912f44 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir
@@ -34,8 +34,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %gpr:gpr(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
- ; CHECK-NEXT: %lround:fpr(s64) = G_LROUND [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(i64) = COPY %gpr(s64)
+ ; CHECK-NEXT: %lround:fpr(s64) = G_LROUND [[COPY]](i64)
; CHECK-NEXT: $d0 = COPY %lround(s64)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%gpr:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
index b718ea300cca9..bba98072d8a1f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
@@ -36,8 +36,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:gpr(s32) = COPY $w0
; CHECK-NEXT: %rhs:gpr(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY %lhs(s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s32) = COPY %rhs(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(i32) = COPY %lhs(s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(i32) = COPY %rhs(s32)
; CHECK-NEXT: %maxnum:fpr(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
; CHECK-NEXT: $s0 = COPY %maxnum(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
index 6be73170fd938..ac5bbbb3d1c1f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
@@ -36,8 +36,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:gpr(s32) = COPY $w0
; CHECK-NEXT: %rhs:gpr(s32) = COPY $w1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY %lhs(s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s32) = COPY %rhs(s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(i32) = COPY %lhs(s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(i32) = COPY %rhs(s32)
; CHECK-NEXT: %minnum:fpr(s32) = G_FMINNUM [[COPY]], [[COPY1]]
; CHECK-NEXT: $s0 = COPY %minnum(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
index e700c834a93cd..6b93849f2455e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
@@ -108,7 +108,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(s64) = COPY [[COPY2]](s64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(i64) = COPY [[COPY2]](s64)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY]](s32), [[COPY1]], [[COPY3]]
; CHECK-NEXT: $d0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -139,7 +139,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr(s64) = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr(i64) = COPY [[COPY1]](s64)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[COPY]](s32), [[COPY3]], [[COPY2]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
index 55f316facfca3..e60d64410b724 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir
@@ -15,15 +15,15 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:fpr(<8 x s16>) = G_BUILD_VECTOR [[COPY1]](s16), [[COPY2]](s16), [[COPY3]](s16), [[COPY4]](s16), [[COPY5]](s16), [[COPY6]](s16), [[COPY7]](s16), [[COPY8]](s16)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(i16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr(i16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(i16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr(i16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr(i16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr(i16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:fpr(i16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:fpr(i16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:fpr(<8 x s16>) = G_BUILD_VECTOR [[COPY1]](i16), [[COPY2]](i16), [[COPY3]](i16), [[COPY4]](i16), [[COPY5]](i16), [[COPY6]](i16), [[COPY7]](i16), [[COPY8]](i16)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(s32) = COPY $w0
@@ -44,24 +44,24 @@ body: |
; They're all constant, so we can select it via a constant-pool load if needed
; and this form is more amenable to selection by patterns (without x-bank copies).
; CHECK-LABEL: name: g_constant_operands_on_gpr
- ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s8) = G_TRUNC [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[C1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:gpr(s8) = G_TRUNC [[C2]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:gpr(s8) = G_TRUNC [[C3]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:gpr(s8) = G_TRUNC [[C4]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 44
- ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:gpr(s8) = G_TRUNC [[C5]](s32)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 22
- ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:gpr(s8) = G_TRUNC [[C6]](s32)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 19
- ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:gpr(s8) = G_TRUNC [[C7]](s32)
- ; CHECK-NEXT: [[C8:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 55
- ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:gpr(s8) = G_TRUNC [[C8]](s32)
+ ; CHECK: [[C:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s8) = G_TRUNC [[C]](i32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[C1]](i32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:gpr(s8) = G_TRUNC [[C2]](i32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:gpr(s8) = G_TRUNC [[C3]](i32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:gpr(s8) = G_TRUNC [[C4]](i32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 44
+ ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:gpr(s8) = G_TRUNC [[C5]](i32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 22
+ ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:gpr(s8) = G_TRUNC [[C6]](i32)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 19
+ ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:gpr(s8) = G_TRUNC [[C7]](i32)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:gpr(i32) = G_CONSTANT i32 55
+ ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:gpr(s8) = G_TRUNC [[C8]](i32)
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s8) = COPY [[TRUNC]](s8)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s8) = COPY [[TRUNC1]](s8)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr(s8) = COPY [[TRUNC2]](s8)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-abs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-abs.mir
index d8cdcdb3e2f62..36e4412793e36 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-abs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-abs.mir
@@ -18,9 +18,9 @@ body: |
; CHECK-NEXT: [[ABSv4i16_:%[0-9]+]]:fpr64 = ABSv4i16 [[COPY]]
; CHECK-NEXT: $d0 = COPY [[ABSv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_ABS %0
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = G_ABS %0
+ $d0 = COPY %1(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -40,9 +40,9 @@ body: |
; CHECK-NEXT: [[ABSv8i16_:%[0-9]+]]:fpr128 = ABSv8i16 [[COPY]]
; CHECK-NEXT: $q0 = COPY [[ABSv8i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_ABS %0
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = G_ABS %0
+ $q0 = COPY %1(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -62,9 +62,9 @@ body: |
; CHECK-NEXT: [[ABSv2i32_:%[0-9]+]]:fpr64 = ABSv2i32 [[COPY]]
; CHECK-NEXT: $d0 = COPY [[ABSv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_ABS %0
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = G_ABS %0
+ $d0 = COPY %1(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -84,9 +84,9 @@ body: |
; CHECK-NEXT: [[ABSv4i32_:%[0-9]+]]:fpr128 = ABSv4i32 [[COPY]]
; CHECK-NEXT: $q0 = COPY [[ABSv4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_ABS %0
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = G_ABS %0
+ $q0 = COPY %1(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -106,9 +106,9 @@ body: |
; CHECK-NEXT: [[ABSv8i8_:%[0-9]+]]:fpr64 = ABSv8i8 [[COPY]]
; CHECK-NEXT: $d0 = COPY [[ABSv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = G_ABS %0
- $d0 = COPY %1(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = G_ABS %0
+ $d0 = COPY %1(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -128,9 +128,9 @@ body: |
; CHECK-NEXT: [[ABSv16i8_:%[0-9]+]]:fpr128 = ABSv16i8 [[COPY]]
; CHECK-NEXT: $q0 = COPY [[ABSv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = G_ABS %0
- $q0 = COPY %1(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = G_ABS %0
+ $q0 = COPY %1(<16 x i8>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
index e4d6ad8320ab7..9389fff12fb93 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
@@ -19,11 +19,11 @@ body: |
; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY]], 48
; CHECK-NEXT: $x3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $x3
- %1:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_SEXT %1(s32)
- %add_lhs:gpr(s64) = COPY $x2
- %res:gpr(s64) = G_ADD %add_lhs, %ext
- $x3 = COPY %res(s64)
+ %1:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_SEXT %1(i32)
+ %add_lhs:gpr(i64) = COPY $x2
+ %res:gpr(i64) = G_ADD %add_lhs, %ext
+ $x3 = COPY %res(i64)
RET_ReallyLR implicit $x3
...
---
@@ -46,12 +46,12 @@ body: |
; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16
; CHECK-NEXT: $x3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $x3
- %1:gpr(s64) = COPY $x1
- %mask:gpr(s64) = G_CONSTANT i64 4294967295 ; 0xffff
- %ext:gpr(s64) = G_AND %1(s64), %mask
- %add_lhs:gpr(s64) = COPY $x2
- %res:gpr(s64) = G_ADD %add_lhs, %ext
- $x3 = COPY %res(s64)
+ %1:gpr(i64) = COPY $x1
+ %mask:gpr(i64) = G_CONSTANT i64 4294967295 ; 0xffff
+ %ext:gpr(i64) = G_AND %1(i64), %mask
+ %add_lhs:gpr(i64) = COPY $x2
+ %res:gpr(i64) = G_ADD %add_lhs, %ext
+ $x3 = COPY %res(i64)
RET_ReallyLR implicit $x3
...
---
@@ -72,12 +72,12 @@ body: |
; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 40
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
- %1:gpr(s16) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_SEXT %1(s16)
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %ext
- $w3 = COPY %res(s32)
+ %wide_1:gpr(i32) = COPY $w1
+ %1:gpr(i16) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_SEXT %1(i16)
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -98,12 +98,12 @@ body: |
; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
- %1:gpr(s16) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_ZEXT %1(s16)
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %ext
- $w3 = COPY %res(s32)
+ %wide_1:gpr(i32) = COPY $w1
+ %1:gpr(i16) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_ZEXT %1(i16)
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -124,12 +124,12 @@ body: |
; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
- %1:gpr(s16) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_ANYEXT %1(s16)
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %ext
- $w3 = COPY %res(s32)
+ %wide_1:gpr(i32) = COPY $w1
+ %1:gpr(i16) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_ANYEXT %1(i16)
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -150,12 +150,12 @@ body: |
; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 0
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %1:gpr(s32) = COPY $w1
- %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
- %ext:gpr(s32) = G_AND %1(s32), %mask
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %ext
- $w3 = COPY %res(s32)
+ %1:gpr(i32) = COPY $w1
+ %mask:gpr(i32) = G_CONSTANT i32 255 ; 0xff
+ %ext:gpr(i32) = G_AND %1(i32), %mask
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -176,12 +176,12 @@ body: |
; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 8
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %1:gpr(s32) = COPY $w1
- %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff
- %ext:gpr(s32) = G_AND %1(s32), %mask
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %ext
- $w3 = COPY %res(s32)
+ %1:gpr(i32) = COPY $w1
+ %mask:gpr(i32) = G_CONSTANT i32 65535 ; 0xffff
+ %ext:gpr(i32) = G_AND %1(i32), %mask
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -202,12 +202,12 @@ body: |
; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 32
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
+ %wide_1:gpr(i32) = COPY $w1
%1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_SEXT %1(s8)
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %ext
- $w3 = COPY %res(s32)
+ %ext:gpr(i32) = G_SEXT %1(s8)
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -228,12 +228,12 @@ body: |
; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
+ %wide_1:gpr(i32) = COPY $w1
%1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_ZEXT %1(s8)
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %ext
- $w3 = COPY %res(s32)
+ %ext:gpr(i32) = G_ZEXT %1(s8)
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -254,12 +254,12 @@ body: |
; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
+ %wide_1:gpr(i32) = COPY $w1
%1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_ANYEXT %1(s8)
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %ext
- $w3 = COPY %res(s32)
+ %ext:gpr(i32) = G_ANYEXT %1(s8)
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -280,14 +280,14 @@ body: |
; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 43
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
- %1:gpr(s16) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_SEXT %1(s16)
- %imm:gpr(s32) = G_CONSTANT i32 3
- %shl:gpr(s32) = G_SHL %ext, %imm
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %shl
- $w3 = COPY %res(s32)
+ %wide_1:gpr(i32) = COPY $w1
+ %1:gpr(i16) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_SEXT %1(i16)
+ %imm:gpr(i32) = G_CONSTANT i32 3
+ %shl:gpr(i32) = G_SHL %ext, %imm
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %shl
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -308,14 +308,14 @@ body: |
; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 3
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %1:gpr(s32) = COPY $w1
- %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
- %ext:gpr(s32) = G_AND %1(s32), %mask
- %imm:gpr(s32) = G_CONSTANT i32 3
- %shl:gpr(s32) = G_SHL %ext, %imm
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %shl
- $w3 = COPY %res(s32)
+ %1:gpr(i32) = COPY $w1
+ %mask:gpr(i32) = G_CONSTANT i32 255 ; 0xff
+ %ext:gpr(i32) = G_AND %1(i32), %mask
+ %imm:gpr(i32) = G_CONSTANT i32 3
+ %shl:gpr(i32) = G_SHL %ext, %imm
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %shl
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -339,12 +339,12 @@ body: |
; CHECK-NEXT: %res:gpr32 = ADDWrr %add_lhs, %ext
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %1:gpr(s32) = COPY $w1
- %mask:gpr(s32) = G_CONSTANT i32 42
- %ext:gpr(s32) = G_AND %1(s32), %mask
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %ext
- $w3 = COPY %res(s32)
+ %1:gpr(i32) = COPY $w1
+ %mask:gpr(i32) = G_CONSTANT i32 42
+ %ext:gpr(i32) = G_AND %1(i32), %mask
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -366,14 +366,14 @@ body: |
; CHECK-NEXT: %res:gpr32 = ADDWrs %add_lhs, %ext, 5
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
- %1:gpr(s16) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_SEXT %1(s16)
- %imm:gpr(s32) = G_CONSTANT i32 5
- %shl:gpr(s32) = G_SHL %ext, %imm
- %add_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_ADD %add_lhs, %shl
- $w3 = COPY %res(s32)
+ %wide_1:gpr(i32) = COPY $w1
+ %1:gpr(i16) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_SEXT %1(i16)
+ %imm:gpr(i32) = G_CONSTANT i32 5
+ %shl:gpr(i32) = G_SHL %ext, %imm
+ %add_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_ADD %add_lhs, %shl
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -394,11 +394,11 @@ body: |
; CHECK-NEXT: %res:gpr64 = SUBSXrx %sub_lhs, [[COPY]], 48, implicit-def dead $nzcv
; CHECK-NEXT: $x3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $x3
- %1:gpr(s32) = COPY $w1
- %ext:gpr(s64) = G_SEXT %1(s32)
- %sub_lhs:gpr(s64) = COPY $x2
- %res:gpr(s64) = G_SUB %sub_lhs, %ext
- $x3 = COPY %res(s64)
+ %1:gpr(i32) = COPY $w1
+ %ext:gpr(i64) = G_SEXT %1(i32)
+ %sub_lhs:gpr(i64) = COPY $x2
+ %res:gpr(i64) = G_SUB %sub_lhs, %ext
+ $x3 = COPY %res(i64)
RET_ReallyLR implicit $x3
...
---
@@ -419,12 +419,12 @@ body: |
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 40, implicit-def dead $nzcv
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
- %1:gpr(s16) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_SEXT %1(s16)
- %sub_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_SUB %sub_lhs, %ext
- $w3 = COPY %res(s32)
+ %wide_1:gpr(i32) = COPY $w1
+ %1:gpr(i16) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_SEXT %1(i16)
+ %sub_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -445,12 +445,12 @@ body: |
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
- %1:gpr(s16) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_ZEXT %1(s16)
- %sub_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_SUB %sub_lhs, %ext
- $w3 = COPY %res(s32)
+ %wide_1:gpr(i32) = COPY $w1
+ %1:gpr(i16) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_ZEXT %1(i16)
+ %sub_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -471,12 +471,12 @@ body: |
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
- %1:gpr(s16) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_ANYEXT %1(s16)
- %sub_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_SUB %sub_lhs, %ext
- $w3 = COPY %res(s32)
+ %wide_1:gpr(i32) = COPY $w1
+ %1:gpr(i16) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_ANYEXT %1(i16)
+ %sub_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -497,12 +497,12 @@ body: |
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 0, implicit-def dead $nzcv
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %1:gpr(s32) = COPY $w1
- %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
- %ext:gpr(s32) = G_AND %1(s32), %mask
- %sub_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_SUB %sub_lhs, %ext
- $w3 = COPY %res(s32)
+ %1:gpr(i32) = COPY $w1
+ %mask:gpr(i32) = G_CONSTANT i32 255 ; 0xff
+ %ext:gpr(i32) = G_AND %1(i32), %mask
+ %sub_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -523,12 +523,12 @@ body: |
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 8, implicit-def dead $nzcv
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %1:gpr(s32) = COPY $w1
- %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff
- %ext:gpr(s32) = G_AND %1(s32), %mask
- %sub_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_SUB %sub_lhs, %ext
- $w3 = COPY %res(s32)
+ %1:gpr(i32) = COPY $w1
+ %mask:gpr(i32) = G_CONSTANT i32 65535 ; 0xffff
+ %ext:gpr(i32) = G_AND %1(i32), %mask
+ %sub_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
---
name: sub_sext_s8_to_s32
@@ -540,12 +540,12 @@ machineFunctionInfo: {}
body: |
bb.0:
liveins: $w1, $w2, $x2
- %wide_1:gpr(s32) = COPY $w1
+ %wide_1:gpr(i32) = COPY $w1
%1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_SEXT %1(s8)
- %sub_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_SUB %sub_lhs, %ext
- $w3 = COPY %res(s32)
+ %ext:gpr(i32) = G_SEXT %1(s8)
+ %sub_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -566,12 +566,12 @@ body: |
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
+ %wide_1:gpr(i32) = COPY $w1
%1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_ZEXT %1(s8)
- %sub_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_SUB %sub_lhs, %ext
- $w3 = COPY %res(s32)
+ %ext:gpr(i32) = G_ZEXT %1(s8)
+ %sub_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -592,12 +592,12 @@ body: |
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
+ %wide_1:gpr(i32) = COPY $w1
%1:gpr(s8) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_ANYEXT %1(s8)
- %sub_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_SUB %sub_lhs, %ext
- $w3 = COPY %res(s32)
+ %ext:gpr(i32) = G_ANYEXT %1(s8)
+ %sub_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
---
...
@@ -619,14 +619,14 @@ body: |
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 43, implicit-def dead $nzcv
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %wide_1:gpr(s32) = COPY $w1
- %1:gpr(s16) = G_TRUNC %wide_1
- %ext:gpr(s32) = G_SEXT %1(s16)
- %imm:gpr(s32) = G_CONSTANT i32 3
- %shl:gpr(s32) = G_SHL %ext, %imm
- %sub_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_SUB %sub_lhs, %shl
- $w3 = COPY %res(s32)
+ %wide_1:gpr(i32) = COPY $w1
+ %1:gpr(i16) = G_TRUNC %wide_1
+ %ext:gpr(i32) = G_SEXT %1(i16)
+ %imm:gpr(i32) = G_CONSTANT i32 3
+ %shl:gpr(i32) = G_SHL %ext, %imm
+ %sub_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_SUB %sub_lhs, %shl
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -647,14 +647,14 @@ body: |
; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 3, implicit-def dead $nzcv
; CHECK-NEXT: $w3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $w3
- %1:gpr(s32) = COPY $w1
- %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
- %ext:gpr(s32) = G_AND %1(s32), %mask
- %imm:gpr(s32) = G_CONSTANT i32 3
- %shl:gpr(s32) = G_SHL %ext, %imm
- %sub_lhs:gpr(s32) = COPY $w2
- %res:gpr(s32) = G_SUB %sub_lhs, %shl
- $w3 = COPY %res(s32)
+ %1:gpr(i32) = COPY $w1
+ %mask:gpr(i32) = G_CONSTANT i32 255 ; 0xff
+ %ext:gpr(i32) = G_AND %1(i32), %mask
+ %imm:gpr(i32) = G_CONSTANT i32 3
+ %shl:gpr(i32) = G_SHL %ext, %imm
+ %sub_lhs:gpr(i32) = COPY $w2
+ %res:gpr(i32) = G_SUB %sub_lhs, %shl
+ $w3 = COPY %res(i32)
RET_ReallyLR implicit $w3
...
---
@@ -683,13 +683,13 @@ body: |
; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = COPY $w1
+ %1:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
- %small:gpr(s16) = G_TRUNC %1
- %zext:gpr(s64) = G_ZEXT %small(s16)
- %cst:gpr(s64) = G_CONSTANT i64 3
- %shl:gpr(s64) = G_SHL %zext, %cst(s64)
- %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
+ %small:gpr(i16) = G_TRUNC %1
+ %zext:gpr(i64) = G_ZEXT %small(i16)
+ %cst:gpr(i64) = G_CONSTANT i64 3
+ %shl:gpr(i64) = G_SHL %zext, %cst(i64)
+ %gep:gpr(p0) = G_PTR_ADD %0, %shl(i64)
G_STORE %2(p0), %gep(p0) :: (store (p0))
RET_ReallyLR
...
@@ -719,13 +719,13 @@ body: |
; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = COPY $w1
+ %1:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
%small:gpr(s8) = G_TRUNC %1
- %zext:gpr(s64) = G_ZEXT %small(s8)
- %cst:gpr(s64) = G_CONSTANT i64 3
- %shl:gpr(s64) = G_SHL %zext, %cst(s64)
- %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
+ %zext:gpr(i64) = G_ZEXT %small(s8)
+ %cst:gpr(i64) = G_CONSTANT i64 3
+ %shl:gpr(i64) = G_SHL %zext, %cst(i64)
+ %gep:gpr(p0) = G_PTR_ADD %0, %shl(i64)
G_STORE %2(p0), %gep(p0) :: (store (p0))
RET_ReallyLR
...
@@ -755,13 +755,13 @@ body: |
; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = COPY $w1
+ %1:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
- %small:gpr(s16) = G_TRUNC %1
- %zext:gpr(s64) = G_SEXT %small(s16)
- %cst:gpr(s64) = G_CONSTANT i64 3
- %shl:gpr(s64) = G_SHL %zext, %cst(s64)
- %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
+ %small:gpr(i16) = G_TRUNC %1
+ %zext:gpr(i64) = G_SEXT %small(i16)
+ %cst:gpr(i64) = G_CONSTANT i64 3
+ %shl:gpr(i64) = G_SHL %zext, %cst(i64)
+ %gep:gpr(p0) = G_PTR_ADD %0, %shl(i64)
G_STORE %2(p0), %gep(p0) :: (store (p0))
RET_ReallyLR
...
@@ -791,13 +791,13 @@ body: |
; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = COPY $w1
+ %1:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
%small:gpr(s8) = G_TRUNC %1
- %zext:gpr(s64) = G_SEXT %small(s8)
- %cst:gpr(s64) = G_CONSTANT i64 3
- %shl:gpr(s64) = G_SHL %zext, %cst(s64)
- %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
+ %zext:gpr(i64) = G_SEXT %small(s8)
+ %cst:gpr(i64) = G_CONSTANT i64 3
+ %shl:gpr(i64) = G_SHL %zext, %cst(i64)
+ %gep:gpr(p0) = G_PTR_ADD %0, %shl(i64)
G_STORE %2(p0), %gep(p0) :: (store (p0))
RET_ReallyLR
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir
index 3ca1931575470..942882a139dba 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir
@@ -16,11 +16,11 @@ body: |
; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 8
; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
- %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
- $x0 = COPY %3:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_SHL %0, %1:gpr(i64)
+ %3:gpr(i64) = G_ADD %0, %2:gpr(i64)
+ $x0 = COPY %3:gpr(i64)
RET_ReallyLR implicit $x0
...
@@ -40,12 +40,12 @@ body: |
; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY1]], [[COPY]], 8
; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %4:gpr(s64) = COPY $x1
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
- %3:gpr(s64) = G_ADD %2, %4:gpr(s64)
- $x0 = COPY %3:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %4:gpr(i64) = COPY $x1
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_SHL %0, %1:gpr(i64)
+ %3:gpr(i64) = G_ADD %2, %4:gpr(i64)
+ $x0 = COPY %3:gpr(i64)
RET_ReallyLR implicit $x0
...
@@ -64,11 +64,11 @@ body: |
; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
- %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
- $x0 = COPY %3:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_SHL %0, %1:gpr(i64)
+ %3:gpr(i64) = G_SUB %0, %2:gpr(i64)
+ $x0 = COPY %3:gpr(i64)
RET_ReallyLR implicit $x0
---
@@ -79,11 +79,11 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
- %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
- $x0 = COPY %3:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_LSHR %0, %1:gpr(i64)
+ %3:gpr(i64) = G_ADD %0, %2:gpr(i64)
+ $x0 = COPY %3:gpr(i64)
RET_ReallyLR implicit $x0
...
@@ -103,12 +103,12 @@ body: |
; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 72
; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %param2:gpr(s64) = COPY $x1
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
- %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)
- $x0 = COPY %3:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %param2:gpr(i64) = COPY $x1
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_LSHR %0, %1:gpr(i64)
+ %3:gpr(i64) = G_ADD %2, %param2:gpr(i64)
+ $x0 = COPY %3:gpr(i64)
RET_ReallyLR implicit $x0
...
@@ -127,11 +127,11 @@ body: |
; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
- %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
- $x0 = COPY %3:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_LSHR %0, %1:gpr(i64)
+ %3:gpr(i64) = G_SUB %0, %2:gpr(i64)
+ $x0 = COPY %3:gpr(i64)
RET_ReallyLR implicit $x0
...
@@ -150,11 +150,11 @@ body: |
; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 136
; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
- %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
- $x0 = COPY %3:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_ASHR %0, %1:gpr(i64)
+ %3:gpr(i64) = G_ADD %0, %2:gpr(i64)
+ $x0 = COPY %3:gpr(i64)
RET_ReallyLR implicit $x0
...
@@ -174,12 +174,12 @@ body: |
; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 136
; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %param2:gpr(s64) = COPY $x1
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
- %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)
- $x0 = COPY %3:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %param2:gpr(i64) = COPY $x1
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_ASHR %0, %1:gpr(i64)
+ %3:gpr(i64) = G_ADD %2, %param2:gpr(i64)
+ $x0 = COPY %3:gpr(i64)
RET_ReallyLR implicit $x0
...
@@ -198,11 +198,11 @@ body: |
; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
- %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
- $x0 = COPY %3:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_ASHR %0, %1:gpr(i64)
+ %3:gpr(i64) = G_SUB %0, %2:gpr(i64)
+ $x0 = COPY %3:gpr(i64)
RET_ReallyLR implicit $x0
---
@@ -213,11 +213,11 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 8
- %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
- %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
- $w0 = COPY %3:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 8
+ %2:gpr(i32) = G_SHL %0, %1:gpr(i32)
+ %3:gpr(i32) = G_ADD %0, %2:gpr(i32)
+ $w0 = COPY %3:gpr(i32)
RET_ReallyLR implicit $w0
...
@@ -237,12 +237,12 @@ body: |
; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 8
; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %param2:gpr(s32) = COPY $w1
- %1:gpr(s32) = G_CONSTANT i32 8
- %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
- %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
- $w0 = COPY %3:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %param2:gpr(i32) = COPY $w1
+ %1:gpr(i32) = G_CONSTANT i32 8
+ %2:gpr(i32) = G_SHL %0, %1:gpr(i32)
+ %3:gpr(i32) = G_ADD %2, %param2:gpr(i32)
+ $w0 = COPY %3:gpr(i32)
RET_ReallyLR implicit $w0
...
@@ -261,11 +261,11 @@ body: |
; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv
; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 8
- %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
- %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
- $w0 = COPY %3:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 8
+ %2:gpr(i32) = G_SHL %0, %1:gpr(i32)
+ %3:gpr(i32) = G_SUB %0, %2:gpr(i32)
+ $w0 = COPY %3:gpr(i32)
RET_ReallyLR implicit $w0
...
@@ -284,11 +284,11 @@ body: |
; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 72
; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 8
- %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
- %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
- $w0 = COPY %3:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 8
+ %2:gpr(i32) = G_LSHR %0, %1:gpr(i32)
+ %3:gpr(i32) = G_ADD %0, %2:gpr(i32)
+ $w0 = COPY %3:gpr(i32)
RET_ReallyLR implicit $w0
...
@@ -308,12 +308,12 @@ body: |
; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 72
; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %param2:gpr(s32) = COPY $w1
- %1:gpr(s32) = G_CONSTANT i32 8
- %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
- %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
- $w0 = COPY %3:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %param2:gpr(i32) = COPY $w1
+ %1:gpr(i32) = G_CONSTANT i32 8
+ %2:gpr(i32) = G_LSHR %0, %1:gpr(i32)
+ %3:gpr(i32) = G_ADD %2, %param2:gpr(i32)
+ $w0 = COPY %3:gpr(i32)
RET_ReallyLR implicit $w0
...
@@ -332,11 +332,11 @@ body: |
; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv
; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 8
- %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
- %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
- $w0 = COPY %3:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 8
+ %2:gpr(i32) = G_LSHR %0, %1:gpr(i32)
+ %3:gpr(i32) = G_SUB %0, %2:gpr(i32)
+ $w0 = COPY %3:gpr(i32)
RET_ReallyLR implicit $w0
...
@@ -355,11 +355,11 @@ body: |
; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 136
; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 8
- %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
- %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
- $w0 = COPY %3:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 8
+ %2:gpr(i32) = G_ASHR %0, %1:gpr(i32)
+ %3:gpr(i32) = G_ADD %0, %2:gpr(i32)
+ $w0 = COPY %3:gpr(i32)
RET_ReallyLR implicit $w0
...
@@ -379,12 +379,12 @@ body: |
; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 136
; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %param2:gpr(s32) = COPY $w1
- %1:gpr(s32) = G_CONSTANT i32 8
- %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
- %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
- $w0 = COPY %3:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %param2:gpr(i32) = COPY $w1
+ %1:gpr(i32) = G_CONSTANT i32 8
+ %2:gpr(i32) = G_ASHR %0, %1:gpr(i32)
+ %3:gpr(i32) = G_ADD %2, %param2:gpr(i32)
+ $w0 = COPY %3:gpr(i32)
RET_ReallyLR implicit $w0
...
@@ -403,9 +403,9 @@ body: |
; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv
; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 8
- %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
- %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
- $w0 = COPY %3:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 8
+ %2:gpr(i32) = G_ASHR %0, %1:gpr(i32)
+ %3:gpr(i32) = G_SUB %0, %2:gpr(i32)
+ $w0 = COPY %3:gpr(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
index 9f43e1a1ab42a..3b63f182b1f3d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
@@ -23,10 +23,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_ADD %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_ADD %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -51,10 +51,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_ADD %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_ADD %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -77,10 +77,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
; CHECK-NEXT: $w0 = COPY [[ADDWri]]
- %0(s32) = COPY $w0
- %1(s32) = G_CONSTANT i32 1
- %2(s32) = G_ADD %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = G_CONSTANT i32 1
+ %2(i32) = G_ADD %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -103,10 +103,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0
; CHECK-NEXT: $x0 = COPY [[ADDXri]]
- %0(s64) = COPY $x0
- %1(s64) = G_CONSTANT i64 1
- %2(s64) = G_ADD %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = G_CONSTANT i64 1
+ %2(i64) = G_ADD %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -129,10 +129,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w1
; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def dead $nzcv
; CHECK-NEXT: $w2 = COPY [[SUBSWri]]
- %0(s32) = COPY $w1
- %1(s32) = G_CONSTANT i32 -1
- %2(s32) = G_ADD %0, %1
- $w2 = COPY %2(s32)
+ %0(i32) = COPY $w1
+ %1(i32) = G_CONSTANT i32 -1
+ %2(i32) = G_ADD %0, %1
+ $w2 = COPY %2(i32)
...
---
@@ -155,10 +155,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 0, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXri]]
- %0(s64) = COPY $x0
- %1(s64) = G_CONSTANT i64 -1
- %2(s64) = G_ADD %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = G_CONSTANT i64 -1
+ %2(i64) = G_ADD %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -182,10 +182,10 @@ body: |
; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]]
; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
- %0(s64) = COPY $x0
- %1(s64) = G_CONSTANT i64 -5000
- %2(s64) = G_ADD %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = G_CONSTANT i64 -5000
+ %2(i64) = G_ADD %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -209,10 +209,10 @@ body: |
; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]]
; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
- %0(s64) = COPY $x0
- %1(s64) = G_CONSTANT i64 -5000
- %2(s64) = G_ADD %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = G_CONSTANT i64 -5000
+ %2(i64) = G_ADD %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -236,10 +236,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0
; CHECK-NEXT: $x0 = COPY [[ADDXri]]
- %0(s64) = COPY $x0
- %1(s64) = G_CONSTANT i64 0
- %2(s64) = G_ADD %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = G_CONSTANT i64 0
+ %2(i64) = G_ADD %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -263,10 +263,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0
; CHECK-NEXT: $x0 = COPY [[ADDXri]]
- %0(s64) = COPY $x0
- %1(s64) = G_CONSTANT i64 0
- %2(s64) = G_ADD %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = G_CONSTANT i64 0
+ %2(i64) = G_ADD %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -295,13 +295,13 @@ body: |
liveins: $w0, $w1
successors: %bb.1
- %0(s32) = COPY $w0
- %1(s32) = G_CONSTANT i32 1
+ %0(i32) = COPY $w0
+ %1(i32) = G_CONSTANT i32 1
G_BR %bb.1
bb.1:
- %2(s32) = G_ADD %0, %1
- $w0 = COPY %2(s32)
+ %2(i32) = G_ADD %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -326,10 +326,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def dead $nzcv
; CHECK-NEXT: $w0 = COPY [[SUBSWrr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_SUB %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_SUB %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -354,10 +354,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def dead $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_SUB %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_SUB %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -382,10 +382,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ORRWrr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_OR %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_OR %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -410,10 +410,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[ORRXrr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_OR %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_OR %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -440,10 +440,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]]
- %0(<2 x s32>) = COPY $d0
- %1(<2 x s32>) = COPY $d1
- %2(<2 x s32>) = G_OR %0, %1
- $d0 = COPY %2(<2 x s32>)
+ %0(<2 x i32>) = COPY $d0
+ %1(<2 x i32>) = COPY $d1
+ %2(<2 x i32>) = G_OR %0, %1
+ $d0 = COPY %2(<2 x i32>)
...
---
@@ -468,10 +468,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ANDWrr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_AND %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_AND %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -496,10 +496,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[ANDXrr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_AND %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_AND %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -524,10 +524,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[LSLVWr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_SHL %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_SHL %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -552,10 +552,10 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32
; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY2]]
; CHECK-NEXT: $w0 = COPY [[LSLVWr]]
- %0(s32) = COPY $w0
- %1(s64) = COPY $x1
- %2(s32) = G_SHL %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i64) = COPY $x1
+ %2(i32) = G_SHL %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -580,10 +580,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[LSLVXr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_SHL %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_SHL %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -608,10 +608,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[LSRVWr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_LSHR %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_LSHR %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -636,10 +636,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[LSRVXr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_LSHR %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_LSHR %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -664,10 +664,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ASRVWr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_ASHR %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_ASHR %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -692,14 +692,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[ASRVXr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_ASHR %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_ASHR %0, %1
+ $x0 = COPY %2(i64)
...
---
-# Check that we select s32 GPR G_MUL. This is trickier than other binops because
+# Check that we select i32 GPR G_MUL. This is trickier than other binops because
# there is only MADDWrrr, and we have to use the WZR physreg.
name: mul_s32_gpr
legalized: true
@@ -721,14 +721,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
; CHECK-NEXT: $w0 = COPY [[MADDWrrr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_MUL %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_MUL %0, %1
+ $w0 = COPY %2(i32)
...
---
-# Same as mul_s32_gpr for the s64 type.
+# Same as mul_s32_gpr for the i64 type.
name: mul_s64_gpr
legalized: true
regBankSelected: true
@@ -749,14 +749,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr
; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_MUL %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_MUL %0, %1
+ $x0 = COPY %2(i64)
...
---
-# Same as mul_s32_gpr for the s64 type.
+# Same as mul_s32_gpr for the i64 type.
name: mulh_s64_gpr
legalized: true
regBankSelected: true
@@ -775,12 +775,12 @@ body: |
; CHECK-NEXT: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SMULHrr]]
; CHECK-NEXT: $x0 = COPY [[UMULHrr]]
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = COPY $x1
- %2:gpr(s64) = G_SMULH %0, %1
- %3:gpr(s64) = G_UMULH %0, %1
- $x0 = COPY %2(s64)
- $x0 = COPY %3(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = COPY $x1
+ %2:gpr(i64) = G_SMULH %0, %1
+ %3:gpr(i64) = G_UMULH %0, %1
+ $x0 = COPY %2(i64)
+ $x0 = COPY %3(i64)
...
---
@@ -805,10 +805,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SDIVWr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_SDIV %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_SDIV %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -833,10 +833,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SDIVXr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_SDIV %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_SDIV %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -861,10 +861,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[UDIVWr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_UDIV %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_UDIV %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -889,14 +889,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[UDIVXr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_UDIV %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_UDIV %0, %1
+ $x0 = COPY %2(i64)
...
---
-# Check that we select a s32 FPR G_FADD into FADDSrr.
+# Check that we select a f32 FPR G_FADD into FADDSrr.
name: fadd_s32_fpr
legalized: true
regBankSelected: true
@@ -1134,10 +1134,10 @@ body: |
; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ADDv8i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %2:fpr(<8 x s16>) = G_ADD %0, %1
- $q0 = COPY %2(<8 x s16>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %2:fpr(<8 x i16>) = G_ADD %0, %1
+ $q0 = COPY %2(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -1164,10 +1164,10 @@ body: |
; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[ADDv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %2:fpr(<16 x s8>) = G_ADD %0, %1
- $q0 = COPY %2(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %2:fpr(<16 x i8>) = G_ADD %0, %1
+ $q0 = COPY %2(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -1188,10 +1188,10 @@ body: |
; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[ADDv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = G_ADD %0, %1
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = G_ADD %0, %1
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -1211,10 +1211,10 @@ body: |
; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = G_OR %0, %1
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = G_OR %0, %1
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -1234,10 +1234,10 @@ body: |
; CHECK-NEXT: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[EORv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = G_XOR %0, %1
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = G_XOR %0, %1
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -1257,9 +1257,9 @@ body: |
; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[MULv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = G_MUL %0, %1
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = G_MUL %0, %1
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitreverse.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitreverse.mir
index 6327ede4fc40b..b5db40155bece 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitreverse.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitreverse.mir
@@ -18,9 +18,9 @@ body: |
; CHECK-NEXT: %bitreverse:gpr32 = RBITWr %copy
; CHECK-NEXT: $w0 = COPY %bitreverse
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %copy:gpr(s32) = COPY $w0
- %bitreverse:gpr(s32) = G_BITREVERSE %copy
- $w0 = COPY %bitreverse(s32)
+ %copy:gpr(i32) = COPY $w0
+ %bitreverse:gpr(i32) = G_BITREVERSE %copy
+ $w0 = COPY %bitreverse(i32)
RET_ReallyLR implicit $w0
...
@@ -40,9 +40,9 @@ body: |
; CHECK-NEXT: %bitreverse:gpr64 = RBITXr %copy
; CHECK-NEXT: $x0 = COPY %bitreverse
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %copy:gpr(s64) = COPY $x0
- %bitreverse:gpr(s64) = G_BITREVERSE %copy
- $x0 = COPY %bitreverse(s64)
+ %copy:gpr(i64) = COPY $x0
+ %bitreverse:gpr(i64) = G_BITREVERSE %copy
+ $x0 = COPY %bitreverse(i64)
RET_ReallyLR implicit $x0
...
@@ -62,9 +62,9 @@ body: |
; CHECK-NEXT: %bitreverse:fpr64 = RBITv8i8 %vec
; CHECK-NEXT: $x0 = COPY %bitreverse
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %vec:fpr(<8 x s8>) = G_IMPLICIT_DEF
- %bitreverse:fpr(<8 x s8>) = G_BITREVERSE %vec
- $x0 = COPY %bitreverse(<8 x s8>)
+ %vec:fpr(<8 x i8>) = G_IMPLICIT_DEF
+ %bitreverse:fpr(<8 x i8>) = G_BITREVERSE %vec
+ $x0 = COPY %bitreverse(<8 x i8>)
RET_ReallyLR implicit $x0
...
@@ -84,9 +84,9 @@ body: |
; CHECK-NEXT: %bitreverse:fpr128 = RBITv16i8 %vec
; CHECK-NEXT: $q0 = COPY %bitreverse
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %vec:fpr(<16 x s8>) = G_IMPLICIT_DEF
- %bitreverse:fpr(<16 x s8>) = G_BITREVERSE %vec
- $q0 = COPY %bitreverse(<16 x s8>)
+ %vec:fpr(<16 x i8>) = G_IMPLICIT_DEF
+ %bitreverse:fpr(<16 x i8>) = G_BITREVERSE %vec
+ $q0 = COPY %bitreverse(<16 x i8>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
index 5ad64b53769b4..d0f2c9ceed7ef 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
@@ -26,10 +26,10 @@ body: |
liveins: $x0
%0:gpr(p0) = COPY $x0
- %8:gpr(s8) = G_LOAD %0(p0) :: (load (s8))
- %4:gpr(s32) = G_ANYEXT %8(s8)
- %5:gpr(s32) = G_CONSTANT i32 1
- %6:gpr(s32) = G_XOR %4, %5
+ %8:gpr(i8) = G_LOAD %0(p0) :: (load (s8))
+ %4:gpr(i32) = G_ANYEXT %8(i8)
+ %5:gpr(i32) = G_CONSTANT i32 1
+ %6:gpr(i32) = G_XOR %4, %5
G_BRCOND %6, %bb.3
bb.2:
@@ -67,12 +67,12 @@ body: |
liveins: $x0
%0:gpr(p0) = COPY $x0
- %8:gpr(s8) = G_LOAD %0(p0) :: (load (s8))
- %4:gpr(s64) = G_ANYEXT %8(s8)
- %5:gpr(s64) = G_CONSTANT i64 1
- %6:gpr(s64) = G_XOR %4, %5
- %3:gpr(s32) = G_TRUNC %6(s64)
- G_BRCOND %3(s32), %bb.3
+ %8:gpr(i8) = G_LOAD %0(p0) :: (load (s8))
+ %4:gpr(i64) = G_ANYEXT %8(i8)
+ %5:gpr(i64) = G_CONSTANT i64 1
+ %6:gpr(i64) = G_XOR %4, %5
+ %3:gpr(i32) = G_TRUNC %6(i64)
+ G_BRCOND %3(i32), %bb.3
bb.2:
RET_ReallyLR
@@ -102,9 +102,9 @@ body: |
bb.1:
successors: %bb.2, %bb.3
liveins: $w0
- %lhs:gpr(s32) = COPY $w0
- %rhs:gpr(s32) = G_CONSTANT i32 1
- %op:gpr(s32) = G_AND %lhs, %rhs
+ %lhs:gpr(i32) = COPY $w0
+ %rhs:gpr(i32) = G_CONSTANT i32 1
+ %op:gpr(i32) = G_AND %lhs, %rhs
G_BRCOND %op, %bb.3
bb.2:
@@ -137,9 +137,9 @@ body: |
bb.1:
successors: %bb.2, %bb.3
liveins: $w0, $w1
- %lhs:gpr(s32) = COPY $w0
- %rhs:gpr(s32) = COPY $w1
- %op:gpr(s32) = G_AND %lhs, %rhs
+ %lhs:gpr(i32) = COPY $w0
+ %rhs:gpr(i32) = COPY $w1
+ %op:gpr(i32) = G_AND %lhs, %rhs
G_BRCOND %op, %bb.3
bb.2:
@@ -174,9 +174,9 @@ body: |
bb.1:
successors: %bb.2, %bb.3
liveins: $w0
- %lhs:gpr(s32) = COPY $w0
- %rhs:gpr(s32) = G_CONSTANT i32 1
- %op:gpr(s32) = G_SHL %lhs, %rhs
+ %lhs:gpr(i32) = COPY $w0
+ %rhs:gpr(i32) = G_CONSTANT i32 1
+ %op:gpr(i32) = G_SHL %lhs, %rhs
G_BRCOND %op, %bb.3
bb.2:
@@ -209,9 +209,9 @@ body: |
bb.1:
successors: %bb.2, %bb.3
liveins: $w0
- %lhs:gpr(s32) = COPY $w0
- %rhs:gpr(s32) = G_CONSTANT i32 1
- %op:gpr(s32) = G_ASHR %lhs, %rhs
+ %lhs:gpr(i32) = COPY $w0
+ %rhs:gpr(i32) = G_CONSTANT i32 1
+ %op:gpr(i32) = G_ASHR %lhs, %rhs
G_BRCOND %op, %bb.3
bb.2:
@@ -242,10 +242,10 @@ body: |
bb.1:
successors: %bb.2, %bb.3
liveins: $x0
- %lhs:gpr(s64) = COPY $x0
- %rhs:gpr(s64) = G_CONSTANT i64 8589934592
- %op:gpr(s64) = G_ASHR %lhs, %rhs
- %trunc:gpr(s32) = G_TRUNC %op(s64)
+ %lhs:gpr(i64) = COPY $x0
+ %rhs:gpr(i64) = G_CONSTANT i64 8589934592
+ %op:gpr(i64) = G_ASHR %lhs, %rhs
+ %trunc:gpr(i32) = G_TRUNC %op(i64)
G_BRCOND %trunc, %bb.3
bb.2:
RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
index 6154fd27406bf..cae8160f4a86c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
@@ -17,10 +17,10 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 42
- %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %1
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 42
+ %5:gpr(i32) = G_ICMP intpred(eq), %0(i32), %1
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -41,10 +41,10 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 42
- %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1
- $w0 = COPY %5(s32)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 42
+ %5:gpr(i32) = G_ICMP intpred(eq), %0(i64), %1
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -67,10 +67,10 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 13132
- %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1
- $w0 = COPY %5(s32)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 13132
+ %5:gpr(i32) = G_ICMP intpred(eq), %0(i64), %1
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -90,11 +90,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s64) = G_CONSTANT i64 42
- %2:gpr(s32) = G_TRUNC %1(s64)
- %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i64) = G_CONSTANT i64 42
+ %2:gpr(i32) = G_TRUNC %1(i64)
+ %5:gpr(i32) = G_ICMP intpred(eq), %0(i32), %2
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -114,11 +114,11 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s64) = G_CONSTANT i64 68719476736 ; 0x1000000000
- %2:gpr(s32) = G_TRUNC %1(s64) ; Value truncates to 0
- %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i64) = G_CONSTANT i64 68719476736 ; 0x1000000000
+ %2:gpr(i32) = G_TRUNC %1(i64) ; Value truncates to 0
+ %5:gpr(i32) = G_ICMP intpred(eq), %0(i32), %2
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -138,10 +138,10 @@ body: |
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %cmp
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %cst:gpr(s32) = G_CONSTANT i32 -10
- %cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s32), %cst
- $w0 = COPY %cmp(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %cst:gpr(i32) = G_CONSTANT i32 -10
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %reg0(i32), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -161,10 +161,10 @@ body: |
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %cmp
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s64) = COPY $x0
- %cst:gpr(s64) = G_CONSTANT i64 -10
- %cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s64), %cst
- $w0 = COPY %cmp(s32)
+ %reg0:gpr(i64) = COPY $x0
+ %cst:gpr(i64) = G_CONSTANT i64 -10
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %reg0(i64), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -185,10 +185,10 @@ body: |
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %cmp
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %cst:gpr(s32) = G_CONSTANT i32 -5000
- %cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s32), %cst
- $w0 = COPY %cmp(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %cst:gpr(i32) = G_CONSTANT i32 -5000
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %reg0(i32), %cst
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
---
@@ -209,13 +209,13 @@ body: |
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %cmp
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s64) = COPY $x1
- %ext:gpr(s64) = G_ZEXT %reg0(s32)
- %cst:gpr(s64) = G_CONSTANT i64 2
- %shift:gpr(s64) = G_SHL %ext, %cst(s64)
- %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s64), %shift
- $w0 = COPY %cmp(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i64) = COPY $x1
+ %ext:gpr(i64) = G_ZEXT %reg0(i32)
+ %cst:gpr(i64) = G_CONSTANT i64 2
+ %shift:gpr(i64) = G_SHL %ext, %cst(i64)
+ %cmp:gpr(i32) = G_ICMP intpred(ugt), %reg1(i64), %shift
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -239,13 +239,13 @@ body: |
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %cmp
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s16) = COPY $h0
- %reg1:gpr(s32) = COPY $w1
- %ext:gpr(s32) = G_ZEXT %reg0(s16)
- %cst:gpr(s32) = G_CONSTANT i32 2
- %shift:gpr(s32) = G_SHL %ext, %cst(s32)
- %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s32), %shift
- $w0 = COPY %cmp(s32)
+ %reg0:gpr(i16) = COPY $h0
+ %reg1:gpr(i32) = COPY $w1
+ %ext:gpr(i32) = G_ZEXT %reg0(i16)
+ %cst:gpr(i32) = G_CONSTANT i32 2
+ %shift:gpr(i32) = G_SHL %ext, %cst(i32)
+ %cmp:gpr(i32) = G_ICMP intpred(ugt), %reg1(i32), %shift
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -271,13 +271,13 @@ body: |
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %cmp
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s64) = COPY $x1
- %ext:gpr(s64) = G_ZEXT %reg0(s32)
- %cst:gpr(s64) = G_CONSTANT i64 5
- %shift:gpr(s64) = G_SHL %ext, %cst(s64)
- %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s64), %shift
- $w0 = COPY %cmp(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i64) = COPY $x1
+ %ext:gpr(i64) = G_ZEXT %reg0(i32)
+ %cst:gpr(i64) = G_CONSTANT i64 5
+ %shift:gpr(i64) = G_SHL %ext, %cst(i64)
+ %cmp:gpr(i32) = G_ICMP intpred(ugt), %reg1(i64), %shift
+ $w0 = COPY %cmp(i32)
RET_ReallyLR implicit $w0
...
@@ -303,12 +303,12 @@ body: |
; CHECK-NEXT: %add:gpr32 = CSINCWr %add_rhs, %add_rhs, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %cmp_lhs:gpr(s32) = COPY $w0
- %cmp_rhs:gpr(s32) = COPY $w1
- %add_rhs:gpr(s32) = COPY $w2
- %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s32), %cmp_rhs
- %add:gpr(s32) = G_ADD %cmp, %add_rhs
- $w0 = COPY %add(s32)
+ %cmp_lhs:gpr(i32) = COPY $w0
+ %cmp_rhs:gpr(i32) = COPY $w1
+ %add_rhs:gpr(i32) = COPY $w2
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %cmp_lhs(i32), %cmp_rhs
+ %add:gpr(i32) = G_ADD %cmp, %add_rhs
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -334,12 +334,12 @@ body: |
; CHECK-NEXT: %add:gpr32 = CSINCWr %add_lhs, %add_lhs, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %cmp_lhs:gpr(s32) = COPY $w0
- %cmp_rhs:gpr(s32) = COPY $w1
- %add_lhs:gpr(s32) = COPY $w2
- %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s32), %cmp_rhs
- %add:gpr(s32) = G_ADD %add_lhs, %cmp
- $w0 = COPY %add(s32)
+ %cmp_lhs:gpr(i32) = COPY $w0
+ %cmp_rhs:gpr(i32) = COPY $w1
+ %add_lhs:gpr(i32) = COPY $w2
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %cmp_lhs(i32), %cmp_rhs
+ %add:gpr(i32) = G_ADD %add_lhs, %cmp
+ $w0 = COPY %add(i32)
RET_ReallyLR implicit $w0
...
@@ -365,12 +365,12 @@ body: |
; CHECK-NEXT: %add:fpr128 = ADDv4i32 %add_lhs, %cmp
; CHECK-NEXT: $q0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %cmp_lhs:fpr(<4 x s32>) = COPY $q0
- %cmp_rhs:fpr(<4 x s32>) = COPY $q1
- %add_lhs:fpr(<4 x s32>) = COPY $q2
- %cmp:fpr(<4 x s32>) = G_ICMP intpred(eq), %cmp_lhs(<4 x s32>), %cmp_rhs
- %add:fpr(<4 x s32>) = G_ADD %add_lhs, %cmp
- $q0 = COPY %add(<4 x s32>)
+ %cmp_lhs:fpr(<4 x i32>) = COPY $q0
+ %cmp_rhs:fpr(<4 x i32>) = COPY $q1
+ %add_lhs:fpr(<4 x i32>) = COPY $q2
+ %cmp:fpr(<4 x i32>) = G_ICMP intpred(eq), %cmp_lhs(<4 x i32>), %cmp_rhs
+ %add:fpr(<4 x i32>) = G_ADD %add_lhs, %cmp
+ $q0 = COPY %add(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -395,13 +395,13 @@ body: |
; CHECK-NEXT: %add:gpr64 = CSINCXr %add_rhs, %add_rhs, 1, implicit $nzcv
; CHECK-NEXT: $x0 = COPY %add
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %cmp_lhs:gpr(s64) = COPY $x0
- %cmp_rhs:gpr(s64) = COPY $x1
- %add_rhs:gpr(s64) = COPY $x2
- %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
- %cmp_ext:gpr(s64) = G_ZEXT %cmp
- %add:gpr(s64) = G_ADD %cmp_ext, %add_rhs
- $x0 = COPY %add(s64)
+ %cmp_lhs:gpr(i64) = COPY $x0
+ %cmp_rhs:gpr(i64) = COPY $x1
+ %add_rhs:gpr(i64) = COPY $x2
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %cmp_lhs(i64), %cmp_rhs
+ %cmp_ext:gpr(i64) = G_ZEXT %cmp
+ %add:gpr(i64) = G_ADD %cmp_ext, %add_rhs
+ $x0 = COPY %add(i64)
RET_ReallyLR implicit $x0
...
@@ -430,14 +430,14 @@ body: |
; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext
; CHECK-NEXT: $x0 = COPY %or
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %cmp_lhs:gpr(s64) = COPY $x0
- %cmp_rhs:gpr(s64) = COPY $x1
- %add_rhs:gpr(s64) = COPY $x2
- %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
- %cmp_ext:gpr(s64) = G_ZEXT %cmp
- %add:gpr(s64) = G_ADD %cmp_ext, %add_rhs
- %or:gpr(s64) = G_OR %add, %cmp_ext
- $x0 = COPY %or(s64)
+ %cmp_lhs:gpr(i64) = COPY $x0
+ %cmp_rhs:gpr(i64) = COPY $x1
+ %add_rhs:gpr(i64) = COPY $x2
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %cmp_lhs(i64), %cmp_rhs
+ %cmp_ext:gpr(i64) = G_ZEXT %cmp
+ %add:gpr(i64) = G_ADD %cmp_ext, %add_rhs
+ %or:gpr(i64) = G_OR %add, %cmp_ext
+ $x0 = COPY %or(i64)
RET_ReallyLR implicit $x0
...
@@ -469,13 +469,13 @@ body: |
; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext2
; CHECK-NEXT: $x0 = COPY %or
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %cmp_lhs:gpr(s64) = COPY $x0
- %cmp_rhs:gpr(s64) = COPY $x1
- %add_rhs:gpr(s64) = COPY $x2
- %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
- %cmp_ext:gpr(s64) = G_ZEXT %cmp
- %add:gpr(s64) = G_ADD %cmp_ext, %add_rhs
- %cmp_ext2:gpr(s64) = G_SEXT %cmp
- %or:gpr(s64) = G_OR %add, %cmp_ext2
- $x0 = COPY %or(s64)
+ %cmp_lhs:gpr(i64) = COPY $x0
+ %cmp_rhs:gpr(i64) = COPY $x1
+ %add_rhs:gpr(i64) = COPY $x2
+ %cmp:gpr(i32) = G_ICMP intpred(eq), %cmp_lhs(i64), %cmp_rhs
+ %cmp_ext:gpr(i64) = G_ZEXT %cmp
+ %add:gpr(i64) = G_ADD %cmp_ext, %add_rhs
+ %cmp_ext2:gpr(i64) = G_SEXT %cmp
+ %or:gpr(i64) = G_OR %add, %cmp_ext2
+ $x0 = COPY %or(i64)
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir
index f5290a5edc012..2efb269578ccf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir
@@ -36,22 +36,22 @@ body: |
successors: %bb.4(0x40000000), %bb.3(0x40000000)
liveins: $w0, $w1
- %35:gpr(s32) = G_CONSTANT i32 145185
- G_BRCOND %35(s32), %bb.4
+ %35:gpr(i32) = G_CONSTANT i32 145185
+ G_BRCOND %35(i32), %bb.4
G_BR %bb.3
bb.3:
successors: %bb.5(0x80000000)
- %17:gpr(s32) = G_CONSTANT_FOLD_BARRIER %35
- $w5 = COPY %17(s32)
+ %17:gpr(i32) = G_CONSTANT_FOLD_BARRIER %35
+ $w5 = COPY %17(i32)
G_BR %bb.5
bb.4:
successors: %bb.5(0x80000000)
- %23:gpr(s32) = G_ADD %35, %35
- $w3 = COPY %23(s32)
+ %23:gpr(i32) = G_ADD %35, %35
+ $w3 = COPY %23(i32)
G_BR %bb.5
bb.5:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir
index 97c080049ae01..e3476131e9df7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir
@@ -16,9 +16,9 @@ body: |
; CHECK: [[CLZv8i8_:%[0-9]+]]:fpr64 = CLZv8i8 [[COPY]]
; CHECK: $d0 = COPY [[CLZv8i8_]]
; CHECK: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = G_CTLZ %0(<8 x s8>)
- $d0 = COPY %1(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = G_CTLZ %0(<8 x i8>)
+ $d0 = COPY %1(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -39,9 +39,9 @@ body: |
; CHECK-NEXT: [[CLZv4i16_:%[0-9]+]]:fpr64 = CLZv4i16 [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CLZv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = G_CTLZ %0(<4 x s16>)
- $d0 = COPY %1(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = G_CTLZ %0(<4 x i16>)
+ $d0 = COPY %1(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -62,9 +62,9 @@ body: |
; CHECK-NEXT: [[CLZv2i32_:%[0-9]+]]:fpr64 = CLZv2i32 [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CLZv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = G_CTLZ %0(<2 x s32>)
- $d0 = COPY %1(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = G_CTLZ %0(<2 x i32>)
+ $d0 = COPY %1(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -86,10 +86,10 @@ body: |
; CHECK-NEXT: [[CLZXr:%[0-9]+]]:gpr64 = CLZXr [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CLZXr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(s64) = COPY $d0
- %2:gpr(s64) = COPY %0(s64)
- %1:gpr(s64) = G_CTLZ %2(s64)
- $d0 = COPY %1(s64)
+ %0:fpr(i64) = COPY $d0
+ %2:gpr(i64) = COPY %0(i64)
+ %1:gpr(i64) = G_CTLZ %2(i64)
+ $d0 = COPY %1(i64)
RET_ReallyLR implicit $d0
...
@@ -110,10 +110,10 @@ body: |
; CHECK-NEXT: [[CLZWr:%[0-9]+]]:gpr32 = CLZWr [[COPY1]]
; CHECK-NEXT: $s0 = COPY [[CLZWr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:fpr(s32) = COPY $s0
- %2:gpr(s32) = COPY %0(s32)
- %1:gpr(s32) = G_CTLZ %2(s32)
- $s0 = COPY %1(s32)
+ %0:fpr(i32) = COPY $s0
+ %2:gpr(i32) = COPY %0(i32)
+ %1:gpr(i32) = G_CTLZ %2(i32)
+ $s0 = COPY %1(i32)
RET_ReallyLR implicit $s0
...
@@ -134,9 +134,9 @@ body: |
; CHECK-NEXT: [[CLZv16i8_:%[0-9]+]]:fpr128 = CLZv16i8 [[COPY]]
; CHECK-NEXT: $q0 = COPY [[CLZv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = G_CTLZ %0(<16 x s8>)
- $q0 = COPY %1(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = G_CTLZ %0(<16 x i8>)
+ $q0 = COPY %1(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -157,9 +157,9 @@ body: |
; CHECK-NEXT: [[CLZv8i16_:%[0-9]+]]:fpr128 = CLZv8i16 [[COPY]]
; CHECK-NEXT: $q0 = COPY [[CLZv8i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = G_CTLZ %0(<8 x s16>)
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = G_CTLZ %0(<8 x i16>)
+ $q0 = COPY %1(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -180,9 +180,9 @@ body: |
; CHECK-NEXT: [[CLZv4i32_:%[0-9]+]]:fpr128 = CLZv4i32 [[COPY]]
; CHECK-NEXT: $q0 = COPY [[CLZv4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = G_CTLZ %0(<4 x s32>)
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = G_CTLZ %0(<4 x i32>)
+ $q0 = COPY %1(<4 x i32>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ctpop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ctpop.mir
index d6d41615c37ea..9434f41569c61 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ctpop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ctpop.mir
@@ -18,9 +18,9 @@ body: |
; CHECK-NEXT: %ctpop:fpr64 = CNTv8i8 %copy
; CHECK-NEXT: $d0 = COPY %ctpop
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %copy:fpr(<8 x s8>) = COPY $d0
- %ctpop:fpr(<8 x s8>) = G_CTPOP %copy(<8 x s8>)
- $d0 = COPY %ctpop(<8 x s8>)
+ %copy:fpr(<8 x i8>) = COPY $d0
+ %ctpop:fpr(<8 x i8>) = G_CTPOP %copy(<8 x i8>)
+ $d0 = COPY %ctpop(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -40,9 +40,9 @@ body: |
; CHECK-NEXT: %ctpop:fpr128 = CNTv16i8 %copy
; CHECK-NEXT: $q0 = COPY %ctpop
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %copy:fpr(<16 x s8>) = COPY $q0
- %ctpop:fpr(<16 x s8>) = G_CTPOP %copy(<16 x s8>)
- $q0 = COPY %ctpop(<16 x s8>)
+ %copy:fpr(<16 x i8>) = COPY $q0
+ %ctpop:fpr(<16 x i8>) = G_CTPOP %copy(<16 x i8>)
+ $q0 = COPY %ctpop(<16 x i8>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cttz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cttz.mir
index 0458d9f6ce283..87840d544cf05 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cttz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cttz.mir
@@ -27,9 +27,9 @@ body: |
; CHECK-CSSC-NEXT: [[CTZWr:%[0-9]+]]:gpr32 = CTZWr [[COPY]]
; CHECK-CSSC-NEXT: $w0 = COPY [[CTZWr]]
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CTTZ %0(s32)
- $w0 = COPY %1(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CTTZ %0(i32)
+ $w0 = COPY %1(i32)
RET_ReallyLR implicit $w0
...
@@ -58,9 +58,9 @@ body: |
; CHECK-CSSC-NEXT: [[CTZXr:%[0-9]+]]:gpr64 = CTZXr [[COPY]]
; CHECK-CSSC-NEXT: $x0 = COPY [[CTZXr]]
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CTTZ %0(s64)
- $x0 = COPY %1(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CTTZ %0(i64)
+ $x0 = COPY %1(i64)
RET_ReallyLR implicit $x0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
index 237e158d55311..b28ebbb90a79c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
@@ -49,10 +49,10 @@ body: |
; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY]]
; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
; CHECK-NEXT: DBG_VALUE [[ADDWrr]], $noreg, !7, !DIExpression(), debug-location !9
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_ADD %0, %0
- $w0 = COPY %1(s32)
- DBG_VALUE %1(s32), $noreg, !7, !DIExpression(), debug-location !9
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_ADD %0, %0
+ $w0 = COPY %1(i32)
+ DBG_VALUE %1(i32), $noreg, !7, !DIExpression(), debug-location !9
...
---
@@ -66,7 +66,7 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: DBG_VALUE %1:gpr64, $noreg, !7, !DIExpression(), debug-location !9
- %0:gpr(s32) = COPY $w0
- %1:gpr(s64) = G_ZEXT %0:gpr(s32)
- DBG_VALUE %1(s64), $noreg, !7, !DIExpression(), debug-location !9
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i64) = G_ZEXT %0:gpr(i32)
+ DBG_VALUE %1(i64), $noreg, !7, !DIExpression(), debug-location !9
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
index 2a7a50a5597a7..a10a5c80397b8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
@@ -444,7 +444,9 @@ body: |
; CHECK-LABEL: name: cst_v2p0
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %cst:gpr64 = MOVi64imm 3
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
+ ; CHECK-NEXT: %cst:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %cst
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir
index a487c16f839d2..3b2528dd0a82e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir
@@ -30,9 +30,9 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $w2
; CHECK-NEXT: [[FMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]], implicit $fpcr
; CHECK-NEXT: $w0 = COPY [[FMADDSrrr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = COPY $w2
- %3(s32) = G_FMA %0, %1, %2
+ %0(f32) = COPY $w0
+ %1(f32) = COPY $w1
+ %2(f32) = COPY $w2
+ %3(f32) = G_FMA %0, %1, %2
$w0 = COPY %3
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
index d0ac97e6908aa..caa1f7e7ef19b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
@@ -66,10 +66,10 @@ body: |
%6:gpr(p0) = COPY %7(p0)
%0:gpr(p0) = G_FRAME_INDEX %stack.0.retval
G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.retval)
- %2:gpr(s32) = G_LOAD %3(p0) :: (load (s32) from @foo1)
- %5:gpr(s32) = G_LOAD %6(p0) :: (load (s32) from @foo2)
- %8:gpr(s32) = G_ADD %2, %5
- $w0 = COPY %8(s32)
+ %2:gpr(i32) = G_LOAD %3(p0) :: (load (s32) from @foo1)
+ %5:gpr(i32) = G_LOAD %6(p0) :: (load (s32) from @foo2)
+ %8:gpr(i32) = G_ADD %2, %5
+ $w0 = COPY %8(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
index 3a616c9d3c346..65e85f37c21e3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
@@ -47,10 +47,10 @@ body: |
%6:gpr(p0) = COPY %7(p0)
%0:gpr(p0) = G_FRAME_INDEX %stack.0.retval
G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.retval)
- %2:gpr(s32) = G_LOAD %3(p0) :: (load (s32) from @foo1)
- %5:gpr(s32) = G_LOAD %6(p0) :: (load (s32) from @foo2)
- %8:gpr(s32) = G_ADD %2, %5
- $w0 = COPY %8(s32)
+ %2:gpr(i32) = G_LOAD %3(p0) :: (load (s32) from @foo1)
+ %5:gpr(i32) = G_LOAD %6(p0) :: (load (s32) from @foo2)
+ %8:gpr(i32) = G_ADD %2, %5
+ $w0 = COPY %8(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
index ada185c2c9dc0..9a54a20200367 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
@@ -22,9 +22,9 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[DEF]], [[DEF]]
; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
- %0(s32) = G_IMPLICIT_DEF
- %1(s32) = G_ADD %0, %0
- $w0 = COPY %1(s32)
+ %0(i32) = G_IMPLICIT_DEF
+ %1(i32) = G_ADD %0, %0
+ $w0 = COPY %1(i32)
...
---
name: implicit_def_copy
@@ -40,7 +40,7 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY [[DEF]]
; CHECK-NEXT: $w0 = COPY [[COPY]]
- %0(s32) = G_IMPLICIT_DEF
- %1(s32) = COPY %0(s32)
- $w0 = COPY %1(s32)
+ %0(i32) = G_IMPLICIT_DEF
+ %1(i32) = COPY %0(i32)
+ $w0 = COPY %1(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
index c2d03330cf41c..b4509f694861a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
@@ -47,9 +47,9 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[INSERT_SUBREG]]
- %0(s32) = COPY $w0
- %1(s64) = G_ANYEXT %0
- $x0 = COPY %1(s64)
+ %0(i32) = COPY $w0
+ %1(i64) = G_ANYEXT %0
+ $x0 = COPY %1(i64)
...
---
@@ -71,10 +71,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %2:gpr(s32) = COPY $w0
- %0(s8) = G_TRUNC %2
- %1(s32) = G_ANYEXT %0
- $w0 = COPY %1(s32)
+ %2:gpr(i32) = COPY $w0
+ %0(i8) = G_TRUNC %2
+ %1(i32) = G_ANYEXT %0
+ $w0 = COPY %1(i32)
...
---
@@ -98,9 +98,9 @@ body: |
; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
; CHECK-NEXT: $q0 = COPY [[USHLLv8i8_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s16>) = G_ANYEXT %0(<8 x s8>)
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i16>) = G_ANYEXT %0(<8 x i8>)
+ $q0 = COPY %1(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -125,9 +125,9 @@ body: |
; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
; CHECK-NEXT: $q0 = COPY [[USHLLv4i16_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s32>) = G_ANYEXT %0(<4 x s16>)
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i32>) = G_ANYEXT %0(<4 x i16>)
+ $q0 = COPY %1(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -152,9 +152,9 @@ body: |
; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
; CHECK-NEXT: $q0 = COPY [[USHLLv2i32_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s64>) = G_ANYEXT %0(<2 x s32>)
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i64>) = G_ANYEXT %0(<2 x i32>)
+ $q0 = COPY %1(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -178,9 +178,9 @@ body: |
; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY]], 0
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
- %0(s32) = COPY $w0
- %1(s64) = G_ZEXT %0
- $x0 = COPY %1(s64)
+ %0(i32) = COPY $w0
+ %1(i64) = G_ZEXT %0
+ $x0 = COPY %1(i64)
...
---
@@ -202,9 +202,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
- %2:gpr(s32) = COPY $w0
- %0(s16) = G_TRUNC %2
- %1(s32) = G_ZEXT %0
+ %2:gpr(i32) = COPY $w0
+ %0(i16) = G_TRUNC %2
+ %1(i32) = G_ZEXT %0
$w0 = COPY %1
...
@@ -227,10 +227,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
- %2:gpr(s32) = COPY $w0
- %0(s16) = G_TRUNC %2
- %1(s32) = G_ZEXT %0
- $w0 = COPY %1(s32)
+ %2:gpr(i32) = COPY $w0
+ %0(i16) = G_TRUNC %2
+ %1(i32) = G_ZEXT %0
+ $w0 = COPY %1(i32)
...
---
@@ -253,11 +253,11 @@ body: |
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[UBFMWri]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %2:gpr(s32) = COPY $w0
- %0(s8) = G_TRUNC %2
- %1(s16) = G_ZEXT %0
- %3:gpr(s32) = G_ANYEXT %1
- $w0 = COPY %3(s32)
+ %2:gpr(i32) = COPY $w0
+ %0(i8) = G_TRUNC %2
+ %1(i16) = G_ZEXT %0
+ %3:gpr(i32) = G_ANYEXT %1
+ $w0 = COPY %3(i32)
...
---
@@ -281,9 +281,9 @@ body: |
; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
; CHECK-NEXT: $q0 = COPY [[USHLLv8i8_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i16>) = G_ZEXT %0(<8 x i8>)
+ $q0 = COPY %1(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -309,9 +309,9 @@ body: |
; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
; CHECK-NEXT: $q0 = COPY [[USHLLv4i16_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>)
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i32>) = G_ZEXT %0(<4 x i16>)
+ $q0 = COPY %1(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -336,9 +336,9 @@ body: |
; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
; CHECK-NEXT: $q0 = COPY [[USHLLv2i32_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>)
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i64>) = G_ZEXT %0(<2 x i32>)
+ $q0 = COPY %1(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -363,9 +363,9 @@ body: |
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31
; CHECK-NEXT: $x0 = COPY [[SBFMXri]]
- %0(s32) = COPY $w0
- %1(s64) = G_SEXT %0
- $x0 = COPY %1(s64)
+ %0(i32) = COPY $w0
+ %1(i64) = G_SEXT %0
+ $x0 = COPY %1(i64)
...
---
@@ -387,9 +387,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 15
; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
- %2:gpr(s32) = COPY $w0
- %0(s16) = G_TRUNC %2
- %1(s32) = G_SEXT %0
+ %2:gpr(i32) = COPY $w0
+ %0(i16) = G_TRUNC %2
+ %1(i32) = G_SEXT %0
$w0 = COPY %1
...
@@ -412,10 +412,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
- %2:gpr(s32) = COPY $w0
- %0(s8) = G_TRUNC %2
- %1(s32) = G_SEXT %0
- $w0 = COPY %1(s32)
+ %2:gpr(i32) = COPY $w0
+ %0(i8) = G_TRUNC %2
+ %1(i32) = G_SEXT %0
+ $w0 = COPY %1(i32)
...
---
@@ -438,11 +438,11 @@ body: |
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %2:gpr(s32) = COPY $w0
- %0(s8) = G_TRUNC %2
- %1(s16) = G_SEXT %0
- %3:gpr(s32) = G_ANYEXT %1
- $w0 = COPY %3(s32)
+ %2:gpr(i32) = COPY $w0
+ %0(i8) = G_TRUNC %2
+ %1(i16) = G_SEXT %0
+ %3:gpr(i32) = G_ANYEXT %1
+ $w0 = COPY %3(i32)
...
---
@@ -466,9 +466,9 @@ body: |
; CHECK-NEXT: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
; CHECK-NEXT: $q0 = COPY [[SSHLLv8i8_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s16>) = G_SEXT %0(<8 x s8>)
- $q0 = COPY %1(<8 x s16>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i16>) = G_SEXT %0(<8 x i8>)
+ $q0 = COPY %1(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -494,9 +494,9 @@ body: |
; CHECK-NEXT: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0
; CHECK-NEXT: $q0 = COPY [[SSHLLv4i16_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s32>) = G_SEXT %0(<4 x s16>)
- $q0 = COPY %1(<4 x s32>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i32>) = G_SEXT %0(<4 x i16>)
+ $q0 = COPY %1(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -521,7 +521,7 @@ body: |
; CHECK-NEXT: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
; CHECK-NEXT: $q0 = COPY [[SSHLLv2i32_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s64>) = G_SEXT %0(<2 x s32>)
- $q0 = COPY %1(<2 x s64>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i64>) = G_SEXT %0(<2 x i32>)
+ $q0 = COPY %1(<2 x i64>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
index c8db8445d0e2d..e50f0fd21e7a9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
@@ -76,9 +76,9 @@ body: |
; CHECK-NEXT: $w0 = COPY %int
; CHECK-NEXT: RET_ReallyLR implicit $w0
%ptr:gpr(p0) = COPY $x0
- %ptr2int:gpr(s64) = G_PTRTOINT %ptr(p0)
- %int:gpr(s32) = G_TRUNC %ptr2int(s64)
- $w0 = COPY %int(s32)
+ %ptr2int:gpr(i64) = G_PTRTOINT %ptr(p0)
+ %int:gpr(i32) = G_TRUNC %ptr2int(i64)
+ $w0 = COPY %int(i32)
RET_ReallyLR implicit $w0
...
@@ -103,8 +103,8 @@ body: |
; CHECK-NEXT: $h0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
%ptr:gpr(p0) = COPY $x0
- %ptr2int:gpr(s64) = G_PTRTOINT %ptr(p0)
- %int:gpr(s16) = G_TRUNC %ptr2int(s64)
+ %ptr2int:gpr(i64) = G_PTRTOINT %ptr(p0)
+ %int:gpr(s16) = G_TRUNC %ptr2int(i64)
$h0 = COPY %int(s16)
RET_ReallyLR implicit $h0
...
@@ -130,8 +130,8 @@ body: |
; CHECK-NEXT: $b0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $b0
%ptr:gpr(p0) = COPY $x0
- %ptr2int:gpr(s64) = G_PTRTOINT %ptr(p0)
- %int:gpr(s8) = G_TRUNC %ptr2int(s64)
+ %ptr2int:gpr(i64) = G_PTRTOINT %ptr(p0)
+ %int:gpr(s8) = G_TRUNC %ptr2int(i64)
$b0 = COPY %int(s8)
RET_ReallyLR implicit $b0
@@ -157,11 +157,11 @@ body: |
; CHECK-NEXT: $w0 = COPY %ext
; CHECK-NEXT: RET_ReallyLR implicit $w0
%ptr:gpr(p0) = COPY $x0
- %ptr2int:gpr(s64) = G_PTRTOINT %ptr(p0)
- %one:gpr(s32) = G_CONSTANT i32 1
- %trunc:gpr(s32) = G_TRUNC %ptr2int(s64)
- %ext:gpr(s32) = G_AND %trunc, %one
- $w0 = COPY %ext(s32)
+ %ptr2int:gpr(i64) = G_PTRTOINT %ptr(p0)
+ %one:gpr(i32) = G_CONSTANT i32 1
+ %trunc:gpr(i32) = G_TRUNC %ptr2int(i64)
+ %ext:gpr(i32) = G_AND %trunc, %one
+ $w0 = COPY %ext(i32)
RET_ReallyLR implicit $w0
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
index 8b1f73ec11937..2648955875f18 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
@@ -93,37 +93,37 @@ body: |
bb.1.entry:
liveins: $w0
- %0:gpr(s32) = COPY $w0
- %4:gpr(s32) = G_CONSTANT i32 71
- %8:gpr(s32) = G_CONSTANT i32 3
- %10:gpr(s32) = G_CONSTANT i32 42
- %13:gpr(s32) = G_CONSTANT i32 0
- %1:gpr(s32) = G_CONSTANT i32 4
- %2:gpr(s32) = G_SUB %0, %1
- %3:gpr(s64) = G_ZEXT %2(s32)
- %5:gpr(s64) = G_ZEXT %4(s32)
- %14:gpr(s32) = G_ICMP intpred(ugt), %3(s64), %5
+ %0:gpr(i32) = COPY $w0
+ %4:gpr(i32) = G_CONSTANT i32 71
+ %8:gpr(i32) = G_CONSTANT i32 3
+ %10:gpr(i32) = G_CONSTANT i32 42
+ %13:gpr(i32) = G_CONSTANT i32 0
+ %1:gpr(i32) = G_CONSTANT i32 4
+ %2:gpr(i32) = G_SUB %0, %1
+ %3:gpr(i64) = G_ZEXT %2(i32)
+ %5:gpr(i64) = G_ZEXT %4(i32)
+ %14:gpr(i32) = G_ICMP intpred(ugt), %3(i64), %5
G_BRCOND %14, %bb.4
bb.5.entry:
successors: %bb.3, %bb.4, %bb.2
- %17:gpr(s32) = G_CONSTANT i32 0
+ %17:gpr(i32) = G_CONSTANT i32 0
%7:gpr(p0) = G_JUMP_TABLE %jump-table.0
- G_BRJT %7(p0), %jump-table.0, %3(s64)
+ G_BRJT %7(p0), %jump-table.0, %3(i64)
bb.2.sw.bb:
- %16:gpr(s32) = G_CONSTANT i32 42
- %11:gpr(s32) = nsw G_ADD %0, %16
+ %16:gpr(i32) = G_CONSTANT i32 42
+ %11:gpr(i32) = nsw G_ADD %0, %16
G_BR %bb.4
bb.3.sw.bb1:
- %15:gpr(s32) = G_CONSTANT i32 3
- %9:gpr(s32) = nsw G_MUL %0, %15
+ %15:gpr(i32) = G_CONSTANT i32 3
+ %9:gpr(i32) = nsw G_MUL %0, %15
bb.4.return:
- %12:gpr(s32) = G_PHI %9(s32), %bb.3, %11(s32), %bb.2, %13(s32), %bb.1, %17(s32), %bb.5
- $w0 = COPY %12(s32)
+ %12:gpr(i32) = G_PHI %9(i32), %bb.3, %11(i32), %bb.2, %13(i32), %bb.1, %17(i32), %bb.5
+ $w0 = COPY %12(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-logical-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-logical-imm.mir
index 58f3acc0d5495..86652fbe46340 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-logical-imm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-logical-imm.mir
@@ -16,10 +16,10 @@ body: |
; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
; CHECK-NEXT: $x0 = COPY [[ANDXri]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 1
- %2:gpr(s64) = G_AND %0, %1:gpr(s64)
- $x0 = COPY %2:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 1
+ %2:gpr(i64) = G_AND %0, %1:gpr(i64)
+ $x0 = COPY %2:gpr(i64)
RET_ReallyLR implicit $x0
...
---
@@ -37,10 +37,10 @@ body: |
; CHECK-NEXT: [[ORRXri:%[0-9]+]]:gpr64sp = ORRXri [[COPY]], 4096
; CHECK-NEXT: $x0 = COPY [[ORRXri]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 1
- %2:gpr(s64) = G_OR %0, %1:gpr(s64)
- $x0 = COPY %2:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 1
+ %2:gpr(i64) = G_OR %0, %1:gpr(i64)
+ $x0 = COPY %2:gpr(i64)
RET_ReallyLR implicit $x0
...
---
@@ -58,10 +58,10 @@ body: |
; CHECK-NEXT: [[EORXri:%[0-9]+]]:gpr64sp = EORXri [[COPY]], 4096
; CHECK-NEXT: $x0 = COPY [[EORXri]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 1
- %2:gpr(s64) = G_XOR %0, %1:gpr(s64)
- $x0 = COPY %2:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 1
+ %2:gpr(i64) = G_XOR %0, %1:gpr(i64)
+ $x0 = COPY %2:gpr(i64)
RET_ReallyLR implicit $x0
...
---
@@ -79,10 +79,10 @@ body: |
; CHECK-NEXT: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[COPY]], 0
; CHECK-NEXT: $w0 = COPY [[ANDWri]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_AND %0, %1:gpr(s32)
- $w0 = COPY %2:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_AND %0, %1:gpr(i32)
+ $w0 = COPY %2:gpr(i32)
RET_ReallyLR implicit $w0
...
---
@@ -100,10 +100,10 @@ body: |
; CHECK-NEXT: [[ORRWri:%[0-9]+]]:gpr32sp = ORRWri [[COPY]], 0
; CHECK-NEXT: $w0 = COPY [[ORRWri]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_OR %0, %1:gpr(s32)
- $w0 = COPY %2:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_OR %0, %1:gpr(i32)
+ $w0 = COPY %2:gpr(i32)
RET_ReallyLR implicit $w0
...
---
@@ -121,9 +121,9 @@ body: |
; CHECK-NEXT: [[EORWri:%[0-9]+]]:gpr32sp = EORWri [[COPY]], 0
; CHECK-NEXT: $w0 = COPY [[EORWri]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 1
- %2:gpr(s32) = G_XOR %0, %1:gpr(s32)
- $w0 = COPY %2:gpr(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 1
+ %2:gpr(i32) = G_XOR %0, %1:gpr(i32)
+ $w0 = COPY %2:gpr(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-logical-shifted-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-logical-shifted-reg.mir
index 391069de8f0ca..7b1a115305e10 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-logical-shifted-reg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-logical-shifted-reg.mir
@@ -19,13 +19,13 @@ body: |
; CHECK-NEXT: [[BICXrs:%[0-9]+]]:gpr64 = BICXrs [[COPY]], [[COPY]], 8
; CHECK-NEXT: $x0 = COPY [[BICXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_CONSTANT i64 -1
- %3:gpr(s64) = G_SHL %0, %1:gpr(s64)
- %4:gpr(s64) = G_XOR %3, %2:gpr(s64)
- %5:gpr(s64) = G_AND %0, %4:gpr(s64)
- $x0 = COPY %5:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_CONSTANT i64 -1
+ %3:gpr(i64) = G_SHL %0, %1:gpr(i64)
+ %4:gpr(i64) = G_XOR %3, %2:gpr(i64)
+ %5:gpr(i64) = G_AND %0, %4:gpr(i64)
+ $x0 = COPY %5:gpr(i64)
RET_ReallyLR implicit $x0
...
---
@@ -43,13 +43,13 @@ body: |
; CHECK-NEXT: [[ORNXrs:%[0-9]+]]:gpr64 = ORNXrs [[COPY]], [[COPY]], 8
; CHECK-NEXT: $x0 = COPY [[ORNXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_CONSTANT i64 -1
- %3:gpr(s64) = G_SHL %0, %1:gpr(s64)
- %4:gpr(s64) = G_XOR %3, %2:gpr(s64)
- %5:gpr(s64) = G_OR %0, %4:gpr(s64)
- $x0 = COPY %5:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_CONSTANT i64 -1
+ %3:gpr(i64) = G_SHL %0, %1:gpr(i64)
+ %4:gpr(i64) = G_XOR %3, %2:gpr(i64)
+ %5:gpr(i64) = G_OR %0, %4:gpr(i64)
+ $x0 = COPY %5:gpr(i64)
RET_ReallyLR implicit $x0
...
---
@@ -67,12 +67,12 @@ body: |
; CHECK-NEXT: [[EONXrs:%[0-9]+]]:gpr64 = EONXrs [[COPY]], [[COPY]], 8
; CHECK-NEXT: $x0 = COPY [[EONXrs]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_CONSTANT i64 -1
- %3:gpr(s64) = G_SHL %0, %1:gpr(s64)
- %4:gpr(s64) = G_XOR %3, %2:gpr(s64)
- %5:gpr(s64) = G_XOR %0, %4:gpr(s64)
- $x0 = COPY %5:gpr(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_CONSTANT i64 -1
+ %3:gpr(i64) = G_SHL %0, %1:gpr(i64)
+ %4:gpr(i64) = G_XOR %3, %2:gpr(i64)
+ %5:gpr(i64) = G_XOR %0, %4:gpr(i64)
+ $x0 = COPY %5:gpr(i64)
RET_ReallyLR implicit $x0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-mul.mir
index 2e803b613bea1..1bc8a94c70e16 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-mul.mir
@@ -26,11 +26,11 @@ body: |
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
; CHECK-NEXT: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], $xzr
; CHECK-NEXT: $x0 = COPY [[SMADDLrrr]]
- %0:gpr(s32) = COPY $w0
- %1:gpr(s64) = G_SEXT %0(s32)
- %2:gpr(s64) = G_CONSTANT i64 3
- %3:gpr(s64) = G_MUL %1, %2
- $x0 = COPY %3(s64)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i64) = G_SEXT %0(i32)
+ %2:gpr(i64) = G_CONSTANT i64 3
+ %3:gpr(i64) = G_MUL %1, %2
+ $x0 = COPY %3(i64)
...
---
name: umulh_v8s16
@@ -56,10 +56,10 @@ body: |
; CHECK-NEXT: %mul:fpr128 = UZP2v8i16 [[UMULLv4i16_v4i32_]], [[UMULLv8i16_v4i32_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %mul:fpr(<8 x s16>) = G_UMULH %0, %1
- $q0 = COPY %mul(<8 x s16>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %mul:fpr(<8 x i16>) = G_UMULH %0, %1
+ $q0 = COPY %mul(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -87,10 +87,10 @@ body: |
; CHECK-NEXT: %mul:fpr128 = UZP2v16i8 [[UMULLv8i8_v8i16_]], [[UMULLv16i8_v8i16_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %mul:fpr(<16 x s8>) = G_UMULH %0, %1
- $q0 = COPY %mul(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %mul:fpr(<16 x i8>) = G_UMULH %0, %1
+ $q0 = COPY %mul(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -118,10 +118,10 @@ body: |
; CHECK-NEXT: %mul:fpr128 = UZP2v4i32 [[UMULLv2i32_v2i64_]], [[UMULLv4i32_v2i64_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %mul:fpr(<4 x s32>) = G_UMULH %0, %1
- $q0 = COPY %mul(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %mul:fpr(<4 x i32>) = G_UMULH %0, %1
+ $q0 = COPY %mul(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -149,10 +149,10 @@ body: |
; CHECK-NEXT: %mul:fpr128 = UZP2v8i16 [[SMULLv4i16_v4i32_]], [[SMULLv8i16_v4i32_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %mul:fpr(<8 x s16>) = G_SMULH %0, %1
- $q0 = COPY %mul(<8 x s16>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %mul:fpr(<8 x i16>) = G_SMULH %0, %1
+ $q0 = COPY %mul(<8 x i16>)
RET_ReallyLR implicit $q0
...
@@ -180,10 +180,10 @@ body: |
; CHECK-NEXT: %mul:fpr128 = UZP2v16i8 [[SMULLv8i8_v8i16_]], [[SMULLv16i8_v8i16_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %mul:fpr(<16 x s8>) = G_SMULH %0, %1
- $q0 = COPY %mul(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %mul:fpr(<16 x i8>) = G_SMULH %0, %1
+ $q0 = COPY %mul(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -211,10 +211,10 @@ body: |
; CHECK-NEXT: %mul:fpr128 = UZP2v4i32 [[SMULLv2i32_v2i64_]], [[SMULLv4i32_v2i64_]]
; CHECK-NEXT: $q0 = COPY %mul
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %mul:fpr(<4 x s32>) = G_SMULH %0, %1
- $q0 = COPY %mul(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %mul:fpr(<4 x i32>) = G_SMULH %0, %1
+ $q0 = COPY %mul(<4 x i32>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-muladd.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-muladd.mir
index 13aa001311a2a..18298c3747983 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-muladd.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-muladd.mir
@@ -33,13 +33,13 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
; CHECK-NEXT: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK-NEXT: $x0 = COPY [[SMADDLrrr]]
- %0(s64) = COPY $x0
- %1(s32) = COPY $w1
- %2(s32) = COPY $w2
- %3(s64) = G_SEXT %1
- %4(s64) = G_SEXT %2
- %5(s64) = G_MUL %3, %4
- %6(s64) = G_ADD %0, %5
+ %0(i64) = COPY $x0
+ %1(i32) = COPY $w1
+ %2(i32) = COPY $w2
+ %3(i64) = G_SEXT %1
+ %4(i64) = G_SEXT %2
+ %5(i64) = G_MUL %3, %4
+ %6(i64) = G_ADD %0, %5
$x0 = COPY %6
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
index 265b12338f840..a3c86278923fb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
@@ -15,10 +15,10 @@ body: |
; CHECK-NEXT: %fcmp:fpr128 = nofpexcept FCMEQv2f64 %lhs, %rhs, implicit $fpcr
; CHECK-NEXT: $q0 = COPY %fcmp
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<2 x s64>) = COPY $q0
- %rhs:fpr(<2 x s64>) = COPY $q1
- %fcmp:fpr(<2 x s64>) = G_FCMEQ %lhs, %rhs(<2 x s64>)
- $q0 = COPY %fcmp(<2 x s64>)
+ %lhs:fpr(<2 x f64>) = COPY $q0
+ %rhs:fpr(<2 x f64>) = COPY $q1
+ %fcmp:fpr(<2 x i64>) = G_FCMEQ %lhs, %rhs(<2 x f64>)
+ $q0 = COPY %fcmp(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -35,10 +35,10 @@ body: |
; CHECK-NEXT: %fcmp:fpr128 = nofpexcept FCMGEv2f64 %lhs, %rhs, implicit $fpcr
; CHECK-NEXT: $q0 = COPY %fcmp
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<2 x s64>) = COPY $q0
- %rhs:fpr(<2 x s64>) = COPY $q1
- %fcmp:fpr(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
- $q0 = COPY %fcmp(<2 x s64>)
+ %lhs:fpr(<2 x f64>) = COPY $q0
+ %rhs:fpr(<2 x f64>) = COPY $q1
+ %fcmp:fpr(<2 x i64>) = G_FCMGE %lhs, %rhs(<2 x f64>)
+ $q0 = COPY %fcmp(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -55,10 +55,10 @@ body: |
; CHECK-NEXT: %fcmp:fpr128 = nofpexcept FCMGTv2f64 %lhs, %rhs, implicit $fpcr
; CHECK-NEXT: $q0 = COPY %fcmp
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<2 x s64>) = COPY $q0
- %rhs:fpr(<2 x s64>) = COPY $q1
- %fcmp:fpr(<2 x s64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
- $q0 = COPY %fcmp(<2 x s64>)
+ %lhs:fpr(<2 x f64>) = COPY $q0
+ %rhs:fpr(<2 x f64>) = COPY $q1
+ %fcmp:fpr(<2 x i64>) = G_FCMGT %lhs, %rhs(<2 x f64>)
+ $q0 = COPY %fcmp(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -74,11 +74,11 @@ body: |
; CHECK-NEXT: %fcmp:fpr128 = nofpexcept FCMEQv2i64rz %lhs, implicit $fpcr
; CHECK-NEXT: $q0 = COPY %fcmp
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<2 x s64>) = COPY $q0
- %zero:gpr(s64) = G_CONSTANT i64 0
- %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- %fcmp:fpr(<2 x s64>) = G_FCMEQ %lhs, %zero_vec(<2 x s64>)
- $q0 = COPY %fcmp(<2 x s64>)
+ %lhs:fpr(<2 x f64>) = COPY $q0
+ %zero:gpr(f64) = G_CONSTANT i64 0
+ %zero_vec:fpr(<2 x f64>) = G_BUILD_VECTOR %zero(f64), %zero(f64)
+ %fcmp:fpr(<2 x i64>) = G_FCMEQ %lhs, %zero_vec(<2 x f64>)
+ $q0 = COPY %fcmp(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -94,11 +94,11 @@ body: |
; CHECK-NEXT: %fcmp:fpr128 = nofpexcept FCMGEv2i64rz %lhs, implicit $fpcr
; CHECK-NEXT: $q0 = COPY %fcmp
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<2 x s64>) = COPY $q0
- %zero:gpr(s64) = G_CONSTANT i64 0
- %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- %fcmp:fpr(<2 x s64>) = G_FCMGE %lhs, %zero_vec(<2 x s64>)
- $q0 = COPY %fcmp(<2 x s64>)
+ %lhs:fpr(<2 x f64>) = COPY $q0
+ %zero:gpr(f64) = G_CONSTANT i64 0
+ %zero_vec:fpr(<2 x f64>) = G_BUILD_VECTOR %zero(f64), %zero(f64)
+ %fcmp:fpr(<2 x i64>) = G_FCMGE %lhs, %zero_vec(<2 x f64>)
+ $q0 = COPY %fcmp(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -114,11 +114,11 @@ body: |
; CHECK-NEXT: %fcmp:fpr128 = nofpexcept FCMGTv2i64rz %lhs, implicit $fpcr
; CHECK-NEXT: $q0 = COPY %fcmp
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<2 x s64>) = COPY $q0
- %zero:gpr(s64) = G_CONSTANT i64 0
- %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- %fcmp:fpr(<2 x s64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
- $q0 = COPY %fcmp(<2 x s64>)
+ %lhs:fpr(<2 x f64>) = COPY $q0
+ %zero:gpr(f64) = G_CONSTANT i64 0
+ %zero_vec:fpr(<2 x f64>) = G_BUILD_VECTOR %zero(f64), %zero(f64)
+ %fcmp:fpr(<2 x i64>) = G_FCMGT %lhs, %zero_vec(<2 x f64>)
+ $q0 = COPY %fcmp(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -134,11 +134,11 @@ body: |
; CHECK-NEXT: %fcmp:fpr128 = nofpexcept FCMLEv2i64rz %lhs, implicit $fpcr
; CHECK-NEXT: $q0 = COPY %fcmp
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<2 x s64>) = COPY $q0
- %zero:gpr(s64) = G_CONSTANT i64 0
- %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- %fcmp:fpr(<2 x s64>) = G_FCMGE %zero_vec(<2 x s64>), %lhs
- $q0 = COPY %fcmp(<2 x s64>)
+ %lhs:fpr(<2 x f64>) = COPY $q0
+ %zero:gpr(f64) = G_CONSTANT i64 0
+ %zero_vec:fpr(<2 x f64>) = G_BUILD_VECTOR %zero(f64), %zero(f64)
+ %fcmp:fpr(<2 x i64>) = G_FCMGE %zero_vec(<2 x f64>), %lhs
+ $q0 = COPY %fcmp(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -154,9 +154,9 @@ body: |
; CHECK-NEXT: %fcmp:fpr128 = nofpexcept FCMLTv2i64rz %lhs, implicit $fpcr
; CHECK-NEXT: $q0 = COPY %fcmp
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %lhs:fpr(<2 x s64>) = COPY $q0
- %zero:gpr(s64) = G_CONSTANT i64 0
- %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
- %fcmp:fpr(<2 x s64>) = G_FCMGT %zero_vec(<2 x s64>), %lhs
- $q0 = COPY %fcmp(<2 x s64>)
+ %lhs:fpr(<2 x f64>) = COPY $q0
+ %zero:gpr(f64) = G_CONSTANT i64 0
+ %zero_vec:fpr(<2 x f64>) = G_BUILD_VECTOR %zero(f64), %zero(f64)
+ %fcmp:fpr(<2 x i64>) = G_FCMGT %zero_vec(<2 x f64>), %lhs
+ $q0 = COPY %fcmp(<2 x i64>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
index 4409ffd2c852e..c71de4c1a6831 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
@@ -55,28 +55,28 @@ body: |
; CHECK-LABEL: name: test_phi
; CHECK: [[RES:%.*]]:gpr32 = PHI
- %0(s32) = COPY $w0
- %1(s32) = G_CONSTANT i32 0
- %3(s32) = G_CONSTANT i32 1
- %5(s32) = G_CONSTANT i32 2
- %8(s32) = G_ICMP intpred(ugt), %0(s32), %1
+ %0(i32) = COPY $w0
+ %1(i32) = G_CONSTANT i32 0
+ %3(i32) = G_CONSTANT i32 1
+ %5(i32) = G_CONSTANT i32 2
+ %8(i32) = G_ICMP intpred(ugt), %0(i32), %1
G_BRCOND %8, %bb.2.case1
G_BR %bb.3.case2
bb.2.case1:
successors: %bb.4.return(0x80000000)
- %4(s32) = G_ADD %0, %3
+ %4(i32) = G_ADD %0, %3
G_BR %bb.4.return
bb.3.case2:
successors: %bb.4.return(0x80000000)
- %6(s32) = G_ADD %0, %5
+ %6(i32) = G_ADD %0, %5
bb.4.return:
- %7(s32) = G_PHI %4(s32), %bb.2.case1, %6(s32), %bb.3.case2
- $w0 = COPY %7(s32)
+ %7(i32) = G_PHI %4(i32), %bb.2.case1, %6(i32), %bb.3.case2
+ $w0 = COPY %7(i32)
RET_ReallyLR implicit $w0
...
@@ -105,7 +105,7 @@ body: |
%0(p0) = COPY $x0
%1(p0) = COPY $x1
- %2:gpr(s32) = COPY $w2
+ %2:gpr(i32) = COPY $w2
G_BRCOND %2, %bb.1
G_BR %bb.2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
index 2bdf585d91286..b8bdd57f3a790 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
@@ -58,10 +58,10 @@ body: |
; CHECK-NEXT: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]]
; CHECK-NEXT: [[EORWri:%[0-9]+]]:gpr32sp = EORWri [[ORNWrr]], 0
; CHECK-NEXT: $w0 = COPY [[EORWri]]
- %0(s32) = G_CONSTANT i32 -1
- %3(s32) = G_CONSTANT i32 1
- %1(s32) = COPY $w0
- %2(s32) = G_XOR %1, %0
- %4(s32) = G_XOR %2, %3
- $w0 = COPY %4(s32)
+ %0(i32) = G_CONSTANT i32 -1
+ %3(i32) = G_CONSTANT i32 1
+ %1(i32) = COPY $w0
+ %2(i32) = G_XOR %1, %0
+ %4(i32) = G_XOR %2, %3
+ $w0 = COPY %4(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
index 87acc06df1940..b743cb9f7c578 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
@@ -23,11 +23,11 @@ body: |
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>))
- %2:fpr(s8) = G_VECREDUCE_ADD %1(<16 x s8>)
- %4:gpr(s8) = COPY %2(s8)
- %3:gpr(s32) = G_ANYEXT %4(s8)
- $w0 = COPY %3(s32)
+ %1:fpr(<16 x i8>) = G_LOAD %0(p0) :: (load (<16 x s8>))
+ %2:fpr(i8) = G_VECREDUCE_ADD %1(<16 x i8>)
+ %4:gpr(i8) = COPY %2(i8)
+ %3:gpr(i32) = G_ANYEXT %4(i8)
+ $w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
...
@@ -54,11 +54,11 @@ body: |
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>))
- %2:fpr(s16) = G_VECREDUCE_ADD %1(<8 x s16>)
- %4:gpr(s16) = COPY %2(s16)
- %3:gpr(s32) = G_ANYEXT %4(s16)
- $w0 = COPY %3(s32)
+ %1:fpr(<8 x i16>) = G_LOAD %0(p0) :: (load (<8 x s16>))
+ %2:fpr(i16) = G_VECREDUCE_ADD %1(<8 x i16>)
+ %4:gpr(i16) = COPY %2(i16)
+ %3:gpr(i32) = G_ANYEXT %4(i16)
+ $w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
...
@@ -83,9 +83,9 @@ body: |
; CHECK-NEXT: $w0 = COPY [[ADDVv4i32v]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>))
- %2:fpr(s32) = G_VECREDUCE_ADD %1(<4 x s32>)
- $w0 = COPY %2(s32)
+ %1:fpr(<4 x i32>) = G_LOAD %0(p0) :: (load (<4 x s32>))
+ %2:fpr(i32) = G_VECREDUCE_ADD %1(<4 x i32>)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -111,9 +111,9 @@ body: |
; CHECK-NEXT: $w0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %1:fpr(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
- %2:fpr(s32) = G_VECREDUCE_ADD %1(<2 x s32>)
- $w0 = COPY %2(s32)
+ %1:fpr(<2 x i32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
+ %2:fpr(i32) = G_VECREDUCE_ADD %1(<2 x i32>)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -138,9 +138,9 @@ body: |
; CHECK-NEXT: $x0 = COPY [[ADDPv2i64p]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
- %1:fpr(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>))
- %2:fpr(s64) = G_VECREDUCE_ADD %1(<2 x s64>)
- $x0 = COPY %2(s64)
+ %1:fpr(<2 x i64>) = G_LOAD %0(p0) :: (load (<2 x s64>))
+ %2:fpr(i64) = G_VECREDUCE_ADD %1(<2 x i64>)
+ $x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
index 3103ef512ad00..f5a94c7ad51fe 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
@@ -24,11 +24,11 @@ body: |
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_ADD %1, %0
- %3:gpr(s64) = G_ZEXT %2(s32)
- $x0 = COPY %3(s64)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_ADD %1, %0
+ %3:gpr(i64) = G_ZEXT %2(i32)
+ $x0 = COPY %3(i64)
RET_ReallyLR implicit $x0
...
@@ -53,8 +53,8 @@ body: |
; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(s16) = G_IMPLICIT_DEF
- %3:gpr(s64) = G_ZEXT %0(s16)
- $x0 = COPY %3(s64)
+ %3:gpr(i64) = G_ZEXT %0(s16)
+ $x0 = COPY %3(i64)
RET_ReallyLR implicit $x0
...
@@ -77,9 +77,9 @@ body: |
; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY %zext
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %copy:gpr(s32) = COPY $w0
- %zext:gpr(s64) = G_ZEXT %copy(s32)
- $x0 = COPY %zext(s64)
+ %copy:gpr(i32) = COPY $w0
+ %zext:gpr(i64) = G_ZEXT %copy(i32)
+ $x0 = COPY %zext(i64)
RET_ReallyLR implicit $x0
...
@@ -103,11 +103,11 @@ body: |
; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY %zext
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %copy:gpr(s32) = COPY $w0
- %bitcast0:gpr(<4 x s8>) = G_BITCAST %copy(s32)
- %bitcast1:gpr(s32) = G_BITCAST %bitcast0
- %zext:gpr(s64) = G_ZEXT %bitcast1(s32)
- $x0 = COPY %zext(s64)
+ %copy:gpr(i32) = COPY $w0
+ %bitcast0:gpr(<4 x s8>) = G_BITCAST %copy(i32)
+ %bitcast1:gpr(i32) = G_BITCAST %bitcast0
+ %zext:gpr(i64) = G_ZEXT %bitcast1(i32)
+ $x0 = COPY %zext(i64)
RET_ReallyLR implicit $x0
...
@@ -131,10 +131,10 @@ body: |
; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY %zext
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %copy:gpr(s64) = COPY $x0
- %trunc:gpr(s32) = G_TRUNC %copy(s64)
- %zext:gpr(s64) = G_ZEXT %trunc(s32)
- $x0 = COPY %zext(s64)
+ %copy:gpr(i64) = COPY $x0
+ %trunc:gpr(i32) = G_TRUNC %copy(i64)
+ %zext:gpr(i64) = G_ZEXT %trunc(i32)
+ $x0 = COPY %zext(i64)
RET_ReallyLR implicit $x0
...
@@ -169,18 +169,18 @@ body: |
bb.0:
liveins: $w0, $w1, $w2
- %copy1:gpr(s32) = COPY $w0
- %copy2:gpr(s32) = COPY $w1
- %cond_wide:gpr(s32) = COPY $w2
+ %copy1:gpr(i32) = COPY $w0
+ %copy2:gpr(i32) = COPY $w1
+ %cond_wide:gpr(i32) = COPY $w2
G_BRCOND %cond_wide, %bb.1
G_BR %bb.2
bb.1:
bb.2:
- %phi:gpr(s32) = G_PHI %copy1(s32), %bb.0, %copy2(s32), %bb.1
- %5:gpr(s64) = G_ZEXT %phi(s32)
- $x0 = COPY %5(s64)
+ %phi:gpr(i32) = G_PHI %copy1(i32), %bb.0, %copy2(i32), %bb.1
+ %5:gpr(i64) = G_ZEXT %phi(i32)
+ $x0 = COPY %5(i64)
RET_ReallyLR implicit $x0
...
@@ -205,10 +205,10 @@ body: |
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %2:gpr(s32) = G_ADD %1, %0
- %3:gpr(s32) = COPY %2(s32)
- %4:gpr(s64) = G_ZEXT %3(s32)
- $x0 = COPY %4(s64)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %2:gpr(i32) = G_ADD %1, %0
+ %3:gpr(i32) = COPY %2(i32)
+ %4:gpr(i64) = G_ZEXT %3(i32)
+ $x0 = COPY %4(i64)
RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-rotate.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-rotate.mir
index 2fb4df2a61dca..9382f4999876b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-rotate.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-rotate.mir
@@ -24,13 +24,13 @@ body: |
; CHECK-NEXT: [[EORWrs:%[0-9]+]]:gpr32 = EORWrs [[EXTRWrri]], [[COPY]], 198
; CHECK-NEXT: $w0 = COPY [[EORWrs]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %13:gpr(s64) = G_CONSTANT i64 6
- %2:gpr(s32) = G_ROTR %0, %13(s64)
- %14:gpr(s64) = G_CONSTANT i64 11
- %4:gpr(s32) = G_ROTR %0, %14(s64)
- %5:gpr(s32) = G_XOR %2, %4
- $w0 = COPY %5(s32)
+ %0:gpr(i32) = COPY $w0
+ %13:gpr(i64) = G_CONSTANT i64 6
+ %2:gpr(i32) = G_ROTR %0, %13(i64)
+ %14:gpr(i64) = G_CONSTANT i64 11
+ %4:gpr(i32) = G_ROTR %0, %14(i64)
+ %5:gpr(i32) = G_XOR %2, %4
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -58,12 +58,12 @@ body: |
; CHECK-NEXT: [[EORWrs:%[0-9]+]]:gpr32 = EORWrs [[COPY1]], [[COPY]], 198
; CHECK-NEXT: $w0 = COPY [[EORWrs]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = COPY $w1
- %9:gpr(s64) = G_CONSTANT i64 6
- %3:gpr(s32) = G_ROTR %0, %9(s64)
- %4:gpr(s32) = G_XOR %1, %3
- $w0 = COPY %4(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = COPY $w1
+ %9:gpr(i64) = G_CONSTANT i64 6
+ %3:gpr(i32) = G_ROTR %0, %9(i64)
+ %4:gpr(i32) = G_XOR %1, %3
+ $w0 = COPY %4(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir
index c802914bbb981..fed5ef1c24d3c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir
@@ -15,10 +15,10 @@ body: |
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 24, 23
; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 8
- %2:gpr(s32) = G_SHL %0, %1(s32)
- $w0 = COPY %2(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 8
+ %2:gpr(i32) = G_SHL %0, %1(i32)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -37,10 +37,10 @@ body: |
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 56, 55
; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_SHL %0, %1(s64)
- $x0 = COPY %2(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_SHL %0, %1(i64)
+ $x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
...
@@ -59,10 +59,10 @@ body: |
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 8, 31
; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %3:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s32) = G_LSHR %0, %3(s64)
- $w0 = COPY %2(s32)
+ %0:gpr(i32) = COPY $w0
+ %3:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i32) = G_LSHR %0, %3(i64)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -81,10 +81,10 @@ body: |
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 8, 63
; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_LSHR %0, %1(s64)
- $x0 = COPY %2(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_LSHR %0, %1(i64)
+ $x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
...
@@ -103,10 +103,10 @@ body: |
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 8, 31
; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %3:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s32) = G_ASHR %0, %3(s64)
- $w0 = COPY %2(s32)
+ %0:gpr(i32) = COPY $w0
+ %3:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i32) = G_ASHR %0, %3(i64)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -127,10 +127,10 @@ body: |
; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ASRVWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %3:gpr(s64) = G_CONSTANT i64 -8
- %2:gpr(s32) = G_ASHR %0, %3(s64)
- $w0 = COPY %2(s32)
+ %0:gpr(i32) = COPY $w0
+ %3:gpr(i64) = G_CONSTANT i64 -8
+ %2:gpr(i32) = G_ASHR %0, %3(i64)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -151,10 +151,10 @@ body: |
; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[LSRVWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %3:gpr(s64) = G_CONSTANT i64 -8
- %2:gpr(s32) = G_LSHR %0, %3(s64)
- $w0 = COPY %2(s32)
+ %0:gpr(i32) = COPY $w0
+ %3:gpr(i64) = G_CONSTANT i64 -8
+ %2:gpr(i32) = G_LSHR %0, %3(i64)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -173,10 +173,10 @@ body: |
; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[COPY]], 8, 63
; CHECK-NEXT: $x0 = COPY [[SBFMXri]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %0:gpr(s64) = COPY $x0
- %1:gpr(s64) = G_CONSTANT i64 8
- %2:gpr(s64) = G_ASHR %0, %1(s64)
- $x0 = COPY %2(s64)
+ %0:gpr(i64) = COPY $x0
+ %1:gpr(i64) = G_CONSTANT i64 8
+ %2:gpr(i64) = G_ASHR %0, %1(i64)
+ $x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
...
@@ -199,11 +199,11 @@ body: |
; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[LSRVWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %3:gpr(s64) = G_CONSTANT i64 8
- %4:gpr(s64) = G_AND %3, %3
- %2:gpr(s32) = G_LSHR %0, %4(s64)
- $w0 = COPY %2(s32)
+ %0:gpr(i32) = COPY $w0
+ %3:gpr(i64) = G_CONSTANT i64 8
+ %4:gpr(i64) = G_AND %3, %3
+ %2:gpr(i32) = G_LSHR %0, %4(i64)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -226,11 +226,11 @@ body: |
; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ASRVWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr(s32) = COPY $w0
- %3:gpr(s64) = G_CONSTANT i64 8
- %4:gpr(s64) = G_AND %3, %3
- %2:gpr(s32) = G_ASHR %0, %4(s64)
- $w0 = COPY %2(s32)
+ %0:gpr(i32) = COPY $w0
+ %3:gpr(i64) = G_CONSTANT i64 8
+ %4:gpr(i64) = G_AND %3, %3
+ %2:gpr(i32) = G_ASHR %0, %4(i64)
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
index e36e8c8b5ab29..0ac9017e3d296 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
@@ -23,11 +23,11 @@ body: |
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
- %0:gpr(s32) = COPY $w0
- %1:fpr(s32) = COPY $s0
- %2:fpr(s32) = COPY $s1
- %4:fpr(s32) = G_SELECT %0, %1, %2
- $s0 = COPY %4(s32)
+ %0:gpr(i32) = COPY $w0
+ %1:fpr(i32) = COPY $s0
+ %2:fpr(i32) = COPY $s1
+ %4:fpr(i32) = G_SELECT %0, %1, %2
+ $s0 = COPY %4(i32)
RET_ReallyLR implicit $s0
...
@@ -52,11 +52,11 @@ body: |
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:gpr(s32) = COPY $w0
- %1:fpr(s64) = COPY $d0
- %2:fpr(s64) = COPY $d1
- %4:fpr(s64) = G_SELECT %0, %1, %2
- $d0 = COPY %4(s64)
+ %0:gpr(i32) = COPY $w0
+ %1:fpr(i64) = COPY $d0
+ %2:fpr(i64) = COPY $d1
+ %4:fpr(i64) = G_SELECT %0, %1, %2
+ $d0 = COPY %4(i64)
RET_ReallyLR implicit $d0
...
---
@@ -78,13 +78,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSELWr %t, %f, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
- %t:gpr(s32) = COPY $w2
- %f:gpr(s32) = COPY $w3
- %select:gpr(s32) = G_SELECT %cmp, %t, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %reg0(i32), %reg1
+ %t:gpr(i32) = COPY $w2
+ %f:gpr(i32) = COPY $w3
+ %select:gpr(i32) = G_SELECT %cmp, %t, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
---
@@ -106,13 +106,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
- %t:gpr(s32) = G_CONSTANT i32 0
- %f:gpr(s32) = G_CONSTANT i32 1
- %select:gpr(s32) = G_SELECT %cmp, %t, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %reg0(i32), %reg1
+ %t:gpr(i32) = G_CONSTANT i32 0
+ %f:gpr(i32) = G_CONSTANT i32 1
+ %select:gpr(i32) = G_SELECT %cmp, %t, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
---
@@ -134,13 +134,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINVWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
- %t:gpr(s32) = G_CONSTANT i32 0
- %f:gpr(s32) = G_CONSTANT i32 -1
- %select:gpr(s32) = G_SELECT %cmp, %t, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %reg0(i32), %reg1
+ %t:gpr(i32) = G_CONSTANT i32 0
+ %f:gpr(i32) = G_CONSTANT i32 -1
+ %select:gpr(i32) = G_SELECT %cmp, %t, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
---
@@ -163,13 +163,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
- %t:gpr(s32) = G_CONSTANT i32 1
- %f:gpr(s32) = COPY $w2
- %select:gpr(s32) = G_SELECT %cmp, %t, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %reg0(i32), %reg1
+ %t:gpr(i32) = G_CONSTANT i32 1
+ %f:gpr(i32) = COPY $w2
+ %select:gpr(i32) = G_SELECT %cmp, %t, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
---
@@ -192,13 +192,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINVWr %f, $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
- %t:gpr(s32) = G_CONSTANT i32 -1
- %f:gpr(s32) = COPY $w2
- %select:gpr(s32) = G_SELECT %cmp, %t, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %reg0(i32), %reg1
+ %t:gpr(i32) = G_CONSTANT i32 -1
+ %f:gpr(i32) = COPY $w2
+ %select:gpr(i32) = G_SELECT %cmp, %t, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
---
@@ -221,13 +221,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
- %t:gpr(s32) = COPY $w2
- %f:gpr(s32) = G_CONSTANT i32 1
- %select:gpr(s32) = G_SELECT %cmp, %t, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %reg0(i32), %reg1
+ %t:gpr(i32) = COPY $w2
+ %f:gpr(i32) = G_CONSTANT i32 1
+ %select:gpr(i32) = G_SELECT %cmp, %t, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
---
@@ -250,13 +250,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINVWr %t, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
- %t:gpr(s32) = COPY $w2
- %f:gpr(s32) = G_CONSTANT i32 -1
- %select:gpr(s32) = G_SELECT %cmp, %t, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %cmp:gpr(i32) = G_ICMP intpred(ne), %reg0(i32), %reg1
+ %t:gpr(i32) = COPY $w2
+ %f:gpr(i32) = G_CONSTANT i32 -1
+ %select:gpr(i32) = G_SELECT %cmp, %t, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
---
@@ -278,11 +278,11 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %t:gpr(s32) = G_CONSTANT i32 1
- %f:gpr(s32) = COPY $w1
- %select:gpr(s32) = G_SELECT %reg0, %t, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %t:gpr(i32) = G_CONSTANT i32 1
+ %f:gpr(i32) = COPY $w1
+ %select:gpr(i32) = G_SELECT %reg0, %t, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
@@ -305,11 +305,11 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %t:gpr(s32) = COPY $w1
- %f:gpr(s32) = G_CONSTANT i32 1
- %select:gpr(s32) = G_SELECT %reg0, %t, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %t:gpr(i32) = COPY $w1
+ %f:gpr(i32) = G_CONSTANT i32 1
+ %select:gpr(i32) = G_SELECT %reg0, %t, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
@@ -333,12 +333,12 @@ body: |
; CHECK-NEXT: %select:gpr64 = CSINCXr %f, $xzr, 0, implicit $nzcv
; CHECK-NEXT: $x0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %reg0:gpr(s64) = COPY $x0
- %cond:gpr(s32) = G_TRUNC %reg0(s64)
- %t:gpr(s64) = G_CONSTANT i64 1
- %f:gpr(s64) = COPY $x1
- %select:gpr(s64) = G_SELECT %cond, %t, %f
- $x0 = COPY %select(s64)
+ %reg0:gpr(i64) = COPY $x0
+ %cond:gpr(i32) = G_TRUNC %reg0(i64)
+ %t:gpr(i64) = G_CONSTANT i64 1
+ %f:gpr(i64) = COPY $x1
+ %select:gpr(i64) = G_SELECT %cond, %t, %f
+ $x0 = COPY %select(i64)
RET_ReallyLR implicit $x0
...
@@ -362,13 +362,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg1, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %t:gpr(s32) = COPY $w2
- %zero:gpr(s32) = G_CONSTANT i32 0
- %sub:gpr(s32) = G_SUB %zero(s32), %reg1
- %select:gpr(s32) = G_SELECT %reg0, %t, %sub
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %t:gpr(i32) = COPY $w2
+ %zero:gpr(i32) = G_CONSTANT i32 0
+ %sub:gpr(i32) = G_SUB %zero(i32), %reg1
+ %select:gpr(i32) = G_SELECT %reg0, %t, %sub
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
@@ -392,13 +392,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSNEGWr %f, %reg1, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %f:gpr(s32) = COPY $w2
- %zero:gpr(s32) = G_CONSTANT i32 0
- %sub:gpr(s32) = G_SUB %zero(s32), %reg1
- %select:gpr(s32) = G_SELECT %reg0, %sub, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %f:gpr(i32) = COPY $w2
+ %zero:gpr(i32) = G_CONSTANT i32 0
+ %sub:gpr(i32) = G_SUB %zero(i32), %reg1
+ %select:gpr(i32) = G_SELECT %reg0, %sub, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
@@ -423,14 +423,14 @@ body: |
; CHECK-NEXT: %select:gpr64 = CSNEGXr %t, %reg1, 1, implicit $nzcv
; CHECK-NEXT: $x0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %reg0:gpr(s64) = COPY $x0
- %cond:gpr(s32) = G_TRUNC %reg0(s64)
- %reg1:gpr(s64) = COPY $x1
- %t:gpr(s64) = COPY $x2
- %zero:gpr(s64) = G_CONSTANT i64 0
- %sub:gpr(s64) = G_SUB %zero(s64), %reg1
- %select:gpr(s64) = G_SELECT %cond, %t, %sub
- $x0 = COPY %select(s64)
+ %reg0:gpr(i64) = COPY $x0
+ %cond:gpr(i32) = G_TRUNC %reg0(i64)
+ %reg1:gpr(i64) = COPY $x1
+ %t:gpr(i64) = COPY $x2
+ %zero:gpr(i64) = G_CONSTANT i64 0
+ %sub:gpr(i64) = G_SUB %zero(i64), %reg1
+ %select:gpr(i64) = G_SELECT %cond, %t, %sub
+ $x0 = COPY %select(i64)
RET_ReallyLR implicit $x0
...
---
@@ -454,14 +454,14 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg2, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %t:gpr(s32) = G_CONSTANT i32 1
- %zero:gpr(s32) = G_CONSTANT i32 0
- %reg2:gpr(s32) = COPY $w2
- %sub:gpr(s32) = G_SUB %zero(s32), %reg2
- %select:gpr(s32) = G_SELECT %reg0, %t, %sub
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %t:gpr(i32) = G_CONSTANT i32 1
+ %zero:gpr(i32) = G_CONSTANT i32 0
+ %reg2:gpr(i32) = COPY $w2
+ %sub:gpr(i32) = G_SUB %zero(i32), %reg2
+ %select:gpr(i32) = G_SELECT %reg0, %t, %sub
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
---
@@ -484,13 +484,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINVWr %t, %reg1, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %t:gpr(s32) = COPY $w2
- %negative_one:gpr(s32) = G_CONSTANT i32 -1
- %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one
- %select:gpr(s32) = G_SELECT %reg0, %t, %xor
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %t:gpr(i32) = COPY $w2
+ %negative_one:gpr(i32) = G_CONSTANT i32 -1
+ %xor:gpr(i32) = G_XOR %reg1(i32), %negative_one
+ %select:gpr(i32) = G_SELECT %reg0, %t, %xor
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
@@ -514,13 +514,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINVWr %f, %reg1, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %f:gpr(s32) = COPY $w2
- %negative_one:gpr(s32) = G_CONSTANT i32 -1
- %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one
- %select:gpr(s32) = G_SELECT %reg0, %xor, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %f:gpr(i32) = COPY $w2
+ %negative_one:gpr(i32) = G_CONSTANT i32 -1
+ %xor:gpr(i32) = G_XOR %reg1(i32), %negative_one
+ %select:gpr(i32) = G_SELECT %reg0, %xor, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
@@ -545,14 +545,14 @@ body: |
; CHECK-NEXT: %select:gpr64 = CSINVXr %t, %reg1, 1, implicit $nzcv
; CHECK-NEXT: $x0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %reg0:gpr(s64) = COPY $x0
- %reg1:gpr(s64) = COPY $x1
- %cond:gpr(s32) = G_TRUNC %reg0(s64)
- %t:gpr(s64) = COPY $x2
- %negative_one:gpr(s64) = G_CONSTANT i64 -1
- %xor:gpr(s64) = G_XOR %reg1(s64), %negative_one
- %select:gpr(s64) = G_SELECT %cond, %t, %xor
- $x0 = COPY %select(s64)
+ %reg0:gpr(i64) = COPY $x0
+ %reg1:gpr(i64) = COPY $x1
+ %cond:gpr(i32) = G_TRUNC %reg0(i64)
+ %t:gpr(i64) = COPY $x2
+ %negative_one:gpr(i64) = G_CONSTANT i64 -1
+ %xor:gpr(i64) = G_XOR %reg1(i64), %negative_one
+ %select:gpr(i64) = G_SELECT %cond, %t, %xor
+ $x0 = COPY %select(i64)
RET_ReallyLR implicit $x0
...
@@ -564,7 +564,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1, $x2
- ; zext(s32 -1) != s64 -1, so we can't fold it away.
+ ; zext(i32 -1) != i64 -1, so we can't fold it away.
; CHECK-LABEL: name: xor_not_negative_one
; CHECK: liveins: $x0, $x1, $x2
@@ -581,15 +581,15 @@ body: |
; CHECK-NEXT: %select:gpr64 = CSELXr %t, %xor, 1, implicit $nzcv
; CHECK-NEXT: $x0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %reg0:gpr(s64) = COPY $x0
- %reg1:gpr(s64) = COPY $x1
- %cond:gpr(s32) = G_TRUNC %reg0(s64)
- %t:gpr(s64) = COPY $x2
- %negative_one:gpr(s32) = G_CONSTANT i32 -1
- %zext:gpr(s64) = G_ZEXT %negative_one(s32)
- %xor:gpr(s64) = G_XOR %reg1(s64), %zext
- %select:gpr(s64) = G_SELECT %cond(s32), %t, %xor
- $x0 = COPY %select(s64)
+ %reg0:gpr(i64) = COPY $x0
+ %reg1:gpr(i64) = COPY $x1
+ %cond:gpr(i32) = G_TRUNC %reg0(i64)
+ %t:gpr(i64) = COPY $x2
+ %negative_one:gpr(i32) = G_CONSTANT i32 -1
+ %zext:gpr(i64) = G_ZEXT %negative_one(i32)
+ %xor:gpr(i64) = G_XOR %reg1(i64), %zext
+ %select:gpr(i64) = G_SELECT %cond(i32), %t, %xor
+ $x0 = COPY %select(i64)
RET_ReallyLR implicit $x0
...
@@ -612,13 +612,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINCWr %t, %reg1, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %t:gpr(s32) = COPY $w2
- %one:gpr(s32) = G_CONSTANT i32 1
- %add:gpr(s32) = G_ADD %reg1(s32), %one
- %select:gpr(s32) = G_SELECT %reg0, %t, %add
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %t:gpr(i32) = COPY $w2
+ %one:gpr(i32) = G_CONSTANT i32 1
+ %add:gpr(i32) = G_ADD %reg1(i32), %one
+ %select:gpr(i32) = G_SELECT %reg0, %t, %add
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
@@ -641,13 +641,13 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSINCWr %f, %reg1, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %f:gpr(s32) = COPY $w2
- %one:gpr(s32) = G_CONSTANT i32 1
- %add:gpr(s32) = G_ADD %reg1(s32), %one
- %select:gpr(s32) = G_SELECT %reg0, %add, %f
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %f:gpr(i32) = COPY $w2
+ %one:gpr(i32) = G_CONSTANT i32 1
+ %add:gpr(i32) = G_ADD %reg1(i32), %one
+ %select:gpr(i32) = G_SELECT %reg0, %add, %f
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
...
@@ -672,13 +672,13 @@ body: |
; CHECK-NEXT: %select:gpr64 = CSINCXr %t, %reg1, 1, implicit $nzcv
; CHECK-NEXT: $x0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $x0
- %reg0:gpr(s64) = COPY $x0
+ %reg0:gpr(i64) = COPY $x0
%reg1:gpr(p0) = COPY $x1
- %cond:gpr(s32) = G_TRUNC %reg0(s64)
+ %cond:gpr(i32) = G_TRUNC %reg0(i64)
%t:gpr(p0) = COPY $x2
- %one:gpr(s64) = G_CONSTANT i64 1
+ %one:gpr(i64) = G_CONSTANT i64 1
%ptr_add:gpr(p0) = G_PTR_ADD %reg1(p0), %one
- %select:gpr(p0) = G_SELECT %cond(s32), %t, %ptr_add
+ %select:gpr(p0) = G_SELECT %cond(i32), %t, %ptr_add
$x0 = COPY %select(p0)
RET_ReallyLR implicit $x0
@@ -702,14 +702,14 @@ body: |
; CHECK-NEXT: %select:gpr32 = CSNEGWr %xor, %reg2, 1, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %select
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %reg0:gpr(s32) = COPY $w0
- %reg1:gpr(s32) = COPY $w1
- %reg2:gpr(s32) = COPY $w2
- %f:gpr(s32) = COPY $w2
- %negative_one:gpr(s32) = G_CONSTANT i32 -1
- %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one
- %zero:gpr(s32) = G_CONSTANT i32 0
- %sub:gpr(s32) = G_SUB %zero(s32), %reg2
- %select:gpr(s32) = G_SELECT %reg0, %xor, %sub
- $w0 = COPY %select(s32)
+ %reg0:gpr(i32) = COPY $w0
+ %reg1:gpr(i32) = COPY $w1
+ %reg2:gpr(i32) = COPY $w2
+ %f:gpr(i32) = COPY $w2
+ %negative_one:gpr(i32) = G_CONSTANT i32 -1
+ %xor:gpr(i32) = G_XOR %reg1(i32), %negative_one
+ %zero:gpr(i32) = G_CONSTANT i32 0
+ %sub:gpr(i32) = G_SUB %zero(i32), %reg2
+ %select:gpr(i32) = G_SELECT %reg0, %xor, %sub
+ $w0 = COPY %select(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
index 8f3a8f761ae4d..d2bf5839f1be7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
@@ -24,8 +24,8 @@ body: |
; CHECK-NEXT: [[LDRSHWui:%[0-9]+]]:gpr32 = LDRSHWui [[COPY]], 0 :: (load (s16) from %ir.addr)
; CHECK-NEXT: $w0 = COPY [[LDRSHWui]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_SEXTLOAD %0 :: (load (s16) from %ir.addr)
- $w0 = COPY %1(s32)
+ %1:gpr(i32) = G_SEXTLOAD %0 :: (load (s16) from %ir.addr)
+ $w0 = COPY %1(i32)
...
---
@@ -45,7 +45,7 @@ body: |
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[LDRHHui]], 0, 15
; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)
- %2:gpr(s32) = G_SEXT %1
- $w0 = COPY %2(s32)
+ %1:gpr(i16) = G_LOAD %0 :: (load (s16) from %ir.addr)
+ %2:gpr(i32) = G_SEXT %1
+ $w0 = COPY %2(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
index fd2cc71dd9040..857ed9b3efbd3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
@@ -31,10 +31,10 @@ body: |
; CHECK-NEXT: early-clobber %2:gpr32 = STLXRX [[COPY]], [[COPY1]] :: (volatile store (s64) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %1:gpr(s64) = COPY $x1
+ %1:gpr(i64) = COPY $x1
%2:gpr(p0) = COPY $x2
- %3:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %1(s64), %2(p0) :: (volatile store (s64) into %ir.addr)
- $w0 = COPY %3(s32)
+ %3:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %1(i64), %2(p0) :: (volatile store (s64) into %ir.addr)
+ $w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
...
@@ -55,11 +55,11 @@ body: |
; CHECK-NEXT: early-clobber %3:gpr32 = STLXRW [[COPY]], [[COPY1]] :: (volatile store (s32) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %1:gpr(s32) = COPY $w1
+ %1:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
- %3:gpr(s64) = G_ZEXT %1(s32)
- %4:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %3(s64), %2(p0) :: (volatile store (s32) into %ir.addr)
- $w0 = COPY %4(s32)
+ %3:gpr(i64) = G_ZEXT %1(i32)
+ %4:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %3(i64), %2(p0) :: (volatile store (s32) into %ir.addr)
+ $w0 = COPY %4(i32)
RET_ReallyLR implicit $w0
...
@@ -84,13 +84,13 @@ body: |
; CHECK-NEXT: early-clobber %5:gpr32 = STLXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %5
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %3:gpr(s32) = COPY $w1
+ %3:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
- %6:gpr(s64) = G_CONSTANT i64 255
- %7:gpr(s64) = G_ANYEXT %3(s32)
- %4:gpr(s64) = G_AND %7, %6
- %5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(s64), %2(p0) :: (volatile store (s8) into %ir.addr)
- $w0 = COPY %5(s32)
+ %6:gpr(i64) = G_CONSTANT i64 255
+ %7:gpr(i64) = G_ANYEXT %3(i32)
+ %4:gpr(i64) = G_AND %7, %6
+ %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(i64), %2(p0) :: (volatile store (s8) into %ir.addr)
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -115,11 +115,11 @@ body: |
; CHECK-NEXT: early-clobber %5:gpr32 = STLXRH [[COPY2]], [[COPY1]] :: (volatile store (s16) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %5
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %3:gpr(s32) = COPY $w1
+ %3:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
- %6:gpr(s64) = G_CONSTANT i64 65535
- %7:gpr(s64) = G_ANYEXT %3(s32)
- %4:gpr(s64) = G_AND %7, %6
- %5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(s64), %2(p0) :: (volatile store (s16) into %ir.addr)
- $w0 = COPY %5(s32)
+ %6:gpr(i64) = G_CONSTANT i64 65535
+ %7:gpr(i64) = G_ANYEXT %3(i32)
+ %4:gpr(i64) = G_AND %7, %6
+ %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(i64), %2(p0) :: (volatile store (s16) into %ir.addr)
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
index 31ba705fdadb6..3cc916e020095 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
@@ -29,13 +29,13 @@ body: |
; CHECK-NEXT: early-clobber %5:gpr32 = STXRB [[COPY2]], [[COPY1]] :: (volatile store (s8) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %5
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %3:gpr(s32) = COPY $w1
+ %3:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
- %6:gpr(s64) = G_CONSTANT i64 255
- %7:gpr(s64) = G_ANYEXT %3(s32)
- %4:gpr(s64) = G_AND %7, %6
- %5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(s64), %2(p0) :: (volatile store (s8) into %ir.addr)
- $w0 = COPY %5(s32)
+ %6:gpr(i64) = G_CONSTANT i64 255
+ %7:gpr(i64) = G_ANYEXT %3(i32)
+ %4:gpr(i64) = G_AND %7, %6
+ %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(i64), %2(p0) :: (volatile store (s8) into %ir.addr)
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -61,13 +61,13 @@ body: |
; CHECK-NEXT: early-clobber %5:gpr32 = STXRH [[COPY2]], [[COPY1]] :: (volatile store (s16) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %5
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %3:gpr(s32) = COPY $w1
+ %3:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
- %6:gpr(s64) = G_CONSTANT i64 65535
- %7:gpr(s64) = G_ANYEXT %3(s32)
- %4:gpr(s64) = G_AND %7, %6
- %5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(s64), %2(p0) :: (volatile store (s16) into %ir.addr)
- $w0 = COPY %5(s32)
+ %6:gpr(i64) = G_CONSTANT i64 65535
+ %7:gpr(i64) = G_ANYEXT %3(i32)
+ %4:gpr(i64) = G_AND %7, %6
+ %5:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(i64), %2(p0) :: (volatile store (s16) into %ir.addr)
+ $w0 = COPY %5(i32)
RET_ReallyLR implicit $w0
...
@@ -90,11 +90,11 @@ body: |
; CHECK-NEXT: early-clobber %3:gpr32 = STXRW [[COPY]], [[COPY1]] :: (volatile store (s32) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %1:gpr(s32) = COPY $w1
+ %1:gpr(i32) = COPY $w1
%2:gpr(p0) = COPY $x2
- %3:gpr(s64) = G_ZEXT %1(s32)
- %4:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %3(s64), %2(p0) :: (volatile store (s32) into %ir.addr)
- $w0 = COPY %4(s32)
+ %3:gpr(i64) = G_ZEXT %1(i32)
+ %4:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %3(i64), %2(p0) :: (volatile store (s32) into %ir.addr)
+ $w0 = COPY %4(i32)
RET_ReallyLR implicit $w0
...
@@ -117,10 +117,10 @@ body: |
; CHECK-NEXT: early-clobber %2:gpr32 = STXRX [[COPY]], [[COPY1]] :: (volatile store (s64) into %ir.addr)
; CHECK-NEXT: $w0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $w0
- %1:gpr(s64) = COPY $x1
+ %1:gpr(i64) = COPY $x1
%2:gpr(p0) = COPY $x2
- %3:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %1(s64), %2(p0) :: (volatile store (s64) into %ir.addr)
- $w0 = COPY %3(s32)
+ %3:gpr(i32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %1(i64), %2(p0) :: (volatile store (s64) into %ir.addr)
+ $w0 = COPY %3(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
index 6c91a374e67f7..c0b936332ca88 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
@@ -30,9 +30,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %0(s64) = COPY $x0
- %1(s32) = G_TRUNC %0
- $w0 = COPY %1(s32)
+ %0(i64) = COPY $x0
+ %1(i32) = G_TRUNC %0
+ $w0 = COPY %1(i32)
...
---
@@ -55,10 +55,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[COPY2]]
- %0(s64) = COPY $x0
- %1(s8) = G_TRUNC %0
- %2:gpr(s32) = G_ANYEXT %1
- $w0 = COPY %2(s32)
+ %0(i64) = COPY $x0
+ %1(i8) = G_TRUNC %0
+ %2:gpr(i32) = G_ANYEXT %1
+ $w0 = COPY %2(i32)
...
---
@@ -80,10 +80,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %0(s32) = COPY $w0
- %1(s8) = G_TRUNC %0
- %2:gpr(s32) = G_ANYEXT %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i8) = G_TRUNC %0
+ %2:gpr(i32) = G_ANYEXT %1
+ $w0 = COPY %2(i32)
...
---
@@ -105,8 +105,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: $x0 = COPY [[COPY1]]
%0(s128) = COPY $q0
- %1(s64) = G_TRUNC %0
- $x0 = COPY %1(s64)
+ %1(i64) = G_TRUNC %0
+ $x0 = COPY %1(i64)
...
---
@@ -128,6 +128,6 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(s128) = COPY $q0
- %1(s32) = G_TRUNC %0
- $w0 = COPY %1(s32)
+ %1(i32) = G_TRUNC %0
+ $w0 = COPY %1(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-unreachable-blocks.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-unreachable-blocks.mir
index 70f08d0685611..f4f98bc4a1e17 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-unreachable-blocks.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-unreachable-blocks.mir
@@ -36,25 +36,25 @@ body: |
successors: %bb.3
liveins: $w0
- %0:gpr(s32) = COPY $w0
- %1:gpr(s32) = G_CONSTANT i32 0
- %3:gpr(s32) = G_CONSTANT i32 1
- %5:gpr(s32) = G_CONSTANT i32 2
+ %0:gpr(i32) = COPY $w0
+ %1:gpr(i32) = G_CONSTANT i32 0
+ %3:gpr(i32) = G_CONSTANT i32 1
+ %5:gpr(i32) = G_CONSTANT i32 2
G_BR %bb.3
bb.5:
; This block is unreachable.
- %unreachable_inst:gpr(s32) = G_XOR %1, %3
- $w0 = COPY %unreachable_inst(s32)
+ %unreachable_inst:gpr(i32) = G_XOR %1, %3
+ $w0 = COPY %unreachable_inst(i32)
bb.3:
successors: %bb.4(0x80000000)
- %6:gpr(s32) = G_ADD %0, %5
+ %6:gpr(i32) = G_ADD %0, %5
bb.4:
- %7:gpr(s32) = G_PHI %6(s32), %bb.3
- $w0 = COPY %7(s32)
+ %7:gpr(i32) = G_PHI %6(i32), %bb.3
+ $w0 = COPY %7(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
index 7884d9e1b1d72..4ee74f3a952a1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
@@ -393,11 +393,11 @@ body: |
; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMEQv2i64_]]
; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %4:fpr(<2 x s64>) = G_ICMP intpred(eq), %0(<2 x s64>), %1
- %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %4:fpr(<2 x i64>) = G_ICMP intpred(eq), %0(<2 x i64>), %1
+ %3:fpr(<2 x i32>) = G_TRUNC %4(<2 x i64>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -427,11 +427,11 @@ body: |
; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMEQv4i32_]]
; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %4:fpr(<4 x s32>) = G_ICMP intpred(eq), %0(<4 x s32>), %1
- %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %4:fpr(<4 x i32>) = G_ICMP intpred(eq), %0(<4 x i32>), %1
+ %3:fpr(<4 x i16>) = G_TRUNC %4(<4 x i32>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -460,11 +460,11 @@ body: |
; CHECK-NEXT: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMEQv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %4:fpr(<2 x s32>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
- %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %4:fpr(<2 x i32>) = G_ICMP intpred(eq), %0(<2 x i32>), %1
+ %3:fpr(<2 x i32>) = COPY %4(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -508,19 +508,19 @@ body: |
; CHECK-NEXT: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]
; CHECK-NEXT: $d0 = COPY [[CMEQv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %2:fpr(<2 x s32>) = COPY $d0
- %3:fpr(<2 x s32>) = COPY $d1
+ %2:fpr(<2 x i32>) = COPY $d0
+ %3:fpr(<2 x i32>) = COPY $d1
%13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
- %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
- %7:fpr(<2 x s32>) = G_AND %15, %14
+ %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(s32), %13(s32)
+ %15:fpr(<2 x i32>) = COPY %2(<2 x i32>)
+ %7:fpr(<2 x i32>) = G_AND %15, %14
%10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
- %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
- %8:fpr(<2 x s32>) = G_AND %12, %11
- %9:fpr(<2 x s32>) = G_ICMP intpred(eq), %7(<2 x s32>), %8
- %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
- $d0 = COPY %5(<2 x s32>)
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
+ %8:fpr(<2 x i32>) = G_AND %12, %11
+ %9:fpr(<2 x i32>) = G_ICMP intpred(eq), %7(<2 x i32>), %8
+ %5:fpr(<2 x i32>) = COPY %9(<2 x i32>)
+ $d0 = COPY %5(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -550,11 +550,11 @@ body: |
; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMEQv8i16_]]
; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %4:fpr(<8 x s16>) = G_ICMP intpred(eq), %0(<8 x s16>), %1
- %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %4:fpr(<8 x i16>) = G_ICMP intpred(eq), %0(<8 x i16>), %1
+ %3:fpr(<8 x i8>) = G_TRUNC %4(<8 x i16>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -583,11 +583,11 @@ body: |
; CHECK-NEXT: [[CMEQv4i16_:%[0-9]+]]:fpr64 = CMEQv4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMEQv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %4:fpr(<4 x s16>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
- %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %4:fpr(<4 x i16>) = G_ICMP intpred(eq), %0(<4 x i16>), %1
+ %3:fpr(<4 x i16>) = COPY %4(<4 x i16>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -616,11 +616,11 @@ body: |
; CHECK-NEXT: [[CMEQv16i8_:%[0-9]+]]:fpr128 = CMEQv16i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[CMEQv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %4:fpr(<16 x s8>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
- %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
- $q0 = COPY %3(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %4:fpr(<16 x i8>) = G_ICMP intpred(eq), %0(<16 x i8>), %1
+ %3:fpr(<16 x i8>) = COPY %4(<16 x i8>)
+ $q0 = COPY %3(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -649,11 +649,11 @@ body: |
; CHECK-NEXT: [[CMEQv8i8_:%[0-9]+]]:fpr64 = CMEQv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMEQv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %4:fpr(<8 x s8>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
- %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %4:fpr(<8 x i8>) = G_ICMP intpred(eq), %0(<8 x i8>), %1
+ %3:fpr(<8 x i8>) = COPY %4(<8 x i8>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -683,11 +683,11 @@ body: |
; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHIv2i64_]]
; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %4:fpr(<2 x s64>) = G_ICMP intpred(ugt), %0(<2 x s64>), %1
- %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %4:fpr(<2 x i64>) = G_ICMP intpred(ugt), %0(<2 x i64>), %1
+ %3:fpr(<2 x i32>) = G_TRUNC %4(<2 x i64>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -717,11 +717,11 @@ body: |
; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHIv4i32_]]
; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %4:fpr(<4 x s32>) = G_ICMP intpred(ugt), %0(<4 x s32>), %1
- %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %4:fpr(<4 x i32>) = G_ICMP intpred(ugt), %0(<4 x i32>), %1
+ %3:fpr(<4 x i16>) = G_TRUNC %4(<4 x i32>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -750,11 +750,11 @@ body: |
; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %4:fpr(<2 x s32>) = G_ICMP intpred(ugt), %0(<2 x s32>), %1
- %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %4:fpr(<2 x i32>) = G_ICMP intpred(ugt), %0(<2 x i32>), %1
+ %3:fpr(<2 x i32>) = COPY %4(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -798,19 +798,19 @@ body: |
; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]
; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %2:fpr(<2 x s32>) = COPY $d0
- %3:fpr(<2 x s32>) = COPY $d1
+ %2:fpr(<2 x i32>) = COPY $d0
+ %3:fpr(<2 x i32>) = COPY $d1
%13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
- %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
- %7:fpr(<2 x s32>) = G_AND %15, %14
+ %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(s32), %13(s32)
+ %15:fpr(<2 x i32>) = COPY %2(<2 x i32>)
+ %7:fpr(<2 x i32>) = G_AND %15, %14
%10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
- %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
- %8:fpr(<2 x s32>) = G_AND %12, %11
- %9:fpr(<2 x s32>) = G_ICMP intpred(ugt), %7(<2 x s32>), %8
- %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
- $d0 = COPY %5(<2 x s32>)
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
+ %8:fpr(<2 x i32>) = G_AND %12, %11
+ %9:fpr(<2 x i32>) = G_ICMP intpred(ugt), %7(<2 x i32>), %8
+ %5:fpr(<2 x i32>) = COPY %9(<2 x i32>)
+ $d0 = COPY %5(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -840,11 +840,11 @@ body: |
; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHIv8i16_]]
; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %4:fpr(<8 x s16>) = G_ICMP intpred(ugt), %0(<8 x s16>), %1
- %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %4:fpr(<8 x i16>) = G_ICMP intpred(ugt), %0(<8 x i16>), %1
+ %3:fpr(<8 x i8>) = G_TRUNC %4(<8 x i16>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -873,11 +873,11 @@ body: |
; CHECK-NEXT: [[CMHIv4i16_:%[0-9]+]]:fpr64 = CMHIv4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMHIv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %4:fpr(<4 x s16>) = G_ICMP intpred(ugt), %0(<4 x s16>), %1
- %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %4:fpr(<4 x i16>) = G_ICMP intpred(ugt), %0(<4 x i16>), %1
+ %3:fpr(<4 x i16>) = COPY %4(<4 x i16>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -906,11 +906,11 @@ body: |
; CHECK-NEXT: [[CMHIv16i8_:%[0-9]+]]:fpr128 = CMHIv16i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[CMHIv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %4:fpr(<16 x s8>) = G_ICMP intpred(ugt), %0(<16 x s8>), %1
- %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
- $q0 = COPY %3(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %4:fpr(<16 x i8>) = G_ICMP intpred(ugt), %0(<16 x i8>), %1
+ %3:fpr(<16 x i8>) = COPY %4(<16 x i8>)
+ $q0 = COPY %3(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -939,11 +939,11 @@ body: |
; CHECK-NEXT: [[CMHIv8i8_:%[0-9]+]]:fpr64 = CMHIv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMHIv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %4:fpr(<8 x s8>) = G_ICMP intpred(ugt), %0(<8 x s8>), %1
- %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %4:fpr(<8 x i8>) = G_ICMP intpred(ugt), %0(<8 x i8>), %1
+ %3:fpr(<8 x i8>) = COPY %4(<8 x i8>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -973,11 +973,11 @@ body: |
; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHSv2i64_]]
; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %4:fpr(<2 x s64>) = G_ICMP intpred(uge), %0(<2 x s64>), %1
- %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %4:fpr(<2 x i64>) = G_ICMP intpred(uge), %0(<2 x i64>), %1
+ %3:fpr(<2 x i32>) = G_TRUNC %4(<2 x i64>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1007,11 +1007,11 @@ body: |
; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHSv4i32_]]
; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %4:fpr(<4 x s32>) = G_ICMP intpred(uge), %0(<4 x s32>), %1
- %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %4:fpr(<4 x i32>) = G_ICMP intpred(uge), %0(<4 x i32>), %1
+ %3:fpr(<4 x i16>) = G_TRUNC %4(<4 x i32>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -1040,11 +1040,11 @@ body: |
; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %4:fpr(<2 x s32>) = G_ICMP intpred(uge), %0(<2 x s32>), %1
- %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %4:fpr(<2 x i32>) = G_ICMP intpred(uge), %0(<2 x i32>), %1
+ %3:fpr(<2 x i32>) = COPY %4(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1088,19 +1088,19 @@ body: |
; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]
; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %2:fpr(<2 x s32>) = COPY $d0
- %3:fpr(<2 x s32>) = COPY $d1
+ %2:fpr(<2 x i32>) = COPY $d0
+ %3:fpr(<2 x i32>) = COPY $d1
%13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
- %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
- %7:fpr(<2 x s32>) = G_AND %15, %14
+ %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(s32), %13(s32)
+ %15:fpr(<2 x i32>) = COPY %2(<2 x i32>)
+ %7:fpr(<2 x i32>) = G_AND %15, %14
%10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
- %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
- %8:fpr(<2 x s32>) = G_AND %12, %11
- %9:fpr(<2 x s32>) = G_ICMP intpred(uge), %7(<2 x s32>), %8
- %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
- $d0 = COPY %5(<2 x s32>)
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
+ %8:fpr(<2 x i32>) = G_AND %12, %11
+ %9:fpr(<2 x i32>) = G_ICMP intpred(uge), %7(<2 x i32>), %8
+ %5:fpr(<2 x i32>) = COPY %9(<2 x i32>)
+ $d0 = COPY %5(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1130,11 +1130,11 @@ body: |
; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHSv8i16_]]
; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %4:fpr(<8 x s16>) = G_ICMP intpred(uge), %0(<8 x s16>), %1
- %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %4:fpr(<8 x i16>) = G_ICMP intpred(uge), %0(<8 x i16>), %1
+ %3:fpr(<8 x i8>) = G_TRUNC %4(<8 x i16>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -1163,11 +1163,11 @@ body: |
; CHECK-NEXT: [[CMHSv4i16_:%[0-9]+]]:fpr64 = CMHSv4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMHSv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %4:fpr(<4 x s16>) = G_ICMP intpred(uge), %0(<4 x s16>), %1
- %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %4:fpr(<4 x i16>) = G_ICMP intpred(uge), %0(<4 x i16>), %1
+ %3:fpr(<4 x i16>) = COPY %4(<4 x i16>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -1196,11 +1196,11 @@ body: |
; CHECK-NEXT: [[CMHSv16i8_:%[0-9]+]]:fpr128 = CMHSv16i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[CMHSv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %4:fpr(<16 x s8>) = G_ICMP intpred(uge), %0(<16 x s8>), %1
- %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
- $q0 = COPY %3(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %4:fpr(<16 x i8>) = G_ICMP intpred(uge), %0(<16 x i8>), %1
+ %3:fpr(<16 x i8>) = COPY %4(<16 x i8>)
+ $q0 = COPY %3(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -1229,11 +1229,11 @@ body: |
; CHECK-NEXT: [[CMHSv8i8_:%[0-9]+]]:fpr64 = CMHSv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMHSv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %4:fpr(<8 x s8>) = G_ICMP intpred(uge), %0(<8 x s8>), %1
- %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %4:fpr(<8 x i8>) = G_ICMP intpred(uge), %0(<8 x i8>), %1
+ %3:fpr(<8 x i8>) = COPY %4(<8 x i8>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -1263,11 +1263,11 @@ body: |
; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHIv2i64_]]
; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %4:fpr(<2 x s64>) = G_ICMP intpred(ult), %0(<2 x s64>), %1
- %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %4:fpr(<2 x i64>) = G_ICMP intpred(ult), %0(<2 x i64>), %1
+ %3:fpr(<2 x i32>) = G_TRUNC %4(<2 x i64>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1297,11 +1297,11 @@ body: |
; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHIv4i32_]]
; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %4:fpr(<4 x s32>) = G_ICMP intpred(ult), %0(<4 x s32>), %1
- %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %4:fpr(<4 x i32>) = G_ICMP intpred(ult), %0(<4 x i32>), %1
+ %3:fpr(<4 x i16>) = G_TRUNC %4(<4 x i32>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -1330,11 +1330,11 @@ body: |
; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %4:fpr(<2 x s32>) = G_ICMP intpred(ult), %0(<2 x s32>), %1
- %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %4:fpr(<2 x i32>) = G_ICMP intpred(ult), %0(<2 x i32>), %1
+ %3:fpr(<2 x i32>) = COPY %4(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1378,19 +1378,19 @@ body: |
; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[ANDv8i8_1]], [[ANDv8i8_]]
; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %2:fpr(<2 x s32>) = COPY $d0
- %3:fpr(<2 x s32>) = COPY $d1
+ %2:fpr(<2 x i32>) = COPY $d0
+ %3:fpr(<2 x i32>) = COPY $d1
%13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
- %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
- %7:fpr(<2 x s32>) = G_AND %15, %14
+ %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(s32), %13(s32)
+ %15:fpr(<2 x i32>) = COPY %2(<2 x i32>)
+ %7:fpr(<2 x i32>) = G_AND %15, %14
%10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
- %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
- %8:fpr(<2 x s32>) = G_AND %12, %11
- %9:fpr(<2 x s32>) = G_ICMP intpred(ult), %7(<2 x s32>), %8
- %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
- $d0 = COPY %5(<2 x s32>)
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
+ %8:fpr(<2 x i32>) = G_AND %12, %11
+ %9:fpr(<2 x i32>) = G_ICMP intpred(ult), %7(<2 x i32>), %8
+ %5:fpr(<2 x i32>) = COPY %9(<2 x i32>)
+ $d0 = COPY %5(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1420,11 +1420,11 @@ body: |
; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHIv8i16_]]
; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %4:fpr(<8 x s16>) = G_ICMP intpred(ult), %0(<8 x s16>), %1
- %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %4:fpr(<8 x i16>) = G_ICMP intpred(ult), %0(<8 x i16>), %1
+ %3:fpr(<8 x i8>) = G_TRUNC %4(<8 x i16>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -1453,11 +1453,11 @@ body: |
; CHECK-NEXT: [[CMHIv4i16_:%[0-9]+]]:fpr64 = CMHIv4i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMHIv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %4:fpr(<4 x s16>) = G_ICMP intpred(ult), %0(<4 x s16>), %1
- %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %4:fpr(<4 x i16>) = G_ICMP intpred(ult), %0(<4 x i16>), %1
+ %3:fpr(<4 x i16>) = COPY %4(<4 x i16>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -1486,11 +1486,11 @@ body: |
; CHECK-NEXT: [[CMHIv16i8_:%[0-9]+]]:fpr128 = CMHIv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $q0 = COPY [[CMHIv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %4:fpr(<16 x s8>) = G_ICMP intpred(ult), %0(<16 x s8>), %1
- %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
- $q0 = COPY %3(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %4:fpr(<16 x i8>) = G_ICMP intpred(ult), %0(<16 x i8>), %1
+ %3:fpr(<16 x i8>) = COPY %4(<16 x i8>)
+ $q0 = COPY %3(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -1519,11 +1519,11 @@ body: |
; CHECK-NEXT: [[CMHIv8i8_:%[0-9]+]]:fpr64 = CMHIv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMHIv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %4:fpr(<8 x s8>) = G_ICMP intpred(ult), %0(<8 x s8>), %1
- %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %4:fpr(<8 x i8>) = G_ICMP intpred(ult), %0(<8 x i8>), %1
+ %3:fpr(<8 x i8>) = COPY %4(<8 x i8>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -1553,11 +1553,11 @@ body: |
; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHSv2i64_]]
; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %4:fpr(<2 x s64>) = G_ICMP intpred(ule), %0(<2 x s64>), %1
- %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %4:fpr(<2 x i64>) = G_ICMP intpred(ule), %0(<2 x i64>), %1
+ %3:fpr(<2 x i32>) = G_TRUNC %4(<2 x i64>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1587,11 +1587,11 @@ body: |
; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHSv4i32_]]
; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %4:fpr(<4 x s32>) = G_ICMP intpred(ule), %0(<4 x s32>), %1
- %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %4:fpr(<4 x i32>) = G_ICMP intpred(ule), %0(<4 x i32>), %1
+ %3:fpr(<4 x i16>) = G_TRUNC %4(<4 x i32>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -1620,11 +1620,11 @@ body: |
; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %4:fpr(<2 x s32>) = G_ICMP intpred(ule), %0(<2 x s32>), %1
- %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %4:fpr(<2 x i32>) = G_ICMP intpred(ule), %0(<2 x i32>), %1
+ %3:fpr(<2 x i32>) = COPY %4(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1668,19 +1668,19 @@ body: |
; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[ANDv8i8_1]], [[ANDv8i8_]]
; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %2:fpr(<2 x s32>) = COPY $d0
- %3:fpr(<2 x s32>) = COPY $d1
+ %2:fpr(<2 x i32>) = COPY $d0
+ %3:fpr(<2 x i32>) = COPY $d1
%13:gpr(s32) = G_CONSTANT i32 65535
- %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
- %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
- %7:fpr(<2 x s32>) = G_AND %15, %14
+ %14:fpr(<2 x i32>) = G_BUILD_VECTOR %13(s32), %13(s32)
+ %15:fpr(<2 x i32>) = COPY %2(<2 x i32>)
+ %7:fpr(<2 x i32>) = G_AND %15, %14
%10:gpr(s32) = G_CONSTANT i32 65535
- %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
- %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
- %8:fpr(<2 x s32>) = G_AND %12, %11
- %9:fpr(<2 x s32>) = G_ICMP intpred(ule), %7(<2 x s32>), %8
- %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
- $d0 = COPY %5(<2 x s32>)
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
+ %8:fpr(<2 x i32>) = G_AND %12, %11
+ %9:fpr(<2 x i32>) = G_ICMP intpred(ule), %7(<2 x i32>), %8
+ %5:fpr(<2 x i32>) = COPY %9(<2 x i32>)
+ $d0 = COPY %5(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1710,11 +1710,11 @@ body: |
; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHSv8i16_]]
; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %4:fpr(<8 x s16>) = G_ICMP intpred(ule), %0(<8 x s16>), %1
- %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %4:fpr(<8 x i16>) = G_ICMP intpred(ule), %0(<8 x i16>), %1
+ %3:fpr(<8 x i8>) = G_TRUNC %4(<8 x i16>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -1743,11 +1743,11 @@ body: |
; CHECK-NEXT: [[CMHSv4i16_:%[0-9]+]]:fpr64 = CMHSv4i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMHSv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %4:fpr(<4 x s16>) = G_ICMP intpred(ule), %0(<4 x s16>), %1
- %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %4:fpr(<4 x i16>) = G_ICMP intpred(ule), %0(<4 x i16>), %1
+ %3:fpr(<4 x i16>) = COPY %4(<4 x i16>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -1776,11 +1776,11 @@ body: |
; CHECK-NEXT: [[CMHSv16i8_:%[0-9]+]]:fpr128 = CMHSv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $q0 = COPY [[CMHSv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %4:fpr(<16 x s8>) = G_ICMP intpred(ule), %0(<16 x s8>), %1
- %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
- $q0 = COPY %3(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %4:fpr(<16 x i8>) = G_ICMP intpred(ule), %0(<16 x i8>), %1
+ %3:fpr(<16 x i8>) = COPY %4(<16 x i8>)
+ $q0 = COPY %3(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -1809,11 +1809,11 @@ body: |
; CHECK-NEXT: [[CMHSv8i8_:%[0-9]+]]:fpr64 = CMHSv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMHSv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %4:fpr(<8 x s8>) = G_ICMP intpred(ule), %0(<8 x s8>), %1
- %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %4:fpr(<8 x i8>) = G_ICMP intpred(ule), %0(<8 x i8>), %1
+ %3:fpr(<8 x i8>) = COPY %4(<8 x i8>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -1843,11 +1843,11 @@ body: |
; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGTv2i64_]]
; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %4:fpr(<2 x s64>) = G_ICMP intpred(sgt), %0(<2 x s64>), %1
- %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %4:fpr(<2 x i64>) = G_ICMP intpred(sgt), %0(<2 x i64>), %1
+ %3:fpr(<2 x i32>) = G_TRUNC %4(<2 x i64>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1877,11 +1877,11 @@ body: |
; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGTv4i32_]]
; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %4:fpr(<4 x s32>) = G_ICMP intpred(sgt), %0(<4 x s32>), %1
- %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %4:fpr(<4 x i32>) = G_ICMP intpred(sgt), %0(<4 x i32>), %1
+ %3:fpr(<4 x i16>) = G_TRUNC %4(<4 x i32>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -1910,11 +1910,11 @@ body: |
; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %4:fpr(<2 x s32>) = G_ICMP intpred(sgt), %0(<2 x s32>), %1
- %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %4:fpr(<2 x i32>) = G_ICMP intpred(sgt), %0(<2 x i32>), %1
+ %3:fpr(<2 x i32>) = COPY %4(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -1964,21 +1964,21 @@ body: |
; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]]
; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %2:fpr(<2 x s32>) = COPY $d0
- %3:fpr(<2 x s32>) = COPY $d1
+ %2:fpr(<2 x i32>) = COPY $d0
+ %3:fpr(<2 x i32>) = COPY $d1
%14:gpr(s32) = G_CONSTANT i32 16
- %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)
- %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)
- %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)
- %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)
+ %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(s32), %14(s32)
+ %16:fpr(<2 x i32>) = COPY %2(<2 x i32>)
+ %17:fpr(<2 x i32>) = G_SHL %16, %15(<2 x i32>)
+ %7:fpr(<2 x i32>) = G_ASHR %17, %15(<2 x i32>)
%10:gpr(s32) = G_CONSTANT i32 16
- %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
- %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
- %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)
- %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)
- %9:fpr(<2 x s32>) = G_ICMP intpred(sgt), %7(<2 x s32>), %8
- %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
- $d0 = COPY %5(<2 x s32>)
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
+ %13:fpr(<2 x i32>) = G_SHL %12, %11(<2 x i32>)
+ %8:fpr(<2 x i32>) = G_ASHR %13, %11(<2 x i32>)
+ %9:fpr(<2 x i32>) = G_ICMP intpred(sgt), %7(<2 x i32>), %8
+ %5:fpr(<2 x i32>) = COPY %9(<2 x i32>)
+ $d0 = COPY %5(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -2008,11 +2008,11 @@ body: |
; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGTv8i16_]]
; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %4:fpr(<8 x s16>) = G_ICMP intpred(sgt), %0(<8 x s16>), %1
- %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %4:fpr(<8 x i16>) = G_ICMP intpred(sgt), %0(<8 x i16>), %1
+ %3:fpr(<8 x i8>) = G_TRUNC %4(<8 x i16>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -2041,11 +2041,11 @@ body: |
; CHECK-NEXT: [[CMGTv4i16_:%[0-9]+]]:fpr64 = CMGTv4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMGTv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %4:fpr(<4 x s16>) = G_ICMP intpred(sgt), %0(<4 x s16>), %1
- %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %4:fpr(<4 x i16>) = G_ICMP intpred(sgt), %0(<4 x i16>), %1
+ %3:fpr(<4 x i16>) = COPY %4(<4 x i16>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -2074,11 +2074,11 @@ body: |
; CHECK-NEXT: [[CMGTv16i8_:%[0-9]+]]:fpr128 = CMGTv16i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[CMGTv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %4:fpr(<16 x s8>) = G_ICMP intpred(sgt), %0(<16 x s8>), %1
- %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
- $q0 = COPY %3(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %4:fpr(<16 x i8>) = G_ICMP intpred(sgt), %0(<16 x i8>), %1
+ %3:fpr(<16 x i8>) = COPY %4(<16 x i8>)
+ $q0 = COPY %3(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -2107,11 +2107,11 @@ body: |
; CHECK-NEXT: [[CMGTv8i8_:%[0-9]+]]:fpr64 = CMGTv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMGTv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %4:fpr(<8 x s8>) = G_ICMP intpred(sgt), %0(<8 x s8>), %1
- %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %4:fpr(<8 x i8>) = G_ICMP intpred(sgt), %0(<8 x i8>), %1
+ %3:fpr(<8 x i8>) = COPY %4(<8 x i8>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -2141,11 +2141,11 @@ body: |
; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGEv2i64_]]
; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %4:fpr(<2 x s64>) = G_ICMP intpred(sge), %0(<2 x s64>), %1
- %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %4:fpr(<2 x i64>) = G_ICMP intpred(sge), %0(<2 x i64>), %1
+ %3:fpr(<2 x i32>) = G_TRUNC %4(<2 x i64>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -2175,11 +2175,11 @@ body: |
; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGEv4i32_]]
; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %4:fpr(<4 x s32>) = G_ICMP intpred(sge), %0(<4 x s32>), %1
- %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %4:fpr(<4 x i32>) = G_ICMP intpred(sge), %0(<4 x i32>), %1
+ %3:fpr(<4 x i16>) = G_TRUNC %4(<4 x i32>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -2208,11 +2208,11 @@ body: |
; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %4:fpr(<2 x s32>) = G_ICMP intpred(sge), %0(<2 x s32>), %1
- %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %4:fpr(<2 x i32>) = G_ICMP intpred(sge), %0(<2 x i32>), %1
+ %3:fpr(<2 x i32>) = COPY %4(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -2262,21 +2262,21 @@ body: |
; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]]
; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %2:fpr(<2 x s32>) = COPY $d0
- %3:fpr(<2 x s32>) = COPY $d1
+ %2:fpr(<2 x i32>) = COPY $d0
+ %3:fpr(<2 x i32>) = COPY $d1
%14:gpr(s32) = G_CONSTANT i32 16
- %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)
- %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)
- %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)
- %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)
+ %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(s32), %14(s32)
+ %16:fpr(<2 x i32>) = COPY %2(<2 x i32>)
+ %17:fpr(<2 x i32>) = G_SHL %16, %15(<2 x i32>)
+ %7:fpr(<2 x i32>) = G_ASHR %17, %15(<2 x i32>)
%10:gpr(s32) = G_CONSTANT i32 16
- %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
- %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
- %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)
- %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)
- %9:fpr(<2 x s32>) = G_ICMP intpred(sge), %7(<2 x s32>), %8
- %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
- $d0 = COPY %5(<2 x s32>)
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
+ %13:fpr(<2 x i32>) = G_SHL %12, %11(<2 x i32>)
+ %8:fpr(<2 x i32>) = G_ASHR %13, %11(<2 x i32>)
+ %9:fpr(<2 x i32>) = G_ICMP intpred(sge), %7(<2 x i32>), %8
+ %5:fpr(<2 x i32>) = COPY %9(<2 x i32>)
+ $d0 = COPY %5(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -2306,11 +2306,11 @@ body: |
; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGEv8i16_]]
; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %4:fpr(<8 x s16>) = G_ICMP intpred(sge), %0(<8 x s16>), %1
- %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %4:fpr(<8 x i16>) = G_ICMP intpred(sge), %0(<8 x i16>), %1
+ %3:fpr(<8 x i8>) = G_TRUNC %4(<8 x i16>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -2339,11 +2339,11 @@ body: |
; CHECK-NEXT: [[CMGEv4i16_:%[0-9]+]]:fpr64 = CMGEv4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMGEv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %4:fpr(<4 x s16>) = G_ICMP intpred(sge), %0(<4 x s16>), %1
- %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %4:fpr(<4 x i16>) = G_ICMP intpred(sge), %0(<4 x i16>), %1
+ %3:fpr(<4 x i16>) = COPY %4(<4 x i16>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -2372,11 +2372,11 @@ body: |
; CHECK-NEXT: [[CMGEv16i8_:%[0-9]+]]:fpr128 = CMGEv16i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[CMGEv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %4:fpr(<16 x s8>) = G_ICMP intpred(sge), %0(<16 x s8>), %1
- %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
- $q0 = COPY %3(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %4:fpr(<16 x i8>) = G_ICMP intpred(sge), %0(<16 x i8>), %1
+ %3:fpr(<16 x i8>) = COPY %4(<16 x i8>)
+ $q0 = COPY %3(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -2405,11 +2405,11 @@ body: |
; CHECK-NEXT: [[CMGEv8i8_:%[0-9]+]]:fpr64 = CMGEv8i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[CMGEv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %4:fpr(<8 x s8>) = G_ICMP intpred(sge), %0(<8 x s8>), %1
- %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %4:fpr(<8 x i8>) = G_ICMP intpred(sge), %0(<8 x i8>), %1
+ %3:fpr(<8 x i8>) = COPY %4(<8 x i8>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -2439,11 +2439,11 @@ body: |
; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGTv2i64_]]
; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %4:fpr(<2 x s64>) = G_ICMP intpred(slt), %0(<2 x s64>), %1
- %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %4:fpr(<2 x i64>) = G_ICMP intpred(slt), %0(<2 x i64>), %1
+ %3:fpr(<2 x i32>) = G_TRUNC %4(<2 x i64>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -2473,11 +2473,11 @@ body: |
; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGTv4i32_]]
; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %4:fpr(<4 x s32>) = G_ICMP intpred(slt), %0(<4 x s32>), %1
- %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %4:fpr(<4 x i32>) = G_ICMP intpred(slt), %0(<4 x i32>), %1
+ %3:fpr(<4 x i16>) = G_TRUNC %4(<4 x i32>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -2506,11 +2506,11 @@ body: |
; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %4:fpr(<2 x s32>) = G_ICMP intpred(slt), %0(<2 x s32>), %1
- %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %4:fpr(<2 x i32>) = G_ICMP intpred(slt), %0(<2 x i32>), %1
+ %3:fpr(<2 x i32>) = COPY %4(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -2560,21 +2560,21 @@ body: |
; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]]
; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %2:fpr(<2 x s32>) = COPY $d0
- %3:fpr(<2 x s32>) = COPY $d1
+ %2:fpr(<2 x i32>) = COPY $d0
+ %3:fpr(<2 x i32>) = COPY $d1
%14:gpr(s32) = G_CONSTANT i32 16
- %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)
- %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)
- %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)
- %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)
+ %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(s32), %14(s32)
+ %16:fpr(<2 x i32>) = COPY %2(<2 x i32>)
+ %17:fpr(<2 x i32>) = G_SHL %16, %15(<2 x i32>)
+ %7:fpr(<2 x i32>) = G_ASHR %17, %15(<2 x i32>)
%10:gpr(s32) = G_CONSTANT i32 16
- %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
- %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
- %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)
- %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)
- %9:fpr(<2 x s32>) = G_ICMP intpred(slt), %7(<2 x s32>), %8
- %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
- $d0 = COPY %5(<2 x s32>)
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
+ %13:fpr(<2 x i32>) = G_SHL %12, %11(<2 x i32>)
+ %8:fpr(<2 x i32>) = G_ASHR %13, %11(<2 x i32>)
+ %9:fpr(<2 x i32>) = G_ICMP intpred(slt), %7(<2 x i32>), %8
+ %5:fpr(<2 x i32>) = COPY %9(<2 x i32>)
+ $d0 = COPY %5(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -2604,11 +2604,11 @@ body: |
; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGTv8i16_]]
; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %4:fpr(<8 x s16>) = G_ICMP intpred(slt), %0(<8 x s16>), %1
- %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %4:fpr(<8 x i16>) = G_ICMP intpred(slt), %0(<8 x i16>), %1
+ %3:fpr(<8 x i8>) = G_TRUNC %4(<8 x i16>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -2637,11 +2637,11 @@ body: |
; CHECK-NEXT: [[CMGTv4i16_:%[0-9]+]]:fpr64 = CMGTv4i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMGTv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %4:fpr(<4 x s16>) = G_ICMP intpred(slt), %0(<4 x s16>), %1
- %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %4:fpr(<4 x i16>) = G_ICMP intpred(slt), %0(<4 x i16>), %1
+ %3:fpr(<4 x i16>) = COPY %4(<4 x i16>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -2670,11 +2670,11 @@ body: |
; CHECK-NEXT: [[CMGTv16i8_:%[0-9]+]]:fpr128 = CMGTv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $q0 = COPY [[CMGTv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %4:fpr(<16 x s8>) = G_ICMP intpred(slt), %0(<16 x s8>), %1
- %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
- $q0 = COPY %3(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %4:fpr(<16 x i8>) = G_ICMP intpred(slt), %0(<16 x i8>), %1
+ %3:fpr(<16 x i8>) = COPY %4(<16 x i8>)
+ $q0 = COPY %3(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -2703,11 +2703,11 @@ body: |
; CHECK-NEXT: [[CMGTv8i8_:%[0-9]+]]:fpr64 = CMGTv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMGTv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %4:fpr(<8 x s8>) = G_ICMP intpred(slt), %0(<8 x s8>), %1
- %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %4:fpr(<8 x i8>) = G_ICMP intpred(slt), %0(<8 x i8>), %1
+ %3:fpr(<8 x i8>) = COPY %4(<8 x i8>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -2737,11 +2737,11 @@ body: |
; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGEv2i64_]]
; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %4:fpr(<2 x s64>) = G_ICMP intpred(sle), %0(<2 x s64>), %1
- %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %4:fpr(<2 x i64>) = G_ICMP intpred(sle), %0(<2 x i64>), %1
+ %3:fpr(<2 x i32>) = G_TRUNC %4(<2 x i64>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -2771,11 +2771,11 @@ body: |
; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGEv4i32_]]
; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %4:fpr(<4 x s32>) = G_ICMP intpred(sle), %0(<4 x s32>), %1
- %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %4:fpr(<4 x i32>) = G_ICMP intpred(sle), %0(<4 x i32>), %1
+ %3:fpr(<4 x i16>) = G_TRUNC %4(<4 x i32>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -2804,11 +2804,11 @@ body: |
; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %4:fpr(<2 x s32>) = G_ICMP intpred(sle), %0(<2 x s32>), %1
- %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %4:fpr(<2 x i32>) = G_ICMP intpred(sle), %0(<2 x i32>), %1
+ %3:fpr(<2 x i32>) = COPY %4(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -2858,21 +2858,21 @@ body: |
; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]]
; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %2:fpr(<2 x s32>) = COPY $d0
- %3:fpr(<2 x s32>) = COPY $d1
+ %2:fpr(<2 x i32>) = COPY $d0
+ %3:fpr(<2 x i32>) = COPY $d1
%14:gpr(s32) = G_CONSTANT i32 16
- %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)
- %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)
- %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)
- %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)
+ %15:fpr(<2 x i32>) = G_BUILD_VECTOR %14(s32), %14(s32)
+ %16:fpr(<2 x i32>) = COPY %2(<2 x i32>)
+ %17:fpr(<2 x i32>) = G_SHL %16, %15(<2 x i32>)
+ %7:fpr(<2 x i32>) = G_ASHR %17, %15(<2 x i32>)
%10:gpr(s32) = G_CONSTANT i32 16
- %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
- %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
- %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)
- %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)
- %9:fpr(<2 x s32>) = G_ICMP intpred(sle), %7(<2 x s32>), %8
- %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
- $d0 = COPY %5(<2 x s32>)
+ %11:fpr(<2 x i32>) = G_BUILD_VECTOR %10(s32), %10(s32)
+ %12:fpr(<2 x i32>) = COPY %3(<2 x i32>)
+ %13:fpr(<2 x i32>) = G_SHL %12, %11(<2 x i32>)
+ %8:fpr(<2 x i32>) = G_ASHR %13, %11(<2 x i32>)
+ %9:fpr(<2 x i32>) = G_ICMP intpred(sle), %7(<2 x i32>), %8
+ %5:fpr(<2 x i32>) = COPY %9(<2 x i32>)
+ $d0 = COPY %5(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -2902,11 +2902,11 @@ body: |
; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGEv8i16_]]
; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %4:fpr(<8 x s16>) = G_ICMP intpred(sle), %0(<8 x s16>), %1
- %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %4:fpr(<8 x i16>) = G_ICMP intpred(sle), %0(<8 x i16>), %1
+ %3:fpr(<8 x i8>) = G_TRUNC %4(<8 x i16>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
@@ -2935,11 +2935,11 @@ body: |
; CHECK-NEXT: [[CMGEv4i16_:%[0-9]+]]:fpr64 = CMGEv4i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMGEv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %4:fpr(<4 x s16>) = G_ICMP intpred(sle), %0(<4 x s16>), %1
- %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
- $d0 = COPY %3(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %4:fpr(<4 x i16>) = G_ICMP intpred(sle), %0(<4 x i16>), %1
+ %3:fpr(<4 x i16>) = COPY %4(<4 x i16>)
+ $d0 = COPY %3(<4 x i16>)
RET_ReallyLR implicit $d0
...
@@ -2968,11 +2968,11 @@ body: |
; CHECK-NEXT: [[CMGEv16i8_:%[0-9]+]]:fpr128 = CMGEv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $q0 = COPY [[CMGEv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %4:fpr(<16 x s8>) = G_ICMP intpred(sle), %0(<16 x s8>), %1
- %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
- $q0 = COPY %3(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %4:fpr(<16 x i8>) = G_ICMP intpred(sle), %0(<16 x i8>), %1
+ %3:fpr(<16 x i8>) = COPY %4(<16 x i8>)
+ $q0 = COPY %3(<16 x i8>)
RET_ReallyLR implicit $q0
...
@@ -3001,11 +3001,11 @@ body: |
; CHECK-NEXT: [[CMGEv8i8_:%[0-9]+]]:fpr64 = CMGEv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[CMGEv8i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s8>) = COPY $d1
- %4:fpr(<8 x s8>) = G_ICMP intpred(sle), %0(<8 x s8>), %1
- %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
- $d0 = COPY %3(<8 x s8>)
+ %0:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i8>) = COPY $d1
+ %4:fpr(<8 x i8>) = G_ICMP intpred(sle), %0(<8 x i8>), %1
+ %3:fpr(<8 x i8>) = COPY %4(<8 x i8>)
+ $d0 = COPY %3(<8 x i8>)
RET_ReallyLR implicit $d0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
index 9fa63268afa82..605ab99094719 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
@@ -23,10 +23,10 @@ body: |
; CHECK-NEXT: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[USHLv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)
- $d0 = COPY %2(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %2:fpr(<2 x i32>) = G_SHL %0, %1(<2 x i32>)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -57,11 +57,11 @@ body: |
; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 24
; CHECK-NEXT: $d0 = COPY [[SHLv2i32_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
+ %0:fpr(<2 x i32>) = COPY $d0
%2:gpr(s32) = G_CONSTANT i32 24
- %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32)
- %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %1:fpr(<2 x i32>) = G_BUILD_VECTOR %2(s32), %2(s32)
+ %3:fpr(<2 x i32>) = G_SHL %0, %1(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -93,11 +93,11 @@ body: |
; CHECK-NEXT: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[MOVIv2i32_]]
; CHECK-NEXT: $d0 = COPY [[USHLv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
+ %0:fpr(<2 x i32>) = COPY $d0
%2:gpr(s32) = G_CONSTANT i32 40
- %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32)
- %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %1:fpr(<2 x i32>) = G_BUILD_VECTOR %2(s32), %2(s32)
+ %3:fpr(<2 x i32>) = G_SHL %0, %1(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -124,10 +124,10 @@ body: |
; CHECK-NEXT: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[USHLv4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>)
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_SHL %0, %1(<4 x i32>)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -158,11 +158,11 @@ body: |
; CHECK-NEXT: [[SHLv4i32_shift:%[0-9]+]]:fpr128 = SHLv4i32_shift [[COPY]], 24
; CHECK-NEXT: $q0 = COPY [[SHLv4i32_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
+ %0:fpr(<4 x i32>) = COPY $q0
%2:gpr(s32) = G_CONSTANT i32 24
- %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)
- %3:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>)
- $q0 = COPY %3(<4 x s32>)
+ %1:fpr(<4 x i32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)
+ %3:fpr(<4 x i32>) = G_SHL %0, %1(<4 x i32>)
+ $q0 = COPY %3(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -189,10 +189,10 @@ body: |
; CHECK-NEXT: [[USHLv2i64_:%[0-9]+]]:fpr128 = USHLv2i64 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[USHLv2i64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>)
- $q0 = COPY %2(<2 x s64>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %2:fpr(<2 x i64>) = G_SHL %0, %1(<2 x i64>)
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -223,11 +223,11 @@ body: |
; CHECK-NEXT: [[SHLv2i64_shift:%[0-9]+]]:fpr128 = SHLv2i64_shift [[COPY]], 24
; CHECK-NEXT: $q0 = COPY [[SHLv2i64_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
+ %0:fpr(<2 x i64>) = COPY $q0
%2:gpr(s64) = G_CONSTANT i64 24
- %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64)
- %3:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>)
- $q0 = COPY %3(<2 x s64>)
+ %1:fpr(<2 x i64>) = G_BUILD_VECTOR %2(s64), %2(s64)
+ %3:fpr(<2 x i64>) = G_SHL %0, %1(<2 x i64>)
+ $q0 = COPY %3(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -260,11 +260,11 @@ body: |
; CHECK-NEXT: [[USHLv2i64_:%[0-9]+]]:fpr128 = USHLv2i64 [[COPY]], [[LDRQui]]
; CHECK-NEXT: $q0 = COPY [[USHLv2i64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
+ %0:fpr(<2 x i64>) = COPY $q0
%2:gpr(s64) = G_CONSTANT i64 70
- %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64)
- %3:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>)
- $q0 = COPY %3(<2 x s64>)
+ %1:fpr(<2 x i64>) = G_BUILD_VECTOR %2(s64), %2(s64)
+ %3:fpr(<2 x i64>) = G_SHL %0, %1(<2 x i64>)
+ $q0 = COPY %3(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -292,10 +292,10 @@ body: |
; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[COPY]], [[NEGv2i32_]]
; CHECK-NEXT: $d0 = COPY [[SSHLv2i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s32>) = COPY $d1
- %2:fpr(<2 x s32>) = G_ASHR %0, %1(<2 x s32>)
- $d0 = COPY %2(<2 x s32>)
+ %0:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i32>) = COPY $d1
+ %2:fpr(<2 x i32>) = G_ASHR %0, %1(<2 x i32>)
+ $d0 = COPY %2(<2 x i32>)
RET_ReallyLR implicit $d0
...
@@ -323,10 +323,10 @@ body: |
; CHECK-NEXT: [[SSHLv4i32_:%[0-9]+]]:fpr128 = SSHLv4i32 [[COPY]], [[NEGv4i32_]]
; CHECK-NEXT: $q0 = COPY [[SSHLv4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_ASHR %0, %1(<4 x s32>)
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_ASHR %0, %1(<4 x i32>)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -354,10 +354,10 @@ body: |
; CHECK-NEXT: [[SSHLv2i64_:%[0-9]+]]:fpr128 = SSHLv2i64 [[COPY]], [[NEGv2i64_]]
; CHECK-NEXT: $q0 = COPY [[SSHLv2i64_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = COPY $q1
- %2:fpr(<2 x s64>) = G_ASHR %0, %1(<2 x s64>)
- $q0 = COPY %2(<2 x s64>)
+ %0:fpr(<2 x i64>) = COPY $q0
+ %1:fpr(<2 x i64>) = COPY $q1
+ %2:fpr(<2 x i64>) = G_ASHR %0, %1(<2 x i64>)
+ $q0 = COPY %2(<2 x i64>)
RET_ReallyLR implicit $q0
...
@@ -377,10 +377,10 @@ body: |
; CHECK-NEXT: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $d0 = COPY [[USHLv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = G_SHL %0, %1(<4 x s16>)
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = G_SHL %0, %1(<4 x i16>)
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -400,10 +400,10 @@ body: |
; CHECK-NEXT: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[NEGv4i16_]]
; CHECK-NEXT: $d0 = COPY [[USHLv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = G_LSHR %0, %1(<4 x s16>)
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = G_LSHR %0, %1(<4 x i16>)
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -430,10 +430,10 @@ body: |
; CHECK-NEXT: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[NEGv4i32_]]
; CHECK-NEXT: $q0 = COPY [[USHLv4i32_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x s32>) = COPY $q0
- %1:fpr(<4 x s32>) = COPY $q1
- %2:fpr(<4 x s32>) = G_LSHR %0, %1(<4 x s32>)
- $q0 = COPY %2(<4 x s32>)
+ %0:fpr(<4 x i32>) = COPY $q0
+ %1:fpr(<4 x i32>) = COPY $q1
+ %2:fpr(<4 x i32>) = G_LSHR %0, %1(<4 x i32>)
+ $q0 = COPY %2(<4 x i32>)
RET_ReallyLR implicit $q0
...
@@ -454,10 +454,10 @@ body: |
; CHECK-NEXT: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY]], [[NEGv8i16_]]
; CHECK-NEXT: $q0 = COPY [[USHLv8i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %2:fpr(<8 x s16>) = G_LSHR %0, %1(<8 x s16>)
- $q0 = COPY %2(<8 x s16>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %2:fpr(<8 x i16>) = G_LSHR %0, %1(<8 x i16>)
+ $q0 = COPY %2(<8 x i16>)
RET_ReallyLR implicit $q0
...
---
@@ -477,10 +477,10 @@ body: |
; CHECK-NEXT: [[SSHLv4i16_:%[0-9]+]]:fpr64 = SSHLv4i16 [[COPY]], [[NEGv4i16_]]
; CHECK-NEXT: $d0 = COPY [[SSHLv4i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = G_ASHR %0, %1(<4 x s16>)
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = G_ASHR %0, %1(<4 x i16>)
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -498,9 +498,9 @@ body: |
; CHECK-NEXT: [[SSHRv4i16_shift:%[0-9]+]]:fpr64 = SSHRv4i16_shift [[COPY]], 5
; CHECK-NEXT: $d0 = COPY [[SSHRv4i16_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %2:fpr(<4 x s16>) = G_VASHR %0, 5
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %2:fpr(<4 x i16>) = G_VASHR %0, 5
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -518,9 +518,9 @@ body: |
; CHECK-NEXT: [[USHRv4i16_shift:%[0-9]+]]:fpr64 = USHRv4i16_shift [[COPY]], 5
; CHECK-NEXT: $d0 = COPY [[USHRv4i16_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<4 x s16>) = COPY $d0
- %2:fpr(<4 x s16>) = G_VLSHR %0, 5
- $d0 = COPY %2(<4 x s16>)
+ %0:fpr(<4 x i16>) = COPY $d0
+ %2:fpr(<4 x i16>) = G_VLSHR %0, 5
+ $d0 = COPY %2(<4 x i16>)
RET_ReallyLR implicit $d0
...
---
@@ -539,10 +539,10 @@ body: |
; CHECK-NEXT: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[USHLv8i16_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x s16>) = COPY $q0
- %1:fpr(<8 x s16>) = COPY $q1
- %2:fpr(<8 x s16>) = G_SHL %0, %1(<8 x s16>)
- $q0 = COPY %2(<8 x s16>)
+ %0:fpr(<8 x i16>) = COPY $q0
+ %1:fpr(<8 x i16>) = COPY $q1
+ %2:fpr(<8 x i16>) = G_SHL %0, %1(<8 x i16>)
+ $q0 = COPY %2(<8 x i16>)
RET_ReallyLR implicit $q0
...
---
@@ -561,10 +561,10 @@ body: |
; CHECK-NEXT: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY]], [[COPY1]]
; CHECK-NEXT: $q0 = COPY [[USHLv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %2:fpr(<16 x s8>) = G_SHL %0, %1(<16 x s8>)
- $q0 = COPY %2(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %2:fpr(<16 x i8>) = G_SHL %0, %1(<16 x i8>)
+ $q0 = COPY %2(<16 x i8>)
RET_ReallyLR implicit $q0
...
---
@@ -584,10 +584,10 @@ body: |
; CHECK-NEXT: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY]], [[NEGv16i8_]]
; CHECK-NEXT: $q0 = COPY [[USHLv16i8_]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<16 x s8>) = COPY $q0
- %1:fpr(<16 x s8>) = COPY $q1
- %2:fpr(<16 x s8>) = G_LSHR %0, %1(<16 x s8>)
- $q0 = COPY %2(<16 x s8>)
+ %0:fpr(<16 x i8>) = COPY $q0
+ %1:fpr(<16 x i8>) = COPY $q1
+ %2:fpr(<16 x i8>) = G_LSHR %0, %1(<16 x i8>)
+ $q0 = COPY %2(<16 x i8>)
RET_ReallyLR implicit $q0
...
---
@@ -618,9 +618,9 @@ body: |
; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 24
; CHECK-NEXT: $d0 = COPY [[SHLv2i32_shift]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x s32>) = COPY $d0
+ %0:fpr(<2 x i32>) = COPY $d0
%2:gpr(s32) = G_CONSTANT i32 24
- %1:fpr(<2 x s32>) = G_DUP %2(s32)
- %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)
- $d0 = COPY %3(<2 x s32>)
+ %1:fpr(<2 x i32>) = G_DUP %2(s32)
+ %3:fpr(<2 x i32>) = G_SHL %0, %1(<2 x i32>)
+ $d0 = COPY %3(<2 x i32>)
RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
index 603ded2030b8e..d22305e441936 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
@@ -51,11 +51,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: STRDui [[COPY1]], [[COPY2]], 0 :: (store (<8 x s8>))
+ ; CHECK-NEXT: STRDui [[COPY1]], [[COPY2]], 0 :: (store (<8 x i8>))
; CHECK-NEXT: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d1
- %0:fpr(<8 x s8>) = COPY $d0
- G_STORE %0(<8 x s8>), %1(p0) :: (store (<8 x s8>))
+ %0:fpr(<8 x i8>) = COPY $d0
+ G_STORE %0(<8 x i8>), %1(p0) :: (store (<8 x i8>))
$noreg = PATCHABLE_RET
...
@@ -81,11 +81,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: STRDui [[COPY1]], [[COPY2]], 0 :: (store (<4 x s16>))
+ ; CHECK-NEXT: STRDui [[COPY1]], [[COPY2]], 0 :: (store (<4 x i16>))
; CHECK-NEXT: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d1
- %0:fpr(<4 x s16>) = COPY $d0
- G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>))
+ %0:fpr(<4 x i16>) = COPY $d0
+ G_STORE %0(<4 x i16>), %1(p0) :: (store (<4 x i16>))
$noreg = PATCHABLE_RET
...
@@ -111,11 +111,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<4 x s32>))
+ ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<4 x i32>))
; CHECK-NEXT: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
- %0:fpr(<4 x s32>) = COPY $q0
- G_STORE %0(<4 x s32>), %1(p0) :: (store (<4 x s32>))
+ %0:fpr(<4 x i32>) = COPY $q0
+ G_STORE %0(<4 x i32>), %1(p0) :: (store (<4 x i32>))
$noreg = PATCHABLE_RET
...
@@ -141,11 +141,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<2 x s64>))
+ ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<2 x i64>))
; CHECK-NEXT: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
- %0:fpr(<2 x s64>) = COPY $q0
- G_STORE %0(<2 x s64>), %1(p0) :: (store (<2 x s64>))
+ %0:fpr(<2 x i64>) = COPY $q0
+ G_STORE %0(<2 x i64>), %1(p0) :: (store (<2 x i64>))
$noreg = PATCHABLE_RET
...
@@ -171,11 +171,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<16 x s8>))
+ ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<16 x i8>))
; CHECK-NEXT: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
- %0:fpr(<16 x s8>) = COPY $q0
- G_STORE %0(<16 x s8>), %1(p0) :: (store (<16 x s8>))
+ %0:fpr(<16 x i8>) = COPY $q0
+ G_STORE %0(<16 x i8>), %1(p0) :: (store (<16 x i8>))
$noreg = PATCHABLE_RET
...
@@ -201,11 +201,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<8 x s16>))
+ ; CHECK-NEXT: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<8 x i16>))
; CHECK-NEXT: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
- %0:fpr(<8 x s16>) = COPY $q0
- G_STORE %0(<8 x s16>), %1(p0) :: (store (<8 x s16>))
+ %0:fpr(<8 x i16>) = COPY $q0
+ G_STORE %0(<8 x i16>), %1(p0) :: (store (<8 x i16>))
$noreg = PATCHABLE_RET
...
@@ -318,11 +318,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<8 x s8>))
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<8 x i8>))
; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRDui]]
%1:fpr(p0) = COPY $d0
- %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load (<8 x s8>))
- $noreg = PATCHABLE_RET %0(<8 x s8>)
+ %0:fpr(<8 x i8>) = G_LOAD %1(p0) :: (load (<8 x i8>))
+ $noreg = PATCHABLE_RET %0(<8 x i8>)
...
---
@@ -345,11 +345,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<4 x s16>))
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<4 x i16>))
; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRDui]]
%1:fpr(p0) = COPY $d0
- %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load (<4 x s16>))
- $noreg = PATCHABLE_RET %0(<4 x s16>)
+ %0:fpr(<4 x i16>) = G_LOAD %1(p0) :: (load (<4 x i16>))
+ $noreg = PATCHABLE_RET %0(<4 x i16>)
...
---
@@ -372,11 +372,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<4 x s32>))
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<4 x i32>))
; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
- %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>))
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %0:fpr(<4 x i32>) = G_LOAD %1(p0) :: (load (<4 x i32>))
+ $noreg = PATCHABLE_RET %0(<4 x i32>)
...
---
@@ -399,11 +399,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<2 x s64>))
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<2 x i64>))
; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
- %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>))
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %0:fpr(<2 x i64>) = G_LOAD %1(p0) :: (load (<2 x i64>))
+ $noreg = PATCHABLE_RET %0(<2 x i64>)
...
---
@@ -426,11 +426,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<16 x s8>))
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<16 x i8>))
; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
- %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>))
- $noreg = PATCHABLE_RET %0(<16 x s8>)
+ %0:fpr(<16 x i8>) = G_LOAD %1(p0) :: (load (<16 x i8>))
+ $noreg = PATCHABLE_RET %0(<16 x i8>)
...
---
@@ -453,11 +453,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<8 x s16>))
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<8 x i16>))
; CHECK-NEXT: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
- %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>))
- $noreg = PATCHABLE_RET %0(<8 x s16>)
+ %0:fpr(<8 x i16>) = G_LOAD %1(p0) :: (load (<8 x i16>))
+ $noreg = PATCHABLE_RET %0(<8 x i16>)
...
---
@@ -672,12 +672,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDLv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDLv4i16_v4i32_]]
- %4:fpr(<4 x s16>) = COPY $d1
- %3:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
- %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
- %2:fpr(<4 x s32>) = G_ADD %0, %1
- $noreg = PATCHABLE_RET %2(<4 x s32>)
+ %4:fpr(<4 x i16>) = COPY $d1
+ %3:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i32>) = G_SEXT %4(<4 x i16>)
+ %0:fpr(<4 x i32>) = G_SEXT %3(<4 x i16>)
+ %2:fpr(<4 x i32>) = G_ADD %0, %1
+ $noreg = PATCHABLE_RET %2(<4 x i32>)
...
---
@@ -706,12 +706,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDLv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDLv2i32_v2i64_]]
- %4:fpr(<2 x s32>) = COPY $d1
- %3:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
- %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
- %2:fpr(<2 x s64>) = G_ADD %0, %1
- $noreg = PATCHABLE_RET %2(<2 x s64>)
+ %4:fpr(<2 x i32>) = COPY $d1
+ %3:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i64>) = G_SEXT %4(<2 x i32>)
+ %0:fpr(<2 x i64>) = G_SEXT %3(<2 x i32>)
+ %2:fpr(<2 x i64>) = G_ADD %0, %1
+ $noreg = PATCHABLE_RET %2(<2 x i64>)
...
---
@@ -740,12 +740,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[UADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDLv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDLv8i8_v8i16_]]
- %4:fpr(<8 x s8>) = COPY $d1
- %3:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
- %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
- %2:fpr(<8 x s16>) = G_ADD %0, %1
- $noreg = PATCHABLE_RET %2(<8 x s16>)
+ %4:fpr(<8 x i8>) = COPY $d1
+ %3:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i16>) = G_ZEXT %4(<8 x i8>)
+ %0:fpr(<8 x i16>) = G_ZEXT %3(<8 x i8>)
+ %2:fpr(<8 x i16>) = G_ADD %0, %1
+ $noreg = PATCHABLE_RET %2(<8 x i16>)
...
---
@@ -774,12 +774,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[UADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDLv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDLv4i16_v4i32_]]
- %4:fpr(<4 x s16>) = COPY $d1
- %3:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
- %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
- %2:fpr(<4 x s32>) = G_ADD %0, %1
- $noreg = PATCHABLE_RET %2(<4 x s32>)
+ %4:fpr(<4 x i16>) = COPY $d1
+ %3:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i32>) = G_ZEXT %4(<4 x i16>)
+ %0:fpr(<4 x i32>) = G_ZEXT %3(<4 x i16>)
+ %2:fpr(<4 x i32>) = G_ADD %0, %1
+ $noreg = PATCHABLE_RET %2(<4 x i32>)
...
---
@@ -808,12 +808,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[UADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDLv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDLv2i32_v2i64_]]
- %4:fpr(<2 x s32>) = COPY $d1
- %3:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
- %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
- %2:fpr(<2 x s64>) = G_ADD %0, %1
- $noreg = PATCHABLE_RET %2(<2 x s64>)
+ %4:fpr(<2 x i32>) = COPY $d1
+ %3:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i64>) = G_ZEXT %4(<2 x i32>)
+ %0:fpr(<2 x i64>) = G_ZEXT %3(<2 x i32>)
+ %2:fpr(<2 x i64>) = G_ADD %0, %1
+ $noreg = PATCHABLE_RET %2(<2 x i64>)
...
---
@@ -842,12 +842,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SSUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBLv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBLv8i8_v8i16_]]
- %4:fpr(<8 x s8>) = COPY $d1
- %3:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
- %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
- %2:fpr(<8 x s16>) = G_SUB %0, %1
- $noreg = PATCHABLE_RET %2(<8 x s16>)
+ %4:fpr(<8 x i8>) = COPY $d1
+ %3:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i16>) = G_SEXT %4(<8 x i8>)
+ %0:fpr(<8 x i16>) = G_SEXT %3(<8 x i8>)
+ %2:fpr(<8 x i16>) = G_SUB %0, %1
+ $noreg = PATCHABLE_RET %2(<8 x i16>)
...
---
@@ -876,12 +876,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SSUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBLv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBLv4i16_v4i32_]]
- %4:fpr(<4 x s16>) = COPY $d1
- %3:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
- %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
- %2:fpr(<4 x s32>) = G_SUB %0, %1
- $noreg = PATCHABLE_RET %2(<4 x s32>)
+ %4:fpr(<4 x i16>) = COPY $d1
+ %3:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i32>) = G_SEXT %4(<4 x i16>)
+ %0:fpr(<4 x i32>) = G_SEXT %3(<4 x i16>)
+ %2:fpr(<4 x i32>) = G_SUB %0, %1
+ $noreg = PATCHABLE_RET %2(<4 x i32>)
...
---
@@ -910,12 +910,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SSUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBLv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBLv2i32_v2i64_]]
- %4:fpr(<2 x s32>) = COPY $d1
- %3:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
- %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
- %2:fpr(<2 x s64>) = G_SUB %0, %1
- $noreg = PATCHABLE_RET %2(<2 x s64>)
+ %4:fpr(<2 x i32>) = COPY $d1
+ %3:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i64>) = G_SEXT %4(<2 x i32>)
+ %0:fpr(<2 x i64>) = G_SEXT %3(<2 x i32>)
+ %2:fpr(<2 x i64>) = G_SUB %0, %1
+ $noreg = PATCHABLE_RET %2(<2 x i64>)
...
---
@@ -944,12 +944,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[USUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBLv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBLv8i8_v8i16_]]
- %4:fpr(<8 x s8>) = COPY $d1
- %3:fpr(<8 x s8>) = COPY $d0
- %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
- %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
- %2:fpr(<8 x s16>) = G_SUB %0, %1
- $noreg = PATCHABLE_RET %2(<8 x s16>)
+ %4:fpr(<8 x i8>) = COPY $d1
+ %3:fpr(<8 x i8>) = COPY $d0
+ %1:fpr(<8 x i16>) = G_ZEXT %4(<8 x i8>)
+ %0:fpr(<8 x i16>) = G_ZEXT %3(<8 x i8>)
+ %2:fpr(<8 x i16>) = G_SUB %0, %1
+ $noreg = PATCHABLE_RET %2(<8 x i16>)
...
---
@@ -978,12 +978,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[USUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBLv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBLv4i16_v4i32_]]
- %4:fpr(<4 x s16>) = COPY $d1
- %3:fpr(<4 x s16>) = COPY $d0
- %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
- %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
- %2:fpr(<4 x s32>) = G_SUB %0, %1
- $noreg = PATCHABLE_RET %2(<4 x s32>)
+ %4:fpr(<4 x i16>) = COPY $d1
+ %3:fpr(<4 x i16>) = COPY $d0
+ %1:fpr(<4 x i32>) = G_ZEXT %4(<4 x i16>)
+ %0:fpr(<4 x i32>) = G_ZEXT %3(<4 x i16>)
+ %2:fpr(<4 x i32>) = G_SUB %0, %1
+ $noreg = PATCHABLE_RET %2(<4 x i32>)
...
---
@@ -1012,12 +1012,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[USUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBLv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBLv2i32_v2i64_]]
- %4:fpr(<2 x s32>) = COPY $d1
- %3:fpr(<2 x s32>) = COPY $d0
- %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
- %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
- %2:fpr(<2 x s64>) = G_SUB %0, %1
- $noreg = PATCHABLE_RET %2(<2 x s64>)
+ %4:fpr(<2 x i32>) = COPY $d1
+ %3:fpr(<2 x i32>) = COPY $d0
+ %1:fpr(<2 x i64>) = G_ZEXT %4(<2 x i32>)
+ %0:fpr(<2 x i64>) = G_ZEXT %3(<2 x i32>)
+ %2:fpr(<2 x i64>) = G_SUB %0, %1
+ $noreg = PATCHABLE_RET %2(<2 x i64>)
...
---
@@ -1481,12 +1481,12 @@ body: |
; CHECK-NEXT: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[MULv8i8_]], [[COPY2]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i8_]]
- %4:fpr(<8 x s8>) = COPY $d2
- %3:fpr(<8 x s8>) = COPY $d1
- %2:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s8>) = G_MUL %3, %4
- %1:fpr(<8 x s8>) = G_ADD %0, %2
- $noreg = PATCHABLE_RET %1(<8 x s8>)
+ %4:fpr(<8 x i8>) = COPY $d2
+ %3:fpr(<8 x i8>) = COPY $d1
+ %2:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i8>) = G_MUL %3, %4
+ %1:fpr(<8 x i8>) = G_ADD %0, %2
+ $noreg = PATCHABLE_RET %1(<8 x i8>)
...
---
@@ -1518,12 +1518,12 @@ body: |
; CHECK-NEXT: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[MULv16i8_]], [[COPY2]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv16i8_]]
- %4:fpr(<16 x s8>) = COPY $q2
- %3:fpr(<16 x s8>) = COPY $q1
- %2:fpr(<16 x s8>) = COPY $q0
- %0:fpr(<16 x s8>) = G_MUL %3, %4
- %1:fpr(<16 x s8>) = G_ADD %0, %2
- $noreg = PATCHABLE_RET %1(<16 x s8>)
+ %4:fpr(<16 x i8>) = COPY $q2
+ %3:fpr(<16 x i8>) = COPY $q1
+ %2:fpr(<16 x i8>) = COPY $q0
+ %0:fpr(<16 x i8>) = G_MUL %3, %4
+ %1:fpr(<16 x i8>) = G_ADD %0, %2
+ $noreg = PATCHABLE_RET %1(<16 x i8>)
...
---
@@ -1555,12 +1555,12 @@ body: |
; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[MULv4i16_]], [[COPY2]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv4i16_]]
- %4:fpr(<4 x s16>) = COPY $d2
- %3:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s16>) = G_MUL %3, %4
- %1:fpr(<4 x s16>) = G_ADD %0, %2
- $noreg = PATCHABLE_RET %1(<4 x s16>)
+ %4:fpr(<4 x i16>) = COPY $d2
+ %3:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i16>) = G_MUL %3, %4
+ %1:fpr(<4 x i16>) = G_ADD %0, %2
+ $noreg = PATCHABLE_RET %1(<4 x i16>)
...
---
@@ -1592,12 +1592,12 @@ body: |
; CHECK-NEXT: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[MULv8i16_]], [[COPY2]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i16_]]
- %4:fpr(<8 x s16>) = COPY $q2
- %3:fpr(<8 x s16>) = COPY $q1
- %2:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_MUL %3, %4
- %1:fpr(<8 x s16>) = G_ADD %0, %2
- $noreg = PATCHABLE_RET %1(<8 x s16>)
+ %4:fpr(<8 x i16>) = COPY $q2
+ %3:fpr(<8 x i16>) = COPY $q1
+ %2:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_MUL %3, %4
+ %1:fpr(<8 x i16>) = G_ADD %0, %2
+ $noreg = PATCHABLE_RET %1(<8 x i16>)
...
---
@@ -1625,11 +1625,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]
- %3:fpr(<8 x s8>) = COPY $d0
- %2:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
- %1:fpr(<8 x s16>) = G_ADD %0, %2
- $noreg = PATCHABLE_RET %1(<8 x s16>)
+ %3:fpr(<8 x i8>) = COPY $d0
+ %2:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_SEXT %3(<8 x i8>)
+ %1:fpr(<8 x i16>) = G_ADD %0, %2
+ $noreg = PATCHABLE_RET %1(<8 x i16>)
...
---
@@ -1657,11 +1657,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]
- %3:fpr(<4 x s16>) = COPY $d0
- %2:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
- %1:fpr(<4 x s32>) = G_ADD %0, %2
- $noreg = PATCHABLE_RET %1(<4 x s32>)
+ %3:fpr(<4 x i16>) = COPY $d0
+ %2:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x i32>) = G_SEXT %3(<4 x i16>)
+ %1:fpr(<4 x i32>) = G_ADD %0, %2
+ $noreg = PATCHABLE_RET %1(<4 x i32>)
...
---
@@ -1689,11 +1689,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]
- %3:fpr(<2 x s32>) = COPY $d0
- %2:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
- %1:fpr(<2 x s64>) = G_ADD %0, %2
- $noreg = PATCHABLE_RET %1(<2 x s64>)
+ %3:fpr(<2 x i32>) = COPY $d0
+ %2:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x i64>) = G_SEXT %3(<2 x i32>)
+ %1:fpr(<2 x i64>) = G_ADD %0, %2
+ $noreg = PATCHABLE_RET %1(<2 x i64>)
...
---
@@ -1721,11 +1721,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]
- %3:fpr(<8 x s8>) = COPY $d0
- %2:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
- %1:fpr(<8 x s16>) = G_ADD %0, %2
- $noreg = PATCHABLE_RET %1(<8 x s16>)
+ %3:fpr(<8 x i8>) = COPY $d0
+ %2:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_ZEXT %3(<8 x i8>)
+ %1:fpr(<8 x i16>) = G_ADD %0, %2
+ $noreg = PATCHABLE_RET %1(<8 x i16>)
...
---
@@ -1753,11 +1753,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]
- %3:fpr(<4 x s16>) = COPY $d0
- %2:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
- %1:fpr(<4 x s32>) = G_ADD %0, %2
- $noreg = PATCHABLE_RET %1(<4 x s32>)
+ %3:fpr(<4 x i16>) = COPY $d0
+ %2:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x i32>) = G_ZEXT %3(<4 x i16>)
+ %1:fpr(<4 x i32>) = G_ADD %0, %2
+ $noreg = PATCHABLE_RET %1(<4 x i32>)
...
---
@@ -1785,11 +1785,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]
- %3:fpr(<2 x s32>) = COPY $d0
- %2:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
- %1:fpr(<2 x s64>) = G_ADD %0, %2
- $noreg = PATCHABLE_RET %1(<2 x s64>)
+ %3:fpr(<2 x i32>) = COPY $d0
+ %2:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x i64>) = G_ZEXT %3(<2 x i32>)
+ %1:fpr(<2 x i64>) = G_ADD %0, %2
+ $noreg = PATCHABLE_RET %1(<2 x i64>)
...
---
@@ -1821,12 +1821,12 @@ body: |
; CHECK-NEXT: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY2]], [[MULv8i8_]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i8_]]
- %4:fpr(<8 x s8>) = COPY $d2
- %3:fpr(<8 x s8>) = COPY $d1
- %2:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s8>) = G_MUL %3, %4
- %1:fpr(<8 x s8>) = G_ADD %2, %0
- $noreg = PATCHABLE_RET %1(<8 x s8>)
+ %4:fpr(<8 x i8>) = COPY $d2
+ %3:fpr(<8 x i8>) = COPY $d1
+ %2:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i8>) = G_MUL %3, %4
+ %1:fpr(<8 x i8>) = G_ADD %2, %0
+ $noreg = PATCHABLE_RET %1(<8 x i8>)
...
---
@@ -1858,12 +1858,12 @@ body: |
; CHECK-NEXT: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY2]], [[MULv16i8_]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv16i8_]]
- %4:fpr(<16 x s8>) = COPY $q2
- %3:fpr(<16 x s8>) = COPY $q1
- %2:fpr(<16 x s8>) = COPY $q0
- %0:fpr(<16 x s8>) = G_MUL %3, %4
- %1:fpr(<16 x s8>) = G_ADD %2, %0
- $noreg = PATCHABLE_RET %1(<16 x s8>)
+ %4:fpr(<16 x i8>) = COPY $q2
+ %3:fpr(<16 x i8>) = COPY $q1
+ %2:fpr(<16 x i8>) = COPY $q0
+ %0:fpr(<16 x i8>) = G_MUL %3, %4
+ %1:fpr(<16 x i8>) = G_ADD %2, %0
+ $noreg = PATCHABLE_RET %1(<16 x i8>)
...
---
@@ -1895,12 +1895,12 @@ body: |
; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY2]], [[MULv4i16_]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv4i16_]]
- %4:fpr(<4 x s16>) = COPY $d2
- %3:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s16>) = G_MUL %3, %4
- %1:fpr(<4 x s16>) = G_ADD %2, %0
- $noreg = PATCHABLE_RET %1(<4 x s16>)
+ %4:fpr(<4 x i16>) = COPY $d2
+ %3:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i16>) = G_MUL %3, %4
+ %1:fpr(<4 x i16>) = G_ADD %2, %0
+ $noreg = PATCHABLE_RET %1(<4 x i16>)
...
---
@@ -1932,12 +1932,12 @@ body: |
; CHECK-NEXT: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY2]], [[MULv8i16_]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i16_]]
- %4:fpr(<8 x s16>) = COPY $q2
- %3:fpr(<8 x s16>) = COPY $q1
- %2:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_MUL %3, %4
- %1:fpr(<8 x s16>) = G_ADD %2, %0
- $noreg = PATCHABLE_RET %1(<8 x s16>)
+ %4:fpr(<8 x i16>) = COPY $q2
+ %3:fpr(<8 x i16>) = COPY $q1
+ %2:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_MUL %3, %4
+ %1:fpr(<8 x i16>) = G_ADD %2, %0
+ $noreg = PATCHABLE_RET %1(<8 x i16>)
...
---
@@ -1965,11 +1965,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]
- %3:fpr(<8 x s8>) = COPY $d0
- %2:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
- %1:fpr(<8 x s16>) = G_ADD %2, %0
- $noreg = PATCHABLE_RET %1(<8 x s16>)
+ %3:fpr(<8 x i8>) = COPY $d0
+ %2:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_SEXT %3(<8 x i8>)
+ %1:fpr(<8 x i16>) = G_ADD %2, %0
+ $noreg = PATCHABLE_RET %1(<8 x i16>)
...
---
@@ -1997,11 +1997,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]
- %3:fpr(<4 x s16>) = COPY $d0
- %2:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
- %1:fpr(<4 x s32>) = G_ADD %2, %0
- $noreg = PATCHABLE_RET %1(<4 x s32>)
+ %3:fpr(<4 x i16>) = COPY $d0
+ %2:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x i32>) = G_SEXT %3(<4 x i16>)
+ %1:fpr(<4 x i32>) = G_ADD %2, %0
+ $noreg = PATCHABLE_RET %1(<4 x i32>)
...
---
@@ -2029,11 +2029,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]
- %3:fpr(<2 x s32>) = COPY $d0
- %2:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
- %1:fpr(<2 x s64>) = G_ADD %2, %0
- $noreg = PATCHABLE_RET %1(<2 x s64>)
+ %3:fpr(<2 x i32>) = COPY $d0
+ %2:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x i64>) = G_SEXT %3(<2 x i32>)
+ %1:fpr(<2 x i64>) = G_ADD %2, %0
+ $noreg = PATCHABLE_RET %1(<2 x i64>)
...
---
@@ -2061,11 +2061,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]
- %3:fpr(<8 x s8>) = COPY $d0
- %2:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
- %1:fpr(<8 x s16>) = G_ADD %2, %0
- $noreg = PATCHABLE_RET %1(<8 x s16>)
+ %3:fpr(<8 x i8>) = COPY $d0
+ %2:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_ZEXT %3(<8 x i8>)
+ %1:fpr(<8 x i16>) = G_ADD %2, %0
+ $noreg = PATCHABLE_RET %1(<8 x i16>)
...
---
@@ -2093,11 +2093,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]
- %3:fpr(<4 x s16>) = COPY $d0
- %2:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
- %1:fpr(<4 x s32>) = G_ADD %2, %0
- $noreg = PATCHABLE_RET %1(<4 x s32>)
+ %3:fpr(<4 x i16>) = COPY $d0
+ %2:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x i32>) = G_ZEXT %3(<4 x i16>)
+ %1:fpr(<4 x i32>) = G_ADD %2, %0
+ $noreg = PATCHABLE_RET %1(<4 x i32>)
...
---
@@ -2125,11 +2125,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]
- %3:fpr(<2 x s32>) = COPY $d0
- %2:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
- %1:fpr(<2 x s64>) = G_ADD %2, %0
- $noreg = PATCHABLE_RET %1(<2 x s64>)
+ %3:fpr(<2 x i32>) = COPY $d0
+ %2:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x i64>) = G_ZEXT %3(<2 x i32>)
+ %1:fpr(<2 x i64>) = G_ADD %2, %0
+ $noreg = PATCHABLE_RET %1(<2 x i64>)
...
---
@@ -2161,12 +2161,12 @@ body: |
; CHECK-NEXT: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY2]], [[MULv8i8_]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv8i8_]]
- %4:fpr(<8 x s8>) = COPY $d2
- %3:fpr(<8 x s8>) = COPY $d1
- %2:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s8>) = G_MUL %3, %4
- %1:fpr(<8 x s8>) = G_SUB %2, %0
- $noreg = PATCHABLE_RET %1(<8 x s8>)
+ %4:fpr(<8 x i8>) = COPY $d2
+ %3:fpr(<8 x i8>) = COPY $d1
+ %2:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i8>) = G_MUL %3, %4
+ %1:fpr(<8 x i8>) = G_SUB %2, %0
+ $noreg = PATCHABLE_RET %1(<8 x i8>)
...
---
@@ -2198,12 +2198,12 @@ body: |
; CHECK-NEXT: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY2]], [[MULv16i8_]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv16i8_]]
- %4:fpr(<16 x s8>) = COPY $q2
- %3:fpr(<16 x s8>) = COPY $q1
- %2:fpr(<16 x s8>) = COPY $q0
- %0:fpr(<16 x s8>) = G_MUL %3, %4
- %1:fpr(<16 x s8>) = G_SUB %2, %0
- $noreg = PATCHABLE_RET %1(<16 x s8>)
+ %4:fpr(<16 x i8>) = COPY $q2
+ %3:fpr(<16 x i8>) = COPY $q1
+ %2:fpr(<16 x i8>) = COPY $q0
+ %0:fpr(<16 x i8>) = G_MUL %3, %4
+ %1:fpr(<16 x i8>) = G_SUB %2, %0
+ $noreg = PATCHABLE_RET %1(<16 x i8>)
...
---
@@ -2235,12 +2235,12 @@ body: |
; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY2]], [[MULv4i16_]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv4i16_]]
- %4:fpr(<4 x s16>) = COPY $d2
- %3:fpr(<4 x s16>) = COPY $d1
- %2:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s16>) = G_MUL %3, %4
- %1:fpr(<4 x s16>) = G_SUB %2, %0
- $noreg = PATCHABLE_RET %1(<4 x s16>)
+ %4:fpr(<4 x i16>) = COPY $d2
+ %3:fpr(<4 x i16>) = COPY $d1
+ %2:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i16>) = G_MUL %3, %4
+ %1:fpr(<4 x i16>) = G_SUB %2, %0
+ $noreg = PATCHABLE_RET %1(<4 x i16>)
...
---
@@ -2272,12 +2272,12 @@ body: |
; CHECK-NEXT: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY2]], [[MULv8i16_]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv8i16_]]
- %4:fpr(<8 x s16>) = COPY $q2
- %3:fpr(<8 x s16>) = COPY $q1
- %2:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_MUL %3, %4
- %1:fpr(<8 x s16>) = G_SUB %2, %0
- $noreg = PATCHABLE_RET %1(<8 x s16>)
+ %4:fpr(<8 x i16>) = COPY $q2
+ %3:fpr(<8 x i16>) = COPY $q1
+ %2:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_MUL %3, %4
+ %1:fpr(<8 x i16>) = G_SUB %2, %0
+ $noreg = PATCHABLE_RET %1(<8 x i16>)
...
---
@@ -2305,11 +2305,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SSUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBWv8i8_v8i16_]]
- %3:fpr(<8 x s8>) = COPY $d0
- %2:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
- %1:fpr(<8 x s16>) = G_SUB %2, %0
- $noreg = PATCHABLE_RET %1(<8 x s16>)
+ %3:fpr(<8 x i8>) = COPY $d0
+ %2:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_SEXT %3(<8 x i8>)
+ %1:fpr(<8 x i16>) = G_SUB %2, %0
+ $noreg = PATCHABLE_RET %1(<8 x i16>)
...
---
@@ -2337,11 +2337,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SSUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBWv4i16_v4i32_]]
- %3:fpr(<4 x s16>) = COPY $d0
- %2:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
- %1:fpr(<4 x s32>) = G_SUB %2, %0
- $noreg = PATCHABLE_RET %1(<4 x s32>)
+ %3:fpr(<4 x i16>) = COPY $d0
+ %2:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x i32>) = G_SEXT %3(<4 x i16>)
+ %1:fpr(<4 x i32>) = G_SUB %2, %0
+ $noreg = PATCHABLE_RET %1(<4 x i32>)
...
---
@@ -2369,11 +2369,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SSUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSUBWv2i32_v2i64_]]
- %3:fpr(<2 x s32>) = COPY $d0
- %2:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
- %1:fpr(<2 x s64>) = G_SUB %2, %0
- $noreg = PATCHABLE_RET %1(<2 x s64>)
+ %3:fpr(<2 x i32>) = COPY $d0
+ %2:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x i64>) = G_SEXT %3(<2 x i32>)
+ %1:fpr(<2 x i64>) = G_SUB %2, %0
+ $noreg = PATCHABLE_RET %1(<2 x i64>)
...
---
@@ -2401,11 +2401,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[USUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBWv8i8_v8i16_]]
- %3:fpr(<8 x s8>) = COPY $d0
- %2:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
- %1:fpr(<8 x s16>) = G_SUB %2, %0
- $noreg = PATCHABLE_RET %1(<8 x s16>)
+ %3:fpr(<8 x i8>) = COPY $d0
+ %2:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_ZEXT %3(<8 x i8>)
+ %1:fpr(<8 x i16>) = G_SUB %2, %0
+ $noreg = PATCHABLE_RET %1(<8 x i16>)
...
---
@@ -2433,11 +2433,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[USUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBWv4i16_v4i32_]]
- %3:fpr(<4 x s16>) = COPY $d0
- %2:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
- %1:fpr(<4 x s32>) = G_SUB %2, %0
- $noreg = PATCHABLE_RET %1(<4 x s32>)
+ %3:fpr(<4 x i16>) = COPY $d0
+ %2:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x i32>) = G_ZEXT %3(<4 x i16>)
+ %1:fpr(<4 x i32>) = G_SUB %2, %0
+ $noreg = PATCHABLE_RET %1(<4 x i32>)
...
---
@@ -2465,11 +2465,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[USUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USUBWv2i32_v2i64_]]
- %3:fpr(<2 x s32>) = COPY $d0
- %2:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
- %1:fpr(<2 x s64>) = G_SUB %2, %0
- $noreg = PATCHABLE_RET %1(<2 x s64>)
+ %3:fpr(<2 x i32>) = COPY $d0
+ %2:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x i64>) = G_ZEXT %3(<2 x i32>)
+ %1:fpr(<2 x i64>) = G_SUB %2, %0
+ $noreg = PATCHABLE_RET %1(<2 x i64>)
...
---
@@ -2630,11 +2630,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
- ; CHECK-NEXT: ST1Onev8b [[COPY2]], [[COPY]] :: (store (<8 x s8>))
+ ; CHECK-NEXT: ST1Onev8b [[COPY2]], [[COPY]] :: (store (<8 x i8>))
; CHECK-NEXT: $noreg = PATCHABLE_RET
%1:gpr(p0) = COPY $x1
- %0:gpr(<8 x s8>) = COPY $x0
- G_STORE %0(<8 x s8>), %1(p0) :: (store (<8 x s8>))
+ %0:gpr(<8 x i8>) = COPY $x0
+ G_STORE %0(<8 x i8>), %1(p0) :: (store (<8 x i8>))
$noreg = PATCHABLE_RET
...
@@ -2660,11 +2660,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
- ; CHECK-NEXT: ST1Onev4h [[COPY2]], [[COPY]] :: (store (<4 x s16>))
+ ; CHECK-NEXT: ST1Onev4h [[COPY2]], [[COPY]] :: (store (<4 x i16>))
; CHECK-NEXT: $noreg = PATCHABLE_RET
%1:gpr(p0) = COPY $x1
- %0:gpr(<4 x s16>) = COPY $x0
- G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>))
+ %0:gpr(<4 x i16>) = COPY $x0
+ G_STORE %0(<4 x i16>), %1(p0) :: (store (<4 x i16>))
$noreg = PATCHABLE_RET
...
@@ -2794,10 +2794,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i8_]]
- %2:fpr(<8 x s8>) = COPY $d1
- %1:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s8>) = G_ADD %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s8>)
+ %2:fpr(<8 x i8>) = COPY $d1
+ %1:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i8>) = G_ADD %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i8>)
...
---
@@ -2824,10 +2824,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv16i8_]]
- %2:fpr(<16 x s8>) = COPY $q1
- %1:fpr(<16 x s8>) = COPY $q0
- %0:fpr(<16 x s8>) = G_ADD %1, %2
- $noreg = PATCHABLE_RET %0(<16 x s8>)
+ %2:fpr(<16 x i8>) = COPY $q1
+ %1:fpr(<16 x i8>) = COPY $q0
+ %0:fpr(<16 x i8>) = G_ADD %1, %2
+ $noreg = PATCHABLE_RET %0(<16 x i8>)
...
---
@@ -2854,10 +2854,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv4i16_]]
- %2:fpr(<4 x s16>) = COPY $d1
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s16>) = G_ADD %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s16>)
+ %2:fpr(<4 x i16>) = COPY $d1
+ %1:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i16>) = G_ADD %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x i16>)
...
---
@@ -2884,10 +2884,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ADDv8i16_]]
- %2:fpr(<8 x s16>) = COPY $q1
- %1:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_ADD %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s16>)
+ %2:fpr(<8 x i16>) = COPY $q1
+ %1:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_ADD %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i16>)
...
---
@@ -2914,10 +2914,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ANDv8i8_]]
- %2:fpr(<8 x s8>) = COPY $d1
- %1:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s8>) = G_AND %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s8>)
+ %2:fpr(<8 x i8>) = COPY $d1
+ %1:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i8>) = G_AND %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i8>)
...
---
@@ -2944,10 +2944,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ANDv16i8_]]
- %2:fpr(<16 x s8>) = COPY $q1
- %1:fpr(<16 x s8>) = COPY $q0
- %0:fpr(<16 x s8>) = G_AND %1, %2
- $noreg = PATCHABLE_RET %0(<16 x s8>)
+ %2:fpr(<16 x i8>) = COPY $q1
+ %1:fpr(<16 x i8>) = COPY $q0
+ %0:fpr(<16 x i8>) = G_AND %1, %2
+ $noreg = PATCHABLE_RET %0(<16 x i8>)
...
---
@@ -2974,10 +2974,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ANDv8i8_]]
- %2:fpr(<4 x s16>) = COPY $d1
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s16>) = G_AND %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s16>)
+ %2:fpr(<4 x i16>) = COPY $d1
+ %1:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i16>) = G_AND %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x i16>)
...
---
@@ -3004,10 +3004,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ANDv16i8_]]
- %2:fpr(<8 x s16>) = COPY $q1
- %1:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_AND %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s16>)
+ %2:fpr(<8 x i16>) = COPY $q1
+ %1:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_AND %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i16>)
...
---
@@ -3394,10 +3394,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[MULv8i8_]]
- %2:fpr(<8 x s8>) = COPY $d1
- %1:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s8>) = G_MUL %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s8>)
+ %2:fpr(<8 x i8>) = COPY $d1
+ %1:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i8>) = G_MUL %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i8>)
...
---
@@ -3424,10 +3424,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[MULv16i8_]]
- %2:fpr(<16 x s8>) = COPY $q1
- %1:fpr(<16 x s8>) = COPY $q0
- %0:fpr(<16 x s8>) = G_MUL %1, %2
- $noreg = PATCHABLE_RET %0(<16 x s8>)
+ %2:fpr(<16 x i8>) = COPY $q1
+ %1:fpr(<16 x i8>) = COPY $q0
+ %0:fpr(<16 x i8>) = G_MUL %1, %2
+ $noreg = PATCHABLE_RET %0(<16 x i8>)
...
---
@@ -3454,10 +3454,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[MULv4i16_]]
- %2:fpr(<4 x s16>) = COPY $d1
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s16>) = G_MUL %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s16>)
+ %2:fpr(<4 x i16>) = COPY $d1
+ %1:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i16>) = G_MUL %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x i16>)
...
---
@@ -3484,10 +3484,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[MULv8i16_]]
- %2:fpr(<8 x s16>) = COPY $q1
- %1:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_MUL %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s16>)
+ %2:fpr(<8 x i16>) = COPY $q1
+ %1:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_MUL %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i16>)
...
---
@@ -3514,10 +3514,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ORRv8i8_]]
- %2:fpr(<8 x s8>) = COPY $d1
- %1:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s8>) = G_OR %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s8>)
+ %2:fpr(<8 x i8>) = COPY $d1
+ %1:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i8>) = G_OR %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i8>)
...
---
@@ -3544,10 +3544,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ORRv16i8_]]
- %2:fpr(<16 x s8>) = COPY $q1
- %1:fpr(<16 x s8>) = COPY $q0
- %0:fpr(<16 x s8>) = G_OR %1, %2
- $noreg = PATCHABLE_RET %0(<16 x s8>)
+ %2:fpr(<16 x i8>) = COPY $q1
+ %1:fpr(<16 x i8>) = COPY $q0
+ %0:fpr(<16 x i8>) = G_OR %1, %2
+ $noreg = PATCHABLE_RET %0(<16 x i8>)
...
---
@@ -3574,10 +3574,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ORRv8i8_]]
- %2:fpr(<4 x s16>) = COPY $d1
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s16>) = G_OR %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s16>)
+ %2:fpr(<4 x i16>) = COPY $d1
+ %1:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i16>) = G_OR %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x i16>)
...
---
@@ -3604,10 +3604,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[ORRv16i8_]]
- %2:fpr(<8 x s16>) = COPY $q1
- %1:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_OR %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s16>)
+ %2:fpr(<8 x i16>) = COPY $q1
+ %1:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_OR %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i16>)
...
---
@@ -3634,10 +3634,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv8i8_]]
- %2:fpr(<8 x s8>) = COPY $d1
- %1:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s8>) = G_SUB %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s8>)
+ %2:fpr(<8 x i8>) = COPY $d1
+ %1:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i8>) = G_SUB %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i8>)
...
---
@@ -3664,10 +3664,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv16i8_]]
- %2:fpr(<16 x s8>) = COPY $q1
- %1:fpr(<16 x s8>) = COPY $q0
- %0:fpr(<16 x s8>) = G_SUB %1, %2
- $noreg = PATCHABLE_RET %0(<16 x s8>)
+ %2:fpr(<16 x i8>) = COPY $q1
+ %1:fpr(<16 x i8>) = COPY $q0
+ %0:fpr(<16 x i8>) = G_SUB %1, %2
+ $noreg = PATCHABLE_RET %0(<16 x i8>)
...
---
@@ -3694,10 +3694,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv4i16_]]
- %2:fpr(<4 x s16>) = COPY $d1
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s16>) = G_SUB %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s16>)
+ %2:fpr(<4 x i16>) = COPY $d1
+ %1:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i16>) = G_SUB %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x i16>)
...
---
@@ -3724,10 +3724,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SUBv8i16_]]
- %2:fpr(<8 x s16>) = COPY $q1
- %1:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_SUB %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s16>)
+ %2:fpr(<8 x i16>) = COPY $q1
+ %1:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_SUB %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i16>)
...
---
@@ -3754,10 +3754,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[EORv8i8_]]
- %2:fpr(<8 x s8>) = COPY $d1
- %1:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s8>) = G_XOR %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s8>)
+ %2:fpr(<8 x i8>) = COPY $d1
+ %1:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i8>) = G_XOR %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i8>)
...
---
@@ -3784,10 +3784,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[EORv16i8_]]
- %2:fpr(<16 x s8>) = COPY $q1
- %1:fpr(<16 x s8>) = COPY $q0
- %0:fpr(<16 x s8>) = G_XOR %1, %2
- $noreg = PATCHABLE_RET %0(<16 x s8>)
+ %2:fpr(<16 x i8>) = COPY $q1
+ %1:fpr(<16 x i8>) = COPY $q0
+ %0:fpr(<16 x i8>) = G_XOR %1, %2
+ $noreg = PATCHABLE_RET %0(<16 x i8>)
...
---
@@ -3814,10 +3814,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[EORv8i8_]]
- %2:fpr(<4 x s16>) = COPY $d1
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s16>) = G_XOR %1, %2
- $noreg = PATCHABLE_RET %0(<4 x s16>)
+ %2:fpr(<4 x i16>) = COPY $d1
+ %1:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i16>) = G_XOR %1, %2
+ $noreg = PATCHABLE_RET %0(<4 x i16>)
...
---
@@ -3844,10 +3844,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[EORv16i8_]]
- %2:fpr(<8 x s16>) = COPY $q1
- %1:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s16>) = G_XOR %1, %2
- $noreg = PATCHABLE_RET %0(<8 x s16>)
+ %2:fpr(<8 x i16>) = COPY $q1
+ %1:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i16>) = G_XOR %1, %2
+ $noreg = PATCHABLE_RET %0(<8 x i16>)
...
---
@@ -3871,9 +3871,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]]
- %1:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
- $noreg = PATCHABLE_RET %0(<8 x s16>)
+ %1:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i16>) = G_ANYEXT %1(<8 x i8>)
+ $noreg = PATCHABLE_RET %0(<8 x i16>)
...
---
@@ -3897,9 +3897,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]]
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i32>) = G_ANYEXT %1(<4 x i16>)
+ $noreg = PATCHABLE_RET %0(<4 x i32>)
...
---
@@ -3923,9 +3923,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x i32>) = COPY $d0
+ %0:fpr(<2 x i64>) = G_ANYEXT %1(<2 x i32>)
+ $noreg = PATCHABLE_RET %0(<2 x i64>)
...
---
@@ -4339,9 +4339,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSHLLv8i8_shift]]
- %1:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s16>) = G_SEXT %1(<8 x s8>)
- $noreg = PATCHABLE_RET %0(<8 x s16>)
+ %1:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i16>) = G_SEXT %1(<8 x i8>)
+ $noreg = PATCHABLE_RET %0(<8 x i16>)
...
---
@@ -4365,9 +4365,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSHLLv4i16_shift]]
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s32>) = G_SEXT %1(<4 x s16>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i32>) = G_SEXT %1(<4 x i16>)
+ $noreg = PATCHABLE_RET %0(<4 x i32>)
...
---
@@ -4391,9 +4391,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
; CHECK-NEXT: $noreg = PATCHABLE_RET [[SSHLLv2i32_shift]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s64>) = G_SEXT %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x i32>) = COPY $d0
+ %0:fpr(<2 x i64>) = G_SEXT %1(<2 x i32>)
+ $noreg = PATCHABLE_RET %0(<2 x i64>)
...
---
@@ -4495,9 +4495,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[XTNv8i8_]]
- %1:fpr(<8 x s16>) = COPY $q0
- %0:fpr(<8 x s8>) = G_TRUNC %1(<8 x s16>)
- $noreg = PATCHABLE_RET %0(<8 x s8>)
+ %1:fpr(<8 x i16>) = COPY $q0
+ %0:fpr(<8 x i8>) = G_TRUNC %1(<8 x i16>)
+ $noreg = PATCHABLE_RET %0(<8 x i8>)
...
---
@@ -4521,9 +4521,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[XTNv4i16_]]
- %1:fpr(<4 x s32>) = COPY $q0
- %0:fpr(<4 x s16>) = G_TRUNC %1(<4 x s32>)
- $noreg = PATCHABLE_RET %0(<4 x s16>)
+ %1:fpr(<4 x i32>) = COPY $q0
+ %0:fpr(<4 x i16>) = G_TRUNC %1(<4 x i32>)
+ $noreg = PATCHABLE_RET %0(<4 x i16>)
...
---
@@ -4547,9 +4547,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[COPY]]
; CHECK-NEXT: $noreg = PATCHABLE_RET [[XTNv2i32_]]
- %1:fpr(<2 x s64>) = COPY $q0
- %0:fpr(<2 x s32>) = G_TRUNC %1(<2 x s64>)
- $noreg = PATCHABLE_RET %0(<2 x s32>)
+ %1:fpr(<2 x i64>) = COPY $q0
+ %0:fpr(<2 x i32>) = G_TRUNC %1(<2 x i64>)
+ $noreg = PATCHABLE_RET %0(<2 x i32>)
...
---
@@ -4651,9 +4651,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]]
- %1:fpr(<8 x s8>) = COPY $d0
- %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
- $noreg = PATCHABLE_RET %0(<8 x s16>)
+ %1:fpr(<8 x i8>) = COPY $d0
+ %0:fpr(<8 x i16>) = G_ZEXT %1(<8 x i8>)
+ $noreg = PATCHABLE_RET %0(<8 x i16>)
...
---
@@ -4677,9 +4677,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]]
- %1:fpr(<4 x s16>) = COPY $d0
- %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
- $noreg = PATCHABLE_RET %0(<4 x s32>)
+ %1:fpr(<4 x i16>) = COPY $d0
+ %0:fpr(<4 x i32>) = G_ZEXT %1(<4 x i16>)
+ $noreg = PATCHABLE_RET %0(<4 x i32>)
...
---
@@ -4703,8 +4703,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
; CHECK-NEXT: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]]
- %1:fpr(<2 x s32>) = COPY $d0
- %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
- $noreg = PATCHABLE_RET %0(<2 x s64>)
+ %1:fpr(<2 x i32>) = COPY $d0
+ %0:fpr(<2 x i64>) = G_ZEXT %1(<2 x i32>)
+ $noreg = PATCHABLE_RET %0(<2 x i64>)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir
index 6465e9a8c4e80..ba08376dda393 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir
@@ -35,10 +35,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[EORWrr:%[0-9]+]]:gpr32 = EORWrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[EORWrr]]
- %0(s32) = COPY $w0
- %1(s32) = COPY $w1
- %2(s32) = G_XOR %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = COPY $w1
+ %2(i32) = G_XOR %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -63,10 +63,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[EORXrr:%[0-9]+]]:gpr64 = EORXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[EORXrr]]
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_XOR %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = COPY $x1
+ %2(i64) = G_XOR %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -91,10 +91,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]]
; CHECK-NEXT: $w0 = COPY [[ORNWrr]]
- %0(s32) = COPY $w0
- %1(s32) = G_CONSTANT i32 -1
- %2(s32) = G_XOR %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %1(i32) = G_CONSTANT i32 -1
+ %2(i32) = G_XOR %0, %1
+ $w0 = COPY %2(i32)
...
---
@@ -118,10 +118,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr $xzr, [[COPY]]
; CHECK-NEXT: $x0 = COPY [[ORNXrr]]
- %0(s64) = COPY $x0
- %1(s64) = G_CONSTANT i64 -1
- %2(s64) = G_XOR %0, %1
- $x0 = COPY %2(s64)
+ %0(i64) = COPY $x0
+ %1(i64) = G_CONSTANT i64 -1
+ %2(i64) = G_XOR %0, %1
+ $x0 = COPY %2(i64)
...
---
@@ -151,10 +151,10 @@ body: |
bb.0:
liveins: $w0, $w1
successors: %bb.1
- %1(s32) = G_CONSTANT i32 -1
+ %1(i32) = G_CONSTANT i32 -1
G_BR %bb.1
bb.1:
- %0(s32) = COPY $w0
- %2(s32) = G_XOR %0, %1
- $w0 = COPY %2(s32)
+ %0(i32) = COPY $w0
+ %2(i32) = G_XOR %0, %1
+ $w0 = COPY %2(i32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
index ae10f4a5b30ab..e6b400f324133 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
@@ -29,9 +29,9 @@ body: |
; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
; CHECK-NEXT: $x0 = COPY [[ANDXri]]
%3:gpr(p0) = G_IMPLICIT_DEF
- %2:gpr(s8) = G_LOAD %3(p0) :: (load (s8))
- %4:gpr(s64) = G_ZEXT %2(s8)
- %5:gpr(s64) = G_CONSTANT i64 1
- %6:gpr(s64) = G_AND %4, %5
+ %2:gpr(i8) = G_LOAD %3(p0) :: (load (s8))
+ %4:gpr(i64) = G_ZEXT %2(i8)
+ %5:gpr(i64) = G_CONSTANT i64 1
+ %6:gpr(i64) = G_AND %4, %5
$x0 = COPY %6
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
index 0cf16ec9f8e95..b6b386acdbd9a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
@@ -16,8 +16,8 @@ body: |
; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
%0:gpr(p0) = COPY $x0
- %1:gpr(s32) = G_ZEXTLOAD %0 :: (load (s16))
- $w0 = COPY %1(s32)
+ %1:gpr(i32) = G_ZEXTLOAD %0 :: (load (s16))
+ $w0 = COPY %1(i32)
...
---
name: zextload_s32_from_s16_not_combined
@@ -36,8 +36,8 @@ body: |
; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0:gpr(p0) = COPY $x0
%1:gpr(s16) = G_LOAD %0 :: (load (s16))
- %2:gpr(s32) = G_ZEXT %1
- $w0 = COPY %2(s32)
+ %2:gpr(i32) = G_ZEXT %1
+ $w0 = COPY %2(i32)
...
---
name: i32_to_i64
@@ -56,8 +56,8 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
- %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))
- $x0 = COPY %2(s64)
+ %2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (s32))
+ $x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
...
@@ -78,8 +78,8 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
- %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s16))
- $x0 = COPY %2(s64)
+ %2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (s16))
+ $x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
...
@@ -100,8 +100,8 @@ body: |
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
- %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s8))
- $x0 = COPY %2(s64)
+ %2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ $x0 = COPY %2(i64)
RET_ReallyLR implicit $x0
...
@@ -121,8 +121,8 @@ body: |
; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
- $w0 = COPY %2(s32)
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -142,8 +142,8 @@ body: |
; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
- $w0 = COPY %2(s32)
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load (s16))
+ $w0 = COPY %2(i32)
RET_ReallyLR implicit $w0
...
@@ -164,7 +164,7 @@ body: |
; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load unordered (s8))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load unordered (s8))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -186,7 +186,7 @@ body: |
; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s8))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s8))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -208,7 +208,7 @@ body: |
; CHECK-NEXT: $w0 = COPY [[LDARB]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load acquire (s8))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load acquire (s8))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -230,7 +230,7 @@ body: |
; CHECK-NEXT: $w0 = COPY [[LDARB]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s8))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s8))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -252,7 +252,7 @@ body: |
; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load unordered (s16))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load unordered (s16))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -274,7 +274,7 @@ body: |
; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s16))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s16))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -296,7 +296,7 @@ body: |
; CHECK-NEXT: $w0 = COPY [[LDARH]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load acquire (s16))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load acquire (s16))
$w0 = COPY %2
RET_ReallyLR implicit $w0
@@ -318,7 +318,7 @@ body: |
; CHECK-NEXT: $w0 = COPY [[LDARH]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
- %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s16))
+ %2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s16))
$w0 = COPY %2
RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir b/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
index 47fc19bdc1440..8e8e5dbcbdc49 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
@@ -79,16 +79,16 @@ body: |
%2:gpr(p0) = G_LOAD %1(p0) :: (dereferenceable load (p0) from %ir.ptr.addr)
%15:gpr64(p0) = ADRP target-flags(aarch64-page) @x
%4:gpr(p0) = G_ADD_LOW %15(p0), target-flags(aarch64-pageoff, aarch64-nc) @x
- %3:gpr(s32) = G_LOAD %4(p0) :: (dereferenceable load (s32) from @x)
- %5:gpr(s32) = G_CONSTANT i32 32768
- %6:gpr(s32) = nsw G_SUB %3, %5
- %16:gpr(s64) = G_ANYEXT %6(s32)
- %8:gpr(s64) = G_SEXT_INREG %16, 16
- %14:gpr(s64) = G_CONSTANT i64 2
- %10:gpr(s64) = G_SHL %8, %14(s64)
- %11:gpr(p0) = G_PTR_ADD %2, %10(s64)
- %13:gpr(s32) = G_LOAD %11(p0) :: (load (s32) from %ir.arrayidx)
- $w0 = COPY %13(s32)
+ %3:gpr(i32) = G_LOAD %4(p0) :: (dereferenceable load (s32) from @x)
+ %5:gpr(i32) = G_CONSTANT i32 32768
+ %6:gpr(i32) = nsw G_SUB %3, %5
+ %16:gpr(i64) = G_ANYEXT %6(i32)
+ %8:gpr(i64) = G_SEXT_INREG %16, 16
+ %14:gpr(i64) = G_CONSTANT i64 2
+ %10:gpr(i64) = G_SHL %8, %14(i64)
+ %11:gpr(p0) = G_PTR_ADD %2, %10(i64)
+ %13:gpr(i32) = G_LOAD %11(p0) :: (load (s32) from %ir.arrayidx)
+ $w0 = COPY %13(i32)
RET_ReallyLR implicit $w0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll b/llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll
index b1166e683ec74..67f47c26ccd7e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll
@@ -342,3 +342,16 @@ define void @invalid_zero_offset_no_merge(i64 %0) {
store i32 0, ptr getelementptr inbounds ([10 x i32], ptr @G, i64 0, i64 1), align 4
ret void
}
+
+define void @mismatching_types_i16f16(ptr %ptr) {
+; CHECK-LABEL: mismatching_types_i16f16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov w8, #4 ; =0x4
+; CHECK-NEXT: strh wzr, [x0, #2]
+; CHECK-NEXT: strh w8, [x0]
+; CHECK-NEXT: ret
+ store i16 4, ptr %ptr
+ %addr2 = getelementptr i16, ptr %ptr, i64 1
+ store half 0.0, ptr %addr2
+ ret void
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
index d688561dc0fd0..34162ac4ea265 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
@@ -27,9 +27,9 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %negative_one:gpr(s64) = G_CONSTANT i64 -1
- %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy(s64), %negative_one
+ %copy:gpr(i64) = COPY $x0
+ %negative_one:gpr(i64) = G_CONSTANT i64 -1
+ %cmp:gpr(i32) = G_ICMP intpred(sgt), %copy(i64), %negative_one
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -56,9 +56,9 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s32) = COPY $w0
- %negative_one:gpr(s32) = G_CONSTANT i32 -1
- %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy(s32), %negative_one
+ %copy:gpr(i32) = COPY $w0
+ %negative_one:gpr(i32) = G_CONSTANT i32 -1
+ %cmp:gpr(i32) = G_ICMP intpred(sgt), %copy(i32), %negative_one
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -86,9 +86,9 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s32) = COPY $w0
- %one:gpr(s32) = G_CONSTANT i32 1
- %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy(s32), %one
+ %copy:gpr(i32) = COPY $w0
+ %one:gpr(i32) = G_CONSTANT i32 1
+ %cmp:gpr(i32) = G_ICMP intpred(sgt), %copy(i32), %one
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -117,12 +117,12 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %bit:gpr(s64) = G_CONSTANT i64 8
- %negative_one:gpr(s64) = G_CONSTANT i64 -1
- %c:gpr(s64) = G_CONSTANT i64 8
- %and:gpr(s64) = G_AND %copy, %bit
- %cmp:gpr(s32) = G_ICMP intpred(sgt), %and(s64), %negative_one
+ %copy:gpr(i64) = COPY $x0
+ %bit:gpr(i64) = G_CONSTANT i64 8
+ %negative_one:gpr(i64) = G_CONSTANT i64 -1
+ %c:gpr(i64) = G_CONSTANT i64 8
+ %and:gpr(i64) = G_AND %copy, %bit
+ %cmp:gpr(i32) = G_ICMP intpred(sgt), %and(i64), %negative_one
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
@@ -151,9 +151,9 @@ body: |
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
- %copy:gpr(s64) = COPY $x0
- %negative_one:gpr(s64) = G_CONSTANT i64 -1
- %cmp:gpr(s32) = G_ICMP intpred(sgt), %negative_one, %copy(s64)
+ %copy:gpr(i64) = COPY $x0
+ %negative_one:gpr(i64) = G_CONSTANT i64 -1
+ %cmp:gpr(i32) = G_ICMP intpred(sgt), %negative_one, %copy(i64)
G_BRCOND %cmp, %bb.1
G_BR %bb.0
bb.1:
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll b/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
index 22f89a78c6eeb..bccb70ccd5c03 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
@@ -10,10 +10,9 @@ define ptr @memset_tagged_0_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_0_zeroval:
; GISel-O0: // %bb.0: // %entry
; GISel-O0-NEXT: mov x8, xzr
-; GISel-O0-NEXT: mov x9, xzr
-; GISel-O0-NEXT: setgp [x0]!, x8!, x9
-; GISel-O0-NEXT: setgm [x0]!, x8!, x9
-; GISel-O0-NEXT: setge [x0]!, x8!, x9
+; GISel-O0-NEXT: setgp [x0]!, x8!, x8
+; GISel-O0-NEXT: setgm [x0]!, x8!, x8
+; GISel-O0-NEXT: setge [x0]!, x8!, x8
; GISel-O0-NEXT: ret
;
; GISel-LABEL: memset_tagged_0_zeroval:
@@ -39,7 +38,7 @@ entry:
define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_1_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #1 // =0x1
+; GISel-O0-NEXT: mov w8, #1
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
@@ -49,7 +48,7 @@ define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
;
; GISel-LABEL: memset_tagged_1_zeroval:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #1 // =0x1
+; GISel-NEXT: mov w8, #1
; GISel-NEXT: setgp [x0]!, x8!, xzr
; GISel-NEXT: setgm [x0]!, x8!, xzr
; GISel-NEXT: setge [x0]!, x8!, xzr
@@ -57,7 +56,7 @@ define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
;
; SDAG-LABEL: memset_tagged_1_zeroval:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #1 // =0x1
+; SDAG-NEXT: mov w8, #1
; SDAG-NEXT: setgp [x0]!, x8!, xzr
; SDAG-NEXT: setgm [x0]!, x8!, xzr
; SDAG-NEXT: setge [x0]!, x8!, xzr
@@ -70,7 +69,7 @@ entry:
define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_10_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10 // =0xa
+; GISel-O0-NEXT: mov w8, #10
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
@@ -80,7 +79,7 @@ define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
;
; GISel-LABEL: memset_tagged_10_zeroval:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10 // =0xa
+; GISel-NEXT: mov w8, #10
; GISel-NEXT: setgp [x0]!, x8!, xzr
; GISel-NEXT: setgm [x0]!, x8!, xzr
; GISel-NEXT: setge [x0]!, x8!, xzr
@@ -88,7 +87,7 @@ define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
;
; SDAG-LABEL: memset_tagged_10_zeroval:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10 // =0xa
+; SDAG-NEXT: mov w8, #10
; SDAG-NEXT: setgp [x0]!, x8!, xzr
; SDAG-NEXT: setgm [x0]!, x8!, xzr
; SDAG-NEXT: setge [x0]!, x8!, xzr
@@ -101,7 +100,7 @@ entry:
define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_10000_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10000 // =0x2710
+; GISel-O0-NEXT: mov w8, #10000
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
@@ -111,7 +110,7 @@ define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
;
; GISel-LABEL: memset_tagged_10000_zeroval:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10000 // =0x2710
+; GISel-NEXT: mov w8, #10000
; GISel-NEXT: setgp [x0]!, x8!, xzr
; GISel-NEXT: setgm [x0]!, x8!, xzr
; GISel-NEXT: setge [x0]!, x8!, xzr
@@ -119,7 +118,7 @@ define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
;
; SDAG-LABEL: memset_tagged_10000_zeroval:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10000 // =0x2710
+; SDAG-NEXT: mov w8, #10000
; SDAG-NEXT: setgp [x0]!, x8!, xzr
; SDAG-NEXT: setgm [x0]!, x8!, xzr
; SDAG-NEXT: setge [x0]!, x8!, xzr
@@ -193,7 +192,7 @@ entry:
define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_1:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #1 // =0x1
+; GISel-O0-NEXT: mov w8, #1
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
@@ -204,7 +203,7 @@ define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
;
; GISel-LABEL: memset_tagged_1:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #1 // =0x1
+; GISel-NEXT: mov w8, #1
; GISel-NEXT: // kill: def $w2 killed $w2 def $x2
; GISel-NEXT: setgp [x0]!, x8!, x2
; GISel-NEXT: setgm [x0]!, x8!, x2
@@ -213,7 +212,7 @@ define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
;
; SDAG-LABEL: memset_tagged_1:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #1 // =0x1
+; SDAG-NEXT: mov w8, #1
; SDAG-NEXT: // kill: def $w2 killed $w2 def $x2
; SDAG-NEXT: setgp [x0]!, x8!, x2
; SDAG-NEXT: setgm [x0]!, x8!, x2
@@ -228,7 +227,7 @@ entry:
define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_10:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10 // =0xa
+; GISel-O0-NEXT: mov w8, #10
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
@@ -239,7 +238,7 @@ define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
;
; GISel-LABEL: memset_tagged_10:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10 // =0xa
+; GISel-NEXT: mov w8, #10
; GISel-NEXT: // kill: def $w2 killed $w2 def $x2
; GISel-NEXT: setgp [x0]!, x8!, x2
; GISel-NEXT: setgm [x0]!, x8!, x2
@@ -248,7 +247,7 @@ define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
;
; SDAG-LABEL: memset_tagged_10:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10 // =0xa
+; SDAG-NEXT: mov w8, #10
; SDAG-NEXT: // kill: def $w2 killed $w2 def $x2
; SDAG-NEXT: setgp [x0]!, x8!, x2
; SDAG-NEXT: setgm [x0]!, x8!, x2
@@ -263,7 +262,7 @@ entry:
define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_10000:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov w8, #10000 // =0x2710
+; GISel-O0-NEXT: mov w8, #10000
; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
@@ -274,7 +273,7 @@ define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
;
; GISel-LABEL: memset_tagged_10000:
; GISel: // %bb.0: // %entry
-; GISel-NEXT: mov w8, #10000 // =0x2710
+; GISel-NEXT: mov w8, #10000
; GISel-NEXT: // kill: def $w2 killed $w2 def $x2
; GISel-NEXT: setgp [x0]!, x8!, x2
; GISel-NEXT: setgm [x0]!, x8!, x2
@@ -283,7 +282,7 @@ define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
;
; SDAG-LABEL: memset_tagged_10000:
; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: mov w8, #10000 // =0x2710
+; SDAG-NEXT: mov w8, #10000
; SDAG-NEXT: // kill: def $w2 killed $w2 def $x2
; SDAG-NEXT: setgp [x0]!, x8!, x2
; SDAG-NEXT: setgm [x0]!, x8!, x2
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
index 8f2eaaf860d81..2925b18dd4a1b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFPRCVT
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT,CHECK-SD-FPRCVT
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sme,+neon,+fullfp16,+fprcvt -force-streaming | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT,CHECK-SME
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sve,+neon,+fullfp16,+fprcvt -force-streaming-compatible | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT,CHECK-SVE
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT,CHECK-GI-FPRCVT
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFPRCVT
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sme,+neon,+fullfp16,+fprcvt -force-streaming | FileCheck %s --check-prefixes=CHECK-SME
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sve,+neon,+fullfp16,+fprcvt -force-streaming-compatible | FileCheck %s --check-prefixes=CHECK-SVE
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK
;
; FPTOI
@@ -16,10 +16,20 @@ define float @test_fptosi_f16_i32_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: test_fptosi_f16_i32_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: test_fptosi_f16_i32_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f16_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f16_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, h0
+; CHECK-SVE-NEXT: ret
%r = fptosi half %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -32,10 +42,20 @@ define double @test_fptosi_f16_i64_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: test_fptosi_f16_i64_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: test_fptosi_f16_i64_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f16_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f16_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, h0
+; CHECK-SVE-NEXT: ret
%r = fptosi half %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -48,10 +68,20 @@ define float @test_fptosi_f64_i32_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: test_fptosi_f64_i32_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: test_fptosi_f64_i32_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f64_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f64_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, d0
+; CHECK-SVE-NEXT: ret
%r = fptosi double %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -64,20 +94,45 @@ define double @test_fptosi_f32_i64_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: test_fptosi_f32_i64_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: test_fptosi_f32_i64_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f32_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f32_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, s0
+; CHECK-SVE-NEXT: ret
%r = fptosi float %a to i64
%bc = bitcast i64 %r to double
ret double %bc
}
define double @test_fptosi_f64_i64_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i64_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: test_fptosi_f64_i64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f64_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f64_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, d0
+; CHECK-SVE-NEXT: ret
%r = fptosi double %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -85,10 +140,25 @@ define double @test_fptosi_f64_i64_simd(double %a) {
define float @test_fptosi_f32_i32_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i32_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: test_fptosi_f32_i32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f32_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f32_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, s0
+; CHECK-SVE-NEXT: ret
%r = fptosi float %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -101,10 +171,20 @@ define float @test_fptoui_f16_i32_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: test_fptoui_f16_i32_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: test_fptoui_f16_i32_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f16_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f16_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, h0
+; CHECK-SVE-NEXT: ret
%r = fptoui half %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -117,10 +197,20 @@ define double @test_fptoui_f16_i64_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: test_fptoui_f16_i64_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: test_fptoui_f16_i64_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f16_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f16_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, h0
+; CHECK-SVE-NEXT: ret
%r = fptoui half %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -133,10 +223,20 @@ define float @test_fptoui_f64_i32_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: test_fptoui_f64_i32_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: test_fptoui_f64_i32_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f64_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f64_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, d0
+; CHECK-SVE-NEXT: ret
%r = fptoui double %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -149,20 +249,45 @@ define double @test_fptoui_f32_i64_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: test_fptoui_f32_i64_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: test_fptoui_f32_i64_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f32_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f32_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, s0
+; CHECK-SVE-NEXT: ret
%r = fptoui float %a to i64
%bc = bitcast i64 %r to double
ret double %bc
}
define double @test_fptoui_f64_i64_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i64_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: test_fptoui_f64_i64_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f64_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f64_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, d0
+; CHECK-SVE-NEXT: ret
%r = fptoui double %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -170,10 +295,25 @@ define double @test_fptoui_f64_i64_simd(double %a) {
define float @test_fptoui_f32_i32_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i32_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: test_fptoui_f32_i32_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f32_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f32_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, s0
+; CHECK-SVE-NEXT: ret
%r = fptoui float %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -191,10 +331,20 @@ define double @fcvtas_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtas_ds_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtas d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtas_ds_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -208,10 +358,20 @@ define float @fcvtas_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtas_sd_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtas s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtas_sd_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -219,10 +379,25 @@ define float @fcvtas_sd_round_simd(double %a) {
}
define float @fcvtas_ss_round_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtas_ss_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtas_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -230,10 +405,25 @@ define float @fcvtas_ss_round_simd(float %a) {
}
define double @fcvtas_dd_round_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtas_dd_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtas_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -248,10 +438,20 @@ define double @fcvtau_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtau_ds_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtau d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtau_ds_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -265,10 +465,20 @@ define float @fcvtau_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtau_sd_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtau s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtau_sd_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -276,10 +486,25 @@ define float @fcvtau_sd_round_simd(double %a) {
}
define float @fcvtau_ss_round_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtau_ss_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtau_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -287,10 +512,25 @@ define float @fcvtau_ss_round_simd(float %a) {
}
define double @fcvtau_dd_round_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtau_dd_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtau_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -304,10 +544,20 @@ define double @fcvtns_ds_roundeven_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtns_ds_roundeven_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtns d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtns_ds_roundeven_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_ds_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_ds_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -321,10 +571,20 @@ define float @fcvtns_sd_roundeven_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtns_sd_roundeven_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtns s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtns_sd_roundeven_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_sd_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_sd_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -332,10 +592,25 @@ define float @fcvtns_sd_roundeven_simd(double %a) {
}
define float @fcvtns_ss_roundeven_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtns_ss_roundeven_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtns s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtns_ss_roundeven_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_ss_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_ss_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -343,10 +618,25 @@ define float @fcvtns_ss_roundeven_simd(float %a) {
}
define double @fcvtns_dd_roundeven_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtns_dd_roundeven_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtns d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtns_dd_roundeven_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_dd_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_dd_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -361,10 +651,20 @@ define double @fcvtnu_ds_roundeven_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtnu_ds_roundeven_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtnu d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtnu_ds_roundeven_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_ds_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_ds_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -378,10 +678,20 @@ define float @fcvtnu_sd_roundeven_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtnu_sd_roundeven_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtnu s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtnu_sd_roundeven_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_sd_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_sd_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -389,10 +699,25 @@ define float @fcvtnu_sd_roundeven_simd(double %a) {
}
define float @fcvtnu_ss_roundeven_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtnu_ss_roundeven_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtnu s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtnu_ss_roundeven_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_ss_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_ss_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptoui float %r to i32
%bc = bitcast i32 %i to float
@@ -400,10 +725,25 @@ define float @fcvtnu_ss_roundeven_simd(float %a) {
}
define double @fcvtnu_dd_roundeven_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtnu_dd_roundeven_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtnu d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtnu_dd_roundeven_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_dd_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_dd_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptoui double %r to i64
%bc = bitcast i64 %i to double
@@ -417,10 +757,20 @@ define double @fcvtms_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtms_ds_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtms d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtms_ds_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -434,10 +784,20 @@ define float @fcvtms_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtms_sd_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtms s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtms_sd_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -445,10 +805,25 @@ define float @fcvtms_sd_round_simd(double %a) {
}
define float @fcvtms_ss_round_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtms_ss_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtms_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -456,10 +831,25 @@ define float @fcvtms_ss_round_simd(float %a) {
}
define double @fcvtms_dd_round_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtms_dd_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtms_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -475,10 +865,20 @@ define double @fcvtmu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtmu_ds_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtmu d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtmu_ds_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -492,10 +892,20 @@ define float @fcvtmu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtmu_sd_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtmu s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtmu_sd_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -503,10 +913,25 @@ define float @fcvtmu_sd_round_simd(double %a) {
}
define float @fcvtmu_ss_round_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtmu_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -514,10 +939,25 @@ define float @fcvtmu_ss_round_simd(float %a) {
}
define double @fcvtmu_dd_round_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtmu_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -532,10 +972,20 @@ define double @fcvtps_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtps_ds_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtps d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtps_ds_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -549,10 +999,20 @@ define float @fcvtps_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtps_sd_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtps s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtps_sd_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -560,10 +1020,25 @@ define float @fcvtps_sd_round_simd(double %a) {
}
define float @fcvtps_ss_round_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtps_ss_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtps_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -571,10 +1046,25 @@ define float @fcvtps_ss_round_simd(float %a) {
}
define double @fcvtps_dd_round_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtps_dd_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtps_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -589,10 +1079,20 @@ define double @fcvtpu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtpu_ds_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtpu d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtpu_ds_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -606,10 +1106,20 @@ define float @fcvtpu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtpu_sd_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtpu s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtpu_sd_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -617,10 +1127,25 @@ define float @fcvtpu_sd_round_simd(double %a) {
}
define float @fcvtpu_ss_round_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtpu_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -628,10 +1153,25 @@ define float @fcvtpu_ss_round_simd(float %a) {
}
define double @fcvtpu_dd_round_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtpu_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -646,10 +1186,20 @@ define double @fcvtzs_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzs_ds_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzs_ds_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -663,10 +1213,20 @@ define float @fcvtzs_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzs_sd_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzs_sd_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -674,10 +1234,25 @@ define float @fcvtzs_sd_round_simd(double %a) {
}
define float @fcvtzs_ss_round_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzs_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -685,10 +1260,25 @@ define float @fcvtzs_ss_round_simd(float %a) {
}
define double @fcvtzs_dd_round_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzs_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -702,10 +1292,20 @@ define double @fcvtzu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzu_ds_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzu_ds_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -719,10 +1319,20 @@ define float @fcvtzu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzu_sd_round_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzu_sd_round_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -730,10 +1340,25 @@ define float @fcvtzu_sd_round_simd(double %a) {
}
define float @fcvtzu_ss_round_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzu_ss_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -741,10 +1366,25 @@ define float @fcvtzu_ss_round_simd(float %a) {
}
define double @fcvtzu_dd_round_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_round_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzu_dd_round_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -763,10 +1403,20 @@ define float @fcvtzs_sh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzs_sh_sat_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzs_sh_sat_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_sh_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_sh_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, h0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f16(half %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -779,10 +1429,20 @@ define double @fcvtzs_dh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzs_dh_sat_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzs_dh_sat_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_dh_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_dh_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, h0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f16(half %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -795,10 +1455,20 @@ define double @fcvtzs_ds_sat_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzs_ds_sat_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzs_ds_sat_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ds_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ds_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, s0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f32(float %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -811,30 +1481,70 @@ define float @fcvtzs_sd_sat_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzs_sd_sat_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzs_sd_sat_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_sd_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_sd_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, d0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f64(double %a)
%bc = bitcast i32 %i to float
ret float %bc
}
define float @fcvtzs_ss_sat_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_sat_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzs_ss_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ss_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ss_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, s0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f32(float %a)
%bc = bitcast i32 %i to float
ret float %bc
}
define double @fcvtzs_dd_sat_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_sat_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzs_dd_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_dd_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_dd_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, d0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f64(double %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -847,10 +1557,20 @@ define float @fcvtzu_sh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzu_sh_sat_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzu_sh_sat_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_sh_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_sh_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, h0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptoui.sat.i32.f16(half %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -863,10 +1583,20 @@ define double @fcvtzu_dh_sat_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzu_dh_sat_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzu_dh_sat_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_dh_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_dh_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, h0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptoui.sat.i64.f16(half %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -879,10 +1609,20 @@ define double @fcvtzu_ds_sat_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzu_ds_sat_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzu_ds_sat_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ds_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ds_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, s0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptoui.sat.i64.f32(float %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -895,30 +1635,70 @@ define float @fcvtzu_sd_sat_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzu_sd_sat_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzu_sd_sat_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_sd_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_sd_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, d0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptoui.sat.i32.f64(double %a)
%bc = bitcast i32 %i to float
ret float %bc
}
define float @fcvtzu_ss_sat_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_sat_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzu_ss_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ss_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ss_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, s0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f32(float %a)
%bc = bitcast i32 %i to float
ret float %bc
}
define double @fcvtzu_dd_sat_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_sat_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzu_dd_sat_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_dd_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_dd_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, d0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f64(double %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -935,10 +1715,20 @@ define float @fcvtas_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtas_sh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtas s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtas_sh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -952,10 +1742,20 @@ define double @fcvtas_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtas_dh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtas d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtas_dh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -969,10 +1769,20 @@ define double @fcvtas_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtas_ds_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtas d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtas_ds_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -986,10 +1796,20 @@ define float @fcvtas_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtas_sd_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtas s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtas_sd_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -997,10 +1817,25 @@ define float @fcvtas_sd_simd(double %a) {
}
define float @fcvtas_ss_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtas_ss_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtas_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1008,10 +1843,25 @@ define float @fcvtas_ss_simd(float %a) {
}
define double @fcvtas_dd_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtas_dd_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtas_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1025,10 +1875,20 @@ define float @fcvtau_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtau_sh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtau s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtau_sh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1042,10 +1902,20 @@ define double @fcvtau_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtau_dh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtau d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtau_dh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1059,10 +1929,20 @@ define double @fcvtau_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtau_ds_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtau d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtau_ds_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1076,10 +1956,20 @@ define float @fcvtau_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtau_sd_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtau s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtau_sd_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1087,10 +1977,25 @@ define float @fcvtau_sd_simd(double %a) {
}
define float @fcvtau_ss_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtau_ss_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtau_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1098,10 +2003,25 @@ define float @fcvtau_ss_simd(float %a) {
}
define double @fcvtau_dd_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtau_dd_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtau_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1115,10 +2035,20 @@ define float @fcvtns_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtns_sh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtns s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtns_sh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1132,10 +2062,20 @@ define double @fcvtns_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtns_dh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtns d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtns_dh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1149,10 +2089,20 @@ define double @fcvtns_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtns_ds_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtns d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtns_ds_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1166,10 +2116,20 @@ define float @fcvtns_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtns_sd_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtns s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtns_sd_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1177,10 +2137,25 @@ define float @fcvtns_sd_simd(double %a) {
}
define float @fcvtns_ss_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtns_ss_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtns s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtns_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1188,10 +2163,25 @@ define float @fcvtns_ss_simd(float %a) {
}
define double @fcvtns_dd_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtns_dd_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtns d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtns_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1205,10 +2195,20 @@ define float @fcvtnu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtnu_sh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtnu s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtnu_sh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1222,10 +2222,20 @@ define double @fcvtnu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtnu_dh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtnu d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtnu_dh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1239,10 +2249,20 @@ define double @fcvtnu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtnu_ds_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtnu d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtnu_ds_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1256,10 +2276,20 @@ define float @fcvtnu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtnu_sd_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtnu s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtnu_sd_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1267,10 +2297,25 @@ define float @fcvtnu_sd_simd(double %a) {
}
define float @fcvtnu_ss_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtnu_ss_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtnu s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtnu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1278,10 +2323,25 @@ define float @fcvtnu_ss_simd(float %a) {
}
define double @fcvtnu_dd_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtnu_dd_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtnu d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtnu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1295,10 +2355,20 @@ define float @fcvtms_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtms_sh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtms s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtms_sh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1312,10 +2382,20 @@ define double @fcvtms_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtms_dh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtms d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtms_dh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1329,10 +2409,20 @@ define double @fcvtms_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtms_ds_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtms d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtms_ds_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1346,10 +2436,20 @@ define float @fcvtms_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtms_sd_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtms s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtms_sd_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1357,10 +2457,25 @@ define float @fcvtms_sd_simd(double %a) {
}
define float @fcvtms_ss_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtms_ss_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtms_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1368,10 +2483,25 @@ define float @fcvtms_ss_simd(float %a) {
}
define double @fcvtms_dd_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtms_dd_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtms_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1385,10 +2515,20 @@ define float @fcvtmu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtmu_sh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtmu s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtmu_sh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1402,10 +2542,20 @@ define double @fcvtmu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtmu_dh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtmu d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtmu_dh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1419,10 +2569,20 @@ define double @fcvtmu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtmu_ds_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtmu d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtmu_ds_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1436,10 +2596,20 @@ define float @fcvtmu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtmu_sd_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtmu s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtmu_sd_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1447,10 +2617,25 @@ define float @fcvtmu_sd_simd(double %a) {
}
define float @fcvtmu_ss_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtmu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1458,10 +2643,25 @@ define float @fcvtmu_ss_simd(float %a) {
}
define double @fcvtmu_dd_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtmu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1475,10 +2675,20 @@ define float @fcvtps_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtps_sh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtps s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtps_sh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1492,10 +2702,20 @@ define double @fcvtps_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtps_dh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtps d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtps_dh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1509,10 +2729,20 @@ define double @fcvtps_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtps_ds_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtps d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtps_ds_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1526,10 +2756,20 @@ define float @fcvtps_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtps_sd_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtps s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtps_sd_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1537,10 +2777,25 @@ define float @fcvtps_sd_simd(double %a) {
}
define float @fcvtps_ss_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtps_ss_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtps_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1548,10 +2803,25 @@ define float @fcvtps_ss_simd(float %a) {
}
define double @fcvtps_dd_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtps_dd_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtps_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1565,10 +2835,20 @@ define float @fcvtpu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtpu_sh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtpu s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtpu_sh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1582,10 +2862,20 @@ define double @fcvtpu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtpu_dh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtpu d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtpu_dh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1599,10 +2889,20 @@ define double @fcvtpu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtpu_ds_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtpu d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtpu_ds_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1616,10 +2916,20 @@ define float @fcvtpu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtpu_sd_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtpu s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtpu_sd_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1627,10 +2937,25 @@ define float @fcvtpu_sd_simd(double %a) {
}
define float @fcvtpu_ss_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtpu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1638,10 +2963,25 @@ define float @fcvtpu_ss_simd(float %a) {
}
define double @fcvtpu_dd_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtpu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1655,10 +2995,20 @@ define float @fcvtzs_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzs_sh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzs_sh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1672,10 +3022,20 @@ define double @fcvtzs_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzs_dh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzs_dh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1689,10 +3049,20 @@ define double @fcvtzs_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzs_ds_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzs_ds_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1706,10 +3076,20 @@ define float @fcvtzs_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzs_sd_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzs_sd_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1717,10 +3097,25 @@ define float @fcvtzs_sd_simd(double %a) {
}
define float @fcvtzs_ss_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzs_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1728,10 +3123,25 @@ define float @fcvtzs_ss_simd(float %a) {
}
define double @fcvtzs_dd_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzs_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1745,10 +3155,20 @@ define float @fcvtzu_sh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzu_sh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu s0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzu_sh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1762,10 +3182,20 @@ define double @fcvtzu_dh_simd(half %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzu_dh_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu d0, h0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzu_dh_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, h0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1779,10 +3209,20 @@ define double @fcvtzu_ds_simd(float %a) {
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzu_ds_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu d0, s0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzu_ds_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu d0, s0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1796,10 +3236,20 @@ define float @fcvtzu_sd_simd(double %a) {
; CHECK-NOFPRCVT-NEXT: fmov s0, w8
; CHECK-NOFPRCVT-NEXT: ret
;
-; CHECK-FPRCVT-LABEL: fcvtzu_sd_simd:
-; CHECK-FPRCVT: // %bb.0:
-; CHECK-FPRCVT-NEXT: fcvtzu s0, d0
-; CHECK-FPRCVT-NEXT: ret
+; CHECK-LABEL: fcvtzu_sd_simd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu s0, d0
+; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1807,10 +3257,25 @@ define float @fcvtzu_sd_simd(double %a) {
}
define float @fcvtzu_ss_simd(float %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzu_ss_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1818,17 +3283,27 @@ define float @fcvtzu_ss_simd(float %a) {
}
define double @fcvtzu_dd_simd(double %a) {
+; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_simd:
+; CHECK-NOFPRCVT: // %bb.0:
+; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
+; CHECK-NOFPRCVT-NEXT: ret
+;
; CHECK-LABEL: fcvtzu_dd_simd:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
ret double %bc
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-GI-FPRCVT: {{.*}}
-; CHECK-SD-FPRCVT: {{.*}}
-; CHECK-SME: {{.*}}
-; CHECK-SVE: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/arm64-fp128.ll b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
index 42ff4bdfc1d3e..c4f91c66fb9a6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
@@ -302,8 +302,10 @@ define fp128 @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
; CHECK-GI-NEXT: tst w8, #0x1
; CHECK-GI-NEXT: fcsel d0, d0, d1, ne
; CHECK-GI-NEXT: fcsel d1, d2, d3, ne
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d1
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: ret
%val = select i1 %cond, fp128 %lhs, fp128 %rhs
ret fp128 %val
@@ -1154,14 +1156,18 @@ define <2 x fp128> @vec_select(<2 x i1> %cond, <2 x fp128> %lhs, <2 x fp128> %rh
; CHECK-GI-NEXT: fcsel d0, d1, d3, ne
; CHECK-GI-NEXT: fcsel d3, d5, d6, ne
; CHECK-GI-NEXT: tst w8, #0x1
-; CHECK-GI-NEXT: mov d5, v2.d[1]
-; CHECK-GI-NEXT: mov d6, v4.d[1]
-; CHECK-GI-NEXT: fcsel d1, d2, d4, ne
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
-; CHECK-GI-NEXT: fcsel d2, d5, d6, ne
-; CHECK-GI-NEXT: mov v0.d[1], v3.d[0]
-; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
+; CHECK-GI-NEXT: mov d1, v2.d[1]
+; CHECK-GI-NEXT: mov d5, v4.d[1]
+; CHECK-GI-NEXT: fcsel d2, d2, d4, ne
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d2
+; CHECK-GI-NEXT: fcsel d2, d1, d5, ne
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d3
+; CHECK-GI-NEXT: mov v1.d[0], x9
+; CHECK-GI-NEXT: fmov x9, d2
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v1.d[1], x9
; CHECK-GI-NEXT: ret
%val = select <2 x i1> %cond, <2 x fp128> %lhs, <2 x fp128> %rhs
ret <2 x fp128> %val
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index 8d2980a922593..4f3666c58d317 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -2,6 +2,11 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; CHECK-GI: warning: Instruction selection used fallback path for test_bitcastv2f32tov1f64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_bitcastv1f64tov2f32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_v1i32_undef
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_diff_v1i32_v1i32
+
define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
; CHECK-LABEL: ins16bw:
; CHECK: // %bb.0:
diff --git a/llvm/test/CodeGen/AArch64/arm64-smaxv.ll b/llvm/test/CodeGen/AArch64/arm64-smaxv.ll
index 981c4d2aeecbb..1bed8df916ea2 100644
--- a/llvm/test/CodeGen/AArch64/arm64-smaxv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-smaxv.ll
@@ -1,12 +1,11 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
; RUN: llc < %s -global-isel=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define signext i8 @test_vmaxv_s8(<8 x i8> %a1) {
-; CHECK-LABEL: test_vmaxv_s8:
-; CHECK: smaxv.8b b0, v0
-; CHECK-NEXT: smov.b w0, v0[0]
-; CHECK-NEXT: ret
+; CHECK: test_vmaxv_s8
+; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
+; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
%0 = trunc i32 %vmaxv.i to i8
@@ -14,10 +13,10 @@ entry:
}
define signext i16 @test_vmaxv_s16(<4 x i16> %a1) {
-; CHECK-LABEL: test_vmaxv_s16:
-; CHECK: smaxv.4h h0, v0
-; CHECK-NEXT: smov.h w0, v0[0]
-; CHECK-NEXT: ret
+; CHECK: test_vmaxv_s16
+; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
+; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a1)
%0 = trunc i32 %vmaxv.i to i16
@@ -25,21 +24,21 @@ entry:
}
define i32 @test_vmaxv_s32(<2 x i32> %a1) {
-; CHECK-LABEL: test_vmaxv_s32:
-; CHECK: smaxp.2s v0, v0, v0
-; CHECK-NEXT: fmov w0, s0
-; CHECK-NEXT: ret
+; CHECK: test_vmaxv_s32
; 2 x i32 is not supported by the ISA, thus, this is a special case
+; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v0, v0
+; CHECK-NEXT: fmov w0, s[[REGNUM]]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a1)
ret i32 %vmaxv.i
}
define signext i8 @test_vmaxvq_s8(<16 x i8> %a1) {
-; CHECK-LABEL: test_vmaxvq_s8:
-; CHECK: smaxv.16b b0, v0
-; CHECK-NEXT: smov.b w0, v0[0]
-; CHECK-NEXT: ret
+; CHECK: test_vmaxvq_s8
+; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
+; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a1)
%0 = trunc i32 %vmaxv.i to i8
@@ -47,10 +46,10 @@ entry:
}
define signext i16 @test_vmaxvq_s16(<8 x i16> %a1) {
-; CHECK-LABEL: test_vmaxvq_s16:
-; CHECK: smaxv.8h h0, v0
-; CHECK-NEXT: smov.h w0, v0[0]
-; CHECK-NEXT: ret
+; CHECK: test_vmaxvq_s16
+; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
+; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a1)
%0 = trunc i32 %vmaxv.i to i16
@@ -58,10 +57,10 @@ entry:
}
define i32 @test_vmaxvq_s32(<4 x i32> %a1) {
-; CHECK-LABEL: test_vmaxvq_s32:
-; CHECK: smaxv.4s s0, v0
-; CHECK-NEXT: fmov w0, s0
-; CHECK-NEXT: ret
+; CHECK: test_vmaxvq_s32
+; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v0
+; CHECK-NEXT: fmov w0, [[REGNUM]]
+; CHECK-NEXT: ret
entry:
%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a1)
ret i32 %vmaxv.i
@@ -69,9 +68,9 @@ entry:
define <8 x i8> @test_vmaxv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
; CHECK-LABEL: test_vmaxv_s8_used_by_laneop:
-; CHECK: smaxv.8b b1, v1
-; CHECK-NEXT: mov.b v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -81,9 +80,9 @@ entry:
define <4 x i16> @test_vmaxv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: test_vmaxv_s16_used_by_laneop:
-; CHECK: smaxv.4h h1, v1
-; CHECK-NEXT: mov.h v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -93,9 +92,9 @@ entry:
define <2 x i32> @test_vmaxv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
; CHECK-LABEL: test_vmaxv_s32_used_by_laneop:
-; CHECK: smaxp.2s v1, v1, v1
-; CHECK-NEXT: mov.s v0[1], v1[0]
-; CHECK-NEXT: ret
+; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v1, v1
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a2)
%1 = insertelement <2 x i32> %a1, i32 %0, i32 1
@@ -104,9 +103,9 @@ entry:
define <16 x i8> @test_vmaxvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
; CHECK-LABEL: test_vmaxvq_s8_used_by_laneop:
-; CHECK: smaxv.16b b1, v1
-; CHECK-NEXT: mov.b v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -116,9 +115,9 @@ entry:
define <8 x i16> @test_vmaxvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
; CHECK-LABEL: test_vmaxvq_s16_used_by_laneop:
-; CHECK: smaxv.8h h1, v1
-; CHECK-NEXT: mov.h v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -128,9 +127,9 @@ entry:
define <4 x i32> @test_vmaxvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
; CHECK-LABEL: test_vmaxvq_s32_used_by_laneop:
-; CHECK: smaxv.4s s1, v1
-; CHECK-NEXT: mov.s v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: smaxv.4s s[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a2)
%1 = insertelement <4 x i32> %a1, i32 %0, i32 3
diff --git a/llvm/test/CodeGen/AArch64/arm64-sminv.ll b/llvm/test/CodeGen/AArch64/arm64-sminv.ll
index 6d27249c32432..683044c9e8e0b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-sminv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-sminv.ll
@@ -1,12 +1,11 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
; RUN: llc < %s -global-isel=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
define signext i8 @test_vminv_s8(<8 x i8> %a1) {
-; CHECK-LABEL: test_vminv_s8:
-; CHECK: sminv.8b b0, v0
-; CHECK-NEXT: smov.b w0, v0[0]
-; CHECK-NEXT: ret
+; CHECK: test_vminv_s8
+; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
+; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)
%0 = trunc i32 %vminv.i to i8
@@ -14,10 +13,10 @@ entry:
}
define signext i16 @test_vminv_s16(<4 x i16> %a1) {
-; CHECK-LABEL: test_vminv_s16:
-; CHECK: sminv.4h h0, v0
-; CHECK-NEXT: smov.h w0, v0[0]
-; CHECK-NEXT: ret
+; CHECK: test_vminv_s16
+; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
+; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a1)
%0 = trunc i32 %vminv.i to i16
@@ -25,21 +24,21 @@ entry:
}
define i32 @test_vminv_s32(<2 x i32> %a1) {
-; CHECK-LABEL: test_vminv_s32:
-; CHECK: sminp.2s v0, v0, v0
-; CHECK-NEXT: fmov w0, s0
-; CHECK-NEXT: ret
+; CHECK: test_vminv_s32
; 2 x i32 is not supported by the ISA, thus, this is a special case
+; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
+; CHECK-NEXT: fmov w0, s[[REGNUM]]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a1)
ret i32 %vminv.i
}
define signext i8 @test_vminvq_s8(<16 x i8> %a1) {
-; CHECK-LABEL: test_vminvq_s8:
-; CHECK: sminv.16b b0, v0
-; CHECK-NEXT: smov.b w0, v0[0]
-; CHECK-NEXT: ret
+; CHECK: test_vminvq_s8
+; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
+; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a1)
%0 = trunc i32 %vminv.i to i8
@@ -47,10 +46,10 @@ entry:
}
define signext i16 @test_vminvq_s16(<8 x i16> %a1) {
-; CHECK-LABEL: test_vminvq_s16:
-; CHECK: sminv.8h h0, v0
-; CHECK-NEXT: smov.h w0, v0[0]
-; CHECK-NEXT: ret
+; CHECK: test_vminvq_s16
+; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
+; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a1)
%0 = trunc i32 %vminv.i to i16
@@ -58,10 +57,10 @@ entry:
}
define i32 @test_vminvq_s32(<4 x i32> %a1) {
-; CHECK-LABEL: test_vminvq_s32:
-; CHECK: sminv.4s s0, v0
-; CHECK-NEXT: fmov w0, s0
-; CHECK-NEXT: ret
+; CHECK: test_vminvq_s32
+; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
+; CHECK-NEXT: fmov w0, [[REGNUM]]
+; CHECK-NEXT: ret
entry:
%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a1)
ret i32 %vminv.i
@@ -69,9 +68,9 @@ entry:
define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
; CHECK-LABEL: test_vminv_s8_used_by_laneop:
-; CHECK: sminv.8b b1, v1
-; CHECK-NEXT: mov.b v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -81,9 +80,9 @@ entry:
define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: test_vminv_s16_used_by_laneop:
-; CHECK: sminv.4h h1, v1
-; CHECK-NEXT: mov.h v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -93,9 +92,9 @@ entry:
define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
; CHECK-LABEL: test_vminv_s32_used_by_laneop:
-; CHECK: sminp.2s v1, v1, v1
-; CHECK-NEXT: mov.s v0[1], v1[0]
-; CHECK-NEXT: ret
+; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)
%1 = insertelement <2 x i32> %a1, i32 %0, i32 1
@@ -104,9 +103,9 @@ entry:
define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
; CHECK-LABEL: test_vminvq_s8_used_by_laneop:
-; CHECK: sminv.16b b1, v1
-; CHECK-NEXT: mov.b v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)
%1 = trunc i32 %0 to i8
@@ -116,9 +115,9 @@ entry:
define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
; CHECK-LABEL: test_vminvq_s16_used_by_laneop:
-; CHECK: sminv.8h h1, v1
-; CHECK-NEXT: mov.h v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)
%1 = trunc i32 %0 to i16
@@ -128,9 +127,9 @@ entry:
define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
; CHECK-LABEL: test_vminvq_s32_used_by_laneop:
-; CHECK: sminv.4s s1, v1
-; CHECK-NEXT: mov.s v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ret
entry:
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)
%1 = insertelement <4 x i32> %a1, i32 %0, i32 3
diff --git a/llvm/test/CodeGen/AArch64/arm64-vaddv.ll b/llvm/test/CodeGen/AArch64/arm64-vaddv.ll
index 6d6484a584d81..d60b6d7097308 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vaddv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vaddv.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s
define signext i8 @test_vaddv_s8(<8 x i8> %a1) {
; CHECK-LABEL: test_vaddv_s8:
@@ -451,6 +451,3 @@ declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
declare float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)
declare float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)
declare double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-GI: {{.*}}
-; CHECK-SD: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/bf16-instructions.ll b/llvm/test/CodeGen/AArch64/bf16-instructions.ll
index ff180347447fe..1e9f955d3dd88 100644
--- a/llvm/test/CodeGen/AArch64/bf16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/bf16-instructions.ll
@@ -10,9 +10,6 @@
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_fmadd
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_fdiv
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_frem
-; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_call
-; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_call_flipped
-; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_tailcall_flipped
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_select_cc
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_select_cc_f32_f16
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_une
@@ -67,7 +64,6 @@
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_fabs
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_minnum
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_maxnum
-; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_copysign
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_copysign_f32
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_copysign_f64
; CHECK-CVT-GI-NEXT: warning: Instruction selection used fallback path for test_copysign_extended
@@ -86,9 +82,6 @@
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_fmadd
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_fdiv
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_frem
-; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_call
-; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_call_flipped
-; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_tailcall_flipped
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_select_cc
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_select_cc_f32_f16
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_fcmp_une
@@ -143,7 +136,6 @@
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_fabs
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_minnum
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_maxnum
-; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_copysign
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_copysign_f32
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_copysign_f64
; CHECK-BF16-GI-NEXT: warning: Instruction selection used fallback path for test_copysign_extended
@@ -1893,30 +1885,48 @@ define bfloat @test_maxnum(bfloat %a, bfloat %b) #0 {
}
define bfloat @test_copysign(bfloat %a, bfloat %b) #0 {
-; CHECK-CVT-LABEL: test_copysign:
-; CHECK-CVT: // %bb.0:
-; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-CVT-NEXT: mvni v2.4s, #128, lsl #24
-; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-CVT-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-CVT-NEXT: fmov w8, s0
-; CHECK-CVT-NEXT: lsr w8, w8, #16
-; CHECK-CVT-NEXT: fmov s0, w8
-; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 killed $s0
-; CHECK-CVT-NEXT: ret
+; CHECK-CVT-SD-LABEL: test_copysign:
+; CHECK-CVT-SD: // %bb.0:
+; CHECK-CVT-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-SD-NEXT: mvni v2.4s, #128, lsl #24
+; CHECK-CVT-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-CVT-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-CVT-SD-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-SD-NEXT: fmov w8, s0
+; CHECK-CVT-SD-NEXT: lsr w8, w8, #16
+; CHECK-CVT-SD-NEXT: fmov s0, w8
+; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-CVT-SD-NEXT: ret
;
-; CHECK-BF16-LABEL: test_copysign:
-; CHECK-BF16: // %bb.0:
-; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1
-; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-BF16-NEXT: mvni v2.4s, #128, lsl #24
-; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16
-; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-BF16-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-BF16-NEXT: bfcvt h0, s0
-; CHECK-BF16-NEXT: ret
+; CHECK-BF16-SD-LABEL: test_copysign:
+; CHECK-BF16-SD: // %bb.0:
+; CHECK-BF16-SD-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-BF16-SD-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-BF16-SD-NEXT: mvni v2.4s, #128, lsl #24
+; CHECK-BF16-SD-NEXT: shll v1.4s, v1.4h, #16
+; CHECK-BF16-SD-NEXT: shll v0.4s, v0.4h, #16
+; CHECK-BF16-SD-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-BF16-SD-NEXT: bfcvt h0, s0
+; CHECK-BF16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: test_copysign:
+; CHECK-CVT-GI: // %bb.0:
+; CHECK-CVT-GI-NEXT: mvni v2.4h, #128, lsl #8
+; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-CVT-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-CVT-GI-NEXT: bif v0.8b, v1.8b, v2.8b
+; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 killed $d0
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-BF16-GI-LABEL: test_copysign:
+; CHECK-BF16-GI: // %bb.0:
+; CHECK-BF16-GI-NEXT: mvni v2.4h, #128, lsl #8
+; CHECK-BF16-GI-NEXT: // kill: def $h0 killed $h0 def $d0
+; CHECK-BF16-GI-NEXT: // kill: def $h1 killed $h1 def $d1
+; CHECK-BF16-GI-NEXT: bif v0.8b, v1.8b, v2.8b
+; CHECK-BF16-GI-NEXT: // kill: def $h0 killed $h0 killed $d0
+; CHECK-BF16-GI-NEXT: ret
%r = call bfloat @llvm.copysign.bf16(bfloat %a, bfloat %b)
ret bfloat %r
}
diff --git a/llvm/test/CodeGen/AArch64/bitcast-extend.ll b/llvm/test/CodeGen/AArch64/bitcast-extend.ll
index b4c77aa76a9fa..e110a6e283989 100644
--- a/llvm/test/CodeGen/AArch64/bitcast-extend.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast-extend.ll
@@ -570,16 +570,11 @@ define <2 x float> @load_zext_i32_v2f32(ptr %p) {
}
define <1 x double> @load_zext_i8_v1f64(ptr %p) {
-; CHECK-SD-LABEL: load_zext_i8_v1f64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ldrb w8, [x0]
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: load_zext_i8_v1f64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr b0, [x0]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: load_zext_i8_v1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldrb w8, [x0]
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
%l = load i8, ptr %p
%z = zext i8 %l to i64
%b = bitcast i64 %z to <1 x double>
@@ -587,16 +582,11 @@ define <1 x double> @load_zext_i8_v1f64(ptr %p) {
}
define <1 x double> @load_zext_i16_v1f64(ptr %p) {
-; CHECK-SD-LABEL: load_zext_i16_v1f64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ldrh w8, [x0]
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: load_zext_i16_v1f64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr h0, [x0]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: load_zext_i16_v1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldrh w8, [x0]
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
%l = load i16, ptr %p
%z = zext i16 %l to i64
%b = bitcast i64 %z to <1 x double>
@@ -604,16 +594,11 @@ define <1 x double> @load_zext_i16_v1f64(ptr %p) {
}
define <1 x double> @load_zext_i32_v1f64(ptr %p) {
-; CHECK-SD-LABEL: load_zext_i32_v1f64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ldr w8, [x0]
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: load_zext_i32_v1f64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr s0, [x0]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: load_zext_i32_v1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr w8, [x0]
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
%l = load i32, ptr %p
%z = zext i32 %l to i64
%b = bitcast i64 %z to <1 x double>
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index 450a121d8b6a6..d360a9da7d966 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -31,15 +31,17 @@ define fp128 @f128_fp128(fp128 %a, fp128 %b, fp128 %d, fp128 %e) {
; CHECK-GI-NEXT: .cfi_offset w30, -16
; CHECK-GI-NEXT: stp q3, q2, [sp] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q3, q0, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q3, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: mov d2, v3.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d3, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d2, mi
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov d0, v2.d[1]
+; CHECK-GI-NEXT: mov d1, v3.d[1]
+; CHECK-GI-NEXT: fcsel d2, d2, d3, mi
+; CHECK-GI-NEXT: fmov x8, d2
+; CHECK-GI-NEXT: fcsel d1, d0, d1, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d1
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
entry:
@@ -475,17 +477,21 @@ define <2 x fp128> @v2f128_fp128(<2 x fp128> %a, <2 x fp128> %b, <2 x fp128> %d,
; CHECK-GI-NEXT: mov d0, v2.d[1]
; CHECK-GI-NEXT: mov d1, v3.d[1]
; CHECK-GI-NEXT: fcsel d2, d2, d3, mi
+; CHECK-GI-NEXT: fmov x8, d2
; CHECK-GI-NEXT: fcsel d3, d0, d1, mi
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q5, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d4, v0.d[1]
-; CHECK-GI-NEXT: mov d5, v1.d[1]
-; CHECK-GI-NEXT: fcsel d1, d0, d1, mi
-; CHECK-GI-NEXT: mov v0.d[0], v2.d[0]
-; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
-; CHECK-GI-NEXT: fcsel d2, d4, d5, mi
-; CHECK-GI-NEXT: mov v0.d[1], v3.d[0]
-; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: mov d4, v5.d[1]
+; CHECK-GI-NEXT: fcsel d0, d0, d5, mi
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d3
+; CHECK-GI-NEXT: fcsel d2, d1, d4, mi
+; CHECK-GI-NEXT: mov v1.d[0], x9
+; CHECK-GI-NEXT: fmov x9, d2
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v1.d[1], x9
; CHECK-GI-NEXT: add sp, sp, #112
; CHECK-GI-NEXT: ret
entry:
@@ -568,23 +574,29 @@ define <3 x fp128> @v3f128_fp128(<3 x fp128> %a, <3 x fp128> %b, <3 x fp128> %d,
; CHECK-GI-NEXT: fcsel d4, d4, d5, mi
; CHECK-GI-NEXT: mov d2, v7.d[1]
; CHECK-GI-NEXT: mov d3, v6.d[1]
+; CHECK-GI-NEXT: fmov x8, d4
; CHECK-GI-NEXT: fcsel d5, d0, d1, mi
; CHECK-GI-NEXT: cmp w20, #0
-; CHECK-GI-NEXT: fcsel d3, d2, d3, mi
-; CHECK-GI-NEXT: ldp q2, q0, [sp, #128] // 32-byte Folded Reload
; CHECK-GI-NEXT: fcsel d1, d7, d6, mi
+; CHECK-GI-NEXT: ldp q7, q0, [sp, #128] // 32-byte Folded Reload
+; CHECK-GI-NEXT: fcsel d3, d2, d3, mi
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
-; CHECK-GI-NEXT: mov d6, v0.d[1]
-; CHECK-GI-NEXT: mov d7, v2.d[1]
-; CHECK-GI-NEXT: fcsel d2, d0, d2, mi
-; CHECK-GI-NEXT: mov v0.d[0], v4.d[0]
-; CHECK-GI-NEXT: mov v1.d[0], v1.d[0]
-; CHECK-GI-NEXT: mov v2.d[0], v2.d[0]
-; CHECK-GI-NEXT: fcsel d4, d6, d7, mi
-; CHECK-GI-NEXT: mov v0.d[1], v5.d[0]
-; CHECK-GI-NEXT: mov v1.d[1], v3.d[0]
-; CHECK-GI-NEXT: mov v2.d[1], v4.d[0]
+; CHECK-GI-NEXT: mov d2, v0.d[1]
+; CHECK-GI-NEXT: mov d6, v7.d[1]
+; CHECK-GI-NEXT: fcsel d7, d0, d7, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d1
+; CHECK-GI-NEXT: fmov x9, d7
+; CHECK-GI-NEXT: fcsel d4, d2, d6, mi
+; CHECK-GI-NEXT: mov v1.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d5
+; CHECK-GI-NEXT: mov v2.d[0], x9
+; CHECK-GI-NEXT: fmov x9, d3
+; CHECK-GI-NEXT: fmov x10, d4
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v1.d[1], x9
+; CHECK-GI-NEXT: mov v2.d[1], x10
; CHECK-GI-NEXT: add sp, sp, #192
; CHECK-GI-NEXT: ret
entry:
@@ -831,19 +843,19 @@ define <3 x double> @v3f64_double(<3 x double> %a, <3 x double> %b, <3 x double>
; CHECK-GI-NEXT: // kill: def $d6 killed $d6 def $q6
; CHECK-GI-NEXT: // kill: def $d7 killed $d7 def $q7
; CHECK-GI-NEXT: fcmp d2, d5
-; CHECK-GI-NEXT: ldr x9, [sp]
+; CHECK-GI-NEXT: ldr x8, [sp]
; CHECK-GI-NEXT: ldr x10, [sp, #24]
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]
; CHECK-GI-NEXT: mov v6.d[1], v7.d[0]
; CHECK-GI-NEXT: ldp d1, d4, [sp, #8]
-; CHECK-GI-NEXT: cset w8, mi
-; CHECK-GI-NEXT: sbfx x8, x8, #0, #1
+; CHECK-GI-NEXT: cset w9, mi
+; CHECK-GI-NEXT: sbfx x9, x9, #0, #1
; CHECK-GI-NEXT: fcmgt v0.2d, v3.2d, v0.2d
; CHECK-GI-NEXT: mov v1.d[1], v4.d[0]
-; CHECK-GI-NEXT: and x9, x9, x8
-; CHECK-GI-NEXT: bic x8, x10, x8
-; CHECK-GI-NEXT: orr x8, x9, x8
+; CHECK-GI-NEXT: and x8, x8, x9
+; CHECK-GI-NEXT: bic x9, x10, x9
+; CHECK-GI-NEXT: orr x8, x8, x9
; CHECK-GI-NEXT: fmov d2, x8
; CHECK-GI-NEXT: bsl v0.16b, v6.16b, v1.16b
; CHECK-GI-NEXT: mov d1, v0.d[1]
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
index 7d527f6b6464e..b6cbe9eb46389 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
@@ -968,51 +968,46 @@ define i32 @test_signed_f128_i32(fp128 %f) {
;
; CHECK-GI-LABEL: test_signed_f128_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #80
-; CHECK-GI-NEXT: str d8, [sp, #48] // 8-byte Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
+; CHECK-GI-NEXT: sub sp, sp, #48
+; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: .cfi_offset b8, -32
-; CHECK-GI-NEXT: adrp x8, .LCPI30_2
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_2]
-; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fmov d2, x8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: adrp x8, .LCPI30_1
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d2, gt
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
-; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: bl __gttf2
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov x9, #-4603241769126068224 // =0xc01e000000000000
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, x9, gt
; CHECK-GI-NEXT: adrp x8, .LCPI30_0
-; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
+; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
+; CHECK-GI-NEXT: movk x8, #16413, lsl #48
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr d8, [sp, #48] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: csel w0, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: add sp, sp, #80
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
%x = call i32 @llvm.fptosi.sat.i32.f128(fp128 %f)
ret i32 %x
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 5783a961e2161..6a06d99689df9 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -517,52 +517,47 @@ define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v1f128_v1i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #80
-; CHECK-GI-NEXT: str d8, [sp, #48] // 8-byte Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
+; CHECK-GI-NEXT: sub sp, sp, #48
+; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: .cfi_offset b8, -32
-; CHECK-GI-NEXT: adrp x8, .LCPI14_2
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_2]
-; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fmov d2, x8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -32
; CHECK-GI-NEXT: adrp x8, .LCPI14_1
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d2, gt
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
-; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: bl __gttf2
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov x9, #-4603241769126068224 // =0xc01e000000000000
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, x9, gt
; CHECK-GI-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
+; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
+; CHECK-GI-NEXT: movk x8, #16413, lsl #48
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr d8, [sp, #48] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: add sp, sp, #80
+; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f128.v1i32(<1 x fp128> %f)
ret <1 x i32> %x
@@ -636,92 +631,82 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #144
-; CHECK-GI-NEXT: str d10, [sp, #96] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #104] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #120] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 144
+; CHECK-GI-NEXT: sub sp, sp, #112
+; CHECK-GI-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -24
-; CHECK-GI-NEXT: .cfi_offset b8, -32
-; CHECK-GI-NEXT: .cfi_offset b9, -40
-; CHECK-GI-NEXT: .cfi_offset b10, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI15_2
-; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
-; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: .cfi_offset w21, -24
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: adrp x8, .LCPI15_1
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_1]
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
-; CHECK-GI-NEXT: str q2, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q2, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fmov d9, x8
-; CHECK-GI-NEXT: adrp x8, .LCPI15_1
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
-; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x21, x8, x20, gt
+; CHECK-GI-NEXT: adrp x8, .LCPI15_0
+; CHECK-GI-NEXT: mov v0.d[1], x21
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI15_0]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: movk x22, #16413, lsl #48
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w20, wzr, w19, ne
+; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, x20, gt
+; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w20
+; CHECK-GI-NEXT: fmov s0, w21
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #120] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #104] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d10, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #144
+; CHECK-GI-NEXT: add sp, sp, #112
; CHECK-GI-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x
@@ -814,119 +799,107 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v3f128_v3i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #176
-; CHECK-GI-NEXT: str d10, [sp, #112] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x21, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #160] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 176
+; CHECK-GI-NEXT: sub sp, sp, #128
+; CHECK-GI-NEXT: stp x30, x23, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: .cfi_offset b8, -40
-; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: .cfi_offset b10, -64
-; CHECK-GI-NEXT: adrp x8, .LCPI16_2
-; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_2]
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: str q2, [sp, #96] // 16-byte Spill
-; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w23, -40
+; CHECK-GI-NEXT: .cfi_offset w30, -48
; CHECK-GI-NEXT: adrp x8, .LCPI16_1
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: str q2, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: bl __gttf2
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x21, x8, x20, gt
+; CHECK-GI-NEXT: adrp x8, .LCPI16_0
+; CHECK-GI-NEXT: mov v0.d[1], x21
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI16_0]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: movk x22, #16413, lsl #48
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w20, wzr, w19, ne
+; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x23, x8, x20, gt
+; CHECK-GI-NEXT: mov v0.d[1], x23
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w21, wzr, w19, ne
+; CHECK-GI-NEXT: csel w23, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, x20, gt
+; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w20
+; CHECK-GI-NEXT: fmov s0, w21
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr d10, [sp, #112] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #128] // 16-byte Folded Reload
-; CHECK-GI-NEXT: mov v0.s[1], w21
-; CHECK-GI-NEXT: ldp x30, x21, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.s[1], w23
+; CHECK-GI-NEXT: ldp x30, x23, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: add sp, sp, #176
+; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x
@@ -1041,150 +1014,134 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v4f128_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #192
-; CHECK-GI-NEXT: str d10, [sp, #128] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #136] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #152] // 8-byte Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #160] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 192
+; CHECK-GI-NEXT: sub sp, sp, #160
+; CHECK-GI-NEXT: str x30, [sp, #96] // 8-byte Spill
+; CHECK-GI-NEXT: stp x24, x23, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w30, -40
-; CHECK-GI-NEXT: .cfi_offset b8, -48
-; CHECK-GI-NEXT: .cfi_offset b9, -56
-; CHECK-GI-NEXT: .cfi_offset b10, -64
-; CHECK-GI-NEXT: adrp x8, .LCPI17_2
-; CHECK-GI-NEXT: stp q0, q1, [sp, #32] // 32-byte Folded Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_2]
-; CHECK-GI-NEXT: str q2, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: stp q1, q3, [sp, #96] // 32-byte Folded Spill
-; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x8, #4123168604160 // =0x3c000000000
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: .cfi_offset w23, -40
+; CHECK-GI-NEXT: .cfi_offset w24, -48
+; CHECK-GI-NEXT: .cfi_offset w30, -64
; CHECK-GI-NEXT: adrp x8, .LCPI17_1
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
-; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
-; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
+; CHECK-GI-NEXT: str q2, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: stp q1, q3, [sp, #64] // 32-byte Folded Spill
+; CHECK-GI-NEXT: bl __gttf2
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov x20, #-4603241769126068224 // =0xc01e000000000000
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x21, x8, x20, gt
; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: ldr d10, [x8, :lo12:.LCPI17_0]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], x21
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: bl __lttf2
+; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: mov x22, #281474976448512 // =0xfffffffc0000
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: movk x22, #16413, lsl #48
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w20, wzr, w19, ne
+; CHECK-GI-NEXT: csel w21, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x23, x8, x20, gt
+; CHECK-GI-NEXT: mov v0.d[1], x23
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w21, wzr, w19, ne
+; CHECK-GI-NEXT: csel w23, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x24, x8, x20, gt
+; CHECK-GI-NEXT: mov v0.d[1], x24
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x24, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #96] // 32-byte Folded Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w22, wzr, w19, ne
+; CHECK-GI-NEXT: csel w24, wzr, w19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, x20, gt
+; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov s0, w20
+; CHECK-GI-NEXT: fmov s0, w21
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #152] // 8-byte Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #136] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d10, [sp, #128] // 8-byte Reload
-; CHECK-GI-NEXT: mov v0.s[1], w21
-; CHECK-GI-NEXT: mov v0.s[2], w22
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #128] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.s[1], w23
+; CHECK-GI-NEXT: mov v0.s[2], w24
+; CHECK-GI-NEXT: ldp x24, x23, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: add sp, sp, #192
+; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x
@@ -5169,96 +5126,82 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #160
-; CHECK-GI-NEXT: stp d11, d10, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #128] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
+; CHECK-GI-NEXT: sub sp, sp, #112
+; CHECK-GI-NEXT: stp x30, x23, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: .cfi_offset b8, -40
-; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: .cfi_offset b10, -56
-; CHECK-GI-NEXT: .cfi_offset b11, -64
+; CHECK-GI-NEXT: .cfi_offset w21, -24
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w23, -40
+; CHECK-GI-NEXT: .cfi_offset w30, -48
; CHECK-GI-NEXT: adrp x8, .LCPI86_1
-; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
-; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: mov v1.16b, v2.16b
-; CHECK-GI-NEXT: str q2, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: str q2, [sp, #16] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov x8, #8521215115264 // =0x7c000000000
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: movk x8, #17384, lsl #48
-; CHECK-GI-NEXT: fmov d9, x8
+; CHECK-GI-NEXT: mov x20, #-4594234569871327232 // =0xc03e000000000000
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x21, x8, x20, gt
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], x21
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
-; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: mov x8, #280925220896768 // =0xff8000000000
-; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
-; CHECK-GI-NEXT: movk x8, #17391, lsl #48
+; CHECK-GI-NEXT: mov x22, #-1125899906842624 // =0xfffc000000000000
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov d10, x8
-; CHECK-GI-NEXT: mov x8, #-264432546480129 // =0xffff0f7fffffffff
-; CHECK-GI-NEXT: movk x8, #17360, lsl #48
-; CHECK-GI-NEXT: fmov d11, x8
-; CHECK-GI-NEXT: fcsel d0, d0, d10, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d11, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov x23, #4629137466983448575 // =0x403dffffffffffff
+; CHECK-GI-NEXT: csel x8, x19, x22, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x21, x23, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfdi
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel x20, xzr, x19, ne
+; CHECK-GI-NEXT: csel x21, xzr, x19, ne
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d9, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, x20, gt
+; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d10, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d11, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x19, x22, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x20, x23, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfdi
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
-; CHECK-GI-NEXT: fmov d0, x20
+; CHECK-GI-NEXT: fmov d0, x21
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #128] // 8-byte Reload
; CHECK-GI-NEXT: csel x8, xzr, x19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #112] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x23, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: add sp, sp, #160
+; CHECK-GI-NEXT: add sp, sp, #112
; CHECK-GI-NEXT: ret
%x = call <2 x i64> @llvm.fptosi.sat.v2f128.v2i64(<2 x fp128> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
index 038ac9f97e6ea..7a5fe0f4222bc 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
@@ -784,38 +784,35 @@ define i32 @test_unsigned_f128_i32(fp128 %f) {
; CHECK-GI-LABEL: test_unsigned_f128_i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str d8, [sp, #32] // 8-byte Spill
-; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
+; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
-; CHECK-GI-NEXT: .cfi_offset w30, -8
-; CHECK-GI-NEXT: .cfi_offset b8, -16
-; CHECK-GI-NEXT: adrp x8, .LCPI30_2
-; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_2]
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI30_1
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: adrp x8, .LCPI30_0
+; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI30_0
-; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
-; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: ldr d8, [sp, #32] // 8-byte Reload
-; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
+; CHECK-GI-NEXT: movk x8, #16414, lsl #48
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: b __fixunstfsi
%x = call i32 @llvm.fptoui.sat.i32.f128(fp128 %f)
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index ead181d4a86a0..d4feab2ea5d9b 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -474,40 +474,37 @@ define <1 x i32> @test_unsigned_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-GI-LABEL: test_unsigned_v1f128_v1i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #48
-; CHECK-GI-NEXT: str d8, [sp, #32] // 8-byte Spill
-; CHECK-GI-NEXT: str x30, [sp, #40] // 8-byte Spill
+; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
-; CHECK-GI-NEXT: .cfi_offset w30, -8
-; CHECK-GI-NEXT: .cfi_offset b8, -16
-; CHECK-GI-NEXT: adrp x8, .LCPI14_2
-; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_2]
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -32
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI14_1
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: adrp x8, .LCPI14_0
+; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI14_0
-; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d2, d1, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov x8, #281474976579584 // =0xfffffffe0000
+; CHECK-GI-NEXT: movk x8, #16414, lsl #48
+; CHECK-GI-NEXT: csel x8, x20, x8, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldr x30, [sp, #40] // 8-byte Reload
-; CHECK-GI-NEXT: ldr d8, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: fmov s0, w0
+; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
%x = call <1 x i32> @llvm.fptoui.sat.v1f128.v1i32(<1 x fp128> %f)
@@ -566,70 +563,65 @@ define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v2f128_v2i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #112
-; CHECK-GI-NEXT: stp d9, d8, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 112
+; CHECK-GI-NEXT: sub sp, sp, #80
+; CHECK-GI-NEXT: str x30, [sp, #32] // 8-byte Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
; CHECK-GI-NEXT: .cfi_offset w19, -8
-; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: .cfi_offset b8, -24
-; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: adrp x8, .LCPI15_2
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]
-; CHECK-GI-NEXT: stp q2, q1, [sp, #48] // 32-byte Folded Spill
-; CHECK-GI-NEXT: mov v1.16b, v2.16b
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w21, -24
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI15_1
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
-; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: adrp x8, .LCPI15_0
+; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
+; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI15_0
-; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI15_0]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov x21, #281474976579584 // =0xfffffffe0000
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: movk x21, #16414, lsl #48
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x20
+; CHECK-GI-NEXT: csel x22, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x22
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x20, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x22, x21, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: add sp, sp, #112
+; CHECK-GI-NEXT: add sp, sp, #80
; CHECK-GI-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f128.v2i32(<2 x fp128> %f)
ret <2 x i32> %x
@@ -700,94 +692,86 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v3f128_v3i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #144
-; CHECK-GI-NEXT: stp d9, d8, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x30, [sp, #112] // 8-byte Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 144
+; CHECK-GI-NEXT: sub sp, sp, #96
+; CHECK-GI-NEXT: stp x30, x23, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: .cfi_offset b8, -40
-; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI16_2
-; CHECK-GI-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_2]
-; CHECK-GI-NEXT: stp q1, q2, [sp, #64] // 32-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_offset w21, -24
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w23, -40
+; CHECK-GI-NEXT: .cfi_offset w30, -48
+; CHECK-GI-NEXT: stp q1, q0, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: str q2, [sp, #32] // 16-byte Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI16_1
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: adrp x8, .LCPI16_0
+; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI16_0
-; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI16_0]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov x21, #281474976579584 // =0xfffffffe0000
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: movk x21, #16414, lsl #48
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x20, x21, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x20
+; CHECK-GI-NEXT: csel x22, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x22
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x20, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x22, x21, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w20, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x22, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x22
+; CHECK-GI-NEXT: csel x23, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x23
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #64] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x22, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x23, x21, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr x30, [sp, #112] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x30, x23, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w0
-; CHECK-GI-NEXT: add sp, sp, #144
+; CHECK-GI-NEXT: add sp, sp, #96
; CHECK-GI-NEXT: ret
%x = call <3 x i32> @llvm.fptoui.sat.v3f128.v3i32(<3 x fp128> %f)
ret <3 x i32> %x
@@ -876,123 +860,111 @@ define <4 x i32> @test_unsigned_v4f128_v4i32(<4 x fp128> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v4f128_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #160
-; CHECK-GI-NEXT: stp d9, d8, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x21, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 160
+; CHECK-GI-NEXT: sub sp, sp, #128
+; CHECK-GI-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-GI-NEXT: stp x24, x23, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w30, -32
-; CHECK-GI-NEXT: .cfi_offset b8, -40
-; CHECK-GI-NEXT: .cfi_offset b9, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI17_2
-; CHECK-GI-NEXT: stp q1, q2, [sp, #32] // 32-byte Folded Spill
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_2]
-; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
-; CHECK-GI-NEXT: str q3, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: str q1, [sp, #96] // 16-byte Spill
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w23, -40
+; CHECK-GI-NEXT: .cfi_offset w24, -48
+; CHECK-GI-NEXT: .cfi_offset w30, -64
+; CHECK-GI-NEXT: stp q1, q2, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: stp q3, q0, [sp, #32] // 32-byte Folded Spill
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI17_1
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
-; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: adrp x8, .LCPI17_0
+; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: adrp x8, .LCPI17_0
-; CHECK-GI-NEXT: ldr d9, [x8, :lo12:.LCPI17_0]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov x22, #281474976579584 // =0xfffffffe0000
+; CHECK-GI-NEXT: csel x8, x19, xzr, mi
+; CHECK-GI-NEXT: movk x22, #16414, lsl #48
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: mov w19, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x20, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x20
+; CHECK-GI-NEXT: csel x21, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x21
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x20, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x21, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: mov w20, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x21, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x21
+; CHECK-GI-NEXT: csel x23, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x23
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x21, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x23, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-GI-NEXT: ldr q1, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-GI-NEXT: mov w21, w0
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q1, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x23, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x23
+; CHECK-GI-NEXT: csel x24, x8, xzr, gt
+; CHECK-GI-NEXT: mov v0.d[1], x24
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr q1, [sp, #64] // 16-byte Reload
-; CHECK-GI-NEXT: fcsel d0, d0, d8, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d9, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: csel x8, x23, xzr, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x24, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfsi
; CHECK-GI-NEXT: fmov s0, w19
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x24, x23, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-GI-NEXT: mov v0.s[1], w20
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[2], w21
-; CHECK-GI-NEXT: ldp x30, x21, [sp, #128] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[3], w0
-; CHECK-GI-NEXT: add sp, sp, #160
+; CHECK-GI-NEXT: add sp, sp, #128
; CHECK-GI-NEXT: ret
%x = call <4 x i32> @llvm.fptoui.sat.v4f128.v4i32(<4 x fp128> %f)
ret <4 x i32> %x
@@ -4152,41 +4124,12 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
;
; CHECK-GI-LABEL: test_signed_v2f128_v2i64:
; CHECK-GI: // %bb.0:
-<<<<<<< HEAD
-<<<<<<< HEAD
; CHECK-GI-NEXT: sub sp, sp, #80
; CHECK-GI-NEXT: stp x30, x23, [sp, #32] // 16-byte Folded Spill
; CHECK-GI-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
; CHECK-GI-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-GI-NEXT: .cfi_def_cfa_offset 80
-||||||| parent of 25bc4b2b4034 (Update tests)
-; CHECK-GI-NEXT: sub sp, sp, #96
-; CHECK-GI-NEXT: stp x30, x23, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
-=======
-; CHECK-GI-NEXT: sub sp, sp, #96
-; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
->>>>>>> 25bc4b2b4034 (Update tests)
-||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
-; CHECK-GI-NEXT: sub sp, sp, #96
-; CHECK-GI-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 96
-=======
-; CHECK-GI-NEXT: sub sp, sp, #128
-; CHECK-GI-NEXT: str d10, [sp, #80] // 8-byte Spill
-; CHECK-GI-NEXT: stp d9, d8, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x30, x19, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 128
->>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
; CHECK-GI-NEXT: .cfi_offset w19, -8
-<<<<<<< HEAD
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
; CHECK-GI-NEXT: .cfi_offset w22, -32
@@ -4194,165 +4137,52 @@ define <2 x i64> @test_signed_v2f128_v2i64(<2 x fp128> %f) {
; CHECK-GI-NEXT: .cfi_offset w30, -48
; CHECK-GI-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-||||||| parent of 25bc4b2b4034 (Update tests)
-; CHECK-GI-NEXT: .cfi_offset w20, -16
-; CHECK-GI-NEXT: .cfi_offset w21, -24
-; CHECK-GI-NEXT: .cfi_offset w22, -32
-; CHECK-GI-NEXT: .cfi_offset w23, -40
-; CHECK-GI-NEXT: .cfi_offset w30, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI86_1
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
-; CHECK-GI-NEXT: stp q2, q1, [sp, #16] // 32-byte Folded Spill
-; CHECK-GI-NEXT: mov v1.16b, v2.16b
-=======
-; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: .cfi_offset b8, -24
-; CHECK-GI-NEXT: .cfi_offset b9, -32
-; CHECK-GI-NEXT: .cfi_offset b10, -48
-; CHECK-GI-NEXT: adrp x8, .LCPI86_1
-; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI86_1]
-; CHECK-GI-NEXT: stp q2, q1, [sp, #48] // 32-byte Folded Spill
-; CHECK-GI-NEXT: mov v1.16b, v2.16b
->>>>>>> 25bc4b2b4034 (Update tests)
; CHECK-GI-NEXT: bl __gttf2
-; CHECK-GI-NEXT: movi d8, #0000000000000000
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-GI-NEXT: cmp w0, #0
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: csel x19, x8, xzr, gt
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: mov v0.d[0], x19
+; CHECK-GI-NEXT: csel x20, x8, xzr, gt
; CHECK-GI-NEXT: adrp x8, .LCPI86_0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI86_0]
-; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: mov x8, #281200098803712 // =0xffc000000000
-; CHECK-GI-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
-; CHECK-GI-NEXT: movk x8, #17391, lsl #48
+; CHECK-GI-NEXT: mov x21, #-562949953421312 // =0xfffe000000000000
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fmov d9, x8
-; CHECK-GI-NEXT: mov x8, #-264157668573185 // =0xffff0fbfffffffff
-; CHECK-GI-NEXT: movk x8, #17360, lsl #48
-; CHECK-GI-NEXT: fmov d10, x8
-; CHECK-GI-NEXT: fcsel d0, d0, d9, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: mov x22, #4629418941960159231 // =0x403effffffffffff
+; CHECK-GI-NEXT: csel x8, x19, x21, mi
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: csel x8, x20, x22, mi
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixunstfdi
-<<<<<<< HEAD
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #16] // 32-byte Folded Reload
-=======
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
->>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
; CHECK-GI-NEXT: mov x19, x0
; CHECK-GI-NEXT: bl __gttf2
-<<<<<<< HEAD
-<<<<<<< HEAD
; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload
-||||||| parent of 25bc4b2b4034 (Update tests)
-; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-=======
-||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
-=======
-; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcsel d0, d0, d8, gt
-; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: fcsel d1, d1, d8, gt
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
->>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
-; CHECK-GI-NEXT: ldr q1, [sp, #32] // 16-byte Reload
-<<<<<<< HEAD
->>>>>>> 25bc4b2b4034 (Update tests)
; CHECK-GI-NEXT: cmp w0, #0
-<<<<<<< HEAD
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: csel x20, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x20
; CHECK-GI-NEXT: csel x23, x8, xzr, gt
; CHECK-GI-NEXT: mov v0.d[1], x23
-||||||| parent of 25bc4b2b4034 (Update tests)
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d0
-; CHECK-GI-NEXT: csel x20, x8, xzr, gt
-; CHECK-GI-NEXT: mov x8, v0.d[1]
-; CHECK-GI-NEXT: mov v0.d[0], x20
-; CHECK-GI-NEXT: csel x23, x8, xzr, gt
-; CHECK-GI-NEXT: mov v0.d[1], x23
-=======
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d8, d0, d8, gt
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d8
-; CHECK-GI-NEXT: mov v0.d[1], x8
->>>>>>> 25bc4b2b4034 (Update tests)
-||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
+; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: mov d0, v1.d[1]
-; CHECK-GI-NEXT: fcsel d10, d1, d8, gt
-; CHECK-GI-NEXT: ldr q1, [sp] // 16-byte Reload
-; CHECK-GI-NEXT: fmov x8, d10
-; CHECK-GI-NEXT: fcsel d8, d0, d8, gt
+; CHECK-GI-NEXT: csel x8, x20, x21, mi
; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: fmov x8, d8
+; CHECK-GI-NEXT: csel x8, x23, x22, mi
; CHECK-GI-NEXT: mov v0.d[1], x8
-=======
->>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
-; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: ldp q1, q0, [sp, #48] // 32-byte Folded Reload
-; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: fcsel d0, d0, d9, mi
-; CHECK-GI-NEXT: fcsel d1, d1, d10, mi
-; CHECK-GI-NEXT: mov v0.d[0], v0.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: bl __fixunstfdi
; CHECK-GI-NEXT: fmov d0, x19
-<<<<<<< HEAD
-<<<<<<< HEAD
; CHECK-GI-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp x30, x23, [sp, #32] // 16-byte Folded Reload
-||||||| parent of 25bc4b2b4034 (Update tests)
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x30, x23, [sp, #48] // 16-byte Folded Reload
-=======
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
->>>>>>> 25bc4b2b4034 (Update tests)
-||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #80] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
-=======
-; CHECK-GI-NEXT: ldp x30, x19, [sp, #112] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp d9, d8, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr d10, [sp, #80] // 8-byte Reload
->>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
; CHECK-GI-NEXT: mov v0.d[1], x0
-<<<<<<< HEAD
; CHECK-GI-NEXT: add sp, sp, #80
-||||||| parent of fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
-; CHECK-GI-NEXT: add sp, sp, #96
-=======
-; CHECK-GI-NEXT: add sp, sp, #128
->>>>>>> fadc4d6243d4 (Merge should not force values onto GPR if the operands are on FPR registers)
; CHECK-GI-NEXT: ret
%x = call <2 x i64> @llvm.fptoui.sat.v2f128.v2i64(<2 x fp128> %f)
ret <2 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll b/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
index 5753798e87512..b35511dd4ab69 100644
--- a/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
+++ b/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
@@ -786,7 +786,7 @@ define <2 x i8> @extract_scalable_vec() vscale_range(1,16) "target-features"="+s
; CHECK-GI-LABEL: extract_scalable_vec:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov x8, xzr
-; CHECK-GI-NEXT: mov x9, #1 // =0x1
+; CHECK-GI-NEXT: mov w9, #1 // =0x1
; CHECK-GI-NEXT: ld1 { v0.b }[0], [x8]
; CHECK-GI-NEXT: ldr b1, [x9]
; CHECK-GI-NEXT: adrp x8, .LCPI36_0
diff --git a/llvm/test/CodeGen/AArch64/phi.ll b/llvm/test/CodeGen/AArch64/phi.ll
index a7ca9ed8a8165..02842c04bf7bf 100644
--- a/llvm/test/CodeGen/AArch64/phi.ll
+++ b/llvm/test/CodeGen/AArch64/phi.ll
@@ -274,8 +274,10 @@ define fp128 @tf128(i1 %c, ptr %p, fp128 %a, fp128 %b) {
; CHECK-GI-NEXT: .LBB9_2:
; CHECK-GI-NEXT: mov d2, v1.d[1]
; CHECK-GI-NEXT: .LBB9_3: // %e
-; CHECK-GI-NEXT: mov v0.d[0], v1.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-GI-NEXT: fmov x8, d1
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: fmov x8, d2
+; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -1301,10 +1303,14 @@ define <2 x fp128> @tv2f128(i1 %c, ptr %p, <2 x fp128> %a, <2 x fp128> %b) {
; CHECK-GI-NEXT: mov d4, v3.d[1]
; CHECK-GI-NEXT: mov d5, v2.d[1]
; CHECK-GI-NEXT: .LBB44_3: // %e
-; CHECK-GI-NEXT: mov v0.d[0], v2.d[0]
-; CHECK-GI-NEXT: mov v1.d[0], v3.d[0]
-; CHECK-GI-NEXT: mov v0.d[1], v5.d[0]
-; CHECK-GI-NEXT: mov v1.d[1], v4.d[0]
+; CHECK-GI-NEXT: fmov x8, d2
+; CHECK-GI-NEXT: fmov x9, d3
+; CHECK-GI-NEXT: mov v0.d[0], x8
+; CHECK-GI-NEXT: mov v1.d[0], x9
+; CHECK-GI-NEXT: fmov x8, d5
+; CHECK-GI-NEXT: fmov x9, d4
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: mov v1.d[1], x9
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
diff --git a/llvm/test/CodeGen/AArch64/popcount.ll b/llvm/test/CodeGen/AArch64/popcount.ll
index d0a24b9cd287b..bb81776a7f6d6 100644
--- a/llvm/test/CodeGen/AArch64/popcount.ll
+++ b/llvm/test/CodeGen/AArch64/popcount.ll
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+neon,+dotprod | FileCheck %s --check-prefixes=CHECK,DOT
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+sve | FileCheck %s --check-prefixes=CHECK,SVE
; RUN: llc < %s -mtriple=aarch64_be-unknown-unknown | FileCheck %s --check-prefixes=BE
-; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefixes=GISEL,GISELO3
+; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefix=GISEL
; RUN: llc < %s -O0 -global-isel -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefix=GISELO0
; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown -mattr=+neon | FileCheck %s --check-prefixes=GISEL,NEON-GISEL
; RUN: llc < %s -global-isel -mtriple=aarch64-unknown-unknown -mattr=+neon,+dotprod | FileCheck %s --check-prefixes=GISEL,DOT-GISEL
@@ -397,14 +397,6 @@ define <2 x i64> @popcount2x64(<2 x i64> %0) {
; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; BE-NEXT: ret
;
-; GISELO3-LABEL: popcount2x64:
-; GISELO3: // %bb.0: // %Entry
-; GISELO3-NEXT: cnt v0.16b, v0.16b
-; GISELO3-NEXT: uaddlp v0.8h, v0.16b
-; GISELO3-NEXT: uaddlp v0.4s, v0.8h
-; GISELO3-NEXT: uaddlp v0.2d, v0.4s
-; GISELO3-NEXT: ret
-;
; GISELO0-LABEL: popcount2x64:
; GISELO0: // %bb.0: // %Entry
; GISELO0-NEXT: cnt v0.16b, v0.16b
@@ -437,13 +429,6 @@ define <2 x i64> @popcount2x64(<2 x i64> %0) {
; SVE-GISEL-NEXT: uaddlp v0.4s, v0.8h
; SVE-GISEL-NEXT: uaddlp v0.2d, v0.4s
; SVE-GISEL-NEXT: ret
-; GISEL-O3-LABEL: popcount2x64:
-; GISEL-O3: // %bb.0: // %Entry
-; GISEL-O3-NEXT: cnt v0.16b, v0.16b
-; GISEL-O3-NEXT: uaddlp v0.8h, v0.16b
-; GISEL-O3-NEXT: uaddlp v0.4s, v0.8h
-; GISEL-O3-NEXT: uaddlp v0.2d, v0.4s
-; GISEL-O3-NEXT: ret
Entry:
%1 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
ret <2 x i64> %1
@@ -561,13 +546,6 @@ define <4 x i32> @popcount4x32(<4 x i32> %0) {
; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; BE-NEXT: ret
;
-; GISELO3-LABEL: popcount4x32:
-; GISELO3: // %bb.0: // %Entry
-; GISELO3-NEXT: cnt v0.16b, v0.16b
-; GISELO3-NEXT: uaddlp v0.8h, v0.16b
-; GISELO3-NEXT: uaddlp v0.4s, v0.8h
-; GISELO3-NEXT: ret
-;
; GISELO0-LABEL: popcount4x32:
; GISELO0: // %bb.0: // %Entry
; GISELO0-NEXT: cnt v0.16b, v0.16b
@@ -597,12 +575,6 @@ define <4 x i32> @popcount4x32(<4 x i32> %0) {
; SVE-GISEL-NEXT: uaddlp v0.8h, v0.16b
; SVE-GISEL-NEXT: uaddlp v0.4s, v0.8h
; SVE-GISEL-NEXT: ret
-; GISEL-O3-LABEL: popcount4x32:
-; GISEL-O3: // %bb.0: // %Entry
-; GISEL-O3-NEXT: cnt v0.16b, v0.16b
-; GISEL-O3-NEXT: uaddlp v0.8h, v0.16b
-; GISEL-O3-NEXT: uaddlp v0.4s, v0.8h
-; GISEL-O3-NEXT: ret
Entry:
%1 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
ret <4 x i32> %1
@@ -651,13 +623,6 @@ define <2 x i32> @popcount2x32(<2 x i32> %0) {
; BE-NEXT: rev64 v0.2s, v0.2s
; BE-NEXT: ret
;
-; GISELO3-LABEL: popcount2x32:
-; GISELO3: // %bb.0: // %Entry
-; GISELO3-NEXT: cnt v0.8b, v0.8b
-; GISELO3-NEXT: uaddlp v0.4h, v0.8b
-; GISELO3-NEXT: uaddlp v0.2s, v0.4h
-; GISELO3-NEXT: ret
-;
; GISELO0-LABEL: popcount2x32:
; GISELO0: // %bb.0: // %Entry
; GISELO0-NEXT: cnt v0.8b, v0.8b
@@ -687,12 +652,6 @@ define <2 x i32> @popcount2x32(<2 x i32> %0) {
; SVE-GISEL-NEXT: uaddlp v0.4h, v0.8b
; SVE-GISEL-NEXT: uaddlp v0.2s, v0.4h
; SVE-GISEL-NEXT: ret
-; GISEL-O3-LABEL: popcount2x32:
-; GISEL-O3: // %bb.0: // %Entry
-; GISEL-O3-NEXT: cnt v0.8b, v0.8b
-; GISEL-O3-NEXT: uaddlp v0.4h, v0.8b
-; GISEL-O3-NEXT: uaddlp v0.2s, v0.4h
-; GISEL-O3-NEXT: ret
Entry:
%1 = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %0)
ret <2 x i32> %1
diff --git a/llvm/test/CodeGen/AArch64/select_const.ll b/llvm/test/CodeGen/AArch64/select_const.ll
index 0a73aed803415..daa9971dbcd58 100644
--- a/llvm/test/CodeGen/AArch64/select_const.ll
+++ b/llvm/test/CodeGen/AArch64/select_const.ll
@@ -972,3 +972,27 @@ define double @frem_constant_sel_constants(i1 %cond) {
%bo = frem double 5.1, %sel
ret double %bo
}
+
+define <4 x float> @select_const_i1(i1 %c) {
+; CHECK-SD-LABEL: select_const_i1:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: tst w0, #0x1
+; CHECK-SD-NEXT: fmov v0.4s, #1.00000000
+; CHECK-SD-NEXT: csetm w8, ne
+; CHECK-SD-NEXT: dup v1.4s, w8
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: select_const_i1:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: and w8, w0, #0x1
+; CHECK-GI-NEXT: fmov v0.4s, #1.00000000
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: sbfx w8, w8, #0, #1
+; CHECK-GI-NEXT: dup v2.4s, w8
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %a.addr.5.i = select i1 %c, <4 x float> splat (float 1.000000e+00), <4 x float> zeroinitializer
+ ret <4 x float> %a.addr.5.i
+}
diff --git a/llvm/test/CodeGen/AArch64/store.ll b/llvm/test/CodeGen/AArch64/store.ll
index 1dc55fccc3dac..72f1cb5a0b22f 100644
--- a/llvm/test/CodeGen/AArch64/store.ll
+++ b/llvm/test/CodeGen/AArch64/store.ll
@@ -39,6 +39,29 @@ define void @store_i64(i64 %a, ptr %ptr){
ret void
}
+define i32 @store_i112(ptr %p) {
+; CHECK-SD-LABEL: store_i112:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov x8, x0
+; CHECK-SD-NEXT: mov w0, wzr
+; CHECK-SD-NEXT: str xzr, [x8]
+; CHECK-SD-NEXT: strh wzr, [x8, #12]
+; CHECK-SD-NEXT: str wzr, [x8, #8]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: store_i112:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, x0
+; CHECK-GI-NEXT: mov w0, wzr
+; CHECK-GI-NEXT: str xzr, [x8]
+; CHECK-GI-NEXT: str wzr, [x8, #8]
+; CHECK-GI-NEXT: strh wzr, [x8, #12]
+; CHECK-GI-NEXT: ret
+ store i112 0, ptr %p, align 16
+ ret i32 0
+}
+
+
; ===== Legal Vector Types =====
define void @store_v8i8(<8 x i8> %a, ptr %ptr){
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
index 1a7cad7886635..60ccd20c095cd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
@@ -22,8 +22,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; SI-NEXT: %4:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %4(s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s16
@@ -37,8 +37,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; VI-NEXT: %4:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %4(s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s16
@@ -52,8 +52,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; GFX9-NEXT: %4:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %4(s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -79,8 +79,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; SI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY %2(s32)
;
; VI-LABEL: name: test_copysign_s32_s32
; VI: liveins: $vgpr0, $vgpr1
@@ -91,8 +91,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; VI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY %2(s32)
;
; GFX9-LABEL: name: test_copysign_s32_s32
; GFX9: liveins: $vgpr0, $vgpr1
@@ -103,8 +103,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; GFX9-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY %2(s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_FCOPYSIGN %0, %1
@@ -126,8 +126,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; SI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; SI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
;
; VI-LABEL: name: test_copysign_s64_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -138,8 +138,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; VI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
;
; GFX9-LABEL: name: test_copysign_s64_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -150,8 +150,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; GFX9-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_FCOPYSIGN %0, %1
@@ -176,8 +176,8 @@ body: |
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; SI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
;
; VI-LABEL: name: test_copysign_s64_s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2
@@ -191,8 +191,8 @@ body: |
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; VI-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
;
; GFX9-LABEL: name: test_copysign_s64_s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
@@ -206,8 +206,8 @@ body: |
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; GFX9-NEXT: %2:_(s64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_FCOPYSIGN %0, %1
@@ -232,8 +232,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; SI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY %2(s32)
;
; VI-LABEL: name: test_copysign_s32_s64
; VI: liveins: $vgpr0, $vgpr1_vgpr2
@@ -247,8 +247,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; VI-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY %2(s32)
;
; GFX9-LABEL: name: test_copysign_s32_s64
; GFX9: liveins: $vgpr0, $vgpr1_vgpr2
@@ -262,8 +262,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; GFX9-NEXT: %2:_(s32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY %2(s32)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = COPY $vgpr1_vgpr2
%2:_(s32) = G_FCOPYSIGN %0, %1
@@ -289,8 +289,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; SI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s32
@@ -306,8 +306,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; VI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s32
@@ -323,8 +323,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; GFX9-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -353,8 +353,8 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; SI-NEXT: %3:_(s32) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: $vgpr0 = COPY %3(s32)
;
; VI-LABEL: name: test_copysign_s32_s16
; VI: liveins: $vgpr0, $vgpr1
@@ -369,8 +369,8 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; VI-NEXT: %3:_(s32) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: $vgpr0 = COPY %3(s32)
;
; GFX9-LABEL: name: test_copysign_s32_s16
; GFX9: liveins: $vgpr0, $vgpr1
@@ -385,8 +385,8 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; GFX9-NEXT: %3:_(s32) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: $vgpr0 = COPY %3(s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
@@ -414,8 +414,8 @@ body: |
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; SI-NEXT: %3:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY %3(s64)
;
; VI-LABEL: name: test_copysign_s64_s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2
@@ -431,8 +431,8 @@ body: |
; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; VI-NEXT: %3:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY %3(s64)
;
; GFX9-LABEL: name: test_copysign_s64_s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
@@ -448,8 +448,8 @@ body: |
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
+ ; GFX9-NEXT: %3:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %3(s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
@@ -476,8 +476,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; SI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s64
@@ -493,8 +493,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; VI-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s64
@@ -510,8 +510,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; GFX9-NEXT: %3:_(s16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = COPY $vgpr1_vgpr2
@@ -543,8 +543,8 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BITCAST1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BITCAST]]
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY [[OR2]](<2 x s16>)
+ ; SI-NEXT: %2:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY %2(<2 x s16>)
;
; VI-LABEL: name: test_copysign_v2s16_v2s16
; VI: liveins: $vgpr0, $vgpr1
@@ -562,8 +562,8 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BITCAST1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BITCAST]]
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY [[OR2]](<2 x s16>)
+ ; VI-NEXT: %2:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY %2(<2 x s16>)
;
; GFX9-LABEL: name: test_copysign_v2s16_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
@@ -576,8 +576,8 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C1]](s16)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](<2 x s16>)
+ ; GFX9-NEXT: %2:_(<2 x s16>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY %2(<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_FCOPYSIGN %0, %1
@@ -601,8 +601,8 @@ body: |
; SI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ ; SI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
;
; VI-LABEL: name: test_copysign_v2s32_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -615,8 +615,8 @@ body: |
; VI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ ; VI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
;
; GFX9-LABEL: name: test_copysign_v2s32_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
@@ -629,8 +629,8 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ ; GFX9-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = G_FCOPYSIGN %0, %1
@@ -656,9 +656,9 @@ body: |
; SI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
+ ; SI-NEXT: %13:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: %14:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %13(s64), %14(s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; VI-LABEL: name: test_copysign_v2s64_v2s64
@@ -674,9 +674,9 @@ body: |
; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
+ ; VI-NEXT: %13:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: %14:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %13(s64), %14(s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; GFX9-LABEL: name: test_copysign_v2s64_v2s64
@@ -692,9 +692,9 @@ body: |
; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
+ ; GFX9-NEXT: %13:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: %14:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %13(s64), %14(s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
@@ -727,9 +727,9 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[C2]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; SI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
+ ; SI-NEXT: %17:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: %18:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %17(s64), %18(s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; VI-LABEL: name: test_copysign_v2s64_v2s32
@@ -751,9 +751,9 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[C2]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
+ ; VI-NEXT: %17:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: %18:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %17(s64), %18(s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
;
; GFX9-LABEL: name: test_copysign_v2s64_v2s32
@@ -775,9 +775,9 @@ body: |
; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
+ ; GFX9-NEXT: %17:_(s64) = disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: %18:_(s64) = disjoint G_OR [[AND1]], [[AND3]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %17(s64), %18(s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s32>) = COPY $vgpr4_vgpr5
@@ -811,8 +811,8 @@ body: |
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64)
; SI-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ ; SI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
;
; VI-LABEL: name: test_copysign_v2s32_v2s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
@@ -833,8 +833,8 @@ body: |
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64)
; VI-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ ; VI-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
;
; GFX9-LABEL: name: test_copysign_v2s32_v2s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
@@ -855,8 +855,8 @@ body: |
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64)
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
+ ; GFX9-NEXT: %2:_(<2 x s32>) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY %2(<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
%2:_(<2 x s32>) = G_FCOPYSIGN %0, %1
@@ -878,8 +878,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; SI-NEXT: %2:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: $vgpr0 = COPY %2(s32)
;
; VI-LABEL: name: test_copysign_s32_s32_flagss
; VI: liveins: $vgpr0, $vgpr1
@@ -890,8 +890,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; VI-NEXT: %2:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: $vgpr0 = COPY %2(s32)
;
; GFX9-LABEL: name: test_copysign_s32_s32_flagss
; GFX9: liveins: $vgpr0, $vgpr1
@@ -902,8 +902,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; GFX9-NEXT: %2:_(s32) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: $vgpr0 = COPY %2(s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = nnan G_FCOPYSIGN %0, %1
@@ -929,8 +929,8 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; SI-NEXT: %3:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; SI-NEXT: $vgpr0 = COPY %3(s32)
;
; VI-LABEL: name: test_copysign_s32_s16_flags
; VI: liveins: $vgpr0, $vgpr1
@@ -945,8 +945,8 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; VI-NEXT: %3:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; VI-NEXT: $vgpr0 = COPY %3(s32)
;
; GFX9-LABEL: name: test_copysign_s32_s16_flags
; GFX9: liveins: $vgpr0, $vgpr1
@@ -961,8 +961,8 @@ body: |
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
- ; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
+ ; GFX9-NEXT: %3:_(s32) = nnan disjoint G_OR [[AND]], [[AND2]]
+ ; GFX9-NEXT: $vgpr0 = COPY %3(s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
@@ -990,8 +990,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; SI-NEXT: %3:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; VI-LABEL: name: test_copysign_s16_s32_flags
@@ -1007,8 +1007,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; VI-NEXT: %3:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
;
; GFX9-LABEL: name: test_copysign_s16_s32_flags
@@ -1024,8 +1024,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; GFX9-NEXT: %3:_(s16) = nnan disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
index 8d110ab955dc8..d09034fd53eca 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
@@ -113,14 +113,12 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// EXTENDED-NEXT: enum {
// EXTENDED-NEXT: GILLT_s32,
// EXTENDED-NEXT: GILLT_i32,
-// EXTENDED-NEXT: GILLT_f32,
// EXTENDED-NEXT: GILLT_p0s32,
// EXTENDED-NEXT: };
-// EXTENDED-NEXT: const static size_t NumTypeObjects = 4;
+// EXTENDED-NEXT: const static size_t NumTypeObjects = 3;
// EXTENDED-NEXT: const static LLT TypeObjects[] = {
-// EXTENDED-NEXT: LLT(LLT::Kind::SCALAR, ElementCount::getFixed(0), 32),
+// EXTENDED-NEXT: LLT::scalar(32),
// EXTENDED-NEXT: LLT(LLT::Kind::INTEGER, ElementCount::getFixed(0), 32),
-// EXTENDED-NEXT: LLT(LLT::Kind::FLOAT, ElementCount::getFixed(0), 32, LLT::FpSemantics::S_IEEEsingle),
// EXTENDED-NEXT: LLT::pointer(0, 32),
// EXTENDED-NEXT: };
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
index 21f59753fb478..3a382c595eefc 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
@@ -270,12 +270,12 @@ TEST_F(AArch64GISelMITest, NarrowScalarCTLZ) {
auto CheckStr = R"(
CHECK: [[UNMERGE_LO:%[0-9]+]]:_(s32), [[UNMERGE_HI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %0:_(s64)
CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- CHECK: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UNMERGE_HI]]:_(s32), [[ZERO]]:_
+ CHECK: [[CMP:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[UNMERGE_HI]]:_(s32), [[ZERO]]:_
CHECK: [[CTLZ_LO:%[0-9]+]]:_(s32) = G_CTLZ [[UNMERGE_LO]]:_(s32)
CHECK: [[THIRTYTWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ_LO]]:_, [[THIRTYTWO]]:_
CHECK: [[CTLZ_HI:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UNMERGE_HI]]:_(s32)
- CHECK: %{{[0-9]+}}:_(s32) = G_SELECT [[CMP]]:_(s1), [[ADD]]:_, [[CTLZ_HI]]:_
+ CHECK: %{{[0-9]+}}:_(s32) = G_SELECT [[CMP]]:_(i1), [[ADD]]:_, [[CTLZ_HI]]:_
)";
// Check
@@ -1100,8 +1100,8 @@ TEST_F(AArch64GISelMITest, NarrowUADDO) {
CHECK: [[IMP_DEF1:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
CHECK: [[OP0_0:%[0-9]+]]:_(s32), [[OP0_1:%[0-9]+]]:_(s32), [[OP0_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF0]]
CHECK: [[OP1_0:%[0-9]+]]:_(s32), [[OP1_1:%[0-9]+]]:_(s32), [[OP1_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF1]]
- CHECK: [[UADDO0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(s1) = G_UADDO [[OP0_0]]:_, [[OP1_0]]:_
- CHECK: [[UADDO1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(s1) = G_UADDE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
+ CHECK: [[UADDO0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(i1) = G_UADDO [[OP0_0]]:_, [[OP1_0]]:_
+ CHECK: [[UADDO1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(i1) = G_UADDE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
CHECK: [[UADDO2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_UADDE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
CHECK: [[UADDO:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UADDO0]]:_(s32), [[UADDO1]]:_(s32), [[UADDO2]]:_(s32)
)";
@@ -1137,8 +1137,8 @@ TEST_F(AArch64GISelMITest, NarrowUSUBO) {
CHECK: [[IMP_DEF1:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
CHECK: [[OP0_0:%[0-9]+]]:_(s32), [[OP0_1:%[0-9]+]]:_(s32), [[OP0_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF0]]
CHECK: [[OP1_0:%[0-9]+]]:_(s32), [[OP1_1:%[0-9]+]]:_(s32), [[OP1_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF1]]
- CHECK: [[USUBO0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(s1) = G_USUBO [[OP0_0]]:_, [[OP1_0]]:_
- CHECK: [[USUBO1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(s1) = G_USUBE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
+ CHECK: [[USUBO0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(i1) = G_USUBO [[OP0_0]]:_, [[OP1_0]]:_
+ CHECK: [[USUBO1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(i1) = G_USUBE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
CHECK: [[USUBO2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_USUBE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
CHECK: [[USUBO:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[USUBO0]]:_(s32), [[USUBO1]]:_(s32), [[USUBO2]]:_(s32)
)";
@@ -1174,8 +1174,8 @@ TEST_F(AArch64GISelMITest, NarrowSADDO) {
CHECK: [[IMP_DEF1:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
CHECK: [[OP0_0:%[0-9]+]]:_(s32), [[OP0_1:%[0-9]+]]:_(s32), [[OP0_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF0]]
CHECK: [[OP1_0:%[0-9]+]]:_(s32), [[OP1_1:%[0-9]+]]:_(s32), [[OP1_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF1]]
- CHECK: [[SADDO0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(s1) = G_UADDO [[OP0_0]]:_, [[OP1_0]]:_
- CHECK: [[SADDO1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(s1) = G_UADDE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
+ CHECK: [[SADDO0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(i1) = G_UADDO [[OP0_0]]:_, [[OP1_0]]:_
+ CHECK: [[SADDO1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(i1) = G_UADDE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
CHECK: [[SADDO2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_SADDE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
CHECK: [[SADDO:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[SADDO0]]:_(s32), [[SADDO1]]:_(s32), [[SADDO2]]:_(s32)
)";
@@ -1211,8 +1211,8 @@ TEST_F(AArch64GISelMITest, NarrowSSUBO) {
CHECK: [[IMP_DEF1:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
CHECK: [[OP0_0:%[0-9]+]]:_(s32), [[OP0_1:%[0-9]+]]:_(s32), [[OP0_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF0]]
CHECK: [[OP1_0:%[0-9]+]]:_(s32), [[OP1_1:%[0-9]+]]:_(s32), [[OP1_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF1]]
- CHECK: [[SSUBO0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(s1) = G_USUBO [[OP0_0]]:_, [[OP1_0]]:_
- CHECK: [[SSUBO1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(s1) = G_USUBE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
+ CHECK: [[SSUBO0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(i1) = G_USUBO [[OP0_0]]:_, [[OP1_0]]:_
+ CHECK: [[SSUBO1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(i1) = G_USUBE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
CHECK: [[SSUBO2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_SSUBE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
CHECK: [[SSUBO:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[SSUBO0]]:_(s32), [[SSUBO1]]:_(s32), [[SSUBO2]]:_(s32)
)";
@@ -1250,8 +1250,8 @@ TEST_F(AArch64GISelMITest, NarrowUADDE) {
CHECK: [[IMP_DEF2:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
CHECK: [[OP0_0:%[0-9]+]]:_(s32), [[OP0_1:%[0-9]+]]:_(s32), [[OP0_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF0]]
CHECK: [[OP1_0:%[0-9]+]]:_(s32), [[OP1_1:%[0-9]+]]:_(s32), [[OP1_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF1]]
- CHECK: [[UADDE0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(s1) = G_UADDE [[OP0_0]]:_, [[OP1_0]]:_, [[IMP_DEF2]]:_
- CHECK: [[UADDE1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(s1) = G_UADDE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
+ CHECK: [[UADDE0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(i1) = G_UADDE [[OP0_0]]:_, [[OP1_0]]:_, [[IMP_DEF2]]:_
+ CHECK: [[UADDE1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(i1) = G_UADDE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
CHECK: [[UADDE2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_UADDE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
CHECK: [[UADDE:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UADDE0]]:_(s32), [[UADDE1]]:_(s32), [[UADDE2]]:_(s32)
)";
@@ -1289,8 +1289,8 @@ TEST_F(AArch64GISelMITest, NarrowUSUBE) {
CHECK: [[IMP_DEF2:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
CHECK: [[OP0_0:%[0-9]+]]:_(s32), [[OP0_1:%[0-9]+]]:_(s32), [[OP0_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF0]]
CHECK: [[OP1_0:%[0-9]+]]:_(s32), [[OP1_1:%[0-9]+]]:_(s32), [[OP1_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF1]]
- CHECK: [[USUBE0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(s1) = G_USUBE [[OP0_0]]:_, [[OP1_0]]:_, [[IMP_DEF2]]:_
- CHECK: [[USUBE1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(s1) = G_USUBE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
+ CHECK: [[USUBE0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(i1) = G_USUBE [[OP0_0]]:_, [[OP1_0]]:_, [[IMP_DEF2]]:_
+ CHECK: [[USUBE1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(i1) = G_USUBE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
CHECK: [[USUBE2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_USUBE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
CHECK: [[USUBE:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[USUBE0]]:_(s32), [[USUBE1]]:_(s32), [[USUBE2]]:_(s32)
)";
@@ -1328,8 +1328,8 @@ TEST_F(AArch64GISelMITest, NarrowSADDE) {
CHECK: [[IMP_DEF2:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
CHECK: [[OP0_0:%[0-9]+]]:_(s32), [[OP0_1:%[0-9]+]]:_(s32), [[OP0_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF0]]
CHECK: [[OP1_0:%[0-9]+]]:_(s32), [[OP1_1:%[0-9]+]]:_(s32), [[OP1_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF1]]
- CHECK: [[SADDE0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(s1) = G_UADDE [[OP0_0]]:_, [[OP1_0]]:_, [[IMP_DEF2]]:_
- CHECK: [[SADDE1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(s1) = G_UADDE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
+ CHECK: [[SADDE0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(i1) = G_UADDE [[OP0_0]]:_, [[OP1_0]]:_, [[IMP_DEF2]]:_
+ CHECK: [[SADDE1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(i1) = G_UADDE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
CHECK: [[SADDE2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_SADDE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
CHECK: [[SADDE:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[SADDE0]]:_(s32), [[SADDE1]]:_(s32), [[SADDE2]]:_(s32)
)";
@@ -1367,8 +1367,8 @@ TEST_F(AArch64GISelMITest, NarrowSSUBE) {
CHECK: [[IMP_DEF2:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
CHECK: [[OP0_0:%[0-9]+]]:_(s32), [[OP0_1:%[0-9]+]]:_(s32), [[OP0_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF0]]
CHECK: [[OP1_0:%[0-9]+]]:_(s32), [[OP1_1:%[0-9]+]]:_(s32), [[OP1_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[IMP_DEF1]]
- CHECK: [[SSUBE0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(s1) = G_USUBE [[OP0_0]]:_, [[OP1_0]]:_, [[IMP_DEF2]]:_
- CHECK: [[SSUBE1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(s1) = G_USUBE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
+ CHECK: [[SSUBE0:%[0-9]+]]:_(s32), [[CARRY0:%[0-9]+]]:_(i1) = G_USUBE [[OP0_0]]:_, [[OP1_0]]:_, [[IMP_DEF2]]:_
+ CHECK: [[SSUBE1:%[0-9]+]]:_(s32), [[CARRY1:%[0-9]+]]:_(i1) = G_USUBE [[OP0_1]]:_, [[OP1_1]]:_, [[CARRY0]]:_
CHECK: [[SSUBE2:%[0-9]+]]:_(s32), [[CARRY2:%[0-9]+]]:_(s1) = G_SSUBE [[OP0_2]]:_, [[OP1_2]]:_, [[CARRY1]]:_
CHECK: [[SSUBE:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[SSUBE0]]:_(s32), [[SSUBE1]]:_(s32), [[SSUBE2]]:_(s32)
)";
@@ -3446,8 +3446,8 @@ TEST_F(AArch64GISelMITest, LowerSelect) {
// Declare your legalization info
DefineLegalizerInfo(A, { getActionDefinitionsBuilder(G_SELECT).lower(); });
- LLT S1 = LLT::scalar(1);
- LLT S32 = LLT::scalar(32);
+ LLT S1 = LLT::integer(1);
+ LLT S32 = LLT::integer(32);
auto Tst = B.buildTrunc(S1, Copies[0]);
auto SrcA = B.buildTrunc(S32, Copies[1]);
auto SrcB = B.buildTrunc(S32, Copies[2]);
@@ -3461,15 +3461,15 @@ TEST_F(AArch64GISelMITest, LowerSelect) {
Helper.lower(*SELECT, 0, S32));
auto CheckStr = R"(
- CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC
- CHECK: [[TRUE:%[0-9]+]]:_(s32) = G_TRUNC
- CHECK: [[FALSE:%[0-9]+]]:_(s32) = G_TRUNC
- CHECK: [[MSK:%[0-9]+]]:_(s32) = G_SEXT [[TST]]
- CHECK: [[M:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- CHECK: [[NEGMSK:%[0-9]+]]:_(s32) = G_XOR [[MSK]]:_, [[M]]:_
- CHECK: [[TVAL:%[0-9]+]]:_(s32) = G_AND [[TRUE]]:_, [[MSK]]:_
- CHECK: [[FVAL:%[0-9]+]]:_(s32) = G_AND [[FALSE]]:_, [[NEGMSK]]:_
- CHECK: [[RES:%[0-9]+]]:_(s32) = G_OR [[TVAL]]:_, [[FVAL]]:_
+ CHECK: [[TST:%[0-9]+]]:_(i1) = G_TRUNC
+ CHECK: [[TRUE:%[0-9]+]]:_(i32) = G_TRUNC
+ CHECK: [[FALSE:%[0-9]+]]:_(i32) = G_TRUNC
+ CHECK: [[MSK:%[0-9]+]]:_(i32) = G_SEXT [[TST]]
+ CHECK: [[M:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1
+ CHECK: [[NEGMSK:%[0-9]+]]:_(i32) = G_XOR [[MSK]]:_, [[M]]:_
+ CHECK: [[TVAL:%[0-9]+]]:_(i32) = G_AND [[TRUE]]:_, [[MSK]]:_
+ CHECK: [[FVAL:%[0-9]+]]:_(i32) = G_AND [[FALSE]]:_, [[NEGMSK]]:_
+ CHECK: [[RES:%[0-9]+]]:_(i32) = G_OR [[TVAL]]:_, [[FVAL]]:_
)";
// Check
@@ -4102,9 +4102,9 @@ TEST_F(AArch64GISelMITest, widenScalarUnmerge) {
DefineLegalizerInfo(A, {});
- LLT S96{LLT::scalar(96)};
- LLT S64{LLT::scalar(64)};
- LLT S48{LLT::scalar(48)};
+ LLT S96{LLT::integer(96)};
+ LLT S64{LLT::integer(64)};
+ LLT S48{LLT::integer(48)};
auto Src = B.buildAnyExt(S96, Copies[0]);
auto Unmerge = B.buildUnmerge(S48, Src);
@@ -4116,7 +4116,7 @@ TEST_F(AArch64GISelMITest, widenScalarUnmerge) {
// Perform Legalization
B.setInsertPt(*EntryMBB, Unmerge->getIterator());
- // This should create unmerges to a GCD type (S16), then remerge to S48
+ // This should create unmerges to a GCD type (i16), then remerge to i48
EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
Helper.widenScalar(*Unmerge, 0, S64));
@@ -4124,14 +4124,14 @@ TEST_F(AArch64GISelMITest, widenScalarUnmerge) {
CHECK: [[COPY0:%[0-9]+]]:_(s64) = COPY
CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY
CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY
- CHECK: [[ANYEXT:%[0-9]+]]:_(s96) = G_ANYEXT [[COPY0]]
+ CHECK: [[ANYEXT:%[0-9]+]]:_(i96) = G_ANYEXT [[COPY0]]
CHECK: [[ANYEXT1:%[0-9]+]]:_(s192) = G_ANYEXT [[ANYEXT]]
- CHECK: [[UNMERGE:%[0-9]+]]:_(s64), [[UNMERGE1:%[0-9]+]]:_(s64), [[UNMERGE2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT1]]
- CHECK: [[UNMERGE3:%[0-9]+]]:_(s16), [[UNMERGE4:%[0-9]+]]:_(s16), [[UNMERGE5:%[0-9]+]]:_(s16), [[UNMERGE6:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[UNMERGE]]
- CHECK: [[UNMERGE7:%[0-9]+]]:_(s16), [[UNMERGE8:%[0-9]+]]:_(s16), [[UNMERGE9:%[0-9]+]]:_(s16), [[UNMERGE10:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[UNMERGE1]]
- CHECK: [[UNMERGE11:%[0-9]+]]:_(s16), [[UNMERGE12:%[0-9]+]]:_(s16), [[UNMERGE13:%[0-9]+]]:_(s16), [[UNMERGE14:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[UNMERGE2]]
- CHECK: [[MERGE:%[0-9]+]]:_(s48) = G_MERGE_VALUES [[UNMERGE3]]:_(s16), [[UNMERGE4]]:_(s16), [[UNMERGE5]]:_(s16)
- CHECK: [[MERGE1:%[0-9]+]]:_(s48) = G_MERGE_VALUES [[UNMERGE6]]:_(s16), [[UNMERGE7]]:_(s16), [[UNMERGE8]]:_(s16)
+ CHECK: [[UNMERGE:%[0-9]+]]:_(i64), [[UNMERGE1:%[0-9]+]]:_(i64), [[UNMERGE2:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT1]]
+ CHECK: [[UNMERGE3:%[0-9]+]]:_(i16), [[UNMERGE4:%[0-9]+]]:_(i16), [[UNMERGE5:%[0-9]+]]:_(i16), [[UNMERGE6:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[UNMERGE]]
+ CHECK: [[UNMERGE7:%[0-9]+]]:_(i16), [[UNMERGE8:%[0-9]+]]:_(i16), [[UNMERGE9:%[0-9]+]]:_(i16), [[UNMERGE10:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[UNMERGE1]]
+ CHECK: [[UNMERGE11:%[0-9]+]]:_(i16), [[UNMERGE12:%[0-9]+]]:_(i16), [[UNMERGE13:%[0-9]+]]:_(i16), [[UNMERGE14:%[0-9]+]]:_(i16) = G_UNMERGE_VALUES [[UNMERGE2]]
+ CHECK: [[MERGE:%[0-9]+]]:_(i48) = G_MERGE_VALUES [[UNMERGE3]]:_(i16), [[UNMERGE4]]:_(i16), [[UNMERGE5]]:_(i16)
+ CHECK: [[MERGE1:%[0-9]+]]:_(i48) = G_MERGE_VALUES [[UNMERGE6]]:_(i16), [[UNMERGE7]]:_(i16), [[UNMERGE8]]:_(i16)
)";
// Check
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 7e585c1e74b69..238d76326b588 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -2500,7 +2500,7 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
// Skip any patterns containing BF16 types, as GISel cannot currently tell
// the difference between fp16 and bf16. FIXME: This can be removed once
- // BF16 is supported properly.
+ // UseExtended are universally supported.
bool UseExtended = LLT::getUseExtended();
if (hasBFloatType(Pat.getSrcPattern()) && !UseExtended)
continue;
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