[llvm] [AMDGPU] SIFoldOperands: Add REQ_SEQUENCE subregister use fold (PR #188451)
Frederik Harwath via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 15 02:09:42 PDT 2026
https://github.com/frederik-h updated https://github.com/llvm/llvm-project/pull/188451
>From dd40047222596df1c6f04264d336e4c33e12e34a Mon Sep 17 00:00:00 2001
From: Frederik Harwath <fharwath at amd.com>
Date: Wed, 25 Mar 2026 10:47:41 +0000
Subject: [PATCH 1/2] [AMDGPU] SIFoldOperands: Add REQ_SEQUENCE subregister use
fold
Replace uses of subregisters of REG_SEQUENCE instructions by
uses of copies of the subregisters and try to fold those
uses into their users. This frees later passes such as
the si-peephole-sdwa pass from the responsibility to deal
with REG_SEQUENCE instructions.
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 92 ++-
.../test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll | 190 ++---
.../atomic_optimizations_global_pointer.ll | 28 +-
.../branch-folding-implicit-def-subreg.ll | 446 +++++------
...ug-multi-operands-to-update-after-fold.mir | 1 -
llvm/test/CodeGen/AMDGPU/div_i128.ll | 84 +--
llvm/test/CodeGen/AMDGPU/div_v2i128.ll | 711 +++++++++---------
llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir | 5 +-
.../AMDGPU/fold-operands-frame-index.mir | 1 -
llvm/test/CodeGen/AMDGPU/fold-readlane.mir | 220 +++---
.../fold-zero-high-bits-skips-non-reg.mir | 1 -
llvm/test/CodeGen/AMDGPU/fptoi.i128.ll | 68 +-
llvm/test/CodeGen/AMDGPU/frem.ll | 120 ++-
llvm/test/CodeGen/AMDGPU/idiv-licm.ll | 50 +-
.../CodeGen/AMDGPU/image-sample-waterfall.ll | 112 +--
...e92561-restore-undef-scc-verifier-error.ll | 56 +-
llvm/test/CodeGen/AMDGPU/itofp.i128.ll | 54 +-
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 42 +-
llvm/test/CodeGen/AMDGPU/load-global-i16.ll | 112 +--
llvm/test/CodeGen/AMDGPU/load-global-i8.ll | 22 +-
llvm/test/CodeGen/AMDGPU/load-local-i16.ll | 628 ++++++++--------
.../loop-live-out-copy-undef-subrange.ll | 6 +-
.../CodeGen/AMDGPU/memintrinsic-unroll.ll | 2 +-
.../AMDGPU/memset-param-combinations.ll | 227 ++----
.../CodeGen/AMDGPU/misched-remat-revert.ll | 2 +-
.../CodeGen/AMDGPU/mubuf-legalize-operands.ll | 65 +-
.../CodeGen/AMDGPU/no-fold-accvgpr-read.mir | 11 +-
.../CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir | 11 +-
.../AMDGPU/promote-constOffset-to-imm.ll | 98 +--
llvm/test/CodeGen/AMDGPU/rem_i128.ll | 175 +++--
llvm/test/CodeGen/AMDGPU/sdiv64.ll | 87 +--
.../AMDGPU/sdwa-peephole-reg-sequence.mir | 114 +++
.../si-fold-operands-subreg-imm.gfx942.mir | 8 +-
.../AMDGPU/si-fold-operands-subreg-imm.mir | 1 -
llvm/test/CodeGen/AMDGPU/srem64.ll | 42 +-
llvm/test/CodeGen/AMDGPU/true16-fold.mir | 1 -
...r-descriptor-waterfall-loop-idom-update.ll | 17 +-
llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll | 18 +-
llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll | 8 +-
.../test/CodeGen/AMDGPU/vni8-across-blocks.ll | 344 ++++-----
.../CodeGen/AMDGPU/waterfall_kills_scc.ll | 23 +-
41 files changed, 2213 insertions(+), 2090 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/sdwa-peephole-reg-sequence.mir
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index a2fe31bd849c3..95f8e75e3f365 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -257,6 +257,8 @@ class SIFoldOperandsImpl {
std::pair<const MachineOperand *, int> isOMod(const MachineInstr &MI) const;
bool tryFoldOMod(MachineInstr &MI);
bool tryFoldRegSequence(MachineInstr &MI);
+ bool tryFoldRegSequenceSubRegUses(MachineInstr &MI,
+ MachineOperand *&CurrentKnownM0Val);
bool tryFoldPhiAGPR(MachineInstr &MI);
bool tryFoldLoad(MachineInstr &MI);
@@ -2359,6 +2361,92 @@ bool SIFoldOperandsImpl::tryFoldOMod(MachineInstr &MI) {
return true;
}
+/// This function tries to replace uses of REG_SEQUENCE subregisters
+/// by uses of copies of the corresponding REG_SEQUENCE inputs. It
+/// tries to fold the copies into their users and removes the
+/// REG_SEQUENCE if no users are left. This helps later optimizations
+/// which might not support REG_SEQUENCE instructions,
+/// e.g. si-peephole-sdwa.
+bool SIFoldOperandsImpl::tryFoldRegSequenceSubRegUses(
+ MachineInstr &MI, MachineOperand *&CurrentKnownM0Val) {
+ assert(MI.isRegSequence());
+
+ Register Reg = MI.getOperand(0).getReg();
+
+ LLVM_DEBUG(dbgs() << "\nMI: " << MI);
+ using DefPair = std::pair<MachineOperand *, unsigned>;
+ SmallVector<DefPair, 16> Defs;
+
+ const TargetRegisterClass *InputRC = getRegSeqInit(Defs, Reg);
+ if (!InputRC) {
+ LLVM_DEBUG(
+ dbgs() << "Failed to infer uniform register class for REG_SEQUENCE.\n");
+ return false;
+ }
+ assert(Defs.size() == (MI.getNumExplicitOperands() - 1) / 2 &&
+ "Must contain def for each REG_SEQUENCE input operand.");
+
+ bool Changed = false;
+ for (auto UseIt = MRI->use_nodbg_begin(Reg), End = MRI->use_nodbg_end();
+ UseIt != End;) {
+ MachineOperand &Use = *UseIt++;
+ MachineInstr *UseMI = Use.getParent();
+ if (UseMI->isCopyLike() || UseMI->isRegSequence())
+ continue;
+
+ unsigned UseSubReg = Use.getSubReg();
+ if (UseSubReg == 0)
+ continue;
+
+ LLVM_DEBUG(dbgs() << "Use: " << Use << '\n');
+ LLVM_DEBUG(dbgs() << "User: " << *UseMI);
+
+ // V_MOVRELS_B32_e32 requires its first source operand to be a
+ // subreg of a vector provided as an implicit operand. Without
+ // further ado, the transformation would violate this.
+ Register UseReg = Use.getReg();
+ if (UseMI->hasRegisterImplicitUseOperand(UseReg))
+ continue;
+
+ // The lookup can fail, for instance, if the use refers to a
+ // subregister of a subregister.
+ // TODO Handle subregister composition. See also getRegSeqInits.
+ auto *It =
+ find_if(Defs, [=](const DefPair &P) { return P.second == UseSubReg; });
+ if (It == Defs.end() || !It->first) {
+ LLVM_DEBUG(dbgs() << "Could not resolve subregister definition.\n");
+ continue;
+ }
+
+ MachineOperand *DefOp = It->first;
+ LLVM_DEBUG(dbgs() << "Resolved definition to: " << *DefOp << '\n');
+ if (DefOp->isImm() || MRI->getVRegDef(DefOp->getReg())->isCopy())
+ continue;
+
+ Register CopyDst = MRI->createVirtualRegister(InputRC);
+ const MCInstrDesc &CopyDesc = TII->get(AMDGPU::COPY);
+ MachineInstr *CopyMI = BuildMI(*UseMI->getParent(), UseMI,
+ UseMI->getDebugLoc(), CopyDesc, CopyDst)
+ .add(*DefOp);
+ CopyMI->getOperand(1).setIsKill(false);
+
+ LLVM_DEBUG(dbgs() << "Created Copy: " << *CopyMI);
+ Use.ChangeToRegister(CopyDst, false);
+ Use.setSubReg(0);
+ LLVM_DEBUG(dbgs() << "Modified Use: " << *UseMI);
+ Changed = true;
+
+ tryFoldFoldableCopy(*CopyMI, CurrentKnownM0Val);
+ }
+
+ if (MRI->hasAtMostUserInstrs(Reg, 0)) {
+ LLVM_DEBUG(dbgs() << "Removing REG_SEQUENCE which is dead after fold.\n");
+ MI.removeFromParent();
+ }
+
+ return Changed;
+}
+
// Try to fold a reg_sequence with vgpr output and agpr inputs into an
// instruction which can take an agpr. So far that means a store.
bool SIFoldOperandsImpl::tryFoldRegSequence(MachineInstr &MI) {
@@ -2787,7 +2875,9 @@ bool SIFoldOperandsImpl::run(MachineFunction &MF) {
continue;
}
- if (MI.isRegSequence() && tryFoldRegSequence(MI)) {
+ if (MI.isRegSequence() &&
+ (tryFoldRegSequence(MI) ||
+ tryFoldRegSequenceSubRegUses(MI, CurrentKnownM0Val))) {
Changed = true;
continue;
}
diff --git a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
index 3dac24ed89fa0..69a5a06715828 100644
--- a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
@@ -952,12 +952,12 @@ define void @flat_atomic_xchg_i64_ret_av_av(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_xchg_i64_ret_av_av:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ; def v[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -966,23 +966,23 @@ define void @flat_atomic_xchg_i64_ret_av_av(ptr %ptr) #0 {
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[4:5], v[2:3] glc
+; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol
-; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: .LBB14_2: ; %Flow
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB14_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
-; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
+; GFX90A-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_nop 0
-; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB14_4: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: s_waitcnt vmcnt(2)
@@ -1044,12 +1044,12 @@ define void @flat_atomic_xchg_i64_ret_av_v(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_xchg_i64_ret_av_v:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ; def v[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -1058,23 +1058,23 @@ define void @flat_atomic_xchg_i64_ret_av_v(ptr %ptr) #0 {
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[4:5], v[2:3] glc
+; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol
-; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: .LBB15_2: ; %Flow
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB15_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
-; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
+; GFX90A-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_nop 0
-; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB15_4: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: s_waitcnt vmcnt(2)
@@ -1328,12 +1328,12 @@ define void @flat_atomic_xchg_i64_ret_v_av(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_xchg_i64_ret_v_av:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ; def v[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -1342,23 +1342,23 @@ define void @flat_atomic_xchg_i64_ret_v_av(ptr %ptr) #0 {
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
; GFX90A-NEXT: buffer_wbl2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[4:5], v[2:3] glc
+; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: buffer_invl2
; GFX90A-NEXT: buffer_wbinvl1_vol
-; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: .LBB18_2: ; %Flow
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB18_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
-; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
+; GFX90A-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_nop 0
-; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB18_4: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: s_waitcnt vmcnt(2)
@@ -6512,35 +6512,35 @@ define void @flat_atomic_add_i64_ret_av_av(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_add_i64_ret_av_av:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ; def v[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB90_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_atomic_add_x2 v[0:1], v[4:5], v[2:3] glc
+; GFX90A-NEXT: flat_atomic_add_x2 v[0:1], v[2:3], v[4:5] glc
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: .LBB90_2: ; %Flow
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB90_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
-; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
+; GFX90A-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2
-; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc
-; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v0, v4
+; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v1, v5, vcc
+; GFX90A-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB90_4: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -6697,35 +6697,35 @@ define void @flat_atomic_sub_i64_ret_av_av(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_sub_i64_ret_av_av:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ; def v[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB92_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_atomic_sub_x2 v[0:1], v[4:5], v[2:3] glc
+; GFX90A-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3], v[4:5] glc
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: .LBB92_2: ; %Flow
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB92_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; GFX90A-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
-; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
+; GFX90A-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_sub_co_u32_e32 v2, vcc, v0, v2
-; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
-; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; GFX90A-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
+; GFX90A-NEXT: v_sub_co_u32_e32 v3, vcc, v0, v4
+; GFX90A-NEXT: v_subb_co_u32_e32 v4, vcc, v1, v5, vcc
+; GFX90A-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen
+; GFX90A-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: .LBB92_4: ; %atomicrmw.phi
; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -8984,28 +8984,28 @@ define void @flat_atomic_usub_sat_i64_ret_av_av(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_usub_sat_i64_ret_av_av:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v7
+; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:5]
+; GFX90A-NEXT: ; def v[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB114_4
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[6:7]
+; GFX90A-NEXT: flat_load_dwordx2 v[2:3], v[4:5]
; GFX90A-NEXT: s_mov_b64 s[6:7], 0
; GFX90A-NEXT: .LBB114_2: ; %atomicrmw.start
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_sub_co_u32_e32 v0, vcc, v2, v4
-; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v5, vcc
+; GFX90A-NEXT: v_sub_co_u32_e32 v0, vcc, v2, v6
+; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v7, vcc
; GFX90A-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX90A-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:7], v[0:3] glc
+; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
; GFX90A-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
@@ -9014,20 +9014,20 @@ define void @flat_atomic_usub_sat_i64_ret_av_av(ptr %ptr) #0 {
; GFX90A-NEXT: s_cbranch_execnz .LBB114_2
; GFX90A-NEXT: ; %bb.3: ; %Flow
; GFX90A-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX90A-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX90A-NEXT: .LBB114_4: ; %Flow3
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB114_6
; GFX90A-NEXT: ; %bb.5: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
; GFX90A-NEXT: buffer_load_dword v0, v2, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(1)
-; GFX90A-NEXT: v_sub_co_u32_e32 v3, vcc, v0, v4
+; GFX90A-NEXT: v_sub_co_u32_e32 v3, vcc, v0, v6
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_subb_co_u32_e32 v4, vcc, v1, v5, vcc
+; GFX90A-NEXT: v_subb_co_u32_e32 v4, vcc, v1, v7, vcc
; GFX90A-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc
; GFX90A-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
; GFX90A-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen
@@ -10516,31 +10516,31 @@ define void @flat_atomic_fmax_f64_ret_av_av(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_fmax_f64_ret_av_av:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ; def v[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB132_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_atomic_max_f64 v[0:1], v[4:5], v[2:3] glc
+; GFX90A-NEXT: flat_atomic_max_f64 v[0:1], v[2:3], v[4:5] glc
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: .LBB132_2: ; %Flow
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB132_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; GFX90A-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v6, -1, v2, vcc
; GFX90A-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
-; GFX90A-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX90A-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
; GFX90A-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
@@ -10704,31 +10704,31 @@ define void @flat_atomic_fmin_f64_ret_av_av(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_fmin_f64_ret_av_av:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x50, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x50, v0
; GFX90A-NEXT: s_mov_b64 s[4:5], src_private_base
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v5
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, s5, v3
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ; def v[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB134_2
; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global
-; GFX90A-NEXT: flat_atomic_min_f64 v[0:1], v[4:5], v[2:3] glc
+; GFX90A-NEXT: flat_atomic_min_f64 v[0:1], v[2:3], v[4:5] glc
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: .LBB134_2: ; %Flow
; GFX90A-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX90A-NEXT: s_cbranch_execz .LBB134_4
; GFX90A-NEXT: ; %bb.3: ; %atomicrmw.private
-; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; GFX90A-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc
+; GFX90A-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GFX90A-NEXT: v_cndmask_b32_e32 v6, -1, v2, vcc
; GFX90A-NEXT: buffer_load_dword v0, v6, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v1, v6, s[0:3], 0 offen offset:4
-; GFX90A-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX90A-NEXT: v_max_f64 v[2:3], v[4:5], v[4:5]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_max_f64 v[4:5], v[0:1], v[0:1]
; GFX90A-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index fbc8b812d96c9..f5133ac9c2ed6 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -5547,10 +5547,10 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX7LESS-NEXT: ; %bb.1:
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX7LESS-NEXT: s_bcnt1_i32_b64 s12, s[6:7]
; GFX7LESS-NEXT: s_mov_b64 s[10:11], 0
; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000
-; GFX7LESS-NEXT: s_mul_i32 s12, s6, 5
+; GFX7LESS-NEXT: s_mul_i32 s12, s12, 5
; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0)
; GFX7LESS-NEXT: v_mov_b32_e32 v0, s4
; GFX7LESS-NEXT: v_mov_b32_e32 v1, s5
@@ -5606,10 +5606,10 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX8-NEXT: ; %bb.1:
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX8-NEXT: s_bcnt1_i32_b64 s12, s[6:7]
; GFX8-NEXT: s_mov_b64 s[10:11], 0
; GFX8-NEXT: s_mov_b32 s7, 0xf000
-; GFX8-NEXT: s_mul_i32 s12, s6, 5
+; GFX8-NEXT: s_mul_i32 s12, s12, 5
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5
@@ -5663,10 +5663,10 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX9-NEXT: s_bcnt1_i32_b64 s12, s[6:7]
; GFX9-NEXT: s_mov_b64 s[10:11], 0
; GFX9-NEXT: s_mov_b32 s7, 0xf000
-; GFX9-NEXT: s_mul_i32 s12, s6, 5
+; GFX9-NEXT: s_mul_i32 s12, s12, 5
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
@@ -5720,9 +5720,9 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1064-NEXT: s_bcnt1_i32_b64 s12, s[6:7]
; GFX1064-NEXT: s_mov_b64 s[10:11], 0
-; GFX1064-NEXT: s_mul_i32 s12, s6, 5
+; GFX1064-NEXT: s_mul_i32 s12, s12, 5
; GFX1064-NEXT: s_mov_b32 s7, 0x31016000
; GFX1064-NEXT: s_mov_b32 s6, -1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
@@ -5777,9 +5777,9 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GFX1032-NEXT: s_bcnt1_i32_b32 s6, s6
+; GFX1032-NEXT: s_bcnt1_i32_b32 s10, s6
; GFX1032-NEXT: s_mov_b32 s7, 0x31016000
-; GFX1032-NEXT: s_mul_i32 s10, s6, 5
+; GFX1032-NEXT: s_mul_i32 s10, s10, 5
; GFX1032-NEXT: s_mov_b32 s6, -1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mov_b32_e32 v0, s4
@@ -5834,9 +5834,9 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1164-NEXT: ; %bb.1:
; GFX1164-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-NEXT: s_load_b64 s[4:5], s[2:3], 0x0
-; GFX1164-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1164-NEXT: s_bcnt1_i32_b64 s12, s[6:7]
; GFX1164-NEXT: s_mov_b64 s[10:11], 0
-; GFX1164-NEXT: s_mul_i32 s12, s6, 5
+; GFX1164-NEXT: s_mul_i32 s12, s12, 5
; GFX1164-NEXT: s_mov_b32 s7, 0x31016000
; GFX1164-NEXT: s_mov_b32 s6, -1
; GFX1164-NEXT: s_waitcnt lgkmcnt(0)
@@ -5899,9 +5899,9 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1132-NEXT: ; %bb.1:
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: s_load_b64 s[4:5], s[2:3], 0x0
-; GFX1132-NEXT: s_bcnt1_i32_b32 s6, s6
+; GFX1132-NEXT: s_bcnt1_i32_b32 s10, s6
; GFX1132-NEXT: s_mov_b32 s7, 0x31016000
-; GFX1132-NEXT: s_mul_i32 s10, s6, 5
+; GFX1132-NEXT: s_mul_i32 s10, s10, 5
; GFX1132-NEXT: s_mov_b32 s6, -1
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
diff --git a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
index e0b83eeaa0faa..c91133a7de9b1 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
@@ -42,31 +42,31 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: successors: %bb.3(0x80000000)
; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr56, $sgpr57, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr4, $vgpr5
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF implicit-def $vgpr16
+ ; GFX90A-NEXT: renamable $vgpr15 = IMPLICIT_DEF implicit-def $vgpr14
; GFX90A-NEXT: renamable $vgpr3 = IMPLICIT_DEF implicit-def $vgpr2
+ ; GFX90A-NEXT: renamable $vgpr25 = IMPLICIT_DEF implicit-def $vgpr24
; GFX90A-NEXT: renamable $vgpr27 = IMPLICIT_DEF implicit-def $vgpr26
; GFX90A-NEXT: renamable $vgpr29 = IMPLICIT_DEF implicit-def $vgpr28
- ; GFX90A-NEXT: renamable $vgpr33 = IMPLICIT_DEF implicit-def $vgpr32
; GFX90A-NEXT: renamable $sgpr36_sgpr37 = S_MOV_B64 0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.3.Flow17:
; GFX90A-NEXT: successors: %bb.4(0x40000000), %bb.57(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr16_vgpr17:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr6 = V_AND_B32_e32 1023, $vgpr31, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr30 = V_AND_B32_e32 1023, $vgpr31, implicit $exec
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr18_sgpr19, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCZ %bb.57, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.4.bb15:
; GFX90A-NEXT: successors: %bb.35(0x40000000), %bb.5(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr4_vgpr5:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = nsw V_LSHLREV_B64_e64 2, $vgpr4_vgpr5, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = COPY renamable $sgpr25, implicit $exec
; GFX90A-NEXT: renamable $vgpr46, renamable $vcc = V_ADD_CO_U32_e64 $sgpr24, $vgpr0, 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr47, dead renamable $vcc = V_ADDC_U32_e64 killed $vgpr2, killed $vgpr1, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 2, $vgpr6, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 2, $vgpr30, implicit $exec
; GFX90A-NEXT: renamable $vgpr40, renamable $vcc = V_ADD_CO_U32_e64 $vgpr46, killed $vgpr0, 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr41, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr47, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, renamable $sgpr30_sgpr31, implicit-def dead $scc
@@ -74,7 +74,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.5:
; GFX90A-NEXT: successors: %bb.6(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr34_sgpr35 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_MOV_B64 0
@@ -87,9 +87,9 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr38_sgpr39 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
@@ -97,32 +97,32 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr56_vgpr57 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr44_vgpr45 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr42_vgpr43 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.6.Flow20:
; GFX90A-NEXT: successors: %bb.7(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: renamable $vgpr24 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr26 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr28 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr32 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr33 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr17 = COPY killed renamable $sgpr18, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr29 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr15 = COPY killed renamable $sgpr18, implicit $exec
; GFX90A-NEXT: renamable $vgpr3 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr25 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr27 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr29 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.7.Flow19:
; GFX90A-NEXT: successors: %bb.62(0x40000000), %bb.8(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000F, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000F, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_MOV_B64 0
; GFX90A-NEXT: $sgpr18_sgpr19 = S_AND_SAVEEXEC_B64 $sgpr36_sgpr37, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -130,7 +130,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.8.Flow32:
; GFX90A-NEXT: successors: %bb.9(0x40000000), %bb.10(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr18_sgpr19, implicit-def $scc
; GFX90A-NEXT: $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $sgpr40_sgpr41, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -139,15 +139,15 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.9.bb89:
; GFX90A-NEXT: successors: %bb.10(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_OR_B64 killed renamable $sgpr68_sgpr69, $exec, implicit-def dead $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.10.Flow33:
; GFX90A-NEXT: successors: %bb.11(0x40000000), %bb.12(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def $scc
; GFX90A-NEXT: $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $sgpr46_sgpr47, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -156,15 +156,15 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.11.bb84:
; GFX90A-NEXT: successors: %bb.12(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_OR_B64 killed renamable $sgpr68_sgpr69, $exec, implicit-def dead $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.12.Flow34:
; GFX90A-NEXT: successors: %bb.13(0x40000000), %bb.14(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def $scc
; GFX90A-NEXT: $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $sgpr44_sgpr45, implicit-def $exec, implicit-def $scc, implicit $exec
@@ -173,10 +173,10 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.13.bb79:
; GFX90A-NEXT: successors: %bb.14(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr42_sgpr43, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
- ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET renamable $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
+ ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_OR_B64 killed renamable $sgpr68_sgpr69, $exec, implicit-def dead $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.14.Flow35:
@@ -358,7 +358,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.35.bb20:
; GFX90A-NEXT: successors: %bb.37(0x40000000), %bb.36(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr0 = FLAT_LOAD_SBYTE renamable $vgpr40_vgpr41, 1024, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i23)
; GFX90A-NEXT: renamable $vgpr42 = V_ADD_CO_U32_e32 1024, $vgpr40, implicit-def $vcc, implicit $exec
@@ -375,37 +375,37 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr43, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_LT_I16_e64 0, killed $vgpr0, implicit $exec
; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr58_vgpr59 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr56_vgpr57 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr44_vgpr45 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr24_sgpr25 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.37, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.36.Flow21:
; GFX90A-NEXT: successors: %bb.6(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr24_sgpr25, implicit-def $scc
; GFX90A-NEXT: S_BRANCH %bb.6
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.37.bb27:
; GFX90A-NEXT: successors: %bb.39(0x40000000), %bb.38(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41, $sgpr46_sgpr47, $sgpr44_sgpr45, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr66_sgpr67, $sgpr48_sgpr49
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr40_sgpr41, $sgpr46_sgpr47, $sgpr44_sgpr45, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr66_sgpr67, $sgpr48_sgpr49
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr0 = FLAT_LOAD_UBYTE renamable $vgpr40_vgpr41, 2048, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i30)
; GFX90A-NEXT: renamable $vgpr44 = V_ADD_CO_U32_e32 2048, $vgpr40, implicit-def $vcc, implicit $exec
@@ -415,29 +415,29 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $sgpr62_sgpr63 = S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr45, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr58_vgpr59 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr56_vgpr57 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr38_sgpr39 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.39, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.38.Flow22:
; GFX90A-NEXT: successors: %bb.36(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr38_sgpr39, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr38_sgpr39 = S_XOR_B64 $exec, -1, implicit-def dead $scc
@@ -458,7 +458,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.39.bb34:
; GFX90A-NEXT: successors: %bb.41(0x40000000), %bb.40(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr46_sgpr47, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr66_sgpr67
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr46_sgpr47, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr52_sgpr53, $sgpr66_sgpr67
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr0 = FLAT_LOAD_UBYTE renamable $vgpr40_vgpr41, 3072, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i37)
; GFX90A-NEXT: renamable $vgpr56 = V_ADD_CO_U32_e32 3072, $vgpr40, implicit-def $vcc, implicit $exec
@@ -468,28 +468,28 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr57, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr58_vgpr59 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr40_sgpr41 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.41, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.40.Flow23:
; GFX90A-NEXT: successors: %bb.38(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr68_sgpr69, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr68_sgpr69, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr40_sgpr41, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr42_sgpr43 = S_XOR_B64 $exec, -1, implicit-def dead $scc
@@ -509,7 +509,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.41.bb41:
; GFX90A-NEXT: successors: %bb.46(0x40000000), %bb.42(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr52_sgpr53, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr66_sgpr67, $sgpr68_sgpr69
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr52_sgpr53, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr54_sgpr55, $sgpr66_sgpr67, $sgpr68_sgpr69
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr58 = V_ADD_CO_U32_e32 4096, $vgpr40, implicit-def $vcc, implicit $exec
; GFX90A-NEXT: renamable $vgpr1, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, $vgpr41, $vcc, 0, implicit $exec
@@ -519,27 +519,27 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = COPY renamable $sgpr36_sgpr37
; GFX90A-NEXT: renamable $vgpr59, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr42_sgpr43 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.46, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.42.Flow24:
; GFX90A-NEXT: successors: %bb.40(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr42_sgpr43, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr44_sgpr45 = S_XOR_B64 $exec, -1, implicit-def dead $scc
@@ -558,11 +558,11 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.43.bb55:
; GFX90A-NEXT: successors: %bb.48(0x40000000), %bb.44(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr46_sgpr47, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59, $sgpr48_sgpr49
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr46_sgpr47, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59, $sgpr48_sgpr49
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: S_BITCMP1_B32 renamable $sgpr20, 16, implicit-def $scc
- ; GFX90A-NEXT: renamable $sgpr64_sgpr65 = S_CSELECT_B64 -1, 0, implicit killed $scc
- ; GFX90A-NEXT: renamable $sgpr18_sgpr19 = S_XOR_B64 renamable $sgpr64_sgpr65, -1, implicit-def dead $scc
+ ; GFX90A-NEXT: renamable $sgpr66_sgpr67 = S_CSELECT_B64 -1, 0, implicit killed $scc
+ ; GFX90A-NEXT: renamable $sgpr18_sgpr19 = S_XOR_B64 renamable $sgpr66_sgpr67, -1, implicit-def dead $scc
; GFX90A-NEXT: renamable $vgpr62 = V_ADD_CO_U32_e32 6144, $vgpr40, implicit-def $vcc, implicit $exec
; GFX90A-NEXT: renamable $vgpr63, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, renamable $sgpr18_sgpr19, implicit-def dead $scc
@@ -570,27 +570,27 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.44:
; GFX90A-NEXT: successors: %bb.45(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr57, $vgpr62, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $vgpr40, $vgpr61, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr56, $vgpr47, $vgpr2, $vgpr4, $vgpr5, $vgpr6, $vgpr46, $vgpr45, $vgpr44, $vgpr43, $vgpr42, $vgpr41, $vgpr58, $vgpr60, $vgpr63, $vgpr59
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr62, $vgpr57, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $vgpr40, $vgpr58, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr56, $vgpr47, $vgpr2, $vgpr4, $vgpr5, $vgpr46, $vgpr45, $vgpr44, $vgpr43, $vgpr42, $vgpr41, $vgpr60, $vgpr63, $vgpr59, $vgpr61
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.45.Flow26:
; GFX90A-NEXT: successors: %bb.47(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr62_sgpr63 = S_XOR_B64 $exec, -1, implicit-def dead $scc
; GFX90A-NEXT: renamable $sgpr64_sgpr65 = S_AND_B64 killed renamable $sgpr46_sgpr47, $exec, implicit-def dead $scc
@@ -606,7 +606,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.46.bb48:
; GFX90A-NEXT: successors: %bb.43(0x40000000), %bb.47(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr66_sgpr67, $sgpr58_sgpr59, $sgpr68_sgpr69, $sgpr64_sgpr65, $sgpr46_sgpr47, $sgpr54_sgpr55, $sgpr60_sgpr61
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr66_sgpr67, $sgpr58_sgpr59, $sgpr68_sgpr69, $sgpr64_sgpr65, $sgpr46_sgpr47, $sgpr54_sgpr55, $sgpr60_sgpr61
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr60 = V_ADD_CO_U32_e32 5120, $vgpr40, implicit-def $vcc, implicit $exec
; GFX90A-NEXT: renamable $sgpr18_sgpr19 = COPY $vcc
@@ -618,26 +618,26 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $sgpr70_sgpr71 = S_MOV_B64 0
; GFX90A-NEXT: renamable $vgpr61, dead renamable $vcc = V_ADDC_U32_e64 0, $vgpr41, killed $sgpr18_sgpr19, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr44_sgpr45 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.43, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.47.Flow25:
; GFX90A-NEXT: successors: %bb.42(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr58_sgpr59, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $sgpr70_sgpr71, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr58_sgpr59, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr68_sgpr69, $sgpr70_sgpr71, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr44_sgpr45, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_XOR_B64 $exec, -1, implicit-def dead $scc
@@ -655,138 +655,138 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.48.bb63:
; GFX90A-NEXT: successors: %bb.50(0x40000000), %bb.49(0x40000000)
- ; GFX90A-NEXT: liveins: $vcc, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59, $sgpr48_sgpr49
+ ; GFX90A-NEXT: liveins: $vcc, $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr56_sgpr57:0x000000000000000F, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59, $sgpr48_sgpr49
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_MOV_B64 0
; GFX90A-NEXT: S_CBRANCH_VCCNZ %bb.50, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.49:
; GFX90A-NEXT: successors: %bb.44(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 -1
; GFX90A-NEXT: S_BRANCH %bb.44
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.50.bb68:
; GFX90A-NEXT: successors: %bb.54(0x40000000), %bb.51(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr56_sgpr57:0x000000000000000F, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr48_sgpr49, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 3, $vgpr6, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr0 = nuw nsw V_LSHLREV_B32_e32 3, $vgpr30, implicit $exec
; GFX90A-NEXT: renamable $vgpr1 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr18_sgpr19, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCNZ %bb.54, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.51:
; GFX90A-NEXT: successors: %bb.45(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61, $sgpr58_sgpr59
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: S_BRANCH %bb.45
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.52.bb80:
; GFX90A-NEXT: successors: %bb.59(0x40000000), %bb.53(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: dead renamable $sgpr17 = S_BFE_U32 renamable $sgpr20, 65560, implicit-def $scc
- ; GFX90A-NEXT: renamable $vgpr10 = V_ADD_CO_U32_e32 4096, $vgpr0, implicit-def $vcc, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr11, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr8 = V_ADD_CO_U32_e32 4096, $vgpr0, implicit-def $vcc, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr9, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: S_CBRANCH_SCC0 %bb.59, implicit killed $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.53:
; GFX90A-NEXT: successors: %bb.61(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr54_sgpr55 = S_MOV_B64 -1
- ; GFX90A-NEXT: renamable $sgpr66_sgpr67 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $sgpr64_sgpr65 = COPY renamable $sgpr36_sgpr37
+ ; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: S_BRANCH %bb.61
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.54.bb73:
; GFX90A-NEXT: successors: %bb.52(0x40000000), %bb.55(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57:0x000000000000000F, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr56_sgpr57:0x000000000000000F, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr54_sgpr55, $sgpr60_sgpr61
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr3 = FLAT_LOAD_UBYTE renamable $vgpr0_vgpr1, 2048, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i76)
- ; GFX90A-NEXT: renamable $vgpr8 = V_ADD_CO_U32_e32 2048, $vgpr0, implicit-def $vcc, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr6 = V_ADD_CO_U32_e32 2048, $vgpr0, implicit-def $vcc, implicit $exec
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr58_sgpr59 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $vgpr9, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr7, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr3, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr62_sgpr63 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.52, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.55.Flow29:
; GFX90A-NEXT: successors: %bb.45(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr62_sgpr63, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr62_sgpr63, implicit-def $scc
; GFX90A-NEXT: S_BRANCH %bb.45
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.56.bb90:
; GFX90A-NEXT: successors: %bb.60(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr54_sgpr55, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr30 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $sgpr64_sgpr65, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr12 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $sgpr66_sgpr67, implicit $exec
; GFX90A-NEXT: renamable $vgpr3 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr7 = COPY renamable $sgpr21, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr24_vgpr25 = DS_READ_B64_gfx9 killed renamable $vgpr7, 0, 0, implicit $exec :: (load (s64) from %ir.4, addrspace 3)
- ; GFX90A-NEXT: renamable $vgpr22_vgpr23 = DS_READ_B64_gfx9 killed renamable $vgpr3, 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr13 = COPY renamable $sgpr21, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr22_vgpr23 = DS_READ_B64_gfx9 killed renamable $vgpr13, 0, 0, implicit $exec :: (load (s64) from %ir.4, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr20_vgpr21 = DS_READ_B64_gfx9 killed renamable $vgpr3, 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
; GFX90A-NEXT: renamable $vgpr3 = COPY renamable $sgpr22, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr20_vgpr21 = DS_READ_B64_gfx9 killed renamable $vgpr3, 0, 0, implicit $exec :: (load (s64) from %ir.5, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr18_vgpr19 = DS_READ_B64_gfx9 killed renamable $vgpr3, 0, 0, implicit $exec :: (load (s64) from %ir.5, addrspace 3)
; GFX90A-NEXT: renamable $sgpr18_sgpr19 = S_LSHR_B64 killed renamable $sgpr56_sgpr57, 1, implicit-def dead $scc
- ; GFX90A-NEXT: renamable $vgpr18_vgpr19 = V_LSHRREV_B64_e64 1, $vgpr24_vgpr25, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr7 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr12_sgpr13, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr14_vgpr15 = V_LSHRREV_B64_e64 1, $vgpr22_vgpr23, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr16_vgpr17 = V_LSHRREV_B64_e64 1, $vgpr22_vgpr23, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr17 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr12_sgpr13, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr32_vgpr33 = V_LSHRREV_B64_e64 1, $vgpr20_vgpr21, implicit $exec
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_XOR_B64 $exec, -1, implicit-def dead $scc
- ; GFX90A-NEXT: renamable $sgpr66_sgpr67 = S_OR_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
- ; GFX90A-NEXT: renamable $vgpr16 = COPY renamable $vgpr22, implicit $exec
+ ; GFX90A-NEXT: renamable $sgpr64_sgpr65 = S_OR_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
+ ; GFX90A-NEXT: renamable $vgpr14 = COPY renamable $vgpr20, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.60
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.57:
; GFX90A-NEXT: successors: %bb.7(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr36_sgpr37, $sgpr40_sgpr41, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000F, $vgpr24_vgpr25:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr24 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr20 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr21 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr30 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr22 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr14 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr18 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr19 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr12 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr20 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr32 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr16 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX90A-NEXT: renamable $sgpr46_sgpr47 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr44_sgpr45 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr42_sgpr43 = S_MOV_B64 0
@@ -797,9 +797,9 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $sgpr50_sgpr51 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr48_sgpr49 = S_MOV_B64 0
; GFX90A-NEXT: renamable $sgpr38_sgpr39 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr10_vgpr11 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr6_vgpr7 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr0_vgpr1 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr62_vgpr63 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr60_vgpr61 = IMPLICIT_DEF
@@ -809,7 +809,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: renamable $vgpr42_vgpr43 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr40_vgpr41 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr46_vgpr47 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr7 = COPY renamable $vgpr5, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr17 = COPY renamable $vgpr5, implicit $exec
; GFX90A-NEXT: renamable $sgpr34_sgpr35 = S_MOV_B64 0
; GFX90A-NEXT: S_BRANCH %bb.7
; GFX90A-NEXT: {{ $}}
@@ -818,62 +818,62 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr56_sgpr57:0x000000000000000F, $sgpr20_sgpr21_sgpr22_sgpr23:0x00000000000000FF, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000FF, $vgpr4_vgpr5:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr0 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr28_vgpr29 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr26_vgpr27 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
; GFX90A-NEXT: renamable $vgpr0 = COPY renamable $sgpr23, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr26_vgpr27 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.419, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr24_vgpr25 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.419, addrspace 3)
; GFX90A-NEXT: renamable $vgpr0 = COPY renamable $sgpr21, implicit $exec
; GFX90A-NEXT: renamable $vgpr2_vgpr3 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.4, addrspace 3)
; GFX90A-NEXT: renamable $vgpr0 = COPY killed renamable $sgpr17, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr16_vgpr17 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.420, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr14_vgpr15 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.420, addrspace 3)
; GFX90A-NEXT: renamable $vgpr0 = COPY renamable $sgpr22, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr32_vgpr33 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.5, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr28_vgpr29 = DS_READ_B64_gfx9 killed renamable $vgpr0, 0, 0, implicit $exec :: (load (s64) from %ir.5, addrspace 3)
; GFX90A-NEXT: renamable $sgpr36_sgpr37 = S_MOV_B64 -1
; GFX90A-NEXT: S_BRANCH %bb.3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.59.bb85:
; GFX90A-NEXT: successors: %bb.56(0x40000000), %bb.60(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr12 = V_OR_B32_e32 1, $vgpr10, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr13 = COPY renamable $vgpr11, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr3 = FLAT_LOAD_UBYTE renamable $vgpr12_vgpr13, 0, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i86)
+ ; GFX90A-NEXT: renamable $vgpr10 = V_OR_B32_e32 1, $vgpr8, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr11 = COPY renamable $vgpr9, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr3 = FLAT_LOAD_UBYTE renamable $vgpr10_vgpr11, 0, 0, implicit $exec, implicit $flat_scr :: (load (s8) from %ir.i86)
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U16_e64 0, killed $vgpr3, implicit $exec
- ; GFX90A-NEXT: renamable $sgpr66_sgpr67 = COPY renamable $sgpr36_sgpr37
- ; GFX90A-NEXT: renamable $vgpr7 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $sgpr64_sgpr65 = COPY renamable $sgpr36_sgpr37
+ ; GFX90A-NEXT: renamable $vgpr17 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr32 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr20 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
; GFX90A-NEXT: renamable $vgpr22 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr24 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr30 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr21 = IMPLICIT_DEF implicit-def $vgpr20
+ ; GFX90A-NEXT: renamable $vgpr12 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr19 = IMPLICIT_DEF implicit-def $vgpr18
; GFX90A-NEXT: renamable $sgpr18 = IMPLICIT_DEF
- ; GFX90A-NEXT: renamable $vgpr16 = IMPLICIT_DEF
+ ; GFX90A-NEXT: renamable $vgpr14 = IMPLICIT_DEF
; GFX90A-NEXT: $sgpr54_sgpr55 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.56, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.60.Flow31:
; GFX90A-NEXT: successors: %bb.61(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr62_sgpr63, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr54_sgpr55, implicit-def $scc
; GFX90A-NEXT: renamable $sgpr54_sgpr55 = S_MOV_B64 0
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.61.Flow30:
; GFX90A-NEXT: successors: %bb.55(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr62_sgpr63, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19:0x0000000000000003, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr62_sgpr63, $sgpr64_sgpr65, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr58_sgpr59 = S_XOR_B64 $exec, -1, implicit-def dead $scc
; GFX90A-NEXT: renamable $sgpr60_sgpr61 = S_AND_B64 killed renamable $sgpr54_sgpr55, $exec, implicit-def dead $scc
; GFX90A-NEXT: renamable $sgpr54_sgpr55 = S_AND_B64 killed renamable $sgpr52_sgpr53, $exec, implicit-def dead $scc
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_ANDN2_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
- ; GFX90A-NEXT: renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr66_sgpr67, $exec, implicit-def dead $scc
+ ; GFX90A-NEXT: renamable $sgpr56_sgpr57 = S_AND_B64 killed renamable $sgpr64_sgpr65, $exec, implicit-def dead $scc
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_OR_B64 killed renamable $sgpr52_sgpr53, killed renamable $sgpr56_sgpr57, implicit-def dead $scc
; GFX90A-NEXT: S_BRANCH %bb.55
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.62.bb140:
; GFX90A-NEXT: successors: %bb.68(0x40000000), %bb.63(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000F, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000F, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr24_sgpr25 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr30_sgpr31, implicit-def dead $scc
@@ -881,122 +881,122 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.63.Flow13:
; GFX90A-NEXT: successors: %bb.64(0x40000000), %bb.66(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr24_sgpr25, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $vcc = S_ANDN2_B64 $exec, killed renamable $sgpr24_sgpr25, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCNZ %bb.66, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.64.bb159:
; GFX90A-NEXT: successors: %bb.67(0x40000000), %bb.65(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vcc = V_CMP_NE_U32_e64 0, killed $vgpr6, implicit $exec
+ ; GFX90A-NEXT: renamable $vcc = V_CMP_NE_U32_e64 0, killed $vgpr30, implicit $exec
; GFX90A-NEXT: $sgpr12_sgpr13 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: renamable $sgpr12_sgpr13 = S_XOR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_EXECNZ %bb.67, implicit $exec
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.65.Flow10:
; GFX90A-NEXT: successors: %bb.66(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $sgpr12_sgpr13 = S_ANDN2_SAVEEXEC_B64 $sgpr12_sgpr13, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def $scc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.66.Flow14:
; GFX90A-NEXT: successors: %bb.8(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr68_sgpr69 = COPY $exec
; GFX90A-NEXT: S_BRANCH %bb.8
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.67.bb161:
; GFX90A-NEXT: successors: %bb.65(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr27, killed $vgpr29, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr2, killed $vgpr33, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr3 = V_OR_B32_e32 killed $vgpr17, killed $vgpr3, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr25, killed $vgpr27, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr2, killed $vgpr29, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr3 = V_OR_B32_e32 killed $vgpr15, killed $vgpr3, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr3, killed $vgpr2, implicit $exec
; GFX90A-NEXT: renamable $vgpr3 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U32_sdwa 0, killed $vgpr30, 0, $vgpr3, 0, 0, 6, implicit $exec
+ ; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U32_sdwa 0, killed $vgpr12, 0, $vgpr3, 0, 0, 6, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = V_CNDMASK_B32_e64 0, 0, 0, killed $vgpr2, killed $vcc, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr4 = V_OR_B32_e32 killed $vgpr18, killed $vgpr21, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr4 = V_OR_B32_e32 killed $vgpr16, killed $vgpr19, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr4, killed $vgpr2, implicit $exec
- ; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U32_sdwa 0, killed $vgpr7, 0, $vgpr3, 0, 0, 6, implicit $exec
+ ; GFX90A-NEXT: renamable $vcc = V_CMP_EQ_U32_sdwa 0, killed $vgpr17, 0, $vgpr3, 0, 0, 6, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = V_CNDMASK_B32_e64 0, 0, 0, killed $vgpr2, killed $vcc, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr2, killed $vgpr14, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 killed $vgpr2, killed $vgpr32, implicit $exec
; GFX90A-NEXT: DS_WRITE2_B32_gfx9 killed renamable $vgpr3, killed renamable $vgpr2, renamable $vgpr3, 0, 1, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, align 4, addrspace 3)
; GFX90A-NEXT: S_BRANCH %bb.65
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.68.bb174:
; GFX90A-NEXT: successors: %bb.72(0x40000000), %bb.69(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000F, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000F, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
- ; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $agpr0 = COPY killed renamable $vgpr14, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr34 = V_OR_B32_e32 1, $vgpr32, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr54 = V_OR_B32_e32 $vgpr34, $vgpr28, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr48 = V_OR_B32_e32 $vgpr54, $vgpr26, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr36 = V_CNDMASK_B32_e64 0, $vgpr48, 0, 0, $sgpr12_sgpr13, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr52 = V_OR_B32_e32 $vgpr36, $vgpr2, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr50 = V_OR_B32_e32 $vgpr52, $vgpr16, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr38 = V_OR_B32_e32 $vgpr50, $vgpr20, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr14 = V_CNDMASK_B32_e64 0, 0, 0, $vgpr38, killed $sgpr12_sgpr13, implicit $exec
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000F, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000F, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000F, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x000000000000000F, $vgpr26_vgpr27:0x000000000000000F, $vgpr28_vgpr29:0x000000000000000F, $vgpr32_vgpr33:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: renamable $agpr0 = COPY killed renamable $vgpr32, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr32 = V_OR_B32_e32 1, $vgpr28, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr52 = V_OR_B32_e32 $vgpr32, $vgpr26, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr38 = V_OR_B32_e32 $vgpr52, $vgpr24, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr34 = V_CNDMASK_B32_e64 0, $vgpr38, 0, 0, $sgpr12_sgpr13, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr50 = V_OR_B32_e32 $vgpr34, $vgpr2, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr48 = V_OR_B32_e32 $vgpr50, $vgpr14, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr36 = V_OR_B32_e32 $vgpr48, $vgpr18, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr54 = V_CNDMASK_B32_e64 0, 0, 0, $vgpr36, killed $sgpr12_sgpr13, implicit $exec
; GFX90A-NEXT: renamable $sgpr12_sgpr13 = S_MOV_B64 -1
; GFX90A-NEXT: renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr28_sgpr29, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCNZ %bb.72, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.69.Flow:
; GFX90A-NEXT: successors: %bb.70(0x40000000), %bb.71(0x40000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x0000000000000003, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: $vcc = S_ANDN2_B64 $exec, killed renamable $sgpr12_sgpr13, implicit-def dead $scc
; GFX90A-NEXT: S_CBRANCH_VCCNZ %bb.71, implicit $vcc
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.70.bb186:
; GFX90A-NEXT: successors: %bb.71(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x0000000000000003, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr4_vgpr5 = nsw V_LSHLREV_B64_e64 3, killed $vgpr4_vgpr5, implicit $exec
; GFX90A-NEXT: renamable $vgpr2 = COPY renamable $sgpr27, implicit $exec
; GFX90A-NEXT: renamable $vgpr4, renamable $vcc = V_ADD_CO_U32_e64 killed $sgpr26, $vgpr4, 0, implicit $exec
; GFX90A-NEXT: renamable $vgpr2, dead renamable $vcc = V_ADDC_U32_e64 killed $vgpr2, killed $vgpr5, killed $vcc, 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr35 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr55 = COPY renamable $vgpr35, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr49 = COPY renamable $vgpr35, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr53 = COPY renamable $vgpr35, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr51 = COPY renamable $vgpr35, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr37 = COPY renamable $vgpr35, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr15 = COPY renamable $vgpr35, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr39 = COPY renamable $vgpr35, implicit $exec
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr35, renamable $vgpr34_vgpr35, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr33 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr53 = COPY renamable $vgpr33, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr39 = COPY renamable $vgpr33, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr51 = COPY renamable $vgpr33, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr49 = COPY renamable $vgpr33, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr35 = COPY renamable $vgpr33, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr55 = COPY renamable $vgpr33, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr37 = COPY renamable $vgpr33, implicit $exec
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr33, renamable $vgpr32_vgpr33, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
; GFX90A-NEXT: renamable $vgpr5 = COPY renamable $sgpr21, implicit $exec
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr5, killed renamable $vgpr54_vgpr55, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
- ; GFX90A-NEXT: renamable $vgpr16 = COPY killed renamable $sgpr22, implicit $exec
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr16, killed renamable $vgpr48_vgpr49, 0, 0, implicit $exec :: (store (s64) into %ir.5, addrspace 3)
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr35, killed renamable $vgpr52_vgpr53, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr5, killed renamable $vgpr50_vgpr51, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr35, killed renamable $vgpr36_vgpr37, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr5, killed renamable $vgpr14_vgpr15, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr35, killed renamable $vgpr38_vgpr39, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr5, killed renamable $vgpr52_vgpr53, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr13 = COPY killed renamable $sgpr22, implicit $exec
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr13, killed renamable $vgpr38_vgpr39, 0, 0, implicit $exec :: (store (s64) into %ir.5, addrspace 3)
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr33, killed renamable $vgpr50_vgpr51, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr5, killed renamable $vgpr48_vgpr49, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 renamable $vgpr33, killed renamable $vgpr34_vgpr35, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr5, killed renamable $vgpr54_vgpr55, 0, 0, implicit $exec :: (store (s64) into %ir.4, addrspace 3)
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr33, killed renamable $vgpr36_vgpr37, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null` + 4, basealign 8, addrspace 5)
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) null`, align 8, addrspace 5)
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.71.Flow9:
; GFX90A-NEXT: successors: %bb.63(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr24_sgpr25 = S_MOV_B64 0
- ; GFX90A-NEXT: renamable $vgpr14 = COPY killed renamable $agpr0, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr32 = COPY killed renamable $agpr0, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.63
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.72.bb196:
; GFX90A-NEXT: successors: %bb.69(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr7, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x0000000000000003, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr12_vgpr13:0x000000000000000F, $vgpr14_vgpr15:0x0000000000000003, $vgpr16_vgpr17:0x000000000000000C, $vgpr18_vgpr19:0x0000000000000003, $vgpr20_vgpr21:0x000000000000000C, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x0000000000000003, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x000000000000000C, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr12, $vgpr17, $vgpr30, $vgpr31, $agpr0_agpr1:0x0000000000000003, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr18_sgpr19, $sgpr34_sgpr35, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55, $sgpr64_sgpr65, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003C, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x000000000000000C, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr8_vgpr9:0x000000000000000F, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000C, $vgpr16_vgpr17:0x0000000000000003, $vgpr18_vgpr19:0x000000000000000C, $vgpr20_vgpr21:0x0000000000000003, $vgpr22_vgpr23:0x0000000000000003, $vgpr24_vgpr25:0x000000000000000C, $vgpr26_vgpr27:0x000000000000000C, $vgpr28_vgpr29:0x000000000000000C, $vgpr32_vgpr33:0x0000000000000003, $vgpr34_vgpr35:0x0000000000000003, $vgpr36_vgpr37:0x0000000000000003, $vgpr38_vgpr39:0x0000000000000003, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr48_vgpr49:0x0000000000000003, $vgpr50_vgpr51:0x0000000000000003, $vgpr52_vgpr53:0x0000000000000003, $vgpr54_vgpr55:0x0000000000000003, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 $vgpr14, killed $vgpr24, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr22 = V_OR_B32_e32 killed $vgpr2, killed $vgpr22, implicit $exec
- ; GFX90A-NEXT: renamable $vgpr23 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
- ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr23, renamable $vgpr22_vgpr23, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
+ ; GFX90A-NEXT: renamable $vgpr2 = V_OR_B32_e32 $vgpr54, killed $vgpr22, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr20 = V_OR_B32_e32 killed $vgpr2, killed $vgpr20, implicit $exec
+ ; GFX90A-NEXT: renamable $vgpr21 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
+ ; GFX90A-NEXT: DS_WRITE_B64_gfx9 killed renamable $vgpr21, renamable $vgpr20_vgpr21, 0, 0, implicit $exec :: (store (s64) into `ptr addrspace(3) null`, addrspace 3)
; GFX90A-NEXT: renamable $sgpr12_sgpr13 = S_MOV_B64 0
; GFX90A-NEXT: S_BRANCH %bb.69
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir b/llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir
index d0c9740c6954e..6261a25cc69e2 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir
+++ b/llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir
@@ -6,7 +6,6 @@ body: |
bb.0:
; CHECK-LABEL: name: snork
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3
; CHECK-NEXT: SI_RETURN
%0:sreg_32 = S_MOV_B32 0
%1:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1, %0, %subreg.sub2, %0, %subreg.sub3
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index 8193ee4104ab7..486028ca8f3b1 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -24,12 +24,12 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_ashrrev_i32_e32 v17, 31, v3
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, 0, v7, vcc
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v21, v5, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v22, v4, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v19, v5, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v20, v4, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
-; GFX9-NEXT: v_or_b32_e32 v3, v21, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v22, v0
+; GFX9-NEXT: v_or_b32_e32 v3, v19, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v20, v0
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
; GFX9-NEXT: v_or_b32_e32 v3, v9, v11
; GFX9-NEXT: v_or_b32_e32 v2, v8, v10
@@ -38,9 +38,9 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_u32_e32 v2, 32, v2
; GFX9-NEXT: v_ffbh_u32_e32 v3, v1
; GFX9-NEXT: v_min_u32_e32 v2, v2, v3
-; GFX9-NEXT: v_ffbh_u32_e32 v3, v22
+; GFX9-NEXT: v_ffbh_u32_e32 v3, v20
; GFX9-NEXT: v_add_u32_e32 v3, 32, v3
-; GFX9-NEXT: v_ffbh_u32_e32 v4, v21
+; GFX9-NEXT: v_ffbh_u32_e32 v4, v19
; GFX9-NEXT: v_min_u32_e32 v3, v3, v4
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, 64, v3
@@ -69,18 +69,16 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v19, v17
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; GFX9-NEXT: v_mov_b32_e32 v20, v18
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
; GFX9-NEXT: v_xor_b32_e32 v6, 0x7f, v2
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v4
; GFX9-NEXT: v_or_b32_e32 v7, v3, v5
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v4
; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GFX9-NEXT: s_xor_b64 s[6:7], s[4:5], -1
@@ -92,14 +90,14 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB0_6
; GFX9-NEXT: ; %bb.1: ; %udiv-bb1
-; GFX9-NEXT: v_add_co_u32_e32 v23, vcc, 1, v2
-; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, 0, v3, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, 0, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, 1, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v22, vcc, 0, v3, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v7, 0x7f, v2
-; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, 0, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, 0, v5, vcc
; GFX9-NEXT: v_sub_u32_e32 v12, 64, v7
-; GFX9-NEXT: v_or_b32_e32 v4, v24, v26
-; GFX9-NEXT: v_or_b32_e32 v3, v23, v25
+; GFX9-NEXT: v_or_b32_e32 v4, v22, v24
+; GFX9-NEXT: v_or_b32_e32 v3, v21, v23
; GFX9-NEXT: v_lshlrev_b64 v[5:6], v7, v[10:11]
; GFX9-NEXT: v_lshrrev_b64 v[12:13], v12, v[8:9]
; GFX9-NEXT: v_sub_u32_e32 v2, 63, v2
@@ -122,67 +120,67 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB0_5
; GFX9-NEXT: ; %bb.2: ; %udiv-preheader
-; GFX9-NEXT: v_sub_u32_e32 v12, 64, v23
-; GFX9-NEXT: v_lshrrev_b64 v[6:7], v23, v[8:9]
+; GFX9-NEXT: v_sub_u32_e32 v12, 64, v21
+; GFX9-NEXT: v_lshrrev_b64 v[6:7], v21, v[8:9]
; GFX9-NEXT: v_lshlrev_b64 v[12:13], v12, v[10:11]
-; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23
+; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v21
; GFX9-NEXT: v_or_b32_e32 v14, v6, v12
-; GFX9-NEXT: v_subrev_u32_e32 v6, 64, v23
+; GFX9-NEXT: v_subrev_u32_e32 v6, 64, v21
; GFX9-NEXT: v_or_b32_e32 v13, v7, v13
; GFX9-NEXT: v_lshrrev_b64 v[6:7], v6, v[10:11]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v23
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v21
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v13, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v12, v7, v9, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v9, v6, v14, vcc
-; GFX9-NEXT: v_lshrrev_b64 v[6:7], v23, v[10:11]
+; GFX9-NEXT: v_lshrrev_b64 v[6:7], v21, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v11, v9, v8, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v14, 0, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v6, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, -1, v22
-; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, -1, v21, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v28, vcc, -1, v0, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, -1, v20
+; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v19, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, -1, v0, vcc
; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mov_b32_e32 v15, 0
-; GFX9-NEXT: v_addc_co_u32_e32 v29, vcc, -1, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, -1, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v9, 0
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: v_mov_b32_e32 v16, 0
; GFX9-NEXT: v_mov_b32_e32 v7, 0
; GFX9-NEXT: .LBB0_3: ; %udiv-do-while
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_lshlrev_b64 v[30:31], 1, v[4:5]
+; GFX9-NEXT: v_lshlrev_b64 v[28:29], 1, v[4:5]
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 31, v5
-; GFX9-NEXT: v_or_b32_e32 v4, v15, v30
+; GFX9-NEXT: v_or_b32_e32 v4, v15, v28
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 31, v12
; GFX9-NEXT: v_lshlrev_b64 v[11:12], 1, v[11:12]
-; GFX9-NEXT: v_or_b32_e32 v5, v16, v31
+; GFX9-NEXT: v_or_b32_e32 v5, v16, v29
; GFX9-NEXT: v_lshlrev_b64 v[13:14], 1, v[13:14]
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 31, v3
; GFX9-NEXT: v_or_b32_e32 v11, v11, v16
; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
; GFX9-NEXT: v_sub_co_u32_e32 v15, vcc, v10, v11
-; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v27, v12, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v28, v13, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v29, v14, vcc
-; GFX9-NEXT: v_ashrrev_i32_e32 v30, 31, v15
-; GFX9-NEXT: v_and_b32_e32 v15, v30, v22
+; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v25, v12, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v26, v13, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v27, v14, vcc
+; GFX9-NEXT: v_ashrrev_i32_e32 v28, 31, v15
+; GFX9-NEXT: v_and_b32_e32 v15, v28, v20
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX9-NEXT: v_sub_co_u32_e32 v11, vcc, v11, v15
-; GFX9-NEXT: v_and_b32_e32 v15, v30, v21
+; GFX9-NEXT: v_and_b32_e32 v15, v28, v19
; GFX9-NEXT: v_subb_co_u32_e32 v12, vcc, v12, v15, vcc
; GFX9-NEXT: v_or3_b32 v2, v2, v6, v8
-; GFX9-NEXT: v_and_b32_e32 v6, v30, v0
-; GFX9-NEXT: v_and_b32_e32 v15, v30, v1
+; GFX9-NEXT: v_and_b32_e32 v6, v28, v0
+; GFX9-NEXT: v_and_b32_e32 v15, v28, v1
; GFX9-NEXT: v_subb_co_u32_e32 v13, vcc, v13, v6, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v14, vcc, v14, v15, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v23, vcc, -1, v23
+; GFX9-NEXT: v_add_co_u32_e32 v21, vcc, -1, v21
+; GFX9-NEXT: v_addc_co_u32_e32 v22, vcc, -1, v22, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v23, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, -1, v24, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v25, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, -1, v26, vcc
-; GFX9-NEXT: v_or_b32_e32 v15, v23, v25
-; GFX9-NEXT: v_or_b32_e32 v16, v24, v26
+; GFX9-NEXT: v_or_b32_e32 v15, v21, v23
+; GFX9-NEXT: v_or_b32_e32 v16, v22, v24
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[15:16]
-; GFX9-NEXT: v_and_b32_e32 v6, 1, v30
+; GFX9-NEXT: v_and_b32_e32 v6, 1, v28
; GFX9-NEXT: v_mov_b32_e32 v16, v7
; GFX9-NEXT: v_or3_b32 v3, v3, 0, v9
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -202,7 +200,7 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: .LBB0_6: ; %Flow3
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT: v_xor_b32_e32 v2, v18, v17
-; GFX9-NEXT: v_xor_b32_e32 v3, v20, v19
+; GFX9-NEXT: v_xor_b32_e32 v3, v18, v17
; GFX9-NEXT: v_xor_b32_e32 v0, v6, v2
; GFX9-NEXT: v_xor_b32_e32 v1, v7, v3
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
index 0eebada5c1c9e..edcad03bdc2ec 100644
--- a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
@@ -12,29 +12,27 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_ashrrev_i32_e32 v24, 31, v3
; SDAG-NEXT: v_ashrrev_i32_e32 v25, 31, v11
; SDAG-NEXT: v_subb_u32_e32 v17, vcc, 0, v1, vcc
-; SDAG-NEXT: v_mov_b32_e32 v26, v24
-; SDAG-NEXT: v_mov_b32_e32 v27, v25
-; SDAG-NEXT: v_subb_u32_e32 v21, vcc, 0, v2, vcc
+; SDAG-NEXT: v_subb_u32_e32 v18, vcc, 0, v2, vcc
; SDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v3
-; SDAG-NEXT: v_cndmask_b32_e64 v19, v1, v17, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v18, v0, v16, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v17, v1, v17, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v16, v0, v16, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v0, vcc, 0, v3, vcc
-; SDAG-NEXT: v_cndmask_b32_e64 v16, v2, v21, s[4:5]
-; SDAG-NEXT: v_ffbh_u32_e32 v1, v18
-; SDAG-NEXT: v_ffbh_u32_e32 v2, v19
-; SDAG-NEXT: v_cndmask_b32_e64 v17, v3, v0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v18, v2, v18, s[4:5]
+; SDAG-NEXT: v_ffbh_u32_e32 v1, v16
+; SDAG-NEXT: v_ffbh_u32_e32 v2, v17
+; SDAG-NEXT: v_cndmask_b32_e64 v19, v3, v0, s[4:5]
; SDAG-NEXT: v_sub_i32_e32 v3, vcc, 0, v8
-; SDAG-NEXT: v_or_b32_e32 v0, v18, v16
+; SDAG-NEXT: v_or_b32_e32 v0, v16, v18
; SDAG-NEXT: v_add_i32_e64 v21, s[4:5], 32, v1
-; SDAG-NEXT: v_ffbh_u32_e32 v22, v16
+; SDAG-NEXT: v_ffbh_u32_e32 v22, v18
; SDAG-NEXT: v_subb_u32_e32 v23, vcc, 0, v9, vcc
-; SDAG-NEXT: v_or_b32_e32 v1, v19, v17
+; SDAG-NEXT: v_or_b32_e32 v1, v17, v19
; SDAG-NEXT: v_min_u32_e32 v2, v21, v2
; SDAG-NEXT: v_add_i32_e64 v21, s[4:5], 32, v22
-; SDAG-NEXT: v_ffbh_u32_e32 v22, v17
+; SDAG-NEXT: v_ffbh_u32_e32 v22, v19
; SDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v11
-; SDAG-NEXT: v_cndmask_b32_e64 v28, v9, v23, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v29, v8, v3, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v26, v9, v23, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v27, v8, v3, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v3, vcc, 0, v10, vcc
; SDAG-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[0:1]
; SDAG-NEXT: v_min_u32_e32 v0, v21, v22
@@ -42,16 +40,16 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_addc_u32_e64 v8, s[8:9], 0, 0, s[8:9]
; SDAG-NEXT: v_subb_u32_e32 v9, vcc, 0, v11, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v3, s[4:5]
-; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[16:17]
+; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[18:19]
; SDAG-NEXT: v_cndmask_b32_e64 v10, v8, 0, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v8, v1, v0, vcc
-; SDAG-NEXT: v_ffbh_u32_e32 v1, v29
-; SDAG-NEXT: v_ffbh_u32_e32 v21, v28
+; SDAG-NEXT: v_ffbh_u32_e32 v1, v27
+; SDAG-NEXT: v_ffbh_u32_e32 v21, v26
; SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v9, s[4:5]
-; SDAG-NEXT: v_or_b32_e32 v0, v29, v2
+; SDAG-NEXT: v_or_b32_e32 v0, v27, v2
; SDAG-NEXT: v_add_i32_e32 v9, vcc, 32, v1
; SDAG-NEXT: v_ffbh_u32_e32 v11, v2
-; SDAG-NEXT: v_or_b32_e32 v1, v28, v3
+; SDAG-NEXT: v_or_b32_e32 v1, v26, v3
; SDAG-NEXT: v_min_u32_e32 v9, v9, v21
; SDAG-NEXT: v_add_i32_e32 v11, vcc, 32, v11
; SDAG-NEXT: v_ffbh_u32_e32 v21, v3
@@ -80,115 +78,115 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_and_b32_e32 v0, 1, v0
; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
; SDAG-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v1, v17, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v1, v19, 0, s[4:5]
; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1
-; SDAG-NEXT: v_cndmask_b32_e64 v0, v16, 0, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v20, v19, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v0, v18, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v20, v17, 0, s[4:5]
; SDAG-NEXT: s_and_b64 s[8:9], s[6:7], vcc
-; SDAG-NEXT: v_cndmask_b32_e64 v21, v18, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v21, v16, 0, s[4:5]
; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[8:9]
; SDAG-NEXT: s_cbranch_execz .LBB0_6
; SDAG-NEXT: ; %bb.1: ; %udiv-bb15
-; SDAG-NEXT: v_add_i32_e32 v30, vcc, 1, v8
+; SDAG-NEXT: v_add_i32_e32 v28, vcc, 1, v8
; SDAG-NEXT: v_sub_i32_e64 v0, s[4:5], 63, v8
-; SDAG-NEXT: v_addc_u32_e32 v31, vcc, 0, v9, vcc
-; SDAG-NEXT: v_lshl_b64 v[0:1], v[18:19], v0
-; SDAG-NEXT: v_addc_u32_e32 v32, vcc, 0, v10, vcc
-; SDAG-NEXT: v_addc_u32_e32 v33, vcc, 0, v11, vcc
-; SDAG-NEXT: v_or_b32_e32 v9, v30, v32
-; SDAG-NEXT: v_sub_i32_e32 v34, vcc, 0x7f, v8
-; SDAG-NEXT: v_or_b32_e32 v10, v31, v33
-; SDAG-NEXT: v_lshl_b64 v[20:21], v[16:17], v34
-; SDAG-NEXT: v_sub_i32_e32 v8, vcc, 64, v34
-; SDAG-NEXT: v_lshl_b64 v[22:23], v[18:19], v34
+; SDAG-NEXT: v_addc_u32_e32 v29, vcc, 0, v9, vcc
+; SDAG-NEXT: v_lshl_b64 v[0:1], v[16:17], v0
+; SDAG-NEXT: v_addc_u32_e32 v30, vcc, 0, v10, vcc
+; SDAG-NEXT: v_addc_u32_e32 v31, vcc, 0, v11, vcc
+; SDAG-NEXT: v_or_b32_e32 v9, v28, v30
+; SDAG-NEXT: v_sub_i32_e32 v32, vcc, 0x7f, v8
+; SDAG-NEXT: v_or_b32_e32 v10, v29, v31
+; SDAG-NEXT: v_lshl_b64 v[20:21], v[18:19], v32
+; SDAG-NEXT: v_sub_i32_e32 v8, vcc, 64, v32
+; SDAG-NEXT: v_lshl_b64 v[22:23], v[16:17], v32
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10]
-; SDAG-NEXT: v_lshr_b64 v[8:9], v[18:19], v8
+; SDAG-NEXT: v_lshr_b64 v[8:9], v[16:17], v8
; SDAG-NEXT: v_or_b32_e32 v9, v21, v9
; SDAG-NEXT: v_or_b32_e32 v8, v20, v8
-; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v34
+; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v32
; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v8, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, v23, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, v22, s[4:5]
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v34
-; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5]
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v32
+; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v19, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v18, s[4:5]
; SDAG-NEXT: v_mov_b32_e32 v8, 0
; SDAG-NEXT: v_mov_b32_e32 v9, 0
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB0_5
; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4
-; SDAG-NEXT: v_lshr_b64 v[8:9], v[18:19], v30
-; SDAG-NEXT: v_sub_i32_e32 v20, vcc, 64, v30
-; SDAG-NEXT: v_lshl_b64 v[20:21], v[16:17], v20
-; SDAG-NEXT: v_or_b32_e32 v21, v9, v21
-; SDAG-NEXT: v_or_b32_e32 v20, v8, v20
-; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v30
-; SDAG-NEXT: v_subrev_i32_e64 v8, s[4:5], 64, v30
-; SDAG-NEXT: v_lshr_b64 v[8:9], v[16:17], v8
-; SDAG-NEXT: v_cndmask_b32_e32 v9, v9, v21, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v30
-; SDAG-NEXT: v_cndmask_b32_e64 v19, v9, v19, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v8, v8, v20, vcc
-; SDAG-NEXT: v_cndmask_b32_e64 v18, v8, v18, s[4:5]
-; SDAG-NEXT: v_lshr_b64 v[8:9], v[16:17], v30
-; SDAG-NEXT: v_cndmask_b32_e32 v23, 0, v9, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v22, 0, v8, vcc
-; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v29
-; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v28, vcc
-; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v2, vcc
-; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v3, vcc
-; SDAG-NEXT: v_mov_b32_e32 v16, 0
-; SDAG-NEXT: v_mov_b32_e32 v17, 0
-; SDAG-NEXT: s_mov_b64 s[4:5], 0
-; SDAG-NEXT: v_mov_b32_e32 v9, 0
+; SDAG-NEXT: v_lshr_b64 v[22:23], v[16:17], v28
+; SDAG-NEXT: v_sub_i32_e32 v8, vcc, 64, v28
+; SDAG-NEXT: v_subrev_i32_e32 v33, vcc, 64, v28
+; SDAG-NEXT: v_lshr_b64 v[35:36], v[18:19], v28
+; SDAG-NEXT: v_add_i32_e32 v32, vcc, -1, v27
; SDAG-NEXT: v_mov_b32_e32 v20, 0
; SDAG-NEXT: v_mov_b32_e32 v21, 0
+; SDAG-NEXT: s_mov_b64 s[10:11], 0
+; SDAG-NEXT: v_mov_b32_e32 v9, 0
+; SDAG-NEXT: v_lshl_b64 v[37:38], v[18:19], v8
+; SDAG-NEXT: v_lshr_b64 v[18:19], v[18:19], v33
+; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v26, vcc
+; SDAG-NEXT: v_or_b32_e32 v8, v23, v38
+; SDAG-NEXT: v_or_b32_e32 v22, v22, v37
+; SDAG-NEXT: v_addc_u32_e32 v34, vcc, -1, v2, vcc
+; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v28
+; SDAG-NEXT: v_cndmask_b32_e64 v8, v19, v8, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v18, v18, v22, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v23, 0, v36, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v22, 0, v35, s[4:5]
+; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v3, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v28
+; SDAG-NEXT: v_cndmask_b32_e32 v19, v8, v17, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v18, v18, v16, vcc
+; SDAG-NEXT: v_mov_b32_e32 v16, 0
+; SDAG-NEXT: v_mov_b32_e32 v17, 0
; SDAG-NEXT: .LBB0_3: ; %udiv-do-while3
; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
; SDAG-NEXT: v_lshrrev_b32_e32 v8, 31, v11
; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; SDAG-NEXT: v_lshl_b64 v[22:23], v[22:23], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v38, 31, v19
+; SDAG-NEXT: v_lshrrev_b32_e32 v36, 31, v19
; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v39, 31, v1
+; SDAG-NEXT: v_lshrrev_b32_e32 v37, 31, v1
; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
-; SDAG-NEXT: v_or_b32_e32 v11, v21, v11
-; SDAG-NEXT: v_or_b32_e32 v10, v20, v10
-; SDAG-NEXT: v_or_b32_e32 v20, v22, v38
-; SDAG-NEXT: v_or_b32_e32 v18, v18, v39
+; SDAG-NEXT: v_or_b32_e32 v11, v17, v11
+; SDAG-NEXT: v_or_b32_e32 v10, v16, v10
+; SDAG-NEXT: v_or_b32_e32 v16, v22, v36
+; SDAG-NEXT: v_or_b32_e32 v17, v18, v37
; SDAG-NEXT: v_or_b32_e32 v0, v0, v8
-; SDAG-NEXT: v_sub_i32_e32 v8, vcc, v34, v18
-; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v35, v19, vcc
-; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v36, v20, vcc
-; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v37, v23, vcc
+; SDAG-NEXT: v_sub_i32_e32 v8, vcc, v32, v17
+; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v33, v19, vcc
+; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v34, v16, vcc
+; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v35, v23, vcc
; SDAG-NEXT: v_ashrrev_i32_e32 v8, 31, v8
-; SDAG-NEXT: v_and_b32_e32 v21, v8, v29
-; SDAG-NEXT: v_and_b32_e32 v22, v8, v28
-; SDAG-NEXT: v_and_b32_e32 v38, v8, v2
-; SDAG-NEXT: v_and_b32_e32 v39, v8, v3
+; SDAG-NEXT: v_and_b32_e32 v18, v8, v27
+; SDAG-NEXT: v_and_b32_e32 v22, v8, v26
+; SDAG-NEXT: v_and_b32_e32 v36, v8, v2
+; SDAG-NEXT: v_and_b32_e32 v37, v8, v3
; SDAG-NEXT: v_and_b32_e32 v8, 1, v8
-; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v18, v21
+; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v17, v18
; SDAG-NEXT: v_subb_u32_e32 v19, vcc, v19, v22, vcc
-; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v20, v38, vcc
-; SDAG-NEXT: v_subb_u32_e32 v23, vcc, v23, v39, vcc
-; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v30
+; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v16, v36, vcc
+; SDAG-NEXT: v_subb_u32_e32 v23, vcc, v23, v37, vcc
+; SDAG-NEXT: v_add_i32_e32 v28, vcc, -1, v28
+; SDAG-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc
+; SDAG-NEXT: v_addc_u32_e32 v30, vcc, -1, v30, vcc
; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc
-; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc
-; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc
-; SDAG-NEXT: v_or_b32_e32 v20, v30, v32
-; SDAG-NEXT: v_or_b32_e32 v21, v31, v33
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[20:21]
-; SDAG-NEXT: v_or_b32_e32 v1, v17, v1
-; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; SDAG-NEXT: v_or_b32_e32 v0, v16, v0
-; SDAG-NEXT: v_mov_b32_e32 v21, v9
-; SDAG-NEXT: v_mov_b32_e32 v20, v8
-; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5]
+; SDAG-NEXT: v_or_b32_e32 v16, v28, v30
+; SDAG-NEXT: v_or_b32_e32 v17, v29, v31
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17]
+; SDAG-NEXT: v_or_b32_e32 v1, v21, v1
+; SDAG-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
+; SDAG-NEXT: v_or_b32_e32 v0, v20, v0
+; SDAG-NEXT: v_mov_b32_e32 v17, v9
+; SDAG-NEXT: v_mov_b32_e32 v16, v8
+; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
; SDAG-NEXT: s_cbranch_execnz .LBB0_3
; SDAG-NEXT: ; %bb.4: ; %Flow13
-; SDAG-NEXT: s_or_b64 exec, exec, s[4:5]
+; SDAG-NEXT: s_or_b64 exec, exec, s[10:11]
; SDAG-NEXT: .LBB0_5: ; %Flow14
; SDAG-NEXT: s_or_b64 exec, exec, s[8:9]
; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
@@ -204,178 +202,176 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_sub_i32_e32 v2, vcc, 0, v4
; SDAG-NEXT: v_mov_b32_e32 v11, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0x7f
-; SDAG-NEXT: v_mov_b32_e32 v22, v18
-; SDAG-NEXT: v_mov_b32_e32 v23, v19
; SDAG-NEXT: v_subb_u32_e32 v3, vcc, 0, v5, vcc
; SDAG-NEXT: v_subb_u32_e32 v8, vcc, 0, v6, vcc
; SDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v7
; SDAG-NEXT: v_cndmask_b32_e64 v5, v5, v3, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v4, v4, v2, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc
-; SDAG-NEXT: v_cndmask_b32_e64 v8, v6, v8, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[4:5]
; SDAG-NEXT: v_ffbh_u32_e32 v3, v4
-; SDAG-NEXT: v_ffbh_u32_e32 v6, v5
-; SDAG-NEXT: v_cndmask_b32_e64 v9, v7, v2, s[4:5]
-; SDAG-NEXT: v_sub_i32_e32 v7, vcc, 0, v12
-; SDAG-NEXT: v_or_b32_e32 v2, v4, v8
-; SDAG-NEXT: v_ffbh_u32_e32 v10, v8
+; SDAG-NEXT: v_ffbh_u32_e32 v8, v5
+; SDAG-NEXT: v_cndmask_b32_e64 v7, v7, v2, s[4:5]
+; SDAG-NEXT: v_sub_i32_e32 v9, vcc, 0, v12
+; SDAG-NEXT: v_or_b32_e32 v2, v4, v6
+; SDAG-NEXT: v_ffbh_u32_e32 v10, v6
; SDAG-NEXT: v_add_i32_e64 v16, s[4:5], 32, v3
; SDAG-NEXT: v_subb_u32_e32 v17, vcc, 0, v13, vcc
-; SDAG-NEXT: v_or_b32_e32 v3, v5, v9
+; SDAG-NEXT: v_or_b32_e32 v3, v5, v7
; SDAG-NEXT: v_add_i32_e64 v10, s[4:5], 32, v10
-; SDAG-NEXT: v_ffbh_u32_e32 v30, v9
-; SDAG-NEXT: v_min_u32_e32 v6, v16, v6
+; SDAG-NEXT: v_ffbh_u32_e32 v26, v7
+; SDAG-NEXT: v_min_u32_e32 v8, v16, v8
; SDAG-NEXT: v_subb_u32_e32 v16, vcc, 0, v14, vcc
; SDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v15
-; SDAG-NEXT: v_cndmask_b32_e64 v28, v13, v17, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v29, v12, v7, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v22, v13, v17, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v23, v12, v9, s[4:5]
; SDAG-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[2:3]
-; SDAG-NEXT: v_min_u32_e32 v3, v10, v30
-; SDAG-NEXT: v_add_i32_e64 v6, s[8:9], 64, v6
-; SDAG-NEXT: v_addc_u32_e64 v7, s[8:9], 0, 0, s[8:9]
+; SDAG-NEXT: v_min_u32_e32 v3, v10, v26
+; SDAG-NEXT: v_add_i32_e64 v8, s[8:9], 64, v8
+; SDAG-NEXT: v_addc_u32_e64 v9, s[8:9], 0, 0, s[8:9]
; SDAG-NEXT: v_subb_u32_e32 v10, vcc, 0, v15, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v2, v14, v16, s[4:5]
-; SDAG-NEXT: v_ffbh_u32_e32 v12, v29
-; SDAG-NEXT: v_ffbh_u32_e32 v13, v28
-; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
-; SDAG-NEXT: v_cndmask_b32_e64 v14, v7, 0, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v16, v6, v3, vcc
+; SDAG-NEXT: v_ffbh_u32_e32 v12, v23
+; SDAG-NEXT: v_ffbh_u32_e32 v13, v22
+; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
+; SDAG-NEXT: v_cndmask_b32_e64 v14, v9, 0, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v16, v8, v3, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v3, v15, v10, s[4:5]
-; SDAG-NEXT: v_or_b32_e32 v6, v29, v2
+; SDAG-NEXT: v_or_b32_e32 v8, v23, v2
; SDAG-NEXT: v_ffbh_u32_e32 v10, v2
; SDAG-NEXT: v_add_i32_e32 v12, vcc, 32, v12
-; SDAG-NEXT: v_or_b32_e32 v7, v28, v3
+; SDAG-NEXT: v_or_b32_e32 v9, v22, v3
; SDAG-NEXT: v_add_i32_e32 v10, vcc, 32, v10
; SDAG-NEXT: v_ffbh_u32_e32 v15, v3
; SDAG-NEXT: v_min_u32_e32 v12, v12, v13
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
-; SDAG-NEXT: v_min_u32_e32 v6, v10, v15
-; SDAG-NEXT: v_add_i32_e64 v7, s[4:5], 64, v12
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; SDAG-NEXT: v_min_u32_e32 v8, v10, v15
+; SDAG-NEXT: v_add_i32_e64 v9, s[4:5], 64, v12
; SDAG-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
; SDAG-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; SDAG-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
-; SDAG-NEXT: v_sub_i32_e32 v6, vcc, v6, v16
-; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v10, v14, vcc
-; SDAG-NEXT: v_xor_b32_e32 v12, 0x7f, v6
+; SDAG-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
+; SDAG-NEXT: v_sub_i32_e32 v8, vcc, v8, v16
+; SDAG-NEXT: v_subb_u32_e32 v9, vcc, v10, v14, vcc
+; SDAG-NEXT: v_xor_b32_e32 v12, 0x7f, v8
; SDAG-NEXT: v_subb_u32_e32 v10, vcc, 0, v11, vcc
-; SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], s[10:11], v[6:7]
+; SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], s[10:11], v[8:9]
; SDAG-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v11, vcc, 0, v11, vcc
; SDAG-NEXT: v_or_b32_e32 v12, v12, v10
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
; SDAG-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; SDAG-NEXT: v_or_b32_e32 v13, v7, v11
+; SDAG-NEXT: v_or_b32_e32 v13, v9, v11
; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; SDAG-NEXT: v_cndmask_b32_e32 v14, v15, v14, vcc
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13]
; SDAG-NEXT: v_and_b32_e32 v12, 1, v14
; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v12
; SDAG-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v15, v9, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v15, v7, 0, s[4:5]
; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1
-; SDAG-NEXT: v_cndmask_b32_e64 v14, v8, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v14, v6, 0, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v13, v5, 0, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v12, v4, 0, s[4:5]
; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB0_12
; SDAG-NEXT: ; %bb.7: ; %udiv-bb1
-; SDAG-NEXT: v_add_i32_e32 v30, vcc, 1, v6
-; SDAG-NEXT: v_sub_i32_e64 v12, s[4:5], 63, v6
-; SDAG-NEXT: v_addc_u32_e32 v31, vcc, 0, v7, vcc
+; SDAG-NEXT: v_add_i32_e32 v26, vcc, 1, v8
+; SDAG-NEXT: v_sub_i32_e64 v12, s[4:5], 63, v8
+; SDAG-NEXT: v_addc_u32_e32 v27, vcc, 0, v9, vcc
; SDAG-NEXT: v_lshl_b64 v[12:13], v[4:5], v12
-; SDAG-NEXT: v_addc_u32_e32 v32, vcc, 0, v10, vcc
-; SDAG-NEXT: v_addc_u32_e32 v33, vcc, 0, v11, vcc
-; SDAG-NEXT: v_or_b32_e32 v10, v30, v32
-; SDAG-NEXT: v_sub_i32_e32 v16, vcc, 0x7f, v6
-; SDAG-NEXT: v_or_b32_e32 v11, v31, v33
-; SDAG-NEXT: v_lshl_b64 v[6:7], v[8:9], v16
-; SDAG-NEXT: v_sub_i32_e32 v17, vcc, 64, v16
-; SDAG-NEXT: v_lshl_b64 v[14:15], v[4:5], v16
-; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
-; SDAG-NEXT: v_lshr_b64 v[10:11], v[4:5], v17
-; SDAG-NEXT: v_or_b32_e32 v7, v7, v11
-; SDAG-NEXT: v_or_b32_e32 v6, v6, v10
-; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v16
-; SDAG-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v6, v12, v6, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, v15, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, v14, s[4:5]
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; SDAG-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; SDAG-NEXT: v_addc_u32_e32 v28, vcc, 0, v10, vcc
+; SDAG-NEXT: v_addc_u32_e32 v29, vcc, 0, v11, vcc
+; SDAG-NEXT: v_or_b32_e32 v9, v26, v28
+; SDAG-NEXT: v_sub_i32_e32 v11, vcc, 0x7f, v8
+; SDAG-NEXT: v_or_b32_e32 v10, v27, v29
+; SDAG-NEXT: v_lshl_b64 v[14:15], v[6:7], v11
+; SDAG-NEXT: v_sub_i32_e32 v8, vcc, 64, v11
+; SDAG-NEXT: v_lshl_b64 v[16:17], v[4:5], v11
+; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10]
+; SDAG-NEXT: v_lshr_b64 v[8:9], v[4:5], v8
+; SDAG-NEXT: v_or_b32_e32 v9, v15, v9
+; SDAG-NEXT: v_or_b32_e32 v8, v14, v8
+; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v11
+; SDAG-NEXT: v_cndmask_b32_e64 v10, v13, v9, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v12, v12, v8, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v9, 0, v17, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v8, 0, v16, s[4:5]
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11
+; SDAG-NEXT: v_cndmask_b32_e64 v11, v10, v7, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v10, v12, v6, s[4:5]
; SDAG-NEXT: v_mov_b32_e32 v12, 0
; SDAG-NEXT: v_mov_b32_e32 v13, 0
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB0_11
; SDAG-NEXT: ; %bb.8: ; %udiv-preheader
-; SDAG-NEXT: v_lshr_b64 v[16:17], v[4:5], v30
-; SDAG-NEXT: v_sub_i32_e32 v12, vcc, 64, v30
-; SDAG-NEXT: v_subrev_i32_e32 v35, vcc, 64, v30
-; SDAG-NEXT: v_lshr_b64 v[37:38], v[8:9], v30
-; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v29
+; SDAG-NEXT: v_lshr_b64 v[16:17], v[4:5], v26
+; SDAG-NEXT: v_sub_i32_e32 v12, vcc, 64, v26
+; SDAG-NEXT: v_subrev_i32_e32 v31, vcc, 64, v26
+; SDAG-NEXT: v_lshr_b64 v[33:34], v[6:7], v26
+; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v23
; SDAG-NEXT: v_mov_b32_e32 v14, 0
; SDAG-NEXT: v_mov_b32_e32 v15, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0
; SDAG-NEXT: v_mov_b32_e32 v13, 0
-; SDAG-NEXT: v_lshl_b64 v[48:49], v[8:9], v12
-; SDAG-NEXT: v_lshr_b64 v[8:9], v[8:9], v35
-; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v28, vcc
-; SDAG-NEXT: v_or_b32_e32 v12, v17, v49
-; SDAG-NEXT: v_or_b32_e32 v16, v16, v48
-; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v2, vcc
-; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v30
-; SDAG-NEXT: v_cndmask_b32_e64 v9, v9, v12, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v8, v8, v16, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v17, 0, v38, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v16, 0, v37, s[4:5]
-; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v3, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v30
-; SDAG-NEXT: v_cndmask_b32_e32 v9, v9, v5, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v8, v8, v4, vcc
+; SDAG-NEXT: v_lshl_b64 v[35:36], v[6:7], v12
+; SDAG-NEXT: v_lshr_b64 v[6:7], v[6:7], v31
+; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v22, vcc
+; SDAG-NEXT: v_or_b32_e32 v12, v17, v36
+; SDAG-NEXT: v_or_b32_e32 v16, v16, v35
+; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v2, vcc
+; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v26
+; SDAG-NEXT: v_cndmask_b32_e64 v7, v7, v12, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v6, v6, v16, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v17, 0, v34, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v16, 0, v33, s[4:5]
+; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v3, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v26
+; SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v5, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc
; SDAG-NEXT: v_mov_b32_e32 v4, 0
; SDAG-NEXT: v_mov_b32_e32 v5, 0
; SDAG-NEXT: .LBB0_9: ; %udiv-do-while
; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v12, 31, v9
-; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v38, 31, v7
+; SDAG-NEXT: v_lshrrev_b32_e32 v12, 31, v7
; SDAG-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v39, 31, v11
+; SDAG-NEXT: v_lshrrev_b32_e32 v34, 31, v11
; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
-; SDAG-NEXT: v_or_b32_e32 v12, v16, v12
-; SDAG-NEXT: v_or_b32_e32 v8, v8, v38
-; SDAG-NEXT: v_or_b32_e32 v6, v6, v39
-; SDAG-NEXT: v_or_b32_e32 v7, v15, v7
-; SDAG-NEXT: v_or_b32_e32 v11, v5, v11
-; SDAG-NEXT: v_sub_i32_e32 v5, vcc, v34, v8
-; SDAG-NEXT: v_or_b32_e32 v6, v14, v6
-; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v35, v9, vcc
-; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v36, v12, vcc
-; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v37, v17, vcc
+; SDAG-NEXT: v_lshrrev_b32_e32 v35, 31, v9
+; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
+; SDAG-NEXT: v_or_b32_e32 v16, v16, v12
+; SDAG-NEXT: v_or_b32_e32 v6, v6, v34
+; SDAG-NEXT: v_or_b32_e32 v10, v10, v35
+; SDAG-NEXT: v_or_b32_e32 v11, v15, v11
+; SDAG-NEXT: v_or_b32_e32 v9, v5, v9
+; SDAG-NEXT: v_or_b32_e32 v10, v14, v10
+; SDAG-NEXT: v_sub_i32_e32 v5, vcc, v30, v6
+; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v31, v7, vcc
+; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v32, v16, vcc
+; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v33, v17, vcc
; SDAG-NEXT: v_ashrrev_i32_e32 v5, 31, v5
-; SDAG-NEXT: v_and_b32_e32 v16, v5, v29
-; SDAG-NEXT: v_and_b32_e32 v38, v5, v28
-; SDAG-NEXT: v_and_b32_e32 v39, v5, v2
-; SDAG-NEXT: v_and_b32_e32 v48, v5, v3
-; SDAG-NEXT: v_sub_i32_e32 v8, vcc, v8, v16
-; SDAG-NEXT: v_subb_u32_e32 v9, vcc, v9, v38, vcc
-; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v12, v39, vcc
-; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v17, v48, vcc
-; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v30
-; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc
-; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc
-; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc
-; SDAG-NEXT: v_or_b32_e32 v38, v30, v32
-; SDAG-NEXT: v_or_b32_e32 v39, v31, v33
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[38:39]
; SDAG-NEXT: v_and_b32_e32 v12, 1, v5
+; SDAG-NEXT: v_and_b32_e32 v34, v5, v3
+; SDAG-NEXT: v_and_b32_e32 v35, v5, v2
+; SDAG-NEXT: v_and_b32_e32 v36, v5, v22
+; SDAG-NEXT: v_and_b32_e32 v5, v5, v23
+; SDAG-NEXT: v_sub_i32_e32 v6, vcc, v6, v5
+; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v7, v36, vcc
+; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v16, v35, vcc
+; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v17, v34, vcc
+; SDAG-NEXT: v_add_i32_e32 v26, vcc, -1, v26
+; SDAG-NEXT: v_addc_u32_e32 v27, vcc, -1, v27, vcc
+; SDAG-NEXT: v_addc_u32_e32 v28, vcc, -1, v28, vcc
+; SDAG-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc
+; SDAG-NEXT: v_or_b32_e32 v35, v27, v29
+; SDAG-NEXT: v_or_b32_e32 v34, v26, v28
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[34:35]
; SDAG-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
-; SDAG-NEXT: v_or_b32_e32 v10, v4, v10
+; SDAG-NEXT: v_or_b32_e32 v8, v4, v8
; SDAG-NEXT: v_mov_b32_e32 v4, v12
; SDAG-NEXT: v_mov_b32_e32 v5, v13
; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11]
@@ -384,17 +380,17 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: s_or_b64 exec, exec, s[10:11]
; SDAG-NEXT: .LBB0_11: ; %Flow11
; SDAG-NEXT: s_or_b64 exec, exec, s[8:9]
-; SDAG-NEXT: v_lshl_b64 v[14:15], v[6:7], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v4, 31, v11
-; SDAG-NEXT: v_lshl_b64 v[2:3], v[10:11], 1
+; SDAG-NEXT: v_lshl_b64 v[14:15], v[10:11], 1
+; SDAG-NEXT: v_lshrrev_b32_e32 v4, 31, v9
+; SDAG-NEXT: v_lshl_b64 v[2:3], v[8:9], 1
; SDAG-NEXT: v_or_b32_e32 v14, v14, v4
; SDAG-NEXT: v_or_b32_e32 v13, v13, v3
; SDAG-NEXT: v_or_b32_e32 v12, v12, v2
; SDAG-NEXT: .LBB0_12: ; %Flow12
; SDAG-NEXT: s_or_b64 exec, exec, s[6:7]
-; SDAG-NEXT: v_xor_b32_e32 v3, v27, v26
+; SDAG-NEXT: v_xor_b32_e32 v3, v25, v24
; SDAG-NEXT: v_xor_b32_e32 v2, v25, v24
-; SDAG-NEXT: v_xor_b32_e32 v7, v23, v22
+; SDAG-NEXT: v_xor_b32_e32 v7, v19, v18
; SDAG-NEXT: v_xor_b32_e32 v6, v19, v18
; SDAG-NEXT: v_xor_b32_e32 v4, v1, v3
; SDAG-NEXT: v_xor_b32_e32 v5, v0, v2
@@ -993,14 +989,14 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cndmask_b32_e32 v20, v20, v22, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v0, v20, v0, s[4:5]
; SDAG-NEXT: v_lshr_b64 v[16:17], v[16:17], v26
-; SDAG-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v23, 0, v17, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v22, 0, v16, vcc
; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v8
; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v9, vcc
; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v10, vcc
; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v11, vcc
-; SDAG-NEXT: v_mov_b32_e32 v22, 0
-; SDAG-NEXT: v_mov_b32_e32 v23, 0
+; SDAG-NEXT: v_mov_b32_e32 v16, 0
+; SDAG-NEXT: v_mov_b32_e32 v17, 0
; SDAG-NEXT: s_mov_b64 s[4:5], 0
; SDAG-NEXT: v_mov_b32_e32 v21, 0
; SDAG-NEXT: v_mov_b32_e32 v24, 0
@@ -1011,25 +1007,25 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
; SDAG-NEXT: v_or_b32_e32 v19, v25, v19
; SDAG-NEXT: v_or_b32_e32 v18, v24, v18
-; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
+; SDAG-NEXT: v_lshl_b64 v[22:23], v[22:23], 1
; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v1
; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
-; SDAG-NEXT: v_or_b32_e32 v16, v16, v20
-; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v3
-; SDAG-NEXT: v_or_b32_e32 v0, v0, v20
-; SDAG-NEXT: v_sub_i32_e32 v20, vcc, v30, v0
-; SDAG-NEXT: v_subb_u32_e32 v20, vcc, v31, v1, vcc
-; SDAG-NEXT: v_subb_u32_e32 v20, vcc, v32, v16, vcc
-; SDAG-NEXT: v_subb_u32_e32 v20, vcc, v33, v17, vcc
-; SDAG-NEXT: v_ashrrev_i32_e32 v20, 31, v20
-; SDAG-NEXT: v_and_b32_e32 v24, v20, v8
-; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v24
-; SDAG-NEXT: v_and_b32_e32 v24, v20, v9
-; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v24, vcc
-; SDAG-NEXT: v_and_b32_e32 v24, v20, v10
-; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v16, v24, vcc
-; SDAG-NEXT: v_and_b32_e32 v24, v20, v11
-; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v17, v24, vcc
+; SDAG-NEXT: v_or_b32_e32 v20, v22, v20
+; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v3
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v22
+; SDAG-NEXT: v_sub_i32_e32 v22, vcc, v30, v0
+; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v31, v1, vcc
+; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v32, v20, vcc
+; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v33, v23, vcc
+; SDAG-NEXT: v_ashrrev_i32_e32 v35, 31, v22
+; SDAG-NEXT: v_and_b32_e32 v22, v35, v8
+; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v22
+; SDAG-NEXT: v_and_b32_e32 v22, v35, v9
+; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v22, vcc
+; SDAG-NEXT: v_and_b32_e32 v22, v35, v10
+; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v20, v22, vcc
+; SDAG-NEXT: v_and_b32_e32 v20, v35, v11
+; SDAG-NEXT: v_subb_u32_e32 v23, vcc, v23, v20, vcc
; SDAG-NEXT: v_add_i32_e32 v26, vcc, -1, v26
; SDAG-NEXT: v_addc_u32_e32 v27, vcc, -1, v27, vcc
; SDAG-NEXT: v_addc_u32_e32 v28, vcc, -1, v28, vcc
@@ -1037,12 +1033,12 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_or_b32_e32 v24, v26, v28
; SDAG-NEXT: v_or_b32_e32 v25, v27, v29
; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[24:25]
-; SDAG-NEXT: v_and_b32_e32 v20, 1, v20
+; SDAG-NEXT: v_and_b32_e32 v20, 1, v35
; SDAG-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; SDAG-NEXT: v_or_b32_e32 v2, v2, v34
-; SDAG-NEXT: v_or_b32_e32 v3, v23, v3
+; SDAG-NEXT: v_or_b32_e32 v3, v17, v3
; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; SDAG-NEXT: v_or_b32_e32 v2, v22, v2
+; SDAG-NEXT: v_or_b32_e32 v2, v16, v2
; SDAG-NEXT: v_mov_b32_e32 v25, v21
; SDAG-NEXT: v_mov_b32_e32 v24, v20
; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5]
@@ -1638,13 +1634,11 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-LABEL: v_srem_v2i128_vv:
; SDAG: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases
; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SDAG-NEXT: v_sub_i32_e32 v16, vcc, 0, v0
; SDAG-NEXT: v_mov_b32_e32 v19, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0x7f
; SDAG-NEXT: v_ashrrev_i32_e32 v28, 31, v3
; SDAG-NEXT: v_subb_u32_e32 v17, vcc, 0, v1, vcc
-; SDAG-NEXT: v_mov_b32_e32 v29, v28
; SDAG-NEXT: v_subb_u32_e32 v18, vcc, 0, v2, vcc
; SDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v3
; SDAG-NEXT: v_cndmask_b32_e64 v17, v1, v17, s[4:5]
@@ -1665,9 +1659,9 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_ffbh_u32_e32 v20, v1
; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[2:3]
; SDAG-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v11
-; SDAG-NEXT: v_cndmask_b32_e64 v30, v9, v23, s[6:7]
+; SDAG-NEXT: v_cndmask_b32_e64 v29, v9, v23, s[6:7]
; SDAG-NEXT: v_subb_u32_e32 v2, vcc, 0, v10, vcc
-; SDAG-NEXT: v_cndmask_b32_e64 v31, v8, v21, s[6:7]
+; SDAG-NEXT: v_cndmask_b32_e64 v30, v8, v21, s[6:7]
; SDAG-NEXT: v_min_u32_e32 v3, v22, v20
; SDAG-NEXT: v_add_i32_e64 v8, s[8:9], 64, v18
; SDAG-NEXT: v_addc_u32_e64 v9, s[8:9], 0, 0, s[8:9]
@@ -1676,13 +1670,13 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
; SDAG-NEXT: v_cndmask_b32_e64 v20, v9, 0, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v10, v8, v3, vcc
-; SDAG-NEXT: v_ffbh_u32_e32 v9, v31
-; SDAG-NEXT: v_ffbh_u32_e32 v21, v30
+; SDAG-NEXT: v_ffbh_u32_e32 v9, v30
+; SDAG-NEXT: v_ffbh_u32_e32 v21, v29
; SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v18, s[6:7]
-; SDAG-NEXT: v_or_b32_e32 v8, v31, v2
+; SDAG-NEXT: v_or_b32_e32 v8, v30, v2
; SDAG-NEXT: v_add_i32_e32 v11, vcc, 32, v9
; SDAG-NEXT: v_ffbh_u32_e32 v18, v2
-; SDAG-NEXT: v_or_b32_e32 v9, v30, v3
+; SDAG-NEXT: v_or_b32_e32 v9, v29, v3
; SDAG-NEXT: v_min_u32_e32 v11, v11, v21
; SDAG-NEXT: v_add_i32_e32 v18, vcc, 32, v18
; SDAG-NEXT: v_ffbh_u32_e32 v21, v3
@@ -1714,21 +1708,21 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_cndmask_b32_e64 v9, v1, 0, s[4:5]
; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; SDAG-NEXT: v_cndmask_b32_e64 v8, v0, 0, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v33, v17, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v32, v17, 0, s[4:5]
; SDAG-NEXT: s_and_b64 s[8:9], s[6:7], vcc
-; SDAG-NEXT: v_cndmask_b32_e64 v34, v16, 0, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v33, v16, 0, s[4:5]
; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[8:9]
; SDAG-NEXT: s_cbranch_execz .LBB4_6
; SDAG-NEXT: ; %bb.1: ; %udiv-bb15
-; SDAG-NEXT: v_add_i32_e32 v32, vcc, 1, v10
+; SDAG-NEXT: v_add_i32_e32 v31, vcc, 1, v10
; SDAG-NEXT: v_sub_i32_e64 v8, s[4:5], 63, v10
-; SDAG-NEXT: v_addc_u32_e32 v33, vcc, 0, v11, vcc
+; SDAG-NEXT: v_addc_u32_e32 v32, vcc, 0, v11, vcc
; SDAG-NEXT: v_lshl_b64 v[8:9], v[16:17], v8
-; SDAG-NEXT: v_addc_u32_e32 v34, vcc, 0, v18, vcc
-; SDAG-NEXT: v_addc_u32_e32 v35, vcc, 0, v19, vcc
-; SDAG-NEXT: v_or_b32_e32 v18, v32, v34
+; SDAG-NEXT: v_addc_u32_e32 v33, vcc, 0, v18, vcc
+; SDAG-NEXT: v_addc_u32_e32 v34, vcc, 0, v19, vcc
+; SDAG-NEXT: v_or_b32_e32 v18, v31, v33
; SDAG-NEXT: v_sub_i32_e32 v22, vcc, 0x7f, v10
-; SDAG-NEXT: v_or_b32_e32 v19, v33, v35
+; SDAG-NEXT: v_or_b32_e32 v19, v32, v34
; SDAG-NEXT: v_lshl_b64 v[10:11], v[0:1], v22
; SDAG-NEXT: v_sub_i32_e32 v23, vcc, 64, v22
; SDAG-NEXT: v_lshl_b64 v[20:21], v[16:17], v22
@@ -1750,28 +1744,28 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB4_5
; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4
-; SDAG-NEXT: v_lshr_b64 v[22:23], v[16:17], v32
-; SDAG-NEXT: v_sub_i32_e32 v10, vcc, 64, v32
-; SDAG-NEXT: v_subrev_i32_e32 v37, vcc, 64, v32
-; SDAG-NEXT: v_lshr_b64 v[24:25], v[0:1], v32
-; SDAG-NEXT: v_add_i32_e32 v36, vcc, -1, v31
+; SDAG-NEXT: v_lshr_b64 v[22:23], v[16:17], v31
+; SDAG-NEXT: v_sub_i32_e32 v10, vcc, 64, v31
+; SDAG-NEXT: v_subrev_i32_e32 v36, vcc, 64, v31
+; SDAG-NEXT: v_lshr_b64 v[24:25], v[0:1], v31
+; SDAG-NEXT: v_add_i32_e32 v35, vcc, -1, v30
; SDAG-NEXT: v_mov_b32_e32 v20, 0
; SDAG-NEXT: v_mov_b32_e32 v21, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0
; SDAG-NEXT: v_mov_b32_e32 v11, 0
; SDAG-NEXT: v_lshl_b64 v[26:27], v[0:1], v10
-; SDAG-NEXT: v_lshr_b64 v[48:49], v[0:1], v37
-; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v30, vcc
+; SDAG-NEXT: v_lshr_b64 v[38:39], v[0:1], v36
+; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v29, vcc
; SDAG-NEXT: v_or_b32_e32 v10, v23, v27
; SDAG-NEXT: v_or_b32_e32 v22, v22, v26
-; SDAG-NEXT: v_addc_u32_e32 v38, vcc, -1, v2, vcc
-; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v32
-; SDAG-NEXT: v_cndmask_b32_e64 v10, v49, v10, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v22, v48, v22, s[4:5]
+; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v2, vcc
+; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v31
+; SDAG-NEXT: v_cndmask_b32_e64 v10, v39, v10, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v22, v38, v22, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v27, 0, v25, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v26, 0, v24, s[4:5]
-; SDAG-NEXT: v_addc_u32_e32 v39, vcc, -1, v3, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v32
+; SDAG-NEXT: v_addc_u32_e32 v38, vcc, -1, v3, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
; SDAG-NEXT: v_cndmask_b32_e32 v25, v10, v17, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v24, v22, v16, vcc
; SDAG-NEXT: v_mov_b32_e32 v22, 0
@@ -1781,35 +1775,35 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_lshrrev_b32_e32 v10, 31, v19
; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
; SDAG-NEXT: v_lshl_b64 v[26:27], v[26:27], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v48, 31, v25
+; SDAG-NEXT: v_lshrrev_b32_e32 v39, 31, v25
; SDAG-NEXT: v_lshl_b64 v[24:25], v[24:25], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v49, 31, v9
+; SDAG-NEXT: v_lshrrev_b32_e32 v48, 31, v9
; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; SDAG-NEXT: v_or_b32_e32 v19, v23, v19
; SDAG-NEXT: v_or_b32_e32 v18, v22, v18
-; SDAG-NEXT: v_or_b32_e32 v22, v26, v48
-; SDAG-NEXT: v_or_b32_e32 v23, v24, v49
+; SDAG-NEXT: v_or_b32_e32 v22, v26, v39
+; SDAG-NEXT: v_or_b32_e32 v23, v24, v48
; SDAG-NEXT: v_or_b32_e32 v8, v8, v10
-; SDAG-NEXT: v_sub_i32_e32 v10, vcc, v36, v23
-; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v37, v25, vcc
-; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v38, v22, vcc
-; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v39, v27, vcc
+; SDAG-NEXT: v_sub_i32_e32 v10, vcc, v35, v23
+; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v36, v25, vcc
+; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v37, v22, vcc
+; SDAG-NEXT: v_subb_u32_e32 v10, vcc, v38, v27, vcc
; SDAG-NEXT: v_ashrrev_i32_e32 v10, 31, v10
-; SDAG-NEXT: v_and_b32_e32 v24, v10, v31
-; SDAG-NEXT: v_and_b32_e32 v26, v10, v30
-; SDAG-NEXT: v_and_b32_e32 v48, v10, v2
-; SDAG-NEXT: v_and_b32_e32 v49, v10, v3
+; SDAG-NEXT: v_and_b32_e32 v24, v10, v30
+; SDAG-NEXT: v_and_b32_e32 v26, v10, v29
+; SDAG-NEXT: v_and_b32_e32 v39, v10, v2
+; SDAG-NEXT: v_and_b32_e32 v48, v10, v3
; SDAG-NEXT: v_and_b32_e32 v10, 1, v10
; SDAG-NEXT: v_sub_i32_e32 v24, vcc, v23, v24
; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v26, vcc
-; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v22, v48, vcc
-; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v49, vcc
-; SDAG-NEXT: v_add_i32_e32 v32, vcc, -1, v32
+; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v22, v39, vcc
+; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v48, vcc
+; SDAG-NEXT: v_add_i32_e32 v31, vcc, -1, v31
+; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc
; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc
; SDAG-NEXT: v_addc_u32_e32 v34, vcc, -1, v34, vcc
-; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v35, vcc
-; SDAG-NEXT: v_or_b32_e32 v22, v32, v34
-; SDAG-NEXT: v_or_b32_e32 v23, v33, v35
+; SDAG-NEXT: v_or_b32_e32 v22, v31, v33
+; SDAG-NEXT: v_or_b32_e32 v23, v32, v34
; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[22:23]
; SDAG-NEXT: v_or_b32_e32 v9, v21, v9
; SDAG-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
@@ -1826,15 +1820,14 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v19
; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
; SDAG-NEXT: v_or_b32_e32 v8, v8, v20
-; SDAG-NEXT: v_or_b32_e32 v33, v11, v19
-; SDAG-NEXT: v_or_b32_e32 v34, v10, v18
+; SDAG-NEXT: v_or_b32_e32 v32, v11, v19
+; SDAG-NEXT: v_or_b32_e32 v33, v10, v18
; SDAG-NEXT: .LBB4_6: ; %Flow16
; SDAG-NEXT: s_or_b64 exec, exec, s[6:7]
-; SDAG-NEXT: v_ashrrev_i32_e32 v32, 31, v7
+; SDAG-NEXT: v_ashrrev_i32_e32 v31, 31, v7
; SDAG-NEXT: v_sub_i32_e32 v10, vcc, 0, v4
; SDAG-NEXT: v_mov_b32_e32 v19, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0x7f
-; SDAG-NEXT: v_mov_b32_e32 v35, v32
; SDAG-NEXT: v_subb_u32_e32 v11, vcc, 0, v5, vcc
; SDAG-NEXT: v_subb_u32_e32 v18, vcc, 0, v6, vcc
; SDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v7
@@ -1856,24 +1849,24 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_min_u32_e32 v18, v18, v20
; SDAG-NEXT: v_subb_u32_e32 v20, vcc, 0, v14, vcc
; SDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v15
-; SDAG-NEXT: v_cndmask_b32_e64 v36, v13, v23, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v37, v12, v21, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v34, v13, v23, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v35, v12, v21, s[4:5]
; SDAG-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[6:7]
; SDAG-NEXT: v_min_u32_e32 v7, v22, v24
; SDAG-NEXT: v_add_i32_e64 v12, s[8:9], 64, v18
; SDAG-NEXT: v_addc_u32_e64 v13, s[8:9], 0, 0, s[8:9]
; SDAG-NEXT: v_subb_u32_e32 v18, vcc, 0, v15, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v20, s[4:5]
-; SDAG-NEXT: v_ffbh_u32_e32 v14, v37
-; SDAG-NEXT: v_ffbh_u32_e32 v20, v36
+; SDAG-NEXT: v_ffbh_u32_e32 v14, v35
+; SDAG-NEXT: v_ffbh_u32_e32 v20, v34
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v21, v13, 0, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v22, v12, v7, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v18, s[4:5]
-; SDAG-NEXT: v_or_b32_e32 v12, v37, v6
+; SDAG-NEXT: v_or_b32_e32 v12, v35, v6
; SDAG-NEXT: v_ffbh_u32_e32 v15, v6
; SDAG-NEXT: v_add_i32_e32 v14, vcc, 32, v14
-; SDAG-NEXT: v_or_b32_e32 v13, v36, v7
+; SDAG-NEXT: v_or_b32_e32 v13, v34, v7
; SDAG-NEXT: v_add_i32_e32 v15, vcc, 32, v15
; SDAG-NEXT: v_ffbh_u32_e32 v18, v7
; SDAG-NEXT: v_min_u32_e32 v14, v14, v20
@@ -1911,15 +1904,15 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB4_12
; SDAG-NEXT: ; %bb.7: ; %udiv-bb1
-; SDAG-NEXT: v_add_i32_e32 v38, vcc, 1, v12
+; SDAG-NEXT: v_add_i32_e32 v36, vcc, 1, v12
; SDAG-NEXT: v_sub_i32_e64 v14, s[4:5], 63, v12
-; SDAG-NEXT: v_addc_u32_e32 v39, vcc, 0, v13, vcc
+; SDAG-NEXT: v_addc_u32_e32 v37, vcc, 0, v13, vcc
; SDAG-NEXT: v_lshl_b64 v[13:14], v[10:11], v14
-; SDAG-NEXT: v_addc_u32_e32 v48, vcc, 0, v18, vcc
-; SDAG-NEXT: v_addc_u32_e32 v49, vcc, 0, v19, vcc
-; SDAG-NEXT: v_or_b32_e32 v18, v38, v48
+; SDAG-NEXT: v_addc_u32_e32 v38, vcc, 0, v18, vcc
+; SDAG-NEXT: v_addc_u32_e32 v39, vcc, 0, v19, vcc
+; SDAG-NEXT: v_or_b32_e32 v18, v36, v38
; SDAG-NEXT: v_sub_i32_e32 v15, vcc, 0x7f, v12
-; SDAG-NEXT: v_or_b32_e32 v19, v39, v49
+; SDAG-NEXT: v_or_b32_e32 v19, v37, v39
; SDAG-NEXT: v_lshl_b64 v[20:21], v[4:5], v15
; SDAG-NEXT: v_sub_i32_e32 v12, vcc, 64, v15
; SDAG-NEXT: v_lshl_b64 v[22:23], v[10:11], v15
@@ -1941,28 +1934,28 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB4_11
; SDAG-NEXT: ; %bb.8: ; %udiv-preheader
-; SDAG-NEXT: v_lshr_b64 v[22:23], v[10:11], v38
-; SDAG-NEXT: v_sub_i32_e32 v18, vcc, 64, v38
-; SDAG-NEXT: v_subrev_i32_e32 v51, vcc, 64, v38
-; SDAG-NEXT: v_lshr_b64 v[24:25], v[4:5], v38
-; SDAG-NEXT: v_add_i32_e32 v50, vcc, -1, v37
+; SDAG-NEXT: v_lshr_b64 v[22:23], v[10:11], v36
+; SDAG-NEXT: v_sub_i32_e32 v18, vcc, 64, v36
+; SDAG-NEXT: v_subrev_i32_e32 v49, vcc, 64, v36
+; SDAG-NEXT: v_lshr_b64 v[24:25], v[4:5], v36
+; SDAG-NEXT: v_add_i32_e32 v48, vcc, -1, v35
; SDAG-NEXT: v_mov_b32_e32 v20, 0
; SDAG-NEXT: v_mov_b32_e32 v21, 0
; SDAG-NEXT: s_mov_b64 s[10:11], 0
; SDAG-NEXT: v_mov_b32_e32 v19, 0
; SDAG-NEXT: v_lshl_b64 v[26:27], v[4:5], v18
-; SDAG-NEXT: v_lshr_b64 v[53:54], v[4:5], v51
-; SDAG-NEXT: v_addc_u32_e32 v51, vcc, -1, v36, vcc
+; SDAG-NEXT: v_lshr_b64 v[51:52], v[4:5], v49
+; SDAG-NEXT: v_addc_u32_e32 v49, vcc, -1, v34, vcc
; SDAG-NEXT: v_or_b32_e32 v18, v23, v27
; SDAG-NEXT: v_or_b32_e32 v22, v22, v26
-; SDAG-NEXT: v_addc_u32_e32 v52, vcc, -1, v6, vcc
-; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v38
-; SDAG-NEXT: v_cndmask_b32_e64 v18, v54, v18, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v22, v53, v22, s[4:5]
+; SDAG-NEXT: v_addc_u32_e32 v50, vcc, -1, v6, vcc
+; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v36
+; SDAG-NEXT: v_cndmask_b32_e64 v18, v52, v18, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v22, v51, v22, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v27, 0, v25, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v26, 0, v24, s[4:5]
-; SDAG-NEXT: v_addc_u32_e32 v53, vcc, -1, v7, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v38
+; SDAG-NEXT: v_addc_u32_e32 v51, vcc, -1, v7, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v36
; SDAG-NEXT: v_cndmask_b32_e32 v25, v18, v11, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v24, v22, v10, vcc
; SDAG-NEXT: v_mov_b32_e32 v22, 0
@@ -1972,37 +1965,37 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_lshl_b64 v[26:27], v[26:27], 1
; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v25
; SDAG-NEXT: v_lshl_b64 v[24:25], v[24:25], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v54, 31, v15
+; SDAG-NEXT: v_lshrrev_b32_e32 v52, 31, v15
; SDAG-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
-; SDAG-NEXT: v_lshrrev_b32_e32 v55, 31, v13
+; SDAG-NEXT: v_lshrrev_b32_e32 v53, 31, v13
; SDAG-NEXT: v_lshl_b64 v[12:13], v[12:13], 1
; SDAG-NEXT: v_or_b32_e32 v26, v26, v18
-; SDAG-NEXT: v_or_b32_e32 v24, v24, v54
-; SDAG-NEXT: v_or_b32_e32 v14, v14, v55
+; SDAG-NEXT: v_or_b32_e32 v24, v24, v52
+; SDAG-NEXT: v_or_b32_e32 v14, v14, v53
; SDAG-NEXT: v_or_b32_e32 v15, v21, v15
; SDAG-NEXT: v_or_b32_e32 v13, v23, v13
; SDAG-NEXT: v_or_b32_e32 v14, v20, v14
-; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v50, v24
-; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v51, v25, vcc
-; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v52, v26, vcc
-; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v53, v27, vcc
+; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v48, v24
+; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v49, v25, vcc
+; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v50, v26, vcc
+; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v51, v27, vcc
; SDAG-NEXT: v_ashrrev_i32_e32 v23, 31, v18
; SDAG-NEXT: v_and_b32_e32 v18, 1, v23
-; SDAG-NEXT: v_and_b32_e32 v54, v23, v7
-; SDAG-NEXT: v_and_b32_e32 v55, v23, v6
-; SDAG-NEXT: v_and_b32_e32 v40, v23, v36
-; SDAG-NEXT: v_and_b32_e32 v23, v23, v37
+; SDAG-NEXT: v_and_b32_e32 v52, v23, v7
+; SDAG-NEXT: v_and_b32_e32 v53, v23, v6
+; SDAG-NEXT: v_and_b32_e32 v54, v23, v34
+; SDAG-NEXT: v_and_b32_e32 v23, v23, v35
; SDAG-NEXT: v_sub_i32_e32 v24, vcc, v24, v23
-; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v40, vcc
-; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v26, v55, vcc
-; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v54, vcc
-; SDAG-NEXT: v_add_i32_e32 v38, vcc, -1, v38
+; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v54, vcc
+; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v26, v53, vcc
+; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v52, vcc
+; SDAG-NEXT: v_add_i32_e32 v36, vcc, -1, v36
+; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v37, vcc
+; SDAG-NEXT: v_addc_u32_e32 v38, vcc, -1, v38, vcc
; SDAG-NEXT: v_addc_u32_e32 v39, vcc, -1, v39, vcc
-; SDAG-NEXT: v_addc_u32_e32 v48, vcc, -1, v48, vcc
-; SDAG-NEXT: v_addc_u32_e32 v49, vcc, -1, v49, vcc
-; SDAG-NEXT: v_or_b32_e32 v55, v39, v49
-; SDAG-NEXT: v_or_b32_e32 v54, v38, v48
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[54:55]
+; SDAG-NEXT: v_or_b32_e32 v53, v37, v39
+; SDAG-NEXT: v_or_b32_e32 v52, v36, v38
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[52:53]
; SDAG-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; SDAG-NEXT: v_or_b32_e32 v12, v22, v12
; SDAG-NEXT: v_mov_b32_e32 v23, v19
@@ -2021,42 +2014,42 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_or_b32_e32 v21, v18, v12
; SDAG-NEXT: .LBB4_12: ; %Flow12
; SDAG-NEXT: s_or_b64 exec, exec, s[6:7]
-; SDAG-NEXT: v_mul_lo_u32 v18, v34, v3
-; SDAG-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v34, v2, 0
-; SDAG-NEXT: v_mul_lo_u32 v19, v33, v2
-; SDAG-NEXT: v_mul_lo_u32 v25, v9, v31
-; SDAG-NEXT: v_mul_lo_u32 v26, v8, v30
-; SDAG-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v31, v34, 0
+; SDAG-NEXT: v_mul_lo_u32 v18, v33, v3
+; SDAG-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v33, v2, 0
+; SDAG-NEXT: v_mul_lo_u32 v19, v32, v2
+; SDAG-NEXT: v_mul_lo_u32 v25, v9, v30
+; SDAG-NEXT: v_mul_lo_u32 v26, v8, v29
+; SDAG-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v30, v33, 0
; SDAG-NEXT: v_mov_b32_e32 v24, 0
; SDAG-NEXT: v_mul_lo_u32 v9, v21, v7
; SDAG-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v21, v6, 0
; SDAG-NEXT: v_mul_lo_u32 v27, v20, v6
-; SDAG-NEXT: v_mul_lo_u32 v38, v15, v37
-; SDAG-NEXT: v_mul_lo_u32 v39, v14, v36
+; SDAG-NEXT: v_mul_lo_u32 v36, v15, v35
+; SDAG-NEXT: v_mul_lo_u32 v37, v14, v34
; SDAG-NEXT: v_add_i32_e32 v13, vcc, v13, v18
-; SDAG-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v30, v34, v[23:24]
+; SDAG-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v29, v33, v[23:24]
; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v16, v22
; SDAG-NEXT: v_add_i32_e64 v3, s[4:5], v3, v9
; SDAG-NEXT: v_add_i32_e64 v13, s[4:5], v13, v19
; SDAG-NEXT: v_mov_b32_e32 v23, v6
-; SDAG-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v31, v33, v[23:24]
+; SDAG-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v30, v32, v[23:24]
; SDAG-NEXT: v_xor_b32_e32 v18, v18, v28
; SDAG-NEXT: v_add_i32_e64 v3, s[4:5], v3, v27
-; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v8, v31, v[12:13]
+; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v8, v30, v[12:13]
; SDAG-NEXT: v_add_i32_e64 v6, s[4:5], v7, v16
; SDAG-NEXT: v_addc_u32_e64 v7, s[4:5], 0, 0, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v12, vcc, v17, v15, vcc
-; SDAG-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v14, v37, v[2:3]
-; SDAG-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v37, v21, 0
+; SDAG-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v14, v35, v[2:3]
+; SDAG-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v35, v21, 0
; SDAG-NEXT: v_add_i32_e64 v9, s[4:5], v25, v9
-; SDAG-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v30, v33, v[6:7]
-; SDAG-NEXT: v_xor_b32_e32 v16, v12, v29
-; SDAG-NEXT: v_add_i32_e64 v3, s[4:5], v38, v3
-; SDAG-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v36, v21, v[23:24]
+; SDAG-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v29, v32, v[6:7]
+; SDAG-NEXT: v_xor_b32_e32 v16, v12, v28
+; SDAG-NEXT: v_add_i32_e64 v3, s[4:5], v36, v3
+; SDAG-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v34, v21, v[23:24]
; SDAG-NEXT: v_add_i32_e64 v9, s[4:5], v26, v9
-; SDAG-NEXT: v_add_i32_e64 v3, s[4:5], v39, v3
+; SDAG-NEXT: v_add_i32_e64 v3, s[4:5], v37, v3
; SDAG-NEXT: v_mov_b32_e32 v23, v12
-; SDAG-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v37, v20, v[23:24]
+; SDAG-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v35, v20, v[23:24]
; SDAG-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8
; SDAG-NEXT: v_addc_u32_e64 v8, s[4:5], v7, v9, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v0, vcc, v0, v6, vcc
@@ -2064,28 +2057,26 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; SDAG-NEXT: v_addc_u32_e64 v7, s[4:5], 0, 0, s[4:5]
; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
; SDAG-NEXT: v_xor_b32_e32 v8, v0, v28
-; SDAG-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v36, v20, v[6:7]
-; SDAG-NEXT: v_xor_b32_e32 v9, v1, v29
+; SDAG-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v34, v20, v[6:7]
+; SDAG-NEXT: v_xor_b32_e32 v9, v1, v28
; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v18, v28
; SDAG-NEXT: v_add_i32_e64 v6, s[4:5], v6, v2
; SDAG-NEXT: v_addc_u32_e64 v7, s[4:5], v7, v3, s[4:5]
-; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v16, v29, vcc
+; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v16, v28, vcc
; SDAG-NEXT: v_subb_u32_e32 v2, vcc, v8, v28, vcc
-; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v9, v29, vcc
+; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v9, v28, vcc
; SDAG-NEXT: v_sub_i32_e32 v8, vcc, v10, v22
; SDAG-NEXT: v_subb_u32_e32 v9, vcc, v11, v14, vcc
-; SDAG-NEXT: v_xor_b32_e32 v8, v8, v32
+; SDAG-NEXT: v_xor_b32_e32 v8, v8, v31
; SDAG-NEXT: v_subb_u32_e32 v4, vcc, v4, v6, vcc
-; SDAG-NEXT: v_xor_b32_e32 v6, v9, v35
+; SDAG-NEXT: v_xor_b32_e32 v6, v9, v31
; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v5, v7, vcc
-; SDAG-NEXT: v_xor_b32_e32 v7, v4, v32
-; SDAG-NEXT: v_xor_b32_e32 v9, v5, v35
-; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v8, v32
-; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v6, v35, vcc
-; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v7, v32, vcc
-; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v9, v35, vcc
-; SDAG-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
-; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: v_xor_b32_e32 v7, v4, v31
+; SDAG-NEXT: v_xor_b32_e32 v9, v5, v31
+; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v8, v31
+; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v6, v31, vcc
+; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v7, v31, vcc
+; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v9, v31, vcc
; SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-LABEL: v_srem_v2i128_vv:
diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
index bec188e4e8378..430c4303eff7e 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
@@ -42,8 +42,7 @@ body: |
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[DEF]], %subreg.sub0, killed [[V_MOV_B32_e32_]], %subreg.sub1
- ; GCN-NEXT: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[DEF2]], [[REG_SEQUENCE]].sub0, implicit $exec
+ ; GCN-NEXT: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[DEF2]], [[DEF]], implicit $exec
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF
@@ -460,7 +459,6 @@ body: |
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1, [[V_MOV_B32_e32_2]], %subreg.sub2
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, [[COPY]], 1, 0, 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_ADD_F64_e64_]]
; GCN-NEXT: S_ENDPGM 0
@@ -489,7 +487,6 @@ body: |
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1, [[V_MOV_B32_e32_2]], %subreg.sub2
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_ADD_F64_e64 0, [[COPY]], 1, -1, 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_ADD_F64_e64_]]
; GCN-NEXT: S_ENDPGM 0
diff --git a/llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir b/llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
index a88b1ecc40cc9..6fc101f16b5d0 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
@@ -412,7 +412,6 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr8
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 %stack.0
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def $scc
; CHECK-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], 123, implicit-def $scc
; CHECK-NEXT: $sgpr4 = COPY [[S_ADD_I32_]]
diff --git a/llvm/test/CodeGen/AMDGPU/fold-readlane.mir b/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
index 3ac463b4fb448..ee764a9eaa6f3 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-readlane.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool build/hpe-sjc2-37-Release-all/bin/llc --version 6
# RUN: llc -mtriple=amdgcn -run-pass si-fold-operands -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: fold-imm-readfirstlane{{$}}
@@ -7,9 +8,9 @@ name: fold-imm-readfirstlane
tracksRegLiveness: true
body: |
bb.0:
- %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
- %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
- S_NOP 0, implicit %1
+ %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
+ %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
+ S_NOP 0, implicit %1
...
# GCN-LABEL: name: fold-imm-readfirstlane-dbgvalue{{$}}
@@ -20,10 +21,10 @@ name: fold-imm-readfirstlane-dbgvalue
tracksRegLiveness: true
body: |
bb.0:
- %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
- %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
- DBG_VALUE %0, 0, 0
- S_NOP 0, implicit %1
+ %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
+ %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
+ DBG_VALUE %0, 0, 0
+ S_NOP 0, implicit %1
...
# GCN-LABEL: name: fold-imm-readfirstlane-readfirstlane{{$}}
@@ -34,11 +35,11 @@ name: fold-imm-readfirstlane-readfirstlane
tracksRegLiveness: true
body: |
bb.0:
- %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
- %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
- %2:vgpr_32 = COPY %1
- %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2, implicit $exec
- S_NOP 0, implicit %3
+ %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
+ %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
+ %2:vgpr_32 = COPY %1
+ %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2, implicit $exec
+ S_NOP 0, implicit %3
...
@@ -50,11 +51,11 @@ name: fold-copy-readfirstlane
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr10
- %0:sreg_32_xm0 = COPY $sgpr10
- %1:vgpr_32 = COPY %0
- %2:sreg_32_xm0 = V_READFIRSTLANE_B32 %1, implicit $exec
- S_NOP 0, implicit %2
+ liveins: $sgpr10
+ %0:sreg_32_xm0 = COPY $sgpr10
+ %1:vgpr_32 = COPY %0
+ %2:sreg_32_xm0 = V_READFIRSTLANE_B32 %1, implicit $exec
+ S_NOP 0, implicit %2
...
# GCN-LABEL: name: no-fold-copy-readfirstlane-physreg0{{$}}
@@ -65,9 +66,9 @@ name: no-fold-copy-readfirstlane-physreg0
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr10
- %0:vgpr_32 = COPY $sgpr10
- %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
+ liveins: $sgpr10
+ %0:vgpr_32 = COPY $sgpr10
+ %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
...
@@ -79,9 +80,9 @@ name: no-fold-copy-readfirstlane-physreg1
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr10
- $vgpr0 = COPY $sgpr10
- %0:sreg_32_xm0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
+ liveins: $sgpr10
+ $vgpr0 = COPY $sgpr10
+ %0:sreg_32_xm0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
...
@@ -94,8 +95,8 @@ name: no-fold-imm-readfirstlane-physreg
tracksRegLiveness: true
body: |
bb.0:
- $vgpr0 = V_MOV_B32_e32 123, implicit $exec
- %0:sreg_32_xm0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
+ $vgpr0 = V_MOV_B32_e32 123, implicit $exec
+ %0:sreg_32_xm0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
...
# TODO: This could be folded, if the search for exec modifications was
@@ -109,10 +110,10 @@ name: fold-imm-readfirstlane-cross-block
tracksRegLiveness: true
body: |
bb.0:
- %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
+ %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
bb.1:
- %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
+ %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
...
# TODO: This could be folded, if the search for exec modifications was
@@ -126,12 +127,12 @@ name: fold-copy-readfirstlane-cross-block
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr12
- %0:sreg_32_xm0 = COPY $sgpr12
- %1:vgpr_32 = V_MOV_B32_e32 %0, implicit $exec
+ liveins: $sgpr12
+ %0:sreg_32_xm0 = COPY $sgpr12
+ %1:vgpr_32 = V_MOV_B32_e32 %0, implicit $exec
bb.1:
- %2:sreg_32_xm0 = V_READFIRSTLANE_B32 %1, implicit $exec
+ %2:sreg_32_xm0 = V_READFIRSTLANE_B32 %1, implicit $exec
...
# GCN-LABEL: name: fold-copy-readfirstlane-cross-block-exec-def{{$}}
@@ -143,13 +144,13 @@ name: fold-copy-readfirstlane-cross-block-exec-def
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr10_sgpr11, $sgpr12
- %0:sreg_32_xm0 = COPY $sgpr12
- %1:vgpr_32 = V_MOV_B32_e32 %0, implicit $exec
- $exec = S_MOV_B64_term $sgpr10_sgpr11
+ liveins: $sgpr10_sgpr11, $sgpr12
+ %0:sreg_32_xm0 = COPY $sgpr12
+ %1:vgpr_32 = V_MOV_B32_e32 %0, implicit $exec
+ $exec = S_MOV_B64_term $sgpr10_sgpr11
bb.1:
- %2:sreg_32_xm0 = V_READFIRSTLANE_B32 %1, implicit $exec
+ %2:sreg_32_xm0 = V_READFIRSTLANE_B32 %1, implicit $exec
...
# GCN-LABEL: name: fold-copy-readfirstlane-same-block-exec-def{{$}}
@@ -162,11 +163,11 @@ name: fold-copy-readfirstlane-same-block-exec-def
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr10_sgpr11, $sgpr12
- %0:sreg_32_xm0 = COPY $sgpr12
- %1:vgpr_32 = COPY %0, implicit $exec
- $exec = S_MOV_B64 $sgpr10_sgpr11
- %2:sreg_32_xm0 = V_READFIRSTLANE_B32 %1, implicit $exec
+ liveins: $sgpr10_sgpr11, $sgpr12
+ %0:sreg_32_xm0 = COPY $sgpr12
+ %1:vgpr_32 = COPY %0, implicit $exec
+ $exec = S_MOV_B64 $sgpr10_sgpr11
+ %2:sreg_32_xm0 = V_READFIRSTLANE_B32 %1, implicit $exec
...
@@ -180,12 +181,12 @@ name: fold-imm-readfirstlane-cross-block-exec-def
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr10_sgpr11, $sgpr12_sgpr13
- %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
- $exec = S_MOV_B64_term $sgpr10_sgpr11
+ liveins: $sgpr10_sgpr11, $sgpr12_sgpr13
+ %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
+ $exec = S_MOV_B64_term $sgpr10_sgpr11
bb.1:
- %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
+ %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
...
# GCN-LABEL: name: fold-imm-readfirstlane-same-block-exec-def{{$}}
@@ -197,10 +198,10 @@ name: fold-imm-readfirstlane-same-block-exec-def
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr10_sgpr11
- %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
- $exec = S_MOV_B64 $sgpr10_sgpr11
- %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
+ liveins: $sgpr10_sgpr11
+ %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
+ $exec = S_MOV_B64 $sgpr10_sgpr11
+ %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
...
@@ -213,10 +214,10 @@ name: fold-sgpr-copy-readfirstlane-same-block-exec-def
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr10_sgpr11, $sgpr12
- %0:vgpr_32 = COPY $sgpr12
- $exec = S_MOV_B64 $sgpr10_sgpr11
- %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
+ liveins: $sgpr10_sgpr11, $sgpr12
+ %0:vgpr_32 = COPY $sgpr12
+ $exec = S_MOV_B64 $sgpr10_sgpr11
+ %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
...
# GCN-LABEL: name: fold-imm-readfirstlane-user{{$}}
@@ -226,12 +227,12 @@ name: fold-imm-readfirstlane-user
tracksRegLiveness: true
body: |
bb.0:
- liveins: $vgpr0, $sgpr0_sgpr1
- %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
- %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
- %2:sreg_32_xm0 = COPY %1
- %3:sreg_32_xm0 = COPY %2
- S_ENDPGM 0, implicit %3
+ liveins: $vgpr0, $sgpr0_sgpr1
+ %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
+ %1:sreg_32_xm0 = V_READFIRSTLANE_B32 %0, implicit $exec
+ %2:sreg_32_xm0 = COPY %1
+ %3:sreg_32_xm0 = COPY %2
+ S_ENDPGM 0, implicit %3
...
# GCN-LABEL: name: fold-imm-readlane{{$}}
@@ -241,10 +242,10 @@ name: fold-imm-readlane
tracksRegLiveness: true
body: |
bb.0:
- liveins: $vgpr0, $sgpr0_sgpr1
- %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
- %1:sreg_32_xm0 = V_READLANE_B32 %0, 0, implicit $exec
- S_NOP 0, implicit %1
+ liveins: $vgpr0, $sgpr0_sgpr1
+ %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
+ %1:sreg_32_xm0 = V_READLANE_B32 %0, 0, implicit $exec
+ S_NOP 0, implicit %1
...
# GCN-LABEL: name: fold-imm-readlane-src1{{$}}
@@ -255,10 +256,10 @@ name: fold-imm-readlane-src1
tracksRegLiveness: true
body: |
bb.0:
- liveins: $vgpr0
- %0:vgpr_32 = COPY $vgpr0
- %1:sreg_32_xm0 = S_MOV_B32 12
- %2:sreg_32_xm0 = V_READLANE_B32 %0, %1, implicit $exec
+ liveins: $vgpr0
+ %0:vgpr_32 = COPY $vgpr0
+ %1:sreg_32_xm0 = S_MOV_B32 12
+ %2:sreg_32_xm0 = V_READLANE_B32 %0, %1, implicit $exec
...
# Constant for subreg0
@@ -274,13 +275,13 @@ name: fold-imm-readfirstlane-regsequence0
tracksRegLiveness: true
body: |
bb.0:
- liveins: $vgpr0
- %0:vgpr_32 = COPY $vgpr0
- %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
- %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
- %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
- S_NOP 0, implicit %3, implicit %4
+ liveins: $vgpr0
+ %0:vgpr_32 = COPY $vgpr0
+ %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
+ %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
+ %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
+ S_NOP 0, implicit %3, implicit %4
...
# Constant for subreg1
@@ -296,20 +297,19 @@ name: fold-imm-readfirstlane-regsequence1
tracksRegLiveness: true
body: |
bb.0:
- liveins: $vgpr0
- %0:vgpr_32 = COPY $vgpr0
- %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- %2:vreg_64 = REG_SEQUENCE %1:vgpr_32, %subreg.sub0, killed %0:vgpr_32, %subreg.sub1
- %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
- %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
- S_NOP 0, implicit %3, implicit %4
+ liveins: $vgpr0
+ %0:vgpr_32 = COPY $vgpr0
+ %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %2:vreg_64 = REG_SEQUENCE %1:vgpr_32, %subreg.sub0, killed %0:vgpr_32, %subreg.sub1
+ %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
+ %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
+ S_NOP 0, implicit %3, implicit %4
...
# Different constant regs for each subreg
# GCN-LABEL: name: fold-imm-readfirstlane-regsequence2{{$}}
# GCN: %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# GCN-NEXT: %1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-# GCN-NEXT: %2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, killed %1, %subreg.sub1
# GCN-NEXT: %3:sreg_32_xm0 = S_MOV_B32 0
# GCN-NEXT: %4:sreg_32_xm0 = S_MOV_B32 1
---
@@ -317,19 +317,18 @@ name: fold-imm-readfirstlane-regsequence2
tracksRegLiveness: true
body: |
bb.0:
- %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- %1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
- %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
- %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
- %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
- S_NOP 0, implicit %3, implicit %4
+ %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+ %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
+ %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
+ %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
+ S_NOP 0, implicit %3, implicit %4
...
# Same constant reg for each subreg, so there are multiple constant uses
# GCN-LABEL: name: fold-imm-readfirstlane-regsequence3{{$}}
# GCN: %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
# GCN-NEXT: %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-# GCN-NEXT: %2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, killed %1, %subreg.sub1
# GCN-NEXT: %3:sreg_32_xm0 = S_MOV_B32 0
# GCN-NEXT: %4:sreg_32_xm0 = S_MOV_B32 0
---
@@ -337,12 +336,12 @@ name: fold-imm-readfirstlane-regsequence3
tracksRegLiveness: true
body: |
bb.0:
- %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
- %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
- %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
- S_NOP 0, implicit %3, implicit %4
+ %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
+ %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
+ %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
+ S_NOP 0, implicit %3, implicit %4
...
# FIXME: This should fold
@@ -357,12 +356,12 @@ name: fold-copy-readfirstlane-regsequence0
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr10, $sgpr11
- %0:vgpr_32 = COPY $sgpr10
- %1:vgpr_32 = COPY $sgpr11
- %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
- %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
- %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
+ liveins: $sgpr10, $sgpr11
+ %0:vgpr_32 = COPY $sgpr10
+ %1:vgpr_32 = COPY $sgpr11
+ %2:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, killed %1:vgpr_32, %subreg.sub1
+ %3:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub0:vreg_64, implicit $exec
+ %4:sreg_32_xm0 = V_READFIRSTLANE_B32 %2.sub1:vreg_64, implicit $exec
...
# GCN-LABEL: name: fold-copy-readfirstlane-regsequence1{{$}}
@@ -370,20 +369,17 @@ body: |
# GCN-NEXT: %1:sreg_32_xm0 = COPY $sgpr11
# GCN-NEXT: %2:vgpr_32 = COPY %0
# GCN-NEXT: %3:vgpr_32 = COPY %1
-# GCN-NEXT: %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, killed %3, %subreg.sub1
-# GCN-NEXT: %5:sreg_32_xm0 = V_READFIRSTLANE_B32 %4.sub0, implicit $exec
-# GCN-NEXT: %6:sreg_32_xm0 = V_READFIRSTLANE_B32 %4.sub1, implicit $exec
---
name: fold-copy-readfirstlane-regsequence1
tracksRegLiveness: true
body: |
bb.0:
- liveins: $sgpr10, $sgpr11
- %0:sreg_32_xm0 = COPY $sgpr10
- %1:sreg_32_xm0 = COPY $sgpr11
- %2:vgpr_32 = COPY %0
- %3:vgpr_32 = COPY %1
- %4:vreg_64 = REG_SEQUENCE %2:vgpr_32, %subreg.sub0, killed %3:vgpr_32, %subreg.sub1
- %5:sreg_32_xm0 = V_READFIRSTLANE_B32 %4.sub0:vreg_64, implicit $exec
- %6:sreg_32_xm0 = V_READFIRSTLANE_B32 %4.sub1:vreg_64, implicit $exec
+ liveins: $sgpr10, $sgpr11
+ %0:sreg_32_xm0 = COPY $sgpr10
+ %1:sreg_32_xm0 = COPY $sgpr11
+ %2:vgpr_32 = COPY %0
+ %3:vgpr_32 = COPY %1
+ %4:vreg_64 = REG_SEQUENCE %2:vgpr_32, %subreg.sub0, killed %3:vgpr_32, %subreg.sub1
+ %5:sreg_32_xm0 = V_READFIRSTLANE_B32 %4.sub0:vreg_64, implicit $exec
+ %6:sreg_32_xm0 = V_READFIRSTLANE_B32 %4.sub1:vreg_64, implicit $exec
...
diff --git a/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir b/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir
index dc03eb74cbf11..1787a49143bfd 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir
@@ -7,7 +7,6 @@ body: |
bb.0:
; CHECK-LABEL: name: test_tryFoldZeroHighBits_skips_nonreg
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
index dbe34d19cf3eb..96072e2a5c242 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
@@ -64,7 +64,7 @@ define i128 @fptosi_f64_to_i128(double %x) {
; SDAG-NEXT: v_add3_u32 v4, v7, v6, v9
; SDAG-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
; SDAG-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
-; SDAG-NEXT: ; implicit-def: $vgpr6_vgpr7
+; SDAG-NEXT: ; implicit-def: $vgpr6
; SDAG-NEXT: ; implicit-def: $vgpr4_vgpr5
; SDAG-NEXT: ; implicit-def: $vgpr9
; SDAG-NEXT: .LBB0_3: ; %Flow
@@ -271,7 +271,7 @@ define i128 @fptoui_f64_to_i128(double %x) {
; SDAG-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc
-; SDAG-NEXT: ; implicit-def: $vgpr6_vgpr7
+; SDAG-NEXT: ; implicit-def: $vgpr6
; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1
; SDAG-NEXT: .LBB1_3: ; %Flow
; SDAG-NEXT: s_andn2_saveexec_b64 s[4:5], s[8:9]
@@ -356,74 +356,74 @@ define i128 @fptosi_f32_to_i128(float %x) {
; SDAG: ; %bb.0: ; %fp-to-i-entry
; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-NEXT: v_mov_b32_e32 v4, v0
-; SDAG-NEXT: v_bfe_u32 v9, v4, 23, 8
+; SDAG-NEXT: v_bfe_u32 v8, v4, 23, 8
; SDAG-NEXT: s_movk_i32 s4, 0x7e
; SDAG-NEXT: v_mov_b32_e32 v0, 0
; SDAG-NEXT: v_mov_b32_e32 v2, 0
; SDAG-NEXT: v_mov_b32_e32 v1, 0
; SDAG-NEXT: v_mov_b32_e32 v3, 0
-; SDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v9
+; SDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v8
; SDAG-NEXT: s_and_saveexec_b64 s[6:7], vcc
; SDAG-NEXT: s_cbranch_execz .LBB2_6
; SDAG-NEXT: ; %bb.1: ; %fp-to-i-if-check.exp.size
; SDAG-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; SDAG-NEXT: v_and_b32_e32 v0, 0x7fffff, v4
; SDAG-NEXT: s_movk_i32 s4, 0x95
-; SDAG-NEXT: v_ashrrev_i32_e32 v7, 31, v5
-; SDAG-NEXT: v_or_b32_e32 v8, 1, v5
+; SDAG-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; SDAG-NEXT: v_or_b32_e32 v7, 1, v5
; SDAG-NEXT: v_or_b32_e32 v1, 0x800000, v0
-; SDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v9
+; SDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v8
; SDAG-NEXT: ; implicit-def: $vgpr2_vgpr3
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; SDAG-NEXT: s_cbranch_execz .LBB2_3
; SDAG-NEXT: ; %bb.2: ; %fp-to-i-if-exp.large
+; SDAG-NEXT: v_add_u32_e32 v0, 0xffffff6a, v8
; SDAG-NEXT: v_mov_b32_e32 v2, 0
-; SDAG-NEXT: v_sub_u32_e32 v3, 0xd6, v9
-; SDAG-NEXT: v_add_u32_e32 v6, 0xffffff2a, v9
-; SDAG-NEXT: v_add_u32_e32 v0, 0xffffff6a, v9
+; SDAG-NEXT: v_sub_u32_e32 v3, 0xd6, v8
+; SDAG-NEXT: v_add_u32_e32 v8, 0xffffff2a, v8
; SDAG-NEXT: v_lshrrev_b64 v[3:4], v3, v[1:2]
-; SDAG-NEXT: v_lshlrev_b64 v[9:10], v6, v[1:2]
+; SDAG-NEXT: v_lshlrev_b64 v[8:9], v8, v[1:2]
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v0
-; SDAG-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
+; SDAG-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc
; SDAG-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
-; SDAG-NEXT: v_cndmask_b32_e64 v6, 0, v4, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v9, v9, v3, vcc
+; SDAG-NEXT: v_cndmask_b32_e64 v9, 0, v4, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e32 v8, v8, v3, vcc
; SDAG-NEXT: v_lshlrev_b64 v[3:4], v0, v[1:2]
-; SDAG-NEXT: v_cndmask_b32_e64 v9, 0, v9, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v11, 0, v3, vcc
-; SDAG-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v11, v8, 0
+; SDAG-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v3, vcc
+; SDAG-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v10, v7, 0
; SDAG-NEXT: v_cndmask_b32_e32 v13, 0, v4, vcc
+; SDAG-NEXT: v_mul_lo_u32 v11, v6, v8
+; SDAG-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v13, v7, v[1:2]
; SDAG-NEXT: v_mul_lo_u32 v12, v7, v9
-; SDAG-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v13, v8, v[1:2]
-; SDAG-NEXT: v_mul_lo_u32 v6, v8, v6
-; SDAG-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v8, v9, 0
+; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v7, v8, 0
; SDAG-NEXT: v_mov_b32_e32 v1, v3
-; SDAG-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v11, v7, v[1:2]
-; SDAG-NEXT: v_add3_u32 v10, v10, v6, v12
-; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v5, v11, v[9:10]
+; SDAG-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v10, v6, v[1:2]
+; SDAG-NEXT: v_add3_u32 v9, v9, v12, v11
+; SDAG-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v5, v10, v[8:9]
; SDAG-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
; SDAG-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc
-; SDAG-NEXT: v_mul_lo_u32 v6, v5, v13
-; SDAG-NEXT: v_mul_lo_u32 v5, v5, v11
-; SDAG-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v13, v7, v[2:3]
-; SDAG-NEXT: ; implicit-def: $vgpr7
-; SDAG-NEXT: v_add3_u32 v4, v5, v9, v6
-; SDAG-NEXT: v_add_co_u32_e32 v2, vcc, v2, v8
+; SDAG-NEXT: v_mul_lo_u32 v9, v5, v13
+; SDAG-NEXT: v_mul_lo_u32 v5, v5, v10
+; SDAG-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v13, v6, v[2:3]
+; SDAG-NEXT: ; implicit-def: $vgpr6
+; SDAG-NEXT: v_add3_u32 v4, v5, v8, v9
+; SDAG-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7
; SDAG-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
-; SDAG-NEXT: ; implicit-def: $vgpr9
; SDAG-NEXT: ; implicit-def: $vgpr8
-; SDAG-NEXT: ; implicit-def: $vgpr5_vgpr6
+; SDAG-NEXT: ; implicit-def: $vgpr7
+; SDAG-NEXT: ; implicit-def: $vgpr5
; SDAG-NEXT: .LBB2_3: ; %Flow
; SDAG-NEXT: s_andn2_saveexec_b64 s[4:5], s[8:9]
; SDAG-NEXT: s_cbranch_execz .LBB2_5
; SDAG-NEXT: ; %bb.4: ; %fp-to-i-if-exp.small
-; SDAG-NEXT: v_sub_u32_e32 v0, 0x96, v9
+; SDAG-NEXT: v_sub_u32_e32 v0, 0x96, v8
; SDAG-NEXT: v_lshrrev_b32_e32 v3, v0, v1
-; SDAG-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v3, v8, 0
+; SDAG-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v3, v7, 0
; SDAG-NEXT: v_mov_b32_e32 v2, 0
; SDAG-NEXT: v_mov_b32_e32 v8, v2
-; SDAG-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v3, v7, v[1:2]
+; SDAG-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v3, v6, v[1:2]
; SDAG-NEXT: v_mad_i64_i32 v[2:3], s[8:9], v5, v3, v[7:8]
; SDAG-NEXT: v_mov_b32_e32 v1, v6
; SDAG-NEXT: .LBB2_5: ; %Flow1
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index bf153a88982e0..03aeda32b31cd 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -501,62 +501,61 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[4:5] offset:8
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v4, |v1.l|
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] offset:8
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.h|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v2
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v2, v1
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB0_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v2
+; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v2, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.l, v3.l, vcc_lo
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB0_3
; GFX11-TRUE16-NEXT: s_branch .LBB0_8
; GFX11-TRUE16-NEXT: .LBB0_2:
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: .LBB0_3: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v4
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v3, 11
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v2
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v2
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v2, 11
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v1
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v5, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
@@ -565,49 +564,48 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: .LBB0_5: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v4, v3, v7
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX11-TRUE16-NEXT: v_fma_f32 v3, -v3, v2, v6
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_5
; GFX11-TRUE16-NEXT: ; %bb.6: ; %Flow
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v6
; GFX11-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v5, v3, v4
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT: v_fma_f32 v3, -v4, v2, v3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
-; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fff, v2, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fff, v1, v0
; GFX11-TRUE16-NEXT: .LBB0_8: ; %Flow19
-; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v1.l|
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v3.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: frem_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
index 6f9531ecfa1b8..f94f335a16679 100644
--- a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
+++ b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
@@ -50,18 +50,18 @@ define amdgpu_kernel void @udiv32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s6, s[4:5], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX10-NEXT: s_mov_b32 s3, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX10-NEXT: s_sub_i32 s3, 0, s6
+; GFX10-NEXT: s_sub_i32 s2, 0, s6
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s2, v0
+; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: s_mul_i32 s3, s3, s2
-; GFX10-NEXT: s_mul_hi_u32 s4, s2, s3
-; GFX10-NEXT: s_mov_b32 s3, 0
-; GFX10-NEXT: s_add_i32 s4, s2, s4
+; GFX10-NEXT: s_mul_i32 s2, s2, s4
+; GFX10-NEXT: s_mul_hi_u32 s2, s4, s2
+; GFX10-NEXT: s_add_i32 s4, s4, s2
; GFX10-NEXT: s_mov_b32 s2, s3
; GFX10-NEXT: .LBB0_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -93,21 +93,22 @@ define amdgpu_kernel void @udiv32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_mov_b32 s3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX11-NEXT: s_sub_i32 s3, 0, s6
+; GFX11-NEXT: s_sub_i32 s2, 0, s6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-NEXT: v_readfirstlane_b32 s4, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_mul_i32 s3, s3, s2
-; GFX11-NEXT: s_mul_hi_u32 s4, s2, s3
-; GFX11-NEXT: s_mov_b32 s3, 0
-; GFX11-NEXT: s_add_i32 s4, s2, s4
+; GFX11-NEXT: s_mul_i32 s2, s2, s4
+; GFX11-NEXT: s_mul_hi_u32 s2, s4, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s4, s4, s2
; GFX11-NEXT: s_mov_b32 s2, s3
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB0_1: ; %bb3
@@ -198,18 +199,18 @@ define amdgpu_kernel void @urem32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s6, s[4:5], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX10-NEXT: s_mov_b32 s3, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX10-NEXT: s_sub_i32 s3, 0, s6
+; GFX10-NEXT: s_sub_i32 s2, 0, s6
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s2, v0
+; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: s_mul_i32 s3, s3, s2
-; GFX10-NEXT: s_mul_hi_u32 s4, s2, s3
-; GFX10-NEXT: s_mov_b32 s3, 0
-; GFX10-NEXT: s_add_i32 s4, s2, s4
+; GFX10-NEXT: s_mul_i32 s2, s2, s4
+; GFX10-NEXT: s_mul_hi_u32 s2, s4, s2
+; GFX10-NEXT: s_add_i32 s4, s4, s2
; GFX10-NEXT: s_mov_b32 s2, s3
; GFX10-NEXT: .LBB1_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -239,21 +240,22 @@ define amdgpu_kernel void @urem32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_mov_b32 s3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX11-NEXT: s_sub_i32 s3, 0, s6
+; GFX11-NEXT: s_sub_i32 s2, 0, s6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-NEXT: v_readfirstlane_b32 s4, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_mul_i32 s3, s3, s2
-; GFX11-NEXT: s_mul_hi_u32 s4, s2, s3
-; GFX11-NEXT: s_mov_b32 s3, 0
-; GFX11-NEXT: s_add_i32 s4, s2, s4
+; GFX11-NEXT: s_mul_i32 s2, s2, s4
+; GFX11-NEXT: s_mul_hi_u32 s2, s4, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s4, s4, s2
; GFX11-NEXT: s_mov_b32 s2, s3
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB1_1: ; %bb3
diff --git a/llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll b/llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll
index 3206e9593320e..3c8c165a13cb1 100644
--- a/llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll
+++ b/llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll
@@ -1,60 +1,82 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GCN %s
declare <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
-; GCN-LABEL: {{^}}water_loop_rsrc:
-
-; GCN: [[RSRC_LOOP:.L[a-zA-Z0-9_]+]]: ; =>This Inner Loop Header: Depth=1
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]]
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]]
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]]
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]]
-; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s[[[SREG0]]:[[SREG1]]], v[[[VREG0]]:[[VREG1]]]
-; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s[[[SREG2]]:[[SREG3]]], v[[[VREG2]]:[[VREG3]]]
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]]
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]]
-; GCN-NEXT: s_and_b64 [[AND0:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
-; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP2:vcc]], s[[[SREG4]]:[[SREG5]]], v[[[VREG4]]:[[VREG5]]]
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]]
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]]
-; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP3:s\[[0-9]+:[0-9]+\]]], s[[[SREG6]]:[[SREG7]]], v[[[VREG6]]:[[VREG7]]]
-; GCN-NEXT: s_and_b64 [[AND1:s\[[0-9]+:[0-9]+\]]], [[AND0]], [[CMP2]]
-; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[AND1]], [[CMP3]]
-; GCN-NEXT: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, s[[[SREG0]]:[[SREG7]]], {{s\[[0-9]+:[0-9]+\]}} dmask:0x1
-; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GCN-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GCN-NEXT: s_xor_b64 exec, exec, [[SAVE]]
-; GCN-NEXT: s_cbranch_execnz [[RSRC_LOOP]]
define amdgpu_ps <4 x float> @water_loop_rsrc(<8 x i32> %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
+; GCN-LABEL: water_loop_rsrc:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[6:7], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: s_mov_b64 s[16:17], exec
+; GCN-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; GCN-NEXT: v_readfirstlane_b32 s8, v0
+; GCN-NEXT: v_readfirstlane_b32 s9, v1
+; GCN-NEXT: v_readfirstlane_b32 s10, v2
+; GCN-NEXT: v_readfirstlane_b32 s11, v3
+; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1]
+; GCN-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[2:3]
+; GCN-NEXT: v_readfirstlane_b32 s12, v4
+; GCN-NEXT: v_readfirstlane_b32 s13, v5
+; GCN-NEXT: s_and_b64 s[18:19], vcc, s[4:5]
+; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[12:13], v[4:5]
+; GCN-NEXT: v_readfirstlane_b32 s14, v6
+; GCN-NEXT: v_readfirstlane_b32 s15, v7
+; GCN-NEXT: v_cmp_eq_u64_e64 s[4:5], s[14:15], v[6:7]
+; GCN-NEXT: s_and_b64 s[18:19], s[18:19], vcc
+; GCN-NEXT: s_and_b64 s[4:5], s[18:19], s[4:5]
+; GCN-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: image_gather4 v[10:13], v[8:9], s[8:15], s[0:3] dmask:0x1
+; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GCN-NEXT: ; implicit-def: $vgpr8_vgpr9
+; GCN-NEXT: s_xor_b64 exec, exec, s[4:5]
+; GCN-NEXT: s_cbranch_execnz .LBB0_1
+; GCN-NEXT: ; %bb.2:
+; GCN-NEXT: s_mov_b64 exec, s[16:17]
+; GCN-NEXT: s_and_b64 exec, exec, s[6:7]
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, v10
+; GCN-NEXT: v_mov_b32_e32 v1, v11
+; GCN-NEXT: v_mov_b32_e32 v2, v12
+; GCN-NEXT: v_mov_b32_e32 v3, v13
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-
-; GCN-LABEL: {{^}}water_loop_samp:
-
-; GCN: [[SAMP_LOOP:.L[a-zA-Z0-9_]+]]: ; =>This Inner Loop Header: Depth=1
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]]
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]]
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]]
-; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]]
-
-; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s[[[SREG0]]:[[SREG1]]], v[[[VREG0]]:[[VREG1]]]
-; GCN-NEXT: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s[[[SREG2]]:[[SREG3]]], v[[[VREG2]]:[[VREG3]]]
-; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
-; GCN-NEXT: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
-; GCN-NEXT: s_nop 0
-
-; GCN-NEXT: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, s[[[SREG0]]:[[SREG3]]] dmask:0x1
-; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GCN-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GCN-NEXT: s_xor_b64 exec, exec, [[SAVE]]
-; GCN-NEXT: s_cbranch_execnz [[SAMP_LOOP]]
define amdgpu_ps <4 x float> @water_loop_samp(<8 x i32> inreg %rsrc, <4 x i32> %samp, float %s, float %t) {
+; GCN-LABEL: water_loop_samp:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[10:11], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: s_mov_b64 s[16:17], exec
+; GCN-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GCN-NEXT: v_readfirstlane_b32 s12, v0
+; GCN-NEXT: v_readfirstlane_b32 s13, v1
+; GCN-NEXT: v_readfirstlane_b32 s14, v2
+; GCN-NEXT: v_readfirstlane_b32 s15, v3
+; GCN-NEXT: v_cmp_eq_u64_e32 vcc, s[12:13], v[0:1]
+; GCN-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], v[2:3]
+; GCN-NEXT: s_and_b64 s[8:9], vcc, s[8:9]
+; GCN-NEXT: s_and_saveexec_b64 s[8:9], s[8:9]
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: image_gather4 v[6:9], v[4:5], s[0:7], s[12:15] dmask:0x1
+; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GCN-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GCN-NEXT: s_xor_b64 exec, exec, s[8:9]
+; GCN-NEXT: s_cbranch_execnz .LBB1_1
+; GCN-NEXT: ; %bb.2:
+; GCN-NEXT: s_mov_b64 exec, s[16:17]
+; GCN-NEXT: s_and_b64 exec, exec, s[10:11]
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, v6
+; GCN-NEXT: v_mov_b32_e32 v1, v7
+; GCN-NEXT: v_mov_b32_e32 v2, v8
+; GCN-NEXT: v_mov_b32_e32 v3, v9
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
diff --git a/llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll b/llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
index 9644c941cd06c..bb6b59e887881 100644
--- a/llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
+++ b/llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
@@ -12,9 +12,9 @@ define void @issue92561(ptr addrspace(1) %arg) {
; SDAG: ; %bb.0: ; %bb
; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-NEXT: s_clause 0x1
-; SDAG-NEXT: global_load_b128 v[4:7], v[0:1], off offset:16
-; SDAG-NEXT: global_load_b128 v[0:3], v[0:1], off
-; SDAG-NEXT: v_mov_b32_e32 v8, 0
+; SDAG-NEXT: global_load_b128 v[2:5], v[0:1], off offset:16
+; SDAG-NEXT: global_load_b128 v[6:9], v[0:1], off
+; SDAG-NEXT: v_mov_b32_e32 v1, 0
; SDAG-NEXT: s_mov_b32 s12, 0
; SDAG-NEXT: s_mov_b32 s3, exec_lo
; SDAG-NEXT: s_mov_b32 s13, s12
@@ -22,31 +22,32 @@ define void @issue92561(ptr addrspace(1) %arg) {
; SDAG-NEXT: s_mov_b32 s15, s12
; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
-; SDAG-NEXT: v_readfirstlane_b32 s4, v0
-; SDAG-NEXT: v_readfirstlane_b32 s5, v1
-; SDAG-NEXT: v_readfirstlane_b32 s6, v2
-; SDAG-NEXT: v_readfirstlane_b32 s7, v3
-; SDAG-NEXT: v_readfirstlane_b32 s8, v4
-; SDAG-NEXT: v_readfirstlane_b32 s9, v5
-; SDAG-NEXT: v_readfirstlane_b32 s10, v6
-; SDAG-NEXT: v_readfirstlane_b32 s11, v7
-; SDAG-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
-; SDAG-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
-; SDAG-NEXT: v_cmp_eq_u64_e64 s1, s[8:9], v[4:5]
+; SDAG-NEXT: v_readfirstlane_b32 s4, v6
+; SDAG-NEXT: v_readfirstlane_b32 s5, v7
+; SDAG-NEXT: v_readfirstlane_b32 s6, v8
+; SDAG-NEXT: v_readfirstlane_b32 s7, v9
+; SDAG-NEXT: v_readfirstlane_b32 s8, v2
+; SDAG-NEXT: v_readfirstlane_b32 s9, v3
+; SDAG-NEXT: v_readfirstlane_b32 s10, v4
+; SDAG-NEXT: v_readfirstlane_b32 s11, v5
+; SDAG-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[6:7]
+; SDAG-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[8:9]
+; SDAG-NEXT: v_cmp_eq_u64_e64 s1, s[8:9], v[2:3]
; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; SDAG-NEXT: v_cmp_eq_u64_e64 s2, s[10:11], v[6:7]
+; SDAG-NEXT: v_cmp_eq_u64_e64 s2, s[10:11], v[4:5]
; SDAG-NEXT: s_and_b32 s0, vcc_lo, s0
; SDAG-NEXT: s_and_b32 s0, s0, s1
; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; SDAG-NEXT: s_and_b32 s0, s0, s2
; SDAG-NEXT: s_and_saveexec_b32 s0, s0
-; SDAG-NEXT: image_sample_c_lz v9, [v8, v8, v8, v8], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
-; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; SDAG-NEXT: image_sample_c_lz v0, [v1, v1, v1, v1], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
+; SDAG-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9
+; SDAG-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
; SDAG-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; SDAG-NEXT: s_cbranch_execnz .LBB0_1
; SDAG-NEXT: ; %bb.2:
; SDAG-NEXT: s_mov_b32 exec_lo, s3
-; SDAG-NEXT: v_dual_mov_b32 v0, 0x7fc00000 :: v_dual_mov_b32 v1, 1.0
+; SDAG-NEXT: v_dual_mov_b32 v2, 0x7fc00000 :: v_dual_mov_b32 v3, 1.0
; SDAG-NEXT: s_mov_b32 s0, s12
; SDAG-NEXT: s_mov_b32 s1, s12
; SDAG-NEXT: s_mov_b32 s2, s12
@@ -56,18 +57,19 @@ define void @issue92561(ptr addrspace(1) %arg) {
; SDAG-NEXT: s_mov_b32 s6, s12
; SDAG-NEXT: s_mov_b32 s7, s12
; SDAG-NEXT: s_clause 0x2
-; SDAG-NEXT: image_sample_c_lz v0, [v8, v8, v0, v8], s[0:7], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
-; SDAG-NEXT: image_sample_c_lz v2, [v8, v8, v8, v8], s[0:7], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
-; SDAG-NEXT: image_sample_c_lz v1, [v8, v1, v8, v8], s[0:7], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
+; SDAG-NEXT: image_sample_c_lz v2, [v1, v1, v2, v1], s[0:7], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
+; SDAG-NEXT: image_sample_c_lz v4, [v1, v1, v1, v1], s[0:7], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
+; SDAG-NEXT: image_sample_c_lz v3, [v1, v3, v1, v1], s[0:7], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
; SDAG-NEXT: s_waitcnt vmcnt(2)
-; SDAG-NEXT: v_dual_add_f32 v0, v9, v0 :: v_dual_mov_b32 v9, v8
+; SDAG-NEXT: v_add_f32_e32 v0, v0, v2
+; SDAG-NEXT: v_mov_b32_e32 v2, v1
; SDAG-NEXT: s_waitcnt vmcnt(0)
-; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-NEXT: v_add_f32_e32 v0, v1, v0
-; SDAG-NEXT: v_add_f32_e32 v0, v2, v0
+; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-NEXT: v_dual_add_f32 v0, v3, v0 :: v_dual_mov_b32 v3, 0
+; SDAG-NEXT: v_add_f32_e32 v0, v4, v0
; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-NEXT: v_dual_mul_f32 v7, 0x3e800000, v0 :: v_dual_mov_b32 v0, 0
-; SDAG-NEXT: image_store v[7:9], [v0, v0], s[0:7] dim:SQ_RSRC_IMG_2D unorm
+; SDAG-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
+; SDAG-NEXT: image_store v[0:2], [v3, v3], s[0:7] dim:SQ_RSRC_IMG_2D unorm
; SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-LABEL: issue92561:
diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
index c08b0304239fe..db37e291b0930 100644
--- a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
@@ -557,7 +557,7 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SDAG-NEXT: ; implicit-def: $vgpr2
; SDAG-NEXT: ; implicit-def: $vgpr6_vgpr7
-; SDAG-NEXT: ; implicit-def: $vgpr4_vgpr5
+; SDAG-NEXT: ; implicit-def: $vgpr5
; SDAG-NEXT: ; %bb.3: ; %Flow3
; SDAG-NEXT: s_or_saveexec_b64 s[8:9], s[4:5]
; SDAG-NEXT: v_sub_u32_e32 v8, 0x7f, v9
@@ -582,27 +582,26 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_or_b32_e32 v10, v0, v10
; SDAG-NEXT: v_lshrrev_b64 v[0:1], v13, v[6:7]
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v12
-; SDAG-NEXT: v_add_u32_e32 v16, 55, v9
; SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v12
; SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; SDAG-NEXT: v_lshrrev_b64 v[10:11], v12, v[6:7]
-; SDAG-NEXT: v_lshrrev_b64 v[12:13], v13, v[4:5]
-; SDAG-NEXT: v_lshlrev_b64 v[14:15], v16, v[6:7]
+; SDAG-NEXT: v_add_u32_e32 v15, 55, v9
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v12
+; SDAG-NEXT: v_lshrrev_b64 v[11:12], v13, v[4:5]
+; SDAG-NEXT: v_lshlrev_b64 v[13:14], v15, v[6:7]
; SDAG-NEXT: v_add_u32_e32 v9, -9, v9
-; SDAG-NEXT: v_or_b32_e32 v15, v15, v13
; SDAG-NEXT: v_or_b32_e32 v14, v14, v12
-; SDAG-NEXT: v_lshlrev_b64 v[12:13], v9, v[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
+; SDAG-NEXT: v_or_b32_e32 v13, v13, v11
+; SDAG-NEXT: v_lshlrev_b64 v[11:12], v9, v[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
+; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v9, v13, v15, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; SDAG-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
+; SDAG-NEXT: v_lshlrev_b64 v[4:5], v15, v[4:5]
+; SDAG-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v6, v9, v6, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
@@ -620,10 +619,10 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: .LBB2_8: ; %Flow2
; SDAG-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]
; SDAG-NEXT: ; %bb.9: ; %itofp-sw-bb
-; SDAG-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
-; SDAG-NEXT: v_lshrrev_b32_e32 v0, 31, v5
+; SDAG-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
+; SDAG-NEXT: v_lshrrev_b32_e32 v1, 31, v5
; SDAG-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
-; SDAG-NEXT: v_or_b32_e32 v6, v6, v0
+; SDAG-NEXT: v_or_b32_e32 v6, v0, v1
; SDAG-NEXT: ; %bb.10: ; %itofp-sw-epilog
; SDAG-NEXT: s_or_b64 exec, exec, s[4:5]
; SDAG-NEXT: v_lshrrev_b32_e32 v0, 2, v4
@@ -870,27 +869,26 @@ define double @uitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_or_b32_e32 v9, v4, v9
; SDAG-NEXT: v_lshrrev_b64 v[4:5], v12, v[2:3]
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v11
-; SDAG-NEXT: v_add_u32_e32 v15, 55, v8
; SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11
; SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
; SDAG-NEXT: v_lshrrev_b64 v[9:10], v11, v[2:3]
-; SDAG-NEXT: v_lshrrev_b64 v[11:12], v12, v[0:1]
-; SDAG-NEXT: v_lshlrev_b64 v[13:14], v15, v[2:3]
+; SDAG-NEXT: v_add_u32_e32 v14, 55, v8
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11
+; SDAG-NEXT: v_lshrrev_b64 v[10:11], v12, v[0:1]
+; SDAG-NEXT: v_lshlrev_b64 v[12:13], v14, v[2:3]
; SDAG-NEXT: v_add_u32_e32 v8, -9, v8
-; SDAG-NEXT: v_or_b32_e32 v14, v14, v12
; SDAG-NEXT: v_or_b32_e32 v13, v13, v11
-; SDAG-NEXT: v_lshlrev_b64 v[11:12], v8, v[0:1]
-; SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; SDAG-NEXT: v_or_b32_e32 v12, v12, v10
+; SDAG-NEXT: v_lshlrev_b64 v[10:11], v8, v[0:1]
; SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
+; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
; SDAG-NEXT: v_cndmask_b32_e64 v5, v5, v1, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v4, v4, v0, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v8, v12, v14, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
-; SDAG-NEXT: v_lshlrev_b64 v[0:1], v15, v[0:1]
-; SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
+; SDAG-NEXT: v_lshlrev_b64 v[0:1], v14, v[0:1]
+; SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
+; SDAG-NEXT: v_cndmask_b32_e32 v8, v10, v12, vcc
; SDAG-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index ff2469ec3872a..6a9bcccb0b590 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -5449,10 +5449,10 @@ define amdgpu_kernel void @constant_sextload_v2i1_to_v2i64(ptr addrspace(1) %out
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: global_load_u8 v0, v4, s[2:3] nv
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX1250-NEXT: v_lshrrev_b32_e32 v1, 1, v0
; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX1250-NEXT: v_bfe_i32 v2, v1, 0, 1
; GFX1250-NEXT: v_dual_ashrrev_i32 v1, 31, v0 :: v_dual_ashrrev_i32 v3, 31, v2
; GFX1250-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1250-NEXT: s_endpgm
@@ -5696,23 +5696,21 @@ define amdgpu_kernel void @constant_sextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v5, 0
+; GFX1250-NEXT: v_mov_b32_e32 v6, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u8 v0, v5, s[2:3] nv
+; GFX1250-NEXT: global_load_u8 v0, v6, s[2:3] nv
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_dual_lshrrev_b32 v2, 2, v0 :: v_dual_lshrrev_b32 v4, 1, v0
+; GFX1250-NEXT: v_dual_lshrrev_b32 v1, 2, v0 :: v_dual_lshrrev_b32 v2, 1, v0
; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_bfe_i32 v6, v2, 0, 1
+; GFX1250-NEXT: v_bfe_i32 v4, v1, 0, 1
; GFX1250-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_bfe_i32 v2, v4, 0, 1
-; GFX1250-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX1250-NEXT: v_dual_ashrrev_i32 v5, 31, v4 :: v_dual_ashrrev_i32 v3, 31, v2
; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b64 v5, v[6:7], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v5, v[0:3], s[0:1]
+; GFX1250-NEXT: global_store_b64 v6, v[4:5], s[0:1] offset:16
+; GFX1250-NEXT: global_store_b128 v6, v[0:3], s[0:1]
; GFX1250-NEXT: s_endpgm
%load = load <3 x i1>, ptr addrspace(4) %in
%ext = sext <3 x i1> %load to <3 x i64>
@@ -5985,24 +5983,24 @@ define amdgpu_kernel void @constant_sextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v9, 0
+; GFX1250-NEXT: v_mov_b32_e32 v8, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u8 v0, v9, s[2:3] nv
+; GFX1250-NEXT: global_load_u8 v0, v8, s[2:3] nv
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_dual_lshrrev_b32 v2, 3, v0 :: v_dual_lshrrev_b32 v4, 2, v0
-; GFX1250-NEXT: v_lshrrev_b32_e32 v8, 1, v0
+; GFX1250-NEXT: v_dual_lshrrev_b32 v1, 3, v0 :: v_dual_lshrrev_b32 v2, 2, v0
+; GFX1250-NEXT: v_lshrrev_b32_e32 v3, 1, v0
; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1250-NEXT: v_bfe_i32 v6, v2, 0, 1
-; GFX1250-NEXT: v_bfe_i32 v4, v4, 0, 1
+; GFX1250-NEXT: v_bfe_i32 v6, v1, 0, 1
+; GFX1250-NEXT: v_bfe_i32 v4, v2, 0, 1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_bfe_i32 v2, v8, 0, 1
+; GFX1250-NEXT: v_bfe_i32 v2, v3, 0, 1
; GFX1250-NEXT: v_dual_ashrrev_i32 v1, 31, v0 :: v_dual_ashrrev_i32 v7, 31, v6
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-NEXT: v_dual_ashrrev_i32 v5, 31, v4 :: v_dual_ashrrev_i32 v3, 31, v2
; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b128 v9, v[4:7], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v9, v[0:3], s[0:1]
+; GFX1250-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
+; GFX1250-NEXT: global_store_b128 v8, v[0:3], s[0:1]
; GFX1250-NEXT: s_endpgm
%load = load <4 x i1>, ptr addrspace(4) %in
%ext = sext <4 x i1> %load to <4 x i64>
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
index 388006281abdc..d356bfe2e313d 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
@@ -6030,17 +6030,17 @@ define amdgpu_kernel void @global_sextload_v4i16_to_v4i64(ptr addrspace(1) %out,
;
; GCN-NOHSA-VI-LABEL: global_sextload_v4i16_to_v4i64:
; GCN-NOHSA-VI: ; %bb.0:
-; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s3
+; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx2 v[1:2], off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
@@ -6052,8 +6052,8 @@ define amdgpu_kernel void @global_sextload_v4i16_to_v4i64(ptr addrspace(1) %out,
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: global_sextload_v4i16_to_v4i64:
@@ -7125,60 +7125,60 @@ define amdgpu_kernel void @global_sextload_v16i16_to_v16i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7
-; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[1:4], off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:16
+; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
+; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v8, v0, 0, 16
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v0, v1, 0, 16
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v13, v3, 0, 16
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v12, 16, v3
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v3, v1, 0, 16
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v1, v6, 0, 16
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v9, v2, 0, 16
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v12, v2, 0, 16
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v11, 16, v2
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v17, v4, 0, 16
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v14, 16, v4
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[1:4], off, s[0:3], 0 offset:80
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v25, v5, 0, 16
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 16, v5
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v19, v2, 0, 16
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v17, v5, 0, 16
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v2, v1, 0, 16
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v6, v1, 0, 16
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v8
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v27, v1, 0, 16
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v4, v7, 0, 16
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v2, v10, 0, 16
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v11, v11, 0, 16
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v15, v12, 0, 16
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v19, v14, 0, 16
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v23, v3, 0, 16
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v21, v8, 0, 16
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v26, 31, v25
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v28, 31, v27
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v10, 31, v9
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v18, 31, v17
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v22, 31, v21
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v16, 31, v15
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v20, 31, v19
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v26, v1, 0, 16
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v16, v3, 0, 16
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:80
+; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v5, 16, v6
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v20, v6, 0, 16
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v4, v4, 0, 16
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v6, v1, 0, 16
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v10, v9, 0, 16
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v14, v11, 0, 16
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v18, v3, 0, 16
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v22, v5, 0, 16
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v24, v7, 0, 16
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v24, 31, v23
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[25:28], off, s[0:3], 0 offset:64
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[21:24], off, s[0:3], 0 offset:112
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:96
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:48
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[13:16], off, s[0:3], 0 offset:32
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[9:12], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v17, 31, v16
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v21, 31, v20
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v25, 31, v24
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v19, 31, v18
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v23, 31, v22
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v27, 31, v26
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:112
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:96
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:48
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: global_sextload_v16i16_to_v16i64:
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
index b75c8c7e4177b..26811b93fba60 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
@@ -5929,17 +5929,17 @@ define amdgpu_kernel void @global_sextload_v4i8_to_v4i64(ptr addrspace(1) %out,
;
; GCN-NOHSA-VI-LABEL: global_sextload_v4i8_to_v4i64:
; GCN-NOHSA-VI: ; %bb.0:
-; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s3
+; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
; GCN-NOHSA-VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v4, 24, v0
@@ -5952,8 +5952,8 @@ define amdgpu_kernel void @global_sextload_v4i8_to_v4i64(ptr addrspace(1) %out,
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: global_sextload_v4i8_to_v4i64:
diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i16.ll b/llvm/test/CodeGen/AMDGPU/load-local-i16.ll
index 04d906ca6ad9c..a8f4cfa483498 100644
--- a/llvm/test/CodeGen/AMDGPU/load-local-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-local-i16.ll
@@ -7152,120 +7152,120 @@ define amdgpu_kernel void @local_sextload_v16i16_to_v16i64(ptr addrspace(3) %out
; VI-DS128-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-DS128-NEXT: s_mov_b32 m0, -1
; VI-DS128-NEXT: s_waitcnt lgkmcnt(0)
-; VI-DS128-NEXT: v_mov_b32_e32 v0, s1
-; VI-DS128-NEXT: ds_read_b128 v[3:6], v0
-; VI-DS128-NEXT: ds_read_b128 v[7:10], v0 offset:16
+; VI-DS128-NEXT: v_mov_b32_e32 v4, s1
+; VI-DS128-NEXT: ds_read_b128 v[0:3], v4
+; VI-DS128-NEXT: ds_read_b128 v[4:7], v4 offset:16
+; VI-DS128-NEXT: v_mov_b32_e32 v16, s0
; VI-DS128-NEXT: s_waitcnt lgkmcnt(1)
-; VI-DS128-NEXT: v_bfe_i32 v0, v3, 0, 16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; VI-DS128-NEXT: v_bfe_i32 v8, v0, 0, 16
; VI-DS128-NEXT: s_waitcnt lgkmcnt(0)
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v3, 16, v8
-; VI-DS128-NEXT: v_bfe_i32 v11, v8, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v13, v3, 0, 16
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; VI-DS128-NEXT: v_mov_b32_e32 v8, s0
-; VI-DS128-NEXT: ds_write_b128 v8, v[11:14] offset:80
-; VI-DS128-NEXT: v_bfe_i32 v11, v7, 0, 16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; VI-DS128-NEXT: v_bfe_i32 v13, v7, 0, 16
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v10
-; VI-DS128-NEXT: ds_write_b128 v8, v[11:14] offset:64
-; VI-DS128-NEXT: v_bfe_i32 v11, v10, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v13, v7, 0, 16
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; VI-DS128-NEXT: v_bfe_i32 v10, v4, 0, 16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; VI-DS128-NEXT: ds_write_b128 v8, v[11:14] offset:112
+; VI-DS128-NEXT: v_bfe_i32 v12, v5, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; VI-DS128-NEXT: v_bfe_i32 v14, v5, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v10, v0, 0, 16
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; VI-DS128-NEXT: ds_write_b128 v16, v[12:15] offset:80
; VI-DS128-NEXT: v_bfe_i32 v12, v4, 0, 16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v9
-; VI-DS128-NEXT: v_bfe_i32 v14, v9, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v16, v4, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v14, v0, 0, 16
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; VI-DS128-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v5
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v6
-; VI-DS128-NEXT: ds_write_b128 v8, v[14:17] offset:96
-; VI-DS128-NEXT: v_bfe_i32 v16, v4, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; VI-DS128-NEXT: ds_write_b128 v16, v[12:15] offset:64
+; VI-DS128-NEXT: v_bfe_i32 v12, v7, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v14, v0, 0, 16
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; VI-DS128-NEXT: ds_write_b128 v16, v[12:15] offset:112
+; VI-DS128-NEXT: v_bfe_i32 v14, v0, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v6
; VI-DS128-NEXT: v_bfe_i32 v4, v6, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v6, v7, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v14, v5, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v6, v0, 0, 16
; VI-DS128-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; VI-DS128-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; VI-DS128-NEXT: ds_write_b128 v16, v[4:7] offset:96
+; VI-DS128-NEXT: v_bfe_i32 v4, v2, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; VI-DS128-NEXT: v_bfe_i32 v6, v0, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v0, v3, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v12, v1, 0, 16
; VI-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; VI-DS128-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; VI-DS128-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; VI-DS128-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; VI-DS128-NEXT: ds_write_b128 v8, v[4:7] offset:48
-; VI-DS128-NEXT: ds_write_b128 v8, v[14:17] offset:32
-; VI-DS128-NEXT: ds_write_b128 v8, v[10:13] offset:16
-; VI-DS128-NEXT: ds_write_b128 v8, v[0:3]
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; VI-DS128-NEXT: ds_write_b128 v16, v[0:3] offset:48
+; VI-DS128-NEXT: ds_write_b128 v16, v[4:7] offset:32
+; VI-DS128-NEXT: ds_write_b128 v16, v[12:15] offset:16
+; VI-DS128-NEXT: ds_write_b128 v16, v[8:11]
; VI-DS128-NEXT: s_endpgm
;
; GFX9-DS128-LABEL: local_sextload_v16i16_to_v16i64:
; GFX9-DS128: ; %bb.0:
; GFX9-DS128-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DS128-NEXT: v_mov_b32_e32 v0, s1
-; GFX9-DS128-NEXT: ds_read_b128 v[3:6], v0
-; GFX9-DS128-NEXT: ds_read_b128 v[7:10], v0 offset:16
+; GFX9-DS128-NEXT: v_mov_b32_e32 v4, s1
+; GFX9-DS128-NEXT: ds_read_b128 v[0:3], v4
+; GFX9-DS128-NEXT: ds_read_b128 v[4:7], v4 offset:16
+; GFX9-DS128-NEXT: v_mov_b32_e32 v16, s0
; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(1)
-; GFX9-DS128-NEXT: v_bfe_i32 v0, v3, 0, 16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; GFX9-DS128-NEXT: v_bfe_i32 v8, v0, 0, 16
; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v3, 16, v8
-; GFX9-DS128-NEXT: v_bfe_i32 v11, v8, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v13, v3, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; GFX9-DS128-NEXT: v_mov_b32_e32 v8, s0
-; GFX9-DS128-NEXT: ds_write_b128 v8, v[11:14] offset:80
-; GFX9-DS128-NEXT: v_bfe_i32 v11, v7, 0, 16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-DS128-NEXT: v_bfe_i32 v13, v7, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v10
-; GFX9-DS128-NEXT: ds_write_b128 v8, v[11:14] offset:64
-; GFX9-DS128-NEXT: v_bfe_i32 v11, v10, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v13, v7, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; GFX9-DS128-NEXT: v_bfe_i32 v10, v4, 0, 16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX9-DS128-NEXT: ds_write_b128 v8, v[11:14] offset:112
+; GFX9-DS128-NEXT: v_bfe_i32 v12, v5, 0, 16
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX9-DS128-NEXT: v_bfe_i32 v14, v5, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v10, v0, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX9-DS128-NEXT: ds_write_b128 v16, v[12:15] offset:80
; GFX9-DS128-NEXT: v_bfe_i32 v12, v4, 0, 16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v9
-; GFX9-DS128-NEXT: v_bfe_i32 v14, v9, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v16, v4, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v14, v0, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v5
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v6
-; GFX9-DS128-NEXT: ds_write_b128 v8, v[14:17] offset:96
-; GFX9-DS128-NEXT: v_bfe_i32 v16, v4, 0, 16
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GFX9-DS128-NEXT: ds_write_b128 v16, v[12:15] offset:64
+; GFX9-DS128-NEXT: v_bfe_i32 v12, v7, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v14, v0, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX9-DS128-NEXT: ds_write_b128 v16, v[12:15] offset:112
+; GFX9-DS128-NEXT: v_bfe_i32 v14, v0, 0, 16
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v6
; GFX9-DS128-NEXT: v_bfe_i32 v4, v6, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v6, v7, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v14, v5, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v6, v0, 0, 16
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX9-DS128-NEXT: ds_write_b128 v16, v[4:7] offset:96
+; GFX9-DS128-NEXT: v_bfe_i32 v4, v2, 0, 16
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; GFX9-DS128-NEXT: v_bfe_i32 v6, v0, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v0, v3, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v12, v1, 0, 16
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX9-DS128-NEXT: ds_write_b128 v8, v[4:7] offset:48
-; GFX9-DS128-NEXT: ds_write_b128 v8, v[14:17] offset:32
-; GFX9-DS128-NEXT: ds_write_b128 v8, v[10:13] offset:16
-; GFX9-DS128-NEXT: ds_write_b128 v8, v[0:3]
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX9-DS128-NEXT: ds_write_b128 v16, v[0:3] offset:48
+; GFX9-DS128-NEXT: ds_write_b128 v16, v[4:7] offset:32
+; GFX9-DS128-NEXT: ds_write_b128 v16, v[12:15] offset:16
+; GFX9-DS128-NEXT: ds_write_b128 v16, v[8:11]
; GFX9-DS128-NEXT: s_endpgm
%load = load <16 x i16>, ptr addrspace(3) %in
%ext = sext <16 x i16> %load to <16 x i64>
@@ -8012,103 +8012,103 @@ define amdgpu_kernel void @local_sextload_v32i16_to_v32i64(ptr addrspace(3) %out
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v12, s1
; SI-NEXT: s_mov_b32 m0, -1
-; SI-NEXT: ds_read2_b64 v[4:7], v12 offset0:2 offset1:3
+; SI-NEXT: ds_read2_b64 v[8:11], v12 offset0:2 offset1:3
; SI-NEXT: ds_read2_b64 v[0:3], v12 offset1:1
-; SI-NEXT: ds_read2_b64 v[8:11], v12 offset0:6 offset1:7
+; SI-NEXT: ds_read2_b64 v[4:7], v12 offset0:6 offset1:7
; SI-NEXT: ds_read2_b64 v[12:15], v12 offset0:4 offset1:5
; SI-NEXT: s_waitcnt lgkmcnt(3)
-; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v7
-; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v7
-; SI-NEXT: v_bfe_i32 v18, v7, 0, 16
+; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v11
+; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v11
+; SI-NEXT: v_bfe_i32 v18, v11, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v19, 31, v18
-; SI-NEXT: v_mov_b32_e32 v7, s0
-; SI-NEXT: ds_write2_b64 v7, v[18:19], v[16:17] offset0:14 offset1:15
-; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v5
-; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v5
-; SI-NEXT: v_bfe_i32 v18, v5, 0, 16
+; SI-NEXT: v_mov_b32_e32 v11, s0
+; SI-NEXT: ds_write2_b64 v11, v[18:19], v[16:17] offset0:14 offset1:15
+; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v9
+; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v9
+; SI-NEXT: v_bfe_i32 v18, v9, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v19, 31, v18
-; SI-NEXT: ds_write2_b64 v7, v[18:19], v[16:17] offset0:10 offset1:11
+; SI-NEXT: ds_write2_b64 v11, v[18:19], v[16:17] offset0:10 offset1:11
; SI-NEXT: s_waitcnt lgkmcnt(4)
; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v3
; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v3
; SI-NEXT: v_bfe_i32 v18, v3, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v19, 31, v18
-; SI-NEXT: ds_write2_b64 v7, v[18:19], v[16:17] offset0:6 offset1:7
+; SI-NEXT: ds_write2_b64 v11, v[18:19], v[16:17] offset0:6 offset1:7
; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v1
; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v1
; SI-NEXT: v_bfe_i32 v18, v1, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v19, 31, v18
-; SI-NEXT: ds_write2_b64 v7, v[18:19], v[16:17] offset0:2 offset1:3
+; SI-NEXT: ds_write2_b64 v11, v[18:19], v[16:17] offset0:2 offset1:3
; SI-NEXT: s_waitcnt lgkmcnt(5)
-; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v11
-; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v11
-; SI-NEXT: v_bfe_i32 v18, v11, 0, 16
+; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v7
+; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v7
+; SI-NEXT: v_bfe_i32 v18, v7, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v19, 31, v18
-; SI-NEXT: ds_write2_b64 v7, v[18:19], v[16:17] offset0:30 offset1:31
-; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v9
-; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v9
-; SI-NEXT: v_bfe_i32 v18, v9, 0, 16
+; SI-NEXT: ds_write2_b64 v11, v[18:19], v[16:17] offset0:30 offset1:31
+; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v5
+; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v5
+; SI-NEXT: v_bfe_i32 v18, v5, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v19, 31, v18
-; SI-NEXT: ds_write2_b64 v7, v[18:19], v[16:17] offset0:26 offset1:27
+; SI-NEXT: ds_write2_b64 v11, v[18:19], v[16:17] offset0:26 offset1:27
; SI-NEXT: s_waitcnt lgkmcnt(6)
; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v15
; SI-NEXT: v_ashrrev_i32_e32 v16, 16, v15
; SI-NEXT: v_bfe_i32 v18, v15, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v19, 31, v18
-; SI-NEXT: ds_write2_b64 v7, v[18:19], v[16:17] offset0:22 offset1:23
+; SI-NEXT: ds_write2_b64 v11, v[18:19], v[16:17] offset0:22 offset1:23
; SI-NEXT: v_ashrrev_i32_e32 v16, 31, v13
; SI-NEXT: v_ashrrev_i32_e32 v15, 16, v13
; SI-NEXT: v_bfe_i32 v17, v13, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17
-; SI-NEXT: ds_write2_b64 v7, v[17:18], v[15:16] offset0:18 offset1:19
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
-; SI-NEXT: v_bfe_i32 v5, v6, 0, 16
-; SI-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; SI-NEXT: ds_write2_b64 v11, v[17:18], v[15:16] offset0:18 offset1:19
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v10
+; SI-NEXT: v_bfe_i32 v9, v10, 0, 16
+; SI-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; SI-NEXT: v_bfe_i32 v15, v1, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; SI-NEXT: ds_write2_b64 v7, v[5:6], v[15:16] offset0:12 offset1:13
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; SI-NEXT: v_bfe_i32 v3, v4, 0, 16
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v8
-; SI-NEXT: v_bfe_i32 v5, v1, 0, 16
-; SI-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; SI-NEXT: v_ashrrev_i32_e32 v6, 31, v5
-; SI-NEXT: ds_write2_b64 v7, v[3:4], v[5:6] offset0:8 offset1:9
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v12
+; SI-NEXT: ds_write2_b64 v11, v[9:10], v[15:16] offset0:12 offset1:13
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v6
+; SI-NEXT: v_bfe_i32 v7, v8, 0, 16
+; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v4
+; SI-NEXT: v_bfe_i32 v9, v1, 0, 16
+; SI-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; SI-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; SI-NEXT: ds_write2_b64 v11, v[7:8], v[9:10] offset0:8 offset1:9
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v12
; SI-NEXT: v_bfe_i32 v1, v12, 0, 16
; SI-NEXT: v_bfe_i32 v3, v14, 0, 16
-; SI-NEXT: v_bfe_i32 v5, v8, 0, 16
-; SI-NEXT: v_bfe_i32 v8, v10, 0, 16
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; SI-NEXT: v_bfe_i32 v9, v0, 0, 16
-; SI-NEXT: v_bfe_i32 v10, v2, 0, 16
-; SI-NEXT: v_bfe_i32 v12, v11, 0, 16
-; SI-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; SI-NEXT: v_bfe_i32 v5, v4, 0, 16
+; SI-NEXT: v_bfe_i32 v7, v6, 0, 16
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v0
+; SI-NEXT: v_bfe_i32 v8, v0, 0, 16
+; SI-NEXT: v_bfe_i32 v9, v2, 0, 16
+; SI-NEXT: v_bfe_i32 v12, v13, 0, 16
+; SI-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; SI-NEXT: v_ashrrev_i32_e32 v13, 31, v12
-; SI-NEXT: ds_write2_b64 v7, v[10:11], v[12:13] offset0:4 offset1:5
-; SI-NEXT: v_bfe_i32 v11, v6, 0, 16
+; SI-NEXT: ds_write2_b64 v11, v[9:10], v[12:13] offset0:4 offset1:5
+; SI-NEXT: v_bfe_i32 v12, v18, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; SI-NEXT: v_bfe_i32 v13, v4, 0, 16
+; SI-NEXT: v_bfe_i32 v14, v17, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; SI-NEXT: v_bfe_i32 v15, v15, 0, 16
+; SI-NEXT: v_bfe_i32 v16, v16, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v6, 31, v5
-; SI-NEXT: v_bfe_i32 v16, v14, 0, 16
-; SI-NEXT: v_ashrrev_i32_e32 v10, 31, v9
-; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; SI-NEXT: ds_write2_b64 v7, v[9:10], v[16:17] offset1:1
-; SI-NEXT: v_bfe_i32 v17, v18, 0, 16
+; SI-NEXT: v_bfe_i32 v17, v19, 0, 16
; SI-NEXT: v_ashrrev_i32_e32 v9, 31, v8
-; SI-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; SI-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; SI-NEXT: v_ashrrev_i32_e32 v16, 31, v15
; SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17
-; SI-NEXT: ds_write2_b64 v7, v[8:9], v[17:18] offset0:28 offset1:29
-; SI-NEXT: ds_write2_b64 v7, v[5:6], v[15:16] offset0:24 offset1:25
-; SI-NEXT: ds_write2_b64 v7, v[3:4], v[13:14] offset0:20 offset1:21
-; SI-NEXT: ds_write2_b64 v7, v[1:2], v[11:12] offset0:16 offset1:17
+; SI-NEXT: ds_write2_b64 v11, v[8:9], v[17:18] offset1:1
+; SI-NEXT: v_bfe_i32 v9, v15, 0, 16
+; SI-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; SI-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; SI-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; SI-NEXT: v_ashrrev_i32_e32 v17, 31, v16
+; SI-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; SI-NEXT: ds_write2_b64 v11, v[7:8], v[9:10] offset0:28 offset1:29
+; SI-NEXT: ds_write2_b64 v11, v[5:6], v[16:17] offset0:24 offset1:25
+; SI-NEXT: ds_write2_b64 v11, v[3:4], v[14:15] offset0:20 offset1:21
+; SI-NEXT: ds_write2_b64 v11, v[1:2], v[12:13] offset0:16 offset1:17
; SI-NEXT: s_endpgm
;
; VI-NO-DS128-LABEL: local_sextload_v32i16_to_v32i64:
@@ -8682,223 +8682,223 @@ define amdgpu_kernel void @local_sextload_v32i16_to_v32i64(ptr addrspace(3) %out
; VI-DS128-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-DS128-NEXT: s_mov_b32 m0, -1
; VI-DS128-NEXT: s_waitcnt lgkmcnt(0)
-; VI-DS128-NEXT: v_mov_b32_e32 v4, s1
-; VI-DS128-NEXT: ds_read_b128 v[0:3], v4 offset:48
-; VI-DS128-NEXT: ds_read_b128 v[9:12], v4 offset:32
-; VI-DS128-NEXT: v_mov_b32_e32 v8, s0
-; VI-DS128-NEXT: ds_read_b128 v[17:20], v4 offset:16
-; VI-DS128-NEXT: ds_read_b128 v[4:7], v4
-; VI-DS128-NEXT: s_waitcnt lgkmcnt(3)
-; VI-DS128-NEXT: v_bfe_i32 v13, v2, 0, 16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-DS128-NEXT: v_bfe_i32 v15, v2, 0, 16
+; VI-DS128-NEXT: v_mov_b32_e32 v0, s1
+; VI-DS128-NEXT: ds_read_b128 v[5:8], v0 offset:48
+; VI-DS128-NEXT: ds_read_b128 v[9:12], v0 offset:32
+; VI-DS128-NEXT: v_mov_b32_e32 v4, s0
+; VI-DS128-NEXT: s_waitcnt lgkmcnt(1)
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v1, 16, v7
+; VI-DS128-NEXT: v_bfe_i32 v13, v7, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v15, v1, 0, 16
; VI-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; VI-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; VI-DS128-NEXT: ds_write_b128 v8, v[13:16] offset:224
-; VI-DS128-NEXT: v_bfe_i32 v15, v2, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v13, v3, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v8
+; VI-DS128-NEXT: ds_read_b128 v[17:20], v0 offset:16
+; VI-DS128-NEXT: ds_read_b128 v[0:3], v0
+; VI-DS128-NEXT: ds_write_b128 v4, v[13:16] offset:224
+; VI-DS128-NEXT: v_bfe_i32 v15, v7, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v13, v8, 0, 16
; VI-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; VI-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; VI-DS128-NEXT: ds_write_b128 v8, v[13:16] offset:240
-; VI-DS128-NEXT: v_bfe_i32 v15, v2, 0, 16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; VI-DS128-NEXT: v_bfe_i32 v13, v0, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v0, v1, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; VI-DS128-NEXT: ds_write_b128 v8, v[0:3] offset:208
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; VI-DS128-NEXT: ds_write_b128 v4, v[13:16] offset:240
+; VI-DS128-NEXT: v_bfe_i32 v15, v7, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v6
+; VI-DS128-NEXT: v_bfe_i32 v13, v5, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v5, v6, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v7, v7, 0, 16
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; VI-DS128-NEXT: ds_write_b128 v4, v[5:8] offset:208
; VI-DS128-NEXT: s_waitcnt lgkmcnt(5)
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; VI-DS128-NEXT: v_bfe_i32 v0, v11, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; VI-DS128-NEXT: ds_write_b128 v8, v[0:3] offset:160
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v12
-; VI-DS128-NEXT: v_bfe_i32 v0, v12, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; VI-DS128-NEXT: ds_write_b128 v8, v[0:3] offset:176
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; VI-DS128-NEXT: v_bfe_i32 v0, v9, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; VI-DS128-NEXT: ds_write_b128 v8, v[0:3] offset:128
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v11
+; VI-DS128-NEXT: v_bfe_i32 v5, v11, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v7, v7, 0, 16
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; VI-DS128-NEXT: ds_write_b128 v4, v[5:8] offset:160
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v12
+; VI-DS128-NEXT: v_bfe_i32 v5, v12, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v7, v7, 0, 16
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; VI-DS128-NEXT: ds_write_b128 v4, v[5:8] offset:176
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v9
+; VI-DS128-NEXT: v_bfe_i32 v5, v9, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v7, v7, 0, 16
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; VI-DS128-NEXT: ds_write_b128 v4, v[5:8] offset:128
; VI-DS128-NEXT: s_waitcnt lgkmcnt(6)
-; VI-DS128-NEXT: v_bfe_i32 v0, v5, 0, 16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v5, 16, v10
+; VI-DS128-NEXT: v_bfe_i32 v5, v1, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-DS128-NEXT: v_bfe_i32 v7, v1, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v1, 16, v10
; VI-DS128-NEXT: v_bfe_i32 v9, v10, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v11, v5, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v11, v1, 0, 16
; VI-DS128-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; VI-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v5, 16, v19
-; VI-DS128-NEXT: ds_write_b128 v8, v[9:12] offset:144
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v1, 16, v19
+; VI-DS128-NEXT: ds_write_b128 v4, v[9:12] offset:144
; VI-DS128-NEXT: v_bfe_i32 v9, v19, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v11, v5, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v11, v1, 0, 16
; VI-DS128-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; VI-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v5, 16, v20
-; VI-DS128-NEXT: ds_write_b128 v8, v[9:12] offset:96
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v1, 16, v20
+; VI-DS128-NEXT: ds_write_b128 v4, v[9:12] offset:96
; VI-DS128-NEXT: v_bfe_i32 v9, v20, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v11, v5, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v11, v1, 0, 16
; VI-DS128-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; VI-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v5, 16, v17
-; VI-DS128-NEXT: ds_write_b128 v8, v[9:12] offset:112
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v1, 16, v17
+; VI-DS128-NEXT: ds_write_b128 v4, v[9:12] offset:112
; VI-DS128-NEXT: v_bfe_i32 v9, v17, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v11, v5, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v11, v1, 0, 16
; VI-DS128-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; VI-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
-; VI-DS128-NEXT: ds_write_b128 v8, v[9:12] offset:64
-; VI-DS128-NEXT: v_bfe_i32 v9, v4, 0, 16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; VI-DS128-NEXT: ds_write_b128 v4, v[9:12] offset:64
+; VI-DS128-NEXT: v_bfe_i32 v9, v0, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; VI-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; VI-DS128-NEXT: v_bfe_i32 v11, v4, 0, 16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v18
-; VI-DS128-NEXT: ds_write_b128 v8, v[13:16] offset:192
+; VI-DS128-NEXT: v_bfe_i32 v11, v0, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v18
+; VI-DS128-NEXT: ds_write_b128 v4, v[13:16] offset:192
; VI-DS128-NEXT: v_bfe_i32 v13, v18, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v15, v4, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v15, v0, 0, 16
; VI-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; VI-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; VI-DS128-NEXT: ds_write_b128 v8, v[13:16] offset:80
-; VI-DS128-NEXT: v_bfe_i32 v13, v7, 0, 16
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v7
-; VI-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v6
-; VI-DS128-NEXT: v_bfe_i32 v15, v4, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v4, v6, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v6, v7, 0, 16
-; VI-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; VI-DS128-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; VI-DS128-NEXT: ds_write_b128 v4, v[13:16] offset:80
+; VI-DS128-NEXT: v_bfe_i32 v13, v3, 0, 16
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; VI-DS128-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; VI-DS128-NEXT: v_bfe_i32 v15, v0, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v0, v2, 0, 16
+; VI-DS128-NEXT: v_bfe_i32 v2, v3, 0, 16
; VI-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; VI-DS128-NEXT: v_ashrrev_i32_e32 v8, 31, v7
; VI-DS128-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; VI-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
; VI-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; VI-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; VI-DS128-NEXT: ds_write_b128 v8, v[4:7] offset:32
-; VI-DS128-NEXT: ds_write_b128 v8, v[13:16] offset:48
-; VI-DS128-NEXT: ds_write_b128 v8, v[9:12]
-; VI-DS128-NEXT: ds_write_b128 v8, v[0:3] offset:16
+; VI-DS128-NEXT: ds_write_b128 v4, v[0:3] offset:32
+; VI-DS128-NEXT: ds_write_b128 v4, v[13:16] offset:48
+; VI-DS128-NEXT: ds_write_b128 v4, v[9:12]
+; VI-DS128-NEXT: ds_write_b128 v4, v[5:8] offset:16
; VI-DS128-NEXT: s_endpgm
;
; GFX9-DS128-LABEL: local_sextload_v32i16_to_v32i64:
; GFX9-DS128: ; %bb.0:
; GFX9-DS128-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DS128-NEXT: v_mov_b32_e32 v13, s1
-; GFX9-DS128-NEXT: ds_read_b128 v[4:7], v13 offset:48
-; GFX9-DS128-NEXT: ds_read_b128 v[0:3], v13 offset:32
-; GFX9-DS128-NEXT: v_mov_b32_e32 v12, s0
-; GFX9-DS128-NEXT: ds_read_b128 v[8:11], v13
-; GFX9-DS128-NEXT: ds_read_b128 v[18:21], v13 offset:16
-; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(3)
-; GFX9-DS128-NEXT: v_bfe_i32 v14, v6, 0, 16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX9-DS128-NEXT: v_bfe_i32 v16, v6, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v15, 31, v14
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v6, 16, v7
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[14:17] offset:224
-; GFX9-DS128-NEXT: v_bfe_i32 v15, v6, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v13, v7, 0, 16
+; GFX9-DS128-NEXT: v_mov_b32_e32 v17, s1
+; GFX9-DS128-NEXT: ds_read_b128 v[9:12], v17 offset:48
+; GFX9-DS128-NEXT: ds_read_b128 v[0:3], v17 offset:32
+; GFX9-DS128-NEXT: v_mov_b32_e32 v8, s0
+; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(1)
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v11
+; GFX9-DS128-NEXT: v_bfe_i32 v13, v11, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v15, v4, 0, 16
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[13:16] offset:240
-; GFX9-DS128-NEXT: v_bfe_i32 v15, v6, 0, 16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX9-DS128-NEXT: v_bfe_i32 v13, v4, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v4, v5, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v6, v6, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[4:7] offset:208
-; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(5)
-; GFX9-DS128-NEXT: v_bfe_i32 v4, v2, 0, 16
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v11, 16, v12
+; GFX9-DS128-NEXT: ds_read_b128 v[4:7], v17
+; GFX9-DS128-NEXT: ds_read_b128 v[17:20], v17 offset:16
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[13:16] offset:224
+; GFX9-DS128-NEXT: v_bfe_i32 v13, v11, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v11, v12, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[11:14] offset:240
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v11, 16, v9
+; GFX9-DS128-NEXT: v_bfe_i32 v13, v11, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v11, v9, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[11:14] offset:192
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v11, 16, v10
+; GFX9-DS128-NEXT: v_bfe_i32 v9, v10, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v11, v11, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[9:12] offset:208
+; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(6)
+; GFX9-DS128-NEXT: v_bfe_i32 v9, v2, 0, 16
; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-DS128-NEXT: v_bfe_i32 v6, v2, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX9-DS128-NEXT: v_bfe_i32 v11, v2, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[4:7] offset:160
-; GFX9-DS128-NEXT: v_bfe_i32 v4, v3, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v6, v2, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX9-DS128-NEXT: v_bfe_i32 v2, v0, 0, 16
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[9:12] offset:160
+; GFX9-DS128-NEXT: v_bfe_i32 v9, v3, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v11, v2, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[9:12] offset:176
+; GFX9-DS128-NEXT: v_bfe_i32 v9, v0, 0, 16
; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[4:7] offset:176
-; GFX9-DS128-NEXT: v_bfe_i32 v4, v0, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v5, 31, v4
-; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(6)
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v9
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[2:5] offset:128
-; GFX9-DS128-NEXT: v_bfe_i32 v4, v0, 0, 16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[13:16] offset:192
-; GFX9-DS128-NEXT: v_bfe_i32 v13, v1, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v15, v0, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
+; GFX9-DS128-NEXT: v_bfe_i32 v11, v0, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(7)
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v20
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[13:16] offset:144
-; GFX9-DS128-NEXT: v_bfe_i32 v13, v20, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v15, v0, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v21
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[13:16] offset:96
-; GFX9-DS128-NEXT: v_bfe_i32 v13, v21, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v15, v0, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v18
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[13:16] offset:112
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[9:12] offset:128
+; GFX9-DS128-NEXT: v_bfe_i32 v11, v0, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v0, v1, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[0:3] offset:144
+; GFX9-DS128-NEXT: s_waitcnt lgkmcnt(8)
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v19
+; GFX9-DS128-NEXT: v_bfe_i32 v0, v19, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[0:3] offset:96
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v20
+; GFX9-DS128-NEXT: v_bfe_i32 v0, v20, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[0:3] offset:112
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v17
+; GFX9-DS128-NEXT: v_bfe_i32 v0, v17, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[0:3] offset:64
+; GFX9-DS128-NEXT: v_bfe_i32 v0, v4, 0, 16
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v2, 16, v4
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v18
; GFX9-DS128-NEXT: v_bfe_i32 v13, v18, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v15, v0, 0, 16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; GFX9-DS128-NEXT: v_bfe_i32 v15, v4, 0, 16
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; GFX9-DS128-NEXT: v_bfe_i32 v6, v8, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v8, v0, 0, 16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v19
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[13:16] offset:64
-; GFX9-DS128-NEXT: v_bfe_i32 v13, v19, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v15, v0, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v11
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[13:16] offset:80
-; GFX9-DS128-NEXT: v_bfe_i32 v15, v0, 0, 16
-; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v0, 16, v10
-; GFX9-DS128-NEXT: v_bfe_i32 v17, v10, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v19, v0, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v2, v9, 0, 16
-; GFX9-DS128-NEXT: v_bfe_i32 v13, v11, 0, 16
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v18, 31, v17
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v20, 31, v19
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[13:16] offset:80
+; GFX9-DS128-NEXT: v_bfe_i32 v13, v7, 0, 16
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v4, 16, v7
+; GFX9-DS128-NEXT: v_lshrrev_b32_e32 v7, 16, v6
+; GFX9-DS128-NEXT: v_bfe_i32 v15, v4, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v4, v6, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v6, v7, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v9, v5, 0, 16
+; GFX9-DS128-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v12, 31, v11
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; GFX9-DS128-NEXT: v_ashrrev_i32_e32 v16, 31, v15
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[17:20] offset:32
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[13:16] offset:48
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[6:9]
-; GFX9-DS128-NEXT: ds_write_b128 v12, v[2:5] offset:16
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[4:7] offset:32
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[13:16] offset:48
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[0:3]
+; GFX9-DS128-NEXT: ds_write_b128 v8, v[9:12] offset:16
; GFX9-DS128-NEXT: s_endpgm
%load = load <32 x i16>, ptr addrspace(3) %in
%ext = sext <32 x i16> %load to <32 x i64>
diff --git a/llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll b/llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
index 0ce3742bb0e83..18a7d7954edd7 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
@@ -9,10 +9,8 @@ define <3 x float> @liveout_undef_subrange(<3 x float> %arg) {
; CHECK-LABEL: liveout_undef_subrange:
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_add_f32_e32 v3, v2, v2
+; CHECK-NEXT: v_add_f32_e32 v0, v2, v2
; CHECK-NEXT: s_mov_b64 s[4:5], 0
-; CHECK-NEXT: ; kill: killed $vgpr1
-; CHECK-NEXT: v_add_f32_e32 v0, v0, v0
; CHECK-NEXT: .LBB0_1: ; %bb1
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_cmp_neq_f32_e32 vcc, 0, v2
@@ -22,7 +20,7 @@ define <3 x float> @liveout_undef_subrange(<3 x float> %arg) {
; CHECK-NEXT: ; %bb.2: ; %bb2
; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
-; CHECK-NEXT: v_mul_f32_e32 v2, v3, v2
+; CHECK-NEXT: v_mul_f32_e32 v2, v0, v2
; CHECK-NEXT: s_mov_b64 s[4:5], 0
; CHECK-NEXT: s_cbranch_execnz .LBB0_1
; CHECK-NEXT: ; %bb.3: ; %DummyReturnBlock
diff --git a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
index cc0fce9a5261b..37840b5711261 100644
--- a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+++ b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
@@ -9623,7 +9623,7 @@ define void @memmove_p0_p4_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(4
; UNROLL3-NEXT: s_clause 0x1
; UNROLL3-NEXT: global_load_dwordx4 v[4:7], v[2:3], off offset:2016
; UNROLL3-NEXT: global_load_dwordx4 v[8:11], v[2:3], off offset:2032
-; UNROLL3-NEXT: ; implicit-def: $vgpr2_vgpr3
+; UNROLL3-NEXT: ; implicit-def: $vgpr2
; UNROLL3-NEXT: s_waitcnt vmcnt(1)
; UNROLL3-NEXT: flat_store_dwordx4 v[0:1], v[4:7] offset:2016
; UNROLL3-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll b/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
index 990a986ffab75..7414db08dbf35 100644
--- a/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
+++ b/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
@@ -259,35 +259,32 @@ define void @memset_p3_varsize_align_4_varsetval(ptr addrspace(3) align 4 %dst,
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v3
; GFX942-SDAG-NEXT: v_and_b32_e32 v4, -16, v2
-; GFX942-SDAG-NEXT: v_and_b32_e32 v10, 15, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, 0
+; GFX942-SDAG-NEXT: v_and_b32_e32 v6, 15, v2
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, 0
; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0
; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-SDAG-NEXT: s_cbranch_execz .LBB2_3
; GFX942-SDAG-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader
; GFX942-SDAG-NEXT: s_mov_b32 s4, 0x4040404
-; GFX942-SDAG-NEXT: v_perm_b32 v6, v1, v1, s4
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v6
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v6
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v6
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v0
+; GFX942-SDAG-NEXT: v_perm_b32 v3, v1, v1, s4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v0
; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0
; GFX942-SDAG-NEXT: .LBB2_2: ; %dynamic-memset-expansion-main-body
; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 16
; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0
; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[4:5]
-; GFX942-SDAG-NEXT: ds_write2_b32 v9, v8, v7 offset0:2 offset1:3
-; GFX942-SDAG-NEXT: ds_write2_b32 v9, v6, v3 offset1:1
+; GFX942-SDAG-NEXT: ds_write2_b32 v8, v3, v3 offset0:2 offset1:3
+; GFX942-SDAG-NEXT: ds_write2_b32 v8, v3, v3 offset1:1
; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX942-SDAG-NEXT: v_add_u32_e32 v9, 16, v9
+; GFX942-SDAG-NEXT: v_add_u32_e32 v8, 16, v8
; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1]
; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB2_2
; GFX942-SDAG-NEXT: .LBB2_3: ; %Flow7
; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0
-; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
+; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-SDAG-NEXT: s_cbranch_execz .LBB2_6
; GFX942-SDAG-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader
@@ -298,7 +295,7 @@ define void @memset_p3_varsize_align_4_varsetval(ptr addrspace(3) align 4 %dst,
; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 1
; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0
-; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[10:11]
+; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[6:7]
; GFX942-SDAG-NEXT: ds_write_b8 v0, v1
; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 1, v0
@@ -1107,79 +1104,48 @@ define void @memset_p3_sz1055_align_4_varsetval(ptr addrspace(3) align 4 %dst, i
; GFX942-SDAG: ; %bb.0: ; %entry
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404
-; GFX942-SDAG-NEXT: v_perm_b32 v2, v1, v1, s0
+; GFX942-SDAG-NEXT: v_perm_b32 v4, v1, v1, s0
; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[34:35], 0x400
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v36, v0
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v12, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v14, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v15, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v22, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v23, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v24, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v25, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v26, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v27, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v28, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v29, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v30, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v31, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v32, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v33, v2
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], 0x400
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v0
; GFX942-SDAG-NEXT: .LBB8_1: ; %static-memset-expansion-main-body
; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX942-SDAG-NEXT: s_add_u32 s0, s0, 0x100
; GFX942-SDAG-NEXT: s_addc_u32 s1, s1, 0
-; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[34:35]
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v32, v33 offset0:30 offset1:31
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v30, v31 offset0:28 offset1:29
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v28, v29 offset0:26 offset1:27
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v26, v27 offset0:24 offset1:25
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v24, v25 offset0:22 offset1:23
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v22, v23 offset0:20 offset1:21
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v20, v21 offset0:18 offset1:19
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v18, v19 offset0:16 offset1:17
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v16, v17 offset0:14 offset1:15
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v14, v15 offset0:12 offset1:13
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v12, v13 offset0:10 offset1:11
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v10, v11 offset0:8 offset1:9
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v8, v9 offset0:6 offset1:7
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v6, v7 offset0:4 offset1:5
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v4, v5 offset0:2 offset1:3
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v2, v3 offset1:1
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v32, v33 offset0:62 offset1:63
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v30, v31 offset0:60 offset1:61
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v28, v29 offset0:58 offset1:59
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v26, v27 offset0:56 offset1:57
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v24, v25 offset0:54 offset1:55
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v22, v23 offset0:52 offset1:53
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v20, v21 offset0:50 offset1:51
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v18, v19 offset0:48 offset1:49
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v16, v17 offset0:46 offset1:47
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v14, v15 offset0:44 offset1:45
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v12, v13 offset0:42 offset1:43
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v10, v11 offset0:40 offset1:41
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v8, v9 offset0:38 offset1:39
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v6, v7 offset0:36 offset1:37
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v4, v5 offset0:34 offset1:35
-; GFX942-SDAG-NEXT: ds_write2_b32 v36, v2, v3 offset0:32 offset1:33
-; GFX942-SDAG-NEXT: v_add_u32_e32 v36, 0x100, v36
+; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:30 offset1:31
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:28 offset1:29
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:26 offset1:27
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:24 offset1:25
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:22 offset1:23
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:20 offset1:21
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:18 offset1:19
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:16 offset1:17
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:14 offset1:15
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:12 offset1:13
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:10 offset1:11
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:8 offset1:9
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:6 offset1:7
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:4 offset1:5
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:2 offset1:3
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset1:1
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:62 offset1:63
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:60 offset1:61
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:58 offset1:59
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:56 offset1:57
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:54 offset1:55
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:52 offset1:53
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:50 offset1:51
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:48 offset1:49
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:46 offset1:47
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:44 offset1:45
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:42 offset1:43
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:40 offset1:41
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:38 offset1:39
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:36 offset1:37
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:34 offset1:35
+; GFX942-SDAG-NEXT: ds_write2_b32 v5, v4, v4 offset0:32 offset1:33
+; GFX942-SDAG-NEXT: v_add_u32_e32 v5, 0x100, v5
; GFX942-SDAG-NEXT: s_cbranch_vccnz .LBB8_1
; GFX942-SDAG-NEXT: ; %bb.2: ; %static-memset-post-expansion
; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404
@@ -1268,77 +1234,46 @@ define void @memset_p3_sz2048_align_4_varsetval(ptr addrspace(3) align 4 %dst, i
; GFX942-SDAG: ; %bb.0: ; %entry
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404
-; GFX942-SDAG-NEXT: v_perm_b32 v2, v1, v1, s0
+; GFX942-SDAG-NEXT: v_perm_b32 v1, v1, v1, s0
; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0
-; GFX942-SDAG-NEXT: v_mov_b64_e32 v[34:35], 0x800
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v12, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v14, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v15, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v22, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v24, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v23, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v26, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v25, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v28, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v27, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v30, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v29, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v32, v2
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v31, v2
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], 0x800
; GFX942-SDAG-NEXT: .LBB9_1: ; %static-memset-expansion-main-body
; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX942-SDAG-NEXT: s_add_u32 s0, s0, 0x100
; GFX942-SDAG-NEXT: s_addc_u32 s1, s1, 0
-; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[34:35]
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v32, v31 offset0:30 offset1:31
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v30, v29 offset0:28 offset1:29
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v28, v27 offset0:26 offset1:27
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v26, v25 offset0:24 offset1:25
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v24, v23 offset0:22 offset1:23
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v22, v21 offset0:20 offset1:21
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v20, v19 offset0:18 offset1:19
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v18, v17 offset0:16 offset1:17
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v16, v15 offset0:14 offset1:15
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v14, v13 offset0:12 offset1:13
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v12, v11 offset0:10 offset1:11
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v10, v9 offset0:8 offset1:9
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v8, v7 offset0:6 offset1:7
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v6, v5 offset0:4 offset1:5
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v4, v3 offset0:2 offset1:3
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v2, v1 offset1:1
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v32, v31 offset0:62 offset1:63
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v30, v29 offset0:60 offset1:61
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v28, v27 offset0:58 offset1:59
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v26, v25 offset0:56 offset1:57
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v24, v23 offset0:54 offset1:55
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v22, v21 offset0:52 offset1:53
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v20, v19 offset0:50 offset1:51
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v18, v17 offset0:48 offset1:49
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v16, v15 offset0:46 offset1:47
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v14, v13 offset0:44 offset1:45
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v12, v11 offset0:42 offset1:43
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v10, v9 offset0:40 offset1:41
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v8, v7 offset0:38 offset1:39
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v6, v5 offset0:36 offset1:37
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v4, v3 offset0:34 offset1:35
-; GFX942-SDAG-NEXT: ds_write2_b32 v0, v2, v1 offset0:32 offset1:33
+; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:30 offset1:31
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:28 offset1:29
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:26 offset1:27
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:24 offset1:25
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:22 offset1:23
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:20 offset1:21
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:18 offset1:19
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:16 offset1:17
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:14 offset1:15
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:12 offset1:13
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:10 offset1:11
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:8 offset1:9
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:6 offset1:7
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:4 offset1:5
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:2 offset1:3
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset1:1
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:62 offset1:63
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:60 offset1:61
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:58 offset1:59
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:56 offset1:57
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:54 offset1:55
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:52 offset1:53
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:50 offset1:51
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:48 offset1:49
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:46 offset1:47
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:44 offset1:45
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:42 offset1:43
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:40 offset1:41
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:38 offset1:39
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:36 offset1:37
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:34 offset1:35
+; GFX942-SDAG-NEXT: ds_write2_b32 v0, v1, v1 offset0:32 offset1:33
; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 0x100, v0
; GFX942-SDAG-NEXT: s_cbranch_vccnz .LBB9_1
; GFX942-SDAG-NEXT: ; %bb.2: ; %static-memset-post-expansion
diff --git a/llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll b/llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll
index a588e99980c6e..765fecfaaed29 100644
--- a/llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll
+++ b/llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll
@@ -22,7 +22,7 @@ define amdgpu_kernel void @test_revert_schedule(i32 %arg0, i32 %arg1, ptr addrsp
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 64, 0 :: (dereferenceable invariant load (s32) from %ir.loopcond.kernarg.offset.align.down, align 16, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg0.kernarg.offset1, addrspace 4)
- ; CHECK-NEXT: [[S_LOAD_DWORD_IMM1:%[0-9]+]]:sgpr_32 = S_LOAD_DWORD_IMM [[COPY]](p4), 16, 0 :: (dereferenceable invariant load (s32) from %ir.arg0.kernarg.offset1 + 16, align 16, addrspace 4)
+ ; CHECK-NEXT: [[S_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 16, 0 :: (dereferenceable invariant load (s32) from %ir.arg0.kernarg.offset1 + 16, align 16, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORD_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 32, 0 :: (dereferenceable invariant load (s32) from %ir.arg4.kernarg.offset, align 16, addrspace 4)
; CHECK-NEXT: S_BITCMP1_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc
; CHECK-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
index b7947de7d5836..17bf63178fab9 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
@@ -731,7 +731,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX9_W64-NEXT: ;;#ASMSTART
; GFX9_W64-NEXT: s_mov_b32 s4, 17
; GFX9_W64-NEXT: ;;#ASMEND
-; GFX9_W64-NEXT: v_mov_b32_e32 v8, s4
+; GFX9_W64-NEXT: v_mov_b32_e32 v9, s4
; GFX9_W64-NEXT: s_mov_b64 s[12:13], exec
; GFX9_W64-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
; GFX9_W64-NEXT: v_readfirstlane_b32 s8, v0
@@ -743,9 +743,9 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX9_W64-NEXT: s_and_b64 s[6:7], vcc, s[6:7]
; GFX9_W64-NEXT: s_and_saveexec_b64 s[6:7], s[6:7]
; GFX9_W64-NEXT: s_nop 0
-; GFX9_W64-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen
+; GFX9_W64-NEXT: buffer_load_format_x v8, v9, s[8:11], 0 idxen
; GFX9_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX9_W64-NEXT: ; implicit-def: $vgpr8
+; GFX9_W64-NEXT: ; implicit-def: $vgpr9
; GFX9_W64-NEXT: s_xor_b64 exec, exec, s[6:7]
; GFX9_W64-NEXT: s_cbranch_execnz .LBB2_1
; GFX9_W64-NEXT: ; %bb.2:
@@ -767,9 +767,10 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX9_W64-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX9_W64-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]
; GFX9_W64-NEXT: s_nop 0
-; GFX9_W64-NEXT: buffer_load_format_x v9, v0, s[8:11], 0 idxen
-; GFX9_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
+; GFX9_W64-NEXT: buffer_load_format_x v8, v0, s[8:11], 0 idxen
+; GFX9_W64-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX9_W64-NEXT: ; implicit-def: $vgpr0
+; GFX9_W64-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX9_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX9_W64-NEXT: s_cbranch_execnz .LBB2_4
; GFX9_W64-NEXT: ; %bb.5:
@@ -777,7 +778,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX9_W64-NEXT: .LBB2_6: ; %bb2
; GFX9_W64-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX9_W64-NEXT: s_waitcnt vmcnt(0)
-; GFX9_W64-NEXT: global_store_dword v[11:12], v9, off
+; GFX9_W64-NEXT: global_store_dword v[11:12], v8, off
; GFX9_W64-NEXT: s_waitcnt vmcnt(0)
; GFX9_W64-NEXT: s_setpc_b64 s[30:31]
;
@@ -787,7 +788,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W32-NEXT: ;;#ASMSTART
; GFX1010_W32-NEXT: s_mov_b32 s4, 17
; GFX1010_W32-NEXT: ;;#ASMEND
-; GFX1010_W32-NEXT: v_mov_b32_e32 v8, s4
+; GFX1010_W32-NEXT: v_mov_b32_e32 v9, s4
; GFX1010_W32-NEXT: s_mov_b32 s6, exec_lo
; GFX1010_W32-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
; GFX1010_W32-NEXT: v_readfirstlane_b32 s8, v0
@@ -798,9 +799,9 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W32-NEXT: v_cmp_eq_u64_e64 s5, s[10:11], v[2:3]
; GFX1010_W32-NEXT: s_and_b32 s5, vcc_lo, s5
; GFX1010_W32-NEXT: s_and_saveexec_b32 s5, s5
-; GFX1010_W32-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen
+; GFX1010_W32-NEXT: buffer_load_format_x v8, v9, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX1010_W32-NEXT: ; implicit-def: $vgpr8
+; GFX1010_W32-NEXT: ; implicit-def: $vgpr9
; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s5
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB2_1
@@ -822,9 +823,10 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W32-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[6:7]
; GFX1010_W32-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX1010_W32-NEXT: s_and_saveexec_b32 s4, s4
-; GFX1010_W32-NEXT: buffer_load_format_x v9, v0, s[8:11], 0 idxen
-; GFX1010_W32-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
+; GFX1010_W32-NEXT: buffer_load_format_x v8, v0, s[8:11], 0 idxen
+; GFX1010_W32-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0
+; GFX1010_W32-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB2_4
@@ -833,7 +835,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W32-NEXT: .LBB2_6: ; %bb2
; GFX1010_W32-NEXT: s_or_b32 exec_lo, exec_lo, s5
; GFX1010_W32-NEXT: s_waitcnt vmcnt(0)
-; GFX1010_W32-NEXT: global_store_dword v[11:12], v9, off
+; GFX1010_W32-NEXT: global_store_dword v[11:12], v8, off
; GFX1010_W32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010_W32-NEXT: s_setpc_b64 s[30:31]
;
@@ -843,7 +845,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W64-NEXT: ;;#ASMSTART
; GFX1010_W64-NEXT: s_mov_b32 s4, 17
; GFX1010_W64-NEXT: ;;#ASMEND
-; GFX1010_W64-NEXT: v_mov_b32_e32 v8, s4
+; GFX1010_W64-NEXT: v_mov_b32_e32 v9, s4
; GFX1010_W64-NEXT: s_mov_b64 s[12:13], exec
; GFX1010_W64-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
; GFX1010_W64-NEXT: v_readfirstlane_b32 s8, v0
@@ -854,9 +856,9 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W64-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], v[2:3]
; GFX1010_W64-NEXT: s_and_b64 s[6:7], vcc, s[6:7]
; GFX1010_W64-NEXT: s_and_saveexec_b64 s[6:7], s[6:7]
-; GFX1010_W64-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen
+; GFX1010_W64-NEXT: buffer_load_format_x v8, v9, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX1010_W64-NEXT: ; implicit-def: $vgpr8
+; GFX1010_W64-NEXT: ; implicit-def: $vgpr9
; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[6:7]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB2_1
@@ -878,9 +880,10 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W64-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], v[6:7]
; GFX1010_W64-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX1010_W64-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]
-; GFX1010_W64-NEXT: buffer_load_format_x v9, v0, s[8:11], 0 idxen
-; GFX1010_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
+; GFX1010_W64-NEXT: buffer_load_format_x v8, v0, s[8:11], 0 idxen
+; GFX1010_W64-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0
+; GFX1010_W64-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB2_4
@@ -889,7 +892,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W64-NEXT: .LBB2_6: ; %bb2
; GFX1010_W64-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1010_W64-NEXT: s_waitcnt vmcnt(0)
-; GFX1010_W64-NEXT: global_store_dword v[11:12], v9, off
+; GFX1010_W64-NEXT: global_store_dword v[11:12], v8, off
; GFX1010_W64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010_W64-NEXT: s_setpc_b64 s[30:31]
;
@@ -899,7 +902,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1100_W32-NEXT: ;;#ASMSTART
; GFX1100_W32-NEXT: s_mov_b32 s4, 17
; GFX1100_W32-NEXT: ;;#ASMEND
-; GFX1100_W32-NEXT: v_mov_b32_e32 v8, s4
+; GFX1100_W32-NEXT: v_mov_b32_e32 v9, s4
; GFX1100_W32-NEXT: s_mov_b32 s1, exec_lo
; GFX1100_W32-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
; GFX1100_W32-NEXT: v_readfirstlane_b32 s8, v0
@@ -912,9 +915,9 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1100_W32-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1100_W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1100_W32-NEXT: s_and_saveexec_b32 s0, s0
-; GFX1100_W32-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen
+; GFX1100_W32-NEXT: buffer_load_format_x v8, v9, s[8:11], 0 idxen
; GFX1100_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX1100_W32-NEXT: ; implicit-def: $vgpr8
+; GFX1100_W32-NEXT: ; implicit-def: $vgpr9
; GFX1100_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1100_W32-NEXT: s_cbranch_execnz .LBB2_1
; GFX1100_W32-NEXT: ; %bb.2:
@@ -938,9 +941,10 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1100_W32-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX1100_W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1100_W32-NEXT: s_and_saveexec_b32 s0, s0
-; GFX1100_W32-NEXT: buffer_load_format_x v9, v0, s[4:7], 0 idxen
-; GFX1100_W32-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
+; GFX1100_W32-NEXT: buffer_load_format_x v8, v0, s[4:7], 0 idxen
+; GFX1100_W32-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1100_W32-NEXT: ; implicit-def: $vgpr0
+; GFX1100_W32-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX1100_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1100_W32-NEXT: s_cbranch_execnz .LBB2_4
; GFX1100_W32-NEXT: ; %bb.5:
@@ -949,7 +953,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1100_W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1100_W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1100_W32-NEXT: s_waitcnt vmcnt(0)
-; GFX1100_W32-NEXT: global_store_b32 v[11:12], v9, off dlc
+; GFX1100_W32-NEXT: global_store_b32 v[11:12], v8, off dlc
; GFX1100_W32-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100_W32-NEXT: s_setpc_b64 s[30:31]
;
@@ -959,7 +963,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1100_W64-NEXT: ;;#ASMSTART
; GFX1100_W64-NEXT: s_mov_b32 s4, 17
; GFX1100_W64-NEXT: ;;#ASMEND
-; GFX1100_W64-NEXT: v_mov_b32_e32 v8, s4
+; GFX1100_W64-NEXT: v_mov_b32_e32 v9, s4
; GFX1100_W64-NEXT: s_mov_b64 s[2:3], exec
; GFX1100_W64-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
; GFX1100_W64-NEXT: v_readfirstlane_b32 s8, v0
@@ -972,9 +976,9 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1100_W64-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; GFX1100_W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1100_W64-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
-; GFX1100_W64-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen
+; GFX1100_W64-NEXT: buffer_load_format_x v8, v9, s[8:11], 0 idxen
; GFX1100_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX1100_W64-NEXT: ; implicit-def: $vgpr8
+; GFX1100_W64-NEXT: ; implicit-def: $vgpr9
; GFX1100_W64-NEXT: s_xor_b64 exec, exec, s[0:1]
; GFX1100_W64-NEXT: s_cbranch_execnz .LBB2_1
; GFX1100_W64-NEXT: ; %bb.2:
@@ -998,9 +1002,10 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1100_W64-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; GFX1100_W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1100_W64-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
-; GFX1100_W64-NEXT: buffer_load_format_x v9, v0, s[4:7], 0 idxen
-; GFX1100_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
+; GFX1100_W64-NEXT: buffer_load_format_x v8, v0, s[4:7], 0 idxen
+; GFX1100_W64-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX1100_W64-NEXT: ; implicit-def: $vgpr0
+; GFX1100_W64-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX1100_W64-NEXT: s_xor_b64 exec, exec, s[0:1]
; GFX1100_W64-NEXT: s_cbranch_execnz .LBB2_4
; GFX1100_W64-NEXT: ; %bb.5:
@@ -1009,7 +1014,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1100_W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1100_W64-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1100_W64-NEXT: s_waitcnt vmcnt(0)
-; GFX1100_W64-NEXT: global_store_b32 v[11:12], v9, off dlc
+; GFX1100_W64-NEXT: global_store_b32 v[11:12], v8, off dlc
; GFX1100_W64-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100_W64-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
index a9207de317ea1..0a0eab0ce289d 100644
--- a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
+++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
@@ -33,9 +33,8 @@ body: |
; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_4:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_4]], %subreg.sub3
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]]
; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], 0, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_1:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], killed [[V_MFMA_F32_16X16X16F16_e64_]], 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_2:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], killed [[V_MFMA_F32_16X16X16F16_e64_1]], 0, 0, 0, implicit $mode, implicit $exec
@@ -48,9 +47,9 @@ body: |
; CHECK-NEXT: [[V_CVT_F16_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[V_PACK_B32_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_PACK_B32_F16_e64 0, killed [[V_CVT_F16_F32_e64_]], 0, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_PACK_B32_F16_e64_]], %subreg.sub0, killed [[V_MOV_B32_e32_]], %subreg.sub1
- ; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3
- ; CHECK-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[REG_SEQUENCE2]], killed [[REG_SEQUENCE3]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8)
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_PACK_B32_F16_e64_]], %subreg.sub0, killed [[V_MOV_B32_e32_]], %subreg.sub1
+ ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3
+ ; CHECK-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[REG_SEQUENCE1]], killed [[REG_SEQUENCE2]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8)
; CHECK-NEXT: S_ENDPGM 0
;
; COALESCE-LABEL: name: test
diff --git a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
index 48ac1c60550d7..a331b058c1aa4 100644
--- a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
@@ -371,10 +371,7 @@ body: |
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, killed [[V_MOV_B32_e32_]], %subreg.sub1
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_LOAD_DWORDX2_IMM1]].sub0, [[REG_SEQUENCE]].sub0, implicit-def $vcc, implicit $exec
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_LOAD_DWORDX2_IMM1]].sub1
- ; GCN-NEXT: [[V_ADDC_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 0, [[COPY3]], implicit-def $vcc, implicit $vcc, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[V_ADD_CO_U32_e32_]], %subreg.sub0, killed [[V_ADDC_U32_e32_]], %subreg.sub1
- ; GCN-NEXT: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 killed [[REG_SEQUENCE1]].sub0, 12, implicit $exec
+ ; GCN-NEXT: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 [[V_ADD_CO_U32_e32_]], 12, implicit $exec
; GCN-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_LT_U32_e64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GCN-NEXT: S_BRANCH %bb.1
; GCN-NEXT: {{ $}}
@@ -384,10 +381,10 @@ body: |
; GCN-NEXT: [[V_LSHL_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHL_B64_e64 [[REG_SEQUENCE]], 2, implicit $exec
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 61440
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
- ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
- ; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub1_sub2_sub3_sub4_sub5, killed [[REG_SEQUENCE2]], %subreg.sub1_sub2_sub3_sub4_sub5_sub6
+ ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
+ ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub1_sub2_sub3_sub4_sub5, killed [[REG_SEQUENCE1]], %subreg.sub1_sub2_sub3_sub4_sub5_sub6
; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GCN-NEXT: BUFFER_STORE_DWORD_ADDR64 killed [[V_MOV_B32_e32_1]], [[V_LSHL_B64_e64_]], killed [[REG_SEQUENCE3]], 0, 0, 0, 0, implicit $exec
+ ; GCN-NEXT: BUFFER_STORE_DWORD_ADDR64 killed [[V_MOV_B32_e32_1]], [[V_LSHL_B64_e64_]], killed [[REG_SEQUENCE2]], 0, 0, 0, 0, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2.bb2:
; GCN-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
index a2b0f4d56ebea..ebfda447d1dc2 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
@@ -715,92 +715,92 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX90A-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX90A-NEXT: v_lshlrev_b32_e32 v0, 17, v0
-; GFX90A-NEXT: v_and_b32_e32 v0, 0xfe000000, v0
-; GFX90A-NEXT: v_lshl_or_b32 v1, v1, 3, v0
-; GFX90A-NEXT: v_mov_b32_e32 v2, s35
-; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, s34, v1
-; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v2, vcc
-; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x2800, v1
-; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GFX90A-NEXT: v_pk_mov_b32 v[4:5], 0, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0x7f
+; GFX90A-NEXT: v_and_b32_e32 v6, 0xfe000000, v0
+; GFX90A-NEXT: v_lshl_or_b32 v0, v1, 3, v6
+; GFX90A-NEXT: v_mov_b32_e32 v1, s35
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0
+; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, 0x2800, v0
+; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX90A-NEXT: v_pk_mov_b32 v[2:3], 0, 0
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0x7f
; GFX90A-NEXT: s_movk_i32 s2, 0xf000
; GFX90A-NEXT: s_movk_i32 s3, 0x1000
; GFX90A-NEXT: s_movk_i32 s4, 0x2000
; GFX90A-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX90A-NEXT: ; =>This Loop Header: Depth=1
; GFX90A-NEXT: ; Child Loop BB1_2 Depth 2
-; GFX90A-NEXT: v_pk_mov_b32 v[6:7], v[2:3], v[2:3] op_sel:[0,1]
+; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[0:1], v[0:1] op_sel:[0,1]
; GFX90A-NEXT: s_mov_b32 s5, 0
; GFX90A-NEXT: .LBB1_2: ; %for.body
; GFX90A-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX90A-NEXT: ; => This Inner Loop Header: Depth=2
-; GFX90A-NEXT: v_add_co_u32_e64 v18, s[0:1], s3, v6
-; GFX90A-NEXT: v_addc_co_u32_e64 v19, s[0:1], 0, v7, s[0:1]
-; GFX90A-NEXT: v_add_co_u32_e64 v20, s[0:1], s4, v6
-; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, 0xffffe000, v6
-; GFX90A-NEXT: v_addc_co_u32_e64 v21, s[0:1], 0, v7, s[0:1]
-; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, -1, v7, vcc
+; GFX90A-NEXT: v_add_co_u32_e64 v18, s[0:1], s3, v4
+; GFX90A-NEXT: v_addc_co_u32_e64 v19, s[0:1], 0, v5, s[0:1]
+; GFX90A-NEXT: v_add_co_u32_e64 v20, s[0:1], s4, v4
+; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, 0xffffe000, v4
+; GFX90A-NEXT: v_addc_co_u32_e64 v21, s[0:1], 0, v5, s[0:1]
+; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, -1, v5, vcc
; GFX90A-NEXT: global_load_dwordx2 v[24:25], v[20:21], off offset:-4096
; GFX90A-NEXT: global_load_dwordx2 v[26:27], v[20:21], off
; GFX90A-NEXT: global_load_dwordx2 v[28:29], v[8:9], off offset:-2048
; GFX90A-NEXT: global_load_dwordx2 v[30:31], v[8:9], off
-; GFX90A-NEXT: v_add_co_u32_e32 v22, vcc, s2, v6
-; GFX90A-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v7, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v22, vcc, s2, v4
+; GFX90A-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v5, vcc
; GFX90A-NEXT: global_load_dwordx2 v[8:9], v[22:23], off offset:-2048
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: global_load_dwordx2 v[18:19], v[18:19], off offset:2048
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: global_load_dwordx2 v[20:21], v[20:21], off offset:2048
; GFX90A-NEXT: s_nop 0
-; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[6:7], off offset:-4096
-; GFX90A-NEXT: global_load_dwordx2 v[12:13], v[6:7], off offset:-2048
-; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[6:7], off
-; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[6:7], off offset:2048
-; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, 0x10000, v6
-; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
+; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:-4096
+; GFX90A-NEXT: global_load_dwordx2 v[12:13], v[4:5], off offset:-2048
+; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[4:5], off
+; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[4:5], off offset:2048
+; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, 0x10000, v4
+; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX90A-NEXT: s_addk_i32 s5, 0x2000
; GFX90A-NEXT: s_cmp_gt_u32 s5, 0x3fffff
; GFX90A-NEXT: s_waitcnt vmcnt(8)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v28, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v29, v5, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v28, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v29, v3, vcc
; GFX90A-NEXT: s_waitcnt vmcnt(7)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v30, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v31, v5, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v30, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v31, v3, vcc
; GFX90A-NEXT: s_waitcnt vmcnt(6)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v5, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v3, vcc
; GFX90A-NEXT: s_waitcnt vmcnt(3)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v10, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v11, v5, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v10, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v11, v3, vcc
; GFX90A-NEXT: s_waitcnt vmcnt(2)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v12, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v13, v5, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v12, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v13, v3, vcc
; GFX90A-NEXT: s_waitcnt vmcnt(1)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v14, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v15, v5, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v14, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v15, v3, vcc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v16, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v17, v5, vcc
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v24, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v25, v5, vcc
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v18, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v19, v5, vcc
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v26, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v27, v5, vcc
-; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v20, v4
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v21, v5, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v16, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v17, v3, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v24, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v25, v3, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v18, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v19, v3, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v26, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v27, v3, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v20, v2
+; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v21, v3, vcc
; GFX90A-NEXT: s_cbranch_scc0 .LBB1_2
; GFX90A-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX90A-NEXT: ; in Loop: Header=BB1_1 Depth=1
-; GFX90A-NEXT: v_subrev_co_u32_e32 v1, vcc, 1, v1
+; GFX90A-NEXT: v_subrev_co_u32_e32 v7, vcc, 1, v7
; GFX90A-NEXT: s_and_b64 vcc, exec, vcc
; GFX90A-NEXT: s_cbranch_vccz .LBB1_1
; GFX90A-NEXT: ; %bb.4: ; %while.end
; GFX90A-NEXT: v_mov_b32_e32 v1, s35
-; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s34, v6
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX90A-NEXT: global_store_dwordx2 v[0:1], v[4:5], off
+; GFX90A-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; GFX90A-NEXT: s_endpgm
;
; GFX11-LABEL: clmem_read:
diff --git a/llvm/test/CodeGen/AMDGPU/rem_i128.ll b/llvm/test/CodeGen/AMDGPU/rem_i128.ll
index 0ead77e1a9cf1..b07577f148447 100644
--- a/llvm/test/CodeGen/AMDGPU/rem_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/rem_i128.ll
@@ -25,12 +25,12 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, 0, v6, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, 0, v7, vcc
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v22, v5, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v23, v4, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v21, v5, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v22, v4, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v11, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v10, vcc
-; GFX9-NEXT: v_or_b32_e32 v7, v22, v5
-; GFX9-NEXT: v_or_b32_e32 v6, v23, v4
+; GFX9-NEXT: v_or_b32_e32 v7, v21, v5
+; GFX9-NEXT: v_or_b32_e32 v6, v22, v4
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
; GFX9-NEXT: v_or_b32_e32 v7, v1, v3
; GFX9-NEXT: v_or_b32_e32 v6, v0, v2
@@ -39,9 +39,9 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_u32_e32 v6, 32, v6
; GFX9-NEXT: v_ffbh_u32_e32 v7, v5
; GFX9-NEXT: v_min_u32_e32 v6, v6, v7
-; GFX9-NEXT: v_ffbh_u32_e32 v7, v23
+; GFX9-NEXT: v_ffbh_u32_e32 v7, v22
; GFX9-NEXT: v_add_u32_e32 v7, 32, v7
-; GFX9-NEXT: v_ffbh_u32_e32 v8, v22
+; GFX9-NEXT: v_ffbh_u32_e32 v8, v21
; GFX9-NEXT: v_min_u32_e32 v7, v7, v8
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 64, v7
@@ -69,7 +69,6 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[6:7]
-; GFX9-NEXT: v_mov_b32_e32 v21, v20
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
@@ -85,20 +84,20 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GFX9-NEXT: v_cndmask_b32_e64 v13, v3, 0, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v12, v2, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v11, v1, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v10, v0, 0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v1, 0, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v0, 0, s[4:5]
; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB0_6
; GFX9-NEXT: ; %bb.1: ; %udiv-bb1
-; GFX9-NEXT: v_add_co_u32_e32 v24, vcc, 1, v6
-; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, 0, v7, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, 0, v8, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v23, vcc, 1, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, 0, v7, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, 0, v8, vcc
; GFX9-NEXT: v_sub_u32_e32 v13, 0x7f, v6
-; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, 0, v9, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, 0, v9, vcc
; GFX9-NEXT: v_sub_u32_e32 v11, 64, v13
-; GFX9-NEXT: v_or_b32_e32 v8, v25, v27
-; GFX9-NEXT: v_or_b32_e32 v7, v24, v26
+; GFX9-NEXT: v_or_b32_e32 v8, v24, v26
+; GFX9-NEXT: v_or_b32_e32 v7, v23, v25
; GFX9-NEXT: v_lshlrev_b64 v[9:10], v13, v[2:3]
; GFX9-NEXT: v_lshrrev_b64 v[11:12], v11, v[0:1]
; GFX9-NEXT: v_sub_u32_e32 v6, 63, v6
@@ -107,85 +106,85 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_or_b32_e32 v8, v10, v12
; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
; GFX9-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v13
+; GFX9-NEXT: v_lshlrev_b64 v[10:11], v13, v[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[4:5]
-; GFX9-NEXT: v_lshlrev_b64 v[8:9], v13, v[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v13
-; GFX9-NEXT: v_mov_b32_e32 v10, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v3, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v2, s[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, v9, s[4:5]
-; GFX9-NEXT: v_mov_b32_e32 v11, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, v8, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, v11, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v9, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, v10, s[4:5]
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB0_5
; GFX9-NEXT: ; %bb.2: ; %udiv-preheader
-; GFX9-NEXT: v_sub_u32_e32 v12, 64, v24
-; GFX9-NEXT: v_lshrrev_b64 v[10:11], v24, v[0:1]
+; GFX9-NEXT: v_sub_u32_e32 v12, 64, v23
+; GFX9-NEXT: v_lshrrev_b64 v[8:9], v23, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[12:13], v12, v[2:3]
-; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v24
-; GFX9-NEXT: v_or_b32_e32 v12, v10, v12
-; GFX9-NEXT: v_subrev_u32_e32 v10, 64, v24
-; GFX9-NEXT: v_or_b32_e32 v13, v11, v13
-; GFX9-NEXT: v_lshrrev_b64 v[10:11], v10, v[2:3]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v24
-; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v15, v11, v1, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v12, v10, v12, vcc
-; GFX9-NEXT: v_lshrrev_b64 v[10:11], v24, v[2:3]
+; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23
+; GFX9-NEXT: v_or_b32_e32 v12, v8, v12
+; GFX9-NEXT: v_subrev_u32_e32 v8, 64, v23
+; GFX9-NEXT: v_or_b32_e32 v13, v9, v13
+; GFX9-NEXT: v_lshrrev_b64 v[8:9], v8, v[2:3]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v23
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v13, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v15, v9, v1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v8, v12, vcc
+; GFX9-NEXT: v_lshrrev_b64 v[8:9], v23, v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v14, v12, v0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v11, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v16, 0, v10, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v28, vcc, -1, v23
-; GFX9-NEXT: v_addc_co_u32_e32 v29, vcc, -1, v22, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v30, vcc, -1, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v16, 0, v8, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v27, vcc, -1, v22
+; GFX9-NEXT: v_addc_co_u32_e32 v28, vcc, -1, v21, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v29, vcc, -1, v4, vcc
; GFX9-NEXT: v_mov_b32_e32 v12, 0
; GFX9-NEXT: v_mov_b32_e32 v18, 0
-; GFX9-NEXT: v_addc_co_u32_e32 v31, vcc, -1, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v30, vcc, -1, v5, vcc
; GFX9-NEXT: v_mov_b32_e32 v13, 0
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: v_mov_b32_e32 v19, 0
-; GFX9-NEXT: v_mov_b32_e32 v11, 0
+; GFX9-NEXT: v_mov_b32_e32 v9, 0
; GFX9-NEXT: .LBB0_3: ; %udiv-do-while
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_lshrrev_b32_e32 v32, 31, v15
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 31, v15
; GFX9-NEXT: v_lshlrev_b64 v[14:15], 1, v[14:15]
-; GFX9-NEXT: v_lshrrev_b32_e32 v33, 31, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 31, v7
; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 31, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 31, v11
; GFX9-NEXT: v_lshlrev_b64 v[16:17], 1, v[16:17]
-; GFX9-NEXT: v_or_b32_e32 v14, v14, v33
-; GFX9-NEXT: v_or3_b32 v6, v6, v10, v12
-; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, v28, v14
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v32
-; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v29, v15, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v30, v16, vcc
-; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[8:9]
-; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v31, v17, vcc
-; GFX9-NEXT: v_ashrrev_i32_e32 v10, 31, v10
-; GFX9-NEXT: v_or_b32_e32 v8, v18, v8
-; GFX9-NEXT: v_and_b32_e32 v18, v10, v23
-; GFX9-NEXT: v_or_b32_e32 v9, v19, v9
-; GFX9-NEXT: v_and_b32_e32 v19, v10, v22
+; GFX9-NEXT: v_or_b32_e32 v14, v14, v32
+; GFX9-NEXT: v_or3_b32 v6, v6, v8, v12
+; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v27, v14
+; GFX9-NEXT: v_or_b32_e32 v16, v16, v31
+; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, v28, v15, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, v29, v16, vcc
+; GFX9-NEXT: v_lshlrev_b64 v[10:11], 1, v[10:11]
+; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, v30, v17, vcc
+; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v8
+; GFX9-NEXT: v_or_b32_e32 v10, v18, v10
+; GFX9-NEXT: v_and_b32_e32 v18, v8, v22
+; GFX9-NEXT: v_or_b32_e32 v11, v19, v11
+; GFX9-NEXT: v_and_b32_e32 v19, v8, v21
; GFX9-NEXT: v_sub_co_u32_e32 v14, vcc, v14, v18
-; GFX9-NEXT: v_and_b32_e32 v32, v10, v4
+; GFX9-NEXT: v_and_b32_e32 v31, v8, v4
; GFX9-NEXT: v_subb_co_u32_e32 v15, vcc, v15, v19, vcc
-; GFX9-NEXT: v_and_b32_e32 v33, v10, v5
-; GFX9-NEXT: v_subb_co_u32_e32 v16, vcc, v16, v32, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v17, v33, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v24, vcc, -1, v24
+; GFX9-NEXT: v_and_b32_e32 v32, v8, v5
+; GFX9-NEXT: v_subb_co_u32_e32 v16, vcc, v16, v31, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v17, v32, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v23, vcc, -1, v23
+; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, -1, v24, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, -1, v25, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, -1, v26, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, -1, v27, vcc
-; GFX9-NEXT: v_or_b32_e32 v18, v24, v26
-; GFX9-NEXT: v_or_b32_e32 v19, v25, v27
+; GFX9-NEXT: v_or_b32_e32 v18, v23, v25
+; GFX9-NEXT: v_or_b32_e32 v19, v24, v26
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[18:19]
-; GFX9-NEXT: v_and_b32_e32 v10, 1, v10
-; GFX9-NEXT: v_mov_b32_e32 v19, v11
+; GFX9-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX9-NEXT: v_mov_b32_e32 v19, v9
; GFX9-NEXT: v_or3_b32 v7, v7, 0, v13
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: v_mov_b32_e32 v18, v10
+; GFX9-NEXT: v_mov_b32_e32 v18, v8
; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execnz .LBB0_3
; GFX9-NEXT: ; %bb.4: ; %Flow
@@ -193,29 +192,29 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: .LBB0_5: ; %Flow2
; GFX9-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX9-NEXT: v_lshlrev_b64 v[12:13], 1, v[6:7]
-; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[8:9]
-; GFX9-NEXT: v_lshrrev_b32_e32 v14, 31, v9
+; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[10:11]
+; GFX9-NEXT: v_lshrrev_b32_e32 v14, 31, v11
; GFX9-NEXT: v_or_b32_e32 v12, v12, v14
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v7
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v6
+; GFX9-NEXT: v_or_b32_e32 v10, v9, v7
+; GFX9-NEXT: v_or_b32_e32 v11, v8, v6
; GFX9-NEXT: .LBB0_6: ; %Flow3
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
-; GFX9-NEXT: v_mul_lo_u32 v17, v10, v5
-; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v23, v10, 0
+; GFX9-NEXT: v_mul_lo_u32 v17, v11, v5
+; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v22, v11, 0
; GFX9-NEXT: v_mov_b32_e32 v7, 0
-; GFX9-NEXT: v_mul_lo_u32 v16, v11, v4
-; GFX9-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v22, v10, v[6:7]
-; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v10, v4, 0
+; GFX9-NEXT: v_mul_lo_u32 v16, v10, v4
+; GFX9-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v21, v11, v[6:7]
+; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v11, v4, 0
; GFX9-NEXT: v_mov_b32_e32 v6, v14
-; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v23, v11, v[6:7]
+; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v22, v10, v[6:7]
; GFX9-NEXT: v_add3_u32 v9, v9, v17, v16
-; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v23, v[8:9]
-; GFX9-NEXT: v_mul_lo_u32 v4, v12, v22
-; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v15, v7
-; GFX9-NEXT: v_mul_lo_u32 v14, v13, v23
-; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, 0, vcc
-; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v22, v11, v[12:13]
-; GFX9-NEXT: v_add3_u32 v4, v14, v9, v4
+; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v22, v[8:9]
+; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v15, v7
+; GFX9-NEXT: v_mul_lo_u32 v4, v12, v21
+; GFX9-NEXT: v_addc_co_u32_e64 v12, s[4:5], 0, 0, vcc
+; GFX9-NEXT: v_mul_lo_u32 v13, v13, v22
+; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v21, v10, v[11:12]
+; GFX9-NEXT: v_add3_u32 v4, v13, v9, v4
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v10, v8
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v4, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v5
@@ -223,13 +222,13 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v7, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v20
-; GFX9-NEXT: v_xor_b32_e32 v1, v1, v21
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v20
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v20
; GFX9-NEXT: v_xor_b32_e32 v2, v2, v20
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v21, vcc
-; GFX9-NEXT: v_xor_b32_e32 v3, v3, v21
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v20, vcc
+; GFX9-NEXT: v_xor_b32_e32 v3, v3, v20
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v20, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v21, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v20, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-O0-LABEL: v_srem_i128_vv:
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
index fdb20f372ab8d..9531c95985a5a 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -405,15 +405,13 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) {
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
-; GCN-IR-NEXT: v_mov_b32_e32 v12, v10
-; GCN-IR-NEXT: v_mov_b32_e32 v13, v11
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v6, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
-; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v2
+; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[6:7], v2
@@ -424,12 +422,12 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) {
; GCN-IR-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
-; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[6:7], v14
-; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0
-; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc
+; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[6:7], v12
+; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
+; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_not_b32_e32 v4, v8
-; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, v4, v9
-; GCN-IR-NEXT: v_addc_u32_e64 v17, s[8:9], -1, 0, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, v4, v9
+; GCN-IR-NEXT: v_addc_u32_e64 v15, s[8:9], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
@@ -440,8 +438,8 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) {
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
-; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v14, v6
-; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v15, v7, vcc
+; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v6
+; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v7, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v8, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v4
; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
@@ -450,8 +448,8 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) {
; GCN-IR-NEXT: v_and_b32_e32 v8, v8, v0
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
-; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, 1, v16
-; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v14
+; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
@@ -467,7 +465,7 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) {
; GCN-IR-NEXT: .LBB1_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v11, v10
-; GCN-IR-NEXT: v_xor_b32_e32 v1, v13, v12
+; GCN-IR-NEXT: v_xor_b32_e32 v1, v11, v10
; GCN-IR-NEXT: v_xor_b32_e32 v3, v4, v0
; GCN-IR-NEXT: v_xor_b32_e32 v2, v5, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v3, v0
@@ -1325,12 +1323,12 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x)
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[2:3]
; GCN-IR-NEXT: .LBB10_5: ; %udiv-end
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[4:5]
-; GCN-IR-NEXT: s_sub_u32 s4, s6, s4
-; GCN-IR-NEXT: s_subb_u32 s5, s7, s5
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
+; GCN-IR-NEXT: s_sub_u32 s6, s6, s4
+; GCN-IR-NEXT: s_subb_u32 s7, s7, s4
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
+; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
%result = sdiv i64 24, %x
@@ -1466,7 +1464,6 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) {
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, 24, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
-; GCN-IR-NEXT: v_mov_b32_e32 v11, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
@@ -1483,11 +1480,11 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) {
; GCN-IR-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execz .LBB11_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
-; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
-; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
-; GCN-IR-NEXT: v_sub_i32_e32 v14, vcc, 58, v8
+; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, -1, v0
+; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, -1, v1, vcc
+; GCN-IR-NEXT: v_sub_i32_e32 v13, vcc, 58, v8
; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v6
-; GCN-IR-NEXT: v_subb_u32_e64 v15, s[8:9], 0, 0, vcc
+; GCN-IR-NEXT: v_subb_u32_e64 v14, s[8:9], 0, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
@@ -1498,8 +1495,8 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
-; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v6
-; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v7, vcc
+; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v11, v6
+; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v12, v7, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v8, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v4
; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
@@ -1508,8 +1505,8 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_and_b32_e32 v8, v8, v0
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
-; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v14
-; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v13, vcc, 1, v13
+; GCN-IR-NEXT: v_addc_u32_e32 v14, vcc, 0, v14, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
@@ -1525,9 +1522,9 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) {
; GCN-IR-NEXT: .LBB11_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v10
-; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v11
+; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v10
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
-; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v11, vcc
+; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v10, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 24, %x
ret i64 %result
@@ -1658,7 +1655,6 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
-; GCN-IR-NEXT: v_mov_b32_e32 v11, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
@@ -1676,11 +1672,11 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: s_xor_b64 s[4:5], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
-; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
-; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
-; GCN-IR-NEXT: v_sub_i32_e32 v14, vcc, 47, v8
+; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, -1, v0
+; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, -1, v1, vcc
+; GCN-IR-NEXT: v_sub_i32_e32 v13, vcc, 47, v8
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[8:9], v6
-; GCN-IR-NEXT: v_subb_u32_e64 v15, s[8:9], 0, 0, vcc
+; GCN-IR-NEXT: v_subb_u32_e64 v14, s[8:9], 0, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
@@ -1691,8 +1687,8 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
-; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v6
-; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v7, vcc
+; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v11, v6
+; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v12, v7, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v8, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v4
; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
@@ -1701,8 +1697,8 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_and_b32_e32 v8, v8, v0
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc
-; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v14
-; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v13, vcc, 1, v13
+; GCN-IR-NEXT: v_addc_u32_e32 v14, vcc, 0, v14, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
@@ -1718,9 +1714,9 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: .LBB12_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v10
-; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v11
+; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v10
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
-; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v11, vcc
+; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v10, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 32768, %x
ret i64 %result
@@ -1753,7 +1749,6 @@ define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[0:1]
-; GCN-IR-NEXT: v_mov_b32_e32 v9, v8
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
@@ -1774,9 +1769,9 @@ define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execz .LBB13_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
-; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 0xffffffcf, v6
+; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 0xffffffcf, v6
; GCN-IR-NEXT: v_lshr_b64 v[4:5], v[4:5], v7
-; GCN-IR-NEXT: v_addc_u32_e64 v11, s[8:9], 0, -1, vcc
+; GCN-IR-NEXT: v_addc_u32_e64 v10, s[8:9], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
@@ -1796,9 +1791,9 @@ define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_and_b32_e32 v6, 0x8000, v6
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GCN-IR-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10
+; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v9
; GCN-IR-NEXT: v_or_b32_e32 v1, v7, v1
-; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
+; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v7, v3
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v6, v2
@@ -1814,9 +1809,9 @@ define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: .LBB13_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v8
-; GCN-IR-NEXT: v_xor_b32_e32 v1, v3, v9
+; GCN-IR-NEXT: v_xor_b32_e32 v1, v3, v8
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
-; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc
+; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %x, 32768
ret i64 %result
diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole-reg-sequence.mir b/llvm/test/CodeGen/AMDGPU/sdwa-peephole-reg-sequence.mir
new file mode 100644
index 0000000000000..5e5e7216a351f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole-reg-sequence.mir
@@ -0,0 +1,114 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -mcpu=gfx900 -start-before si-fold-operands -o - %s | FileCheck --check-prefix=GCN %s
+
+--- |
+ define amdgpu_kernel void @sdwa_reg_sequence_add_shr_i32() {
+ ; GCN-LABEL: sdwa_reg_sequence_add_shr_i32:
+ ; GCN: ; %bb.0:
+ ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+ ; GCN-NEXT: flat_load_dword v2, v[2:3] glc
+ ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+ ; GCN-NEXT: buffer_wbinvl1_vol
+ ; GCN-NEXT: v_mov_b32_e32 v3, 0x7b
+ ; GCN-NEXT: v_add_co_u32_sdwa v2, vcc, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+ ; GCN-NEXT: flat_store_dword v[0:1], v2
+ ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+ ; GCN-NEXT: s_setpc_b64 s[30:31]
+ ret void
+ }
+
+ define amdgpu_kernel void @sdwa_reg_sequence_and_add_co() {
+ ; GCN-LABEL: sdwa_reg_sequence_and_add_co:
+ ; GCN: ; %bb.0:
+ ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+ ; GCN-NEXT: v_add_u32_e32 v1, 10, v0
+ ; GCN-NEXT: v_add_u32_e32 v0, 20, v0
+ ; GCN-NEXT: v_add_co_u32_sdwa v0, vcc, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+ ; GCN-NEXT: v_addc_co_u32_e64 v1, s[0:1], 0, 0, vcc
+ ; GCN-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
+ ; GCN-NEXT: s_endpgm
+ ret void
+ }
+
+ define amdgpu_kernel void @sdwa_reg_sequence_composed_subregs() {
+ ; GCN-LABEL: sdwa_reg_sequence_composed_subregs:
+ ; GCN: ; %bb.0:
+ ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+ ; GCN-NEXT: v_add_u32_e32 v0, 20, v2
+ ; GCN-NEXT: v_mov_b32_e32 v1, 0
+ ; GCN-NEXT: v_add_co_u32_sdwa v0, vcc, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+ ; GCN-NEXT: v_addc_co_u32_e64 v1, s[0:1], 0, 0, vcc
+ ; GCN-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
+ ; GCN-NEXT: s_endpgm
+ ret void
+ }
+...
+
+---
+name: sdwa_reg_sequence_add_shr_i32
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
+
+ %0:vreg_64 = COPY $vgpr0_vgpr1
+ %1:vreg_64 = COPY $vgpr2_vgpr3
+ %2:sreg_64 = COPY $sgpr30_sgpr31
+ %3:vgpr_32 = FLAT_LOAD_DWORD %1, 0, 0, implicit $exec, implicit $flat_scr
+ %4:sreg_32_xm0 = S_MOV_B32 123
+ %5:vgpr_32 = V_LSHRREV_B32_e64 16, %3, implicit $exec
+ %6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %7:vreg_64 = REG_SEQUENCE %5, %subreg.sub0, %6, %subreg.sub1
+ %8:vgpr_32 = V_ADD_CO_U32_e32 %4, killed %7.sub0, implicit-def $vcc, implicit $exec
+ FLAT_STORE_DWORD %0, %8, 0, 0, implicit $exec, implicit $flat_scr
+ $sgpr30_sgpr31 = COPY %2
+ S_SETPC_B64_return $sgpr30_sgpr31
+...
+
+---
+name: sdwa_reg_sequence_and_add_co
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ %0:vgpr_32 = COPY $vgpr0
+ %1:vgpr_32 = V_ADD_U32_e64 %0, 10, 0, implicit $exec
+ %2:vgpr_32 = V_ADD_U32_e64 %0, 20, 0, implicit $exec
+ %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %4:vreg_64 = REG_SEQUENCE %1, %subreg.sub0, %3, %subreg.sub1
+ %5:sreg_32 = S_MOV_B32 255
+ %6:vgpr_32 = V_AND_B32_e64 killed %2, killed %5, implicit $exec
+ %7:vreg_64 = REG_SEQUENCE %6, %subreg.sub0, %3, %subreg.sub1
+ %8:vgpr_32, %9:sreg_64_xexec = V_ADD_CO_U32_e64 %4.sub0, %7.sub0, 0, implicit $exec
+ %10:vgpr_32, dead %11:sreg_64_xexec = V_ADDC_U32_e64 0, 0, killed %9, 0, implicit $exec
+ %12:vreg_64 = REG_SEQUENCE %8, %subreg.sub0, %10, %subreg.sub1
+ %13:sreg_64 = IMPLICIT_DEF
+ %14:vreg_64 = COPY %13
+ GLOBAL_STORE_DWORDX2 killed %14, killed %12, 0, 0, implicit $exec
+ S_ENDPGM 0
+...
+
+---
+name: sdwa_reg_sequence_composed_subregs
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1_vgpr2
+
+ %0:vreg_64 = COPY $vgpr1_vgpr2
+ %1:vgpr_32 = V_ADD_U32_e64 %0.sub0, 10, 0, implicit $exec
+ %2:vgpr_32 = V_ADD_U32_e64 %0.sub1, 20, 0, implicit $exec
+ %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %4:vreg_64 = REG_SEQUENCE %1, %subreg.sub0, %3, %subreg.sub1
+ %5:vreg_64 = REG_SEQUENCE %0.sub0, %subreg.sub0, %4.sub1, %subreg.sub1
+ %6:sreg_32 = S_MOV_B32 255
+ %7:vgpr_32 = V_AND_B32_e64 killed %2, killed %6, implicit $exec
+ %8:vreg_64 = REG_SEQUENCE %7, %subreg.sub0, %3, %subreg.sub1
+ %9:vgpr_32, %10:sreg_64_xexec = V_ADD_CO_U32_e64 %5.sub1, %8.sub0, 0, implicit $exec
+ %11:vgpr_32, dead %12:sreg_64_xexec = V_ADDC_U32_e64 0, 0, killed %10, 0, implicit $exec
+ %13:vreg_64 = REG_SEQUENCE %9, %subreg.sub0, %11, %subreg.sub1
+ %15:vreg_64 = COPY %13
+ GLOBAL_STORE_DWORDX2 killed %15, killed %13, 0, 0, implicit $exec
+ S_ENDPGM 0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.gfx942.mir b/llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.gfx942.mir
index 98b179fb5f2a8..bd8fdb73d9b60 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.gfx942.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.gfx942.mir
@@ -41,7 +41,6 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1107312640
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1006632960
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
; CHECK-NEXT: [[V_PK_ADD_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_ADD_F16 8, [[COPY]], 4, 15360, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_F16_]]
%0:vgpr_32 = COPY $vgpr0
@@ -98,7 +97,6 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1006632960
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
; CHECK-NEXT: [[V_PK_ADD_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_ADD_F16 8, [[COPY]], 8, -16, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_F16_]]
%0:vgpr_32 = COPY $vgpr0
@@ -122,7 +120,6 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15360
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1006632960
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
; CHECK-NEXT: [[V_PK_ADD_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_ADD_F16 8, [[COPY]], 8, 15360, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_F16_]]
%0:vgpr_32 = COPY $vgpr0
@@ -146,7 +143,6 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1006632960
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 15360
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
; CHECK-NEXT: [[V_PK_ADD_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_ADD_F16 8, [[COPY]], 4, 15360, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_F16_]]
%0:vgpr_32 = COPY $vgpr0
@@ -169,8 +165,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4755871576254054400
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B]].sub0, %subreg.sub0, [[S_MOV_B]].sub1, %subreg.sub1
- ; CHECK-NEXT: [[V_PK_ADD_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_ADD_F16 8, [[COPY]], 8, [[REG_SEQUENCE]].sub1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[V_PK_ADD_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_ADD_F16 8, [[COPY]], 8, [[S_MOV_B]].sub1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_F16_]]
%0:vgpr_32 = COPY $vgpr0
%1:sreg_64 = S_MOV_B64_IMM_PSEUDO 4755871576254054400
@@ -191,7 +186,6 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 65971704299520
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B]].sub0, %subreg.sub0, [[S_MOV_B]].sub1, %subreg.sub1
; CHECK-NEXT: [[V_PK_ADD_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_ADD_F16 8, [[COPY]], 8, 15360, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_F16_]]
%0:vgpr_32 = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir b/llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
index 1742349673d7c..0bf7dfa84646c 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
@@ -114,7 +114,6 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 8
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B64_]].sub1, %subreg.sub0, [[S_MOV_B64_]].sub0, %subreg.sub1
; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, 0, implicit-def $scc
; CHECK-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY]].sub1, 8, implicit-def $scc, implicit $scc
; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADDC_U32_]]
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index 02d2e6c1473ab..e884f0e65cb67 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -387,7 +387,6 @@ define i64 @v_test_srem(i64 %x, i64 %y) {
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
-; GCN-IR-NEXT: v_mov_b32_e32 v13, v12
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
@@ -405,12 +404,12 @@ define i64 @v_test_srem(i64 %x, i64 %y) {
; GCN-IR-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
-; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2
-; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v13, vcc, -1, v2
+; GCN-IR-NEXT: v_addc_u32_e32 v14, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_not_b32_e32 v6, v10
-; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, v6, v11
+; GCN-IR-NEXT: v_add_i32_e32 v15, vcc, v6, v11
; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v8
-; GCN-IR-NEXT: v_addc_u32_e64 v17, s[8:9], -1, 0, vcc
+; GCN-IR-NEXT: v_addc_u32_e64 v16, s[8:9], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
@@ -421,8 +420,8 @@ define i64 @v_test_srem(i64 %x, i64 %y) {
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
-; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v8
-; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v9, vcc
+; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v13, v8
+; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v14, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v10, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v6
; GCN-IR-NEXT: v_or_b32_e32 v5, v11, v5
@@ -431,8 +430,8 @@ define i64 @v_test_srem(i64 %x, i64 %y) {
; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v2
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v8, v10
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v9, v11, vcc
-; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, 1, v16
-; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v15, vcc, 1, v15
+; GCN-IR-NEXT: v_addc_u32_e32 v16, vcc, 0, v16, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v11, v7
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v6
@@ -456,9 +455,9 @@ define i64 @v_test_srem(i64 %x, i64 %y) {
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v12
-; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v13
+; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v12
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v12
-; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v13, vcc
+; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v12, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = srem i64 %x, %y
ret i64 %result
@@ -1187,12 +1186,12 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-NEXT: s_sub_u32 s6, s6, s8
; GCN-IR-NEXT: s_subb_u32 s7, s7, s11
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
-; GCN-IR-NEXT: s_sub_u32 s4, s6, s4
-; GCN-IR-NEXT: s_subb_u32 s5, s7, s5
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
+; GCN-IR-NEXT: s_sub_u32 s6, s6, s4
+; GCN-IR-NEXT: s_subb_u32 s7, s7, s4
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
+; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 31
@@ -1906,7 +1905,6 @@ define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
-; GCN-IR-NEXT: v_mov_b32_e32 v11, v10
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
@@ -1927,9 +1925,9 @@ define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: s_xor_b64 s[4:5], exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execz .LBB13_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
-; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 0xffffffcf, v8
+; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 0xffffffcf, v8
; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[0:1], v6
-; GCN-IR-NEXT: v_addc_u32_e64 v13, s[8:9], 0, -1, vcc
+; GCN-IR-NEXT: v_addc_u32_e64 v12, s[8:9], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
@@ -1949,9 +1947,9 @@ define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_and_b32_e32 v8, 0x8000, v8
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GCN-IR-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
-; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v12
+; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 1, v11
; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
-; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
+; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, 0, v12, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
@@ -1970,9 +1968,9 @@ define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v10
-; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v11
+; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v10
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
-; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v11, vcc
+; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v10, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = srem i64 %x, 32768
ret i64 %result
diff --git a/llvm/test/CodeGen/AMDGPU/true16-fold.mir b/llvm/test/CodeGen/AMDGPU/true16-fold.mir
index 6706de13bb89b..f6659ae8d02c5 100644
--- a/llvm/test/CodeGen/AMDGPU/true16-fold.mir
+++ b/llvm/test/CodeGen/AMDGPU/true16-fold.mir
@@ -223,7 +223,6 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, -1, 0, implicit $exec
; CHECK-NEXT: [[V_MOV_B16_t16_e64_1:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, -1, 0, implicit $exec
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_MOV_B16_t16_e64_]], %subreg.lo16, [[V_MOV_B16_t16_e64_1]], %subreg.hi16
; CHECK-NEXT: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MAX_F32_e64 0, -1, 0, -1, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_MAX_F32_e64_]]
; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll b/llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
index a69dba90a9640..4dcd56b32d490 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
@@ -6,28 +6,29 @@ define void @vgpr_descriptor_waterfall_loop_idom_update(ptr %arg) #0 {
; GCN-LABEL: vgpr_descriptor_waterfall_loop_idom_update:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_add_co_u32 v6, vcc_lo, v0, 8
-; GCN-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
+; GCN-NEXT: v_add_co_u32 v2, vcc_lo, v0, 8
+; GCN-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
; GCN-NEXT: .LBB0_1: ; %bb0
; GCN-NEXT: ; =>This Loop Header: Depth=1
; GCN-NEXT: ; Child Loop BB0_2 Depth 2
; GCN-NEXT: s_clause 0x1
-; GCN-NEXT: flat_load_dwordx2 v[4:5], v[6:7]
-; GCN-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
+; GCN-NEXT: flat_load_dwordx2 v[4:5], v[2:3]
+; GCN-NEXT: flat_load_dwordx2 v[6:7], v[0:1]
; GCN-NEXT: s_mov_b32 s5, exec_lo
; GCN-NEXT: .LBB0_2: ; Parent Loop BB0_1 Depth=1
; GCN-NEXT: ; => This Inner Loop Header: Depth=2
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s8, v2
-; GCN-NEXT: v_readfirstlane_b32 s9, v3
+; GCN-NEXT: v_readfirstlane_b32 s8, v6
+; GCN-NEXT: v_readfirstlane_b32 s9, v7
; GCN-NEXT: v_readfirstlane_b32 s10, v4
; GCN-NEXT: v_readfirstlane_b32 s11, v5
-; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[2:3]
+; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[6:7]
; GCN-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[4:5]
; GCN-NEXT: s_and_b32 s4, vcc_lo, s4
; GCN-NEXT: s_and_saveexec_b32 s4, s4
; GCN-NEXT: buffer_store_dword v0, v0, s[8:11], 0 offen
-; GCN-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
+; GCN-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GCN-NEXT: ; implicit-def: $vgpr4_vgpr5
; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GCN-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GCN-NEXT: s_cbranch_execnz .LBB0_2
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll b/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
index 3bc67562012e5..fee14f87d969d 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
@@ -575,29 +575,29 @@ define protected amdgpu_kernel void @nested_waterfalls(ptr addrspace(1) %tex.coe
; SI-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR killed %11, killed [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s64) from %ir.idx, addrspace 1)
; SI-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[GLOBAL_LOAD_DWORDX2_SADDR]], 16, 0, implicit $exec :: (invariant load (s128) from %ir.3 + 16, addrspace 4)
; SI-NEXT: [[GLOBAL_LOAD_DWORDX4_1:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[GLOBAL_LOAD_DWORDX2_SADDR]], 0, 0, implicit $exec :: (invariant load (s128) from %ir.3, align 32, addrspace 4)
- ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_256 = REG_SEQUENCE killed [[GLOBAL_LOAD_DWORDX4_1]].sub0, %subreg.sub0, [[GLOBAL_LOAD_DWORDX4_1]].sub1, %subreg.sub1, [[GLOBAL_LOAD_DWORDX4_1]].sub2, %subreg.sub2, [[GLOBAL_LOAD_DWORDX4_1]].sub3, %subreg.sub3, killed [[GLOBAL_LOAD_DWORDX4_]].sub0, %subreg.sub4, [[GLOBAL_LOAD_DWORDX4_]].sub1, %subreg.sub5, [[GLOBAL_LOAD_DWORDX4_]].sub2, %subreg.sub6, [[GLOBAL_LOAD_DWORDX4_]].sub3, %subreg.sub7
+ ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[GLOBAL_LOAD_DWORDX4_1]].sub0, %subreg.sub0, [[GLOBAL_LOAD_DWORDX4_1]].sub1, %subreg.sub1, [[GLOBAL_LOAD_DWORDX4_1]].sub2, %subreg.sub2, [[GLOBAL_LOAD_DWORDX4_1]].sub3, %subreg.sub3, [[GLOBAL_LOAD_DWORDX4_]].sub0, %subreg.sub4, [[GLOBAL_LOAD_DWORDX4_]].sub1, %subreg.sub5, [[GLOBAL_LOAD_DWORDX4_]].sub2, %subreg.sub6, [[GLOBAL_LOAD_DWORDX4_]].sub3, %subreg.sub7
; SI-NEXT: [[GLOBAL_LOAD_DWORDX4_2:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 killed [[GLOBAL_LOAD_DWORDX2_SADDR]], 48, 0, implicit $exec :: (invariant load (s128) from %ir.add.ptr.i, addrspace 4)
; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
; SI-NEXT: {{ $}}
; SI-NEXT: bb.2:
; SI-NEXT: successors: %bb.3(0x80000000)
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub0, implicit $exec
- ; SI-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub1, implicit $exec
+ ; SI-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_1]].sub0, implicit $exec
+ ; SI-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_1]].sub1, implicit $exec
; SI-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
; SI-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE1]], [[REG_SEQUENCE]].sub0_sub1, implicit $exec
- ; SI-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub2, implicit $exec
- ; SI-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub3, implicit $exec
+ ; SI-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_1]].sub2, implicit $exec
+ ; SI-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_1]].sub3, implicit $exec
; SI-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
; SI-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE2]], [[REG_SEQUENCE]].sub2_sub3, implicit $exec
; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_EQ_U64_e64_]], killed [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
- ; SI-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub4, implicit $exec
- ; SI-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub5, implicit $exec
+ ; SI-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec
+ ; SI-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_]].sub1, implicit $exec
; SI-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_4]], %subreg.sub0, [[V_READFIRSTLANE_B32_5]], %subreg.sub1
; SI-NEXT: [[V_CMP_EQ_U64_e64_2:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE3]], [[REG_SEQUENCE]].sub4_sub5, implicit $exec
; SI-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[S_AND_B32_]], killed [[V_CMP_EQ_U64_e64_2]], implicit-def dead $scc
- ; SI-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub6, implicit $exec
- ; SI-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub7, implicit $exec
+ ; SI-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_]].sub2, implicit $exec
+ ; SI-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_]].sub3, implicit $exec
; SI-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_6]], %subreg.sub0, [[V_READFIRSTLANE_B32_7]], %subreg.sub1
; SI-NEXT: [[V_CMP_EQ_U64_e64_3:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE4]], [[REG_SEQUENCE]].sub6_sub7, implicit $exec
; SI-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[S_AND_B32_1]], killed [[V_CMP_EQ_U64_e64_3]], implicit-def dead $scc
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll b/llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
index b46f5f5640b66..f5476d317e1a2 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
@@ -186,7 +186,7 @@ define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_fun
; SI-NEXT: s_mov_b64 s[2:3], s[14:15]
; SI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; SI-NEXT: v_mov_b32_e32 v1, v0
-; SI-NEXT: ; implicit-def: $vgpr4_vgpr5
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8
; SI-NEXT: s_cbranch_execnz .LBB3_2
@@ -208,7 +208,7 @@ define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_fun
; SI-NEXT: s_mov_b64 s[2:3], s[14:15]
; SI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; SI-NEXT: v_mov_b32_e32 v1, v0
-; SI-NEXT: ; implicit-def: $vgpr2_vgpr3
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8
; SI-NEXT: s_cbranch_execnz .LBB3_6
@@ -263,7 +263,7 @@ define amdgpu_ps float @loop_with_use(i32 %z, float %v, i32 inreg %bound, ptr %e
; SI-NEXT: s_mov_b64 s[0:1], s[12:13]
; SI-NEXT: s_mov_b64 s[2:3], s[14:15]
; SI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; SI-NEXT: ; implicit-def: $vgpr4_vgpr5
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8
; SI-NEXT: s_cbranch_execnz .LBB4_2
; SI-NEXT: ; %bb.3:
@@ -283,7 +283,7 @@ define amdgpu_ps float @loop_with_use(i32 %z, float %v, i32 inreg %bound, ptr %e
; SI-NEXT: s_mov_b64 s[0:1], s[12:13]
; SI-NEXT: s_mov_b64 s[2:3], s[14:15]
; SI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; SI-NEXT: ; implicit-def: $vgpr2_vgpr3
+; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8
; SI-NEXT: s_cbranch_execnz .LBB4_6
; SI-NEXT: ; %bb.7:
diff --git a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
index 20789232b1f25..e10ffe5433906 100644
--- a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
+++ b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
@@ -6,14 +6,14 @@ define amdgpu_kernel void @v3i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; GFX942-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 2, v1
; GFX942-NEXT: v_mov_b32_e32 v2, 8
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dword v3, v1, s[0:1]
+; GFX942-NEXT: global_load_dword v3, v0, s[0:1]
; GFX942-NEXT: s_mov_b32 s4, 0xff0000
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v1
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: v_lshrrev_b32_sdwa v4, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX942-NEXT: s_nop 0
@@ -23,18 +23,18 @@ define amdgpu_kernel void @v3i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB0_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX942-NEXT: global_load_dword v0, v0, s[2:3]
+; GFX942-NEXT: v_lshlrev_b32_e32 v1, 2, v1
+; GFX942-NEXT: global_load_dword v1, v1, s[2:3]
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: v_lshrrev_b32_sdwa v2, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX942-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_or_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX942-NEXT: v_and_or_b32 v3, v0, s4, v2
+; GFX942-NEXT: v_and_or_b32 v3, v1, s4, v2
; GFX942-NEXT: .LBB0_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX942-NEXT: global_store_byte_d16_hi v1, v3, s[6:7] offset:2
-; GFX942-NEXT: global_store_short v1, v3, s[6:7]
+; GFX942-NEXT: global_store_byte_d16_hi v0, v3, s[6:7] offset:2
+; GFX942-NEXT: global_store_short v0, v3, s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -58,21 +58,21 @@ define amdgpu_kernel void @v4i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 2, v0
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
+; GFX942-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 2, v1
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v1
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dword v2, v1, s[0:1]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: global_load_dword v2, v0, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB1_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX942-NEXT: global_load_dword v2, v0, s[2:3]
+; GFX942-NEXT: v_lshlrev_b32_e32 v1, 2, v1
+; GFX942-NEXT: global_load_dword v2, v1, s[2:3]
; GFX942-NEXT: .LBB1_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: global_store_dword v1, v2, s[6:7]
+; GFX942-NEXT: global_store_dword v0, v2, s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -96,25 +96,25 @@ define amdgpu_kernel void @v5i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX942-NEXT: v_and_b32_e32 v2, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v2
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_and_b32_e32 v3, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v3
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1]
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v2
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v3
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB2_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v2
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v3
; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX942-NEXT: .LBB2_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX942-NEXT: global_store_byte v3, v1, s[6:7] offset:4
-; GFX942-NEXT: global_store_dword v3, v0, s[6:7]
+; GFX942-NEXT: global_store_byte v2, v1, s[6:7] offset:4
+; GFX942-NEXT: global_store_dword v2, v0, s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -138,21 +138,21 @@ define amdgpu_kernel void @v8i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
+; GFX942-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v1
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v1
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dwordx2 v[2:3], v1, s[0:1]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: global_load_dwordx2 v[2:3], v0, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB3_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v0
-; GFX942-NEXT: global_load_dwordx2 v[2:3], v0, s[2:3]
+; GFX942-NEXT: v_lshlrev_b32_e32 v1, 3, v1
+; GFX942-NEXT: global_load_dwordx2 v[2:3], v1, s[2:3]
; GFX942-NEXT: .LBB3_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: global_store_dwordx2 v1, v[2:3], s[6:7]
+; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -176,21 +176,21 @@ define amdgpu_kernel void @v16i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 4, v0
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
+; GFX942-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 4, v1
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v1
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dwordx4 v[2:5], v1, s[0:1]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: global_load_dwordx4 v[2:5], v0, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB4_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 4, v0
-; GFX942-NEXT: global_load_dwordx4 v[2:5], v0, s[2:3]
+; GFX942-NEXT: v_lshlrev_b32_e32 v1, 4, v1
+; GFX942-NEXT: global_load_dwordx4 v[2:5], v1, s[2:3]
; GFX942-NEXT: .LBB4_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: global_store_dwordx4 v1, v[2:5], s[6:7]
+; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -214,25 +214,25 @@ define amdgpu_kernel void @v32i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 5, v0
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
+; GFX942-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 5, v1
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v1
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dwordx4 v[6:9], v1, s[0:1] offset:16
-; GFX942-NEXT: global_load_dwordx4 v[2:5], v1, s[0:1]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: global_load_dwordx4 v[6:9], v0, s[0:1] offset:16
+; GFX942-NEXT: global_load_dwordx4 v[2:5], v0, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB5_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX942-NEXT: global_load_dwordx4 v[6:9], v0, s[2:3] offset:16
-; GFX942-NEXT: global_load_dwordx4 v[2:5], v0, s[2:3]
+; GFX942-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX942-NEXT: global_load_dwordx4 v[6:9], v1, s[2:3] offset:16
+; GFX942-NEXT: global_load_dwordx4 v[2:5], v1, s[2:3]
; GFX942-NEXT: .LBB5_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(1)
-; GFX942-NEXT: global_store_dwordx4 v1, v[6:9], s[6:7] offset:16
+; GFX942-NEXT: global_store_dwordx4 v0, v[6:9], s[6:7] offset:16
; GFX942-NEXT: s_waitcnt vmcnt(1)
-; GFX942-NEXT: global_store_dwordx4 v1, v[2:5], s[6:7]
+; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -256,73 +256,73 @@ define amdgpu_kernel void @v256i8_liveout(ptr addrspace(1) %src1, ptr addrspace(
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
+; GFX942-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v1
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v1
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dwordx4 v[30:33], v1, s[0:1] offset:240
-; GFX942-NEXT: global_load_dwordx4 v[26:29], v1, s[0:1] offset:224
-; GFX942-NEXT: global_load_dwordx4 v[22:25], v1, s[0:1] offset:208
-; GFX942-NEXT: global_load_dwordx4 v[18:21], v1, s[0:1] offset:192
-; GFX942-NEXT: global_load_dwordx4 v[14:17], v1, s[0:1] offset:176
-; GFX942-NEXT: global_load_dwordx4 v[10:13], v1, s[0:1] offset:160
-; GFX942-NEXT: global_load_dwordx4 v[6:9], v1, s[0:1] offset:144
-; GFX942-NEXT: global_load_dwordx4 v[2:5], v1, s[0:1] offset:128
-; GFX942-NEXT: global_load_dwordx4 a[0:3], v1, s[0:1] offset:112
-; GFX942-NEXT: global_load_dwordx4 v[58:61], v1, s[0:1] offset:96
-; GFX942-NEXT: global_load_dwordx4 v[54:57], v1, s[0:1] offset:80
-; GFX942-NEXT: global_load_dwordx4 v[50:53], v1, s[0:1] offset:64
-; GFX942-NEXT: global_load_dwordx4 v[46:49], v1, s[0:1] offset:48
-; GFX942-NEXT: global_load_dwordx4 v[42:45], v1, s[0:1] offset:32
-; GFX942-NEXT: global_load_dwordx4 v[38:41], v1, s[0:1] offset:16
-; GFX942-NEXT: global_load_dwordx4 v[34:37], v1, s[0:1]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: global_load_dwordx4 v[30:33], v0, s[0:1] offset:240
+; GFX942-NEXT: global_load_dwordx4 v[26:29], v0, s[0:1] offset:224
+; GFX942-NEXT: global_load_dwordx4 v[22:25], v0, s[0:1] offset:208
+; GFX942-NEXT: global_load_dwordx4 v[18:21], v0, s[0:1] offset:192
+; GFX942-NEXT: global_load_dwordx4 v[14:17], v0, s[0:1] offset:176
+; GFX942-NEXT: global_load_dwordx4 v[10:13], v0, s[0:1] offset:160
+; GFX942-NEXT: global_load_dwordx4 v[6:9], v0, s[0:1] offset:144
+; GFX942-NEXT: global_load_dwordx4 v[2:5], v0, s[0:1] offset:128
+; GFX942-NEXT: global_load_dwordx4 a[0:3], v0, s[0:1] offset:112
+; GFX942-NEXT: global_load_dwordx4 v[58:61], v0, s[0:1] offset:96
+; GFX942-NEXT: global_load_dwordx4 v[54:57], v0, s[0:1] offset:80
+; GFX942-NEXT: global_load_dwordx4 v[50:53], v0, s[0:1] offset:64
+; GFX942-NEXT: global_load_dwordx4 v[46:49], v0, s[0:1] offset:48
+; GFX942-NEXT: global_load_dwordx4 v[42:45], v0, s[0:1] offset:32
+; GFX942-NEXT: global_load_dwordx4 v[38:41], v0, s[0:1] offset:16
+; GFX942-NEXT: global_load_dwordx4 v[34:37], v0, s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB6_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v0
-; GFX942-NEXT: global_load_dwordx4 v[30:33], v0, s[2:3] offset:240
-; GFX942-NEXT: global_load_dwordx4 v[26:29], v0, s[2:3] offset:224
-; GFX942-NEXT: global_load_dwordx4 v[22:25], v0, s[2:3] offset:208
-; GFX942-NEXT: global_load_dwordx4 v[18:21], v0, s[2:3] offset:192
-; GFX942-NEXT: global_load_dwordx4 v[14:17], v0, s[2:3] offset:176
-; GFX942-NEXT: global_load_dwordx4 v[10:13], v0, s[2:3] offset:160
-; GFX942-NEXT: global_load_dwordx4 v[6:9], v0, s[2:3] offset:144
-; GFX942-NEXT: global_load_dwordx4 v[2:5], v0, s[2:3] offset:128
-; GFX942-NEXT: global_load_dwordx4 a[0:3], v0, s[2:3] offset:112
-; GFX942-NEXT: global_load_dwordx4 v[58:61], v0, s[2:3] offset:96
-; GFX942-NEXT: global_load_dwordx4 v[54:57], v0, s[2:3] offset:80
-; GFX942-NEXT: global_load_dwordx4 v[50:53], v0, s[2:3] offset:64
-; GFX942-NEXT: global_load_dwordx4 v[46:49], v0, s[2:3] offset:48
-; GFX942-NEXT: global_load_dwordx4 v[42:45], v0, s[2:3] offset:32
-; GFX942-NEXT: global_load_dwordx4 v[38:41], v0, s[2:3] offset:16
-; GFX942-NEXT: global_load_dwordx4 v[34:37], v0, s[2:3]
+; GFX942-NEXT: v_lshlrev_b32_e32 v1, 3, v1
+; GFX942-NEXT: global_load_dwordx4 v[30:33], v1, s[2:3] offset:240
+; GFX942-NEXT: global_load_dwordx4 v[26:29], v1, s[2:3] offset:224
+; GFX942-NEXT: global_load_dwordx4 v[22:25], v1, s[2:3] offset:208
+; GFX942-NEXT: global_load_dwordx4 v[18:21], v1, s[2:3] offset:192
+; GFX942-NEXT: global_load_dwordx4 v[14:17], v1, s[2:3] offset:176
+; GFX942-NEXT: global_load_dwordx4 v[10:13], v1, s[2:3] offset:160
+; GFX942-NEXT: global_load_dwordx4 v[6:9], v1, s[2:3] offset:144
+; GFX942-NEXT: global_load_dwordx4 v[2:5], v1, s[2:3] offset:128
+; GFX942-NEXT: global_load_dwordx4 a[0:3], v1, s[2:3] offset:112
+; GFX942-NEXT: global_load_dwordx4 v[58:61], v1, s[2:3] offset:96
+; GFX942-NEXT: global_load_dwordx4 v[54:57], v1, s[2:3] offset:80
+; GFX942-NEXT: global_load_dwordx4 v[50:53], v1, s[2:3] offset:64
+; GFX942-NEXT: global_load_dwordx4 v[46:49], v1, s[2:3] offset:48
+; GFX942-NEXT: global_load_dwordx4 v[42:45], v1, s[2:3] offset:32
+; GFX942-NEXT: global_load_dwordx4 v[38:41], v1, s[2:3] offset:16
+; GFX942-NEXT: global_load_dwordx4 v[34:37], v1, s[2:3]
; GFX942-NEXT: .LBB6_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, a[0:3], s[6:7] offset:112
+; GFX942-NEXT: global_store_dwordx4 v0, a[0:3], s[6:7] offset:112
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[58:61], s[6:7] offset:96
+; GFX942-NEXT: global_store_dwordx4 v0, v[58:61], s[6:7] offset:96
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[54:57], s[6:7] offset:80
+; GFX942-NEXT: global_store_dwordx4 v0, v[54:57], s[6:7] offset:80
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[50:53], s[6:7] offset:64
+; GFX942-NEXT: global_store_dwordx4 v0, v[50:53], s[6:7] offset:64
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[46:49], s[6:7] offset:48
+; GFX942-NEXT: global_store_dwordx4 v0, v[46:49], s[6:7] offset:48
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[42:45], s[6:7] offset:32
+; GFX942-NEXT: global_store_dwordx4 v0, v[42:45], s[6:7] offset:32
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[38:41], s[6:7] offset:16
+; GFX942-NEXT: global_store_dwordx4 v0, v[38:41], s[6:7] offset:16
; GFX942-NEXT: s_waitcnt vmcnt(7)
-; GFX942-NEXT: global_store_dwordx4 v1, v[34:37], s[6:7]
-; GFX942-NEXT: global_store_dwordx4 v1, v[30:33], s[6:7] offset:240
-; GFX942-NEXT: global_store_dwordx4 v1, v[26:29], s[6:7] offset:224
-; GFX942-NEXT: global_store_dwordx4 v1, v[22:25], s[6:7] offset:208
-; GFX942-NEXT: global_store_dwordx4 v1, v[18:21], s[6:7] offset:192
-; GFX942-NEXT: global_store_dwordx4 v1, v[14:17], s[6:7] offset:176
-; GFX942-NEXT: global_store_dwordx4 v1, v[10:13], s[6:7] offset:160
-; GFX942-NEXT: global_store_dwordx4 v1, v[6:9], s[6:7] offset:144
-; GFX942-NEXT: global_store_dwordx4 v1, v[2:5], s[6:7] offset:128
+; GFX942-NEXT: global_store_dwordx4 v0, v[34:37], s[6:7]
+; GFX942-NEXT: global_store_dwordx4 v0, v[30:33], s[6:7] offset:240
+; GFX942-NEXT: global_store_dwordx4 v0, v[26:29], s[6:7] offset:224
+; GFX942-NEXT: global_store_dwordx4 v0, v[22:25], s[6:7] offset:208
+; GFX942-NEXT: global_store_dwordx4 v0, v[18:21], s[6:7] offset:192
+; GFX942-NEXT: global_store_dwordx4 v0, v[14:17], s[6:7] offset:176
+; GFX942-NEXT: global_store_dwordx4 v0, v[10:13], s[6:7] offset:160
+; GFX942-NEXT: global_store_dwordx4 v0, v[6:9], s[6:7] offset:144
+; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[6:7] offset:128
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -516,80 +516,80 @@ define amdgpu_kernel void @v8i8_phi_const(ptr addrspace(1) %src1, ptr addrspace(
; GFX942-LABEL: v8i8_phi_const:
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; GFX942-NEXT: v_and_b32_e32 v4, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v4
-; GFX942-NEXT: v_cmp_lt_u32_e64 s[0:1], 14, v4
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v4
+; GFX942-NEXT: v_and_b32_e32 v16, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v16
+; GFX942-NEXT: v_cmp_lt_u32_e64 s[0:1], 14, v16
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v16
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[8:9]
; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr10
; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: ; implicit-def: $vgpr12
; GFX942-NEXT: ; implicit-def: $vgpr13
; GFX942-NEXT: ; implicit-def: $vgpr14
; GFX942-NEXT: ; implicit-def: $vgpr15
-; GFX942-NEXT: ; implicit-def: $vgpr16
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: v_lshrrev_b32_e32 v5, 24, v1
-; GFX942-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX942-NEXT: v_lshrrev_b32_e32 v7, 8, v1
-; GFX942-NEXT: v_lshrrev_b32_e32 v8, 24, v0
-; GFX942-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX942-NEXT: v_lshrrev_b32_e32 v10, 8, v0
+; GFX942-NEXT: v_lshrrev_b32_e32 v4, 24, v1
+; GFX942-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX942-NEXT: v_lshrrev_b32_e32 v6, 8, v1
+; GFX942-NEXT: v_lshrrev_b32_e32 v7, 24, v0
+; GFX942-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX942-NEXT: v_lshrrev_b32_e32 v9, 8, v0
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB10_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v4
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v16
; GFX942-NEXT: global_load_dwordx2 v[2:3], v0, s[10:11]
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 7, v4
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 7, v16
; GFX942-NEXT: s_andn2_b64 s[0:1], s[0:1], exec
; GFX942-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX942-NEXT: v_mov_b32_e32 v5, 8
-; GFX942-NEXT: v_mov_b32_e32 v6, 7
-; GFX942-NEXT: v_mov_b32_e32 v7, 6
+; GFX942-NEXT: v_mov_b32_e32 v4, 8
+; GFX942-NEXT: v_mov_b32_e32 v5, 7
+; GFX942-NEXT: v_mov_b32_e32 v6, 6
; GFX942-NEXT: v_mov_b32_e32 v1, 5
-; GFX942-NEXT: v_mov_b32_e32 v8, 4
-; GFX942-NEXT: v_mov_b32_e32 v9, 3
-; GFX942-NEXT: v_mov_b32_e32 v10, 2
+; GFX942-NEXT: v_mov_b32_e32 v7, 4
+; GFX942-NEXT: v_mov_b32_e32 v8, 3
+; GFX942-NEXT: v_mov_b32_e32 v9, 2
; GFX942-NEXT: v_mov_b32_e32 v0, 1
; GFX942-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: v_lshrrev_b32_e32 v16, 24, v3
-; GFX942-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GFX942-NEXT: v_lshrrev_b32_e32 v14, 8, v3
-; GFX942-NEXT: v_lshrrev_b32_e32 v13, 24, v2
-; GFX942-NEXT: v_lshrrev_b32_e32 v12, 16, v2
-; GFX942-NEXT: v_lshrrev_b32_e32 v11, 8, v2
+; GFX942-NEXT: v_lshrrev_b32_e32 v15, 24, v3
+; GFX942-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; GFX942-NEXT: v_lshrrev_b32_e32 v13, 8, v3
+; GFX942-NEXT: v_lshrrev_b32_e32 v12, 24, v2
+; GFX942-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX942-NEXT: v_lshrrev_b32_e32 v10, 8, v2
; GFX942-NEXT: .LBB10_2: ; %Flow
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], s[0:1]
; GFX942-NEXT: s_cbranch_execz .LBB10_4
; GFX942-NEXT: ; %bb.3: ; %bb.2
; GFX942-NEXT: s_mov_b32 s0, 0xc0c0004
-; GFX942-NEXT: v_perm_b32 v2, v0, v10, s0
-; GFX942-NEXT: v_perm_b32 v3, v9, v8, s0
+; GFX942-NEXT: v_perm_b32 v2, v0, v9, s0
+; GFX942-NEXT: v_perm_b32 v3, v8, v7, s0
; GFX942-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX942-NEXT: v_perm_b32 v3, v1, v7, s0
-; GFX942-NEXT: v_perm_b32 v11, v6, v5, s0
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_perm_b32 v3, v1, v6, s0
+; GFX942-NEXT: v_perm_b32 v11, v5, v4, s0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: v_lshl_or_b32 v3, v11, 16, v3
-; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[12:13]
+; GFX942-NEXT: global_store_dwordx2 v10, v[2:3], s[12:13]
; GFX942-NEXT: v_mov_b32_e32 v2, v0
-; GFX942-NEXT: v_mov_b32_e32 v11, v10
-; GFX942-NEXT: v_mov_b32_e32 v12, v9
-; GFX942-NEXT: v_mov_b32_e32 v13, v8
+; GFX942-NEXT: v_mov_b32_e32 v10, v9
+; GFX942-NEXT: v_mov_b32_e32 v11, v8
+; GFX942-NEXT: v_mov_b32_e32 v12, v7
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: v_mov_b32_e32 v14, v7
-; GFX942-NEXT: v_mov_b32_e32 v15, v6
-; GFX942-NEXT: v_mov_b32_e32 v16, v5
+; GFX942-NEXT: v_mov_b32_e32 v13, v6
+; GFX942-NEXT: v_mov_b32_e32 v14, v5
+; GFX942-NEXT: v_mov_b32_e32 v15, v4
; GFX942-NEXT: .LBB10_4: ; %bb.3
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT: s_mov_b32 s0, 0xc0c0004
-; GFX942-NEXT: v_perm_b32 v0, v2, v11, s0
-; GFX942-NEXT: v_perm_b32 v1, v12, v13, s0
+; GFX942-NEXT: v_perm_b32 v0, v2, v10, s0
+; GFX942-NEXT: v_perm_b32 v1, v11, v12, s0
; GFX942-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX942-NEXT: v_perm_b32 v1, v3, v14, s0
-; GFX942-NEXT: v_perm_b32 v2, v15, v16, s0
+; GFX942-NEXT: v_perm_b32 v1, v3, v13, s0
+; GFX942-NEXT: v_perm_b32 v2, v14, v15, s0
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[14:15]
@@ -621,31 +621,31 @@ define amdgpu_kernel void @v8i8_multi_block(ptr addrspace(1) %src1, ptr addrspac
; GFX942-LABEL: v8i8_multi_block:
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
+; GFX942-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v1
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v1
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dwordx2 v[4:5], v1, s[8:9]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: global_load_dwordx2 v[4:5], v0, s[8:9]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: v_mov_b64_e32 v[2:3], v[4:5]
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB11_4
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v2, 3, v1
; GFX942-NEXT: global_load_dwordx2 v[2:3], v2, s[10:11]
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 7, v0
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 7, v1
; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT: s_cbranch_execz .LBB11_3
; GFX942-NEXT: ; %bb.2: ; %bb.2
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: global_store_dwordx2 v0, v[4:5], s[12:13]
+; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: global_store_dwordx2 v1, v[4:5], s[12:13]
; GFX942-NEXT: .LBB11_3: ; %Flow
; GFX942-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT: .LBB11_4: ; %bb.3
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: global_store_dwordx2 v1, v[2:3], s[14:15]
+; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[14:15]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -863,17 +863,17 @@ define amdgpu_kernel void @v8i8_mfma_i8(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-LABEL: v8i8_mfma_i8:
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 3, v0
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v0
+; GFX942-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v1
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v1
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: global_load_dwordx2 v[2:3], v1, s[8:9]
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: global_load_dwordx2 v[2:3], v0, s[8:9]
+; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB14_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v0
-; GFX942-NEXT: global_load_dwordx2 v[2:3], v0, s[10:11]
+; GFX942-NEXT: v_lshlrev_b32_e32 v1, 3, v1
+; GFX942-NEXT: global_load_dwordx2 v[2:3], v1, s[10:11]
; GFX942-NEXT: .LBB14_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[14:15], 0x0
@@ -884,7 +884,7 @@ define amdgpu_kernel void @v8i8_mfma_i8(ptr addrspace(1) %src1, ptr addrspace(1)
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mfma_i32_16x16x32_i8 v[2:5], v[2:3], v[2:3], v[4:7] cbsz:1 abid:2 blgp:3
; GFX942-NEXT: s_nop 6
-; GFX942-NEXT: global_store_dwordx4 v1, v[2:5], s[12:13]
+; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[12:13]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1000,23 +1000,23 @@ define amdgpu_kernel void @v8i8_intrinsic(ptr addrspace(1) %src1, ptr addrspace(
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX942-NEXT: v_and_b32_e32 v2, 0x3ff, v0
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v2
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_and_b32_e32 v3, 0x3ff, v0
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v3
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1]
-; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v2
+; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 15, v3
; GFX942-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT: s_cbranch_execz .LBB16_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
; GFX942-NEXT: s_waitcnt vmcnt(0)
-; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v2
+; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v3
; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]
; GFX942-NEXT: .LBB16_2: ; %bb.2
; GFX942-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: v_pk_fma_f32 v[0:1], v[0:1], v[0:1], v[0:1]
-; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[6:7]
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX942-NEXT: s_endpgm
entry:
%idx = call i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll b/llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
index e67f992380faa..4337f7f46d798 100644
--- a/llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
+++ b/llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
@@ -24,10 +24,10 @@ define amdgpu_kernel void @foo(i1 %cmp1) {
; GFX906-NEXT: s_mov_b32 s15, 0xe00000
; GFX906-NEXT: s_add_u32 s12, s12, s11
; GFX906-NEXT: s_addc_u32 s13, s13, 0
-; GFX906-NEXT: buffer_load_dword v3, off, s[12:15], 0
-; GFX906-NEXT: buffer_load_dword v4, off, s[12:15], 0 offset:4
-; GFX906-NEXT: buffer_load_dword v5, off, s[12:15], 0 offset:8
-; GFX906-NEXT: buffer_load_dword v6, off, s[12:15], 0 offset:12
+; GFX906-NEXT: buffer_load_dword v5, off, s[12:15], 0
+; GFX906-NEXT: buffer_load_dword v6, off, s[12:15], 0 offset:4
+; GFX906-NEXT: buffer_load_dword v3, off, s[12:15], 0 offset:8
+; GFX906-NEXT: buffer_load_dword v4, off, s[12:15], 0 offset:12
; GFX906-NEXT: s_load_dword s2, s[4:5], 0x24
; GFX906-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1c
; GFX906-NEXT: s_mov_b32 s4, 0
@@ -44,18 +44,19 @@ define amdgpu_kernel void @foo(i1 %cmp1) {
; GFX906-NEXT: ds_write_b64 v2, v[0:1]
; GFX906-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
; GFX906-NEXT: s_waitcnt vmcnt(3)
-; GFX906-NEXT: v_readfirstlane_b32 s0, v3
+; GFX906-NEXT: v_readfirstlane_b32 s0, v5
; GFX906-NEXT: s_waitcnt vmcnt(2)
-; GFX906-NEXT: v_readfirstlane_b32 s1, v4
-; GFX906-NEXT: v_cmp_eq_u64_e32 vcc, s[0:1], v[3:4]
+; GFX906-NEXT: v_readfirstlane_b32 s1, v6
+; GFX906-NEXT: v_cmp_eq_u64_e32 vcc, s[0:1], v[5:6]
; GFX906-NEXT: s_waitcnt vmcnt(1)
-; GFX906-NEXT: v_readfirstlane_b32 s0, v5
+; GFX906-NEXT: v_readfirstlane_b32 s0, v3
; GFX906-NEXT: s_waitcnt vmcnt(0)
-; GFX906-NEXT: v_readfirstlane_b32 s1, v6
-; GFX906-NEXT: v_cmp_eq_u64_e64 s[0:1], s[0:1], v[5:6]
+; GFX906-NEXT: v_readfirstlane_b32 s1, v4
+; GFX906-NEXT: v_cmp_eq_u64_e64 s[0:1], s[0:1], v[3:4]
; GFX906-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
; GFX906-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
-; GFX906-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6
+; GFX906-NEXT: ; implicit-def: $vgpr5
+; GFX906-NEXT: ; implicit-def: $vgpr3_vgpr4
; GFX906-NEXT: s_xor_b64 exec, exec, s[0:1]
; GFX906-NEXT: s_cbranch_execnz .LBB0_1
; GFX906-NEXT: ; %bb.2:
>From aaa7a3e0f9638dd32d511f5f913b8229766837fa Mon Sep 17 00:00:00 2001
From: Frederik Harwath <fharwath at amd.com>
Date: Wed, 25 Mar 2026 09:35:07 -0400
Subject: [PATCH 2/2] Review changes
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 95f8e75e3f365..e65d6126507ab 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -2410,7 +2410,7 @@ bool SIFoldOperandsImpl::tryFoldRegSequenceSubRegUses(
// The lookup can fail, for instance, if the use refers to a
// subregister of a subregister.
- // TODO Handle subregister composition. See also getRegSeqInits.
+ // TODO Handle subregister composition. See also getRegSeqInit.
auto *It =
find_if(Defs, [=](const DefPair &P) { return P.second == UseSubReg; });
if (It == Defs.end() || !It->first) {
@@ -2420,15 +2420,19 @@ bool SIFoldOperandsImpl::tryFoldRegSequenceSubRegUses(
MachineOperand *DefOp = It->first;
LLVM_DEBUG(dbgs() << "Resolved definition to: " << *DefOp << '\n');
- if (DefOp->isImm() || MRI->getVRegDef(DefOp->getReg())->isCopy())
+ if (!DefOp->isReg())
+ continue;
+
+ MachineInstr *DefMI = MRI->getVRegDef(DefOp->getReg());
+ if (!DefMI || DefMI->isCopy())
continue;
Register CopyDst = MRI->createVirtualRegister(InputRC);
const MCInstrDesc &CopyDesc = TII->get(AMDGPU::COPY);
+ MRI->clearKillFlags(DefOp->getReg());
MachineInstr *CopyMI = BuildMI(*UseMI->getParent(), UseMI,
UseMI->getDebugLoc(), CopyDesc, CopyDst)
.add(*DefOp);
- CopyMI->getOperand(1).setIsKill(false);
LLVM_DEBUG(dbgs() << "Created Copy: " << *CopyMI);
Use.ChangeToRegister(CopyDst, false);
@@ -2441,7 +2445,7 @@ bool SIFoldOperandsImpl::tryFoldRegSequenceSubRegUses(
if (MRI->hasAtMostUserInstrs(Reg, 0)) {
LLVM_DEBUG(dbgs() << "Removing REG_SEQUENCE which is dead after fold.\n");
- MI.removeFromParent();
+ MI.eraseFromParent();
}
return Changed;
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