[llvm] Fix assert in SlotIndexes::getInstructionIndex in debug builds (PR #189370)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 15 01:56:34 PDT 2026
https://github.com/MarcoCastorina updated https://github.com/llvm/llvm-project/pull/189370
>From 14a3f05692e51257b2f4b0a464aeb4c5e9464d60 Mon Sep 17 00:00:00 2001
From: "Castorina, Marco" <marco.castorina at amd.com>
Date: Mon, 30 Mar 2026 12:32:13 +0100
Subject: [PATCH 1/4] Fix assert in SlotIndexes::getInstructionIndex in debug
builds
In some cases, when debug info is enabled, the assertion in
SlotIndexes::getInstructionIndex fires as the interval contains only debug
instructions. This change ensures only valid instructions are taken into
account.
---
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 5fd0c1e1064cb..f67b5cd65ec92 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -1174,12 +1174,15 @@ void SIWholeQuadMode::toExact(MachineBasicBlock &MBB,
Register SaveWQM) {
assert(LiveMaskReg.isVirtual());
- bool IsTerminator = Before == MBB.end();
+ auto MBBE = MBB.end();
+ bool IsTerminator = Before == MBBE;
if (!IsTerminator) {
auto FirstTerm = MBB.getFirstTerminator();
- if (FirstTerm != MBB.end()) {
- SlotIndex FirstTermIdx = LIS->getInstructionIndex(*FirstTerm);
- SlotIndex BeforeIdx = LIS->getInstructionIndex(*Before);
+ auto FirstNonDbg = skipDebugInstructionsForward(FirstTerm, MBBE);
+ if (FirstNonDbg != MBBE) {
+ auto BeforeNonDbg = skipDebugInstructionsForward(Before, MBBE);
+ SlotIndex FirstTermIdx = LIS->getInstructionIndex(*FirstNonDbg);
+ SlotIndex BeforeIdx = LIS->getInstructionIndex(*BeforeNonDbg);
IsTerminator = BeforeIdx > FirstTermIdx;
}
}
>From 835c7adb9bd607a365b7412c190c886f76d32e1c Mon Sep 17 00:00:00 2001
From: "Castorina, Marco" <marco.castorina at amd.com>
Date: Tue, 31 Mar 2026 14:43:25 +0100
Subject: [PATCH 2/4] Addressed review comments
Assisted-by: Cursor // Claude Opus 4.6
---
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 15 +-
.../AMDGPU/wqm-debug-instr-terminator.mir | 131 ++++++++++++++++++
2 files changed, 139 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index f67b5cd65ec92..f9b159a6c5fb5 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -1174,16 +1174,17 @@ void SIWholeQuadMode::toExact(MachineBasicBlock &MBB,
Register SaveWQM) {
assert(LiveMaskReg.isVirtual());
- auto MBBE = MBB.end();
+ MachineBasicBlock::iterator MBBE = MBB.end();
bool IsTerminator = Before == MBBE;
if (!IsTerminator) {
auto FirstTerm = MBB.getFirstTerminator();
- auto FirstNonDbg = skipDebugInstructionsForward(FirstTerm, MBBE);
- if (FirstNonDbg != MBBE) {
- auto BeforeNonDbg = skipDebugInstructionsForward(Before, MBBE);
- SlotIndex FirstTermIdx = LIS->getInstructionIndex(*FirstNonDbg);
- SlotIndex BeforeIdx = LIS->getInstructionIndex(*BeforeNonDbg);
- IsTerminator = BeforeIdx > FirstTermIdx;
+ if (FirstTerm != MBBE) {
+ MachineBasicBlock::iterator BeforeNonDbg = skipDebugInstructionsForward(Before, MBBE);
+ if (BeforeNonDbg != MBBE) {
+ SlotIndex FirstTermIdx = LIS->getInstructionIndex(*FirstTerm);
+ SlotIndex BeforeIdx = LIS->getInstructionIndex(*BeforeNonDbg);
+ IsTerminator = BeforeIdx > FirstTermIdx;
+ }
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir b/llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
new file mode 100644
index 0000000000000..04cee829d5250
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
@@ -0,0 +1,131 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s
+
+# Regression test for the toExact() crash with debug instructions (PR #189370).
+#
+# In a non-entry block that starts in WQM (WQMFromExec=false), a
+# StrictWQM->Exact transition has SaveSCC=false, so prepareInsertion()
+# returns the raw First iterator without resolving it through SlotIndexes.
+# If consecutive debug instructions sit right after the StrictWQM
+# instruction, FirstStrict points to the first one. The second consecutive
+# DBG_VALUE is needed because getInstructionIndex uses getBundleEnd (= next
+# instruction) as the skip limit; with two consecutive debug instructions
+# the skip lands on the second debug instruction and the assertion
+# !BundleNonDebug.isDebugInstr() fires inside toExact's call to
+# getInstructionIndex(*Before).
+
+--- |
+ define amdgpu_ps void @wqm_debug_strict_to_exact() !dbg !4 {
+ entry:
+ br label %body, !dbg !10
+ body:
+ ret void, !dbg !10
+ }
+
+ !llvm.dbg.cu = !{!0}
+ !llvm.module.flags = !{!1, !2}
+ !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !3, producer: "test", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+ !1 = !{i32 7, !"Dwarf Version", i32 4}
+ !2 = !{i32 2, !"Debug Info Version", i32 3}
+ !3 = !DIFile(filename: "test.hlsl", directory: "/tmp")
+ !4 = distinct !DISubprogram(name: "wqm_debug_strict_to_exact", scope: !3, file: !3, line: 1, type: !5, scopeLine: 1, unit: !0)
+ !5 = !DISubroutineType(types: !{null})
+ !7 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
+ !8 = !DILocalVariable(name: "v", scope: !4, file: !3, line: 2, type: !7)
+ !10 = !DILocation(line: 2, scope: !4)
+...
+---
+
+---
+name: wqm_debug_strict_to_exact
+tracksRegLiveness: true
+liveins:
+ - { reg: '$vgpr0', virtual-reg: '%0' }
+ - { reg: '$vgpr1', virtual-reg: '%1' }
+body: |
+ ; CHECK-LABEL: name: wqm_debug_strict_to_exact
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $m0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $exec_lo
+ ; CHECK-NEXT: $exec_lo = S_WQM_B32 $exec_lo, implicit-def $scc
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.body:
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $m0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ENTER_STRICT_WQM:%[0-9]+]]:sreg_32 = ENTER_STRICT_WQM -1, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; CHECK-NEXT: [[DS_PARAM_LOAD:%[0-9]+]]:vgpr_32 = DS_PARAM_LOAD 0, 0, 0, 1, implicit $m0, implicit $exec
+ ; CHECK-NEXT: $exec_lo = EXIT_STRICT_WQM [[ENTER_STRICT_WQM]]
+ ; CHECK-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32 = S_AND_SAVEEXEC_B32 [[COPY]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; CHECK-NEXT: DBG_VALUE $noreg, $noreg
+ ; CHECK-NEXT: DBG_VALUE $noreg, $noreg
+ ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET_exact [[DS_PARAM_LOAD]], [[DEF1]], [[DEF2]], 0, 0, 0, implicit $exec
+ ; CHECK-NEXT: $exec_lo = COPY [[S_AND_SAVEEXEC_B32_]]
+ ; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0:vreg_64 = COPY [[DS_PARAM_LOAD]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]].sub1:vreg_64 = COPY [[COPY2]]
+ ; CHECK-NEXT: $exec_lo = S_AND_B32 $exec_lo, [[COPY]], implicit-def $scc
+ ; CHECK-NEXT: [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[COPY3]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 8)
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: EXP_DONE 0, [[IMAGE_SAMPLE_V4_V2_]].sub0, [[IMAGE_SAMPLE_V4_V2_]].sub1, [[IMAGE_SAMPLE_V4_V2_]].sub2, [[IMAGE_SAMPLE_V4_V2_]].sub3, 0, 0, 0, implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]
+ ; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0
+ bb.0.entry:
+ liveins: $vgpr0, $vgpr1, $m0
+
+ %0:vgpr_32 = COPY $vgpr0
+ %1:vgpr_32 = COPY $vgpr1
+ %2:sgpr_256 = IMPLICIT_DEF
+ %3:sgpr_128 = IMPLICIT_DEF
+ %4:sgpr_32 = IMPLICIT_DEF
+ S_BRANCH %bb.1
+
+ bb.1.body:
+ liveins: $m0
+
+ ; DS_PARAM_LOAD needs StrictWQM; its result feeds IMAGE_SAMPLE (below)
+ ; so WQM propagates here, making InNeeds include WQM -> block starts WQM.
+ %5:vgpr_32 = DS_PARAM_LOAD 0, 0, 0, 1, implicit $m0, implicit $exec
+ ; Two consecutive debug instructions after the StrictWQM instruction.
+ ; DS_PARAM_LOAD resets FirstStrict to the block-end sentinel (MBB.end()),
+ ; so the first DBG_VALUE becomes FirstStrict. The second is needed so
+ ; getInstructionIndex's bundle-end
+ ; skip still lands on a debug instruction, triggering the assertion.
+ DBG_VALUE $noreg, $noreg
+ DBG_VALUE $noreg, $noreg
+ ; BUFFER_STORE_exact has DisableWQM -> Needs = StateExact only.
+ ; StrictWQM -> Exact: SaveSCC=false (non-entry, Needs has no Strict/WQM).
+ ; prepareInsertion returns First (= first DBG_VALUE) directly.
+ ; toExact receives Before = first DBG_VALUE and calls
+ ; getInstructionIndex(*Before) which asserts on the debug instruction.
+ BUFFER_STORE_DWORD_OFFSET_exact %5, %3, %4, 0, 0, 0, implicit $exec
+ ; IMAGE_SAMPLE propagates WQM to its inputs (including DS_PARAM_LOAD),
+ ; making this block need WQM -> NonStrictState = WQM -> WQMToExact = true.
+ undef %6.sub0:vreg_64 = COPY %5
+ %6.sub1:vreg_64 = COPY %1
+ %7:vreg_128 = IMAGE_SAMPLE_V4_V2 %6, %2, %3, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 8)
+ S_CBRANCH_EXECZ %bb.3, implicit $exec
+ S_BRANCH %bb.2
+
+ bb.2:
+ EXP_DONE 0, %7.sub0, %7.sub1, %7.sub2, %7.sub3, 0, 0, 0, implicit $exec
+ S_ENDPGM 0
+
+ bb.3:
+ $vgpr0 = COPY %0
+ SI_RETURN_TO_EPILOG $vgpr0
+
+...
>From 284d1558e3744ef4ccd29d09f3c26d52d0d5163e Mon Sep 17 00:00:00 2001
From: "Castorina, Marco" <marco.castorina at amd.com>
Date: Wed, 1 Apr 2026 16:50:39 +0100
Subject: [PATCH 3/4] Simplified check and adjusted test
---
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 12 +++++-------
.../CodeGen/AMDGPU/wqm-debug-instr-terminator.mir | 5 +----
2 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index f9b159a6c5fb5..4000ca9ec4dcb 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -1178,13 +1178,11 @@ void SIWholeQuadMode::toExact(MachineBasicBlock &MBB,
bool IsTerminator = Before == MBBE;
if (!IsTerminator) {
auto FirstTerm = MBB.getFirstTerminator();
- if (FirstTerm != MBBE) {
- MachineBasicBlock::iterator BeforeNonDbg = skipDebugInstructionsForward(Before, MBBE);
- if (BeforeNonDbg != MBBE) {
- SlotIndex FirstTermIdx = LIS->getInstructionIndex(*FirstTerm);
- SlotIndex BeforeIdx = LIS->getInstructionIndex(*BeforeNonDbg);
- IsTerminator = BeforeIdx > FirstTermIdx;
- }
+ MachineBasicBlock::iterator BeforeNonDbg = skipDebugInstructionsForward(Before, MBBE);
+ if (FirstTerm != MBBE && BeforeNonDbg != MBBE) {
+ SlotIndex FirstTermIdx = LIS->getInstructionIndex(*FirstTerm);
+ SlotIndex BeforeIdx = LIS->getInstructionIndex(*BeforeNonDbg);
+ IsTerminator = BeforeIdx > FirstTermIdx;
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir b/llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
index 04cee829d5250..254cbd2b4b312 100644
--- a/llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
+++ b/llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass si-wqm -o - %s | FileCheck %s
# Regression test for the toExact() crash with debug instructions (PR #189370).
#
@@ -39,9 +39,6 @@
---
name: wqm_debug_strict_to_exact
tracksRegLiveness: true
-liveins:
- - { reg: '$vgpr0', virtual-reg: '%0' }
- - { reg: '$vgpr1', virtual-reg: '%1' }
body: |
; CHECK-LABEL: name: wqm_debug_strict_to_exact
; CHECK: bb.0.entry:
>From 5f6de9651e886db81a58a83b4180d1070e65424a Mon Sep 17 00:00:00 2001
From: "Castorina, Marco" <marco.castorina at amd.com>
Date: Wed, 15 Apr 2026 09:56:15 +0100
Subject: [PATCH 4/4] More review comments
---
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 4000ca9ec4dcb..1de7930dd9dc0 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -1178,10 +1178,10 @@ void SIWholeQuadMode::toExact(MachineBasicBlock &MBB,
bool IsTerminator = Before == MBBE;
if (!IsTerminator) {
auto FirstTerm = MBB.getFirstTerminator();
- MachineBasicBlock::iterator BeforeNonDbg = skipDebugInstructionsForward(Before, MBBE);
- if (FirstTerm != MBBE && BeforeNonDbg != MBBE) {
+ if (FirstTerm != MBBE) {
+ Before = skipDebugInstructionsForward(Before, MBBE);
SlotIndex FirstTermIdx = LIS->getInstructionIndex(*FirstTerm);
- SlotIndex BeforeIdx = LIS->getInstructionIndex(*BeforeNonDbg);
+ SlotIndex BeforeIdx = LIS->getInstructionIndex(*Before);
IsTerminator = BeforeIdx > FirstTermIdx;
}
}
More information about the llvm-commits
mailing list