[llvm] [RISCV] Support MachineOutlinerRegSave for RISCV (PR #191351)

[Piyou Chen via llvm-commits]

BeMg wrote:

> Probably should have a test for rv32e to make sure we don't use x29, x30, or x31.

Add llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave-rv32e.mir

https://github.com/llvm/llvm-project/pull/191351