[llvm] [RISCV] Support MachineOutlinerRegSave for RISCV (PR #191351)

[Piyou Chen via llvm-commits]

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@@ -3714,7 +3748,16 @@ bool RISCVInstrInfo::analyzeCandidate(outliner::Candidate &C) const {
       }))
     return true;
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BeMg wrote:

Sure. 

updated. 

https://github.com/llvm/llvm-project/pull/191351