[llvm] [AMDGPU]: Add regbank legalize rules for amdgcn exp2 intrinsics (PR #191953)
Jasmine Tang via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 14 21:24:42 PDT 2026
https://github.com/badumbatish updated https://github.com/llvm/llvm-project/pull/191953
>From 032681fd0010623a59398f329a92402820573088 Mon Sep 17 00:00:00 2001
From: Jasmine Tang <jjasmine at igalia.com>
Date: Mon, 13 Apr 2026 13:18:56 -0700
Subject: [PATCH 1/2] [AMDGPU]: Add regbank legalize rules for amdgcn exp2
intrinsics
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 8 ++
.../AMDGPU/GlobalISel/regbankselect-fexp2.mir | 121 +++++++++++++++++-
.../pseudo-scalar-transcendental-regbank.ll | 96 ++++++++++++++
3 files changed, 224 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental-regbank.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 4d8079b4663b3..aa457b7dcd5bf 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1704,6 +1704,14 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Div(S64, {{Vgpr64}, {IntrId, Vgpr64, Vgpr32}})
.Uni(S64, {{UniInVgprS64}, {IntrId, Vgpr64, Vgpr32}});
+ addRulesForIOpcs({amdgcn_exp2}, Standard)
+ .Div(S16, {{Vgpr16}, {IntrId, Vgpr16}})
+ .Uni(S16, {{Sgpr16}, {IntrId, Sgpr16}}, hasPST)
+ .Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr16}}, !hasPST)
+ .Div(S32, {{Vgpr32}, {IntrId, Vgpr32}})
+ .Uni(S32, {{Sgpr32}, {IntrId, Sgpr32}}, hasPST)
+ .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32}}, !hasPST);
+
addRulesForIOpcs({amdgcn_ds_add_gs_reg_rtn, amdgcn_ds_sub_gs_reg_rtn},
Standard)
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32}})
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
index b743c0db5adda..61e46068aa9b3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX8 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX11 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefixes=CHECK,GFX12 %s
---
name: fexp2_s
@@ -14,6 +16,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: [[FEXP2_:%[0-9]+]]:vgpr(s32) = G_FEXP2 [[COPY1]]
+ ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FEXP2_]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FEXP2 %0
...
@@ -33,3 +36,119 @@ body: |
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FEXP2 %0
...
+
+---
+name: amdgcn_exp2_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GFX8-LABEL: name: amdgcn_exp2_s16_s
+ ; GFX8: liveins: $sgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; GFX8-NEXT: [[INT:%[0-9]+]]:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[COPY1]](s16)
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[INT]](s16)
+ ; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ;
+ ; GFX11-LABEL: name: amdgcn_exp2_s16_s
+ ; GFX11: liveins: $sgpr0
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[COPY1]](s16)
+ ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[INT]](s16)
+ ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ;
+ ; GFX12-LABEL: name: amdgcn_exp2_s16_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[INT:%[0-9]+]]:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[TRUNC]](s16)
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[INT]](s16)
+ ; GFX12-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), %1
+ %3:_(s32) = G_ANYEXT %2
+ $vgpr0 = COPY %3
+...
+
+---
+name: amdgcn_exp2_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: amdgcn_exp2_s16_v
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[TRUNC]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[INT]](s16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), %1
+ %3:_(s32) = G_ANYEXT %2
+ $vgpr0 = COPY %3
+...
+
+---
+name: amdgcn_exp2_s32_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GFX8-LABEL: name: amdgcn_exp2_s32_s
+ ; GFX8: liveins: $sgpr0
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; GFX8-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[COPY1]](s32)
+ ; GFX8-NEXT: $vgpr0 = COPY [[INT]](s32)
+ ;
+ ; GFX11-LABEL: name: amdgcn_exp2_s32_s
+ ; GFX11: liveins: $sgpr0
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[COPY1]](s32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[INT]](s32)
+ ;
+ ; GFX12-LABEL: name: amdgcn_exp2_s32_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[COPY]](s32)
+ ; GFX12-NEXT: $vgpr0 = COPY [[INT]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), %0
+ $vgpr0 = COPY %1
+...
+
+---
+name: amdgcn_exp2_s32_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; CHECK-LABEL: name: amdgcn_exp2_s32_v
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[COPY]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), %0
+ $vgpr0 = COPY %1
+...
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental-regbank.ll b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental-regbank.ll
new file mode 100644
index 0000000000000..adedcfc77cc8e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental-regbank.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
+
+define amdgpu_cs half @exp2_f16_uniform(half inreg %src) {
+; GFX11-LABEL: exp2_f16_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_exp_f16_e32 v0.l, s0
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: exp2_f16_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_s_exp_f16 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+ %r = call half @llvm.exp2.f16(half %src)
+ ret half %r
+}
+
+define amdgpu_cs half @exp2_f16_divergent(half %src) {
+; GFX11-LABEL: exp2_f16_divergent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_exp_f16_e32 v0.l, v0.l
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: exp2_f16_divergent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_exp_f16_e32 v0.l, v0.l
+; GFX12-NEXT: ; return to shader part epilog
+ %r = call half @llvm.exp2.f16(half %src)
+ ret half %r
+}
+
+define amdgpu_cs float @amdgcn_exp2_f32_uniform(float inreg %src) {
+; GFX11-LABEL: amdgcn_exp2_f32_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_exp_f32_e32 v0, s0
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: amdgcn_exp2_f32_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_s_exp_f32 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+ %r = call float @llvm.amdgcn.exp2.f32(float %src)
+ ret float %r
+}
+
+define amdgpu_cs float @amdgcn_exp2_f32_divergent(float %src) {
+; GFX11-LABEL: amdgcn_exp2_f32_divergent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: amdgcn_exp2_f32_divergent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_exp_f32_e32 v0, v0
+; GFX12-NEXT: ; return to shader part epilog
+ %r = call float @llvm.amdgcn.exp2.f32(float %src)
+ ret float %r
+}
+
+define amdgpu_cs half @amdgcn_exp2_f16_uniform(half inreg %src) {
+; GFX11-LABEL: amdgcn_exp2_f16_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_exp_f16_e32 v0.l, s0
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: amdgcn_exp2_f16_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_s_exp_f16 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+ %r = call half @llvm.amdgcn.exp2.f16(half %src)
+ ret half %r
+}
+
+define amdgpu_cs half @amdgcn_exp2_f16_divergent(half %src) {
+; GFX11-LABEL: amdgcn_exp2_f16_divergent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_exp_f16_e32 v0.l, v0.l
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: amdgcn_exp2_f16_divergent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_exp_f16_e32 v0.l, v0.l
+; GFX12-NEXT: ; return to shader part epilog
+ %r = call half @llvm.amdgcn.exp2.f16(half %src)
+ ret half %r
+}
>From 6fdb0ee150aeffd186426284c67aa174581f95e6 Mon Sep 17 00:00:00 2001
From: Jasmine Tang <jjasmine at igalia.com>
Date: Tue, 14 Apr 2026 21:19:54 -0700
Subject: [PATCH 2/2] Move test to AMDGPU/llvm.amdgcn.exp2.ll
---
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll | 156 ++++++++++++++++++
.../pseudo-scalar-transcendental-regbank.ll | 96 -----------
2 files changed, 156 insertions(+), 96 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental-regbank.ll
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
index 99a092e310abb..c6af19a950e6a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN_BANK,GFX11 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN_BANK,GFX12 %s
define float @v_exp2_f32(float %src) {
; GCN-LABEL: v_exp2_f32:
@@ -8,6 +10,50 @@ define float @v_exp2_f32(float %src) {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_exp2_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_exp2_f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_exp_f32_e32 v0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %exp2 = call float @llvm.amdgcn.exp2.f32(float %src)
+ ret float %exp2
+}
+define float @v_exp2_f32_uniform(float inreg %src) {
+; GCN-LABEL: v_exp2_f32_uniform:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_exp_f32_e32 v0, s16
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_exp2_f32_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_exp_f32_e32 v0, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_exp2_f32_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_s_exp_f32 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%exp2 = call float @llvm.amdgcn.exp2.f32(float %src)
ret float %exp2
}
@@ -18,6 +64,22 @@ define float @v_fabs_exp2_f32(float %src) {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f32_e64 v0, |v0|
; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fabs_exp2_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_exp_f32_e64 v0, |v0|
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_fabs_exp2_f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_exp_f32_e64 v0, |v0|
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call float @llvm.fabs.f32(float %src)
%exp2 = call float @llvm.amdgcn.exp2.f32(float %fabs.src)
ret float %exp2
@@ -29,6 +91,22 @@ define float @v_fneg_fabs_exp2_f32(float %src) {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f32_e64 v0, -|v0|
; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fabs_exp2_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_exp_f32_e64 v0, -|v0|
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_fneg_fabs_exp2_f32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_exp_f32_e64 v0, -|v0|
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call float @llvm.fabs.f32(float %src)
%neg.fabs.src = fneg float %fabs.src
%exp2 = call float @llvm.amdgcn.exp2.f32(float %neg.fabs.src)
@@ -41,6 +119,51 @@ define half @v_exp2_f16(half %src) {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f16_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_exp2_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_exp_f16_e32 v0.l, v0.l
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_exp2_f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_exp_f16_e32 v0.l, v0.l
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %exp2 = call half @llvm.amdgcn.exp2.f16(half %src)
+ ret half %exp2
+}
+
+define half @v_exp2_f16_uniform(half inreg %src) {
+; GCN-LABEL: v_exp2_f16_uniform:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_exp_f16_e32 v0, s16
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_exp2_f16_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_exp_f16_e32 v0.l, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_exp2_f16_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_s_exp_f16 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%exp2 = call half @llvm.amdgcn.exp2.f16(half %src)
ret half %exp2
}
@@ -51,6 +174,22 @@ define half @v_fabs_exp2_f16(half %src) {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f16_e64 v0, |v0|
; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fabs_exp2_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_exp_f16_e64 v0.l, |v0.l|
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_fabs_exp2_f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_exp_f16_e64 v0.l, |v0.l|
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call half @llvm.fabs.f16(half %src)
%exp2 = call half @llvm.amdgcn.exp2.f16(half %fabs.src)
ret half %exp2
@@ -62,6 +201,22 @@ define half @v_fneg_fabs_exp2_f16(half %src) {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f16_e64 v0, -|v0|
; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fabs_exp2_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_exp_f16_e64 v0.l, -|v0.l|
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_fneg_fabs_exp2_f16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_exp_f16_e64 v0.l, -|v0.l|
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call half @llvm.fabs.f16(half %src)
%neg.fabs.src = fneg half %fabs.src
%exp2 = call half @llvm.amdgcn.exp2.f16(half %neg.fabs.src)
@@ -75,5 +230,6 @@ declare half @llvm.fabs.f16(half) #0
attributes #0 = { nounwind readnone speculatable willreturn }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GCN_BANK: {{.*}}
; GISEL: {{.*}}
; SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental-regbank.ll b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental-regbank.ll
deleted file mode 100644
index adedcfc77cc8e..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental-regbank.ll
+++ /dev/null
@@ -1,96 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
-
-define amdgpu_cs half @exp2_f16_uniform(half inreg %src) {
-; GFX11-LABEL: exp2_f16_uniform:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_exp_f16_e32 v0.l, s0
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: exp2_f16_uniform:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_s_exp_f16 s0, s0
-; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-NEXT: ; return to shader part epilog
- %r = call half @llvm.exp2.f16(half %src)
- ret half %r
-}
-
-define amdgpu_cs half @exp2_f16_divergent(half %src) {
-; GFX11-LABEL: exp2_f16_divergent:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_exp_f16_e32 v0.l, v0.l
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: exp2_f16_divergent:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_exp_f16_e32 v0.l, v0.l
-; GFX12-NEXT: ; return to shader part epilog
- %r = call half @llvm.exp2.f16(half %src)
- ret half %r
-}
-
-define amdgpu_cs float @amdgcn_exp2_f32_uniform(float inreg %src) {
-; GFX11-LABEL: amdgcn_exp2_f32_uniform:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_exp_f32_e32 v0, s0
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: amdgcn_exp2_f32_uniform:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_s_exp_f32 s0, s0
-; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-NEXT: ; return to shader part epilog
- %r = call float @llvm.amdgcn.exp2.f32(float %src)
- ret float %r
-}
-
-define amdgpu_cs float @amdgcn_exp2_f32_divergent(float %src) {
-; GFX11-LABEL: amdgcn_exp2_f32_divergent:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: amdgcn_exp2_f32_divergent:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_exp_f32_e32 v0, v0
-; GFX12-NEXT: ; return to shader part epilog
- %r = call float @llvm.amdgcn.exp2.f32(float %src)
- ret float %r
-}
-
-define amdgpu_cs half @amdgcn_exp2_f16_uniform(half inreg %src) {
-; GFX11-LABEL: amdgcn_exp2_f16_uniform:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_exp_f16_e32 v0.l, s0
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: amdgcn_exp2_f16_uniform:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_s_exp_f16 s0, s0
-; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-NEXT: ; return to shader part epilog
- %r = call half @llvm.amdgcn.exp2.f16(half %src)
- ret half %r
-}
-
-define amdgpu_cs half @amdgcn_exp2_f16_divergent(half %src) {
-; GFX11-LABEL: amdgcn_exp2_f16_divergent:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: v_exp_f16_e32 v0.l, v0.l
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12-LABEL: amdgcn_exp2_f16_divergent:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_exp_f16_e32 v0.l, v0.l
-; GFX12-NEXT: ; return to shader part epilog
- %r = call half @llvm.amdgcn.exp2.f16(half %src)
- ret half %r
-}
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