[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for async LDS loads (PR #192179)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 14 21:19:33 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: vangthao95
<details>
<summary>Changes</summary>
Add RegBankLegalize rules for async LDS load intrinsics:
llvm.amdgcn.asyncmark
llvm.amdgcn.wait.asyncmark
llvm.amdgcn.global.load.async.to.lds.b8
llvm.amdgcn.global.load.async.to.lds.b32
llvm.amdgcn.global.load.async.to.lds.b64
llvm.amdgcn.global.load.async.to.lds.b128
---
Full diff: https://github.com/llvm/llvm-project/pull/192179.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+19-24)
- (modified) llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll (+94-76)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll (+1-1)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index c3157c9441027..a90cfb5ec3e12 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1493,30 +1493,19 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{Sgpr32}, {IntrId}});
// Intrinsics with no register operands.
- addRulesForIOpcs({amdgcn_endpgm,
- amdgcn_init_exec,
- amdgcn_s_barrier,
- amdgcn_s_barrier_signal,
- amdgcn_s_barrier_wait,
- amdgcn_s_monitor_sleep,
- amdgcn_s_nop,
- amdgcn_s_sethalt,
- amdgcn_s_setprio,
- amdgcn_s_setprio_inc_wg,
- amdgcn_s_sleep,
- amdgcn_s_ttracedata_imm,
- amdgcn_s_wait_asynccnt,
- amdgcn_s_wait_bvhcnt,
- amdgcn_s_wait_dscnt,
- amdgcn_s_wait_event,
- amdgcn_s_wait_event_export_ready,
- amdgcn_s_wait_expcnt,
- amdgcn_s_wait_kmcnt,
- amdgcn_s_wait_loadcnt,
- amdgcn_s_wait_samplecnt,
- amdgcn_s_wait_storecnt,
- amdgcn_s_wait_tensorcnt,
- amdgcn_s_waitcnt,
+ addRulesForIOpcs({amdgcn_asyncmark, amdgcn_endpgm,
+ amdgcn_init_exec, amdgcn_s_barrier,
+ amdgcn_s_barrier_signal, amdgcn_s_barrier_wait,
+ amdgcn_s_monitor_sleep, amdgcn_s_nop,
+ amdgcn_s_sethalt, amdgcn_s_setprio,
+ amdgcn_s_setprio_inc_wg, amdgcn_s_sleep,
+ amdgcn_s_ttracedata_imm, amdgcn_s_wait_asynccnt,
+ amdgcn_s_wait_bvhcnt, amdgcn_s_wait_dscnt,
+ amdgcn_s_wait_event, amdgcn_s_wait_event_export_ready,
+ amdgcn_s_wait_expcnt, amdgcn_s_wait_kmcnt,
+ amdgcn_s_wait_loadcnt, amdgcn_s_wait_samplecnt,
+ amdgcn_s_wait_storecnt, amdgcn_s_wait_tensorcnt,
+ amdgcn_s_waitcnt, amdgcn_wait_asyncmark,
amdgcn_wave_barrier})
.Any({{}, {{}, {}}});
@@ -1694,6 +1683,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({amdgcn_global_load_lds})
.Any({{}, {{}, {IntrId, VgprP1, SgprB32_M0}}});
+ addRulesForIOpcs({amdgcn_global_load_async_to_lds_b8,
+ amdgcn_global_load_async_to_lds_b32,
+ amdgcn_global_load_async_to_lds_b64,
+ amdgcn_global_load_async_to_lds_b128})
+ .Any({{}, {{}, {IntrId, VgprP1, VgprP3}}});
+
addRulesForIOpcs({amdgcn_wwm, amdgcn_strict_wwm, amdgcn_wqm, amdgcn_softwqm,
amdgcn_strict_wqm},
StandardB)
diff --git a/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll b/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
index fb469be45936d..2605b135c4a28 100644
--- a/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
+++ b/llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck %s -check-prefixes=SDAG
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck %s -check-prefixes=GISEL
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck %s -check-prefixes=GISEL
; Test async mark/wait with global_load_lds and global loads
; This version uses wave barriers to enforce program order so that unrelated vmem
@@ -194,38 +194,38 @@ define amdgpu_kernel void @test_pipelined_loop(ptr addrspace(1) %foo, ptr addrsp
; GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
; GISEL-NEXT: s_load_b32 s3, s[4:5], 0x44 nv
; GISEL-NEXT: s_mov_b32 s7, 2
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, s7
+; GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v2, 4
; GISEL-NEXT: s_wait_kmcnt 0x0
-; GISEL-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v0, s2
+; GISEL-NEXT: v_mov_b32_e32 v1, s2
; GISEL-NEXT: s_add_co_u32 s6, s2, 4
-; GISEL-NEXT: global_load_async_to_lds_b32 v0, v1, s[0:1] offset:4 nv
-; GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, 4
+; GISEL-NEXT: s_mov_b32 s8, s2
+; GISEL-NEXT: global_load_async_to_lds_b32 v1, v0, s[0:1] offset:4 nv
+; GISEL-NEXT: v_mov_b32_e32 v1, s6
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: s_mov_b32 s6, 0
-; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-NEXT: v_mov_b32_e32 v2, s6
-; GISEL-NEXT: global_load_async_to_lds_b32 v0, v1, s[0:1] offset:4 nv
+; GISEL-NEXT: global_load_async_to_lds_b32 v1, v2, s[0:1] offset:4 nv
; GISEL-NEXT: s_add_co_u32 s0, s0, 8
; GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
; GISEL-NEXT: ; asyncmark
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GISEL-NEXT: .LBB1_1: ; %loop_body
; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL-NEXT: v_dual_add_nc_u32 v5, 8, v3 :: v_dual_add_nc_u32 v4, 1, v4
-; GISEL-NEXT: global_load_async_to_lds_b32 v5, v[0:1], off offset:4 nv
+; GISEL-NEXT: s_add_co_u32 s9, s8, 8
+; GISEL-NEXT: s_add_co_i32 s7, s7, 1
+; GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GISEL-NEXT: global_load_async_to_lds_b32 v1, v0, s[0:1] offset:4 nv
+; GISEL-NEXT: v_mov_b32_e32 v1, s8
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: ; wait_asyncmark(2)
; GISEL-NEXT: s_wait_asynccnt 0x2
-; GISEL-NEXT: ds_load_b32 v5, v3
-; GISEL-NEXT: v_add_co_u32 v0, s0, v0, 4
-; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, s0
-; GISEL-NEXT: v_add_nc_u32_e32 v3, 4, v3
-; GISEL-NEXT: v_cmp_gt_i32_e32 vcc_lo, s3, v4
+; GISEL-NEXT: ds_load_b32 v1, v1
; GISEL-NEXT: s_wait_dscnt 0x0
-; GISEL-NEXT: v_add_nc_u32_e32 v2, v2, v5
-; GISEL-NEXT: s_cbranch_vccnz .LBB1_1
+; GISEL-NEXT: v_readfirstlane_b32 s9, v1
+; GISEL-NEXT: s_add_co_i32 s6, s6, s9
+; GISEL-NEXT: s_add_co_u32 s0, s0, 4
+; GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
+; GISEL-NEXT: s_add_co_u32 s8, s8, 4
+; GISEL-NEXT: s_cmp_lt_i32 s7, s3
+; GISEL-NEXT: s_cbranch_scc1 .LBB1_1
; GISEL-NEXT: ; %bb.2: ; %epilog
; GISEL-NEXT: s_lshl_b32 s0, s3, 2
; GISEL-NEXT: ; wait_asyncmark(1)
@@ -240,7 +240,10 @@ define amdgpu_kernel void @test_pipelined_loop(ptr addrspace(1) %foo, ptr addrsp
; GISEL-NEXT: ; wait_asyncmark(0)
; GISEL-NEXT: s_wait_dscnt 0x0
; GISEL-NEXT: s_wait_asynccnt 0x0
-; GISEL-NEXT: v_add_nc_u32_e32 v0, v2, v0
+; GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GISEL-NEXT: s_add_co_i32 s2, s6, s2
+; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-NEXT: v_mov_b32_e32 v0, s2
; GISEL-NEXT: s_wait_kmcnt 0x0
; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-NEXT: s_endpgm
@@ -388,91 +391,106 @@ define amdgpu_kernel void @test_pipelined_loop_with_global(ptr addrspace(1) %foo
; GISEL-LABEL: test_pipelined_loop_with_global:
; GISEL: ; %bb.0: ; %prolog
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-NEXT: s_clause 0x1
+; GISEL-NEXT: s_clause 0x2
; GISEL-NEXT: s_load_b96 s[8:10], s[4:5], 0x24 nv
; GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
-; GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-NEXT: s_wait_xcnt 0x0
-; GISEL-NEXT: s_load_b32 s4, s[4:5], 0x44 nv
-; GISEL-NEXT: s_wait_xcnt 0x0
-; GISEL-NEXT: s_mov_b32 s5, 2
+; GISEL-NEXT: s_load_b32 s11, s[4:5], 0x44 nv
+; GISEL-NEXT: v_mov_b32_e32 v0, 0
; GISEL-NEXT: s_wait_kmcnt 0x0
-; GISEL-NEXT: s_load_b32 s11, s[8:9], 0x0
-; GISEL-NEXT: s_load_b32 s12, s[0:1], 0x0
-; GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-NEXT: s_load_b32 s14, s[8:9], 0x0
+; GISEL-NEXT: s_load_b32 s15, s[0:1], 0x0
+; GISEL-NEXT: v_mov_b32_e32 v1, s10
; GISEL-NEXT: s_add_co_u32 s6, s10, 4
-; GISEL-NEXT: v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v11, s5
-; GISEL-NEXT: global_load_async_to_lds_b32 v0, v1, s[8:9] offset:4 nv
+; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-NEXT: v_dual_mov_b32 v4, 4 :: v_dual_mov_b32 v3, s6
+; GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
+; GISEL-NEXT: global_load_async_to_lds_b32 v1, v0, s[8:9] offset:4 nv
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: s_clause 0x1
-; GISEL-NEXT: global_load_b32 v6, v1, s[8:9] offset:4
-; GISEL-NEXT: global_load_b32 v7, v1, s[0:1] offset:4
+; GISEL-NEXT: global_load_b32 v1, v0, s[8:9] offset:4
+; GISEL-NEXT: global_load_b32 v2, v0, s[0:1] offset:4
; GISEL-NEXT: s_wait_xcnt 0x0
-; GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, 4
; GISEL-NEXT: s_add_co_u32 s0, s0, 8
; GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
-; GISEL-NEXT: s_add_co_u32 s6, s8, 8
-; GISEL-NEXT: s_add_co_ci_u32 s7, s9, 0
-; GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
-; GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
-; GISEL-NEXT: s_wait_kmcnt 0x0
-; GISEL-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v15, s12
-; GISEL-NEXT: global_load_async_to_lds_b32 v0, v1, s[8:9] offset:4 nv
-; GISEL-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
+; GISEL-NEXT: s_add_co_u32 s4, s8, 8
+; GISEL-NEXT: s_add_co_ci_u32 s5, s9, 0
+; GISEL-NEXT: global_load_async_to_lds_b32 v3, v4, s[8:9] offset:4 nv
+; GISEL-NEXT: s_wait_loadcnt 0x1
+; GISEL-NEXT: v_readfirstlane_b32 s12, v1
; GISEL-NEXT: s_wait_loadcnt 0x0
-; GISEL-NEXT: v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v12, v7
+; GISEL-NEXT: v_readfirstlane_b32 s13, v2
+; GISEL-NEXT: s_mov_b32 s8, 2
+; GISEL-NEXT: s_mov_b32 s9, s10
; GISEL-NEXT: ; asyncmark
+; GISEL-NEXT: s_mov_b32 s17, s12
+; GISEL-NEXT: s_mov_b32 s19, s13
; GISEL-NEXT: .LBB2_1: ; %loop_body
; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL-NEXT: s_wait_loadcnt 0x1
-; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-NEXT: v_dual_mov_b32 v10, v12 :: v_dual_add_nc_u32 v16, 8, v9
-; GISEL-NEXT: s_wait_loadcnt 0x0
-; GISEL-NEXT: v_dual_mov_b32 v14, v8 :: v_dual_add_nc_u32 v11, 1, v11
-; GISEL-NEXT: global_load_b32 v12, v[4:5], off
-; GISEL-NEXT: global_load_b32 v8, v[2:3], off
-; GISEL-NEXT: s_wait_xcnt 0x1
-; GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v4, 4
-; GISEL-NEXT: global_load_async_to_lds_b32 v16, v[2:3], off offset:4 nv
+; GISEL-NEXT: s_add_co_u32 s16, s9, 8
+; GISEL-NEXT: s_clause 0x1
+; GISEL-NEXT: global_load_b32 v1, v0, s[4:5]
+; GISEL-NEXT: global_load_b32 v2, v0, s[0:1]
+; GISEL-NEXT: v_mov_b32_e32 v3, s16
+; GISEL-NEXT: s_mov_b32 s18, s17
+; GISEL-NEXT: s_wait_kmcnt 0x0
+; GISEL-NEXT: s_add_co_i32 s15, s14, s15
+; GISEL-NEXT: s_add_co_i32 s8, s8, 1
+; GISEL-NEXT: s_mov_b32 s16, s19
+; GISEL-NEXT: global_load_async_to_lds_b32 v3, v0, s[4:5] offset:4 nv
+; GISEL-NEXT: v_mov_b32_e32 v3, s9
; GISEL-NEXT: ; asyncmark
; GISEL-NEXT: ; wait_asyncmark(2)
; GISEL-NEXT: s_wait_asynccnt 0x2
-; GISEL-NEXT: ds_load_b32 v16, v9
-; GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
-; GISEL-NEXT: s_wait_xcnt 0x0
-; GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, 4
-; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
-; GISEL-NEXT: v_add_nc_u32_e32 v9, 4, v9
-; GISEL-NEXT: v_cmp_gt_i32_e32 vcc_lo, s4, v11
+; GISEL-NEXT: s_mov_b32 s14, s12
+; GISEL-NEXT: ds_load_b32 v3, v3
; GISEL-NEXT: s_wait_dscnt 0x0
-; GISEL-NEXT: v_add3_u32 v16, v13, v15, v16
-; GISEL-NEXT: v_dual_mov_b32 v13, v6 :: v_dual_mov_b32 v15, v7
-; GISEL-NEXT: global_store_b32 v[0:1], v16, off
+; GISEL-NEXT: v_readfirstlane_b32 s17, v3
+; GISEL-NEXT: s_add_co_i32 s15, s15, s17
; GISEL-NEXT: s_wait_xcnt 0x0
-; GISEL-NEXT: v_add_co_u32 v0, s0, v0, 4
-; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, s0
-; GISEL-NEXT: s_cbranch_vccnz .LBB2_1
+; GISEL-NEXT: s_add_co_u32 s0, s0, 4
+; GISEL-NEXT: v_mov_b32_e32 v3, s15
+; GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0
+; GISEL-NEXT: s_add_co_u32 s4, s4, 4
+; GISEL-NEXT: s_add_co_ci_u32 s5, s5, 0
+; GISEL-NEXT: s_mov_b32 s15, s13
+; GISEL-NEXT: global_store_b32 v0, v3, s[6:7]
+; GISEL-NEXT: s_wait_xcnt 0x0
+; GISEL-NEXT: s_add_co_u32 s6, s6, 4
+; GISEL-NEXT: s_add_co_ci_u32 s7, s7, 0
+; GISEL-NEXT: s_add_co_u32 s9, s9, 4
+; GISEL-NEXT: s_cmp_lt_i32 s8, s11
+; GISEL-NEXT: s_wait_loadcnt 0x1
+; GISEL-NEXT: v_readfirstlane_b32 s17, v1
+; GISEL-NEXT: s_wait_loadcnt 0x0
+; GISEL-NEXT: v_readfirstlane_b32 s19, v2
+; GISEL-NEXT: s_cbranch_scc1 .LBB2_1
; GISEL-NEXT: ; %bb.2: ; %epilog
-; GISEL-NEXT: s_add_co_i32 s0, s4, -2
+; GISEL-NEXT: s_add_co_i32 s0, s11, -2
; GISEL-NEXT: ; wait_asyncmark(1)
; GISEL-NEXT: s_wait_asynccnt 0x1
; GISEL-NEXT: s_lshl_b32 s1, s0, 2
-; GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GISEL-NEXT: s_add_co_i32 s4, s18, s16
; GISEL-NEXT: s_add_co_u32 s1, s10, s1
; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-NEXT: v_mov_b32_e32 v0, s1
; GISEL-NEXT: ds_load_b32 v1, v0
; GISEL-NEXT: s_wait_dscnt 0x0
-; GISEL-NEXT: v_add3_u32 v1, v14, v10, v1
-; GISEL-NEXT: global_store_b32 v2, v1, s[2:3] scale_offset
+; GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GISEL-NEXT: v_mov_b32_e32 v1, s0
+; GISEL-NEXT: s_add_co_i32 s1, s4, s1
+; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-NEXT: v_mov_b32_e32 v2, s1
+; GISEL-NEXT: s_add_co_i32 s1, s17, s19
+; GISEL-NEXT: global_store_b32 v1, v2, s[2:3] scale_offset
; GISEL-NEXT: ; wait_asyncmark(0)
; GISEL-NEXT: s_wait_asynccnt 0x0
; GISEL-NEXT: ds_load_b32 v0, v0 offset:4
-; GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GISEL-NEXT: v_add3_u32 v0, v8, v12, v0
-; GISEL-NEXT: global_store_b32 v2, v0, s[2:3] offset:4 scale_offset
+; GISEL-NEXT: s_wait_dscnt 0x0
+; GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-NEXT: s_add_co_i32 s0, s1, s0
+; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-NEXT: global_store_b32 v1, v0, s[2:3] offset:4 scale_offset
; GISEL-NEXT: s_endpgm
prolog:
; Load first iteration
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
index ed46f3753ceb8..6e326b133f981 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
declare void @llvm.amdgcn.global.load.async.to.lds.b8(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol)
declare void @llvm.amdgcn.global.load.async.to.lds.b32(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol)
``````````
</details>
https://github.com/llvm/llvm-project/pull/192179
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