[llvm] f32f6a8 - [RISCV] Enable use of vfslide1up in lowerVPSpliceExperimental for bf16 vectors with Zvfbfa (#192169)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 14 20:25:02 PDT 2026
Author: Craig Topper
Date: 2026-04-14T20:24:57-07:00
New Revision: f32f6a829374239e68cb2e8bb2a00908cb248745
URL: https://github.com/llvm/llvm-project/commit/f32f6a829374239e68cb2e8bb2a00908cb248745
DIFF: https://github.com/llvm/llvm-project/commit/f32f6a829374239e68cb2e8bb2a00908cb248745.diff
LOG: [RISCV] Enable use of vfslide1up in lowerVPSpliceExperimental for bf16 vectors with Zvfbfa (#192169)
Added:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice-bf16.ll
llvm/test/CodeGen/RISCV/rvv/vp-splice-bf16.ll
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice.ll
llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index cc6b95607b2c2..1148b801530a0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14146,7 +14146,7 @@ RISCVTargetLowering::lowerVPSpliceExperimental(SDValue Op,
MVT EltVT = ContainerVT.getVectorElementType();
SDValue Result;
if ((EltVT == MVT::f16 && !Subtarget.hasVInstructionsF16()) ||
- EltVT == MVT::bf16) {
+ (EltVT == MVT::bf16 && !Subtarget.hasVInstructionsBF16())) {
EltVT = EltVT.changeTypeToInteger();
ContainerVT = ContainerVT.changeVectorElementType(EltVT);
Op2 = DAG.getBitcast(ContainerVT, Op2);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice-bf16.ll
new file mode 100644
index 0000000000000..c16501e719ff7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice-bf16.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv64 -mattr=+v,+experimental-zvfbfa -verify-machineinstrs \
+; RUN: < %s | FileCheck %s --check-prefixes=CHECK,NOVLDEP,ZVFBFA
+; RUN: llc -mtriple riscv64 -mattr=+v,+zfbfmin,+zvfbfmin -verify-machineinstrs \
+; RUN: < %s | FileCheck %s --check-prefixes=CHECK,NOVLDEP,ZVFBFMIN
+; RUN: llc -mtriple riscv64 -mattr=+v,+experimental-zvfbfa,+vl-dependent-latency -verify-machineinstrs \
+; RUN: < %s | FileCheck %s --check-prefixes=CHECK,VLDEP,ZVFBFA
+; RUN: llc -mtriple riscv64 -mattr=+v,+zfbfmin,+zvfbfmin,+vl-dependent-latency -verify-machineinstrs \
+; RUN: < %s | FileCheck %s --check-prefixes=CHECK,VLDEP,ZVFBFMIN
+
+define <8 x bfloat> @test_vp_splice_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
+; NOVLDEP-LABEL: test_vp_splice_v8bf16:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5
+; NOVLDEP-NEXT: addi a0, a0, -5
+; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: test_vp_splice_v8bf16:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: addi a0, a0, -5
+; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vi v8, v8, 5
+; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; VLDEP-NEXT: vslideup.vx v8, v9, a0
+; VLDEP-NEXT: ret
+ %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
+ ret <8 x bfloat> %v
+}
+
+define <8 x bfloat> @test_vp_splice_v8bf16_negative_offset(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
+; NOVLDEP-LABEL: test_vp_splice_v8bf16_negative_offset:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: addi a0, a0, -5
+; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 5
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: test_vp_splice_v8bf16_negative_offset:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: addi a0, a0, -5
+; VLDEP-NEXT: vsetivli zero, 5, e16, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 5
+; VLDEP-NEXT: ret
+ %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 -5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
+ ret <8 x bfloat> %v
+}
+
+define <8 x bfloat> @test_vp_splice_v8bf16_masked(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
+; NOVLDEP-LABEL: test_vp_splice_v8bf16_masked:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -5
+; NOVLDEP-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: test_vp_splice_v8bf16_masked:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: addi a0, a0, -5
+; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t
+; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, mu
+; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t
+; VLDEP-NEXT: ret
+ %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)
+ ret <8 x bfloat> %v
+}
+
+define <4 x bfloat> @test_vp_splice_v4b16_with_firstelt(bfloat %first, <4 x bfloat> %vb, <4 x i1> %mask, i32 zeroext %evl) {
+; ZVFBFA-LABEL: test_vp_splice_v4b16_with_firstelt:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfslide1up.vf v9, v8, fa0, v0.t
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: test_vp_splice_v4b16_with_firstelt:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: fmv.x.h a1, fa0
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vslide1up.vx v9, v8, a1, v0.t
+; ZVFBFMIN-NEXT: vmv1r.v v8, v9
+; ZVFBFMIN-NEXT: ret
+ %va = insertelement <4 x bfloat> poison, bfloat %first, i32 0
+ %v = call <4 x bfloat> @llvm.experimental.vp.splice.v4b16(<4 x bfloat> %va, <4 x bfloat> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
+ ret <4 x bfloat> %v
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice.ll
index 73c2e06f14d63..aeac235f5867e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice.ll
@@ -506,27 +506,27 @@ define <4 x i32> @test_vp_splice_v4i32_with_splat_firstelt(i32 %first, <4 x i32>
ret <4 x i32> %v
}
-define <4 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <4 x float> %vb, <4 x i1> %mask, i32 zeroext %evl) {
-; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:
+define <4 x float> @test_vp_splice_v4f32_with_firstelt(float %first, <4 x float> %vb, <4 x i1> %mask, i32 zeroext %evl) {
+; CHECK-LABEL: test_vp_splice_v4f32_with_firstelt:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vfslide1up.vf v9, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
%va = insertelement <4 x float> poison, float %first, i32 0
- %v = call <4 x float> @llvm.experimental.vp.splice.nxv2f32(<4 x float> %va, <4 x float> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
+ %v = call <4 x float> @llvm.experimental.vp.splice.v4f32(<4 x float> %va, <4 x float> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
ret <4 x float> %v
}
-define <4 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <4 x half> %vb, <4 x i1> %mask, i32 zeroext %evl) {
-; ZVFH-LABEL: test_vp_splice_nxv2f16_with_firstelt:
+define <4 x half> @test_vp_splice_v4f16_with_firstelt(half %first, <4 x half> %vb, <4 x i1> %mask, i32 zeroext %evl) {
+; ZVFH-LABEL: test_vp_splice_v4f16_with_firstelt:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFH-NEXT: vfslide1up.vf v9, v8, fa0, v0.t
; ZVFH-NEXT: vmv1r.v v8, v9
; ZVFH-NEXT: ret
;
-; ZVFHMIN-LABEL: test_vp_splice_nxv2f16_with_firstelt:
+; ZVFHMIN-LABEL: test_vp_splice_v4f16_with_firstelt:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
@@ -534,72 +534,6 @@ define <4 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <4 x half>
; ZVFHMIN-NEXT: vmv1r.v v8, v9
; ZVFHMIN-NEXT: ret
%va = insertelement <4 x half> poison, half %first, i32 0
- %v = call <4 x half> @llvm.experimental.vp.splice.nxv2f16(<4 x half> %va, <4 x half> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
+ %v = call <4 x half> @llvm.experimental.vp.splice.v4f16(<4 x half> %va, <4 x half> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
ret <4 x half> %v
}
-
-define <8 x bfloat> @test_vp_splice_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
-; NOVLDEP-LABEL: test_vp_splice_v8bf16:
-; NOVLDEP: # %bb.0:
-; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5
-; NOVLDEP-NEXT: addi a0, a0, -5
-; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
-; NOVLDEP-NEXT: ret
-;
-; VLDEP-LABEL: test_vp_splice_v8bf16:
-; VLDEP: # %bb.0:
-; VLDEP-NEXT: addi a0, a0, -5
-; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; VLDEP-NEXT: vslidedown.vi v8, v8, 5
-; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v9, a0
-; VLDEP-NEXT: ret
-
- %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
- ret <8 x bfloat> %v
-}
-
-define <8 x bfloat> @test_vp_splice_v8bf16_negative_offset(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
-; NOVLDEP-LABEL: test_vp_splice_v8bf16_negative_offset:
-; NOVLDEP: # %bb.0:
-; NOVLDEP-NEXT: addi a0, a0, -5
-; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v9, 5
-; NOVLDEP-NEXT: ret
-;
-; VLDEP-LABEL: test_vp_splice_v8bf16_negative_offset:
-; VLDEP: # %bb.0:
-; VLDEP-NEXT: addi a0, a0, -5
-; VLDEP-NEXT: vsetivli zero, 5, e16, m1, ta, ma
-; VLDEP-NEXT: vslidedown.vx v8, v8, a0
-; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v9, 5
-; VLDEP-NEXT: ret
-
- %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 -5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
- ret <8 x bfloat> %v
-}
-
-define <8 x bfloat> @test_vp_splice_v8bf16_masked(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
-; NOVLDEP-LABEL: test_vp_splice_v8bf16_masked:
-; NOVLDEP: # %bb.0:
-; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t
-; NOVLDEP-NEXT: addi a0, a0, -5
-; NOVLDEP-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t
-; NOVLDEP-NEXT: ret
-;
-; VLDEP-LABEL: test_vp_splice_v8bf16_masked:
-; VLDEP: # %bb.0:
-; VLDEP-NEXT: addi a0, a0, -5
-; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; VLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t
-; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t
-; VLDEP-NEXT: ret
- %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)
- ret <8 x bfloat> %v
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-bf16.ll
new file mode 100644
index 0000000000000..2bd4879abb9c2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-bf16.ll
@@ -0,0 +1,97 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv64 -mattr=+v,+zfh,+zfbfmin,+experimental-zvfbfa \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NOVLDEP,ZVFH
+; RUN: llc -mtriple riscv64 -mattr=+v,+zfh,+zfbfmin,+zvfbfmin \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NOVLDEP,ZVFHMIN
+; RUN: llc -mtriple riscv64 -mattr=+v,+zfh,+zfbfmin,+experimental-zvfbfa,+vl-dependent-latency \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLDEP,ZVFH
+; RUN: llc -mtriple riscv64 -mattr=+v,+zfbfmin,+zvfbfmin,+vl-dependent-latency \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLDEP,ZVFHMIN
+
+define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
+; NOVLDEP-LABEL: test_vp_splice_nxv2bf16:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3
+; NOVLDEP-NEXT: addi a0, a0, -3
+; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: test_vp_splice_nxv2bf16:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: addi a0, a0, -3
+; VLDEP-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; VLDEP-NEXT: vslidedown.vi v8, v8, 3
+; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; VLDEP-NEXT: vslideup.vx v8, v9, a0
+; VLDEP-NEXT: ret
+ %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
+ ret <vscale x 2 x bfloat> %v
+}
+
+define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_negative_offset(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
+; NOVLDEP-LABEL: test_vp_splice_nxv2bf16_negative_offset:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: addi a0, a0, -3
+; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 3
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: test_vp_splice_nxv2bf16_negative_offset:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: addi a0, a0, -3
+; VLDEP-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 3
+; VLDEP-NEXT: ret
+ %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
+ ret <vscale x 2 x bfloat> %v
+}
+
+define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_masked(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
+; NOVLDEP-LABEL: test_vp_splice_nxv2bf16_masked:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
+; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -3
+; NOVLDEP-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
+; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: test_vp_splice_nxv2bf16_masked:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: addi a0, a0, -3
+; VLDEP-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; VLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t
+; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
+; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t
+; VLDEP-NEXT: ret
+ %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
+ ret <vscale x 2 x bfloat> %v
+}
+
+define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_with_firstelt(bfloat %first, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {
+; ZVFH-LABEL: test_vp_splice_nxv2bf16_with_firstelt:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma
+; ZVFH-NEXT: vfslide1up.vf v9, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: test_vp_splice_nxv2bf16_with_firstelt:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vslide1up.vx v9, v8, a1, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v9
+; ZVFHMIN-NEXT: ret
+ %va = insertelement <vscale x 2 x bfloat> poison, bfloat %first, i32 0
+ %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
+ ret <vscale x 2 x bfloat> %v
+}
+
+attributes #0 = { nounwind vscale_range(2,0) }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
index b83ddce61f44d..416f092df0c85 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
@@ -671,70 +671,6 @@ define <vscale x 2 x half> @test_vp_splice_nxv2f16_masked(<vscale x 2 x half> %v
ret <vscale x 2 x half> %v
}
-define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
-; NOVLDEP-LABEL: test_vp_splice_nxv2bf16:
-; NOVLDEP: # %bb.0:
-; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3
-; NOVLDEP-NEXT: addi a0, a0, -3
-; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
-; NOVLDEP-NEXT: ret
-;
-; VLDEP-LABEL: test_vp_splice_nxv2bf16:
-; VLDEP: # %bb.0:
-; VLDEP-NEXT: addi a0, a0, -3
-; VLDEP-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; VLDEP-NEXT: vslidedown.vi v8, v8, 3
-; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v9, a0
-; VLDEP-NEXT: ret
- %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
- ret <vscale x 2 x bfloat> %v
-}
-
-define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_negative_offset(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
-; NOVLDEP-LABEL: test_vp_splice_nxv2bf16_negative_offset:
-; NOVLDEP: # %bb.0:
-; NOVLDEP-NEXT: addi a0, a0, -3
-; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v9, 3
-; NOVLDEP-NEXT: ret
-;
-; VLDEP-LABEL: test_vp_splice_nxv2bf16_negative_offset:
-; VLDEP: # %bb.0:
-; VLDEP-NEXT: addi a0, a0, -3
-; VLDEP-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
-; VLDEP-NEXT: vslidedown.vx v8, v8, a0
-; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v9, 3
-; VLDEP-NEXT: ret
- %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
- ret <vscale x 2 x bfloat> %v
-}
-
-define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_masked(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
-; NOVLDEP-LABEL: test_vp_splice_nxv2bf16_masked:
-; NOVLDEP: # %bb.0:
-; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t
-; NOVLDEP-NEXT: addi a0, a0, -3
-; NOVLDEP-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t
-; NOVLDEP-NEXT: ret
-;
-; VLDEP-LABEL: test_vp_splice_nxv2bf16_masked:
-; VLDEP: # %bb.0:
-; VLDEP-NEXT: addi a0, a0, -3
-; VLDEP-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; VLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t
-; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t
-; VLDEP-NEXT: ret
- %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
- ret <vscale x 2 x bfloat> %v
-}
-
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {
; CHECK-LABEL: test_vp_splice_nxv2i32_with_firstelt:
; CHECK: # %bb.0:
@@ -792,17 +728,4 @@ define <vscale x 2 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <v
ret <vscale x 2 x half> %v
}
-define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_with_firstelt(bfloat %first, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {
-; CHECK-LABEL: test_vp_splice_nxv2bf16_with_firstelt:
-; CHECK: # %bb.0:
-; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vslide1up.vx v9, v8, a1, v0.t
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: ret
- %va = insertelement <vscale x 2 x bfloat> poison, bfloat %first, i32 0
- %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
- ret <vscale x 2 x bfloat> %v
-}
-
attributes #0 = { nounwind vscale_range(2,0) }
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