[llvm] 4800482 - [RISCV] Add test showing constant materialization using pli.h/pli.w+srli/slli. NFC (#192159)

[via llvm-commits]

Author: Craig Topper
Date: 2026-04-14T18:50:10-07:00
New Revision: 480048253f117cff5e93bb5bbced94a6ef24adc6

URL: https://github.com/llvm/llvm-project/commit/480048253f117cff5e93bb5bbced94a6ef24adc6
DIFF: https://github.com/llvm/llvm-project/commit/480048253f117cff5e93bb5bbced94a6ef24adc6.diff

LOG: [RISCV] Add test showing constant materialization using pli.h/pli.w+srli/slli. NFC (#192159)

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64p.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll
index b4f74a970c9c0..d4a5e054d312d 100644
--- a/llvm/test/CodeGen/RISCV/rv64p.ll
+++ b/llvm/test/CodeGen/RISCV/rv64p.ll
@@ -119,6 +119,24 @@ define i64 @pli_h_i64() {
   ret i64 u0x0123012301230123
 }
 
+define i64 @pli_h_slli_i64() {
+; CHECK-LABEL: pli_h_slli_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.h a0, 511
+; CHECK-NEXT:    slli a0, a0, 3
+; CHECK-NEXT:    ret
+  ret i64 u0x0ff80ff80ff80ff8
+}
+
+define i64 @pli_h_srli_i64() {
+; CHECK-LABEL: pli_h_srli_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.h a0, -240
+; CHECK-NEXT:    srli a0, a0, 4
+; CHECK-NEXT:    ret
+  ret i64 u0x0ff10ff10ff10ff1
+}
+
 define i64 @pli_w_i64() {
 ; CHECK-LABEL: pli_w_i64:
 ; CHECK:       # %bb.0:
@@ -127,6 +145,24 @@ define i64 @pli_w_i64() {
   ret i64 u0xfffffedcfffffedc
 }
 
+define i64 @pli_w_slli_i64() {
+; CHECK-LABEL: pli_w_slli_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.w a0, 511
+; CHECK-NEXT:    slli a0, a0, 7
+; CHECK-NEXT:    ret
+  ret i64 u0x0000ff800000ff80
+}
+
+define i64 @pli_w_srli_i64() {
+; CHECK-LABEL: pli_w_srli_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pli.w a0, -480
+; CHECK-NEXT:    srli a0, a0, 5
+; CHECK-NEXT:    ret
+  ret i64 u0x07fffff107fffff1
+}
+
 define void @pli_b_store_i32(ptr %p) {
 ; CHECK-LABEL: pli_b_store_i32:
 ; CHECK:       # %bb.0: