[llvm] [AMDGPU][GlobalISel] Implement missing rules for G_TRUNC legalization (PR #180647)
Anshil Gandhi via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 14 18:05:36 PDT 2026
https://github.com/gandhi56 updated https://github.com/llvm/llvm-project/pull/180647
>From 30186a43d712662e5f2083d95e9dbacc065b3a41 Mon Sep 17 00:00:00 2001
From: Anshil Gandhi <Anshil.Gandhi at amd.com>
Date: Mon, 9 Feb 2026 17:45:31 -0600
Subject: [PATCH] [AMDGPU][GlobalISel] Use UniBRC/DivBRC wildcards for G_TRUNC
reg bank rules
Implement G_TRUNC (result, source) register bank rules for sizes
{32, 64, 96, 128, 160, 256, 512} with two generic wildcard
rules using UniBRC/DivBRC predicates and SgprBRC/VgprBRC apply IDs.
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 8 +-
.../CodeGen/AMDGPU/GlobalISel/trunc-brc.ll | 507 ++++++++++++++++++
.../AMDGPU/buffer-fat-pointers-memcpy.ll | 358 +++++++------
3 files changed, 698 insertions(+), 175 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index c3157c9441027..b2801ce45cf34 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -762,14 +762,16 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
// In global-isel G_TRUNC in-reg is treated as no-op, inst selected into COPY.
// It is up to user to deal with truncated bits.
+ // S1, S16, S32 and S64 results are handled with specific rules. Remaining
+ // (result, source) pairs with valid register classes are covered by the
+ // generic UniBRC/DivBRC wildcard rules.
addRulesForGOpcs({G_TRUNC})
.Any({{UniS1, UniS16}, {{None}, {None}}}) // should be combined away
.Any({{UniS1, UniS32}, {{None}, {None}}}) // should be combined away
.Any({{UniS1, UniS64}, {{None}, {None}}}) // should be combined away
.Any({{UniS16, S32}, {{Sgpr16}, {Sgpr32}}})
- .Any({{DivS16, S32}, {{Vgpr16}, {Vgpr32}}})
- .Any({{UniS32, S64}, {{Sgpr32}, {Sgpr64}}})
- .Any({{DivS32, S64}, {{Vgpr32}, {Vgpr64}}})
+ .Any({{UniBRC, UniBRC}, {{SgprBRC}, {SgprBRC}}})
+ .Any({{DivBRC, DivBRC}, {{VgprBRC}, {VgprBRC}}})
.Any({{UniV2S16, V2S32}, {{SgprV2S16}, {SgprV2S32}}})
.Any({{DivV2S16, V2S32}, {{VgprV2S16}, {VgprV2S32}}})
// This is non-trivial. VgprToVccCopy is done using compare instruction.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
new file mode 100644
index 0000000000000..152133c205b87
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
@@ -0,0 +1,507 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx950 -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX-950 %s
+
+;; BRC trunc tests - exercises UniBRC/DivBRC wildcard rules.
+;; Each pair covers a unique subregister extraction sequence.
+
+; --- sub0: 32-bit from 64-bit ---
+
+define amdgpu_ps void @s_trunc_i64_to_i32(ptr addrspace(1) inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i64_to_i32
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (s64) from %ir.src, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub0
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD_SADDR [[V_MOV_B32_e32_]], [[COPY5]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (s32) into %ir.dst, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %val = load i64, ptr addrspace(1) %src
+ %trunc = trunc i64 %val to i32
+ store i32 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i64_to_i32(ptr addrspace(1) %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i64_to_i32
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load (s64) from %ir.src, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub0
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE1]], [[COPY4]], 0, 0, implicit $exec :: (store (s32) into %ir.dst, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %val = load i64, ptr addrspace(1) %src
+ %trunc = trunc i64 %val to i32
+ store i32 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1: 64-bit from 96-bit ---
+
+define amdgpu_ps void @s_trunc_i96_to_i64(ptr addrspace(1) inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i96_to_i64
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<2 x s32>) from %ir.src, addrspace 1)
+ ; GFX-950-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[REG_SEQUENCE]], 8, 0 :: ("amdgpu-noclobber" load (s32) from %ir.src + 8, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub0
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[S_LOAD_DWORD_IMM]], %subreg.sub2
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE2]].sub0_sub1
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:vreg_64_align2 = COPY [[COPY6]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[COPY7]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (s64) into %ir.dst, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %val = load i96, ptr addrspace(1) %src
+ %trunc = trunc i96 %val to i64
+ store i64 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i96_to_i64(ptr addrspace(1) %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i96_to_i64
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load (<3 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vreg_64_align2 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub0_sub1
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY4]], 0, 0, implicit $exec :: (store (s64) into %ir.dst, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %val = load i96, ptr addrspace(1) %src
+ %trunc = trunc i96 %val to i64
+ store i64 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1_sub2: 96-bit from 128-bit ---
+
+define amdgpu_ps void @s_trunc_i128_to_i96(ptr addrspace(1) inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i128_to_i96
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: early-clobber %9:sgpr_128 = S_LOAD_DWORDX4_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sgpr_96 = COPY %9.sub0_sub1_sub2
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vreg_96_align2 = COPY [[COPY4]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX3_SADDR [[V_MOV_B32_e32_]], [[COPY5]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %val = load i128, ptr addrspace(1) %src
+ %trunc = trunc i128 %val to i96
+ store i96 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i128_to_i96(ptr addrspace(1) %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i128_to_i96
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vreg_96_align2 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0_sub1_sub2
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY4]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %val = load i128, ptr addrspace(1) %src
+ %trunc = trunc i128 %val to i96
+ store i96 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1_sub2_sub3: 128-bit from 160-bit ---
+
+define amdgpu_ps void @s_trunc_i160_to_i128(ptr addrspace(1) inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i160_to_i128
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: early-clobber %10:sgpr_128 = S_LOAD_DWORDX4_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[REG_SEQUENCE]], 16, 0 :: ("amdgpu-noclobber" load (s32) from %ir.src + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY %10.sub0
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY %10.sub1
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY %10.sub2
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY %10.sub3
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_160 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3, [[S_LOAD_DWORD_IMM]], %subreg.sub4
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:sgpr_128 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:vreg_128_align2 = COPY [[COPY8]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY9]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %val = load i160, ptr addrspace(1) %src
+ %trunc = trunc i160 %val to i128
+ store i128 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i160_to_i128(ptr addrspace(1) %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i160_to_i128
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[REG_SEQUENCE]], 16, 0, implicit $exec :: (load (s32) from %ir.src + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub1
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub2
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub3
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_160_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3, [[GLOBAL_LOAD_DWORD]], %subreg.sub4
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %val = load i160, ptr addrspace(1) %src
+ %trunc = trunc i160 %val to i128
+ store i128 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1_sub2_sub3_sub4: 160-bit from 192-bit ---
+
+define amdgpu_ps void @s_trunc_i192_to_i160(ptr addrspace(1) inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i192_to_i160
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: early-clobber %18:sgpr_128 = S_LOAD_DWORDX4_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[REG_SEQUENCE]], 16, 0 :: ("amdgpu-noclobber" load (<2 x s32>) from %ir.src + 16, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY %18.sub0
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY %18.sub1
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY %18.sub2
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY %18.sub3
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub0
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_192 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3, [[COPY8]], %subreg.sub4, [[COPY9]], %subreg.sub5
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:sgpr_160 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3_sub4
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[COPY10]].sub0
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[COPY10]].sub1
+ ; GFX-950-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[COPY10]].sub2
+ ; GFX-950-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[COPY10]].sub3
+ ; GFX-950-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[COPY10]].sub4
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY11]], %subreg.sub0, [[COPY12]], %subreg.sub1, [[COPY13]], %subreg.sub2, [[COPY14]], %subreg.sub3
+ ; GFX-950-NEXT: [[COPY16:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE3]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY16]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY15]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD_SADDR [[V_MOV_B32_e32_1]], [[COPY17]], [[REG_SEQUENCE1]], 16, 0, implicit $exec :: (store (s32) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %val = load i192, ptr addrspace(1) %src
+ %trunc = trunc i192 %val to i160
+ store i160 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i192_to_i160(ptr addrspace(1) %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i192_to_i160
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE]], 16, 0, implicit $exec :: (load (<2 x s32>) from %ir.src + 16, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub1
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub2
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub3
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub0
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_192_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3, [[COPY8]], %subreg.sub4, [[COPY9]], %subreg.sub5
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:vreg_160_align2 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3_sub4
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub0
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub1
+ ; GFX-950-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub2
+ ; GFX-950-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub3
+ ; GFX-950-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub4
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY11]], %subreg.sub0, [[COPY12]], %subreg.sub1, [[COPY13]], %subreg.sub2, [[COPY14]], %subreg.sub3
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE1]], [[COPY15]], 16, 0, implicit $exec :: (store (s32) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %val = load i192, ptr addrspace(1) %src
+ %trunc = trunc i192 %val to i160
+ store i160 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1_sub2_sub3_sub4_sub5: 192-bit from 224-bit ---
+
+define amdgpu_ps void @s_trunc_i224_to_i192(ptr addrspace(1) inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i224_to_i192
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: early-clobber %16:sgpr_128 = S_LOAD_DWORDX4_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[REG_SEQUENCE]], 16, 0 :: ("amdgpu-noclobber" load (<2 x s32>) from %ir.src + 16, addrspace 1)
+ ; GFX-950-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[REG_SEQUENCE]], 24, 0 :: ("amdgpu-noclobber" load (s32) from %ir.src + 24, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub0
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub1
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY %16.sub0
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY %16.sub1
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY %16.sub2
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY %16.sub3
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_224 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY8]], %subreg.sub2, [[COPY9]], %subreg.sub3, [[COPY4]], %subreg.sub4, [[COPY5]], %subreg.sub5, [[S_LOAD_DWORD_IMM]], %subreg.sub6
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:sgpr_192 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3_sub4_sub5
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[COPY10]].sub0_sub1
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[COPY10]].sub2_sub3
+ ; GFX-950-NEXT: [[COPY13:%[0-9]+]]:sreg_64 = COPY [[COPY10]].sub4_sub5
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY11]], %subreg.sub0_sub1, [[COPY12]], %subreg.sub2_sub3
+ ; GFX-950-NEXT: [[COPY14:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE3]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY14]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY15:%[0-9]+]]:vreg_64_align2 = COPY [[COPY13]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_1]], [[COPY15]], [[REG_SEQUENCE1]], 16, 0, implicit $exec :: (store (<2 x s32>) into %ir.dst + 16, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %val = load i224, ptr addrspace(1) %src
+ %trunc = trunc i224 %val to i192
+ store i192 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i224_to_i192(ptr addrspace(1) %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i224_to_i192
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX3_:%[0-9]+]]:vreg_96_align2 = GLOBAL_LOAD_DWORDX3 [[REG_SEQUENCE]], 16, 0, implicit $exec :: (load (<3 x s32>) from %ir.src + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub0
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub1
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub2
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub3
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub0
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub1
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub2
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_224_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3, [[COPY8]], %subreg.sub4, [[COPY9]], %subreg.sub5, [[COPY10]], %subreg.sub6
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:vreg_192_align2 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3_sub4_sub5
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:vreg_64_align2 = COPY [[COPY11]].sub0_sub1
+ ; GFX-950-NEXT: [[COPY13:%[0-9]+]]:vreg_64_align2 = COPY [[COPY11]].sub2_sub3
+ ; GFX-950-NEXT: [[COPY14:%[0-9]+]]:vreg_64_align2 = COPY [[COPY11]].sub4_sub5
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY12]], %subreg.sub0_sub1, [[COPY13]], %subreg.sub2_sub3
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY14]], 16, 0, implicit $exec :: (store (<2 x s32>) into %ir.dst + 16, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %val = load i224, ptr addrspace(1) %src
+ %trunc = trunc i224 %val to i192
+ store i192 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1_sub2_sub3_sub4_sub5_sub6: 224-bit from 256-bit ---
+
+define amdgpu_ps void @s_trunc_i256_to_i224(ptr addrspace(1) inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i256_to_i224
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: early-clobber %20:sgpr_256 = S_LOAD_DWORDX8_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<8 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sgpr_224 = COPY %20.lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub0
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub1
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub2
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub3
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub4
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub5
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub6
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1, [[COPY7]], %subreg.sub2, [[COPY8]], %subreg.sub3
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE2]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY12]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY13:%[0-9]+]]:vreg_96_align2 = COPY [[REG_SEQUENCE3]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX3_SADDR [[V_MOV_B32_e32_1]], [[COPY13]], [[REG_SEQUENCE1]], 16, 0, implicit $exec :: (store (<3 x s32>) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %val = load i256, ptr addrspace(1) %src
+ %trunc = trunc i256 %val to i224
+ store i224 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i256_to_i224(ptr addrspace(1) %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i256_to_i224
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_1:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 16, 0, implicit $exec :: (load (<4 x s32>) from %ir.src + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_256_align2 = REG_SEQUENCE [[GLOBAL_LOAD_DWORDX4_]], %subreg.sub0_sub1_sub2_sub3, [[GLOBAL_LOAD_DWORDX4_1]], %subreg.sub4_sub5_sub6_sub7
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vreg_224_align2 = COPY [[REG_SEQUENCE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub0
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub1
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub2
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub3
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub4
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub5
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub6
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1, [[COPY7]], %subreg.sub2, [[COPY8]], %subreg.sub3
+ ; GFX-950-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE4]], 16, 0, implicit $exec :: (store (<3 x s32>) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %val = load i256, ptr addrspace(1) %src
+ %trunc = trunc i256 %val to i224
+ store i224 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0..sub15: 512-bit from 1024-bit ---
+
+define amdgpu_ps void @s_trunc_i1024_to_i512(ptr addrspace(1) inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i1024_to_i512
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: early-clobber %20:sgpr_512 = S_LOAD_DWORDX16_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<16 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: early-clobber %23:sgpr_512 = S_LOAD_DWORDX16_IMM_ec [[REG_SEQUENCE]], 64, 0 :: ("amdgpu-noclobber" load (<16 x s32>) from %ir.src + 64, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_1024 = REG_SEQUENCE %20, %subreg.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, %23, %subreg.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sgpr_512 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sgpr_128 = COPY [[COPY4]].sub0_sub1_sub2_sub3
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sgpr_128 = COPY [[COPY4]].sub4_sub5_sub6_sub7
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY [[COPY4]].sub8_sub9_sub10_sub11
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:sgpr_128 = COPY [[COPY4]].sub12_sub13_sub14_sub15
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:vreg_128_align2 = COPY [[COPY5]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY9]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:vreg_128_align2 = COPY [[COPY6]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_1]], [[COPY10]], [[REG_SEQUENCE1]], 16, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:vreg_128_align2 = COPY [[COPY7]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_2]], [[COPY11]], [[REG_SEQUENCE1]], 32, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 32, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:vreg_128_align2 = COPY [[COPY8]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_3]], [[COPY12]], [[REG_SEQUENCE1]], 48, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 48, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %val = load i1024, ptr addrspace(1) %src
+ %trunc = trunc i1024 %val to i512
+ store i512 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i1024_to_i512(ptr addrspace(1) %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i1024_to_i512
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_1:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 16, 0, implicit $exec :: (load (<4 x s32>) from %ir.src + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_2:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 32, 0, implicit $exec :: (load (<4 x s32>) from %ir.src + 32, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_3:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 48, 0, implicit $exec :: (load (<4 x s32>) from %ir.src + 48, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_512_align2 = REG_SEQUENCE [[GLOBAL_LOAD_DWORDX4_]], %subreg.sub0_sub1_sub2_sub3, [[GLOBAL_LOAD_DWORDX4_1]], %subreg.sub4_sub5_sub6_sub7, [[GLOBAL_LOAD_DWORDX4_2]], %subreg.sub8_sub9_sub10_sub11, [[GLOBAL_LOAD_DWORDX4_3]], %subreg.sub12_sub13_sub14_sub15
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_4:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 64, 0, implicit $exec :: (load (<4 x s32>) from %ir.src + 64, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_5:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 80, 0, implicit $exec :: (load (<4 x s32>) from %ir.src + 80, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_6:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 96, 0, implicit $exec :: (load (<4 x s32>) from %ir.src + 96, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_7:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 112, 0, implicit $exec :: (load (<4 x s32>) from %ir.src + 112, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_512_align2 = REG_SEQUENCE [[GLOBAL_LOAD_DWORDX4_4]], %subreg.sub0_sub1_sub2_sub3, [[GLOBAL_LOAD_DWORDX4_5]], %subreg.sub4_sub5_sub6_sub7, [[GLOBAL_LOAD_DWORDX4_6]], %subreg.sub8_sub9_sub10_sub11, [[GLOBAL_LOAD_DWORDX4_7]], %subreg.sub12_sub13_sub14_sub15
+ ; GFX-950-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_1024_align2 = REG_SEQUENCE [[REG_SEQUENCE2]], %subreg.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, [[REG_SEQUENCE3]], %subreg.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vreg_512_align2 = COPY [[REG_SEQUENCE4]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vreg_128_align2 = COPY [[COPY4]].sub0_sub1_sub2_sub3
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vreg_128_align2 = COPY [[COPY4]].sub4_sub5_sub6_sub7
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:vreg_128_align2 = COPY [[COPY4]].sub8_sub9_sub10_sub11
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:vreg_128_align2 = COPY [[COPY4]].sub12_sub13_sub14_sub15
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY5]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY6]], 16, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY7]], 32, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 32, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY8]], 48, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 48, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %val = load i1024, ptr addrspace(1) %src
+ %trunc = trunc i1024 %val to i512
+ store i512 %trunc, ptr addrspace(1) %dst
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
index 1e79c4f63cd42..5fefe8e178ee9 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefix=SDAG-GFX942 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=SDAG-GFX1100 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL-GFX942 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL-GFX1100 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GISEL-GFX942 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GISEL-GFX1100 %s
; Note: if you're adding tests here, also add them to
; lower-buffer-fat-pointers-mem-transfer.ll to verify the IR produced by
@@ -410,7 +410,6 @@ define amdgpu_kernel void @memcpy_known(ptr addrspace(7) %src, ptr addrspace(7)
; GISEL-GFX942-NEXT: s_load_dword s11, s[4:5], 0x34
; GISEL-GFX942-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x44
; GISEL-GFX942-NEXT: s_mov_b32 s16, 0
-; GISEL-GFX942-NEXT: v_mov_b32_e32 v0, 0x2000
; GISEL-GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-GFX942-NEXT: s_mov_b32 s8, s1
; GISEL-GFX942-NEXT: s_mov_b32 s9, s2
@@ -418,65 +417,72 @@ define amdgpu_kernel void @memcpy_known(ptr addrspace(7) %src, ptr addrspace(7)
; GISEL-GFX942-NEXT: s_mov_b32 s4, s13
; GISEL-GFX942-NEXT: s_mov_b32 s5, s14
; GISEL-GFX942-NEXT: s_mov_b32 s6, s15
-; GISEL-GFX942-NEXT: v_mov_b32_e32 v1, s16
; GISEL-GFX942-NEXT: .LBB0_1: ; %static-memcpy-expansion-main-body
; GISEL-GFX942-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL-GFX942-NEXT: v_add_u32_e32 v62, s0, v1
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[2:5], v62, s[8:11], 0 offen
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[6:9], v62, s[8:11], 0 offen offset:16
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[10:13], v62, s[8:11], 0 offen offset:32
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[14:17], v62, s[8:11], 0 offen offset:48
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[18:21], v62, s[8:11], 0 offen offset:64
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[22:25], v62, s[8:11], 0 offen offset:80
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[26:29], v62, s[8:11], 0 offen offset:96
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[30:33], v62, s[8:11], 0 offen offset:112
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[34:37], v62, s[8:11], 0 offen offset:128
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[38:41], v62, s[8:11], 0 offen offset:144
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[42:45], v62, s[8:11], 0 offen offset:160
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[46:49], v62, s[8:11], 0 offen offset:176
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[50:53], v62, s[8:11], 0 offen offset:192
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[54:57], v62, s[8:11], 0 offen offset:208
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[58:61], v62, s[8:11], 0 offen offset:224
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 a[0:3], v62, s[8:11], 0 offen offset:240
-; GISEL-GFX942-NEXT: v_add_u32_e32 v63, s12, v1
-; GISEL-GFX942-NEXT: v_add_u32_e32 v1, 0x100, v1
-; GISEL-GFX942-NEXT: v_cmp_lt_u32_e32 vcc, v1, v0
-; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[2:5], v63, s[4:7], 0 offen
-; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[6:9], v63, s[4:7], 0 offen offset:16
-; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[10:13], v63, s[4:7], 0 offen offset:32
+; GISEL-GFX942-NEXT: s_add_i32 s1, s0, s16
+; GISEL-GFX942-NEXT: v_mov_b32_e32 v60, s1
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[8:11], v60, s[8:11], 0 offen
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[4:7], v60, s[8:11], 0 offen offset:16
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[12:15], v60, s[8:11], 0 offen offset:32
+; GISEL-GFX942-NEXT: s_add_i32 s2, s12, s16
+; GISEL-GFX942-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-GFX942-NEXT: s_addk_i32 s16, 0x100
+; GISEL-GFX942-NEXT: s_cmpk_lt_u32 s16, 0x2000
+; GISEL-GFX942-NEXT: s_waitcnt vmcnt(0)
+; GISEL-GFX942-NEXT: v_accvgpr_write_b32 a0, v15 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_write_b32 a1, v14 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_write_b32 a2, v13 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_write_b32 a3, v12 ; Reload Reuse
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[12:15], v60, s[8:11], 0 offen offset:48
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[16:19], v60, s[8:11], 0 offen offset:64
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[20:23], v60, s[8:11], 0 offen offset:80
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[24:27], v60, s[8:11], 0 offen offset:96
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[28:31], v60, s[8:11], 0 offen offset:112
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[32:35], v60, s[8:11], 0 offen offset:128
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[36:39], v60, s[8:11], 0 offen offset:144
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[40:43], v60, s[8:11], 0 offen offset:160
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[44:47], v60, s[8:11], 0 offen offset:176
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[48:51], v60, s[8:11], 0 offen offset:192
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[52:55], v60, s[8:11], 0 offen offset:208
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[56:59], v60, s[8:11], 0 offen offset:224
+; GISEL-GFX942-NEXT: s_nop 0
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[60:63], v60, s[8:11], 0 offen offset:240
+; GISEL-GFX942-NEXT: s_nop 0
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[8:11], v0, s[4:7], 0 offen
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[4:7], v0, s[4:7], 0 offen offset:16
+; GISEL-GFX942-NEXT: s_nop 1
+; GISEL-GFX942-NEXT: v_accvgpr_read_b32 v5, a0 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_read_b32 v4, a1 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_read_b32 v3, a2 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_read_b32 v2, a3 ; Reload Reuse
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[2:5], v0, s[4:7], 0 offen offset:32
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[14:17], v63, s[4:7], 0 offen offset:48
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[12:15], v0, s[4:7], 0 offen offset:48
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[18:21], v63, s[4:7], 0 offen offset:64
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[16:19], v0, s[4:7], 0 offen offset:64
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[22:25], v63, s[4:7], 0 offen offset:80
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[20:23], v0, s[4:7], 0 offen offset:80
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[26:29], v63, s[4:7], 0 offen offset:96
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[24:27], v0, s[4:7], 0 offen offset:96
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[30:33], v63, s[4:7], 0 offen offset:112
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[28:31], v0, s[4:7], 0 offen offset:112
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[34:37], v63, s[4:7], 0 offen offset:128
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[32:35], v0, s[4:7], 0 offen offset:128
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[38:41], v63, s[4:7], 0 offen offset:144
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[36:39], v0, s[4:7], 0 offen offset:144
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[42:45], v63, s[4:7], 0 offen offset:160
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[40:43], v0, s[4:7], 0 offen offset:160
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[46:49], v63, s[4:7], 0 offen offset:176
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[44:47], v0, s[4:7], 0 offen offset:176
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[50:53], v63, s[4:7], 0 offen offset:192
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[48:51], v0, s[4:7], 0 offen offset:192
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[54:57], v63, s[4:7], 0 offen offset:208
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[52:55], v0, s[4:7], 0 offen offset:208
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[58:61], v63, s[4:7], 0 offen offset:224
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[56:59], v0, s[4:7], 0 offen offset:224
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: scratch_store_dwordx4 off, a[0:3], off ; 16-byte Folded Spill
-; GISEL-GFX942-NEXT: scratch_load_dwordx4 v[2:5], off, off ; 16-byte Folded Reload
-; GISEL-GFX942-NEXT: s_waitcnt vmcnt(0)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[2:5], v63, s[4:7], 0 offen offset:240
-; GISEL-GFX942-NEXT: s_cbranch_vccnz .LBB0_1
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[60:63], v0, s[4:7], 0 offen offset:240
+; GISEL-GFX942-NEXT: s_cbranch_scc1 .LBB0_1
; GISEL-GFX942-NEXT: ; %bb.2: ; %static-memcpy-post-expansion
; GISEL-GFX942-NEXT: s_endpgm
;
@@ -487,9 +493,7 @@ define amdgpu_kernel void @memcpy_known(ptr addrspace(7) %src, ptr addrspace(7)
; GISEL-GFX1100-NEXT: s_load_b128 s[8:11], s[4:5], 0x44
; GISEL-GFX1100-NEXT: s_load_b32 s7, s[4:5], 0x34
; GISEL-GFX1100-NEXT: s_load_b32 s15, s[4:5], 0x54
-; GISEL-GFX1100-NEXT: s_mov_b32 s4, 0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, s4
+; GISEL-GFX1100-NEXT: s_mov_b32 s16, 0
; GISEL-GFX1100-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-GFX1100-NEXT: s_mov_b32 s4, s1
; GISEL-GFX1100-NEXT: s_mov_b32 s5, s2
@@ -499,60 +503,63 @@ define amdgpu_kernel void @memcpy_known(ptr addrspace(7) %src, ptr addrspace(7)
; GISEL-GFX1100-NEXT: s_mov_b32 s14, s11
; GISEL-GFX1100-NEXT: .LBB0_1: ; %static-memcpy-expansion-main-body
; GISEL-GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL-GFX1100-NEXT: v_add_nc_u32_e32 v61, s0, v0
-; GISEL-GFX1100-NEXT: v_add_nc_u32_e32 v65, s8, v0
-; GISEL-GFX1100-NEXT: v_add_nc_u32_e32 v0, 0x100, v0
+; GISEL-GFX1100-NEXT: s_add_i32 s1, s0, s16
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-GFX1100-NEXT: v_mov_b32_e32 v60, s1
+; GISEL-GFX1100-NEXT: s_add_i32 s1, s8, s16
+; GISEL-GFX1100-NEXT: s_addk_i32 s16, 0x100
+; GISEL-GFX1100-NEXT: v_mov_b32_e32 v64, s1
+; GISEL-GFX1100-NEXT: s_cmpk_lt_u32 s16, 0x2000
; GISEL-GFX1100-NEXT: s_clause 0xf
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[1:4], v61, s[4:7], 0 offen
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[5:8], v61, s[4:7], 0 offen offset:16
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[9:12], v61, s[4:7], 0 offen offset:32
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[13:16], v61, s[4:7], 0 offen offset:48
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[17:20], v61, s[4:7], 0 offen offset:64
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[21:24], v61, s[4:7], 0 offen offset:80
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[25:28], v61, s[4:7], 0 offen offset:96
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[29:32], v61, s[4:7], 0 offen offset:112
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[33:36], v61, s[4:7], 0 offen offset:128
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[37:40], v61, s[4:7], 0 offen offset:144
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[41:44], v61, s[4:7], 0 offen offset:160
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[45:48], v61, s[4:7], 0 offen offset:176
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[49:52], v61, s[4:7], 0 offen offset:192
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[53:56], v61, s[4:7], 0 offen offset:208
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[57:60], v61, s[4:7], 0 offen offset:224
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[61:64], v61, s[4:7], 0 offen offset:240
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[0:3], v60, s[4:7], 0 offen
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[4:7], v60, s[4:7], 0 offen offset:16
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[8:11], v60, s[4:7], 0 offen offset:32
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[12:15], v60, s[4:7], 0 offen offset:48
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[16:19], v60, s[4:7], 0 offen offset:64
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[20:23], v60, s[4:7], 0 offen offset:80
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[24:27], v60, s[4:7], 0 offen offset:96
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[28:31], v60, s[4:7], 0 offen offset:112
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[32:35], v60, s[4:7], 0 offen offset:128
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[36:39], v60, s[4:7], 0 offen offset:144
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[40:43], v60, s[4:7], 0 offen offset:160
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[44:47], v60, s[4:7], 0 offen offset:176
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[48:51], v60, s[4:7], 0 offen offset:192
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[52:55], v60, s[4:7], 0 offen offset:208
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[56:59], v60, s[4:7], 0 offen offset:224
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[60:63], v60, s[4:7], 0 offen offset:240
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[1:4], v65, s[12:15], 0 offen
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[0:3], v64, s[12:15], 0 offen
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(14)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[5:8], v65, s[12:15], 0 offen offset:16
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[4:7], v64, s[12:15], 0 offen offset:16
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(13)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[9:12], v65, s[12:15], 0 offen offset:32
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[8:11], v64, s[12:15], 0 offen offset:32
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(12)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[13:16], v65, s[12:15], 0 offen offset:48
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[12:15], v64, s[12:15], 0 offen offset:48
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(11)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[17:20], v65, s[12:15], 0 offen offset:64
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[16:19], v64, s[12:15], 0 offen offset:64
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(10)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[21:24], v65, s[12:15], 0 offen offset:80
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[20:23], v64, s[12:15], 0 offen offset:80
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(9)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[25:28], v65, s[12:15], 0 offen offset:96
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[24:27], v64, s[12:15], 0 offen offset:96
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(8)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[29:32], v65, s[12:15], 0 offen offset:112
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[28:31], v64, s[12:15], 0 offen offset:112
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(7)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[33:36], v65, s[12:15], 0 offen offset:128
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[32:35], v64, s[12:15], 0 offen offset:128
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(6)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[37:40], v65, s[12:15], 0 offen offset:144
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[36:39], v64, s[12:15], 0 offen offset:144
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(5)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[41:44], v65, s[12:15], 0 offen offset:160
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[40:43], v64, s[12:15], 0 offen offset:160
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(4)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[45:48], v65, s[12:15], 0 offen offset:176
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[44:47], v64, s[12:15], 0 offen offset:176
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(3)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[49:52], v65, s[12:15], 0 offen offset:192
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[48:51], v64, s[12:15], 0 offen offset:192
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(2)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[53:56], v65, s[12:15], 0 offen offset:208
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[52:55], v64, s[12:15], 0 offen offset:208
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(1)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[57:60], v65, s[12:15], 0 offen offset:224
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[56:59], v64, s[12:15], 0 offen offset:224
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[61:64], v65, s[12:15], 0 offen offset:240
-; GISEL-GFX1100-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x2000, v0
-; GISEL-GFX1100-NEXT: s_cbranch_vccnz .LBB0_1
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[60:63], v64, s[12:15], 0 offen offset:240
+; GISEL-GFX1100-NEXT: s_cbranch_scc1 .LBB0_1
; GISEL-GFX1100-NEXT: ; %bb.2: ; %static-memcpy-post-expansion
; GISEL-GFX1100-NEXT: s_endpgm
call void @llvm.memcpy.p7.p7.i32(ptr addrspace(7) noundef nonnull align 16 %dst, ptr addrspace(7) noundef nonnull align 16 %src, i32 8192, i1 false)
@@ -942,7 +949,6 @@ define amdgpu_kernel void @memcpy_known_medium(ptr addrspace(7) %src, ptr addrsp
; GISEL-GFX942-NEXT: s_load_dword s11, s[4:5], 0x34
; GISEL-GFX942-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x44
; GISEL-GFX942-NEXT: s_mov_b32 s16, 0
-; GISEL-GFX942-NEXT: v_mov_b32_e32 v0, 0x100
; GISEL-GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-GFX942-NEXT: s_mov_b32 s8, s1
; GISEL-GFX942-NEXT: s_mov_b32 s9, s2
@@ -950,65 +956,72 @@ define amdgpu_kernel void @memcpy_known_medium(ptr addrspace(7) %src, ptr addrsp
; GISEL-GFX942-NEXT: s_mov_b32 s4, s13
; GISEL-GFX942-NEXT: s_mov_b32 s5, s14
; GISEL-GFX942-NEXT: s_mov_b32 s6, s15
-; GISEL-GFX942-NEXT: v_mov_b32_e32 v1, s16
; GISEL-GFX942-NEXT: .LBB1_1: ; %static-memcpy-expansion-main-body
; GISEL-GFX942-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL-GFX942-NEXT: v_add_u32_e32 v62, s0, v1
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[2:5], v62, s[8:11], 0 offen
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[6:9], v62, s[8:11], 0 offen offset:16
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[10:13], v62, s[8:11], 0 offen offset:32
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[14:17], v62, s[8:11], 0 offen offset:48
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[18:21], v62, s[8:11], 0 offen offset:64
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[22:25], v62, s[8:11], 0 offen offset:80
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[26:29], v62, s[8:11], 0 offen offset:96
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[30:33], v62, s[8:11], 0 offen offset:112
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[34:37], v62, s[8:11], 0 offen offset:128
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[38:41], v62, s[8:11], 0 offen offset:144
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[42:45], v62, s[8:11], 0 offen offset:160
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[46:49], v62, s[8:11], 0 offen offset:176
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[50:53], v62, s[8:11], 0 offen offset:192
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[54:57], v62, s[8:11], 0 offen offset:208
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[58:61], v62, s[8:11], 0 offen offset:224
-; GISEL-GFX942-NEXT: buffer_load_dwordx4 a[0:3], v62, s[8:11], 0 offen offset:240
-; GISEL-GFX942-NEXT: v_add_u32_e32 v63, s12, v1
-; GISEL-GFX942-NEXT: v_add_u32_e32 v1, 0x100, v1
-; GISEL-GFX942-NEXT: v_cmp_lt_u32_e32 vcc, v1, v0
-; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[2:5], v63, s[4:7], 0 offen
-; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[6:9], v63, s[4:7], 0 offen offset:16
-; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[10:13], v63, s[4:7], 0 offen offset:32
+; GISEL-GFX942-NEXT: s_add_i32 s1, s0, s16
+; GISEL-GFX942-NEXT: v_mov_b32_e32 v60, s1
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[8:11], v60, s[8:11], 0 offen
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[4:7], v60, s[8:11], 0 offen offset:16
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[12:15], v60, s[8:11], 0 offen offset:32
+; GISEL-GFX942-NEXT: s_add_i32 s2, s12, s16
+; GISEL-GFX942-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-GFX942-NEXT: s_addk_i32 s16, 0x100
+; GISEL-GFX942-NEXT: s_cmpk_lt_u32 s16, 0x100
+; GISEL-GFX942-NEXT: s_waitcnt vmcnt(0)
+; GISEL-GFX942-NEXT: v_accvgpr_write_b32 a0, v15 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_write_b32 a1, v14 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_write_b32 a2, v13 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_write_b32 a3, v12 ; Reload Reuse
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[12:15], v60, s[8:11], 0 offen offset:48
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[16:19], v60, s[8:11], 0 offen offset:64
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[20:23], v60, s[8:11], 0 offen offset:80
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[24:27], v60, s[8:11], 0 offen offset:96
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[28:31], v60, s[8:11], 0 offen offset:112
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[32:35], v60, s[8:11], 0 offen offset:128
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[36:39], v60, s[8:11], 0 offen offset:144
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[40:43], v60, s[8:11], 0 offen offset:160
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[44:47], v60, s[8:11], 0 offen offset:176
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[48:51], v60, s[8:11], 0 offen offset:192
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[52:55], v60, s[8:11], 0 offen offset:208
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[56:59], v60, s[8:11], 0 offen offset:224
+; GISEL-GFX942-NEXT: s_nop 0
+; GISEL-GFX942-NEXT: buffer_load_dwordx4 v[60:63], v60, s[8:11], 0 offen offset:240
+; GISEL-GFX942-NEXT: s_nop 0
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[8:11], v0, s[4:7], 0 offen
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[4:7], v0, s[4:7], 0 offen offset:16
+; GISEL-GFX942-NEXT: s_nop 1
+; GISEL-GFX942-NEXT: v_accvgpr_read_b32 v5, a0 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_read_b32 v4, a1 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_read_b32 v3, a2 ; Reload Reuse
+; GISEL-GFX942-NEXT: v_accvgpr_read_b32 v2, a3 ; Reload Reuse
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[2:5], v0, s[4:7], 0 offen offset:32
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[14:17], v63, s[4:7], 0 offen offset:48
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[12:15], v0, s[4:7], 0 offen offset:48
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[18:21], v63, s[4:7], 0 offen offset:64
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[16:19], v0, s[4:7], 0 offen offset:64
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[22:25], v63, s[4:7], 0 offen offset:80
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[20:23], v0, s[4:7], 0 offen offset:80
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[26:29], v63, s[4:7], 0 offen offset:96
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[24:27], v0, s[4:7], 0 offen offset:96
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[30:33], v63, s[4:7], 0 offen offset:112
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[28:31], v0, s[4:7], 0 offen offset:112
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[34:37], v63, s[4:7], 0 offen offset:128
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[32:35], v0, s[4:7], 0 offen offset:128
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[38:41], v63, s[4:7], 0 offen offset:144
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[36:39], v0, s[4:7], 0 offen offset:144
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[42:45], v63, s[4:7], 0 offen offset:160
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[40:43], v0, s[4:7], 0 offen offset:160
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[46:49], v63, s[4:7], 0 offen offset:176
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[44:47], v0, s[4:7], 0 offen offset:176
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[50:53], v63, s[4:7], 0 offen offset:192
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[48:51], v0, s[4:7], 0 offen offset:192
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[54:57], v63, s[4:7], 0 offen offset:208
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[52:55], v0, s[4:7], 0 offen offset:208
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[58:61], v63, s[4:7], 0 offen offset:224
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[56:59], v0, s[4:7], 0 offen offset:224
; GISEL-GFX942-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX942-NEXT: scratch_store_dwordx4 off, a[0:3], off ; 16-byte Folded Spill
-; GISEL-GFX942-NEXT: scratch_load_dwordx4 v[2:5], off, off ; 16-byte Folded Reload
-; GISEL-GFX942-NEXT: s_waitcnt vmcnt(0)
-; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[2:5], v63, s[4:7], 0 offen offset:240
-; GISEL-GFX942-NEXT: s_cbranch_vccnz .LBB1_1
+; GISEL-GFX942-NEXT: buffer_store_dwordx4 v[60:63], v0, s[4:7], 0 offen offset:240
+; GISEL-GFX942-NEXT: s_cbranch_scc1 .LBB1_1
; GISEL-GFX942-NEXT: ; %bb.2: ; %static-memcpy-post-expansion
; GISEL-GFX942-NEXT: s_endpgm
;
@@ -1019,9 +1032,7 @@ define amdgpu_kernel void @memcpy_known_medium(ptr addrspace(7) %src, ptr addrsp
; GISEL-GFX1100-NEXT: s_load_b128 s[8:11], s[4:5], 0x44
; GISEL-GFX1100-NEXT: s_load_b32 s7, s[4:5], 0x34
; GISEL-GFX1100-NEXT: s_load_b32 s15, s[4:5], 0x54
-; GISEL-GFX1100-NEXT: s_mov_b32 s4, 0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, s4
+; GISEL-GFX1100-NEXT: s_mov_b32 s16, 0
; GISEL-GFX1100-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-GFX1100-NEXT: s_mov_b32 s4, s1
; GISEL-GFX1100-NEXT: s_mov_b32 s5, s2
@@ -1031,60 +1042,63 @@ define amdgpu_kernel void @memcpy_known_medium(ptr addrspace(7) %src, ptr addrsp
; GISEL-GFX1100-NEXT: s_mov_b32 s14, s11
; GISEL-GFX1100-NEXT: .LBB1_1: ; %static-memcpy-expansion-main-body
; GISEL-GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL-GFX1100-NEXT: v_add_nc_u32_e32 v61, s0, v0
-; GISEL-GFX1100-NEXT: v_add_nc_u32_e32 v65, s8, v0
-; GISEL-GFX1100-NEXT: v_add_nc_u32_e32 v0, 0x100, v0
+; GISEL-GFX1100-NEXT: s_add_i32 s1, s0, s16
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-GFX1100-NEXT: v_mov_b32_e32 v60, s1
+; GISEL-GFX1100-NEXT: s_add_i32 s1, s8, s16
+; GISEL-GFX1100-NEXT: s_addk_i32 s16, 0x100
+; GISEL-GFX1100-NEXT: v_mov_b32_e32 v64, s1
+; GISEL-GFX1100-NEXT: s_cmpk_lt_u32 s16, 0x100
; GISEL-GFX1100-NEXT: s_clause 0xf
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[1:4], v61, s[4:7], 0 offen
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[5:8], v61, s[4:7], 0 offen offset:16
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[9:12], v61, s[4:7], 0 offen offset:32
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[13:16], v61, s[4:7], 0 offen offset:48
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[17:20], v61, s[4:7], 0 offen offset:64
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[21:24], v61, s[4:7], 0 offen offset:80
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[25:28], v61, s[4:7], 0 offen offset:96
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[29:32], v61, s[4:7], 0 offen offset:112
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[33:36], v61, s[4:7], 0 offen offset:128
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[37:40], v61, s[4:7], 0 offen offset:144
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[41:44], v61, s[4:7], 0 offen offset:160
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[45:48], v61, s[4:7], 0 offen offset:176
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[49:52], v61, s[4:7], 0 offen offset:192
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[53:56], v61, s[4:7], 0 offen offset:208
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[57:60], v61, s[4:7], 0 offen offset:224
-; GISEL-GFX1100-NEXT: buffer_load_b128 v[61:64], v61, s[4:7], 0 offen offset:240
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[0:3], v60, s[4:7], 0 offen
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[4:7], v60, s[4:7], 0 offen offset:16
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[8:11], v60, s[4:7], 0 offen offset:32
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[12:15], v60, s[4:7], 0 offen offset:48
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[16:19], v60, s[4:7], 0 offen offset:64
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[20:23], v60, s[4:7], 0 offen offset:80
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[24:27], v60, s[4:7], 0 offen offset:96
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[28:31], v60, s[4:7], 0 offen offset:112
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[32:35], v60, s[4:7], 0 offen offset:128
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[36:39], v60, s[4:7], 0 offen offset:144
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[40:43], v60, s[4:7], 0 offen offset:160
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[44:47], v60, s[4:7], 0 offen offset:176
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[48:51], v60, s[4:7], 0 offen offset:192
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[52:55], v60, s[4:7], 0 offen offset:208
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[56:59], v60, s[4:7], 0 offen offset:224
+; GISEL-GFX1100-NEXT: buffer_load_b128 v[60:63], v60, s[4:7], 0 offen offset:240
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(15)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[1:4], v65, s[12:15], 0 offen
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[0:3], v64, s[12:15], 0 offen
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(14)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[5:8], v65, s[12:15], 0 offen offset:16
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[4:7], v64, s[12:15], 0 offen offset:16
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(13)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[9:12], v65, s[12:15], 0 offen offset:32
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[8:11], v64, s[12:15], 0 offen offset:32
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(12)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[13:16], v65, s[12:15], 0 offen offset:48
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[12:15], v64, s[12:15], 0 offen offset:48
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(11)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[17:20], v65, s[12:15], 0 offen offset:64
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[16:19], v64, s[12:15], 0 offen offset:64
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(10)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[21:24], v65, s[12:15], 0 offen offset:80
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[20:23], v64, s[12:15], 0 offen offset:80
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(9)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[25:28], v65, s[12:15], 0 offen offset:96
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[24:27], v64, s[12:15], 0 offen offset:96
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(8)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[29:32], v65, s[12:15], 0 offen offset:112
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[28:31], v64, s[12:15], 0 offen offset:112
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(7)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[33:36], v65, s[12:15], 0 offen offset:128
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[32:35], v64, s[12:15], 0 offen offset:128
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(6)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[37:40], v65, s[12:15], 0 offen offset:144
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[36:39], v64, s[12:15], 0 offen offset:144
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(5)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[41:44], v65, s[12:15], 0 offen offset:160
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[40:43], v64, s[12:15], 0 offen offset:160
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(4)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[45:48], v65, s[12:15], 0 offen offset:176
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[44:47], v64, s[12:15], 0 offen offset:176
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(3)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[49:52], v65, s[12:15], 0 offen offset:192
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[48:51], v64, s[12:15], 0 offen offset:192
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(2)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[53:56], v65, s[12:15], 0 offen offset:208
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[52:55], v64, s[12:15], 0 offen offset:208
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(1)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[57:60], v65, s[12:15], 0 offen offset:224
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[56:59], v64, s[12:15], 0 offen offset:224
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0)
-; GISEL-GFX1100-NEXT: buffer_store_b128 v[61:64], v65, s[12:15], 0 offen offset:240
-; GISEL-GFX1100-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
-; GISEL-GFX1100-NEXT: s_cbranch_vccnz .LBB1_1
+; GISEL-GFX1100-NEXT: buffer_store_b128 v[60:63], v64, s[12:15], 0 offen offset:240
+; GISEL-GFX1100-NEXT: s_cbranch_scc1 .LBB1_1
; GISEL-GFX1100-NEXT: ; %bb.2: ; %static-memcpy-post-expansion
; GISEL-GFX1100-NEXT: s_endpgm
call void @llvm.memcpy.p7.p7.i32(ptr addrspace(7) noundef nonnull align 16 %dst, ptr addrspace(7) noundef nonnull align 16 %src, i32 256, i1 false)
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