[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for G_INSERT_VECTOR_ELT (PR #191296)

[Petar Avramovic via llvm-commits]

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@@ -979,6 +979,109 @@ bool RegBankLegalizeHelper::lowerExtrVecEltTo32(MachineInstr &MI) {
   return true;
 }
 
+bool RegBankLegalizeHelper::lowerInsVecEltToSel(MachineInstr &MI) {
+  // Lower insert vector element to a compare-select chain:
+  //   for i in 0..N-1:
+  //     result[i] = (idx == i) ? elt : srcVec[i]
+  //   dst = merge(result[0..N-1])
+  //
+  // VGPR B64 requires splitting to lo/hi s32 pairs since there is no
+  // v_cndmask_b64. SGPR B64/B32 and VGPR B32 can be handled natively.
+  Register Dst = MI.getOperand(0).getReg();
+  Register Src = MI.getOperand(1).getReg();
+  Register Elt = MI.getOperand(2).getReg();
+  Register Idx = MI.getOperand(3).getReg();
+
+  LLT VecTy = MRI.getType(Src);
+  LLT ScalarTy = VecTy.getScalarType();
+  unsigned NumElts = VecTy.getNumElements();
+  bool IsSGPR = (MRI.getRegBank(Src) == SgprRB);
+  SmallVector<Register, 16> Selects;
+
+  MachineRegisterInfo::VRegAttrs SrcRB_EltTy = {MRI.getRegBank(Src), ScalarTy};
+  MachineRegisterInfo::VRegAttrs CmpTy = IsSGPR ? SgprRB_S32 : VccRB_S1;
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petar-avramovic wrote:

move down, only used in else path

https://github.com/llvm/llvm-project/pull/191296