[llvm] [AArch64][ISel] Fix interleave3 crash (PR #192046)

[David Sherwood via llvm-commits]

================
@@ -32322,6 +32322,63 @@ SDValue AArch64TargetLowering::LowerVECTOR_INTERLEAVE(SDValue Op,
     return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op->getVTList(), Ops);
   }
 
+  if (Op->getNumOperands() == 3 && (OpVT == MVT::v2f64 || OpVT == MVT::v2i64)) {
+    SDValue A = Op->getOperand(0);
+    SDValue B = Op->getOperand(1);
+    SDValue C = Op->getOperand(2);
+
+    // a0, a1 | b0, b1 | c0, c1
+    //  ->
+    // a0, b0 | c0, a1 | b1, c1
+    SDValue Shuffle0 = DAG.getVectorShuffle(OpVT, DL, A, B, {0, 2});
+    SDValue Shuffle1 = DAG.getVectorShuffle(OpVT, DL, A, C, {2, 1});
+    SDValue Shuffle2 = DAG.getVectorShuffle(OpVT, DL, B, C, {1, 3});
+
+    return DAG.getMergeValues({Shuffle0, Shuffle1, Shuffle2}, DL);
+  }
+  if (Op->getNumOperands() == 3 && OpVT.isFixedLengthVector()) {
----------------
david-arm wrote:

Given the code above:

```
  if (OpVT.isScalableVector() && Op->getNumOperands() == 3) {
```

I think you can just write this as:

```
  if (Op->getNumOperands() == 3) {
    // Scalable vector case already handled above.
    unsigned NElements = OpVT.getVectorNumElements();
```

and getVectorNumElements will assert if it's not a fixed-length vector.

https://github.com/llvm/llvm-project/pull/192046