[llvm] [SLP][NFC]Add extra test for add/shl transformation opportunity in reductions, NFC (PR #192072)

[Alexey Bataev via llvm-commits]

https://github.com/alexey-bataev created https://github.com/llvm/llvm-project/pull/192072

None

>From 3540f65de1bbb83517191f5cc7d358c3069956f5 Mon Sep 17 00:00:00 2001
From: Alexey Bataev <a.bataev at outlook.com>
Date: Tue, 14 Apr 2026 07:51:19 -0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
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Created using spr 1.3.7
---
 .../X86/reduction-shl1-add-merge.ll           | 90 +++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll

diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll
new file mode 100644
index 0000000000000..94f4f806b6687
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll
@@ -0,0 +1,90 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define i32 @reduce_add_sub_shl(ptr %p, ptr %q, ptr %out) {
+; CHECK-LABEL: define i32 @reduce_add_sub_shl(
+; CHECK-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], ptr [[OUT:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[GP0:%.*]] = getelementptr i32, ptr [[P]], i64 0
+; CHECK-NEXT:    [[GP4:%.*]] = getelementptr i32, ptr [[P]], i64 4
+; CHECK-NEXT:    [[GP5:%.*]] = getelementptr i32, ptr [[P]], i64 5
+; CHECK-NEXT:    [[GP6:%.*]] = getelementptr i32, ptr [[P]], i64 6
+; CHECK-NEXT:    [[GP7:%.*]] = getelementptr i32, ptr [[P]], i64 7
+; CHECK-NEXT:    [[GQ0:%.*]] = getelementptr i32, ptr [[Q]], i64 0
+; CHECK-NEXT:    [[LP4:%.*]] = load i32, ptr [[GP4]], align 4
+; CHECK-NEXT:    [[LP5:%.*]] = load i32, ptr [[GP5]], align 4
+; CHECK-NEXT:    [[TMP11:%.*]] = load i32, ptr [[GP6]], align 4
+; CHECK-NEXT:    [[LP7:%.*]] = load i32, ptr [[GP7]], align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, ptr [[GP0]], align 4
+; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr [[GQ0]], align 4
+; CHECK-NEXT:    [[TMP2:%.*]] = add <4 x i32> [[TMP0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
+; CHECK-NEXT:    store volatile i32 [[TMP3]], ptr [[OUT]], align 4
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP2]], i32 1
+; CHECK-NEXT:    store volatile i32 [[TMP4]], ptr [[OUT]], align 4
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2
+; CHECK-NEXT:    store volatile i32 [[TMP5]], ptr [[OUT]], align 4
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3
+; CHECK-NEXT:    store volatile i32 [[TMP6]], ptr [[OUT]], align 4
+; CHECK-NEXT:    [[SHL1:%.*]] = shl i32 [[LP4]], 1
+; CHECK-NEXT:    [[SHL2:%.*]] = shl i32 [[LP5]], 1
+; CHECK-NEXT:    [[TMP12:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
+; CHECK-NEXT:    [[OP_RDX4:%.*]] = add i32 [[TMP12]], [[TMP11]]
+; CHECK-NEXT:    [[OP_RDX1:%.*]] = add i32 [[LP7]], [[SHL1]]
+; CHECK-NEXT:    [[OP_RDX2:%.*]] = add i32 [[OP_RDX4]], [[OP_RDX1]]
+; CHECK-NEXT:    [[OP_RDX3:%.*]] = add i32 [[OP_RDX2]], [[SHL2]]
+; CHECK-NEXT:    ret i32 [[OP_RDX3]]
+;
+entry:
+  %gp0 = getelementptr i32, ptr %p, i64 0
+  %gp1 = getelementptr i32, ptr %p, i64 1
+  %gp2 = getelementptr i32, ptr %p, i64 2
+  %gp3 = getelementptr i32, ptr %p, i64 3
+  %gp4 = getelementptr i32, ptr %p, i64 4
+  %gp5 = getelementptr i32, ptr %p, i64 5
+  %gp6 = getelementptr i32, ptr %p, i64 6
+  %gp7 = getelementptr i32, ptr %p, i64 7
+
+  %gq0 = getelementptr i32, ptr %q, i64 0
+  %gq1 = getelementptr i32, ptr %q, i64 1
+  %gq2 = getelementptr i32, ptr %q, i64 2
+  %gq3 = getelementptr i32, ptr %q, i64 3
+
+  %lp0 = load i32, ptr %gp0, align 4
+  %lp1 = load i32, ptr %gp1, align 4
+  %lp2 = load i32, ptr %gp2, align 4
+  %lp3 = load i32, ptr %gp3, align 4
+  %lp4 = load i32, ptr %gp4, align 4
+  %lp5 = load i32, ptr %gp5, align 4
+  %lp6 = load i32, ptr %gp6, align 4
+  %lp7 = load i32, ptr %gp7, align 4
+
+  %lq0 = load i32, ptr %gq0, align 4
+  %lq1 = load i32, ptr %gq1, align 4
+  %lq2 = load i32, ptr %gq2, align 4
+  %lq3 = load i32, ptr %gq3, align 4
+
+  ; 4 adds (volatile stores give multi-use, prevent store vectorization)
+  %add1 = add i32 %lp0, %lq0
+  %add2 = add i32 %lp1, %lq1
+  %add3 = add i32 %lp2, %lq2
+  %add4 = add i32 %lp3, %lq3
+  store volatile i32 %add1, ptr %out, align 4
+  store volatile i32 %add2, ptr %out, align 4
+  store volatile i32 %add3, ptr %out, align 4
+  store volatile i32 %add4, ptr %out, align 4
+
+  ; 2 shls (natural leaves)
+  %shl1 = shl i32 %lp4, 1
+  %shl2 = shl i32 %lp5, 1
+
+  ; add reduction chain over all 8 values
+  %r1 = add i32 %add1, %add2
+  %r2 = add i32 %r1, %add3
+  %r3 = add i32 %r2, %add4
+  %r4 = add i32 %r3, %shl1
+  %r5 = add i32 %r4, %shl2
+  %r6 = add i32 %r5, %lp6
+  %result = add i32 %r6, %lp7
+  ret i32 %result
+}