[llvm] 56ce7ed - [AArch64] Fix strict weak ordering violation in regalloc hints sort. (#192055)

[via llvm-commits]

Author: Sander de Smalen
Date: 2026-04-14T14:56:25+01:00
New Revision: 56ce7ede7d290758bc00dd8596f65639d1c3544f

URL: https://github.com/llvm/llvm-project/commit/56ce7ede7d290758bc00dd8596f65639d1c3544f
DIFF: https://github.com/llvm/llvm-project/commit/56ce7ede7d290758bc00dd8596f65639d1c3544f.diff

LOG: [AArch64] Fix strict weak ordering violation in regalloc hints sort. (#192055)

This fixes an error with expensive checks after landing #190139.

The issue was:

Error: comparison doesn't meet irreflexive requirements, assert(!(a <
a)).

because it could have previously returned 'true' in the ordering
function if registers A and B were equal.

Also made NFC change to rename 'HandleMatchCmpPredicateHint' ->
'HandleDestructivePredicateHint' (that was missed in the review).

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index a5b934b152abb..f232fa79c7022 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -1115,7 +1115,7 @@ unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
   }
 }
 
-static bool HandleMatchCmpPredicateHint(
+static bool HandleDestructivePredicateHint(
     Register VirtReg, ArrayRef<MCPhysReg> Order,
     SmallVectorImpl<MCPhysReg> &Hints, const VirtRegMap *VRM,
     const MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
@@ -1158,7 +1158,7 @@ static bool HandleMatchCmpPredicateHint(
 
   Hints.append(Order.begin(), Order.end());
   llvm::stable_sort(Hints, [&](Register A, Register B) {
-    return B == Op1Reg &&
+    return A != B && B == Op1Reg &&
            (!CSRs.contains(A) || !MRI.def_empty(A) || Matrix->isPhysRegUsed(A));
   });
   return true;
@@ -1253,8 +1253,8 @@ bool AArch64RegisterInfo::getRegAllocationHints(
       return ConsiderOnlyHints;
   }
 
-  if (HandleMatchCmpPredicateHint(VirtReg, Order, Hints, VRM, MRI, *TII, ST,
-                                  Matrix))
+  if (HandleDestructivePredicateHint(VirtReg, Order, Hints, VRM, MRI, *TII, ST,
+                                     Matrix))
     return ConsiderOnlyHints;
 
   if (!ST.hasSME() || !ST.isStreaming())