[llvm] [AArch64][SVE][SelectionDAG] Improve codegen for SVE patterns sext(icmp) and zext(icmp) (PR #192052)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

Hi, as @paulwalker-arm wrote, this PR does seem to be doing a few things at the same time. It would perhaps be preferable to start with the ext(icmp) changes on their own, and then build on top of them for the other changes.

For the ext(icmp) patterns, would it be preferable to use halving subtraction and shifts? Specifically:
```
sext(icmp slt a, b) --> asr (shsub a, b), bitwidth-1
zext(icmp slt a, b) --> lsr (shsub a, b), bitwidth-1
sext(icmp ult a, b) --> asr (uhsub a, b), bitwidth-1
zext(icmp ult a, b) --> lsr (uhsub a, b), bitwidth-1
```
That should lower the architecture requirements a bit for the cases that currently rely on SCLAMP.

https://github.com/llvm/llvm-project/pull/192052