[llvm] [AMDGPU] Allow SCC-only implicit defs and mark SOP2 SALU as rematerializable (PR #187084)
Romanov Vlad via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 14 06:37:32 PDT 2026
https://github.com/romanovvlad updated https://github.com/llvm/llvm-project/pull/187084
>From f0a79c31d377f11d17583df139818c124a5ae4e4 Mon Sep 17 00:00:00 2001
From: Vlad <Vladislav.Romanov at amd.com>
Date: Tue, 10 Mar 2026 04:38:32 -0500
Subject: [PATCH 1/3] [AMDGPU] Allow SCC-only implicit defs and mark SOP2 SALU
as rematerializable
The old `hasImplicitDef()` check blocked all instructions with any
implicit def from being rematerialized. But rematerializing instructions
that implicitly define SCC should be safe provided SCC is not live at
the rematerialization point.
Patch adds target independent hook to allow backends to check if implicit
defs would clobber live values at remat points.
Relaxes SIInstrInfo::isReMaterializableImpl to allow SCC implicit def.
Marks SOP2 instructions as rematerializable.
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 9 +
llvm/lib/CodeGen/LiveRangeEdit.cpp | 4 +
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 29 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 3 +
llvm/lib/Target/AMDGPU/SOPInstructions.td | 1 +
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 3538 +++++++++--------
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 161 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll | 1503 ++++---
.../CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll | 1575 ++++----
.../AMDGPU/eliminate-frame-index-select.ll | 30 +-
.../CodeGen/AMDGPU/insert_vector_dynelt.ll | 442 +-
llvm/test/CodeGen/AMDGPU/issue176578.ll | 26 +-
...ne-sink-temporal-divergence-swdev407790.ll | 194 +-
.../CodeGen/AMDGPU/memcpy_const_compare.ll | 49 +-
llvm/test/CodeGen/AMDGPU/remat-scc-mir.mir | 220 +
.../AMDGPU/sgpr-spill-wrong-stack-id.mir | 34 +-
.../si-lower-sgpr-spills-vgpr-lanes-usage.mir | 27 +-
.../AMDGPU/tuple-allocation-failure.ll | 88 +-
.../AMDGPU/unstructured-cfg-def-use-issue.ll | 32 +-
19 files changed, 4119 insertions(+), 3846 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/remat-scc-mir.mir
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index ed968d7bd4593..f82cfc1460e84 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -27,6 +27,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOutliner.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/Support/BranchProbability.h"
@@ -197,6 +198,14 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
return false;
}
+ /// Returns true if this instruction can be safely rematerialized at UseIdx
+ /// even if it has implicit physical register defs that are live.
+ virtual bool isImplicitDefRematerializableAt(const MachineInstr &MI,
+ SlotIndex UseIdx,
+ LiveIntervals &LIS) const {
+ return true;
+ }
+
virtual bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
MachineCycleInfo *CI) const {
return true;
diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp
index 6fe11704a9137..0271663ce9c3a 100644
--- a/llvm/lib/CodeGen/LiveRangeEdit.cpp
+++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp
@@ -78,6 +78,10 @@ bool LiveRangeEdit::canRematerializeAt(Remat &RM, SlotIndex UseIdx) {
if (!VirtRegAuxInfo::allUsesAvailableAt(RM.OrigMI, UseIdx, LIS, MRI, TII))
return false;
+ // Verify that implict defs would not clobber live values.
+ if (!TII.isImplicitDefRematerializableAt(*RM.OrigMI, UseIdx, LIS))
+ return false;
+
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index de118f3dbbf14..99547a8121b5d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -140,8 +140,17 @@ bool SIInstrInfo::isReMaterializableImpl(
// There is difference to generic method which does not allow
// rematerialization if there are virtual register uses. We allow this,
// therefore this method includes SOP instructions as well.
- if (!MI.hasImplicitDef() &&
- MI.getNumImplicitOperands() == MI.getDesc().implicit_uses().size() &&
+ // Allow instructions whose only implicit def (if any) is SCC.
+ bool HasUnsafeImplicitDef = false;
+ for (const MachineOperand &MO : MI.implicit_operands())
+ if (MO.isDef() && MO.getReg() != AMDGPU::SCC) {
+ HasUnsafeImplicitDef = true;
+ break;
+ }
+ if (!HasUnsafeImplicitDef &&
+ MI.getNumImplicitOperands() ==
+ MI.getDesc().implicit_defs().size() +
+ MI.getDesc().implicit_uses().size() &&
!MI.mayRaiseFPException())
return true;
}
@@ -149,6 +158,22 @@ bool SIInstrInfo::isReMaterializableImpl(
return TargetInstrInfo::isReMaterializableImpl(MI);
}
+bool SIInstrInfo::isImplicitDefRematerializableAt(const MachineInstr &MI,
+ SlotIndex UseIdx,
+ LiveIntervals &LIS) const {
+
+ // Check if SCC implicit def would clobber a live value.
+ if (MI.modifiesRegister(AMDGPU::SCC, &RI)) {
+ for (MCRegUnit Unit : RI.regunits(AMDGPU::SCC)) {
+ LiveRange &LR = LIS.getRegUnit(Unit);
+ if (LR.liveAt(UseIdx))
+ return false;
+ }
+ }
+
+ return true;
+}
+
// Returns true if the scalar result of a VALU instruction depends on exec.
bool SIInstrInfo::resultDependsOnExec(const MachineInstr &MI) const {
// Ignore comparisons which are only used masked with exec.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 87d51ffe83663..e0c72782d6990 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -263,6 +263,9 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
bool isReMaterializableImpl(const MachineInstr &MI) const override;
+ bool isImplicitDefRematerializableAt(const MachineInstr &MI, SlotIndex UseIdx,
+ LiveIntervals &LIS) const override;
+
bool isIgnorableUse(const MachineOperand &MO) const override;
bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index ce6e862104b4f..f0cbdd221e900 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -591,6 +591,7 @@ class SOP2_Pseudo<string opName, dag outs, dag ins,
let SOP2 = 1;
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
+ let isReMaterializable = 1;
let has_sdst = 1;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 38dc4575d313a..57827118e8902 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -31885,9 +31885,8 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v34, s30, 0
; SI-NEXT: v_writelane_b32 v34, s31, 1
; SI-NEXT: v_writelane_b32 v34, s34, 2
@@ -31922,12 +31921,7 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_writelane_b32 v34, s87, 31
; SI-NEXT: v_writelane_b32 v34, s96, 32
; SI-NEXT: v_readfirstlane_b32 s6, v17
-; SI-NEXT: v_writelane_b32 v34, s97, 33
-; SI-NEXT: s_lshr_b32 vcc_lo, s6, 16
; SI-NEXT: v_readfirstlane_b32 s8, v16
-; SI-NEXT: ; implicit-def: $vgpr35 : SGPR spill to VGPR lane
-; SI-NEXT: v_writelane_b32 v34, s98, 34
-; SI-NEXT: s_lshr_b32 vcc_hi, s8, 16
; SI-NEXT: v_readfirstlane_b32 s10, v15
; SI-NEXT: v_readfirstlane_b32 s12, v14
; SI-NEXT: v_readfirstlane_b32 s14, v13
@@ -31944,44 +31938,43 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s68, v2
; SI-NEXT: v_readfirstlane_b32 s80, v1
; SI-NEXT: v_readfirstlane_b32 s83, v0
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v35, vcc_lo, 0
-; SI-NEXT: v_writelane_b32 v34, s99, 35
-; SI-NEXT: s_lshr_b32 s69, s29, 16
-; SI-NEXT: s_lshr_b32 s71, s28, 16
-; SI-NEXT: s_lshr_b32 s82, s27, 16
-; SI-NEXT: s_lshr_b32 s85, s26, 16
-; SI-NEXT: s_lshr_b32 s86, s25, 16
-; SI-NEXT: s_lshr_b32 s87, s24, 16
-; SI-NEXT: s_lshr_b32 s96, s23, 16
-; SI-NEXT: s_lshr_b32 s97, s22, 16
-; SI-NEXT: s_lshr_b32 s98, s21, 16
-; SI-NEXT: s_lshr_b32 s99, s20, 16
-; SI-NEXT: s_lshr_b32 s7, s19, 16
+; SI-NEXT: v_writelane_b32 v34, s97, 33
+; SI-NEXT: s_lshr_b32 s91, s29, 16
+; SI-NEXT: s_lshr_b32 s95, s28, 16
+; SI-NEXT: s_lshr_b32 s47, s27, 16
+; SI-NEXT: s_lshr_b32 s46, s26, 16
+; SI-NEXT: s_lshr_b32 s45, s25, 16
+; SI-NEXT: s_lshr_b32 s44, s24, 16
+; SI-NEXT: s_lshr_b32 s43, s23, 16
+; SI-NEXT: s_lshr_b32 s42, s22, 16
+; SI-NEXT: s_lshr_b32 s35, s21, 16
+; SI-NEXT: s_lshr_b32 s7, s20, 16
+; SI-NEXT: s_lshr_b32 s39, s19, 16
; SI-NEXT: s_lshr_b32 s9, s18, 16
; SI-NEXT: s_lshr_b32 s11, s17, 16
; SI-NEXT: s_lshr_b32 s13, s16, 16
-; SI-NEXT: s_lshr_b32 s65, s10, 16
-; SI-NEXT: s_lshr_b32 s64, s12, 16
-; SI-NEXT: s_lshr_b32 s15, s14, 16
-; SI-NEXT: s_lshr_b32 s73, s72, 16
-; SI-NEXT: s_lshr_b32 s75, s74, 16
-; SI-NEXT: s_lshr_b32 s77, s76, 16
-; SI-NEXT: s_lshr_b32 s79, s78, 16
-; SI-NEXT: s_lshr_b32 s89, s88, 16
-; SI-NEXT: s_lshr_b32 s91, s90, 16
-; SI-NEXT: s_lshr_b32 s93, s92, 16
-; SI-NEXT: s_lshr_b32 s95, s94, 16
-; SI-NEXT: s_lshr_b32 s31, s30, 16
-; SI-NEXT: s_lshr_b32 s35, s34, 16
-; SI-NEXT: s_lshr_b32 s70, s68, 16
-; SI-NEXT: s_lshr_b32 s81, s80, 16
-; SI-NEXT: s_lshr_b32 s84, s83, 16
+; SI-NEXT: s_lshr_b32 vcc_lo, s6, 16
+; SI-NEXT: s_lshr_b32 s15, s8, 16
+; SI-NEXT: s_lshr_b32 s73, s10, 16
+; SI-NEXT: s_lshr_b32 s75, s12, 16
+; SI-NEXT: s_lshr_b32 s63, s14, 16
+; SI-NEXT: s_lshr_b32 s62, s72, 16
+; SI-NEXT: s_lshr_b32 s61, s74, 16
+; SI-NEXT: s_lshr_b32 s60, s76, 16
+; SI-NEXT: s_lshr_b32 s59, s78, 16
+; SI-NEXT: s_lshr_b32 s58, s88, 16
+; SI-NEXT: s_lshr_b32 s57, s90, 16
+; SI-NEXT: s_lshr_b32 s56, s92, 16
+; SI-NEXT: s_lshr_b32 s77, s94, 16
+; SI-NEXT: s_lshr_b32 s79, s30, 16
+; SI-NEXT: s_lshr_b32 s89, s34, 16
+; SI-NEXT: s_lshr_b32 s93, s68, 16
+; SI-NEXT: s_lshr_b32 vcc_hi, s80, 16
+; SI-NEXT: s_lshr_b32 s31, s83, 16
; SI-NEXT: v_readfirstlane_b32 s4, v18
-; SI-NEXT: v_writelane_b32 v35, vcc_hi, 1
+; SI-NEXT: v_writelane_b32 v34, s98, 34
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v35, s65, 2
-; SI-NEXT: v_writelane_b32 v35, s64, 3
+; SI-NEXT: v_writelane_b32 v34, s99, 35
; SI-NEXT: s_cbranch_scc0 .LBB23_3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
@@ -31991,94 +31984,119 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_lshl_b32 s5, s9, 16
; SI-NEXT: s_or_b32 s38, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s7, 16
+; SI-NEXT: s_lshl_b32 s5, s39, 16
; SI-NEXT: s_and_b32 s40, s17, 0xffff
; SI-NEXT: s_lshl_b32 s41, s11, 16
+; SI-NEXT: s_mov_b32 s71, s39
; SI-NEXT: s_or_b32 s39, s4, s5
; SI-NEXT: s_and_b32 s4, s20, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s99, 16
+; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s37, s40, s41
; SI-NEXT: s_or_b32 s40, s4, s5
; SI-NEXT: s_and_b32 s4, s21, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s98, 16
+; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s41, s4, s5
; SI-NEXT: s_and_b32 s4, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s97, 16
+; SI-NEXT: s_lshl_b32 s5, s42, 16
+; SI-NEXT: s_mov_b32 s69, s42
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s96, 16
+; SI-NEXT: s_lshl_b32 s5, s43, 16
+; SI-NEXT: s_mov_b32 s70, s7
+; SI-NEXT: s_mov_b32 s7, s35
+; SI-NEXT: s_mov_b32 s35, s43
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s87, 16
+; SI-NEXT: s_lshl_b32 s5, s44, 16
+; SI-NEXT: s_mov_b32 s99, s44
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s86, 16
+; SI-NEXT: s_lshl_b32 s5, s45, 16
+; SI-NEXT: s_mov_b32 s98, s45
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s85, 16
+; SI-NEXT: s_lshl_b32 s5, s46, 16
+; SI-NEXT: s_mov_b32 s97, s46
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s82, 16
+; SI-NEXT: s_lshl_b32 s5, s47, 16
+; SI-NEXT: s_mov_b32 s87, s47
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s71, 16
+; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s69, 16
+; SI-NEXT: s_lshl_b32 s5, s91, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s83, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s84, 16
+; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s80, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s81, 16
+; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s68, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s70, 16
+; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s34, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s35, 16
+; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s30, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s31, 16
+; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s94, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s95, 16
+; SI-NEXT: s_lshl_b32 s5, s77, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s92, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s93, 16
+; SI-NEXT: s_lshl_b32 s5, s56, 16
+; SI-NEXT: s_mov_b32 s82, s91
+; SI-NEXT: s_mov_b32 s91, s79
+; SI-NEXT: s_mov_b32 s79, s56
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s90, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s91, 16
+; SI-NEXT: s_lshl_b32 s5, s57, 16
+; SI-NEXT: s_mov_b32 s81, s89
+; SI-NEXT: s_mov_b32 s89, s77
+; SI-NEXT: s_mov_b32 s77, s57
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s88, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s89, 16
+; SI-NEXT: s_lshl_b32 s5, s58, 16
+; SI-NEXT: s_mov_b32 s96, s31
+; SI-NEXT: s_mov_b32 s31, s58
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s78, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s79, 16
+; SI-NEXT: s_lshl_b32 s5, s59, 16
+; SI-NEXT: s_mov_b32 s85, s95
+; SI-NEXT: s_mov_b32 s95, s59
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_and_b32 s4, s76, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s77, 16
+; SI-NEXT: s_lshl_b32 s5, s60, 16
+; SI-NEXT: s_mov_b32 s84, s93
+; SI-NEXT: s_mov_b32 s93, s60
; SI-NEXT: s_or_b32 s60, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s75, 16
+; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s61, s4, s5
; SI-NEXT: s_and_b32 s4, s72, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s73, 16
+; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s62, s4, s5
; SI-NEXT: s_and_b32 s4, s14, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s15, 16
+; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s63, s4, s5
; SI-NEXT: s_and_b32 s4, s12, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s64, 16
+; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s64, s4, s5
; SI-NEXT: s_and_b32 s4, s10, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s65, 16
+; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s65, s4, s5
; SI-NEXT: s_and_b32 s4, s8, 0xffff
-; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
+; SI-NEXT: s_lshl_b32 s5, s15, 16
; SI-NEXT: s_or_b32 s66, s4, s5
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
+; SI-NEXT: s_mov_b32 s86, vcc_hi
+; SI-NEXT: s_mov_b32 s75, s73
+; SI-NEXT: s_mov_b32 s73, s15
+; SI-NEXT: s_mov_b32 s15, vcc_lo
; SI-NEXT: s_or_b32 s67, s4, s5
; SI-NEXT: s_cbranch_execnz .LBB23_4
; SI-NEXT: .LBB23_2: ; %cmp.true
@@ -32104,11 +32122,11 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s7
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s71
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_cvt_f32_f16_e32 v4, s19
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s99
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s70
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
@@ -32119,7 +32137,7 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v6, s20
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s98
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s7
; SI-NEXT: v_cvt_f32_f16_e32 v7, s21
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
@@ -32128,11 +32146,11 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v6, s97
+; SI-NEXT: v_cvt_f32_f16_e32 v6, s69
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v7, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, s22
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s96
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s35
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
@@ -32143,7 +32161,7 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v9, s23
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s87
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s99
; SI-NEXT: v_cvt_f32_f16_e32 v10, s24
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
@@ -32152,11 +32170,11 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_or_b32_e32 v7, v9, v7
-; SI-NEXT: v_cvt_f32_f16_e32 v9, s86
+; SI-NEXT: v_cvt_f32_f16_e32 v9, s98
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_cvt_f32_f16_e32 v10, s25
-; SI-NEXT: v_cvt_f32_f16_e32 v11, s85
+; SI-NEXT: v_cvt_f32_f16_e32 v11, s97
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
@@ -32167,7 +32185,7 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v12, s26
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; SI-NEXT: v_cvt_f32_f16_e32 v11, s82
+; SI-NEXT: v_cvt_f32_f16_e32 v11, s87
; SI-NEXT: v_cvt_f32_f16_e32 v13, s27
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
@@ -32176,11 +32194,11 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_or_b32_e32 v10, v12, v10
-; SI-NEXT: v_cvt_f32_f16_e32 v12, s71
+; SI-NEXT: v_cvt_f32_f16_e32 v12, s85
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: v_cvt_f32_f16_e32 v13, s28
-; SI-NEXT: v_cvt_f32_f16_e32 v14, s69
+; SI-NEXT: v_cvt_f32_f16_e32 v14, s82
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
@@ -32191,7 +32209,7 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v15, s29
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; SI-NEXT: v_cvt_f32_f16_e32 v14, s84
+; SI-NEXT: v_cvt_f32_f16_e32 v14, s96
; SI-NEXT: v_cvt_f32_f16_e32 v16, s83
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
@@ -32200,11 +32218,11 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_or_b32_e32 v13, v15, v13
-; SI-NEXT: v_cvt_f32_f16_e32 v15, s81
+; SI-NEXT: v_cvt_f32_f16_e32 v15, s86
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_cvt_f32_f16_e32 v16, s80
-; SI-NEXT: v_cvt_f32_f16_e32 v17, s70
+; SI-NEXT: v_cvt_f32_f16_e32 v17, s84
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
@@ -32215,7 +32233,7 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v18, s68
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; SI-NEXT: v_cvt_f32_f16_e32 v17, s35
+; SI-NEXT: v_cvt_f32_f16_e32 v17, s81
; SI-NEXT: v_cvt_f32_f16_e32 v19, s34
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
@@ -32224,11 +32242,11 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_or_b32_e32 v16, v18, v16
-; SI-NEXT: v_cvt_f32_f16_e32 v18, s31
+; SI-NEXT: v_cvt_f32_f16_e32 v18, s91
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: v_cvt_f32_f16_e32 v19, s30
-; SI-NEXT: v_cvt_f32_f16_e32 v20, s95
+; SI-NEXT: v_cvt_f32_f16_e32 v20, s89
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
@@ -32239,7 +32257,7 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v21, s94
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
-; SI-NEXT: v_cvt_f32_f16_e32 v20, s93
+; SI-NEXT: v_cvt_f32_f16_e32 v20, s79
; SI-NEXT: v_cvt_f32_f16_e32 v22, s92
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
@@ -32248,11 +32266,11 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_or_b32_e32 v19, v21, v19
-; SI-NEXT: v_cvt_f32_f16_e32 v21, s91
+; SI-NEXT: v_cvt_f32_f16_e32 v21, s77
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_cvt_f32_f16_e32 v22, s90
-; SI-NEXT: v_cvt_f32_f16_e32 v23, s89
+; SI-NEXT: v_cvt_f32_f16_e32 v23, s31
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
@@ -32263,7 +32281,7 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v24, s88
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; SI-NEXT: v_cvt_f32_f16_e32 v23, s79
+; SI-NEXT: v_cvt_f32_f16_e32 v23, s95
; SI-NEXT: v_cvt_f32_f16_e32 v25, s78
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
@@ -32272,11 +32290,12 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_or_b32_e32 v22, v24, v22
-; SI-NEXT: v_cvt_f32_f16_e32 v24, s77
+; SI-NEXT: v_cvt_f32_f16_e32 v24, s93
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_lshr_b32 s4, s74, 16
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: v_cvt_f32_f16_e32 v25, s76
-; SI-NEXT: v_cvt_f32_f16_e32 v26, s75
+; SI-NEXT: v_cvt_f32_f16_e32 v26, s4
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
@@ -32284,10 +32303,11 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_lshr_b32 s4, s72, 16
; SI-NEXT: v_cvt_f32_f16_e32 v27, s74
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
-; SI-NEXT: v_cvt_f32_f16_e32 v26, s73
+; SI-NEXT: v_cvt_f32_f16_e32 v26, s4
; SI-NEXT: v_cvt_f32_f16_e32 v28, s72
; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v27
; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
@@ -32295,10 +32315,11 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
+; SI-NEXT: s_lshr_b32 s4, s14, 16
; SI-NEXT: v_or_b32_e32 v25, v27, v25
-; SI-NEXT: v_cvt_f32_f16_e32 v27, s15
+; SI-NEXT: v_cvt_f32_f16_e32 v27, s4
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_readlane_b32 s4, v35, 3
+; SI-NEXT: s_lshr_b32 s4, s12, 16
; SI-NEXT: v_or_b32_e32 v26, v28, v26
; SI-NEXT: v_cvt_f32_f16_e32 v28, s14
; SI-NEXT: v_cvt_f32_f16_e32 v29, s4
@@ -32309,11 +32330,10 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_readlane_b32 s4, v35, 2
; SI-NEXT: v_cvt_f32_f16_e32 v30, s12
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; SI-NEXT: v_cvt_f32_f16_e32 v29, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v29, s75
; SI-NEXT: v_cvt_f32_f16_e32 v31, s10
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
@@ -32321,14 +32341,12 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
; SI-NEXT: v_add_f32_e32 v31, 0x38000000, v31
; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
-; SI-NEXT: v_readlane_b32 s4, v35, 1
; SI-NEXT: v_or_b32_e32 v28, v30, v28
-; SI-NEXT: v_cvt_f32_f16_e32 v30, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v30, s73
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_readlane_b32 s4, v35, 0
; SI-NEXT: v_or_b32_e32 v29, v31, v29
; SI-NEXT: v_cvt_f32_f16_e32 v31, s8
-; SI-NEXT: v_cvt_f32_f16_e32 v32, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v32, s15
; SI-NEXT: v_cvt_f32_f16_e32 v33, s6
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
@@ -32344,6 +32362,31 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v31, v33, v31
; SI-NEXT: s_branch .LBB23_5
; SI-NEXT: .LBB23_3:
+; SI-NEXT: s_mov_b32 s71, s39
+; SI-NEXT: s_mov_b32 s70, s7
+; SI-NEXT: s_mov_b32 s7, s35
+; SI-NEXT: s_mov_b32 s69, s42
+; SI-NEXT: s_mov_b32 s35, s43
+; SI-NEXT: s_mov_b32 s99, s44
+; SI-NEXT: s_mov_b32 s98, s45
+; SI-NEXT: s_mov_b32 s97, s46
+; SI-NEXT: s_mov_b32 s96, s31
+; SI-NEXT: s_mov_b32 s87, s47
+; SI-NEXT: s_mov_b32 s86, vcc_hi
+; SI-NEXT: s_mov_b32 s85, s95
+; SI-NEXT: s_mov_b32 s84, s93
+; SI-NEXT: s_mov_b32 s82, s91
+; SI-NEXT: s_mov_b32 s81, s89
+; SI-NEXT: s_mov_b32 s91, s79
+; SI-NEXT: s_mov_b32 s89, s77
+; SI-NEXT: s_mov_b32 s79, s56
+; SI-NEXT: s_mov_b32 s77, s57
+; SI-NEXT: s_mov_b32 s31, s58
+; SI-NEXT: s_mov_b32 s95, s59
+; SI-NEXT: s_mov_b32 s93, s60
+; SI-NEXT: s_mov_b32 s75, s73
+; SI-NEXT: s_mov_b32 s73, s15
+; SI-NEXT: s_mov_b32 s15, vcc_lo
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: s_branch .LBB23_2
; SI-NEXT: .LBB23_4:
@@ -32418,7 +32461,6 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_readlane_b32 s30, v34, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -67965,9 +68007,8 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v34, s30, 0
; SI-NEXT: v_writelane_b32 v34, s31, 1
; SI-NEXT: v_writelane_b32 v34, s34, 2
@@ -68002,12 +68043,7 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_writelane_b32 v34, s87, 31
; SI-NEXT: v_writelane_b32 v34, s96, 32
; SI-NEXT: v_readfirstlane_b32 s6, v17
-; SI-NEXT: v_writelane_b32 v34, s97, 33
-; SI-NEXT: s_lshr_b32 vcc_lo, s6, 16
; SI-NEXT: v_readfirstlane_b32 s8, v16
-; SI-NEXT: ; implicit-def: $vgpr35 : SGPR spill to VGPR lane
-; SI-NEXT: v_writelane_b32 v34, s98, 34
-; SI-NEXT: s_lshr_b32 vcc_hi, s8, 16
; SI-NEXT: v_readfirstlane_b32 s10, v15
; SI-NEXT: v_readfirstlane_b32 s12, v14
; SI-NEXT: v_readfirstlane_b32 s14, v13
@@ -68024,44 +68060,43 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_readfirstlane_b32 s68, v2
; SI-NEXT: v_readfirstlane_b32 s80, v1
; SI-NEXT: v_readfirstlane_b32 s83, v0
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v35, vcc_lo, 0
-; SI-NEXT: v_writelane_b32 v34, s99, 35
-; SI-NEXT: s_lshr_b32 s69, s29, 16
-; SI-NEXT: s_lshr_b32 s71, s28, 16
-; SI-NEXT: s_lshr_b32 s82, s27, 16
-; SI-NEXT: s_lshr_b32 s85, s26, 16
-; SI-NEXT: s_lshr_b32 s86, s25, 16
-; SI-NEXT: s_lshr_b32 s87, s24, 16
-; SI-NEXT: s_lshr_b32 s96, s23, 16
-; SI-NEXT: s_lshr_b32 s97, s22, 16
-; SI-NEXT: s_lshr_b32 s98, s21, 16
-; SI-NEXT: s_lshr_b32 s99, s20, 16
-; SI-NEXT: s_lshr_b32 s7, s19, 16
+; SI-NEXT: v_writelane_b32 v34, s97, 33
+; SI-NEXT: s_lshr_b32 s91, s29, 16
+; SI-NEXT: s_lshr_b32 s95, s28, 16
+; SI-NEXT: s_lshr_b32 s47, s27, 16
+; SI-NEXT: s_lshr_b32 s46, s26, 16
+; SI-NEXT: s_lshr_b32 s45, s25, 16
+; SI-NEXT: s_lshr_b32 s44, s24, 16
+; SI-NEXT: s_lshr_b32 s43, s23, 16
+; SI-NEXT: s_lshr_b32 s42, s22, 16
+; SI-NEXT: s_lshr_b32 s35, s21, 16
+; SI-NEXT: s_lshr_b32 s7, s20, 16
+; SI-NEXT: s_lshr_b32 s39, s19, 16
; SI-NEXT: s_lshr_b32 s9, s18, 16
; SI-NEXT: s_lshr_b32 s11, s17, 16
; SI-NEXT: s_lshr_b32 s13, s16, 16
-; SI-NEXT: s_lshr_b32 s65, s10, 16
-; SI-NEXT: s_lshr_b32 s64, s12, 16
-; SI-NEXT: s_lshr_b32 s15, s14, 16
-; SI-NEXT: s_lshr_b32 s73, s72, 16
-; SI-NEXT: s_lshr_b32 s75, s74, 16
-; SI-NEXT: s_lshr_b32 s77, s76, 16
-; SI-NEXT: s_lshr_b32 s79, s78, 16
-; SI-NEXT: s_lshr_b32 s89, s88, 16
-; SI-NEXT: s_lshr_b32 s91, s90, 16
-; SI-NEXT: s_lshr_b32 s93, s92, 16
-; SI-NEXT: s_lshr_b32 s95, s94, 16
-; SI-NEXT: s_lshr_b32 s31, s30, 16
-; SI-NEXT: s_lshr_b32 s35, s34, 16
-; SI-NEXT: s_lshr_b32 s70, s68, 16
-; SI-NEXT: s_lshr_b32 s81, s80, 16
-; SI-NEXT: s_lshr_b32 s84, s83, 16
+; SI-NEXT: s_lshr_b32 vcc_lo, s6, 16
+; SI-NEXT: s_lshr_b32 s15, s8, 16
+; SI-NEXT: s_lshr_b32 s73, s10, 16
+; SI-NEXT: s_lshr_b32 s75, s12, 16
+; SI-NEXT: s_lshr_b32 s63, s14, 16
+; SI-NEXT: s_lshr_b32 s62, s72, 16
+; SI-NEXT: s_lshr_b32 s61, s74, 16
+; SI-NEXT: s_lshr_b32 s60, s76, 16
+; SI-NEXT: s_lshr_b32 s59, s78, 16
+; SI-NEXT: s_lshr_b32 s58, s88, 16
+; SI-NEXT: s_lshr_b32 s57, s90, 16
+; SI-NEXT: s_lshr_b32 s56, s92, 16
+; SI-NEXT: s_lshr_b32 s77, s94, 16
+; SI-NEXT: s_lshr_b32 s79, s30, 16
+; SI-NEXT: s_lshr_b32 s89, s34, 16
+; SI-NEXT: s_lshr_b32 s93, s68, 16
+; SI-NEXT: s_lshr_b32 vcc_hi, s80, 16
+; SI-NEXT: s_lshr_b32 s31, s83, 16
; SI-NEXT: v_readfirstlane_b32 s4, v18
-; SI-NEXT: v_writelane_b32 v35, vcc_hi, 1
+; SI-NEXT: v_writelane_b32 v34, s98, 34
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v35, s65, 2
-; SI-NEXT: v_writelane_b32 v35, s64, 3
+; SI-NEXT: v_writelane_b32 v34, s99, 35
; SI-NEXT: s_cbranch_scc0 .LBB47_3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
@@ -68071,94 +68106,119 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s9, 16
; SI-NEXT: s_or_b32 s38, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s7, 16
+; SI-NEXT: s_lshl_b32 s5, s39, 16
; SI-NEXT: s_and_b32 s40, s17, 0xffff
; SI-NEXT: s_lshl_b32 s41, s11, 16
+; SI-NEXT: s_mov_b32 s71, s39
; SI-NEXT: s_or_b32 s39, s4, s5
; SI-NEXT: s_and_b32 s4, s20, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s99, 16
+; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s37, s40, s41
; SI-NEXT: s_or_b32 s40, s4, s5
; SI-NEXT: s_and_b32 s4, s21, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s98, 16
+; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s41, s4, s5
; SI-NEXT: s_and_b32 s4, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s97, 16
+; SI-NEXT: s_lshl_b32 s5, s42, 16
+; SI-NEXT: s_mov_b32 s69, s42
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s96, 16
+; SI-NEXT: s_lshl_b32 s5, s43, 16
+; SI-NEXT: s_mov_b32 s70, s7
+; SI-NEXT: s_mov_b32 s7, s35
+; SI-NEXT: s_mov_b32 s35, s43
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s87, 16
+; SI-NEXT: s_lshl_b32 s5, s44, 16
+; SI-NEXT: s_mov_b32 s99, s44
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s86, 16
+; SI-NEXT: s_lshl_b32 s5, s45, 16
+; SI-NEXT: s_mov_b32 s98, s45
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s85, 16
+; SI-NEXT: s_lshl_b32 s5, s46, 16
+; SI-NEXT: s_mov_b32 s97, s46
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s82, 16
+; SI-NEXT: s_lshl_b32 s5, s47, 16
+; SI-NEXT: s_mov_b32 s87, s47
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s71, 16
+; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s69, 16
+; SI-NEXT: s_lshl_b32 s5, s91, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s83, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s84, 16
+; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s80, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s81, 16
+; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s68, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s70, 16
+; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s34, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s35, 16
+; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s30, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s31, 16
+; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s94, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s95, 16
+; SI-NEXT: s_lshl_b32 s5, s77, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s92, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s93, 16
+; SI-NEXT: s_lshl_b32 s5, s56, 16
+; SI-NEXT: s_mov_b32 s82, s91
+; SI-NEXT: s_mov_b32 s91, s79
+; SI-NEXT: s_mov_b32 s79, s56
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s90, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s91, 16
+; SI-NEXT: s_lshl_b32 s5, s57, 16
+; SI-NEXT: s_mov_b32 s81, s89
+; SI-NEXT: s_mov_b32 s89, s77
+; SI-NEXT: s_mov_b32 s77, s57
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s88, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s89, 16
+; SI-NEXT: s_lshl_b32 s5, s58, 16
+; SI-NEXT: s_mov_b32 s96, s31
+; SI-NEXT: s_mov_b32 s31, s58
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s78, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s79, 16
+; SI-NEXT: s_lshl_b32 s5, s59, 16
+; SI-NEXT: s_mov_b32 s85, s95
+; SI-NEXT: s_mov_b32 s95, s59
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_and_b32 s4, s76, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s77, 16
+; SI-NEXT: s_lshl_b32 s5, s60, 16
+; SI-NEXT: s_mov_b32 s84, s93
+; SI-NEXT: s_mov_b32 s93, s60
; SI-NEXT: s_or_b32 s60, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s75, 16
+; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s61, s4, s5
; SI-NEXT: s_and_b32 s4, s72, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s73, 16
+; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s62, s4, s5
; SI-NEXT: s_and_b32 s4, s14, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s15, 16
+; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s63, s4, s5
; SI-NEXT: s_and_b32 s4, s12, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s64, 16
+; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s64, s4, s5
; SI-NEXT: s_and_b32 s4, s10, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s65, 16
+; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s65, s4, s5
; SI-NEXT: s_and_b32 s4, s8, 0xffff
-; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
+; SI-NEXT: s_lshl_b32 s5, s15, 16
; SI-NEXT: s_or_b32 s66, s4, s5
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
+; SI-NEXT: s_mov_b32 s86, vcc_hi
+; SI-NEXT: s_mov_b32 s75, s73
+; SI-NEXT: s_mov_b32 s73, s15
+; SI-NEXT: s_mov_b32 s15, vcc_lo
; SI-NEXT: s_or_b32 s67, s4, s5
; SI-NEXT: s_cbranch_execnz .LBB47_4
; SI-NEXT: .LBB47_2: ; %cmp.true
@@ -68184,11 +68244,11 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s7
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s71
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_cvt_f32_f16_e32 v4, s19
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s99
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s70
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
@@ -68199,7 +68259,7 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f32_f16_e32 v6, s20
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s98
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s7
; SI-NEXT: v_cvt_f32_f16_e32 v7, s21
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
@@ -68208,11 +68268,11 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v6, s97
+; SI-NEXT: v_cvt_f32_f16_e32 v6, s69
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v7, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, s22
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s96
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s35
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
@@ -68223,7 +68283,7 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f32_f16_e32 v9, s23
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s87
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s99
; SI-NEXT: v_cvt_f32_f16_e32 v10, s24
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
@@ -68232,11 +68292,11 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_or_b32_e32 v7, v9, v7
-; SI-NEXT: v_cvt_f32_f16_e32 v9, s86
+; SI-NEXT: v_cvt_f32_f16_e32 v9, s98
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_cvt_f32_f16_e32 v10, s25
-; SI-NEXT: v_cvt_f32_f16_e32 v11, s85
+; SI-NEXT: v_cvt_f32_f16_e32 v11, s97
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
@@ -68247,7 +68307,7 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f32_f16_e32 v12, s26
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; SI-NEXT: v_cvt_f32_f16_e32 v11, s82
+; SI-NEXT: v_cvt_f32_f16_e32 v11, s87
; SI-NEXT: v_cvt_f32_f16_e32 v13, s27
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
@@ -68256,11 +68316,11 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_or_b32_e32 v10, v12, v10
-; SI-NEXT: v_cvt_f32_f16_e32 v12, s71
+; SI-NEXT: v_cvt_f32_f16_e32 v12, s85
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: v_cvt_f32_f16_e32 v13, s28
-; SI-NEXT: v_cvt_f32_f16_e32 v14, s69
+; SI-NEXT: v_cvt_f32_f16_e32 v14, s82
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
@@ -68271,7 +68331,7 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f32_f16_e32 v15, s29
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; SI-NEXT: v_cvt_f32_f16_e32 v14, s84
+; SI-NEXT: v_cvt_f32_f16_e32 v14, s96
; SI-NEXT: v_cvt_f32_f16_e32 v16, s83
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
@@ -68280,11 +68340,11 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_or_b32_e32 v13, v15, v13
-; SI-NEXT: v_cvt_f32_f16_e32 v15, s81
+; SI-NEXT: v_cvt_f32_f16_e32 v15, s86
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_cvt_f32_f16_e32 v16, s80
-; SI-NEXT: v_cvt_f32_f16_e32 v17, s70
+; SI-NEXT: v_cvt_f32_f16_e32 v17, s84
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
@@ -68295,7 +68355,7 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f32_f16_e32 v18, s68
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; SI-NEXT: v_cvt_f32_f16_e32 v17, s35
+; SI-NEXT: v_cvt_f32_f16_e32 v17, s81
; SI-NEXT: v_cvt_f32_f16_e32 v19, s34
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
@@ -68304,11 +68364,11 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_or_b32_e32 v16, v18, v16
-; SI-NEXT: v_cvt_f32_f16_e32 v18, s31
+; SI-NEXT: v_cvt_f32_f16_e32 v18, s91
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: v_cvt_f32_f16_e32 v19, s30
-; SI-NEXT: v_cvt_f32_f16_e32 v20, s95
+; SI-NEXT: v_cvt_f32_f16_e32 v20, s89
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
@@ -68319,7 +68379,7 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f32_f16_e32 v21, s94
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
-; SI-NEXT: v_cvt_f32_f16_e32 v20, s93
+; SI-NEXT: v_cvt_f32_f16_e32 v20, s79
; SI-NEXT: v_cvt_f32_f16_e32 v22, s92
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
@@ -68328,11 +68388,11 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_or_b32_e32 v19, v21, v19
-; SI-NEXT: v_cvt_f32_f16_e32 v21, s91
+; SI-NEXT: v_cvt_f32_f16_e32 v21, s77
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_cvt_f32_f16_e32 v22, s90
-; SI-NEXT: v_cvt_f32_f16_e32 v23, s89
+; SI-NEXT: v_cvt_f32_f16_e32 v23, s31
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
@@ -68343,7 +68403,7 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f32_f16_e32 v24, s88
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; SI-NEXT: v_cvt_f32_f16_e32 v23, s79
+; SI-NEXT: v_cvt_f32_f16_e32 v23, s95
; SI-NEXT: v_cvt_f32_f16_e32 v25, s78
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
@@ -68352,11 +68412,12 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_or_b32_e32 v22, v24, v22
-; SI-NEXT: v_cvt_f32_f16_e32 v24, s77
+; SI-NEXT: v_cvt_f32_f16_e32 v24, s93
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_lshr_b32 s4, s74, 16
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: v_cvt_f32_f16_e32 v25, s76
-; SI-NEXT: v_cvt_f32_f16_e32 v26, s75
+; SI-NEXT: v_cvt_f32_f16_e32 v26, s4
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
@@ -68364,10 +68425,11 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_lshr_b32 s4, s72, 16
; SI-NEXT: v_cvt_f32_f16_e32 v27, s74
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
-; SI-NEXT: v_cvt_f32_f16_e32 v26, s73
+; SI-NEXT: v_cvt_f32_f16_e32 v26, s4
; SI-NEXT: v_cvt_f32_f16_e32 v28, s72
; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v27
; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
@@ -68375,10 +68437,11 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
+; SI-NEXT: s_lshr_b32 s4, s14, 16
; SI-NEXT: v_or_b32_e32 v25, v27, v25
-; SI-NEXT: v_cvt_f32_f16_e32 v27, s15
+; SI-NEXT: v_cvt_f32_f16_e32 v27, s4
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_readlane_b32 s4, v35, 3
+; SI-NEXT: s_lshr_b32 s4, s12, 16
; SI-NEXT: v_or_b32_e32 v26, v28, v26
; SI-NEXT: v_cvt_f32_f16_e32 v28, s14
; SI-NEXT: v_cvt_f32_f16_e32 v29, s4
@@ -68389,11 +68452,10 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_readlane_b32 s4, v35, 2
; SI-NEXT: v_cvt_f32_f16_e32 v30, s12
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; SI-NEXT: v_cvt_f32_f16_e32 v29, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v29, s75
; SI-NEXT: v_cvt_f32_f16_e32 v31, s10
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
@@ -68401,14 +68463,12 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
; SI-NEXT: v_add_f32_e32 v31, 0x38000000, v31
; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
-; SI-NEXT: v_readlane_b32 s4, v35, 1
; SI-NEXT: v_or_b32_e32 v28, v30, v28
-; SI-NEXT: v_cvt_f32_f16_e32 v30, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v30, s73
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_readlane_b32 s4, v35, 0
; SI-NEXT: v_or_b32_e32 v29, v31, v29
; SI-NEXT: v_cvt_f32_f16_e32 v31, s8
-; SI-NEXT: v_cvt_f32_f16_e32 v32, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v32, s15
; SI-NEXT: v_cvt_f32_f16_e32 v33, s6
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
@@ -68424,6 +68484,31 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v31, v33, v31
; SI-NEXT: s_branch .LBB47_5
; SI-NEXT: .LBB47_3:
+; SI-NEXT: s_mov_b32 s71, s39
+; SI-NEXT: s_mov_b32 s70, s7
+; SI-NEXT: s_mov_b32 s7, s35
+; SI-NEXT: s_mov_b32 s69, s42
+; SI-NEXT: s_mov_b32 s35, s43
+; SI-NEXT: s_mov_b32 s99, s44
+; SI-NEXT: s_mov_b32 s98, s45
+; SI-NEXT: s_mov_b32 s97, s46
+; SI-NEXT: s_mov_b32 s96, s31
+; SI-NEXT: s_mov_b32 s87, s47
+; SI-NEXT: s_mov_b32 s86, vcc_hi
+; SI-NEXT: s_mov_b32 s85, s95
+; SI-NEXT: s_mov_b32 s84, s93
+; SI-NEXT: s_mov_b32 s82, s91
+; SI-NEXT: s_mov_b32 s81, s89
+; SI-NEXT: s_mov_b32 s91, s79
+; SI-NEXT: s_mov_b32 s89, s77
+; SI-NEXT: s_mov_b32 s79, s56
+; SI-NEXT: s_mov_b32 s77, s57
+; SI-NEXT: s_mov_b32 s31, s58
+; SI-NEXT: s_mov_b32 s95, s59
+; SI-NEXT: s_mov_b32 s93, s60
+; SI-NEXT: s_mov_b32 s75, s73
+; SI-NEXT: s_mov_b32 s73, s15
+; SI-NEXT: s_mov_b32 s15, vcc_lo
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: s_branch .LBB47_2
; SI-NEXT: .LBB47_4:
@@ -68498,7 +68583,6 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; SI-NEXT: v_readlane_b32 s30, v34, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -101355,9 +101439,8 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v34, s30, 0
; SI-NEXT: v_writelane_b32 v34, s31, 1
; SI-NEXT: v_writelane_b32 v34, s34, 2
@@ -101392,12 +101475,7 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_writelane_b32 v34, s87, 31
; SI-NEXT: v_writelane_b32 v34, s96, 32
; SI-NEXT: v_readfirstlane_b32 s6, v17
-; SI-NEXT: v_writelane_b32 v34, s97, 33
-; SI-NEXT: s_lshr_b32 vcc_lo, s6, 16
; SI-NEXT: v_readfirstlane_b32 s8, v16
-; SI-NEXT: ; implicit-def: $vgpr35 : SGPR spill to VGPR lane
-; SI-NEXT: v_writelane_b32 v34, s98, 34
-; SI-NEXT: s_lshr_b32 vcc_hi, s8, 16
; SI-NEXT: v_readfirstlane_b32 s10, v15
; SI-NEXT: v_readfirstlane_b32 s12, v14
; SI-NEXT: v_readfirstlane_b32 s14, v13
@@ -101414,44 +101492,43 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s68, v2
; SI-NEXT: v_readfirstlane_b32 s80, v1
; SI-NEXT: v_readfirstlane_b32 s83, v0
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v35, vcc_lo, 0
-; SI-NEXT: v_writelane_b32 v34, s99, 35
-; SI-NEXT: s_lshr_b32 s69, s29, 16
-; SI-NEXT: s_lshr_b32 s71, s28, 16
-; SI-NEXT: s_lshr_b32 s82, s27, 16
-; SI-NEXT: s_lshr_b32 s85, s26, 16
-; SI-NEXT: s_lshr_b32 s86, s25, 16
-; SI-NEXT: s_lshr_b32 s87, s24, 16
-; SI-NEXT: s_lshr_b32 s96, s23, 16
-; SI-NEXT: s_lshr_b32 s97, s22, 16
-; SI-NEXT: s_lshr_b32 s98, s21, 16
-; SI-NEXT: s_lshr_b32 s99, s20, 16
-; SI-NEXT: s_lshr_b32 s7, s19, 16
+; SI-NEXT: v_writelane_b32 v34, s97, 33
+; SI-NEXT: s_lshr_b32 s91, s29, 16
+; SI-NEXT: s_lshr_b32 s95, s28, 16
+; SI-NEXT: s_lshr_b32 s47, s27, 16
+; SI-NEXT: s_lshr_b32 s46, s26, 16
+; SI-NEXT: s_lshr_b32 s45, s25, 16
+; SI-NEXT: s_lshr_b32 s44, s24, 16
+; SI-NEXT: s_lshr_b32 s43, s23, 16
+; SI-NEXT: s_lshr_b32 s42, s22, 16
+; SI-NEXT: s_lshr_b32 s35, s21, 16
+; SI-NEXT: s_lshr_b32 s7, s20, 16
+; SI-NEXT: s_lshr_b32 s39, s19, 16
; SI-NEXT: s_lshr_b32 s9, s18, 16
; SI-NEXT: s_lshr_b32 s11, s17, 16
; SI-NEXT: s_lshr_b32 s13, s16, 16
-; SI-NEXT: s_lshr_b32 s65, s10, 16
-; SI-NEXT: s_lshr_b32 s64, s12, 16
-; SI-NEXT: s_lshr_b32 s15, s14, 16
-; SI-NEXT: s_lshr_b32 s73, s72, 16
-; SI-NEXT: s_lshr_b32 s75, s74, 16
-; SI-NEXT: s_lshr_b32 s77, s76, 16
-; SI-NEXT: s_lshr_b32 s79, s78, 16
-; SI-NEXT: s_lshr_b32 s89, s88, 16
-; SI-NEXT: s_lshr_b32 s91, s90, 16
-; SI-NEXT: s_lshr_b32 s93, s92, 16
-; SI-NEXT: s_lshr_b32 s95, s94, 16
-; SI-NEXT: s_lshr_b32 s31, s30, 16
-; SI-NEXT: s_lshr_b32 s35, s34, 16
-; SI-NEXT: s_lshr_b32 s70, s68, 16
-; SI-NEXT: s_lshr_b32 s81, s80, 16
-; SI-NEXT: s_lshr_b32 s84, s83, 16
+; SI-NEXT: s_lshr_b32 vcc_lo, s6, 16
+; SI-NEXT: s_lshr_b32 s15, s8, 16
+; SI-NEXT: s_lshr_b32 s73, s10, 16
+; SI-NEXT: s_lshr_b32 s75, s12, 16
+; SI-NEXT: s_lshr_b32 s63, s14, 16
+; SI-NEXT: s_lshr_b32 s62, s72, 16
+; SI-NEXT: s_lshr_b32 s61, s74, 16
+; SI-NEXT: s_lshr_b32 s60, s76, 16
+; SI-NEXT: s_lshr_b32 s59, s78, 16
+; SI-NEXT: s_lshr_b32 s58, s88, 16
+; SI-NEXT: s_lshr_b32 s57, s90, 16
+; SI-NEXT: s_lshr_b32 s56, s92, 16
+; SI-NEXT: s_lshr_b32 s77, s94, 16
+; SI-NEXT: s_lshr_b32 s79, s30, 16
+; SI-NEXT: s_lshr_b32 s89, s34, 16
+; SI-NEXT: s_lshr_b32 s93, s68, 16
+; SI-NEXT: s_lshr_b32 vcc_hi, s80, 16
+; SI-NEXT: s_lshr_b32 s31, s83, 16
; SI-NEXT: v_readfirstlane_b32 s4, v18
-; SI-NEXT: v_writelane_b32 v35, vcc_hi, 1
+; SI-NEXT: v_writelane_b32 v34, s98, 34
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v35, s65, 2
-; SI-NEXT: v_writelane_b32 v35, s64, 3
+; SI-NEXT: v_writelane_b32 v34, s99, 35
; SI-NEXT: s_cbranch_scc0 .LBB67_3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
@@ -101461,94 +101538,119 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_lshl_b32 s5, s9, 16
; SI-NEXT: s_or_b32 s38, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s7, 16
+; SI-NEXT: s_lshl_b32 s5, s39, 16
; SI-NEXT: s_and_b32 s40, s17, 0xffff
; SI-NEXT: s_lshl_b32 s41, s11, 16
+; SI-NEXT: s_mov_b32 s71, s39
; SI-NEXT: s_or_b32 s39, s4, s5
; SI-NEXT: s_and_b32 s4, s20, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s99, 16
+; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s37, s40, s41
; SI-NEXT: s_or_b32 s40, s4, s5
; SI-NEXT: s_and_b32 s4, s21, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s98, 16
+; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s41, s4, s5
; SI-NEXT: s_and_b32 s4, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s97, 16
+; SI-NEXT: s_lshl_b32 s5, s42, 16
+; SI-NEXT: s_mov_b32 s69, s42
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s96, 16
+; SI-NEXT: s_lshl_b32 s5, s43, 16
+; SI-NEXT: s_mov_b32 s70, s7
+; SI-NEXT: s_mov_b32 s7, s35
+; SI-NEXT: s_mov_b32 s35, s43
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s87, 16
+; SI-NEXT: s_lshl_b32 s5, s44, 16
+; SI-NEXT: s_mov_b32 s99, s44
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s86, 16
+; SI-NEXT: s_lshl_b32 s5, s45, 16
+; SI-NEXT: s_mov_b32 s98, s45
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s85, 16
+; SI-NEXT: s_lshl_b32 s5, s46, 16
+; SI-NEXT: s_mov_b32 s97, s46
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s82, 16
+; SI-NEXT: s_lshl_b32 s5, s47, 16
+; SI-NEXT: s_mov_b32 s87, s47
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s71, 16
+; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s69, 16
+; SI-NEXT: s_lshl_b32 s5, s91, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s83, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s84, 16
+; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s80, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s81, 16
+; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s68, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s70, 16
+; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s34, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s35, 16
+; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s30, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s31, 16
+; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s94, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s95, 16
+; SI-NEXT: s_lshl_b32 s5, s77, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s92, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s93, 16
+; SI-NEXT: s_lshl_b32 s5, s56, 16
+; SI-NEXT: s_mov_b32 s82, s91
+; SI-NEXT: s_mov_b32 s91, s79
+; SI-NEXT: s_mov_b32 s79, s56
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s90, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s91, 16
+; SI-NEXT: s_lshl_b32 s5, s57, 16
+; SI-NEXT: s_mov_b32 s81, s89
+; SI-NEXT: s_mov_b32 s89, s77
+; SI-NEXT: s_mov_b32 s77, s57
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s88, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s89, 16
+; SI-NEXT: s_lshl_b32 s5, s58, 16
+; SI-NEXT: s_mov_b32 s96, s31
+; SI-NEXT: s_mov_b32 s31, s58
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s78, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s79, 16
+; SI-NEXT: s_lshl_b32 s5, s59, 16
+; SI-NEXT: s_mov_b32 s85, s95
+; SI-NEXT: s_mov_b32 s95, s59
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_and_b32 s4, s76, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s77, 16
+; SI-NEXT: s_lshl_b32 s5, s60, 16
+; SI-NEXT: s_mov_b32 s84, s93
+; SI-NEXT: s_mov_b32 s93, s60
; SI-NEXT: s_or_b32 s60, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s75, 16
+; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s61, s4, s5
; SI-NEXT: s_and_b32 s4, s72, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s73, 16
+; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s62, s4, s5
; SI-NEXT: s_and_b32 s4, s14, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s15, 16
+; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s63, s4, s5
; SI-NEXT: s_and_b32 s4, s12, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s64, 16
+; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s64, s4, s5
; SI-NEXT: s_and_b32 s4, s10, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s65, 16
+; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s65, s4, s5
; SI-NEXT: s_and_b32 s4, s8, 0xffff
-; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
+; SI-NEXT: s_lshl_b32 s5, s15, 16
; SI-NEXT: s_or_b32 s66, s4, s5
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
+; SI-NEXT: s_mov_b32 s86, vcc_hi
+; SI-NEXT: s_mov_b32 s75, s73
+; SI-NEXT: s_mov_b32 s73, s15
+; SI-NEXT: s_mov_b32 s15, vcc_lo
; SI-NEXT: s_or_b32 s67, s4, s5
; SI-NEXT: s_cbranch_execnz .LBB67_4
; SI-NEXT: .LBB67_2: ; %cmp.true
@@ -101574,11 +101676,11 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s7
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s71
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_cvt_f32_f16_e32 v4, s19
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s99
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s70
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
@@ -101589,7 +101691,7 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v6, s20
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s98
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s7
; SI-NEXT: v_cvt_f32_f16_e32 v7, s21
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
@@ -101598,11 +101700,11 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v6, s97
+; SI-NEXT: v_cvt_f32_f16_e32 v6, s69
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v7, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, s22
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s96
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s35
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
@@ -101613,7 +101715,7 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v9, s23
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s87
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s99
; SI-NEXT: v_cvt_f32_f16_e32 v10, s24
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
@@ -101622,11 +101724,11 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_or_b32_e32 v7, v9, v7
-; SI-NEXT: v_cvt_f32_f16_e32 v9, s86
+; SI-NEXT: v_cvt_f32_f16_e32 v9, s98
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_cvt_f32_f16_e32 v10, s25
-; SI-NEXT: v_cvt_f32_f16_e32 v11, s85
+; SI-NEXT: v_cvt_f32_f16_e32 v11, s97
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
@@ -101637,7 +101739,7 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v12, s26
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; SI-NEXT: v_cvt_f32_f16_e32 v11, s82
+; SI-NEXT: v_cvt_f32_f16_e32 v11, s87
; SI-NEXT: v_cvt_f32_f16_e32 v13, s27
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
@@ -101646,11 +101748,11 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_or_b32_e32 v10, v12, v10
-; SI-NEXT: v_cvt_f32_f16_e32 v12, s71
+; SI-NEXT: v_cvt_f32_f16_e32 v12, s85
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: v_cvt_f32_f16_e32 v13, s28
-; SI-NEXT: v_cvt_f32_f16_e32 v14, s69
+; SI-NEXT: v_cvt_f32_f16_e32 v14, s82
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
@@ -101661,7 +101763,7 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v15, s29
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; SI-NEXT: v_cvt_f32_f16_e32 v14, s84
+; SI-NEXT: v_cvt_f32_f16_e32 v14, s96
; SI-NEXT: v_cvt_f32_f16_e32 v16, s83
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
@@ -101670,11 +101772,11 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_or_b32_e32 v13, v15, v13
-; SI-NEXT: v_cvt_f32_f16_e32 v15, s81
+; SI-NEXT: v_cvt_f32_f16_e32 v15, s86
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_cvt_f32_f16_e32 v16, s80
-; SI-NEXT: v_cvt_f32_f16_e32 v17, s70
+; SI-NEXT: v_cvt_f32_f16_e32 v17, s84
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
@@ -101685,7 +101787,7 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v18, s68
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; SI-NEXT: v_cvt_f32_f16_e32 v17, s35
+; SI-NEXT: v_cvt_f32_f16_e32 v17, s81
; SI-NEXT: v_cvt_f32_f16_e32 v19, s34
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
@@ -101694,11 +101796,11 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_or_b32_e32 v16, v18, v16
-; SI-NEXT: v_cvt_f32_f16_e32 v18, s31
+; SI-NEXT: v_cvt_f32_f16_e32 v18, s91
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: v_cvt_f32_f16_e32 v19, s30
-; SI-NEXT: v_cvt_f32_f16_e32 v20, s95
+; SI-NEXT: v_cvt_f32_f16_e32 v20, s89
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
@@ -101709,7 +101811,7 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v21, s94
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
-; SI-NEXT: v_cvt_f32_f16_e32 v20, s93
+; SI-NEXT: v_cvt_f32_f16_e32 v20, s79
; SI-NEXT: v_cvt_f32_f16_e32 v22, s92
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
@@ -101718,11 +101820,11 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_or_b32_e32 v19, v21, v19
-; SI-NEXT: v_cvt_f32_f16_e32 v21, s91
+; SI-NEXT: v_cvt_f32_f16_e32 v21, s77
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_cvt_f32_f16_e32 v22, s90
-; SI-NEXT: v_cvt_f32_f16_e32 v23, s89
+; SI-NEXT: v_cvt_f32_f16_e32 v23, s31
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
@@ -101733,7 +101835,7 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v24, s88
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; SI-NEXT: v_cvt_f32_f16_e32 v23, s79
+; SI-NEXT: v_cvt_f32_f16_e32 v23, s95
; SI-NEXT: v_cvt_f32_f16_e32 v25, s78
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
@@ -101742,11 +101844,12 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_or_b32_e32 v22, v24, v22
-; SI-NEXT: v_cvt_f32_f16_e32 v24, s77
+; SI-NEXT: v_cvt_f32_f16_e32 v24, s93
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_lshr_b32 s4, s74, 16
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: v_cvt_f32_f16_e32 v25, s76
-; SI-NEXT: v_cvt_f32_f16_e32 v26, s75
+; SI-NEXT: v_cvt_f32_f16_e32 v26, s4
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
@@ -101754,10 +101857,11 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_lshr_b32 s4, s72, 16
; SI-NEXT: v_cvt_f32_f16_e32 v27, s74
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
-; SI-NEXT: v_cvt_f32_f16_e32 v26, s73
+; SI-NEXT: v_cvt_f32_f16_e32 v26, s4
; SI-NEXT: v_cvt_f32_f16_e32 v28, s72
; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v27
; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
@@ -101765,10 +101869,11 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
+; SI-NEXT: s_lshr_b32 s4, s14, 16
; SI-NEXT: v_or_b32_e32 v25, v27, v25
-; SI-NEXT: v_cvt_f32_f16_e32 v27, s15
+; SI-NEXT: v_cvt_f32_f16_e32 v27, s4
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_readlane_b32 s4, v35, 3
+; SI-NEXT: s_lshr_b32 s4, s12, 16
; SI-NEXT: v_or_b32_e32 v26, v28, v26
; SI-NEXT: v_cvt_f32_f16_e32 v28, s14
; SI-NEXT: v_cvt_f32_f16_e32 v29, s4
@@ -101779,11 +101884,10 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_readlane_b32 s4, v35, 2
; SI-NEXT: v_cvt_f32_f16_e32 v30, s12
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; SI-NEXT: v_cvt_f32_f16_e32 v29, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v29, s75
; SI-NEXT: v_cvt_f32_f16_e32 v31, s10
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
@@ -101791,14 +101895,12 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
; SI-NEXT: v_add_f32_e32 v31, 0x38000000, v31
; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
-; SI-NEXT: v_readlane_b32 s4, v35, 1
; SI-NEXT: v_or_b32_e32 v28, v30, v28
-; SI-NEXT: v_cvt_f32_f16_e32 v30, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v30, s73
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_readlane_b32 s4, v35, 0
; SI-NEXT: v_or_b32_e32 v29, v31, v29
; SI-NEXT: v_cvt_f32_f16_e32 v31, s8
-; SI-NEXT: v_cvt_f32_f16_e32 v32, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v32, s15
; SI-NEXT: v_cvt_f32_f16_e32 v33, s6
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
@@ -101814,6 +101916,31 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v31, v33, v31
; SI-NEXT: s_branch .LBB67_5
; SI-NEXT: .LBB67_3:
+; SI-NEXT: s_mov_b32 s71, s39
+; SI-NEXT: s_mov_b32 s70, s7
+; SI-NEXT: s_mov_b32 s7, s35
+; SI-NEXT: s_mov_b32 s69, s42
+; SI-NEXT: s_mov_b32 s35, s43
+; SI-NEXT: s_mov_b32 s99, s44
+; SI-NEXT: s_mov_b32 s98, s45
+; SI-NEXT: s_mov_b32 s97, s46
+; SI-NEXT: s_mov_b32 s96, s31
+; SI-NEXT: s_mov_b32 s87, s47
+; SI-NEXT: s_mov_b32 s86, vcc_hi
+; SI-NEXT: s_mov_b32 s85, s95
+; SI-NEXT: s_mov_b32 s84, s93
+; SI-NEXT: s_mov_b32 s82, s91
+; SI-NEXT: s_mov_b32 s81, s89
+; SI-NEXT: s_mov_b32 s91, s79
+; SI-NEXT: s_mov_b32 s89, s77
+; SI-NEXT: s_mov_b32 s79, s56
+; SI-NEXT: s_mov_b32 s77, s57
+; SI-NEXT: s_mov_b32 s31, s58
+; SI-NEXT: s_mov_b32 s95, s59
+; SI-NEXT: s_mov_b32 s93, s60
+; SI-NEXT: s_mov_b32 s75, s73
+; SI-NEXT: s_mov_b32 s73, s15
+; SI-NEXT: s_mov_b32 s15, vcc_lo
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: s_branch .LBB67_2
; SI-NEXT: .LBB67_4:
@@ -101888,7 +102015,6 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_readlane_b32 s30, v34, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -134300,9 +134426,8 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v34, s30, 0
; SI-NEXT: v_writelane_b32 v34, s31, 1
; SI-NEXT: v_writelane_b32 v34, s34, 2
@@ -134337,12 +134462,7 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_writelane_b32 v34, s87, 31
; SI-NEXT: v_writelane_b32 v34, s96, 32
; SI-NEXT: v_readfirstlane_b32 s6, v17
-; SI-NEXT: v_writelane_b32 v34, s97, 33
-; SI-NEXT: s_lshr_b32 vcc_lo, s6, 16
; SI-NEXT: v_readfirstlane_b32 s8, v16
-; SI-NEXT: ; implicit-def: $vgpr35 : SGPR spill to VGPR lane
-; SI-NEXT: v_writelane_b32 v34, s98, 34
-; SI-NEXT: s_lshr_b32 vcc_hi, s8, 16
; SI-NEXT: v_readfirstlane_b32 s10, v15
; SI-NEXT: v_readfirstlane_b32 s12, v14
; SI-NEXT: v_readfirstlane_b32 s14, v13
@@ -134359,44 +134479,43 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_readfirstlane_b32 s68, v2
; SI-NEXT: v_readfirstlane_b32 s80, v1
; SI-NEXT: v_readfirstlane_b32 s83, v0
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v35, vcc_lo, 0
-; SI-NEXT: v_writelane_b32 v34, s99, 35
-; SI-NEXT: s_lshr_b32 s69, s29, 16
-; SI-NEXT: s_lshr_b32 s71, s28, 16
-; SI-NEXT: s_lshr_b32 s82, s27, 16
-; SI-NEXT: s_lshr_b32 s85, s26, 16
-; SI-NEXT: s_lshr_b32 s86, s25, 16
-; SI-NEXT: s_lshr_b32 s87, s24, 16
-; SI-NEXT: s_lshr_b32 s96, s23, 16
-; SI-NEXT: s_lshr_b32 s97, s22, 16
-; SI-NEXT: s_lshr_b32 s98, s21, 16
-; SI-NEXT: s_lshr_b32 s99, s20, 16
-; SI-NEXT: s_lshr_b32 s7, s19, 16
+; SI-NEXT: v_writelane_b32 v34, s97, 33
+; SI-NEXT: s_lshr_b32 s91, s29, 16
+; SI-NEXT: s_lshr_b32 s95, s28, 16
+; SI-NEXT: s_lshr_b32 s47, s27, 16
+; SI-NEXT: s_lshr_b32 s46, s26, 16
+; SI-NEXT: s_lshr_b32 s45, s25, 16
+; SI-NEXT: s_lshr_b32 s44, s24, 16
+; SI-NEXT: s_lshr_b32 s43, s23, 16
+; SI-NEXT: s_lshr_b32 s42, s22, 16
+; SI-NEXT: s_lshr_b32 s35, s21, 16
+; SI-NEXT: s_lshr_b32 s7, s20, 16
+; SI-NEXT: s_lshr_b32 s39, s19, 16
; SI-NEXT: s_lshr_b32 s9, s18, 16
; SI-NEXT: s_lshr_b32 s11, s17, 16
; SI-NEXT: s_lshr_b32 s13, s16, 16
-; SI-NEXT: s_lshr_b32 s65, s10, 16
-; SI-NEXT: s_lshr_b32 s64, s12, 16
-; SI-NEXT: s_lshr_b32 s15, s14, 16
-; SI-NEXT: s_lshr_b32 s73, s72, 16
-; SI-NEXT: s_lshr_b32 s75, s74, 16
-; SI-NEXT: s_lshr_b32 s77, s76, 16
-; SI-NEXT: s_lshr_b32 s79, s78, 16
-; SI-NEXT: s_lshr_b32 s89, s88, 16
-; SI-NEXT: s_lshr_b32 s91, s90, 16
-; SI-NEXT: s_lshr_b32 s93, s92, 16
-; SI-NEXT: s_lshr_b32 s95, s94, 16
-; SI-NEXT: s_lshr_b32 s31, s30, 16
-; SI-NEXT: s_lshr_b32 s35, s34, 16
-; SI-NEXT: s_lshr_b32 s70, s68, 16
-; SI-NEXT: s_lshr_b32 s81, s80, 16
-; SI-NEXT: s_lshr_b32 s84, s83, 16
+; SI-NEXT: s_lshr_b32 vcc_lo, s6, 16
+; SI-NEXT: s_lshr_b32 s15, s8, 16
+; SI-NEXT: s_lshr_b32 s73, s10, 16
+; SI-NEXT: s_lshr_b32 s75, s12, 16
+; SI-NEXT: s_lshr_b32 s63, s14, 16
+; SI-NEXT: s_lshr_b32 s62, s72, 16
+; SI-NEXT: s_lshr_b32 s61, s74, 16
+; SI-NEXT: s_lshr_b32 s60, s76, 16
+; SI-NEXT: s_lshr_b32 s59, s78, 16
+; SI-NEXT: s_lshr_b32 s58, s88, 16
+; SI-NEXT: s_lshr_b32 s57, s90, 16
+; SI-NEXT: s_lshr_b32 s56, s92, 16
+; SI-NEXT: s_lshr_b32 s77, s94, 16
+; SI-NEXT: s_lshr_b32 s79, s30, 16
+; SI-NEXT: s_lshr_b32 s89, s34, 16
+; SI-NEXT: s_lshr_b32 s93, s68, 16
+; SI-NEXT: s_lshr_b32 vcc_hi, s80, 16
+; SI-NEXT: s_lshr_b32 s31, s83, 16
; SI-NEXT: v_readfirstlane_b32 s4, v18
-; SI-NEXT: v_writelane_b32 v35, vcc_hi, 1
+; SI-NEXT: v_writelane_b32 v34, s98, 34
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v35, s65, 2
-; SI-NEXT: v_writelane_b32 v35, s64, 3
+; SI-NEXT: v_writelane_b32 v34, s99, 35
; SI-NEXT: s_cbranch_scc0 .LBB83_3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
@@ -134406,94 +134525,119 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: s_lshl_b32 s5, s9, 16
; SI-NEXT: s_or_b32 s38, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s7, 16
+; SI-NEXT: s_lshl_b32 s5, s39, 16
; SI-NEXT: s_and_b32 s40, s17, 0xffff
; SI-NEXT: s_lshl_b32 s41, s11, 16
+; SI-NEXT: s_mov_b32 s71, s39
; SI-NEXT: s_or_b32 s39, s4, s5
; SI-NEXT: s_and_b32 s4, s20, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s99, 16
+; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s37, s40, s41
; SI-NEXT: s_or_b32 s40, s4, s5
; SI-NEXT: s_and_b32 s4, s21, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s98, 16
+; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s41, s4, s5
; SI-NEXT: s_and_b32 s4, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s97, 16
+; SI-NEXT: s_lshl_b32 s5, s42, 16
+; SI-NEXT: s_mov_b32 s69, s42
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s96, 16
+; SI-NEXT: s_lshl_b32 s5, s43, 16
+; SI-NEXT: s_mov_b32 s70, s7
+; SI-NEXT: s_mov_b32 s7, s35
+; SI-NEXT: s_mov_b32 s35, s43
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s87, 16
+; SI-NEXT: s_lshl_b32 s5, s44, 16
+; SI-NEXT: s_mov_b32 s99, s44
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s86, 16
+; SI-NEXT: s_lshl_b32 s5, s45, 16
+; SI-NEXT: s_mov_b32 s98, s45
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s85, 16
+; SI-NEXT: s_lshl_b32 s5, s46, 16
+; SI-NEXT: s_mov_b32 s97, s46
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s82, 16
+; SI-NEXT: s_lshl_b32 s5, s47, 16
+; SI-NEXT: s_mov_b32 s87, s47
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s71, 16
+; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s69, 16
+; SI-NEXT: s_lshl_b32 s5, s91, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s83, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s84, 16
+; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s80, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s81, 16
+; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s68, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s70, 16
+; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s34, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s35, 16
+; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s30, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s31, 16
+; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s94, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s95, 16
+; SI-NEXT: s_lshl_b32 s5, s77, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s92, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s93, 16
+; SI-NEXT: s_lshl_b32 s5, s56, 16
+; SI-NEXT: s_mov_b32 s82, s91
+; SI-NEXT: s_mov_b32 s91, s79
+; SI-NEXT: s_mov_b32 s79, s56
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s90, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s91, 16
+; SI-NEXT: s_lshl_b32 s5, s57, 16
+; SI-NEXT: s_mov_b32 s81, s89
+; SI-NEXT: s_mov_b32 s89, s77
+; SI-NEXT: s_mov_b32 s77, s57
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s88, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s89, 16
+; SI-NEXT: s_lshl_b32 s5, s58, 16
+; SI-NEXT: s_mov_b32 s96, s31
+; SI-NEXT: s_mov_b32 s31, s58
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s78, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s79, 16
+; SI-NEXT: s_lshl_b32 s5, s59, 16
+; SI-NEXT: s_mov_b32 s85, s95
+; SI-NEXT: s_mov_b32 s95, s59
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_and_b32 s4, s76, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s77, 16
+; SI-NEXT: s_lshl_b32 s5, s60, 16
+; SI-NEXT: s_mov_b32 s84, s93
+; SI-NEXT: s_mov_b32 s93, s60
; SI-NEXT: s_or_b32 s60, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s75, 16
+; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s61, s4, s5
; SI-NEXT: s_and_b32 s4, s72, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s73, 16
+; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s62, s4, s5
; SI-NEXT: s_and_b32 s4, s14, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s15, 16
+; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s63, s4, s5
; SI-NEXT: s_and_b32 s4, s12, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s64, 16
+; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s64, s4, s5
; SI-NEXT: s_and_b32 s4, s10, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s65, 16
+; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s65, s4, s5
; SI-NEXT: s_and_b32 s4, s8, 0xffff
-; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
+; SI-NEXT: s_lshl_b32 s5, s15, 16
; SI-NEXT: s_or_b32 s66, s4, s5
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
+; SI-NEXT: s_mov_b32 s86, vcc_hi
+; SI-NEXT: s_mov_b32 s75, s73
+; SI-NEXT: s_mov_b32 s73, s15
+; SI-NEXT: s_mov_b32 s15, vcc_lo
; SI-NEXT: s_or_b32 s67, s4, s5
; SI-NEXT: s_cbranch_execnz .LBB83_4
; SI-NEXT: .LBB83_2: ; %cmp.true
@@ -134519,11 +134663,11 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s7
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s71
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v2, v4, v2
; SI-NEXT: v_cvt_f32_f16_e32 v4, s19
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s99
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s70
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
@@ -134534,7 +134678,7 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f32_f16_e32 v6, s20
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s98
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s7
; SI-NEXT: v_cvt_f32_f16_e32 v7, s21
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
@@ -134543,11 +134687,11 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v6, s97
+; SI-NEXT: v_cvt_f32_f16_e32 v6, s69
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v7, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, s22
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s96
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s35
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
@@ -134558,7 +134702,7 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f32_f16_e32 v9, s23
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s87
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s99
; SI-NEXT: v_cvt_f32_f16_e32 v10, s24
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
@@ -134567,11 +134711,11 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_or_b32_e32 v7, v9, v7
-; SI-NEXT: v_cvt_f32_f16_e32 v9, s86
+; SI-NEXT: v_cvt_f32_f16_e32 v9, s98
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_cvt_f32_f16_e32 v10, s25
-; SI-NEXT: v_cvt_f32_f16_e32 v11, s85
+; SI-NEXT: v_cvt_f32_f16_e32 v11, s97
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
@@ -134582,7 +134726,7 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f32_f16_e32 v12, s26
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; SI-NEXT: v_cvt_f32_f16_e32 v11, s82
+; SI-NEXT: v_cvt_f32_f16_e32 v11, s87
; SI-NEXT: v_cvt_f32_f16_e32 v13, s27
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
@@ -134591,11 +134735,11 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_or_b32_e32 v10, v12, v10
-; SI-NEXT: v_cvt_f32_f16_e32 v12, s71
+; SI-NEXT: v_cvt_f32_f16_e32 v12, s85
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: v_cvt_f32_f16_e32 v13, s28
-; SI-NEXT: v_cvt_f32_f16_e32 v14, s69
+; SI-NEXT: v_cvt_f32_f16_e32 v14, s82
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
@@ -134606,7 +134750,7 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f32_f16_e32 v15, s29
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; SI-NEXT: v_cvt_f32_f16_e32 v14, s84
+; SI-NEXT: v_cvt_f32_f16_e32 v14, s96
; SI-NEXT: v_cvt_f32_f16_e32 v16, s83
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
@@ -134615,11 +134759,11 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_or_b32_e32 v13, v15, v13
-; SI-NEXT: v_cvt_f32_f16_e32 v15, s81
+; SI-NEXT: v_cvt_f32_f16_e32 v15, s86
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_cvt_f32_f16_e32 v16, s80
-; SI-NEXT: v_cvt_f32_f16_e32 v17, s70
+; SI-NEXT: v_cvt_f32_f16_e32 v17, s84
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
@@ -134630,7 +134774,7 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f32_f16_e32 v18, s68
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; SI-NEXT: v_cvt_f32_f16_e32 v17, s35
+; SI-NEXT: v_cvt_f32_f16_e32 v17, s81
; SI-NEXT: v_cvt_f32_f16_e32 v19, s34
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
@@ -134639,11 +134783,11 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_or_b32_e32 v16, v18, v16
-; SI-NEXT: v_cvt_f32_f16_e32 v18, s31
+; SI-NEXT: v_cvt_f32_f16_e32 v18, s91
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: v_cvt_f32_f16_e32 v19, s30
-; SI-NEXT: v_cvt_f32_f16_e32 v20, s95
+; SI-NEXT: v_cvt_f32_f16_e32 v20, s89
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
@@ -134654,7 +134798,7 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f32_f16_e32 v21, s94
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
-; SI-NEXT: v_cvt_f32_f16_e32 v20, s93
+; SI-NEXT: v_cvt_f32_f16_e32 v20, s79
; SI-NEXT: v_cvt_f32_f16_e32 v22, s92
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
@@ -134663,11 +134807,11 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_or_b32_e32 v19, v21, v19
-; SI-NEXT: v_cvt_f32_f16_e32 v21, s91
+; SI-NEXT: v_cvt_f32_f16_e32 v21, s77
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_cvt_f32_f16_e32 v22, s90
-; SI-NEXT: v_cvt_f32_f16_e32 v23, s89
+; SI-NEXT: v_cvt_f32_f16_e32 v23, s31
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
@@ -134678,7 +134822,7 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f32_f16_e32 v24, s88
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; SI-NEXT: v_cvt_f32_f16_e32 v23, s79
+; SI-NEXT: v_cvt_f32_f16_e32 v23, s95
; SI-NEXT: v_cvt_f32_f16_e32 v25, s78
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
@@ -134687,11 +134831,12 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_or_b32_e32 v22, v24, v22
-; SI-NEXT: v_cvt_f32_f16_e32 v24, s77
+; SI-NEXT: v_cvt_f32_f16_e32 v24, s93
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: s_lshr_b32 s4, s74, 16
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: v_cvt_f32_f16_e32 v25, s76
-; SI-NEXT: v_cvt_f32_f16_e32 v26, s75
+; SI-NEXT: v_cvt_f32_f16_e32 v26, s4
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
@@ -134699,10 +134844,11 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: s_lshr_b32 s4, s72, 16
; SI-NEXT: v_cvt_f32_f16_e32 v27, s74
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
-; SI-NEXT: v_cvt_f32_f16_e32 v26, s73
+; SI-NEXT: v_cvt_f32_f16_e32 v26, s4
; SI-NEXT: v_cvt_f32_f16_e32 v28, s72
; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v27
; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
@@ -134710,10 +134856,11 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
+; SI-NEXT: s_lshr_b32 s4, s14, 16
; SI-NEXT: v_or_b32_e32 v25, v27, v25
-; SI-NEXT: v_cvt_f32_f16_e32 v27, s15
+; SI-NEXT: v_cvt_f32_f16_e32 v27, s4
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: v_readlane_b32 s4, v35, 3
+; SI-NEXT: s_lshr_b32 s4, s12, 16
; SI-NEXT: v_or_b32_e32 v26, v28, v26
; SI-NEXT: v_cvt_f32_f16_e32 v28, s14
; SI-NEXT: v_cvt_f32_f16_e32 v29, s4
@@ -134724,11 +134871,10 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_readlane_b32 s4, v35, 2
; SI-NEXT: v_cvt_f32_f16_e32 v30, s12
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; SI-NEXT: v_cvt_f32_f16_e32 v29, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v29, s75
; SI-NEXT: v_cvt_f32_f16_e32 v31, s10
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
@@ -134736,14 +134882,12 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
; SI-NEXT: v_add_f32_e32 v31, 0x38000000, v31
; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
-; SI-NEXT: v_readlane_b32 s4, v35, 1
; SI-NEXT: v_or_b32_e32 v28, v30, v28
-; SI-NEXT: v_cvt_f32_f16_e32 v30, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v30, s73
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_readlane_b32 s4, v35, 0
; SI-NEXT: v_or_b32_e32 v29, v31, v29
; SI-NEXT: v_cvt_f32_f16_e32 v31, s8
-; SI-NEXT: v_cvt_f32_f16_e32 v32, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v32, s15
; SI-NEXT: v_cvt_f32_f16_e32 v33, s6
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
@@ -134759,6 +134903,31 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_or_b32_e32 v31, v33, v31
; SI-NEXT: s_branch .LBB83_5
; SI-NEXT: .LBB83_3:
+; SI-NEXT: s_mov_b32 s71, s39
+; SI-NEXT: s_mov_b32 s70, s7
+; SI-NEXT: s_mov_b32 s7, s35
+; SI-NEXT: s_mov_b32 s69, s42
+; SI-NEXT: s_mov_b32 s35, s43
+; SI-NEXT: s_mov_b32 s99, s44
+; SI-NEXT: s_mov_b32 s98, s45
+; SI-NEXT: s_mov_b32 s97, s46
+; SI-NEXT: s_mov_b32 s96, s31
+; SI-NEXT: s_mov_b32 s87, s47
+; SI-NEXT: s_mov_b32 s86, vcc_hi
+; SI-NEXT: s_mov_b32 s85, s95
+; SI-NEXT: s_mov_b32 s84, s93
+; SI-NEXT: s_mov_b32 s82, s91
+; SI-NEXT: s_mov_b32 s81, s89
+; SI-NEXT: s_mov_b32 s91, s79
+; SI-NEXT: s_mov_b32 s89, s77
+; SI-NEXT: s_mov_b32 s79, s56
+; SI-NEXT: s_mov_b32 s77, s57
+; SI-NEXT: s_mov_b32 s31, s58
+; SI-NEXT: s_mov_b32 s95, s59
+; SI-NEXT: s_mov_b32 s93, s60
+; SI-NEXT: s_mov_b32 s75, s73
+; SI-NEXT: s_mov_b32 s73, s15
+; SI-NEXT: s_mov_b32 s15, vcc_lo
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: s_branch .LBB83_2
; SI-NEXT: .LBB83_4:
@@ -134833,7 +135002,6 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; SI-NEXT: v_readlane_b32 s30, v34, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -180349,9 +180517,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: s_waitcnt expcnt(2)
; SI-NEXT: v_writelane_b32 v34, s30, 0
; SI-NEXT: v_writelane_b32 v34, s31, 1
; SI-NEXT: v_writelane_b32 v34, s34, 2
@@ -180379,96 +180546,84 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_writelane_b32 v34, s80, 24
; SI-NEXT: v_writelane_b32 v34, s81, 25
; SI-NEXT: v_writelane_b32 v34, s82, 26
-; SI-NEXT: s_lshr_b32 s5, s16, 16
-; SI-NEXT: ; implicit-def: $vgpr37 : SGPR spill to VGPR lane
; SI-NEXT: v_writelane_b32 v34, s83, 27
-; SI-NEXT: s_lshr_b32 s6, s18, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v37, s5, 0
; SI-NEXT: v_writelane_b32 v34, s84, 28
-; SI-NEXT: s_lshr_b32 s7, s20, 16
-; SI-NEXT: v_writelane_b32 v37, s6, 2
; SI-NEXT: v_writelane_b32 v34, s85, 29
-; SI-NEXT: s_lshr_b32 s8, s22, 16
-; SI-NEXT: v_writelane_b32 v37, s7, 4
; SI-NEXT: v_writelane_b32 v34, s86, 30
-; SI-NEXT: s_lshr_b32 s9, s24, 16
-; SI-NEXT: v_writelane_b32 v37, s8, 5
; SI-NEXT: v_writelane_b32 v34, s87, 31
-; SI-NEXT: s_lshr_b32 s10, s26, 16
-; SI-NEXT: v_writelane_b32 v37, s9, 6
; SI-NEXT: v_writelane_b32 v34, s96, 32
-; SI-NEXT: s_lshr_b32 s11, s28, 16
-; SI-NEXT: v_readfirstlane_b32 s31, v3
-; SI-NEXT: v_writelane_b32 v37, s10, 7
; SI-NEXT: v_writelane_b32 v34, s97, 33
-; SI-NEXT: v_readfirstlane_b32 s37, v5
-; SI-NEXT: s_lshr_b32 s12, s31, 16
-; SI-NEXT: v_writelane_b32 v37, s11, 8
; SI-NEXT: v_writelane_b32 v34, s98, 34
-; SI-NEXT: v_readfirstlane_b32 s81, v18
-; SI-NEXT: v_readfirstlane_b32 s83, v17
-; SI-NEXT: v_readfirstlane_b32 s70, v16
-; SI-NEXT: v_readfirstlane_b32 s34, v15
-; SI-NEXT: v_readfirstlane_b32 s66, v14
-; SI-NEXT: v_readfirstlane_b32 s68, v13
-; SI-NEXT: v_readfirstlane_b32 s54, v12
-; SI-NEXT: v_readfirstlane_b32 s64, v11
-; SI-NEXT: v_readfirstlane_b32 s51, v10
-; SI-NEXT: v_readfirstlane_b32 s52, v9
-; SI-NEXT: v_readfirstlane_b32 s39, v8
-; SI-NEXT: v_readfirstlane_b32 s49, v7
-; SI-NEXT: v_readfirstlane_b32 s35, v6
-; SI-NEXT: s_lshr_b32 s13, s37, 16
-; SI-NEXT: v_readfirstlane_b32 s95, v4
+; SI-NEXT: v_readfirstlane_b32 s67, v18
+; SI-NEXT: v_readfirstlane_b32 s69, v17
+; SI-NEXT: v_readfirstlane_b32 s64, v16
+; SI-NEXT: v_readfirstlane_b32 s66, v15
+; SI-NEXT: v_readfirstlane_b32 s53, v14
+; SI-NEXT: v_readfirstlane_b32 s55, v13
+; SI-NEXT: v_readfirstlane_b32 s51, v12
+; SI-NEXT: v_readfirstlane_b32 s52, v11
+; SI-NEXT: v_readfirstlane_b32 s48, v10
+; SI-NEXT: v_readfirstlane_b32 s50, v9
+; SI-NEXT: v_readfirstlane_b32 s37, v8
+; SI-NEXT: v_readfirstlane_b32 s39, v7
+; SI-NEXT: v_readfirstlane_b32 s34, v6
+; SI-NEXT: v_readfirstlane_b32 s36, v5
+; SI-NEXT: v_readfirstlane_b32 s94, v4
+; SI-NEXT: v_readfirstlane_b32 s31, v3
; SI-NEXT: v_readfirstlane_b32 s91, v2
; SI-NEXT: v_readfirstlane_b32 s93, v1
-; SI-NEXT: v_writelane_b32 v37, s12, 9
; SI-NEXT: v_writelane_b32 v34, s99, 35
-; SI-NEXT: s_mov_b32 s53, s16
; SI-NEXT: s_lshr_b32 s90, s29, 16
+; SI-NEXT: s_lshr_b32 s11, s28, 16
; SI-NEXT: s_lshr_b32 s89, s27, 16
+; SI-NEXT: s_lshr_b32 s10, s26, 16
; SI-NEXT: s_lshr_b32 s88, s25, 16
+; SI-NEXT: s_lshr_b32 s9, s24, 16
; SI-NEXT: s_lshr_b32 s79, s23, 16
+; SI-NEXT: s_lshr_b32 s8, s22, 16
; SI-NEXT: s_lshr_b32 s78, s21, 16
-; SI-NEXT: s_lshr_b32 s77, s19, 16
-; SI-NEXT: s_lshr_b32 s76, s17, 16
-; SI-NEXT: s_lshr_b32 s82, s81, 16
-; SI-NEXT: s_lshr_b32 s84, s83, 16
-; SI-NEXT: s_lshr_b32 s71, s70, 16
-; SI-NEXT: s_lshr_b32 s80, s34, 16
-; SI-NEXT: s_lshr_b32 s67, s66, 16
-; SI-NEXT: s_lshr_b32 s69, s68, 16
-; SI-NEXT: s_lshr_b32 s55, s54, 16
+; SI-NEXT: s_lshr_b32 s7, s20, 16
+; SI-NEXT: s_lshr_b32 s80, s19, 16
+; SI-NEXT: s_lshr_b32 s6, s18, 16
+; SI-NEXT: s_lshr_b32 s99, s17, 16
+; SI-NEXT: s_lshr_b32 s5, s16, 16
+; SI-NEXT: s_lshr_b32 s68, s67, 16
+; SI-NEXT: s_lshr_b32 s76, s69, 16
; SI-NEXT: s_lshr_b32 s65, s64, 16
+; SI-NEXT: s_lshr_b32 s70, s66, 16
+; SI-NEXT: s_lshr_b32 s54, s53, 16
+; SI-NEXT: s_lshr_b32 vcc_hi, s55, 16
; SI-NEXT: s_lshr_b32 s30, s51, 16
-; SI-NEXT: s_lshr_b32 s16, s52, 16
-; SI-NEXT: s_lshr_b32 s48, s39, 16
-; SI-NEXT: s_lshr_b32 s14, s49, 16
-; SI-NEXT: s_lshr_b32 s36, s35, 16
-; SI-NEXT: s_lshr_b32 s94, s95, 16
+; SI-NEXT: s_lshr_b32 vcc_lo, s52, 16
+; SI-NEXT: s_lshr_b32 s49, s48, 16
+; SI-NEXT: s_lshr_b32 s13, s50, 16
+; SI-NEXT: s_lshr_b32 s38, s37, 16
+; SI-NEXT: s_lshr_b32 s12, s39, 16
+; SI-NEXT: s_lshr_b32 s35, s34, 16
+; SI-NEXT: s_lshr_b32 s83, s36, 16
+; SI-NEXT: s_lshr_b32 s95, s94, 16
+; SI-NEXT: s_lshr_b32 s81, s31, 16
; SI-NEXT: s_lshr_b32 s92, s91, 16
-; SI-NEXT: s_lshr_b32 s99, s93, 16
+; SI-NEXT: s_lshr_b32 s71, s93, 16
; SI-NEXT: v_readfirstlane_b32 s4, v19
-; SI-NEXT: v_writelane_b32 v37, s13, 10
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v37, s14, 11
-; SI-NEXT: v_writelane_b32 v37, s16, 12
-; SI-NEXT: ; implicit-def: $vgpr36 : SGPR spill to VGPR lane
; SI-NEXT: ; implicit-def: $vgpr35 : SGPR spill to VGPR lane
+; SI-NEXT: ; implicit-def: $vgpr36 : SGPR spill to VGPR lane
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_writelane_b32 v35, s16, 0
; SI-NEXT: s_cbranch_scc0 .LBB95_3
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: s_and_b32 s4, s53, 0xffff
+; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_or_b32 s74, s4, s5
; SI-NEXT: s_and_b32 s4, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s76, 16
+; SI-NEXT: s_lshl_b32 s5, s99, 16
; SI-NEXT: s_or_b32 s75, s4, s5
; SI-NEXT: s_and_b32 s4, s18, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s72, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s77, 16
+; SI-NEXT: s_lshl_b32 s5, s80, 16
; SI-NEXT: s_or_b32 s73, s4, s5
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
@@ -180501,274 +180656,279 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s93, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s99, 16
+; SI-NEXT: s_lshl_b32 s5, s71, 16
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s91, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s31, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s12, 16
+; SI-NEXT: s_lshl_b32 s5, s81, 16
; SI-NEXT: s_or_b32 s42, s4, s5
-; SI-NEXT: s_and_b32 s4, s95, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s94, 16
+; SI-NEXT: s_and_b32 s4, s94, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s43, s4, s5
-; SI-NEXT: s_and_b32 s4, s37, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s13, 16
+; SI-NEXT: s_and_b32 s4, s36, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s83, 16
; SI-NEXT: s_or_b32 s40, s4, s5
-; SI-NEXT: s_and_b32 s4, s35, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s36, 16
+; SI-NEXT: s_and_b32 s4, s34, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s41, s4, s5
-; SI-NEXT: s_and_b32 s4, s49, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s14, 16
-; SI-NEXT: s_or_b32 s14, s4, s5
; SI-NEXT: s_and_b32 s4, s39, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s48, 16
+; SI-NEXT: s_lshl_b32 s5, s12, 16
+; SI-NEXT: s_or_b32 s14, s4, s5
+; SI-NEXT: s_and_b32 s4, s37, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s38, 16
; SI-NEXT: s_or_b32 s15, s4, s5
-; SI-NEXT: s_and_b32 s4, s52, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s16, 16
+; SI-NEXT: s_and_b32 s4, s50, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s13, 16
; SI-NEXT: s_or_b32 s12, s4, s5
-; SI-NEXT: s_and_b32 s4, s51, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s30, 16
+; SI-NEXT: s_and_b32 s4, s48, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s49, 16
; SI-NEXT: s_or_b32 s13, s4, s5
-; SI-NEXT: s_and_b32 s4, s64, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s65, 16
+; SI-NEXT: s_and_b32 s4, s52, 0xffff
+; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s10, s4, s5
-; SI-NEXT: s_and_b32 s4, s54, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s55, 16
+; SI-NEXT: s_and_b32 s4, s51, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s30, 16
; SI-NEXT: s_or_b32 s11, s4, s5
-; SI-NEXT: s_and_b32 s4, s68, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s69, 16
+; SI-NEXT: s_and_b32 s4, s55, 0xffff
+; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s8, s4, s5
-; SI-NEXT: s_and_b32 s4, s66, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s67, 16
-; SI-NEXT: s_lshr_b32 s16, s75, 8
+; SI-NEXT: s_and_b32 s4, s53, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s54, 16
; SI-NEXT: s_or_b32 s9, s4, s5
-; SI-NEXT: s_and_b32 s4, s34, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s80, 16
-; SI-NEXT: v_writelane_b32 v35, s16, 1
-; SI-NEXT: s_lshr_b32 s16, s73, 8
+; SI-NEXT: s_and_b32 s4, s66, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s70, 16
; SI-NEXT: s_or_b32 s6, s4, s5
-; SI-NEXT: s_and_b32 s4, s70, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s71, 16
-; SI-NEXT: v_writelane_b32 v35, s16, 0
-; SI-NEXT: s_lshr_b32 s16, s63, 8
+; SI-NEXT: s_and_b32 s4, s64, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s65, 16
; SI-NEXT: s_or_b32 s7, s4, s5
-; SI-NEXT: s_and_b32 s4, s83, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s84, 16
-; SI-NEXT: v_writelane_b32 v36, s16, 63
-; SI-NEXT: s_lshr_b32 s16, s59, 8
+; SI-NEXT: s_and_b32 s4, s69, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s76, 16
; SI-NEXT: s_or_b32 s4, s4, s5
-; SI-NEXT: s_and_b32 s5, s81, 0xffff
-; SI-NEXT: s_lshl_b32 vcc_lo, s82, 16
-; SI-NEXT: v_writelane_b32 v36, s16, 62
-; SI-NEXT: s_lshr_b32 s16, s57, 8
+; SI-NEXT: s_and_b32 s5, s67, 0xffff
+; SI-NEXT: s_lshl_b32 vcc_lo, s68, 16
; SI-NEXT: s_or_b32 s5, s5, vcc_lo
-; SI-NEXT: v_writelane_b32 v36, s16, 61
+; SI-NEXT: s_lshr_b32 vcc_lo, s75, 8
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 57
+; SI-NEXT: s_lshr_b32 vcc_lo, s73, 8
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 56
+; SI-NEXT: s_lshr_b32 vcc_lo, s63, 8
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 55
+; SI-NEXT: s_lshr_b32 vcc_lo, s59, 8
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 54
+; SI-NEXT: s_lshr_b32 vcc_lo, s57, 8
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 53
; SI-NEXT: s_lshr_b32 vcc_lo, s61, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 60
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 52
; SI-NEXT: s_lshr_b32 vcc_lo, s47, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 59
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 51
; SI-NEXT: s_lshr_b32 vcc_lo, s45, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 58
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 50
; SI-NEXT: s_lshr_b32 vcc_lo, s43, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 57
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 49
; SI-NEXT: s_lshr_b32 vcc_lo, s41, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 56
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 48
; SI-NEXT: s_lshr_b32 vcc_lo, s15, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 55
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 47
; SI-NEXT: s_lshr_b32 vcc_lo, s13, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 54
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 46
; SI-NEXT: s_lshr_b32 vcc_lo, s11, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 53
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 45
; SI-NEXT: s_lshr_b32 vcc_lo, s9, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 52
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 44
; SI-NEXT: s_lshr_b32 vcc_lo, s7, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 51
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 43
; SI-NEXT: s_lshr_b32 vcc_lo, s5, 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 50
+; SI-NEXT: s_mov_b32 s16, vcc_hi
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 42
; SI-NEXT: s_lshr_b64 vcc, s[74:75], 24
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 17
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 18
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 6
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 7
; SI-NEXT: s_lshr_b64 vcc, s[74:75], 16
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 15
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 16
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 4
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 5
; SI-NEXT: s_lshr_b64 vcc, s[74:75], 8
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 13
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 14
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 2
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 3
; SI-NEXT: s_lshr_b64 vcc, s[72:73], 24
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 23
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 24
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 12
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 13
; SI-NEXT: s_lshr_b64 vcc, s[72:73], 16
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 21
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 22
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 10
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 11
; SI-NEXT: s_lshr_b64 vcc, s[72:73], 8
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 19
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 20
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 8
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 9
; SI-NEXT: s_lshr_b64 vcc, s[62:63], 24
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 29
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 30
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 18
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 19
; SI-NEXT: s_lshr_b64 vcc, s[62:63], 16
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 27
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 28
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 16
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 17
; SI-NEXT: s_lshr_b64 vcc, s[62:63], 8
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 25
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 26
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 14
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 15
; SI-NEXT: s_lshr_b64 vcc, s[58:59], 24
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 35
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 36
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 24
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 25
; SI-NEXT: s_lshr_b64 vcc, s[58:59], 16
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 33
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 34
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 22
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 23
; SI-NEXT: s_lshr_b64 vcc, s[58:59], 8
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 31
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 32
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 20
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 21
; SI-NEXT: s_lshr_b64 vcc, s[56:57], 24
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 41
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 42
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 30
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 31
; SI-NEXT: s_lshr_b64 vcc, s[56:57], 16
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 39
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 40
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 28
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 29
; SI-NEXT: s_lshr_b64 vcc, s[56:57], 8
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 37
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 38
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 26
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 27
; SI-NEXT: s_lshr_b64 vcc, s[60:61], 24
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 47
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 48
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 36
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 37
; SI-NEXT: s_lshr_b64 vcc, s[60:61], 16
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 45
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 46
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 34
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 35
; SI-NEXT: s_lshr_b64 vcc, s[60:61], 8
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 43
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 44
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 32
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 33
; SI-NEXT: s_lshr_b64 vcc, s[46:47], 24
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 53
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 54
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 42
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 43
; SI-NEXT: s_lshr_b64 vcc, s[46:47], 16
-; SI-NEXT: s_bfe_u32 s16, s76, 0x80008
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 51
-; SI-NEXT: v_writelane_b32 v36, s16, 49
-; SI-NEXT: s_bfe_u32 s16, s77, 0x80008
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 52
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 40
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 41
; SI-NEXT: s_lshr_b64 vcc, s[46:47], 8
-; SI-NEXT: v_writelane_b32 v36, s16, 48
-; SI-NEXT: s_bfe_u32 s16, s78, 0x80008
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 49
-; SI-NEXT: v_writelane_b32 v36, s16, 47
-; SI-NEXT: s_bfe_u32 s16, s79, 0x80008
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 50
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 38
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 39
; SI-NEXT: s_lshr_b64 vcc, s[44:45], 24
-; SI-NEXT: v_writelane_b32 v36, s16, 46
-; SI-NEXT: s_bfe_u32 s16, s88, 0x80008
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 59
-; SI-NEXT: v_writelane_b32 v36, s16, 45
-; SI-NEXT: s_bfe_u32 s16, s89, 0x80008
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 60
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 48
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 49
; SI-NEXT: s_lshr_b64 vcc, s[44:45], 16
-; SI-NEXT: v_writelane_b32 v36, s16, 44
-; SI-NEXT: s_bfe_u32 s16, s90, 0x80008
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 57
-; SI-NEXT: v_writelane_b32 v36, s16, 43
-; SI-NEXT: s_bfe_u32 s16, s92, 0x80008
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 58
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 46
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 47
; SI-NEXT: s_lshr_b64 vcc, s[44:45], 8
-; SI-NEXT: v_writelane_b32 v36, s16, 42
-; SI-NEXT: s_bfe_u32 s16, s94, 0x80008
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 55
-; SI-NEXT: v_writelane_b32 v36, s16, 41
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 56
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 44
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 45
; SI-NEXT: s_lshr_b64 vcc, s[42:43], 24
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 1
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 2
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 54
+; SI-NEXT: s_mov_b32 s82, s76
+; SI-NEXT: s_bfe_u32 s76, s99, 0x80008
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 55
; SI-NEXT: s_lshr_b64 vcc, s[42:43], 16
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 63
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 0
+; SI-NEXT: v_writelane_b32 v36, s76, 41
+; SI-NEXT: s_bfe_u32 s76, s80, 0x80008
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 52
+; SI-NEXT: v_writelane_b32 v36, s76, 40
+; SI-NEXT: s_bfe_u32 s76, s78, 0x80008
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 53
; SI-NEXT: s_lshr_b64 vcc, s[42:43], 8
-; SI-NEXT: v_writelane_b32 v37, vcc_lo, 61
-; SI-NEXT: v_writelane_b32 v37, vcc_hi, 62
+; SI-NEXT: v_writelane_b32 v36, s76, 39
+; SI-NEXT: s_bfe_u32 s76, s79, 0x80008
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 50
+; SI-NEXT: v_writelane_b32 v36, s76, 38
+; SI-NEXT: s_bfe_u32 s76, s88, 0x80008
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 51
; SI-NEXT: s_lshr_b64 vcc, s[40:41], 24
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 7
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 8
+; SI-NEXT: v_writelane_b32 v36, s76, 37
+; SI-NEXT: s_bfe_u32 s76, s89, 0x80008
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 60
+; SI-NEXT: v_writelane_b32 v36, s76, 36
+; SI-NEXT: s_bfe_u32 s76, s90, 0x80008
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 61
; SI-NEXT: s_lshr_b64 vcc, s[40:41], 16
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 5
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 6
+; SI-NEXT: v_writelane_b32 v36, s76, 35
+; SI-NEXT: s_bfe_u32 s76, s92, 0x80008
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 58
+; SI-NEXT: v_writelane_b32 v36, s76, 34
+; SI-NEXT: s_bfe_u32 s76, s95, 0x80008
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 59
; SI-NEXT: s_lshr_b64 vcc, s[40:41], 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 3
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 4
+; SI-NEXT: v_writelane_b32 v36, s76, 33
+; SI-NEXT: s_bfe_u32 s76, s35, 0x80008
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 56
+; SI-NEXT: v_writelane_b32 v36, s76, 32
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 57
; SI-NEXT: s_lshr_b64 vcc, s[14:15], 24
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 13
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 14
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 2
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 3
; SI-NEXT: s_lshr_b64 vcc, s[14:15], 16
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 11
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 12
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 0
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 1
; SI-NEXT: s_lshr_b64 vcc, s[14:15], 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 9
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 10
+; SI-NEXT: v_writelane_b32 v35, vcc_lo, 62
+; SI-NEXT: v_writelane_b32 v35, vcc_hi, 63
; SI-NEXT: s_lshr_b64 vcc, s[12:13], 24
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 19
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 20
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 8
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 9
; SI-NEXT: s_lshr_b64 vcc, s[12:13], 16
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 17
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 18
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 6
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 7
; SI-NEXT: s_lshr_b64 vcc, s[12:13], 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 15
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 16
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 4
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 5
; SI-NEXT: s_lshr_b64 vcc, s[10:11], 24
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 25
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 26
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 14
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 15
; SI-NEXT: s_lshr_b64 vcc, s[10:11], 16
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 23
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 24
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 12
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 13
; SI-NEXT: s_lshr_b64 vcc, s[10:11], 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 21
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 22
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 10
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 11
; SI-NEXT: s_lshr_b64 vcc, s[8:9], 24
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 31
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 32
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 20
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 21
; SI-NEXT: s_lshr_b64 vcc, s[8:9], 16
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 29
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 30
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 18
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 19
; SI-NEXT: s_lshr_b64 vcc, s[8:9], 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 27
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 28
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 16
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 17
; SI-NEXT: s_lshr_b64 vcc, s[6:7], 24
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 37
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 38
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 26
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 27
; SI-NEXT: s_lshr_b64 vcc, s[6:7], 16
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 35
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 36
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 24
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 25
; SI-NEXT: s_lshr_b64 vcc, s[6:7], 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 33
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 34
-; SI-NEXT: s_mov_b32 vcc_lo, s99
-; SI-NEXT: s_lshr_b64 s[98:99], s[4:5], 24
-; SI-NEXT: s_mov_b32 s99, s17
-; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 16
-; SI-NEXT: s_mov_b32 s17, s99
-; SI-NEXT: s_mov_b32 s99, vcc_lo
-; SI-NEXT: s_lshr_b64 vcc, s[4:5], 8
-; SI-NEXT: v_writelane_b32 v36, vcc_lo, 39
-; SI-NEXT: s_bfe_u32 s97, s36, 0x80008
-; SI-NEXT: s_bfe_u32 s85, s48, 0x80008
-; SI-NEXT: s_bfe_u32 s38, s30, 0x80008
-; SI-NEXT: s_bfe_u32 s86, s55, 0x80008
-; SI-NEXT: s_bfe_u32 s87, s67, 0x80008
-; SI-NEXT: s_bfe_u32 s50, s71, 0x80008
-; SI-NEXT: s_bfe_u32 s96, s82, 0x80008
-; SI-NEXT: v_writelane_b32 v36, vcc_hi, 40
+; SI-NEXT: v_writelane_b32 v36, vcc_lo, 22
+; SI-NEXT: v_writelane_b32 v36, vcc_hi, 23
+; SI-NEXT: s_lshr_b64 s[76:77], s[4:5], 24
+; SI-NEXT: v_writelane_b32 v36, s76, 30
+; SI-NEXT: v_writelane_b32 v36, s77, 31
+; SI-NEXT: s_lshr_b64 s[76:77], s[4:5], 8
+; SI-NEXT: s_mov_b32 s84, s70
+; SI-NEXT: s_mov_b32 vcc_lo, s71
+; SI-NEXT: s_lshr_b64 s[70:71], s[4:5], 16
+; SI-NEXT: v_writelane_b32 v36, s76, 28
+; SI-NEXT: s_bfe_u32 s85, s38, 0x80008
+; SI-NEXT: s_bfe_u32 s86, s49, 0x80008
+; SI-NEXT: s_bfe_u32 s87, s30, 0x80008
+; SI-NEXT: s_bfe_u32 s96, s54, 0x80008
+; SI-NEXT: s_bfe_u32 s97, s65, 0x80008
+; SI-NEXT: s_bfe_u32 s98, s68, 0x80008
+; SI-NEXT: s_mov_b32 s71, vcc_lo
+; SI-NEXT: v_writelane_b32 v36, s77, 29
; SI-NEXT: s_cbranch_execnz .LBB95_4
; SI-NEXT: .LBB95_2: ; %cmp.true
-; SI-NEXT: v_cvt_f32_f16_e32 v2, s83
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s84
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s82
-; SI-NEXT: v_readlane_b32 s12, v37, 12
+; SI-NEXT: v_cvt_f32_f16_e32 v2, s69
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s82
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s68
+; SI-NEXT: s_lshr_b32 s10, s52, 16
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v4, v1
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v3
; SI-NEXT: v_readfirstlane_b32 s5, v2
-; SI-NEXT: v_cvt_f32_f16_e32 v2, s81
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s80
+; SI-NEXT: v_cvt_f32_f16_e32 v2, s67
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s84
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_readfirstlane_b32 s4, v4
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
@@ -180777,20 +180937,20 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: v_readfirstlane_b32 s6, v2
-; SI-NEXT: v_cvt_f32_f16_e32 v2, s34
+; SI-NEXT: v_cvt_f32_f16_e32 v2, s66
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: v_readfirstlane_b32 s5, v1
; SI-NEXT: s_lshl_b32 s5, s5, 16
; SI-NEXT: s_or_b32 s5, s6, s5
; SI-NEXT: v_readfirstlane_b32 s6, v3
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s71
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s65
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v2
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v3
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s70
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s64
; SI-NEXT: v_readfirstlane_b32 s7, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v4, s69
+; SI-NEXT: v_cvt_f32_f16_e32 v4, s16
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
@@ -180800,17 +180960,17 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s7, v2
; SI-NEXT: s_lshl_b32 s7, s7, 16
; SI-NEXT: v_readfirstlane_b32 s8, v3
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s68
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s55
; SI-NEXT: s_or_b32 s7, s8, s7
; SI-NEXT: v_readfirstlane_b32 s8, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v4, s67
+; SI-NEXT: v_cvt_f32_f16_e32 v4, s54
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v5, v3
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v4, s66
+; SI-NEXT: v_cvt_f32_f16_e32 v4, s53
; SI-NEXT: v_readfirstlane_b32 s9, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s65
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s10
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
@@ -180818,17 +180978,17 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: v_readfirstlane_b32 s10, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v4, s64
+; SI-NEXT: v_cvt_f32_f16_e32 v4, s52
; SI-NEXT: v_readfirstlane_b32 s9, v3
; SI-NEXT: s_lshl_b32 s9, s9, 16
; SI-NEXT: s_or_b32 s9, s10, s9
; SI-NEXT: v_readfirstlane_b32 s10, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s55
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s30
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v6, v4
-; SI-NEXT: s_lshl_b32 s10, s10, 16
+; SI-NEXT: s_lshr_b32 s12, s50, 16
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s54
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s51
; SI-NEXT: v_readfirstlane_b32 s11, v6
; SI-NEXT: v_cvt_f32_f16_e32 v6, s12
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
@@ -180836,19 +180996,20 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_or_b32 s10, s11, s10
; SI-NEXT: v_readfirstlane_b32 s11, v4
; SI-NEXT: s_lshl_b32 s11, s11, 16
; SI-NEXT: v_readfirstlane_b32 s12, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s52
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s50
; SI-NEXT: s_or_b32 s11, s12, s11
; SI-NEXT: v_readfirstlane_b32 s12, v6
-; SI-NEXT: v_cvt_f32_f16_e32 v6, s30
+; SI-NEXT: v_cvt_f32_f16_e32 v6, s49
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v7, v5
-; SI-NEXT: v_readlane_b32 s14, v37, 11
+; SI-NEXT: s_lshr_b32 s14, s39, 16
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v6
-; SI-NEXT: v_cvt_f32_f16_e32 v6, s51
+; SI-NEXT: v_cvt_f32_f16_e32 v6, s48
; SI-NEXT: v_readfirstlane_b32 s13, v7
; SI-NEXT: v_cvt_f32_f16_e32 v7, s14
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
@@ -180858,62 +181019,60 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: v_readfirstlane_b32 s14, v6
-; SI-NEXT: v_cvt_f32_f16_e32 v6, s49
+; SI-NEXT: v_cvt_f32_f16_e32 v6, s39
; SI-NEXT: s_or_b32 s12, s13, s12
; SI-NEXT: v_readfirstlane_b32 s13, v5
; SI-NEXT: s_lshl_b32 s13, s13, 16
; SI-NEXT: s_or_b32 s13, s14, s13
; SI-NEXT: v_readfirstlane_b32 s14, v7
-; SI-NEXT: v_cvt_f32_f16_e32 v7, s48
+; SI-NEXT: v_cvt_f32_f16_e32 v7, s38
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v8, v6
-; SI-NEXT: v_readlane_b32 s16, v37, 10
+; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v7
-; SI-NEXT: v_cvt_f32_f16_e32 v7, s39
+; SI-NEXT: v_cvt_f32_f16_e32 v7, s37
; SI-NEXT: v_readfirstlane_b32 s15, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s16
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s83
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
-; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_or_b32 s14, s15, s14
; SI-NEXT: v_readfirstlane_b32 s15, v6
; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: v_readfirstlane_b32 s40, v7
-; SI-NEXT: v_cvt_f32_f16_e32 v7, s37
+; SI-NEXT: v_cvt_f32_f16_e32 v7, s36
; SI-NEXT: s_or_b32 s15, s40, s15
; SI-NEXT: v_readfirstlane_b32 s40, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s36
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s35
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v9, v7
-; SI-NEXT: v_readlane_b32 s16, v37, 9
+; SI-NEXT: s_lshl_b32 s40, s40, 16
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s35
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s34
; SI-NEXT: v_readfirstlane_b32 s41, v9
-; SI-NEXT: v_cvt_f32_f16_e32 v9, s16
+; SI-NEXT: v_cvt_f32_f16_e32 v9, s81
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
-; SI-NEXT: s_lshl_b32 s40, s40, 16
+; SI-NEXT: s_or_b32 s40, s41, s40
; SI-NEXT: v_readfirstlane_b32 s42, v8
; SI-NEXT: v_cvt_f32_f16_e32 v8, s31
-; SI-NEXT: s_or_b32 s40, s41, s40
; SI-NEXT: v_readfirstlane_b32 s41, v7
; SI-NEXT: s_lshl_b32 s41, s41, 16
; SI-NEXT: s_or_b32 s41, s42, s41
; SI-NEXT: v_readfirstlane_b32 s42, v9
-; SI-NEXT: v_cvt_f32_f16_e32 v9, s94
+; SI-NEXT: v_cvt_f32_f16_e32 v9, s95
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v10, v8
; SI-NEXT: s_lshl_b32 s42, s42, 16
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v9
-; SI-NEXT: v_cvt_f32_f16_e32 v9, s95
+; SI-NEXT: v_cvt_f32_f16_e32 v9, s94
; SI-NEXT: v_readfirstlane_b32 s43, v10
-; SI-NEXT: v_cvt_f32_f16_e32 v10, s99
+; SI-NEXT: v_cvt_f32_f16_e32 v10, s71
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
@@ -180929,7 +181088,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v10, s92
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v11, v9
-; SI-NEXT: v_readlane_b32 s46, v37, 8
+; SI-NEXT: s_lshr_b32 s46, s28, 16
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v10
; SI-NEXT: v_cvt_f32_f16_e32 v10, s91
; SI-NEXT: v_readfirstlane_b32 s45, v11
@@ -180951,7 +181110,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_lshl_b32 s45, s45, 16
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v11
; SI-NEXT: v_cvt_f32_f16_e32 v11, s29
-; SI-NEXT: v_readlane_b32 s29, v37, 7
+; SI-NEXT: s_lshr_b32 s29, s26, 16
; SI-NEXT: s_or_b32 s45, s46, s45
; SI-NEXT: v_readfirstlane_b32 s46, v12
; SI-NEXT: v_cvt_f32_f16_e32 v12, s29
@@ -180972,7 +181131,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v12, s27
; SI-NEXT: v_readfirstlane_b32 s28, v10
; SI-NEXT: s_lshl_b32 s28, s28, 16
-; SI-NEXT: v_readlane_b32 s27, v37, 6
+; SI-NEXT: s_lshr_b32 s27, s24, 16
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: s_or_b32 s47, s29, s28
@@ -180992,7 +181151,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v12, s25
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
-; SI-NEXT: v_readlane_b32 s25, v37, 5
+; SI-NEXT: s_lshr_b32 s25, s22, 16
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_readfirstlane_b32 s24, v13
@@ -181015,7 +181174,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v12, s23
; SI-NEXT: v_readfirstlane_b32 s22, v14
; SI-NEXT: v_cvt_f32_f16_e32 v14, s79
-; SI-NEXT: v_readlane_b32 s23, v37, 4
+; SI-NEXT: s_lshr_b32 s23, s20, 16
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
@@ -181036,110 +181195,110 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f32_f16_e32 v14, s78
; SI-NEXT: v_readfirstlane_b32 s22, v12
; SI-NEXT: v_cvt_f32_f16_e32 v12, s21
-; SI-NEXT: v_readlane_b32 s21, v37, 2
+; SI-NEXT: s_lshr_b32 s21, s18, 16
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v20, v14
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f32_f16_e32 v14, s21
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: s_lshr_b64 s[64:65], s[14:15], 24
-; SI-NEXT: v_writelane_b32 v36, s64, 13
+; SI-NEXT: v_writelane_b32 v36, s64, 2
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_readfirstlane_b32 s21, v12
; SI-NEXT: v_cvt_f32_f16_e32 v12, s18
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
-; SI-NEXT: v_writelane_b32 v36, s65, 14
-; SI-NEXT: s_lshr_b64 s[64:65], s[12:13], 24
+; SI-NEXT: v_writelane_b32 v36, s65, 3
+; SI-NEXT: s_lshr_b64 s[84:85], s[12:13], 24
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_readfirstlane_b32 s18, v14
-; SI-NEXT: v_cvt_f32_f16_e32 v14, s77
+; SI-NEXT: v_cvt_f32_f16_e32 v14, s80
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_writelane_b32 v36, s84, 8
; SI-NEXT: s_lshl_b32 s20, s20, 16
-; SI-NEXT: v_writelane_b32 v36, s64, 19
+; SI-NEXT: v_writelane_b32 v36, s85, 9
+; SI-NEXT: s_lshr_b64 s[84:85], s[12:13], 16
; SI-NEXT: s_or_b32 s62, s22, s20
; SI-NEXT: v_readfirstlane_b32 s20, v20
-; SI-NEXT: v_writelane_b32 v36, s65, 20
-; SI-NEXT: s_lshr_b64 s[64:65], s[12:13], 16
+; SI-NEXT: v_writelane_b32 v36, s84, 6
; SI-NEXT: s_lshl_b32 s20, s20, 16
-; SI-NEXT: v_writelane_b32 v36, s64, 17
+; SI-NEXT: v_readlane_b32 s16, v35, 0
+; SI-NEXT: v_writelane_b32 v36, s85, 7
+; SI-NEXT: s_lshr_b64 s[84:85], s[12:13], 8
; SI-NEXT: s_or_b32 s63, s21, s20
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_readfirstlane_b32 s20, v12
; SI-NEXT: v_cvt_f32_f16_e32 v12, s19
-; SI-NEXT: v_readlane_b32 s19, v37, 0
-; SI-NEXT: v_writelane_b32 v36, s65, 18
-; SI-NEXT: s_lshr_b64 s[64:65], s[12:13], 8
+; SI-NEXT: s_lshr_b32 s19, s16, 16
+; SI-NEXT: v_writelane_b32 v36, s84, 4
; SI-NEXT: v_cvt_f16_f32_e32 v23, v14
; SI-NEXT: v_cvt_f32_f16_e32 v14, s19
-; SI-NEXT: v_writelane_b32 v36, s64, 15
-; SI-NEXT: v_writelane_b32 v36, s65, 16
+; SI-NEXT: v_writelane_b32 v36, s85, 5
; SI-NEXT: s_lshr_b64 s[84:85], s[10:11], 16
-; SI-NEXT: v_writelane_b32 v36, s84, 23
-; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
-; SI-NEXT: v_writelane_b32 v36, s85, 24
+; SI-NEXT: v_writelane_b32 v36, s84, 12
+; SI-NEXT: v_writelane_b32 v36, s85, 13
; SI-NEXT: s_lshr_b64 s[84:85], s[10:11], 8
+; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
+; SI-NEXT: v_writelane_b32 v36, s84, 10
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
-; SI-NEXT: v_cvt_f32_f16_e32 v15, s53
-; SI-NEXT: v_writelane_b32 v36, s84, 21
-; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
-; SI-NEXT: v_writelane_b32 v36, s85, 22
+; SI-NEXT: v_cvt_f32_f16_e32 v15, s16
+; SI-NEXT: v_writelane_b32 v36, s85, 11
; SI-NEXT: s_lshr_b64 s[84:85], s[8:9], 24
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_writelane_b32 v36, s84, 20
; SI-NEXT: s_lshl_b32 s18, s18, 16
-; SI-NEXT: v_writelane_b32 v36, s84, 31
+; SI-NEXT: v_writelane_b32 v36, s85, 21
+; SI-NEXT: s_lshr_b64 s[84:85], s[8:9], 16
; SI-NEXT: s_or_b32 s72, s20, s18
; SI-NEXT: v_readfirstlane_b32 s18, v23
-; SI-NEXT: v_writelane_b32 v36, s85, 32
-; SI-NEXT: s_lshr_b64 s[84:85], s[8:9], 16
+; SI-NEXT: v_writelane_b32 v36, s84, 18
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: v_readfirstlane_b32 s16, v12
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v15
-; SI-NEXT: v_writelane_b32 v36, s84, 29
+; SI-NEXT: v_writelane_b32 v36, s85, 19
+; SI-NEXT: s_lshr_b64 s[84:85], s[8:9], 8
; SI-NEXT: s_or_b32 s73, s16, s18
; SI-NEXT: v_readfirstlane_b32 s16, v14
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
-; SI-NEXT: v_cvt_f32_f16_e32 v14, s76
-; SI-NEXT: v_writelane_b32 v36, s85, 30
-; SI-NEXT: s_lshr_b64 s[84:85], s[8:9], 8
+; SI-NEXT: v_cvt_f32_f16_e32 v14, s99
+; SI-NEXT: v_writelane_b32 v36, s84, 16
; SI-NEXT: v_cvt_f32_f16_e32 v15, s17
-; SI-NEXT: v_writelane_b32 v36, s84, 27
-; SI-NEXT: s_lshr_b64 s[20:21], s[46:47], 24
-; SI-NEXT: v_writelane_b32 v36, s85, 28
+; SI-NEXT: v_writelane_b32 v36, s85, 17
; SI-NEXT: s_lshr_b64 s[84:85], s[6:7], 24
-; SI-NEXT: v_writelane_b32 v37, s20, 53
-; SI-NEXT: v_writelane_b32 v36, s84, 37
+; SI-NEXT: v_writelane_b32 v36, s84, 26
+; SI-NEXT: s_lshr_b64 s[20:21], s[46:47], 24
+; SI-NEXT: v_writelane_b32 v36, s85, 27
+; SI-NEXT: s_lshr_b64 s[84:85], s[6:7], 16
; SI-NEXT: v_readfirstlane_b32 s17, v12
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v14
-; SI-NEXT: v_writelane_b32 v37, s21, 54
-; SI-NEXT: s_lshr_b64 s[20:21], s[46:47], 16
-; SI-NEXT: v_writelane_b32 v36, s85, 38
-; SI-NEXT: s_lshr_b64 s[84:85], s[6:7], 16
+; SI-NEXT: v_writelane_b32 v35, s20, 42
+; SI-NEXT: v_writelane_b32 v36, s84, 24
; SI-NEXT: v_cvt_f16_f32_e32 v26, v12
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v15
-; SI-NEXT: v_writelane_b32 v37, s20, 51
-; SI-NEXT: v_writelane_b32 v36, s84, 35
+; SI-NEXT: v_writelane_b32 v35, s21, 43
+; SI-NEXT: s_lshr_b64 s[20:21], s[46:47], 16
+; SI-NEXT: v_writelane_b32 v36, s85, 25
+; SI-NEXT: s_lshr_b64 s[84:85], s[6:7], 8
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
-; SI-NEXT: v_writelane_b32 v37, s21, 52
+; SI-NEXT: v_writelane_b32 v35, s20, 40
+; SI-NEXT: v_writelane_b32 v36, s84, 22
+; SI-NEXT: v_writelane_b32 v35, s21, 41
; SI-NEXT: s_lshr_b64 s[20:21], s[46:47], 8
-; SI-NEXT: v_writelane_b32 v36, s85, 36
-; SI-NEXT: s_lshr_b64 s[84:85], s[6:7], 8
-; SI-NEXT: v_writelane_b32 v37, s20, 49
-; SI-NEXT: v_writelane_b32 v36, s84, 33
-; SI-NEXT: s_lshl_b32 s16, s16, 16
-; SI-NEXT: v_writelane_b32 v37, s21, 50
-; SI-NEXT: v_writelane_b32 v36, s85, 34
+; SI-NEXT: v_writelane_b32 v36, s85, 23
; SI-NEXT: s_lshr_b64 s[84:85], s[4:5], 24
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: v_writelane_b32 v35, s20, 38
+; SI-NEXT: v_writelane_b32 v36, s84, 30
; SI-NEXT: s_or_b32 s74, s17, s16
; SI-NEXT: v_readfirstlane_b32 s16, v26
-; SI-NEXT: v_writelane_b32 v37, s84, 0
+; SI-NEXT: v_writelane_b32 v35, s21, 39
+; SI-NEXT: v_writelane_b32 v36, s85, 31
+; SI-NEXT: s_lshr_b64 s[84:85], s[4:5], 16
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: v_readfirstlane_b32 s17, v12
-; SI-NEXT: v_writelane_b32 v37, s85, 1
-; SI-NEXT: s_lshr_b64 s[84:85], s[4:5], 16
+; SI-NEXT: v_writelane_b32 v35, s84, 0
; SI-NEXT: s_or_b32 s75, s17, s16
-; SI-NEXT: v_writelane_b32 v37, s84, 2
-; SI-NEXT: s_lshr_b64 s[16:17], s[74:75], 8
-; SI-NEXT: v_writelane_b32 v37, s85, 3
+; SI-NEXT: v_writelane_b32 v35, s85, 1
; SI-NEXT: s_lshr_b64 s[84:85], s[4:5], 8
; SI-NEXT: s_lshr_b64 s[18:19], s[74:75], 24
; SI-NEXT: s_lshr_b64 s[38:39], s[72:73], 16
@@ -181153,13 +181312,9 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_lshr_b64 s[34:35], s[60:61], 24
; SI-NEXT: s_lshr_b64 s[50:51], s[60:61], 16
; SI-NEXT: s_lshr_b64 s[22:23], s[60:61], 8
-; SI-NEXT: s_lshr_b32 s20, s45, 8
-; SI-NEXT: s_lshr_b32 s17, s15, 8
-; SI-NEXT: s_lshr_b64 s[26:27], s[40:41], 24
-; SI-NEXT: s_lshr_b64 s[82:83], s[14:15], 16
-; SI-NEXT: s_lshr_b64 s[64:65], s[10:11], 24
-; SI-NEXT: v_writelane_b32 v36, s84, 39
+; SI-NEXT: v_writelane_b32 v36, s84, 28
; SI-NEXT: s_lshr_b64 s[54:55], s[74:75], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[74:75], 8
; SI-NEXT: s_lshr_b64 vcc, s[72:73], 24
; SI-NEXT: s_lshr_b64 s[70:71], s[56:57], 24
; SI-NEXT: s_lshr_b64 s[86:87], s[56:57], 16
@@ -181171,8 +181326,10 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_lshr_b32 s77, s57, 8
; SI-NEXT: s_lshr_b32 s29, s61, 8
; SI-NEXT: s_lshr_b32 s28, s47, 8
-; SI-NEXT: s_lshr_b32 s19, s43, 8
+; SI-NEXT: s_lshr_b32 s27, s45, 8
+; SI-NEXT: s_lshr_b32 s26, s43, 8
; SI-NEXT: s_lshr_b32 s53, s41, 8
+; SI-NEXT: s_lshr_b32 s19, s15, 8
; SI-NEXT: s_lshr_b32 s51, s13, 8
; SI-NEXT: s_lshr_b32 s39, s11, 8
; SI-NEXT: s_lshr_b32 s37, s9, 8
@@ -181200,34 +181357,48 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_lshr_b64 s[92:93], s[42:43], 24
; SI-NEXT: s_lshr_b64 s[24:25], s[42:43], 16
; SI-NEXT: s_lshr_b64 s[30:31], s[42:43], 8
-; SI-NEXT: s_mov_b32 s27, s20
+; SI-NEXT: s_lshr_b64 s[82:83], s[40:41], 24
; SI-NEXT: s_lshr_b64 s[96:97], s[40:41], 16
; SI-NEXT: s_lshr_b64 s[20:21], s[40:41], 8
+; SI-NEXT: s_lshr_b64 s[64:65], s[14:15], 16
; SI-NEXT: s_lshr_b64 s[66:67], s[14:15], 8
-; SI-NEXT: v_writelane_b32 v36, s85, 40
-; SI-NEXT: s_mov_b32 s84, s64
-; SI-NEXT: s_mov_b32 s64, s82
-; SI-NEXT: s_mov_b32 s82, s26
-; SI-NEXT: s_mov_b32 s26, s17
+; SI-NEXT: v_writelane_b32 v36, s85, 29
+; SI-NEXT: s_lshr_b64 s[84:85], s[10:11], 24
; SI-NEXT: s_branch .LBB95_5
; SI-NEXT: .LBB95_3:
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; implicit-def: $sgpr16
-; SI-NEXT: v_writelane_b32 v37, s4, 13
-; SI-NEXT: v_writelane_b32 v37, s5, 14
+; SI-NEXT: s_mov_b32 s84, s70
+; SI-NEXT: v_writelane_b32 v35, s4, 2
+; SI-NEXT: v_writelane_b32 v35, s5, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr70
+; SI-NEXT: s_mov_b32 s82, s76
+; SI-NEXT: v_writelane_b32 v35, s4, 4
+; SI-NEXT: v_writelane_b32 v35, s5, 5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr76
+; SI-NEXT: s_mov_b32 s16, vcc_hi
+; SI-NEXT: v_writelane_b32 v35, s4, 6
+; SI-NEXT: v_writelane_b32 v35, s5, 7
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; kill: killed $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; kill: killed $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v35, s4, 8
+; SI-NEXT: v_writelane_b32 v35, s5, 9
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr56
-; SI-NEXT: ; implicit-def: $sgpr97
; SI-NEXT: ; implicit-def: $sgpr85
-; SI-NEXT: ; implicit-def: $sgpr38
; SI-NEXT: ; implicit-def: $sgpr86
; SI-NEXT: ; implicit-def: $sgpr87
-; SI-NEXT: ; implicit-def: $sgpr50
; SI-NEXT: ; implicit-def: $sgpr96
+; SI-NEXT: ; implicit-def: $sgpr97
+; SI-NEXT: ; implicit-def: $sgpr98
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr44
@@ -181238,52 +181409,42 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: ; implicit-def: $sgpr10
; SI-NEXT: ; implicit-def: $sgpr8
; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr98
-; SI-NEXT: v_writelane_b32 v37, s4, 15
-; SI-NEXT: v_writelane_b32 v37, s5, 16
+; SI-NEXT: v_writelane_b32 v35, s4, 10
+; SI-NEXT: v_writelane_b32 v35, s5, 11
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 17
-; SI-NEXT: v_writelane_b32 v37, s5, 18
+; SI-NEXT: v_writelane_b32 v35, s4, 12
+; SI-NEXT: v_writelane_b32 v35, s5, 13
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 19
-; SI-NEXT: v_writelane_b32 v37, s5, 20
+; SI-NEXT: v_writelane_b32 v35, s4, 14
+; SI-NEXT: v_writelane_b32 v35, s5, 15
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 21
-; SI-NEXT: v_writelane_b32 v37, s5, 22
+; SI-NEXT: v_writelane_b32 v35, s4, 16
+; SI-NEXT: v_writelane_b32 v35, s5, 17
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 23
-; SI-NEXT: v_writelane_b32 v37, s5, 24
+; SI-NEXT: v_writelane_b32 v35, s4, 18
+; SI-NEXT: v_writelane_b32 v35, s5, 19
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 25
-; SI-NEXT: v_writelane_b32 v37, s5, 26
+; SI-NEXT: v_writelane_b32 v35, s4, 20
+; SI-NEXT: v_writelane_b32 v35, s5, 21
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 27
-; SI-NEXT: v_writelane_b32 v37, s5, 28
+; SI-NEXT: v_writelane_b32 v35, s4, 22
+; SI-NEXT: v_writelane_b32 v35, s5, 23
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 29
-; SI-NEXT: v_writelane_b32 v37, s5, 30
+; SI-NEXT: v_writelane_b32 v35, s4, 24
+; SI-NEXT: v_writelane_b32 v35, s5, 25
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 31
-; SI-NEXT: v_writelane_b32 v37, s5, 32
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 33
-; SI-NEXT: v_writelane_b32 v37, s5, 34
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 35
-; SI-NEXT: v_writelane_b32 v37, s5, 36
-; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
@@ -181320,241 +181481,241 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; kill: killed $sgpr4
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; kill: killed $sgpr4
+; SI-NEXT: v_writelane_b32 v35, s4, 26
+; SI-NEXT: v_writelane_b32 v35, s5, 27
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 37
-; SI-NEXT: v_writelane_b32 v37, s5, 38
+; SI-NEXT: v_writelane_b32 v35, s4, 28
+; SI-NEXT: v_writelane_b32 v35, s5, 29
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 39
-; SI-NEXT: v_writelane_b32 v37, s5, 40
+; SI-NEXT: v_writelane_b32 v35, s4, 30
+; SI-NEXT: v_writelane_b32 v35, s5, 31
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 41
-; SI-NEXT: v_writelane_b32 v37, s5, 42
+; SI-NEXT: v_writelane_b32 v35, s4, 32
+; SI-NEXT: v_writelane_b32 v35, s5, 33
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 43
-; SI-NEXT: v_writelane_b32 v37, s5, 44
+; SI-NEXT: v_writelane_b32 v35, s4, 34
+; SI-NEXT: v_writelane_b32 v35, s5, 35
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 45
-; SI-NEXT: v_writelane_b32 v37, s5, 46
+; SI-NEXT: v_writelane_b32 v35, s4, 36
+; SI-NEXT: v_writelane_b32 v35, s5, 37
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 47
-; SI-NEXT: v_writelane_b32 v37, s5, 48
+; SI-NEXT: v_writelane_b32 v35, s4, 38
+; SI-NEXT: v_writelane_b32 v35, s5, 39
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 49
-; SI-NEXT: v_writelane_b32 v37, s5, 50
+; SI-NEXT: v_writelane_b32 v35, s4, 40
+; SI-NEXT: v_writelane_b32 v35, s5, 41
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 51
-; SI-NEXT: v_writelane_b32 v37, s5, 52
+; SI-NEXT: v_writelane_b32 v35, s4, 42
+; SI-NEXT: v_writelane_b32 v35, s5, 43
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 53
-; SI-NEXT: v_writelane_b32 v37, s5, 54
+; SI-NEXT: v_writelane_b32 v35, s4, 44
+; SI-NEXT: v_writelane_b32 v35, s5, 45
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 55
-; SI-NEXT: v_writelane_b32 v37, s5, 56
+; SI-NEXT: v_writelane_b32 v35, s4, 46
+; SI-NEXT: v_writelane_b32 v35, s5, 47
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 57
-; SI-NEXT: v_writelane_b32 v37, s5, 58
+; SI-NEXT: v_writelane_b32 v35, s4, 48
+; SI-NEXT: v_writelane_b32 v35, s5, 49
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 59
-; SI-NEXT: v_writelane_b32 v37, s5, 60
+; SI-NEXT: v_writelane_b32 v35, s4, 50
+; SI-NEXT: v_writelane_b32 v35, s5, 51
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 61
-; SI-NEXT: v_writelane_b32 v37, s5, 62
+; SI-NEXT: v_writelane_b32 v35, s4, 52
+; SI-NEXT: v_writelane_b32 v35, s5, 53
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v37, s4, 63
-; SI-NEXT: v_writelane_b32 v36, s5, 0
+; SI-NEXT: v_writelane_b32 v35, s4, 54
+; SI-NEXT: v_writelane_b32 v35, s5, 55
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 1
-; SI-NEXT: v_writelane_b32 v36, s5, 2
+; SI-NEXT: v_writelane_b32 v35, s4, 56
+; SI-NEXT: v_writelane_b32 v35, s5, 57
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 3
-; SI-NEXT: v_writelane_b32 v36, s5, 4
+; SI-NEXT: v_writelane_b32 v35, s4, 58
+; SI-NEXT: v_writelane_b32 v35, s5, 59
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 5
-; SI-NEXT: v_writelane_b32 v36, s5, 6
+; SI-NEXT: v_writelane_b32 v35, s4, 60
+; SI-NEXT: v_writelane_b32 v35, s5, 61
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 7
-; SI-NEXT: v_writelane_b32 v36, s5, 8
+; SI-NEXT: v_writelane_b32 v35, s4, 62
+; SI-NEXT: v_writelane_b32 v35, s5, 63
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 9
-; SI-NEXT: v_writelane_b32 v36, s5, 10
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 11
-; SI-NEXT: v_writelane_b32 v36, s5, 12
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_writelane_b32 v36, s4, 0
+; SI-NEXT: v_writelane_b32 v36, s5, 1
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 13
-; SI-NEXT: v_writelane_b32 v36, s5, 14
+; SI-NEXT: v_writelane_b32 v36, s4, 2
+; SI-NEXT: v_writelane_b32 v36, s5, 3
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 15
-; SI-NEXT: v_writelane_b32 v36, s5, 16
+; SI-NEXT: v_writelane_b32 v36, s4, 4
+; SI-NEXT: v_writelane_b32 v36, s5, 5
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 17
-; SI-NEXT: v_writelane_b32 v36, s5, 18
+; SI-NEXT: v_writelane_b32 v36, s4, 6
+; SI-NEXT: v_writelane_b32 v36, s5, 7
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 19
-; SI-NEXT: v_writelane_b32 v36, s5, 20
+; SI-NEXT: v_writelane_b32 v36, s4, 8
+; SI-NEXT: v_writelane_b32 v36, s5, 9
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 21
-; SI-NEXT: v_writelane_b32 v36, s5, 22
+; SI-NEXT: v_writelane_b32 v36, s4, 10
+; SI-NEXT: v_writelane_b32 v36, s5, 11
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 23
-; SI-NEXT: v_writelane_b32 v36, s5, 24
+; SI-NEXT: v_writelane_b32 v36, s4, 12
+; SI-NEXT: v_writelane_b32 v36, s5, 13
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 25
-; SI-NEXT: v_writelane_b32 v36, s5, 26
+; SI-NEXT: v_writelane_b32 v36, s4, 14
+; SI-NEXT: v_writelane_b32 v36, s5, 15
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 27
-; SI-NEXT: v_writelane_b32 v36, s5, 28
+; SI-NEXT: v_writelane_b32 v36, s4, 16
+; SI-NEXT: v_writelane_b32 v36, s5, 17
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 29
-; SI-NEXT: v_writelane_b32 v36, s5, 30
+; SI-NEXT: v_writelane_b32 v36, s4, 18
+; SI-NEXT: v_writelane_b32 v36, s5, 19
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 31
-; SI-NEXT: v_writelane_b32 v36, s5, 32
+; SI-NEXT: v_writelane_b32 v36, s4, 20
+; SI-NEXT: v_writelane_b32 v36, s5, 21
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 33
-; SI-NEXT: v_writelane_b32 v36, s5, 34
+; SI-NEXT: v_writelane_b32 v36, s4, 22
+; SI-NEXT: v_writelane_b32 v36, s5, 23
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 35
-; SI-NEXT: v_writelane_b32 v36, s5, 36
+; SI-NEXT: v_writelane_b32 v36, s4, 24
+; SI-NEXT: v_writelane_b32 v36, s5, 25
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s4, 37
-; SI-NEXT: v_writelane_b32 v36, s5, 38
-; SI-NEXT: v_writelane_b32 v36, s16, 39
+; SI-NEXT: v_writelane_b32 v36, s4, 26
+; SI-NEXT: v_writelane_b32 v36, s5, 27
+; SI-NEXT: v_writelane_b32 v36, s70, 28
+; SI-NEXT: v_writelane_b32 v36, s71, 29
+; SI-NEXT: v_writelane_b32 v36, s76, 30
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v36, s17, 40
-; SI-NEXT: ; implicit-def: $sgpr16
+; SI-NEXT: ; implicit-def: $sgpr70
+; SI-NEXT: v_writelane_b32 v36, s77, 31
; SI-NEXT: s_branch .LBB95_2
; SI-NEXT: .LBB95_4:
-; SI-NEXT: v_readlane_b32 s17, v36, 41
-; SI-NEXT: v_mov_b32_e32 v22, s17
-; SI-NEXT: v_readlane_b32 s17, v36, 42
-; SI-NEXT: v_mov_b32_e32 v24, s17
-; SI-NEXT: v_readlane_b32 s17, v36, 43
-; SI-NEXT: v_mov_b32_e32 v25, s17
-; SI-NEXT: v_readlane_b32 s17, v36, 44
-; SI-NEXT: v_mov_b32_e32 v27, s17
-; SI-NEXT: v_readlane_b32 s17, v36, 45
+; SI-NEXT: v_readlane_b32 s16, v36, 32
+; SI-NEXT: v_mov_b32_e32 v21, s16
+; SI-NEXT: v_readlane_b32 s16, v36, 33
+; SI-NEXT: v_mov_b32_e32 v22, s16
+; SI-NEXT: v_readlane_b32 s16, v36, 34
+; SI-NEXT: v_mov_b32_e32 v24, s16
+; SI-NEXT: v_readlane_b32 s16, v36, 35
+; SI-NEXT: v_mov_b32_e32 v25, s16
+; SI-NEXT: v_readlane_b32 s16, v36, 36
+; SI-NEXT: v_mov_b32_e32 v27, s16
+; SI-NEXT: v_readlane_b32 s16, v36, 37
+; SI-NEXT: v_mov_b32_e32 v8, s95
; SI-NEXT: v_mov_b32_e32 v10, s90
; SI-NEXT: v_mov_b32_e32 v11, s89
; SI-NEXT: v_mov_b32_e32 v13, s88
; SI-NEXT: v_mov_b32_e32 v16, s79
; SI-NEXT: v_mov_b32_e32 v20, s78
-; SI-NEXT: v_mov_b32_e32 v23, s77
-; SI-NEXT: v_mov_b32_e32 v26, s76
-; SI-NEXT: v_mov_b32_e32 v28, s17
-; SI-NEXT: v_readlane_b32 s17, v36, 46
-; SI-NEXT: v_readlane_b32 s76, v37, 35
-; SI-NEXT: v_readlane_b32 s78, v37, 33
-; SI-NEXT: v_readlane_b32 s88, v37, 29
-; SI-NEXT: v_readlane_b32 s90, v37, 31
-; SI-NEXT: v_mov_b32_e32 v29, s17
-; SI-NEXT: v_readlane_b32 s17, v36, 47
-; SI-NEXT: v_readlane_b32 s77, v37, 36
-; SI-NEXT: v_readlane_b32 s79, v37, 34
-; SI-NEXT: v_readlane_b32 s89, v37, 30
-; SI-NEXT: v_readlane_b32 s91, v37, 32
-; SI-NEXT: v_writelane_b32 v37, s98, 0
-; SI-NEXT: v_mov_b32_e32 v30, s17
-; SI-NEXT: v_readlane_b32 s17, v36, 48
-; SI-NEXT: v_writelane_b32 v37, s99, 1
-; SI-NEXT: v_mov_b32_e32 v8, s94
-; SI-NEXT: v_mov_b32_e32 v31, s17
-; SI-NEXT: v_readlane_b32 s17, v36, 49
-; SI-NEXT: v_readlane_b32 s94, v37, 27
-; SI-NEXT: v_mov_b32_e32 v32, s17
-; SI-NEXT: v_readlane_b32 s17, v36, 50
-; SI-NEXT: v_readlane_b32 s95, v37, 28
-; SI-NEXT: s_mov_b32 s95, s17
-; SI-NEXT: v_writelane_b32 v37, s16, 2
-; SI-NEXT: v_writelane_b32 v37, s17, 3
-; SI-NEXT: v_mov_b32_e32 v14, s50
-; SI-NEXT: v_readlane_b32 s34, v37, 47
-; SI-NEXT: v_readlane_b32 s50, v37, 45
-; SI-NEXT: v_mov_b32_e32 v7, s36
-; SI-NEXT: v_mov_b32_e32 v15, s87
-; SI-NEXT: v_mov_b32_e32 v17, s86
-; SI-NEXT: v_mov_b32_e32 v18, s38
-; SI-NEXT: v_readlane_b32 s22, v36, 51
-; SI-NEXT: v_readlane_b32 s23, v36, 54
-; SI-NEXT: v_readlane_b32 s36, v37, 25
-; SI-NEXT: v_readlane_b32 s38, v37, 21
-; SI-NEXT: v_readlane_b32 s16, v37, 17
-; SI-NEXT: v_readlane_b32 s52, v37, 19
-; SI-NEXT: v_readlane_b32 s86, v36, 25
-; SI-NEXT: v_readlane_b32 s35, v37, 48
-; SI-NEXT: v_readlane_b32 s51, v37, 46
-; SI-NEXT: v_readlane_b32 s18, v36, 52
-; SI-NEXT: v_readlane_b32 s20, v36, 53
-; SI-NEXT: v_readlane_b32 s21, v36, 56
-; SI-NEXT: v_readlane_b32 s37, v37, 26
-; SI-NEXT: v_readlane_b32 s39, v37, 22
-; SI-NEXT: v_readlane_b32 s17, v37, 18
-; SI-NEXT: v_readlane_b32 s53, v37, 20
-; SI-NEXT: v_readlane_b32 s87, v36, 26
+; SI-NEXT: v_mov_b32_e32 v28, s16
+; SI-NEXT: v_readlane_b32 s16, v36, 38
+; SI-NEXT: v_readlane_b32 s76, v35, 24
+; SI-NEXT: v_readlane_b32 s78, v35, 22
+; SI-NEXT: v_readlane_b32 s88, v35, 18
+; SI-NEXT: v_readlane_b32 s90, v35, 20
+; SI-NEXT: v_readlane_b32 s94, v35, 16
+; SI-NEXT: v_mov_b32_e32 v29, s16
+; SI-NEXT: v_readlane_b32 s16, v36, 39
+; SI-NEXT: v_readlane_b32 s77, v35, 25
+; SI-NEXT: v_readlane_b32 s79, v35, 23
+; SI-NEXT: v_readlane_b32 s89, v35, 19
+; SI-NEXT: v_readlane_b32 s91, v35, 21
+; SI-NEXT: v_readlane_b32 s95, v35, 17
+; SI-NEXT: v_writelane_b32 v35, s70, 0
+; SI-NEXT: v_mov_b32_e32 v30, s16
+; SI-NEXT: v_readlane_b32 s16, v36, 40
+; SI-NEXT: v_writelane_b32 v35, s71, 1
+; SI-NEXT: v_mov_b32_e32 v7, s35
+; SI-NEXT: v_mov_b32_e32 v31, s16
+; SI-NEXT: v_readlane_b32 s16, v36, 41
+; SI-NEXT: v_readlane_b32 s34, v35, 36
+; SI-NEXT: v_readlane_b32 s50, v35, 34
+; SI-NEXT: v_mov_b32_e32 v6, s38
+; SI-NEXT: v_mov_b32_e32 v17, s87
+; SI-NEXT: v_mov_b32_e32 v18, s86
+; SI-NEXT: v_mov_b32_e32 v32, s16
+; SI-NEXT: v_readlane_b32 s22, v36, 43
+; SI-NEXT: v_readlane_b32 s23, v36, 46
+; SI-NEXT: v_readlane_b32 s36, v35, 14
+; SI-NEXT: v_readlane_b32 s38, v35, 10
+; SI-NEXT: v_readlane_b32 s16, v35, 6
+; SI-NEXT: v_readlane_b32 s52, v35, 8
+; SI-NEXT: v_readlane_b32 s86, v36, 14
+; SI-NEXT: v_readlane_b32 s35, v35, 37
+; SI-NEXT: v_readlane_b32 s51, v35, 35
+; SI-NEXT: v_readlane_b32 s18, v36, 42
+; SI-NEXT: v_readlane_b32 s20, v36, 44
+; SI-NEXT: v_readlane_b32 s21, v36, 45
+; SI-NEXT: v_readlane_b32 s24, v36, 48
+; SI-NEXT: v_readlane_b32 s37, v35, 15
+; SI-NEXT: v_readlane_b32 s39, v35, 11
+; SI-NEXT: v_readlane_b32 s17, v35, 7
+; SI-NEXT: v_readlane_b32 s53, v35, 9
+; SI-NEXT: v_readlane_b32 s87, v36, 15
; SI-NEXT: s_mov_b32 s35, s22
; SI-NEXT: s_mov_b32 s51, s23
-; SI-NEXT: v_readlane_b32 s22, v37, 43
-; SI-NEXT: v_mov_b32_e32 v1, s82
-; SI-NEXT: v_mov_b32_e32 v2, s71
-; SI-NEXT: v_mov_b32_e32 v3, s67
-; SI-NEXT: v_mov_b32_e32 v4, s55
-; SI-NEXT: v_mov_b32_e32 v5, s30
-; SI-NEXT: v_mov_b32_e32 v6, s48
+; SI-NEXT: v_readlane_b32 s22, v35, 32
+; SI-NEXT: v_mov_b32_e32 v1, s68
+; SI-NEXT: v_mov_b32_e32 v2, s65
+; SI-NEXT: v_mov_b32_e32 v3, s54
+; SI-NEXT: v_mov_b32_e32 v4, s30
+; SI-NEXT: v_mov_b32_e32 v5, s49
; SI-NEXT: v_mov_b32_e32 v9, s92
-; SI-NEXT: v_mov_b32_e32 v12, s96
-; SI-NEXT: v_mov_b32_e32 v21, s97
-; SI-NEXT: v_readlane_b32 vcc_lo, v37, 23
-; SI-NEXT: s_mov_b32 s37, s18
-; SI-NEXT: s_mov_b32 s39, s20
+; SI-NEXT: v_mov_b32_e32 v23, s80
+; SI-NEXT: v_mov_b32_e32 v26, s99
+; SI-NEXT: v_mov_b32_e32 v12, s98
+; SI-NEXT: v_mov_b32_e32 v14, s97
+; SI-NEXT: v_mov_b32_e32 v15, s96
+; SI-NEXT: s_mov_b32 s95, s18
+; SI-NEXT: v_readlane_b32 vcc_lo, v35, 12
+; SI-NEXT: s_mov_b32 s37, s20
+; SI-NEXT: s_mov_b32 s39, s21
; SI-NEXT: s_mov_b32 s18, s16
-; SI-NEXT: s_mov_b32 s53, s21
-; SI-NEXT: v_readlane_b32 s54, v37, 15
-; SI-NEXT: v_readlane_b32 s16, v37, 13
+; SI-NEXT: s_mov_b32 s53, s24
+; SI-NEXT: v_readlane_b32 s54, v35, 4
+; SI-NEXT: v_readlane_b32 s16, v35, 2
; SI-NEXT: s_mov_b32 s84, s86
-; SI-NEXT: v_readlane_b32 s64, v36, 11
-; SI-NEXT: v_readlane_b32 s23, v37, 44
-; SI-NEXT: v_readlane_b32 s66, v36, 9
-; SI-NEXT: v_readlane_b32 s70, v37, 41
-; SI-NEXT: v_readlane_b32 s82, v36, 7
-; SI-NEXT: v_readlane_b32 s86, v37, 39
-; SI-NEXT: v_readlane_b32 s96, v36, 5
-; SI-NEXT: v_readlane_b32 s98, v37, 37
-; SI-NEXT: v_readlane_b32 s20, v36, 3
-; SI-NEXT: v_readlane_b32 s92, v36, 1
-; SI-NEXT: v_readlane_b32 s24, v37, 63
-; SI-NEXT: v_readlane_b32 s30, v37, 61
-; SI-NEXT: v_readlane_b32 s68, v37, 59
-; SI-NEXT: v_readlane_b32 s80, v37, 57
-; SI-NEXT: v_readlane_b32 s48, v37, 55
+; SI-NEXT: v_readlane_b32 s64, v36, 0
+; SI-NEXT: v_readlane_b32 s23, v35, 33
+; SI-NEXT: v_readlane_b32 s66, v35, 62
+; SI-NEXT: v_readlane_b32 s70, v35, 30
+; SI-NEXT: v_readlane_b32 s82, v35, 60
+; SI-NEXT: v_readlane_b32 s86, v35, 28
+; SI-NEXT: v_readlane_b32 s96, v35, 58
+; SI-NEXT: v_readlane_b32 s98, v35, 26
+; SI-NEXT: v_readlane_b32 s20, v35, 56
+; SI-NEXT: v_readlane_b32 s92, v35, 54
+; SI-NEXT: v_readlane_b32 s24, v35, 52
+; SI-NEXT: v_readlane_b32 s30, v35, 50
+; SI-NEXT: v_readlane_b32 s68, v35, 48
+; SI-NEXT: v_readlane_b32 s80, v35, 46
+; SI-NEXT: v_readlane_b32 s48, v35, 44
; SI-NEXT: v_mov_b32_e32 v19, s85
-; SI-NEXT: v_readlane_b32 s26, v36, 55
-; SI-NEXT: v_readlane_b32 s19, v36, 57
-; SI-NEXT: v_readlane_b32 s27, v36, 58
-; SI-NEXT: v_readlane_b32 s28, v36, 59
-; SI-NEXT: v_readlane_b32 s29, v36, 60
-; SI-NEXT: v_readlane_b32 vcc_hi, v37, 24
-; SI-NEXT: v_readlane_b32 s77, v36, 61
-; SI-NEXT: v_readlane_b32 s55, v37, 16
-; SI-NEXT: v_readlane_b32 s17, v37, 14
-; SI-NEXT: v_readlane_b32 s79, v36, 62
-; SI-NEXT: v_readlane_b32 s89, v36, 63
-; SI-NEXT: v_readlane_b32 s91, v35, 0
-; SI-NEXT: v_readlane_b32 s65, v36, 12
-; SI-NEXT: v_readlane_b32 s67, v36, 10
-; SI-NEXT: v_readlane_b32 s23, v35, 1
-; SI-NEXT: v_readlane_b32 s71, v37, 42
-; SI-NEXT: v_readlane_b32 s83, v36, 8
-; SI-NEXT: v_readlane_b32 s87, v37, 40
-; SI-NEXT: v_readlane_b32 s97, v36, 6
-; SI-NEXT: v_readlane_b32 s99, v37, 38
-; SI-NEXT: v_readlane_b32 s21, v36, 4
-; SI-NEXT: v_readlane_b32 s93, v36, 2
-; SI-NEXT: v_readlane_b32 s25, v36, 0
-; SI-NEXT: v_readlane_b32 s31, v37, 62
-; SI-NEXT: v_readlane_b32 s69, v37, 60
-; SI-NEXT: v_readlane_b32 s81, v37, 58
-; SI-NEXT: v_readlane_b32 s49, v37, 56
+; SI-NEXT: v_readlane_b32 s19, v36, 47
+; SI-NEXT: v_readlane_b32 s26, v36, 49
+; SI-NEXT: v_readlane_b32 s27, v36, 50
+; SI-NEXT: v_readlane_b32 s28, v36, 51
+; SI-NEXT: v_readlane_b32 s29, v36, 52
+; SI-NEXT: v_readlane_b32 vcc_hi, v35, 13
+; SI-NEXT: v_readlane_b32 s77, v36, 53
+; SI-NEXT: v_readlane_b32 s55, v35, 5
+; SI-NEXT: v_readlane_b32 s17, v35, 3
+; SI-NEXT: v_readlane_b32 s79, v36, 54
+; SI-NEXT: v_readlane_b32 s89, v36, 55
+; SI-NEXT: v_readlane_b32 s91, v36, 56
+; SI-NEXT: v_readlane_b32 s65, v36, 1
+; SI-NEXT: v_readlane_b32 s67, v35, 63
+; SI-NEXT: v_readlane_b32 s23, v36, 57
+; SI-NEXT: v_readlane_b32 s71, v35, 31
+; SI-NEXT: v_readlane_b32 s83, v35, 61
+; SI-NEXT: v_readlane_b32 s87, v35, 29
+; SI-NEXT: v_readlane_b32 s97, v35, 59
+; SI-NEXT: v_readlane_b32 s99, v35, 27
+; SI-NEXT: v_readlane_b32 s21, v35, 57
+; SI-NEXT: v_readlane_b32 s93, v35, 55
+; SI-NEXT: v_readlane_b32 s25, v35, 53
+; SI-NEXT: v_readlane_b32 s31, v35, 51
+; SI-NEXT: v_readlane_b32 s69, v35, 49
+; SI-NEXT: v_readlane_b32 s81, v35, 47
+; SI-NEXT: v_readlane_b32 s49, v35, 45
; SI-NEXT: .LBB95_5: ; %end
; SI-NEXT: s_lshl_b32 s16, s16, 8
; SI-NEXT: s_and_b32 s17, s74, 0xff
@@ -181682,23 +181843,23 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v11, s16, v11
; SI-NEXT: buffer_store_dword v31, v23, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v23, vcc, 20, v0
-; SI-NEXT: v_readlane_b32 s16, v37, 49
+; SI-NEXT: v_readlane_b32 s16, v35, 38
; SI-NEXT: buffer_store_dword v20, v23, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v20, vcc, 24, v0
-; SI-NEXT: v_readlane_b32 s17, v37, 50
-; SI-NEXT: v_readlane_b32 s22, v37, 51
+; SI-NEXT: v_readlane_b32 s17, v35, 39
+; SI-NEXT: v_readlane_b32 s22, v35, 40
; SI-NEXT: buffer_store_dword v30, v20, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v20, vcc, 28, v0
; SI-NEXT: s_lshl_b32 s16, s16, 8
; SI-NEXT: s_and_b32 s17, s46, 0xff
-; SI-NEXT: v_readlane_b32 s23, v37, 52
+; SI-NEXT: v_readlane_b32 s23, v35, 41
; SI-NEXT: buffer_store_dword v16, v20, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v16, vcc, 32, v0
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_and_b32 s17, s22, 0xff
-; SI-NEXT: v_readlane_b32 s22, v37, 53
+; SI-NEXT: v_readlane_b32 s22, v35, 42
; SI-NEXT: buffer_store_dword v29, v16, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v16, vcc, 36, v0
; SI-NEXT: s_lshl_b32 s17, s17, 16
@@ -181764,7 +181925,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_i32_e32 v9, vcc, 64, v0
; SI-NEXT: v_mov_b32_e32 v10, s16
; SI-NEXT: s_and_b32 s16, s43, 0xff
-; SI-NEXT: s_lshl_b32 s17, s19, 8
+; SI-NEXT: s_lshl_b32 s17, s26, 8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: buffer_store_dword v10, v9, s[0:3], 0 offen
; SI-NEXT: s_or_b32 s16, s16, s17
@@ -181801,7 +181962,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_lshl_b32 s16, s66, 8
; SI-NEXT: s_or_b32 s14, s14, s16
; SI-NEXT: s_and_b32 s16, s64, 0xff
-; SI-NEXT: v_readlane_b32 s20, v36, 13
+; SI-NEXT: v_readlane_b32 s20, v36, 2
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: s_lshl_b32 s17, s20, 24
; SI-NEXT: s_and_b32 s14, s14, 0xffff
@@ -181813,7 +181974,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x50, v0
; SI-NEXT: v_mov_b32_e32 v8, s14
; SI-NEXT: s_and_b32 s14, s15, 0xff
-; SI-NEXT: s_lshl_b32 s15, s26, 8
+; SI-NEXT: s_lshl_b32 s15, s19, 8
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: buffer_store_dword v8, v7, s[0:3], 0 offen
; SI-NEXT: s_or_b32 s14, s14, s15
@@ -181822,15 +181983,15 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_and_b32 s14, s14, 0xffff
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_or_b32_e32 v6, s14, v6
-; SI-NEXT: v_readlane_b32 s14, v36, 15
+; SI-NEXT: v_readlane_b32 s14, v36, 4
; SI-NEXT: s_and_b32 s12, s12, 0xff
-; SI-NEXT: v_readlane_b32 s15, v36, 16
+; SI-NEXT: v_readlane_b32 s15, v36, 5
; SI-NEXT: s_lshl_b32 s14, s14, 8
; SI-NEXT: s_or_b32 s12, s12, s14
-; SI-NEXT: v_readlane_b32 s14, v36, 17
-; SI-NEXT: v_readlane_b32 s15, v36, 18
+; SI-NEXT: v_readlane_b32 s14, v36, 6
+; SI-NEXT: v_readlane_b32 s15, v36, 7
; SI-NEXT: s_and_b32 s14, s14, 0xff
-; SI-NEXT: v_readlane_b32 s16, v36, 19
+; SI-NEXT: v_readlane_b32 s16, v36, 8
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_lshl_b32 s15, s16, 24
; SI-NEXT: s_and_b32 s12, s12, 0xffff
@@ -181851,13 +182012,13 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_or_b32_e32 v5, s12, v5
-; SI-NEXT: v_readlane_b32 s12, v36, 21
+; SI-NEXT: v_readlane_b32 s12, v36, 10
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s13, v36, 22
+; SI-NEXT: v_readlane_b32 s13, v36, 11
; SI-NEXT: s_lshl_b32 s12, s12, 8
; SI-NEXT: s_or_b32 s10, s10, s12
-; SI-NEXT: v_readlane_b32 s12, v36, 23
-; SI-NEXT: v_readlane_b32 s13, v36, 24
+; SI-NEXT: v_readlane_b32 s12, v36, 12
+; SI-NEXT: v_readlane_b32 s13, v36, 13
; SI-NEXT: s_and_b32 s12, s12, 0xff
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_lshl_b32 s13, s84, 24
@@ -181879,15 +182040,15 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_or_b32_e32 v4, s10, v4
-; SI-NEXT: v_readlane_b32 s10, v36, 27
+; SI-NEXT: v_readlane_b32 s10, v36, 16
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s11, v36, 28
+; SI-NEXT: v_readlane_b32 s11, v36, 17
; SI-NEXT: s_lshl_b32 s10, s10, 8
; SI-NEXT: s_or_b32 s8, s8, s10
-; SI-NEXT: v_readlane_b32 s10, v36, 29
-; SI-NEXT: v_readlane_b32 s11, v36, 30
+; SI-NEXT: v_readlane_b32 s10, v36, 18
+; SI-NEXT: v_readlane_b32 s11, v36, 19
; SI-NEXT: s_and_b32 s10, s10, 0xff
-; SI-NEXT: v_readlane_b32 s12, v36, 31
+; SI-NEXT: v_readlane_b32 s12, v36, 20
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_lshl_b32 s11, s12, 24
; SI-NEXT: s_and_b32 s8, s8, 0xffff
@@ -181908,15 +182069,15 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v3, s8, v3
-; SI-NEXT: v_readlane_b32 s8, v36, 33
+; SI-NEXT: v_readlane_b32 s8, v36, 22
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: v_readlane_b32 s9, v36, 34
+; SI-NEXT: v_readlane_b32 s9, v36, 23
; SI-NEXT: s_lshl_b32 s8, s8, 8
; SI-NEXT: s_or_b32 s6, s6, s8
-; SI-NEXT: v_readlane_b32 s8, v36, 35
-; SI-NEXT: v_readlane_b32 s9, v36, 36
+; SI-NEXT: v_readlane_b32 s8, v36, 24
+; SI-NEXT: v_readlane_b32 s9, v36, 25
; SI-NEXT: s_and_b32 s8, s8, 0xff
-; SI-NEXT: v_readlane_b32 s10, v36, 37
+; SI-NEXT: v_readlane_b32 s10, v36, 26
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_lshl_b32 s9, s10, 24
; SI-NEXT: s_and_b32 s6, s6, 0xffff
@@ -181937,15 +182098,15 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v2, s6, v2
-; SI-NEXT: v_readlane_b32 s6, v36, 39
+; SI-NEXT: v_readlane_b32 s6, v36, 28
; SI-NEXT: s_and_b32 s4, s4, 0xff
-; SI-NEXT: v_readlane_b32 s7, v36, 40
+; SI-NEXT: v_readlane_b32 s7, v36, 29
; SI-NEXT: s_lshl_b32 s6, s6, 8
; SI-NEXT: s_or_b32 s4, s4, s6
-; SI-NEXT: v_readlane_b32 s6, v37, 2
-; SI-NEXT: v_readlane_b32 s7, v37, 3
+; SI-NEXT: v_readlane_b32 s6, v35, 0
+; SI-NEXT: v_readlane_b32 s7, v35, 1
; SI-NEXT: s_and_b32 s6, s6, 0xff
-; SI-NEXT: v_readlane_b32 s8, v37, 0
+; SI-NEXT: v_readlane_b32 s8, v36, 30
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_lshl_b32 s7, s8, 24
; SI-NEXT: s_and_b32 s4, s4, 0xffff
@@ -181967,12 +182128,12 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v1, s4, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
-; SI-NEXT: v_readlane_b32 s23, v37, 54
-; SI-NEXT: v_readlane_b32 s21, v36, 14
-; SI-NEXT: v_readlane_b32 s17, v36, 20
-; SI-NEXT: v_readlane_b32 s13, v36, 32
-; SI-NEXT: v_readlane_b32 s11, v36, 38
-; SI-NEXT: v_readlane_b32 s9, v37, 1
+; SI-NEXT: v_readlane_b32 s23, v35, 43
+; SI-NEXT: v_readlane_b32 s21, v36, 3
+; SI-NEXT: v_readlane_b32 s17, v36, 9
+; SI-NEXT: v_readlane_b32 s13, v36, 21
+; SI-NEXT: v_readlane_b32 s11, v36, 27
+; SI-NEXT: v_readlane_b32 s9, v36, 31
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: v_readlane_b32 s99, v34, 35
; SI-NEXT: v_readlane_b32 s98, v34, 34
@@ -182014,7 +182175,6 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -215012,8 +215172,8 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_writelane_b32 v63, s30, 0
@@ -215043,29 +215203,13 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_writelane_b32 v63, s80, 24
; SI-NEXT: v_writelane_b32 v63, s81, 25
; SI-NEXT: v_writelane_b32 v63, s82, 26
-; SI-NEXT: s_lshr_b32 s5, s16, 16
-; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; SI-NEXT: v_writelane_b32 v63, s83, 27
-; SI-NEXT: s_lshr_b32 s6, s17, 16
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v62, s5, 0
; SI-NEXT: v_writelane_b32 v63, s84, 28
-; SI-NEXT: s_lshr_b32 s7, s18, 16
-; SI-NEXT: v_writelane_b32 v62, s6, 1
; SI-NEXT: v_writelane_b32 v63, s85, 29
-; SI-NEXT: s_lshr_b32 s8, s19, 16
-; SI-NEXT: v_writelane_b32 v62, s7, 2
; SI-NEXT: v_writelane_b32 v63, s86, 30
-; SI-NEXT: s_lshr_b32 s9, s20, 16
-; SI-NEXT: v_writelane_b32 v62, s8, 3
; SI-NEXT: v_writelane_b32 v63, s87, 31
-; SI-NEXT: s_lshr_b32 s10, s21, 16
-; SI-NEXT: v_writelane_b32 v62, s9, 4
; SI-NEXT: v_writelane_b32 v63, s96, 32
-; SI-NEXT: s_lshr_b32 s11, s22, 16
-; SI-NEXT: v_writelane_b32 v62, s10, 5
; SI-NEXT: v_writelane_b32 v63, s97, 33
-; SI-NEXT: s_lshr_b32 s12, s23, 16
; SI-NEXT: v_readfirstlane_b32 s52, v17
; SI-NEXT: v_readfirstlane_b32 s48, v16
; SI-NEXT: v_readfirstlane_b32 s35, v15
@@ -215084,37 +215228,42 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_readfirstlane_b32 s56, v2
; SI-NEXT: v_readfirstlane_b32 s46, v1
; SI-NEXT: v_readfirstlane_b32 s44, v0
-; SI-NEXT: v_writelane_b32 v62, s11, 6
; SI-NEXT: v_writelane_b32 v63, s98, 34
-; SI-NEXT: s_lshr_b32 s43, s29, 16
-; SI-NEXT: s_lshr_b32 s42, s28, 16
-; SI-NEXT: s_lshr_b32 s41, s27, 16
-; SI-NEXT: s_lshr_b32 s40, s26, 16
-; SI-NEXT: s_lshr_b32 s15, s25, 16
+; SI-NEXT: s_lshr_b32 s42, s29, 16
+; SI-NEXT: s_lshr_b32 s41, s28, 16
+; SI-NEXT: s_lshr_b32 s40, s27, 16
+; SI-NEXT: s_lshr_b32 s15, s26, 16
+; SI-NEXT: s_lshr_b32 s14, s25, 16
; SI-NEXT: s_lshr_b32 s13, s24, 16
-; SI-NEXT: s_lshr_b32 s55, s52, 16
-; SI-NEXT: s_lshr_b32 s51, s48, 16
-; SI-NEXT: s_lshr_b32 s38, s35, 16
-; SI-NEXT: s_lshr_b32 s31, s30, 16
+; SI-NEXT: s_lshr_b32 s12, s23, 16
+; SI-NEXT: s_lshr_b32 s11, s22, 16
+; SI-NEXT: s_lshr_b32 s10, s21, 16
+; SI-NEXT: s_lshr_b32 s9, s20, 16
+; SI-NEXT: s_lshr_b32 s8, s19, 16
+; SI-NEXT: s_lshr_b32 s7, s18, 16
+; SI-NEXT: s_lshr_b32 s6, s17, 16
+; SI-NEXT: s_lshr_b32 s5, s16, 16
+; SI-NEXT: s_lshr_b32 s39, s52, 16
+; SI-NEXT: s_lshr_b32 s36, s48, 16
+; SI-NEXT: s_lshr_b32 vcc_hi, s35, 16
+; SI-NEXT: s_lshr_b32 vcc_lo, s30, 16
; SI-NEXT: s_lshr_b32 s95, s94, 16
-; SI-NEXT: s_lshr_b32 s93, s92, 16
-; SI-NEXT: s_lshr_b32 s91, s90, 16
-; SI-NEXT: s_lshr_b32 s89, s88, 16
-; SI-NEXT: s_lshr_b32 s79, s78, 16
-; SI-NEXT: s_lshr_b32 s77, s76, 16
-; SI-NEXT: s_lshr_b32 s75, s74, 16
-; SI-NEXT: s_lshr_b32 s73, s72, 16
-; SI-NEXT: s_lshr_b32 s63, s62, 16
-; SI-NEXT: s_lshr_b32 s61, s60, 16
-; SI-NEXT: s_lshr_b32 s59, s58, 16
-; SI-NEXT: s_lshr_b32 s57, s56, 16
-; SI-NEXT: s_lshr_b32 s47, s46, 16
-; SI-NEXT: s_lshr_b32 s45, s44, 16
+; SI-NEXT: s_lshr_b32 s91, s92, 16
+; SI-NEXT: s_lshr_b32 s89, s90, 16
+; SI-NEXT: s_lshr_b32 s79, s88, 16
+; SI-NEXT: s_lshr_b32 s77, s78, 16
+; SI-NEXT: s_lshr_b32 s75, s76, 16
+; SI-NEXT: s_lshr_b32 s73, s74, 16
+; SI-NEXT: s_lshr_b32 s63, s72, 16
+; SI-NEXT: s_lshr_b32 s61, s62, 16
+; SI-NEXT: s_lshr_b32 s59, s60, 16
+; SI-NEXT: s_lshr_b32 s57, s58, 16
+; SI-NEXT: s_lshr_b32 s47, s56, 16
+; SI-NEXT: s_lshr_b32 s45, s46, 16
+; SI-NEXT: s_lshr_b32 s43, s44, 16
; SI-NEXT: v_readfirstlane_b32 s4, v18
-; SI-NEXT: v_writelane_b32 v62, s12, 7
; SI-NEXT: v_writelane_b32 v63, s99, 35
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v62, s13, 8
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -215129,105 +215278,115 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB103_3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshl_b32 s4, s16, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 35
+; SI-NEXT: v_writelane_b32 v62, s4, 19
; SI-NEXT: s_lshl_b32 s4, s5, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 34
+; SI-NEXT: v_writelane_b32 v62, s4, 18
; SI-NEXT: s_lshl_b32 s4, s17, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 33
+; SI-NEXT: v_writelane_b32 v62, s4, 17
; SI-NEXT: s_lshl_b32 s4, s6, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 32
+; SI-NEXT: v_writelane_b32 v62, s4, 16
; SI-NEXT: s_lshl_b32 s4, s18, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 31
+; SI-NEXT: v_writelane_b32 v62, s4, 15
; SI-NEXT: s_lshl_b32 s4, s7, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 30
+; SI-NEXT: v_writelane_b32 v62, s4, 14
; SI-NEXT: s_lshl_b32 s4, s19, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 29
+; SI-NEXT: v_writelane_b32 v62, s4, 13
; SI-NEXT: s_lshl_b32 s4, s8, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 28
+; SI-NEXT: v_writelane_b32 v62, s4, 12
; SI-NEXT: s_lshl_b32 s4, s20, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 27
+; SI-NEXT: v_writelane_b32 v62, s4, 11
; SI-NEXT: s_lshl_b32 s4, s9, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 26
+; SI-NEXT: v_writelane_b32 v62, s4, 10
; SI-NEXT: s_lshl_b32 s4, s21, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 25
+; SI-NEXT: v_writelane_b32 v62, s4, 9
; SI-NEXT: s_lshl_b32 s4, s10, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 24
+; SI-NEXT: v_writelane_b32 v62, s4, 8
; SI-NEXT: s_lshl_b32 s4, s22, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 23
+; SI-NEXT: v_writelane_b32 v62, s4, 7
; SI-NEXT: s_lshl_b32 s4, s11, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 22
+; SI-NEXT: v_writelane_b32 v62, s4, 6
; SI-NEXT: s_lshl_b32 s4, s23, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 21
+; SI-NEXT: v_writelane_b32 v62, s4, 5
; SI-NEXT: s_lshl_b32 s4, s12, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 20
+; SI-NEXT: v_writelane_b32 v62, s4, 4
; SI-NEXT: s_lshl_b32 s4, s24, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 19
+; SI-NEXT: v_writelane_b32 v62, s4, 3
; SI-NEXT: s_lshl_b32 s4, s13, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 18
+; SI-NEXT: v_writelane_b32 v62, s4, 2
; SI-NEXT: s_lshl_b32 s4, s25, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 17
-; SI-NEXT: s_lshl_b32 s4, s15, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 16
-; SI-NEXT: s_lshl_b32 s4, s26, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 15
-; SI-NEXT: s_lshl_b32 s4, s40, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 14
-; SI-NEXT: s_lshl_b32 s4, s27, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 13
-; SI-NEXT: s_lshl_b32 s4, s41, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 12
-; SI-NEXT: s_lshl_b32 s4, s28, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 11
-; SI-NEXT: s_lshl_b32 s4, s42, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 10
-; SI-NEXT: s_lshl_b32 s4, s29, 16
-; SI-NEXT: v_writelane_b32 v62, s4, 9
-; SI-NEXT: s_lshl_b32 s99, s43, 16
-; SI-NEXT: s_lshl_b32 s34, s44, 16
-; SI-NEXT: s_lshl_b32 s36, s45, 16
-; SI-NEXT: s_lshl_b32 s37, s46, 16
-; SI-NEXT: s_lshl_b32 s39, s47, 16
-; SI-NEXT: s_lshl_b32 s49, s56, 16
-; SI-NEXT: s_lshl_b32 s50, s57, 16
-; SI-NEXT: s_lshl_b32 s53, s58, 16
-; SI-NEXT: s_lshl_b32 s54, s59, 16
-; SI-NEXT: s_lshl_b32 s64, s60, 16
-; SI-NEXT: s_lshl_b32 s65, s61, 16
-; SI-NEXT: s_lshl_b32 s66, s62, 16
-; SI-NEXT: s_lshl_b32 s67, s63, 16
-; SI-NEXT: s_lshl_b32 s6, s72, 16
-; SI-NEXT: s_lshl_b32 s68, s73, 16
-; SI-NEXT: s_lshl_b32 s7, s74, 16
-; SI-NEXT: s_lshl_b32 s69, s75, 16
-; SI-NEXT: s_lshl_b32 s70, s76, 16
-; SI-NEXT: s_lshl_b32 s71, s77, 16
-; SI-NEXT: s_lshl_b32 s8, s78, 16
-; SI-NEXT: s_lshl_b32 s80, s79, 16
-; SI-NEXT: s_lshl_b32 s81, s88, 16
-; SI-NEXT: s_lshl_b32 s9, s89, 16
-; SI-NEXT: s_lshl_b32 s82, s90, 16
-; SI-NEXT: s_lshl_b32 s83, s91, 16
-; SI-NEXT: s_lshl_b32 s10, s92, 16
-; SI-NEXT: s_lshl_b32 s84, s93, 16
-; SI-NEXT: s_lshl_b32 s85, s94, 16
-; SI-NEXT: s_lshl_b32 s11, s95, 16
-; SI-NEXT: s_lshl_b32 s86, s30, 16
-; SI-NEXT: s_lshl_b32 s87, s31, 16
-; SI-NEXT: s_lshl_b32 s12, s35, 16
-; SI-NEXT: s_lshl_b32 s96, s38, 16
-; SI-NEXT: s_lshl_b32 s13, s48, 16
-; SI-NEXT: s_lshl_b32 s97, s51, 16
-; SI-NEXT: s_lshl_b32 s98, s52, 16
-; SI-NEXT: s_lshl_b32 s14, s55, 16
+; SI-NEXT: v_writelane_b32 v62, s4, 1
+; SI-NEXT: s_lshl_b32 s4, s14, 16
+; SI-NEXT: v_writelane_b32 v62, s4, 0
+; SI-NEXT: s_lshl_b32 s84, s26, 16
+; SI-NEXT: s_lshl_b32 s85, s15, 16
+; SI-NEXT: s_lshl_b32 s86, s27, 16
+; SI-NEXT: s_lshl_b32 s87, s40, 16
+; SI-NEXT: s_lshl_b32 s96, s28, 16
+; SI-NEXT: s_lshl_b32 s97, s41, 16
+; SI-NEXT: s_lshl_b32 s98, s29, 16
+; SI-NEXT: s_lshl_b32 s99, s42, 16
+; SI-NEXT: s_lshl_b32 s6, s44, 16
+; SI-NEXT: s_lshl_b32 s7, s43, 16
+; SI-NEXT: s_lshl_b32 s8, s46, 16
+; SI-NEXT: s_lshl_b32 s9, s45, 16
+; SI-NEXT: s_lshl_b32 s10, s56, 16
+; SI-NEXT: s_mov_b32 s64, s47
+; SI-NEXT: s_lshl_b32 s11, s47, 16
+; SI-NEXT: s_lshl_b32 s12, s58, 16
+; SI-NEXT: s_mov_b32 s65, s57
+; SI-NEXT: s_lshl_b32 s13, s57, 16
+; SI-NEXT: s_lshl_b32 s14, s60, 16
+; SI-NEXT: s_mov_b32 s50, s59
+; SI-NEXT: s_lshl_b32 s15, s59, 16
+; SI-NEXT: s_lshl_b32 s40, s62, 16
+; SI-NEXT: s_mov_b32 s66, s61
+; SI-NEXT: s_lshl_b32 s41, s61, 16
+; SI-NEXT: s_lshl_b32 s42, s72, 16
+; SI-NEXT: s_mov_b32 s67, s63
+; SI-NEXT: s_lshl_b32 s43, s63, 16
+; SI-NEXT: s_lshl_b32 s45, s74, 16
+; SI-NEXT: s_mov_b32 s68, s73
+; SI-NEXT: s_lshl_b32 s47, s73, 16
+; SI-NEXT: s_lshl_b32 s57, s76, 16
+; SI-NEXT: s_mov_b32 s53, s75
+; SI-NEXT: s_lshl_b32 s59, s75, 16
+; SI-NEXT: s_lshl_b32 s61, s78, 16
+; SI-NEXT: s_mov_b32 s69, s77
+; SI-NEXT: s_lshl_b32 s63, s77, 16
+; SI-NEXT: s_lshl_b32 s73, s88, 16
+; SI-NEXT: s_mov_b32 s70, s79
+; SI-NEXT: s_lshl_b32 s75, s79, 16
+; SI-NEXT: s_lshl_b32 s77, s90, 16
+; SI-NEXT: s_mov_b32 s71, s89
+; SI-NEXT: s_lshl_b32 s79, s89, 16
+; SI-NEXT: s_lshl_b32 s89, s92, 16
+; SI-NEXT: s_mov_b32 s49, s91
+; SI-NEXT: s_lshl_b32 s91, s91, 16
+; SI-NEXT: s_lshl_b32 s93, s94, 16
+; SI-NEXT: s_mov_b32 s80, s95
+; SI-NEXT: s_lshl_b32 s95, s95, 16
+; SI-NEXT: s_lshl_b32 s31, s30, 16
+; SI-NEXT: s_mov_b32 s81, vcc_lo
+; SI-NEXT: s_lshl_b32 s38, vcc_lo, 16
+; SI-NEXT: s_lshl_b32 s51, s35, 16
+; SI-NEXT: s_mov_b32 s82, vcc_hi
+; SI-NEXT: s_lshl_b32 s55, vcc_hi, 16
+; SI-NEXT: s_lshl_b32 s34, s48, 16
+; SI-NEXT: s_mov_b32 s54, s36
+; SI-NEXT: s_lshl_b32 s36, s36, 16
+; SI-NEXT: s_lshl_b32 s37, s52, 16
+; SI-NEXT: s_mov_b32 s83, s39
+; SI-NEXT: s_lshl_b32 s39, s39, 16
; SI-NEXT: s_cbranch_execnz .LBB103_4
; SI-NEXT: .LBB103_2: ; %cmp.true
-; SI-NEXT: v_cvt_f32_f16_e32 v0, s55
+; SI-NEXT: v_cvt_f32_f16_e32 v0, s83
; SI-NEXT: v_cvt_f32_f16_e32 v1, s52
-; SI-NEXT: v_cvt_f32_f16_e32 v2, s51
-; SI-NEXT: v_readlane_b32 s4, v62, 8
+; SI-NEXT: v_cvt_f32_f16_e32 v2, s54
+; SI-NEXT: s_lshr_b32 s4, s46, 16
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
@@ -215243,7 +215402,7 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_cvt_f32_f16_e32 v0, s48
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s38
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s82
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
@@ -215255,7 +215414,7 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_cvt_f32_f16_e32 v0, s35
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s31
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s81
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
@@ -215265,7 +215424,7 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_cvt_f32_f16_e32 v0, s30
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s95
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s80
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
@@ -215275,198 +215434,207 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_cvt_f32_f16_e32 v0, s94
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s93
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s49
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v51, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s91
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v0, s92
-; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v7, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s89
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s71
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v48, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s79
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s70
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v0, s90
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v16, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s77
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v1
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v8, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v49, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s88
-; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v53, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s75
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s69
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v49, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v50, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s78
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v55, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s73
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s53
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v52, v0
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v55
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: v_cvt_f16_f32_e32 v51, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s76
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v41, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s63
+; SI-NEXT: v_cvt_f16_f32_e32 v52, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s68
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v54, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v53, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s74
-; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v48
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v54, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s67
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v40, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v55, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s72
-; SI-NEXT: v_cvt_f16_f32_e32 v43, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s61
-; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v42, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v45, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v40, v1
+; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v55
+; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v41, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s62
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v52
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v45
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v53
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v51
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s66
+; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v40
+; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v50
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v44, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v43, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s60
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s59
-; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v43
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v44
+; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v42, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s50
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v46, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v45, v0
+; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v42
+; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v44, v1
+; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v45
+; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v52
+; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v51
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v44
+; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v53
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v54
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v49
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s65
; SI-NEXT: v_cvt_f32_f16_e32 v0, s58
+; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v43
+; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v41
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v35, v1
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v46
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v40
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v49
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s57
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s64
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v34, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s56
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v33, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s47
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v32, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s46
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
+; SI-NEXT: s_lshr_b32 s4, s44, 16
; SI-NEXT: v_cvt_f16_f32_e32 v31, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s45
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v30, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s44
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
+; SI-NEXT: s_lshr_b32 s4, s29, 16
; SI-NEXT: v_cvt_f16_f32_e32 v29, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s43
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v28, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s29
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
+; SI-NEXT: s_lshr_b32 s4, s28, 16
; SI-NEXT: v_cvt_f16_f32_e32 v27, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s42
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v26, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s28
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
+; SI-NEXT: s_lshr_b32 s4, s27, 16
; SI-NEXT: v_cvt_f16_f32_e32 v25, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s41
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v24, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s27
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
+; SI-NEXT: s_lshr_b32 s4, s26, 16
; SI-NEXT: v_cvt_f16_f32_e32 v23, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s40
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v22, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: v_cvt_f32_f16_e32 v0, s26
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
+; SI-NEXT: s_lshr_b32 s4, s25, 16
; SI-NEXT: v_cvt_f16_f32_e32 v21, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s15
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v20, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s25
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
+; SI-NEXT: s_lshr_b32 s4, s24, 16
; SI-NEXT: v_cvt_f16_f32_e32 v19, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v18, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s24
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_readlane_b32 s4, v62, 7
+; SI-NEXT: s_lshr_b32 s4, s23, 16
; SI-NEXT: v_cvt_f16_f32_e32 v17, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v36, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s23
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_readlane_b32 s4, v62, 6
+; SI-NEXT: s_lshr_b32 s4, s22, 16
; SI-NEXT: v_cvt_f16_f32_e32 v15, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v14, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s22
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_readlane_b32 s4, v62, 5
+; SI-NEXT: s_lshr_b32 s4, s21, 16
; SI-NEXT: v_cvt_f16_f32_e32 v13, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v12, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s21
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_readlane_b32 s4, v62, 4
+; SI-NEXT: s_lshr_b32 s4, s20, 16
; SI-NEXT: v_cvt_f16_f32_e32 v11, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v10, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s20
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_readlane_b32 s4, v62, 3
+; SI-NEXT: s_lshr_b32 s4, s19, 16
; SI-NEXT: v_cvt_f16_f32_e32 v9, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v37, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s19
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
-; SI-NEXT: v_readlane_b32 s4, v62, 2
+; SI-NEXT: s_lshr_b32 s4, s18, 16
; SI-NEXT: v_cvt_f16_f32_e32 v38, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v6, v0
-; SI-NEXT: v_readlane_b32 s4, v62, 1
+; SI-NEXT: s_lshr_b32 s4, s17, 16
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v5, v0
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 0
+; SI-NEXT: s_lshr_b32 s4, s16, 16
; SI-NEXT: v_cvt_f32_f16_e32 v1, s17
; SI-NEXT: v_cvt_f32_f16_e32 v2, s4
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v50, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v48, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v39, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v39
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -215475,16 +215643,16 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v38
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v37
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v36
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v36
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
@@ -215504,9 +215672,11 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v34
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v35
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v54
; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v16
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v7
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
@@ -215550,90 +215720,99 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: .LBB103_3:
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s83, s39
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr99
-; SI-NEXT: ; implicit-def: $sgpr34
-; SI-NEXT: ; implicit-def: $sgpr36
-; SI-NEXT: ; implicit-def: $sgpr37
-; SI-NEXT: ; implicit-def: $sgpr39
-; SI-NEXT: ; implicit-def: $sgpr49
-; SI-NEXT: ; implicit-def: $sgpr50
-; SI-NEXT: ; implicit-def: $sgpr53
-; SI-NEXT: ; implicit-def: $sgpr54
-; SI-NEXT: ; implicit-def: $sgpr64
-; SI-NEXT: ; implicit-def: $sgpr65
-; SI-NEXT: ; implicit-def: $sgpr66
-; SI-NEXT: ; implicit-def: $sgpr67
-; SI-NEXT: ; implicit-def: $sgpr68
-; SI-NEXT: ; implicit-def: $sgpr7
-; SI-NEXT: ; implicit-def: $sgpr69
-; SI-NEXT: ; implicit-def: $sgpr70
-; SI-NEXT: ; implicit-def: $sgpr71
-; SI-NEXT: ; implicit-def: $sgpr8
-; SI-NEXT: ; implicit-def: $sgpr80
-; SI-NEXT: ; implicit-def: $sgpr81
-; SI-NEXT: ; implicit-def: $sgpr9
-; SI-NEXT: ; implicit-def: $sgpr82
-; SI-NEXT: ; implicit-def: $sgpr83
-; SI-NEXT: ; implicit-def: $sgpr10
-; SI-NEXT: ; implicit-def: $sgpr84
-; SI-NEXT: ; implicit-def: $sgpr85
-; SI-NEXT: ; implicit-def: $sgpr11
-; SI-NEXT: ; implicit-def: $sgpr86
-; SI-NEXT: ; implicit-def: $sgpr87
-; SI-NEXT: ; implicit-def: $sgpr12
-; SI-NEXT: ; implicit-def: $sgpr96
-; SI-NEXT: ; implicit-def: $sgpr13
-; SI-NEXT: ; implicit-def: $sgpr97
-; SI-NEXT: ; implicit-def: $sgpr98
-; SI-NEXT: ; implicit-def: $sgpr14
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: ; kill: killed $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: ; kill: killed $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: ; kill: killed $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: ; kill: killed $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: ; kill: killed $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: ; kill: killed $sgpr6
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s54, s36
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s82, vcc_hi
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s81, vcc_lo
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s80, s95
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s49, s91
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s71, s89
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s70, s79
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s69, s77
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s53, s75
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s68, s73
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s67, s63
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s66, s61
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s50, s59
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s65, s57
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: s_mov_b32 s64, s47
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
+; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: ; implicit-def: $sgpr85
+; SI-NEXT: ; implicit-def: $sgpr86
+; SI-NEXT: ; implicit-def: $sgpr87
+; SI-NEXT: ; implicit-def: $sgpr96
+; SI-NEXT: ; implicit-def: $sgpr97
+; SI-NEXT: ; implicit-def: $sgpr98
+; SI-NEXT: ; implicit-def: $sgpr99
+; SI-NEXT: ; implicit-def: $sgpr7
+; SI-NEXT: ; implicit-def: $sgpr8
+; SI-NEXT: ; implicit-def: $sgpr9
+; SI-NEXT: ; implicit-def: $sgpr10
+; SI-NEXT: ; implicit-def: $sgpr11
+; SI-NEXT: ; implicit-def: $sgpr12
+; SI-NEXT: ; implicit-def: $sgpr13
+; SI-NEXT: ; implicit-def: $sgpr14
+; SI-NEXT: ; implicit-def: $sgpr15
+; SI-NEXT: ; implicit-def: $sgpr40
+; SI-NEXT: ; implicit-def: $sgpr41
+; SI-NEXT: ; implicit-def: $sgpr42
+; SI-NEXT: ; implicit-def: $sgpr43
+; SI-NEXT: ; implicit-def: $sgpr45
+; SI-NEXT: ; implicit-def: $sgpr47
+; SI-NEXT: ; implicit-def: $sgpr57
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr73
+; SI-NEXT: ; implicit-def: $sgpr75
+; SI-NEXT: ; implicit-def: $sgpr77
+; SI-NEXT: ; implicit-def: $sgpr79
+; SI-NEXT: ; implicit-def: $sgpr89
+; SI-NEXT: ; implicit-def: $sgpr91
+; SI-NEXT: ; implicit-def: $sgpr93
+; SI-NEXT: ; implicit-def: $sgpr95
+; SI-NEXT: ; implicit-def: $sgpr31
+; SI-NEXT: ; implicit-def: $sgpr38
+; SI-NEXT: ; implicit-def: $sgpr51
+; SI-NEXT: ; implicit-def: $sgpr55
+; SI-NEXT: ; implicit-def: $sgpr34
+; SI-NEXT: ; implicit-def: $sgpr36
+; SI-NEXT: ; implicit-def: $sgpr37
+; SI-NEXT: ; implicit-def: $sgpr39
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; kill: killed $sgpr6
; SI-NEXT: ; implicit-def: $sgpr6
@@ -215641,109 +215820,102 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: s_branch .LBB103_2
; SI-NEXT: .LBB103_4:
-; SI-NEXT: v_readlane_b32 s4, v62, 9
-; SI-NEXT: v_mov_b32_e32 v26, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 10
-; SI-NEXT: v_mov_b32_e32 v25, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 11
-; SI-NEXT: v_mov_b32_e32 v24, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 12
-; SI-NEXT: v_mov_b32_e32 v23, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 13
-; SI-NEXT: v_mov_b32_e32 v22, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 14
-; SI-NEXT: v_mov_b32_e32 v21, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 15
-; SI-NEXT: v_mov_b32_e32 v20, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 16
+; SI-NEXT: v_readlane_b32 s4, v62, 0
; SI-NEXT: v_mov_b32_e32 v19, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 17
+; SI-NEXT: v_readlane_b32 s4, v62, 1
; SI-NEXT: v_mov_b32_e32 v18, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 18
+; SI-NEXT: v_readlane_b32 s4, v62, 2
; SI-NEXT: v_mov_b32_e32 v17, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 19
-; SI-NEXT: v_mov_b32_e32 v50, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 20
+; SI-NEXT: v_readlane_b32 s4, v62, 3
+; SI-NEXT: v_mov_b32_e32 v48, s4
+; SI-NEXT: v_readlane_b32 s4, v62, 4
; SI-NEXT: v_mov_b32_e32 v15, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 21
+; SI-NEXT: v_readlane_b32 s4, v62, 5
; SI-NEXT: v_mov_b32_e32 v14, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 22
+; SI-NEXT: v_readlane_b32 s4, v62, 6
; SI-NEXT: v_mov_b32_e32 v13, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 23
+; SI-NEXT: v_readlane_b32 s4, v62, 7
; SI-NEXT: v_mov_b32_e32 v12, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 24
+; SI-NEXT: v_readlane_b32 s4, v62, 8
; SI-NEXT: v_mov_b32_e32 v11, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 25
+; SI-NEXT: v_readlane_b32 s4, v62, 9
; SI-NEXT: v_mov_b32_e32 v10, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 26
+; SI-NEXT: v_readlane_b32 s4, v62, 10
; SI-NEXT: v_mov_b32_e32 v9, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 27
+; SI-NEXT: v_readlane_b32 s4, v62, 11
; SI-NEXT: v_mov_b32_e32 v38, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 28
-; SI-NEXT: v_mov_b32_e32 v0, s14
+; SI-NEXT: v_readlane_b32 s4, v62, 12
+; SI-NEXT: v_mov_b32_e32 v0, s39
; SI-NEXT: v_mov_b32_e32 v39, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 29
+; SI-NEXT: v_readlane_b32 s4, v62, 13
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s98
+; SI-NEXT: v_mov_b32_e32 v0, s37
; SI-NEXT: v_mov_b32_e32 v6, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 30
+; SI-NEXT: v_readlane_b32 s4, v62, 14
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s97
+; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v5, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 31
+; SI-NEXT: v_readlane_b32 s4, v62, 15
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s13
+; SI-NEXT: v_mov_b32_e32 v0, s34
; SI-NEXT: v_mov_b32_e32 v4, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 32
+; SI-NEXT: v_readlane_b32 s4, v62, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s96
+; SI-NEXT: v_mov_b32_e32 v0, s55
; SI-NEXT: v_mov_b32_e32 v3, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 33
+; SI-NEXT: v_readlane_b32 s4, v62, 17
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s12
+; SI-NEXT: v_mov_b32_e32 v0, s51
; SI-NEXT: v_mov_b32_e32 v2, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 34
+; SI-NEXT: v_readlane_b32 s4, v62, 18
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mov_b32_e32 v0, s86
+; SI-NEXT: v_mov_b32_e32 v0, s31
; SI-NEXT: v_mov_b32_e32 v1, s4
-; SI-NEXT: v_readlane_b32 s4, v62, 35
-; SI-NEXT: v_mov_b32_e32 v49, s87
+; SI-NEXT: v_readlane_b32 s4, v62, 19
+; SI-NEXT: v_mov_b32_e32 v49, s38
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v51, s11
-; SI-NEXT: v_mov_b32_e32 v48, s85
-; SI-NEXT: v_mov_b32_e32 v53, s84
-; SI-NEXT: v_mov_b32_e32 v52, s10
-; SI-NEXT: v_mov_b32_e32 v55, s83
-; SI-NEXT: v_mov_b32_e32 v54, s82
-; SI-NEXT: v_mov_b32_e32 v41, s9
-; SI-NEXT: v_mov_b32_e32 v40, s81
-; SI-NEXT: v_mov_b32_e32 v43, s80
-; SI-NEXT: v_mov_b32_e32 v42, s8
-; SI-NEXT: v_mov_b32_e32 v45, s71
-; SI-NEXT: v_mov_b32_e32 v44, s70
-; SI-NEXT: v_mov_b32_e32 v47, s69
-; SI-NEXT: v_mov_b32_e32 v46, s7
-; SI-NEXT: v_mov_b32_e32 v57, s68
-; SI-NEXT: v_mov_b32_e32 v56, s6
-; SI-NEXT: v_mov_b32_e32 v59, s67
-; SI-NEXT: v_mov_b32_e32 v58, s66
-; SI-NEXT: v_mov_b32_e32 v61, s65
-; SI-NEXT: v_mov_b32_e32 v60, s64
-; SI-NEXT: v_mov_b32_e32 v37, s54
-; SI-NEXT: v_mov_b32_e32 v36, s53
-; SI-NEXT: v_mov_b32_e32 v33, s50
-; SI-NEXT: v_mov_b32_e32 v32, s49
-; SI-NEXT: v_mov_b32_e32 v31, s39
-; SI-NEXT: v_mov_b32_e32 v30, s37
-; SI-NEXT: v_mov_b32_e32 v29, s36
-; SI-NEXT: v_mov_b32_e32 v28, s34
+; SI-NEXT: v_mov_b32_e32 v51, s95
+; SI-NEXT: v_mov_b32_e32 v50, s93
+; SI-NEXT: v_mov_b32_e32 v53, s91
+; SI-NEXT: v_mov_b32_e32 v52, s89
+; SI-NEXT: v_mov_b32_e32 v55, s79
+; SI-NEXT: v_mov_b32_e32 v54, s77
+; SI-NEXT: v_mov_b32_e32 v41, s75
+; SI-NEXT: v_mov_b32_e32 v40, s73
+; SI-NEXT: v_mov_b32_e32 v43, s63
+; SI-NEXT: v_mov_b32_e32 v42, s61
+; SI-NEXT: v_mov_b32_e32 v45, s59
+; SI-NEXT: v_mov_b32_e32 v44, s57
+; SI-NEXT: v_mov_b32_e32 v47, s47
+; SI-NEXT: v_mov_b32_e32 v46, s45
+; SI-NEXT: v_mov_b32_e32 v57, s43
+; SI-NEXT: v_mov_b32_e32 v56, s42
+; SI-NEXT: v_mov_b32_e32 v59, s41
+; SI-NEXT: v_mov_b32_e32 v58, s40
+; SI-NEXT: v_mov_b32_e32 v61, s15
+; SI-NEXT: v_mov_b32_e32 v60, s14
+; SI-NEXT: v_mov_b32_e32 v37, s13
+; SI-NEXT: v_mov_b32_e32 v36, s12
+; SI-NEXT: v_mov_b32_e32 v33, s11
+; SI-NEXT: v_mov_b32_e32 v32, s10
+; SI-NEXT: v_mov_b32_e32 v31, s9
+; SI-NEXT: v_mov_b32_e32 v30, s8
+; SI-NEXT: v_mov_b32_e32 v29, s7
+; SI-NEXT: v_mov_b32_e32 v28, s6
; SI-NEXT: v_mov_b32_e32 v27, s99
+; SI-NEXT: v_mov_b32_e32 v26, s98
+; SI-NEXT: v_mov_b32_e32 v25, s97
+; SI-NEXT: v_mov_b32_e32 v24, s96
+; SI-NEXT: v_mov_b32_e32 v23, s87
+; SI-NEXT: v_mov_b32_e32 v22, s86
+; SI-NEXT: v_mov_b32_e32 v21, s85
+; SI-NEXT: v_mov_b32_e32 v20, s84
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: .LBB103_5: ; %end
@@ -215824,8 +215996,7 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v49
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v50
-; SI-NEXT: v_mul_f32_e32 v50, 1.0, v48
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v48
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v4
; SI-NEXT: v_lshr_b64 v[33:34], v[34:35], 16
@@ -215850,6 +216021,7 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_mul_f32_e32 v40, 1.0, v40
; SI-NEXT: v_mul_f32_e32 v54, 1.0, v54
; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52
+; SI-NEXT: v_mul_f32_e32 v50, 1.0, v50
; SI-NEXT: v_readlane_b32 s99, v63, 35
; SI-NEXT: v_readlane_b32 s98, v63, 34
; SI-NEXT: v_readlane_b32 s97, v63, 33
@@ -215963,8 +216135,8 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %
; SI-NEXT: v_mov_b32_e32 v0, v33
; SI-NEXT: v_mov_b32_e32 v1, v34
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -229014,297 +229186,245 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; SI-NEXT: v_writelane_b32 v32, s49, 9
; SI-NEXT: v_writelane_b32 v32, s50, 10
; SI-NEXT: v_writelane_b32 v32, s51, 11
-; SI-NEXT: s_lshr_b32 s4, s27, 16
-; SI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
; SI-NEXT: v_writelane_b32 v32, s52, 12
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v33, s4, 0
-; SI-NEXT: s_lshr_b32 s4, s25, 16
; SI-NEXT: v_writelane_b32 v32, s53, 13
-; SI-NEXT: v_writelane_b32 v33, s4, 1
-; SI-NEXT: s_lshr_b32 s4, s24, 16
; SI-NEXT: v_writelane_b32 v32, s54, 14
-; SI-NEXT: v_writelane_b32 v33, s4, 2
; SI-NEXT: v_writelane_b32 v32, s55, 15
-; SI-NEXT: v_writelane_b32 v33, s23, 3
-; SI-NEXT: s_lshr_b32 s4, s23, 16
; SI-NEXT: v_writelane_b32 v32, s64, 16
-; SI-NEXT: v_writelane_b32 v33, s4, 4
-; SI-NEXT: s_lshr_b32 s4, s21, 16
; SI-NEXT: v_writelane_b32 v32, s65, 17
-; SI-NEXT: v_writelane_b32 v33, s4, 5
; SI-NEXT: v_writelane_b32 v32, s66, 18
-; SI-NEXT: v_writelane_b32 v33, s19, 6
-; SI-NEXT: s_lshr_b32 s4, s19, 16
; SI-NEXT: v_writelane_b32 v32, s67, 19
-; SI-NEXT: v_writelane_b32 v33, s4, 7
; SI-NEXT: v_writelane_b32 v32, s68, 20
-; SI-NEXT: v_writelane_b32 v33, s17, 8
-; SI-NEXT: s_lshr_b32 s4, s17, 16
; SI-NEXT: v_writelane_b32 v32, s69, 21
-; SI-NEXT: v_writelane_b32 v33, s4, 9
-; SI-NEXT: s_lshr_b32 s4, s16, 16
; SI-NEXT: v_writelane_b32 v32, s70, 22
-; SI-NEXT: s_mov_b32 s46, s16
-; SI-NEXT: v_writelane_b32 v33, s4, 10
; SI-NEXT: v_writelane_b32 v32, s71, 23
-; SI-NEXT: s_mov_b32 s47, s18
-; SI-NEXT: v_writelane_b32 v33, s46, 11
; SI-NEXT: v_writelane_b32 v32, s80, 24
-; SI-NEXT: s_mov_b32 s57, s20
-; SI-NEXT: v_writelane_b32 v33, s47, 12
; SI-NEXT: v_writelane_b32 v32, s81, 25
-; SI-NEXT: s_mov_b32 s31, s22
-; SI-NEXT: v_writelane_b32 v33, s57, 13
+; SI-NEXT: s_mov_b32 s46, s16
+; SI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
; SI-NEXT: v_writelane_b32 v32, s82, 26
-; SI-NEXT: s_mov_b32 s35, s24
-; SI-NEXT: v_writelane_b32 v33, s31, 14
+; SI-NEXT: s_mov_b32 s47, s18
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_writelane_b32 v33, s46, 0
; SI-NEXT: v_writelane_b32 v32, s83, 27
-; SI-NEXT: s_mov_b32 s69, s26
-; SI-NEXT: v_writelane_b32 v33, s35, 15
+; SI-NEXT: s_mov_b32 s57, s20
+; SI-NEXT: v_readfirstlane_b32 s69, v0
+; SI-NEXT: v_writelane_b32 v33, s47, 1
; SI-NEXT: v_writelane_b32 v32, s84, 28
-; SI-NEXT: s_mov_b32 s78, s28
-; SI-NEXT: v_writelane_b32 v33, s69, 16
+; SI-NEXT: v_readfirstlane_b32 s71, v2
+; SI-NEXT: s_lshr_b32 s5, s69, 16
+; SI-NEXT: v_writelane_b32 v33, s57, 2
; SI-NEXT: v_writelane_b32 v32, s85, 29
-; SI-NEXT: v_readfirstlane_b32 s77, v10
-; SI-NEXT: v_readfirstlane_b32 s45, v0
-; SI-NEXT: v_writelane_b32 v33, s78, 17
+; SI-NEXT: v_readfirstlane_b32 s81, v4
+; SI-NEXT: s_lshr_b32 s58, s71, 16
+; SI-NEXT: v_writelane_b32 v33, s5, 3
; SI-NEXT: v_writelane_b32 v32, s86, 30
-; SI-NEXT: s_lshr_b32 s34, s18, 16
-; SI-NEXT: s_lshr_b32 s18, s77, 16
-; SI-NEXT: v_writelane_b32 v33, s45, 18
+; SI-NEXT: v_readfirstlane_b32 s82, v6
+; SI-NEXT: s_lshr_b32 s59, s81, 16
+; SI-NEXT: v_writelane_b32 v33, s58, 4
; SI-NEXT: v_writelane_b32 v32, s87, 31
-; SI-NEXT: v_readfirstlane_b32 s19, v13
-; SI-NEXT: v_readfirstlane_b32 s23, v12
-; SI-NEXT: v_writelane_b32 v33, s18, 19
+; SI-NEXT: v_readfirstlane_b32 s76, v8
+; SI-NEXT: s_lshr_b32 s60, s82, 16
+; SI-NEXT: v_writelane_b32 v33, s59, 5
; SI-NEXT: v_writelane_b32 v32, s96, 32
-; SI-NEXT: s_lshr_b32 s36, s20, 16
-; SI-NEXT: s_lshr_b32 s20, s23, 16
-; SI-NEXT: v_writelane_b32 v33, s19, 20
+; SI-NEXT: v_readfirstlane_b32 s78, v10
+; SI-NEXT: s_lshr_b32 s61, s76, 16
+; SI-NEXT: v_writelane_b32 v33, s60, 6
; SI-NEXT: v_writelane_b32 v32, s97, 33
-; SI-NEXT: v_readfirstlane_b32 s58, v15
-; SI-NEXT: v_readfirstlane_b32 s88, v14
-; SI-NEXT: v_writelane_b32 v33, s20, 21
+; SI-NEXT: s_lshr_b32 s55, s18, 16
+; SI-NEXT: v_readfirstlane_b32 s18, v12
+; SI-NEXT: s_lshr_b32 s62, s78, 16
+; SI-NEXT: v_writelane_b32 v33, s61, 7
; SI-NEXT: v_writelane_b32 v32, s98, 34
-; SI-NEXT: s_mov_b32 s39, s27
-; SI-NEXT: v_readfirstlane_b32 s60, v17
-; SI-NEXT: v_readfirstlane_b32 s92, v16
-; SI-NEXT: s_lshr_b32 s59, s88, 16
-; SI-NEXT: v_readfirstlane_b32 s98, v11
-; SI-NEXT: v_readfirstlane_b32 s27, v9
-; SI-NEXT: v_readfirstlane_b32 s76, v8
+; SI-NEXT: s_mov_b32 s90, s19
+; SI-NEXT: s_mov_b32 s39, s17
+; SI-NEXT: s_lshr_b32 s94, s20, 16
+; SI-NEXT: s_lshr_b32 s91, s19, 16
+; SI-NEXT: s_lshr_b32 s84, s17, 16
+; SI-NEXT: s_lshr_b32 s92, s16, 16
+; SI-NEXT: v_readfirstlane_b32 s89, v17
+; SI-NEXT: v_readfirstlane_b32 s20, v16
+; SI-NEXT: v_readfirstlane_b32 s19, v15
+; SI-NEXT: v_readfirstlane_b32 s88, v14
+; SI-NEXT: v_readfirstlane_b32 s79, v13
+; SI-NEXT: s_lshr_b32 s63, s18, 16
+; SI-NEXT: v_readfirstlane_b32 s77, v11
+; SI-NEXT: v_readfirstlane_b32 s16, v9
; SI-NEXT: v_readfirstlane_b32 s17, v7
-; SI-NEXT: v_readfirstlane_b32 s82, v6
-; SI-NEXT: v_readfirstlane_b32 s83, v5
-; SI-NEXT: v_readfirstlane_b32 s81, v4
+; SI-NEXT: v_readfirstlane_b32 s80, v5
; SI-NEXT: v_readfirstlane_b32 s70, v3
-; SI-NEXT: v_readfirstlane_b32 s71, v2
; SI-NEXT: v_readfirstlane_b32 s68, v1
-; SI-NEXT: v_writelane_b32 v33, s58, 22
+; SI-NEXT: v_writelane_b32 v33, s62, 8
; SI-NEXT: v_writelane_b32 v32, s99, 35
-; SI-NEXT: s_lshr_b32 s93, s29, 16
-; SI-NEXT: s_lshr_b32 s85, s28, 16
-; SI-NEXT: s_lshr_b32 s84, s26, 16
-; SI-NEXT: s_lshr_b32 s91, s22, 16
-; SI-NEXT: s_lshr_b32 s99, s60, 16
-; SI-NEXT: s_lshr_b32 s61, s92, 16
-; SI-NEXT: s_lshr_b32 s67, s58, 16
-; SI-NEXT: s_lshr_b32 s30, s19, 16
-; SI-NEXT: s_lshr_b32 s65, s98, 16
-; SI-NEXT: s_lshr_b32 s55, s27, 16
-; SI-NEXT: s_lshr_b32 s90, s76, 16
-; SI-NEXT: s_lshr_b32 s95, s17, 16
-; SI-NEXT: s_lshr_b32 s96, s82, 16
-; SI-NEXT: s_lshr_b32 s53, s83, 16
-; SI-NEXT: s_lshr_b32 s37, s81, 16
+; SI-NEXT: s_lshr_b32 s37, s29, 16
+; SI-NEXT: s_lshr_b32 s86, s28, 16
+; SI-NEXT: s_lshr_b32 s35, s27, 16
+; SI-NEXT: s_lshr_b32 s85, s26, 16
+; SI-NEXT: s_lshr_b32 s31, s25, 16
+; SI-NEXT: s_lshr_b32 s83, s24, 16
+; SI-NEXT: s_lshr_b32 s95, s23, 16
+; SI-NEXT: s_lshr_b32 s67, s22, 16
+; SI-NEXT: s_lshr_b32 s93, s21, 16
+; SI-NEXT: s_lshr_b32 s99, s89, 16
+; SI-NEXT: s_lshr_b32 s73, s20, 16
+; SI-NEXT: s_lshr_b32 s98, s19, 16
+; SI-NEXT: s_lshr_b32 s72, s88, 16
+; SI-NEXT: s_lshr_b32 s97, s79, 16
+; SI-NEXT: s_lshr_b32 s96, s77, 16
+; SI-NEXT: s_lshr_b32 s87, s16, 16
+; SI-NEXT: s_lshr_b32 s65, s17, 16
+; SI-NEXT: s_lshr_b32 s53, s80, 16
; SI-NEXT: s_lshr_b32 s51, s70, 16
-; SI-NEXT: s_lshr_b32 s48, s71, 16
; SI-NEXT: s_lshr_b32 s49, s68, 16
-; SI-NEXT: s_lshr_b32 s86, s45, 16
; SI-NEXT: v_readfirstlane_b32 s4, v18
-; SI-NEXT: v_writelane_b32 v33, s59, 23
-; SI-NEXT: s_mov_b32 s38, s29
+; SI-NEXT: v_writelane_b32 v33, s63, 9
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v33, s60, 24
-; SI-NEXT: v_writelane_b32 v33, s61, 25
+; SI-NEXT: v_writelane_b32 v33, s72, 10
+; SI-NEXT: v_writelane_b32 v33, s73, 11
; SI-NEXT: s_cbranch_scc0 .LBB111_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_readlane_b32 s5, v33, 8
-; SI-NEXT: v_readlane_b32 s7, v33, 9
-; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_lshl_b32 s4, s5, 16
+; SI-NEXT: s_and_b32 s5, s39, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s84, 16
; SI-NEXT: s_or_b32 s43, s5, s7
-; SI-NEXT: v_readlane_b32 s5, v33, 6
-; SI-NEXT: v_readlane_b32 s7, v33, 7
-; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_and_b32 s5, s90, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s91, 16
; SI-NEXT: s_or_b32 s41, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v33, 5
; SI-NEXT: s_and_b32 s5, s21, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_lshl_b32 s7, s93, 16
; SI-NEXT: s_or_b32 s15, s5, s7
-; SI-NEXT: v_readlane_b32 s5, v33, 3
-; SI-NEXT: v_readlane_b32 s7, v33, 4
-; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_and_b32 s5, s23, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s95, 16
; SI-NEXT: s_or_b32 s13, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v33, 1
; SI-NEXT: s_and_b32 s5, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_lshl_b32 s7, s31, 16
; SI-NEXT: s_or_b32 s11, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v33, 0
-; SI-NEXT: s_and_b32 s5, s39, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
-; SI-NEXT: v_readlane_b32 s4, v33, 10
+; SI-NEXT: s_and_b32 s5, s27, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s35, 16
; SI-NEXT: s_or_b32 s9, s5, s7
-; SI-NEXT: s_and_b32 s5, s38, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s93, 16
-; SI-NEXT: s_lshl_b32 s42, s4, 16
-; SI-NEXT: v_readlane_b32 s4, v33, 2
+; SI-NEXT: s_and_b32 s5, s29, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s37, 16
; SI-NEXT: s_or_b32 s7, s5, s7
; SI-NEXT: s_and_b32 s5, s68, 0xffff
; SI-NEXT: s_lshl_b32 s44, s49, 16
-; SI-NEXT: v_writelane_b32 v33, s82, 34
; SI-NEXT: s_or_b32 s5, s5, s44
; SI-NEXT: s_and_b32 s56, s70, 0xffff
; SI-NEXT: s_lshl_b32 s44, s51, 16
-; SI-NEXT: v_writelane_b32 v33, s68, 35
; SI-NEXT: s_or_b32 vcc_hi, s56, s44
-; SI-NEXT: s_and_b32 s56, s83, 0xffff
+; SI-NEXT: s_and_b32 s56, s80, 0xffff
; SI-NEXT: s_lshl_b32 s44, s53, 16
-; SI-NEXT: v_writelane_b32 v33, s38, 36
-; SI-NEXT: s_mov_b32 s82, s39
+; SI-NEXT: s_lshl_b32 s42, s92, 16
+; SI-NEXT: s_lshl_b32 s10, s83, 16
+; SI-NEXT: s_mov_b32 s83, s92
+; SI-NEXT: s_mov_b32 s92, s90
+; SI-NEXT: s_mov_b32 s90, s39
; SI-NEXT: s_or_b32 s39, s56, s44
; SI-NEXT: s_and_b32 s56, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s95, 16
-; SI-NEXT: v_writelane_b32 v33, s76, 37
-; SI-NEXT: s_lshl_b32 s8, s84, 16
-; SI-NEXT: v_writelane_b32 v33, s84, 38
-; SI-NEXT: s_mov_b32 s84, s49
+; SI-NEXT: s_lshl_b32 s44, s65, 16
; SI-NEXT: s_or_b32 s49, s56, s44
-; SI-NEXT: s_and_b32 s56, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s55, 16
-; SI-NEXT: s_lshl_b32 s6, s85, 16
-; SI-NEXT: v_writelane_b32 v33, s92, 39
-; SI-NEXT: s_mov_b32 s92, s77
-; SI-NEXT: s_mov_b32 s77, s70
-; SI-NEXT: s_mov_b32 s70, s85
-; SI-NEXT: s_mov_b32 s85, s51
+; SI-NEXT: s_and_b32 s56, s16, 0xffff
+; SI-NEXT: s_lshl_b32 s44, s87, 16
+; SI-NEXT: s_lshl_b32 s8, s85, 16
+; SI-NEXT: s_mov_b32 s85, s21
; SI-NEXT: s_or_b32 s51, s56, s44
-; SI-NEXT: s_and_b32 s56, s98, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s65, 16
-; SI-NEXT: s_mov_b32 s87, s21
-; SI-NEXT: s_mov_b32 s94, s53
-; SI-NEXT: s_or_b32 s53, s56, s44
-; SI-NEXT: s_and_b32 s21, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s30, 16
-; SI-NEXT: s_mov_b32 s97, s55
+; SI-NEXT: s_and_b32 s21, s77, 0xffff
+; SI-NEXT: s_lshl_b32 s44, s96, 16
+; SI-NEXT: s_or_b32 s53, s21, s44
+; SI-NEXT: s_and_b32 s21, s79, 0xffff
+; SI-NEXT: s_lshl_b32 s44, s97, 16
+; SI-NEXT: s_lshl_b32 s40, s55, 16
+; SI-NEXT: s_lshl_b32 s14, s94, 16
+; SI-NEXT: s_lshl_b32 s6, s86, 16
+; SI-NEXT: s_mov_b32 s86, s94
+; SI-NEXT: s_mov_b32 s94, s55
; SI-NEXT: s_or_b32 s55, s21, s44
-; SI-NEXT: s_and_b32 s21, s58, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s67, 16
-; SI-NEXT: s_lshl_b32 s54, s20, 16
-; SI-NEXT: s_mov_b32 s20, s98
-; SI-NEXT: s_mov_b32 s98, s30
-; SI-NEXT: s_mov_b32 s30, s65
+; SI-NEXT: s_and_b32 s21, s19, 0xffff
+; SI-NEXT: s_lshl_b32 s44, s98, 16
; SI-NEXT: s_or_b32 s65, s21, s44
-; SI-NEXT: s_and_b32 s21, s60, 0xffff
+; SI-NEXT: s_and_b32 s21, s89, 0xffff
; SI-NEXT: s_lshl_b32 s44, s99, 16
-; SI-NEXT: s_lshl_b32 s40, s34, 16
-; SI-NEXT: s_lshl_b32 s14, s36, 16
-; SI-NEXT: s_lshl_b32 s12, s91, 16
-; SI-NEXT: s_lshl_b32 s10, s4, 16
-; SI-NEXT: s_lshl_b32 s4, s86, 16
-; SI-NEXT: s_mov_b32 s80, s86
-; SI-NEXT: s_mov_b32 s86, s91
-; SI-NEXT: s_mov_b32 s91, s36
-; SI-NEXT: s_mov_b32 s36, s34
-; SI-NEXT: s_mov_b32 s34, s99
-; SI-NEXT: s_mov_b32 s99, s67
+; SI-NEXT: s_lshl_b32 s12, s67, 16
; SI-NEXT: s_or_b32 s67, s21, s44
; SI-NEXT: s_and_b32 s21, s46, 0xffff
+; SI-NEXT: s_lshl_b32 s52, s62, 16
+; SI-NEXT: s_lshl_b32 s54, s63, 16
; SI-NEXT: s_or_b32 s62, s21, s42
+; SI-NEXT: s_mov_b32 s63, s43
+; SI-NEXT: s_lshr_b64 s[42:43], s[42:43], 16
+; SI-NEXT: v_writelane_b32 v33, s42, 12
; SI-NEXT: s_and_b32 s21, s47, 0xffff
+; SI-NEXT: v_writelane_b32 v33, s43, 13
; SI-NEXT: s_or_b32 s74, s21, s40
+; SI-NEXT: s_mov_b32 s75, s41
+; SI-NEXT: s_lshr_b64 s[40:41], s[40:41], 16
+; SI-NEXT: v_writelane_b32 v33, s40, 14
; SI-NEXT: s_and_b32 s21, s57, 0xffff
-; SI-NEXT: v_writelane_b32 v33, s23, 40
+; SI-NEXT: s_lshl_b32 s64, s72, 16
+; SI-NEXT: s_lshl_b32 s66, s73, 16
+; SI-NEXT: v_writelane_b32 v33, s41, 15
; SI-NEXT: s_or_b32 s72, s21, s14
-; SI-NEXT: s_lshr_b64 s[22:23], s[14:15], 16
-; SI-NEXT: s_and_b32 s14, s31, 0xffff
-; SI-NEXT: s_mov_b32 s68, s25
+; SI-NEXT: s_mov_b32 s73, s15
+; SI-NEXT: s_lshr_b64 s[14:15], s[14:15], 16
+; SI-NEXT: v_writelane_b32 v33, s14, 16
+; SI-NEXT: v_writelane_b32 v33, s15, 17
+; SI-NEXT: s_and_b32 s14, s22, 0xffff
+; SI-NEXT: s_lshl_b32 s48, s60, 16
+; SI-NEXT: s_lshl_b32 s50, s61, 16
; SI-NEXT: s_or_b32 s60, s14, s12
-; SI-NEXT: s_lshr_b64 s[24:25], s[12:13], 16
-; SI-NEXT: s_and_b32 s12, s35, 0xffff
-; SI-NEXT: s_mov_b32 s89, s27
+; SI-NEXT: s_mov_b32 s61, s13
+; SI-NEXT: s_lshr_b64 s[12:13], s[12:13], 16
+; SI-NEXT: v_writelane_b32 v33, s12, 18
+; SI-NEXT: v_writelane_b32 v33, s13, 19
+; SI-NEXT: s_and_b32 s12, s24, 0xffff
+; SI-NEXT: s_lshl_b32 vcc_lo, s58, 16
+; SI-NEXT: s_lshl_b32 s38, s59, 16
; SI-NEXT: s_or_b32 s58, s12, s10
-; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 16
-; SI-NEXT: s_and_b32 s10, s69, 0xffff
+; SI-NEXT: s_mov_b32 s59, s11
+; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 16
+; SI-NEXT: v_writelane_b32 v33, s10, 20
+; SI-NEXT: v_writelane_b32 v33, s11, 21
+; SI-NEXT: s_and_b32 s10, s26, 0xffff
; SI-NEXT: s_or_b32 s56, s10, s8
-; SI-NEXT: s_lshr_b64 s[28:29], s[8:9], 16
-; SI-NEXT: s_and_b32 s8, s78, 0xffff
+; SI-NEXT: s_mov_b32 s57, s9
+; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
+; SI-NEXT: v_writelane_b32 v33, s8, 22
+; SI-NEXT: v_writelane_b32 v33, s9, 23
+; SI-NEXT: s_and_b32 s8, s28, 0xffff
; SI-NEXT: s_or_b32 s46, s8, s6
-; SI-NEXT: s_lshr_b64 s[78:79], s[6:7], 16
-; SI-NEXT: s_and_b32 s6, s45, 0xffff
-; SI-NEXT: v_writelane_b32 v33, s17, 41
+; SI-NEXT: s_mov_b32 s8, s31
+; SI-NEXT: s_lshr_b64 s[30:31], s[6:7], 16
+; SI-NEXT: s_and_b32 s6, s69, 0xffff
; SI-NEXT: s_or_b32 s44, s6, s4
-; SI-NEXT: s_mov_b32 s45, s5
-; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
-; SI-NEXT: s_lshl_b32 vcc_lo, s48, 16
-; SI-NEXT: v_writelane_b32 v33, s4, 26
-; SI-NEXT: s_mov_b32 s47, s7
-; SI-NEXT: v_writelane_b32 v33, s5, 27
+; SI-NEXT: s_mov_b32 s6, s35
+; SI-NEXT: s_lshr_b64 s[34:35], s[4:5], 16
; SI-NEXT: s_and_b32 s4, s71, 0xffff
-; SI-NEXT: s_lshr_b64 s[6:7], vcc, 16
-; SI-NEXT: s_lshl_b32 s38, s37, 16
-; SI-NEXT: s_lshl_b32 s52, s18, 16
-; SI-NEXT: s_lshr_b64 s[18:19], s[42:43], 16
; SI-NEXT: s_or_b32 s42, s4, vcc_lo
-; SI-NEXT: v_writelane_b32 v33, s6, 28
+; SI-NEXT: s_mov_b32 s4, s37
+; SI-NEXT: s_lshr_b64 s[36:37], vcc, 16
+; SI-NEXT: s_mov_b32 s37, s4
; SI-NEXT: s_and_b32 s4, s81, 0xffff
-; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 16
-; SI-NEXT: v_writelane_b32 v33, s7, 29
; SI-NEXT: s_or_b32 s40, s4, s38
-; SI-NEXT: s_lshr_b64 s[4:5], s[38:39], 16
-; SI-NEXT: v_writelane_b32 v33, s4, 30
-; SI-NEXT: v_writelane_b32 v33, s5, 31
-; SI-NEXT: s_mov_b32 s75, s41
-; SI-NEXT: s_mov_b32 s41, s39
-; SI-NEXT: s_mov_b32 s39, s82
-; SI-NEXT: v_readlane_b32 s82, v33, 34
-; SI-NEXT: s_mov_b32 s76, s48
-; SI-NEXT: s_lshl_b32 s48, s96, 16
; SI-NEXT: s_and_b32 s4, s82, 0xffff
; SI-NEXT: s_or_b32 s14, s4, s48
-; SI-NEXT: s_lshr_b64 s[4:5], s[48:49], 16
-; SI-NEXT: s_mov_b32 s25, s68
-; SI-NEXT: v_readlane_b32 s38, v33, 36
-; SI-NEXT: v_readlane_b32 s68, v33, 35
-; SI-NEXT: v_writelane_b32 v33, s4, 32
-; SI-NEXT: v_writelane_b32 v33, s5, 33
-; SI-NEXT: s_mov_b32 s48, s76
-; SI-NEXT: v_readlane_b32 s76, v33, 37
-; SI-NEXT: s_lshl_b32 s50, s90, 16
; SI-NEXT: s_and_b32 s4, s76, 0xffff
-; SI-NEXT: s_lshl_b32 s66, s61, 16
-; SI-NEXT: s_mov_b32 s61, s13
; SI-NEXT: s_or_b32 s12, s4, s50
-; SI-NEXT: s_mov_b32 s13, s51
-; SI-NEXT: s_lshr_b64 s[50:51], s[50:51], 16
-; SI-NEXT: s_mov_b32 s51, s85
-; SI-NEXT: s_mov_b32 s85, s70
-; SI-NEXT: s_mov_b32 s70, s77
-; SI-NEXT: s_mov_b32 s77, s92
-; SI-NEXT: v_readlane_b32 s23, v33, 40
-; SI-NEXT: s_and_b32 s4, s77, 0xffff
+; SI-NEXT: s_and_b32 s4, s78, 0xffff
; SI-NEXT: s_or_b32 s10, s4, s52
-; SI-NEXT: s_and_b32 s4, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s64, s59, 16
-; SI-NEXT: v_readlane_b32 s92, v33, 39
+; SI-NEXT: s_and_b32 s4, s18, 0xffff
+; SI-NEXT: s_mov_b32 s31, s8
; SI-NEXT: s_or_b32 s8, s4, s54
; SI-NEXT: s_and_b32 s4, s88, 0xffff
+; SI-NEXT: s_mov_b32 s35, s6
; SI-NEXT: s_or_b32 s6, s4, s64
-; SI-NEXT: s_and_b32 s4, s92, 0xffff
-; SI-NEXT: s_mov_b32 s59, s11
-; SI-NEXT: s_mov_b32 s57, s9
+; SI-NEXT: s_and_b32 s4, s20, 0xffff
+; SI-NEXT: s_mov_b32 s47, s7
+; SI-NEXT: s_mov_b32 s45, s5
+; SI-NEXT: s_mov_b32 s41, s39
+; SI-NEXT: s_lshr_b64 s[38:39], s[38:39], 16
+; SI-NEXT: s_mov_b32 s15, s49
+; SI-NEXT: s_lshr_b64 s[48:49], s[48:49], 16
+; SI-NEXT: s_mov_b32 s13, s51
+; SI-NEXT: s_lshr_b64 s[50:51], s[50:51], 16
; SI-NEXT: s_mov_b32 s11, s53
; SI-NEXT: s_lshr_b64 s[52:53], s[52:53], 16
; SI-NEXT: s_mov_b32 s9, s55
@@ -229314,364 +229434,341 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; SI-NEXT: s_or_b32 s4, s4, s66
; SI-NEXT: s_mov_b32 s5, s67
; SI-NEXT: s_lshr_b64 s[66:67], s[66:67], 16
-; SI-NEXT: s_mov_b32 s63, s43
-; SI-NEXT: s_mov_b32 s73, s15
; SI-NEXT: s_mov_b32 s43, vcc_hi
-; SI-NEXT: s_mov_b32 s15, s49
-; SI-NEXT: s_mov_b32 s49, s84
-; SI-NEXT: v_readlane_b32 s84, v33, 38
-; SI-NEXT: s_mov_b32 s53, s94
-; SI-NEXT: s_mov_b32 s21, s87
-; SI-NEXT: v_readlane_b32 s17, v33, 41
-; SI-NEXT: s_mov_b32 s55, s97
-; SI-NEXT: s_mov_b32 s65, s30
-; SI-NEXT: s_mov_b32 s30, s98
-; SI-NEXT: s_mov_b32 s98, s20
-; SI-NEXT: s_mov_b32 s67, s99
-; SI-NEXT: s_mov_b32 s99, s34
-; SI-NEXT: s_mov_b32 s34, s36
-; SI-NEXT: s_mov_b32 s36, s91
-; SI-NEXT: s_mov_b32 s91, s86
-; SI-NEXT: s_mov_b32 s86, s80
-; SI-NEXT: s_mov_b32 s27, s89
-; SI-NEXT: s_mov_b32 s20, s16
+; SI-NEXT: s_mov_b32 s39, s90
+; SI-NEXT: s_mov_b32 s90, s92
+; SI-NEXT: s_mov_b32 s92, s83
+; SI-NEXT: s_lshr_b32 s83, s24, 16
+; SI-NEXT: s_lshr_b32 s49, s68, 16
+; SI-NEXT: s_lshr_b32 s51, s70, 16
+; SI-NEXT: s_mov_b32 s21, s85
+; SI-NEXT: s_lshr_b32 s85, s26, 16
+; SI-NEXT: s_lshr_b32 s53, s80, 16
+; SI-NEXT: s_mov_b32 s55, s94
+; SI-NEXT: s_mov_b32 s94, s86
+; SI-NEXT: s_lshr_b32 s86, s28, 16
+; SI-NEXT: s_lshr_b32 s65, s17, 16
+; SI-NEXT: s_lshr_b32 s67, s22, 16
; SI-NEXT: s_cbranch_execnz .LBB111_3
; SI-NEXT: .LBB111_2: ; %cmp.true
-; SI-NEXT: s_add_i32 s20, s92, 3
-; SI-NEXT: v_readlane_b32 s5, v33, 25
+; SI-NEXT: s_add_i32 s20, s20, 3
+; SI-NEXT: v_readlane_b32 s5, v33, 11
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s5, 16
+; SI-NEXT: s_add_i32 s89, s89, 3
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: v_readlane_b32 s5, v33, 24
-; SI-NEXT: s_add_i32 s89, s5, 3
; SI-NEXT: s_and_b32 s5, s89, 0xffff
; SI-NEXT: s_lshl_b32 s6, s99, 16
; SI-NEXT: s_add_i32 s88, s88, 3
-; SI-NEXT: v_readlane_b32 s7, v33, 23
+; SI-NEXT: v_readlane_b32 s7, v33, 10
; SI-NEXT: s_or_b32 s5, s6, s5
; SI-NEXT: s_and_b32 s6, s88, 0xffff
; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_or_b32 s6, s7, s6
-; SI-NEXT: v_readlane_b32 s7, v33, 22
-; SI-NEXT: s_add_i32 s19, s7, 3
; SI-NEXT: s_and_b32 s7, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s8, s67, 16
-; SI-NEXT: s_add_i32 s18, s23, 3
-; SI-NEXT: v_readlane_b32 s9, v33, 21
+; SI-NEXT: s_lshl_b32 s8, s98, 16
+; SI-NEXT: s_add_i32 s18, s18, 3
+; SI-NEXT: v_readlane_b32 s9, v33, 9
; SI-NEXT: s_or_b32 s7, s8, s7
; SI-NEXT: s_and_b32 s8, s18, 0xffff
; SI-NEXT: s_lshl_b32 s9, s9, 16
+; SI-NEXT: s_add_i32 s79, s79, 3
; SI-NEXT: s_or_b32 s8, s9, s8
-; SI-NEXT: v_readlane_b32 s9, v33, 20
-; SI-NEXT: s_add_i32 s79, s9, 3
; SI-NEXT: s_and_b32 s9, s79, 0xffff
-; SI-NEXT: s_lshl_b32 s10, s30, 16
-; SI-NEXT: s_add_i32 s78, s77, 3
-; SI-NEXT: v_readlane_b32 s11, v33, 19
+; SI-NEXT: s_lshl_b32 s10, s97, 16
+; SI-NEXT: s_add_i32 s78, s78, 3
+; SI-NEXT: v_readlane_b32 s11, v33, 8
; SI-NEXT: s_or_b32 s9, s10, s9
; SI-NEXT: s_and_b32 s10, s78, 0xffff
; SI-NEXT: s_lshl_b32 s11, s11, 16
-; SI-NEXT: s_add_i32 s77, s98, 3
+; SI-NEXT: s_add_i32 s77, s77, 3
; SI-NEXT: s_or_b32 s10, s11, s10
; SI-NEXT: s_and_b32 s11, s77, 0xffff
-; SI-NEXT: s_lshl_b32 s12, s65, 16
+; SI-NEXT: s_lshl_b32 s12, s96, 16
; SI-NEXT: s_add_i32 s76, s76, 3
+; SI-NEXT: v_readlane_b32 s13, v33, 7
; SI-NEXT: s_or_b32 s11, s12, s11
; SI-NEXT: s_and_b32 s12, s76, 0xffff
-; SI-NEXT: s_lshl_b32 s13, s90, 16
-; SI-NEXT: s_add_i32 s16, s27, 3
+; SI-NEXT: s_lshl_b32 s13, s13, 16
+; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_or_b32 s12, s13, s12
; SI-NEXT: s_and_b32 s13, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s14, s55, 16
+; SI-NEXT: s_lshl_b32 s14, s87, 16
; SI-NEXT: s_add_i32 s82, s82, 3
+; SI-NEXT: v_readlane_b32 s15, v33, 6
; SI-NEXT: s_or_b32 s13, s14, s13
; SI-NEXT: s_and_b32 s14, s82, 0xffff
-; SI-NEXT: s_lshl_b32 s15, s96, 16
+; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_or_b32 s14, s15, s14
; SI-NEXT: s_and_b32 s15, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s16, s95, 16
+; SI-NEXT: s_lshl_b32 s16, s65, 16
; SI-NEXT: s_add_i32 s81, s81, 3
+; SI-NEXT: v_readlane_b32 s17, v33, 5
; SI-NEXT: s_or_b32 s15, s16, s15
; SI-NEXT: s_and_b32 s16, s81, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s37, 16
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s80, s83, 3
+; SI-NEXT: s_add_i32 s80, s80, 3
; SI-NEXT: s_add_i32 s40, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s80, 0xffff
; SI-NEXT: s_lshl_b32 s17, s53, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s71, s71, 3
+; SI-NEXT: v_readlane_b32 s17, v33, 4
; SI-NEXT: s_add_i32 s41, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s71, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s48, 16
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s70, s70, 3
; SI-NEXT: s_add_i32 s42, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s70, 0xffff
; SI-NEXT: s_lshl_b32 s17, s51, 16
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s69, s69, 3
+; SI-NEXT: v_readlane_b32 s17, v33, 3
; SI-NEXT: s_add_i32 s43, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 18
-; SI-NEXT: s_add_i32 s69, s16, 3
; SI-NEXT: s_and_b32 s16, s69, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s86, 16
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s68, s68, 3
; SI-NEXT: s_add_i32 s44, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s68, 0xffff
; SI-NEXT: s_lshl_b32 s17, s49, 16
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s45, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 17
-; SI-NEXT: s_add_i32 s28, s16, 3
; SI-NEXT: s_and_b32 s16, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s85, 16
+; SI-NEXT: s_lshl_b32 s17, s86, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s29, s38, 3
+; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s46, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s93, 16
+; SI-NEXT: s_lshl_b32 s17, s37, 16
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_add_i32 s47, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 16
-; SI-NEXT: s_add_i32 s26, s16, 3
; SI-NEXT: s_and_b32 s16, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s84, 16
+; SI-NEXT: s_lshl_b32 s17, s85, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s27, s39, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 0
+; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s56, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s35, 16
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s57, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 15
-; SI-NEXT: s_add_i32 s24, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 2
; SI-NEXT: s_and_b32 s16, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s83, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s25, s25, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 1
; SI-NEXT: s_add_i32 s58, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s31, 16
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s59, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 14
-; SI-NEXT: s_add_i32 s22, s16, 3
; SI-NEXT: s_and_b32 s16, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s91, 16
+; SI-NEXT: s_lshl_b32 s17, s67, 16
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s60, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 3
-; SI-NEXT: s_add_i32 s23, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 4
; SI-NEXT: s_and_b32 s16, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s95, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s61, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 13
+; SI-NEXT: v_readlane_b32 s16, v33, 2
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s36, 16
+; SI-NEXT: s_lshl_b32 s17, s94, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s72, s16, 0x30000
; SI-NEXT: s_add_i32 s16, s21, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 5
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s93, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s73, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 12
+; SI-NEXT: v_readlane_b32 s16, v33, 1
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s34, 16
+; SI-NEXT: s_lshl_b32 s17, s55, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s74, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 6
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 7
+; SI-NEXT: s_add_i32 s16, s90, 3
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s91, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s75, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 11
+; SI-NEXT: v_readlane_b32 s16, v33, 0
; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 10
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s92, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s62, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v33, 8
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v33, 9
+; SI-NEXT: s_add_i32 s16, s39, 3
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s84, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s63, s16, 0x30000
-; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 16
-; SI-NEXT: v_writelane_b32 v33, s16, 26
-; SI-NEXT: v_writelane_b32 v33, s17, 27
-; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
-; SI-NEXT: v_writelane_b32 v33, s16, 28
-; SI-NEXT: v_writelane_b32 v33, s17, 29
-; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 16
-; SI-NEXT: s_add_i32 s14, s14, 0x30000
-; SI-NEXT: s_add_i32 s15, s15, 0x30000
-; SI-NEXT: v_writelane_b32 v33, s16, 30
-; SI-NEXT: v_writelane_b32 v33, s17, 31
-; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 16
-; SI-NEXT: v_writelane_b32 v33, s16, 32
-; SI-NEXT: v_writelane_b32 v33, s17, 33
-; SI-NEXT: s_lshr_b32 s16, s63, 16
-; SI-NEXT: v_writelane_b32 v33, s16, 9
-; SI-NEXT: s_lshr_b32 s16, s75, 16
-; SI-NEXT: v_writelane_b32 v33, s16, 7
-; SI-NEXT: s_lshr_b32 s16, s73, 16
-; SI-NEXT: s_add_i32 s4, s4, 0x30000
-; SI-NEXT: s_add_i32 s5, s5, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 12
+; SI-NEXT: v_writelane_b32 v33, s17, 13
+; SI-NEXT: s_lshr_b64 s[16:17], s[74:75], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 14
+; SI-NEXT: v_writelane_b32 v33, s17, 15
+; SI-NEXT: s_lshr_b64 s[16:17], s[72:73], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 16
+; SI-NEXT: v_writelane_b32 v33, s17, 17
+; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 18
+; SI-NEXT: v_writelane_b32 v33, s17, 19
+; SI-NEXT: s_lshr_b64 s[16:17], s[58:59], 16
; SI-NEXT: s_add_i32 s6, s6, 0x30000
; SI-NEXT: s_add_i32 s7, s7, 0x30000
-; SI-NEXT: s_add_i32 s8, s8, 0x30000
-; SI-NEXT: s_add_i32 s9, s9, 0x30000
; SI-NEXT: s_add_i32 s10, s10, 0x30000
; SI-NEXT: s_add_i32 s11, s11, 0x30000
; SI-NEXT: s_add_i32 s12, s12, 0x30000
; SI-NEXT: s_add_i32 s13, s13, 0x30000
-; SI-NEXT: v_writelane_b32 v33, s16, 5
-; SI-NEXT: s_lshr_b32 s16, s61, 16
+; SI-NEXT: s_add_i32 s14, s14, 0x30000
+; SI-NEXT: s_add_i32 s15, s15, 0x30000
+; SI-NEXT: v_writelane_b32 v33, s16, 20
+; SI-NEXT: s_add_i32 s4, s4, 0x30000
+; SI-NEXT: s_add_i32 s5, s5, 0x30000
+; SI-NEXT: s_add_i32 s8, s8, 0x30000
+; SI-NEXT: s_add_i32 s9, s9, 0x30000
+; SI-NEXT: v_writelane_b32 v33, s17, 21
+; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 16
+; SI-NEXT: s_lshr_b64 s[30:31], s[46:47], 16
+; SI-NEXT: s_lshr_b64 s[34:35], s[44:45], 16
+; SI-NEXT: s_lshr_b64 s[36:37], s[42:43], 16
+; SI-NEXT: s_lshr_b64 s[48:49], s[14:15], 16
; SI-NEXT: s_lshr_b64 s[50:51], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[52:53], s[10:11], 16
-; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[64:65], s[6:7], 16
+; SI-NEXT: v_writelane_b32 v33, s16, 22
+; SI-NEXT: s_lshr_b64 s[38:39], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[66:67], s[4:5], 16
-; SI-NEXT: v_writelane_b32 v33, s16, 4
-; SI-NEXT: s_lshr_b32 s16, s59, 16
-; SI-NEXT: s_lshr_b64 s[18:19], s[62:63], 16
-; SI-NEXT: s_lshr_b64 s[20:21], s[74:75], 16
-; SI-NEXT: s_lshr_b64 s[22:23], s[72:73], 16
-; SI-NEXT: s_lshr_b64 s[24:25], s[60:61], 16
-; SI-NEXT: s_lshr_b64 s[26:27], s[58:59], 16
-; SI-NEXT: s_lshr_b64 s[28:29], s[56:57], 16
-; SI-NEXT: s_lshr_b64 s[78:79], s[46:47], 16
-; SI-NEXT: v_writelane_b32 v33, s16, 1
-; SI-NEXT: s_lshr_b32 s16, s57, 16
-; SI-NEXT: s_lshr_b32 s93, s47, 16
+; SI-NEXT: s_lshr_b32 s84, s63, 16
+; SI-NEXT: s_lshr_b32 s91, s75, 16
+; SI-NEXT: s_lshr_b32 s93, s73, 16
+; SI-NEXT: s_lshr_b32 s95, s61, 16
+; SI-NEXT: s_lshr_b32 s31, s59, 16
+; SI-NEXT: s_lshr_b32 s35, s57, 16
+; SI-NEXT: s_lshr_b32 s37, s47, 16
; SI-NEXT: s_lshr_b32 s49, s45, 16
; SI-NEXT: s_lshr_b32 s51, s43, 16
; SI-NEXT: s_lshr_b32 s53, s41, 16
-; SI-NEXT: s_lshr_b32 s95, s15, 16
-; SI-NEXT: s_lshr_b32 s55, s13, 16
-; SI-NEXT: s_lshr_b32 s65, s11, 16
-; SI-NEXT: s_lshr_b32 s30, s9, 16
-; SI-NEXT: s_lshr_b32 s67, s7, 16
+; SI-NEXT: s_lshr_b32 s65, s15, 16
+; SI-NEXT: s_lshr_b32 s87, s13, 16
+; SI-NEXT: s_lshr_b32 s96, s11, 16
+; SI-NEXT: s_lshr_b32 s97, s9, 16
+; SI-NEXT: s_lshr_b32 s98, s7, 16
; SI-NEXT: s_lshr_b32 s99, s5, 16
-; SI-NEXT: v_writelane_b32 v33, s16, 0
+; SI-NEXT: v_writelane_b32 v33, s17, 23
; SI-NEXT: .LBB111_3: ; %end
+; SI-NEXT: v_readlane_b32 s18, v33, 12
; SI-NEXT: s_and_b32 s16, s62, 0xffff
; SI-NEXT: s_lshl_b32 s17, s18, 16
-; SI-NEXT: v_readlane_b32 s18, v33, 9
+; SI-NEXT: v_readlane_b32 s19, v33, 13
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s63, 0xffff
-; SI-NEXT: s_lshl_b32 s18, s18, 16
+; SI-NEXT: s_lshl_b32 s18, s84, 16
+; SI-NEXT: v_readlane_b32 s20, v33, 14
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s18, s74, 0xffff
; SI-NEXT: s_lshl_b32 s19, s20, 16
-; SI-NEXT: v_readlane_b32 s20, v33, 7
+; SI-NEXT: v_readlane_b32 s21, v33, 15
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_and_b32 s19, s75, 0xffff
-; SI-NEXT: s_lshl_b32 s20, s20, 16
+; SI-NEXT: s_lshl_b32 s20, s91, 16
+; SI-NEXT: v_readlane_b32 s22, v33, 16
; SI-NEXT: s_or_b32 s19, s19, s20
; SI-NEXT: s_and_b32 s20, s72, 0xffff
; SI-NEXT: s_lshl_b32 s21, s22, 16
-; SI-NEXT: v_readlane_b32 s22, v33, 5
+; SI-NEXT: v_readlane_b32 s23, v33, 17
; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s21, s73, 0xffff
-; SI-NEXT: s_lshl_b32 s22, s22, 16
+; SI-NEXT: s_lshl_b32 s22, s93, 16
+; SI-NEXT: v_readlane_b32 s24, v33, 18
; SI-NEXT: s_or_b32 s21, s21, s22
; SI-NEXT: s_and_b32 s22, s60, 0xffff
; SI-NEXT: s_lshl_b32 s23, s24, 16
-; SI-NEXT: v_readlane_b32 s24, v33, 4
+; SI-NEXT: v_readlane_b32 s25, v33, 19
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_and_b32 s23, s61, 0xffff
-; SI-NEXT: s_lshl_b32 s24, s24, 16
+; SI-NEXT: s_lshl_b32 s24, s95, 16
+; SI-NEXT: v_readlane_b32 s26, v33, 20
; SI-NEXT: s_or_b32 s23, s23, s24
; SI-NEXT: s_and_b32 s24, s58, 0xffff
; SI-NEXT: s_lshl_b32 s25, s26, 16
-; SI-NEXT: v_readlane_b32 s26, v33, 1
+; SI-NEXT: v_readlane_b32 s27, v33, 21
; SI-NEXT: s_or_b32 s24, s24, s25
; SI-NEXT: s_and_b32 s25, s59, 0xffff
-; SI-NEXT: s_lshl_b32 s26, s26, 16
+; SI-NEXT: s_lshl_b32 s26, s31, 16
+; SI-NEXT: v_readlane_b32 s28, v33, 22
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s56, 0xffff
; SI-NEXT: s_lshl_b32 s27, s28, 16
-; SI-NEXT: v_readlane_b32 s28, v33, 0
+; SI-NEXT: v_readlane_b32 s29, v33, 23
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s57, 0xffff
-; SI-NEXT: s_lshl_b32 s28, s28, 16
+; SI-NEXT: s_lshl_b32 s28, s35, 16
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s46, 0xffff
-; SI-NEXT: s_lshl_b32 s29, s78, 16
+; SI-NEXT: s_lshl_b32 s29, s30, 16
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s29, s47, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s93, 16
+; SI-NEXT: s_lshl_b32 s46, s37, 16
; SI-NEXT: s_or_b32 s29, s29, s46
-; SI-NEXT: v_readlane_b32 s46, v33, 26
; SI-NEXT: s_and_b32 s44, s44, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s46, 16
-; SI-NEXT: v_readlane_b32 s47, v33, 27
+; SI-NEXT: s_lshl_b32 s46, s34, 16
; SI-NEXT: s_or_b32 s44, s44, s46
; SI-NEXT: s_and_b32 s45, s45, 0xffff
; SI-NEXT: s_lshl_b32 s46, s49, 16
; SI-NEXT: s_or_b32 s45, s45, s46
-; SI-NEXT: v_readlane_b32 s46, v33, 28
; SI-NEXT: s_and_b32 s42, s42, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s46, 16
-; SI-NEXT: v_readlane_b32 s47, v33, 29
+; SI-NEXT: s_lshl_b32 s46, s36, 16
; SI-NEXT: s_or_b32 s42, s42, s46
; SI-NEXT: s_and_b32 s43, s43, 0xffff
; SI-NEXT: s_lshl_b32 s46, s51, 16
; SI-NEXT: s_or_b32 s43, s43, s46
-; SI-NEXT: v_readlane_b32 s46, v33, 30
; SI-NEXT: s_and_b32 s40, s40, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s46, 16
-; SI-NEXT: v_readlane_b32 s47, v33, 31
+; SI-NEXT: s_lshl_b32 s46, s38, 16
; SI-NEXT: s_or_b32 s40, s40, s46
; SI-NEXT: s_and_b32 s41, s41, 0xffff
; SI-NEXT: s_lshl_b32 s46, s53, 16
; SI-NEXT: s_or_b32 s41, s41, s46
-; SI-NEXT: v_readlane_b32 s46, v33, 32
; SI-NEXT: s_and_b32 s14, s14, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s46, 16
+; SI-NEXT: s_lshl_b32 s46, s48, 16
; SI-NEXT: s_or_b32 s14, s14, s46
; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s95, 16
+; SI-NEXT: s_lshl_b32 s46, s65, 16
; SI-NEXT: s_or_b32 s15, s15, s46
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_lshl_b32 s46, s50, 16
; SI-NEXT: s_or_b32 s12, s12, s46
; SI-NEXT: s_and_b32 s13, s13, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s55, 16
+; SI-NEXT: s_lshl_b32 s46, s87, 16
; SI-NEXT: s_or_b32 s13, s13, s46
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_lshl_b32 s46, s52, 16
; SI-NEXT: s_or_b32 s10, s10, s46
; SI-NEXT: s_and_b32 s11, s11, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s65, 16
+; SI-NEXT: s_lshl_b32 s46, s96, 16
; SI-NEXT: s_or_b32 s11, s11, s46
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_lshl_b32 s46, s54, 16
; SI-NEXT: s_or_b32 s8, s8, s46
; SI-NEXT: s_and_b32 s9, s9, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s30, 16
+; SI-NEXT: s_lshl_b32 s46, s97, 16
; SI-NEXT: s_or_b32 s9, s9, s46
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_lshl_b32 s46, s64, 16
; SI-NEXT: s_or_b32 s6, s6, s46
; SI-NEXT: s_and_b32 s7, s7, 0xffff
-; SI-NEXT: s_lshl_b32 s46, s67, 16
+; SI-NEXT: s_lshl_b32 s46, s98, 16
; SI-NEXT: s_or_b32 s7, s7, s46
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s46, s66, 16
@@ -229679,7 +229776,6 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s46, s99, 16
; SI-NEXT: s_or_b32 s5, s5, s46
-; SI-NEXT: v_readlane_b32 s47, v33, 33
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
@@ -229756,27 +229852,25 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB111_4:
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v33, s4, 26
-; SI-NEXT: v_writelane_b32 v33, s5, 27
+; SI-NEXT: v_writelane_b32 v33, s4, 12
+; SI-NEXT: v_writelane_b32 v33, s5, 13
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr62
-; SI-NEXT: ; implicit-def: $sgpr18
; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: ; implicit-def: $sgpr20
; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr22
; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr24
; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr26
; SI-NEXT: ; implicit-def: $sgpr56
-; SI-NEXT: ; implicit-def: $sgpr28
; SI-NEXT: ; implicit-def: $sgpr46
-; SI-NEXT: ; implicit-def: $sgpr78
+; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: ; implicit-def: $sgpr44
+; SI-NEXT: ; implicit-def: $sgpr34
; SI-NEXT: ; implicit-def: $sgpr42
+; SI-NEXT: ; implicit-def: $sgpr36
; SI-NEXT: ; implicit-def: $sgpr40
+; SI-NEXT: ; implicit-def: $sgpr38
; SI-NEXT: ; implicit-def: $sgpr14
+; SI-NEXT: ; implicit-def: $sgpr48
; SI-NEXT: ; implicit-def: $sgpr12
; SI-NEXT: ; implicit-def: $sgpr50
; SI-NEXT: ; implicit-def: $sgpr10
@@ -229786,14 +229880,20 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr64
; SI-NEXT: ; implicit-def: $sgpr66
-; SI-NEXT: v_writelane_b32 v33, s4, 28
-; SI-NEXT: v_writelane_b32 v33, s5, 29
+; SI-NEXT: v_writelane_b32 v33, s4, 14
+; SI-NEXT: v_writelane_b32 v33, s5, 15
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v33, s4, 16
+; SI-NEXT: v_writelane_b32 v33, s5, 17
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: v_writelane_b32 v33, s4, 18
+; SI-NEXT: v_writelane_b32 v33, s5, 19
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v33, s4, 30
-; SI-NEXT: v_writelane_b32 v33, s5, 31
+; SI-NEXT: v_writelane_b32 v33, s4, 20
+; SI-NEXT: v_writelane_b32 v33, s5, 21
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v33, s4, 32
-; SI-NEXT: v_writelane_b32 v33, s5, 33
+; SI-NEXT: v_writelane_b32 v33, s4, 22
+; SI-NEXT: v_writelane_b32 v33, s5, 23
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_branch .LBB111_2
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index 74626bd38f582..b49357bdaa590 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -78030,9 +78030,8 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v18, s30, 0
; SI-NEXT: v_writelane_b32 v18, s31, 1
; SI-NEXT: v_writelane_b32 v18, s34, 2
@@ -78069,71 +78068,54 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_writelane_b32 v18, s97, 33
; SI-NEXT: v_writelane_b32 v18, s98, 34
; SI-NEXT: v_readfirstlane_b32 s98, v2
-; SI-NEXT: v_readfirstlane_b32 s44, v1
+; SI-NEXT: v_readfirstlane_b32 s69, v1
; SI-NEXT: v_writelane_b32 v18, s99, 35
; SI-NEXT: s_lshr_b32 s96, s29, 16
; SI-NEXT: s_lshr_b32 s97, s28, 16
; SI-NEXT: s_lshr_b32 s86, s27, 16
; SI-NEXT: s_lshr_b32 s87, s26, 16
; SI-NEXT: s_lshr_b32 s84, s25, 16
-; SI-NEXT: s_lshr_b32 s85, s24, 16
+; SI-NEXT: s_lshr_b32 s39, s24, 16
; SI-NEXT: s_lshr_b32 s82, s23, 16
-; SI-NEXT: s_lshr_b32 s83, s22, 16
+; SI-NEXT: s_lshr_b32 s37, s22, 16
; SI-NEXT: s_lshr_b32 s80, s21, 16
-; SI-NEXT: s_lshr_b32 s81, s20, 16
+; SI-NEXT: s_lshr_b32 s35, s20, 16
; SI-NEXT: s_lshr_b32 s70, s19, 16
-; SI-NEXT: s_lshr_b32 s71, s18, 16
+; SI-NEXT: s_lshr_b32 s31, s18, 16
; SI-NEXT: s_lshr_b32 s68, s17, 16
-; SI-NEXT: s_lshr_b32 s69, s16, 16
+; SI-NEXT: s_lshr_b32 s95, s16, 16
; SI-NEXT: s_lshr_b32 s99, s98, 16
-; SI-NEXT: s_lshr_b32 s46, s44, 16
+; SI-NEXT: s_lshr_b32 s71, s69, 16
; SI-NEXT: v_readfirstlane_b32 s4, v3
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB105_3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s69, 16
+; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s17, 0xffff
; SI-NEXT: s_lshl_b32 s5, s68, 16
; SI-NEXT: s_or_b32 s43, s4, s5
-; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 24
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v19, s4, 4
-; SI-NEXT: v_writelane_b32 v19, s5, 5
-; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 16
-; SI-NEXT: v_writelane_b32 v19, s4, 2
-; SI-NEXT: v_writelane_b32 v19, s5, 3
-; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 8
-; SI-NEXT: v_writelane_b32 v19, s4, 0
-; SI-NEXT: v_writelane_b32 v19, s5, 1
; SI-NEXT: s_and_b32 s4, s18, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s71, 16
+; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s40, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
; SI-NEXT: s_lshl_b32 s5, s70, 16
; SI-NEXT: s_or_b32 s41, s4, s5
-; SI-NEXT: s_lshr_b64 s[4:5], s[40:41], 24
-; SI-NEXT: v_writelane_b32 v19, s4, 8
-; SI-NEXT: v_writelane_b32 v19, s5, 9
-; SI-NEXT: s_lshr_b64 s[4:5], s[40:41], 16
-; SI-NEXT: v_writelane_b32 v19, s4, 6
-; SI-NEXT: v_writelane_b32 v19, s5, 7
; SI-NEXT: s_and_b32 s4, s20, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s81, 16
+; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s14, s4, s5
; SI-NEXT: s_and_b32 s4, s21, 0xffff
; SI-NEXT: s_lshl_b32 s5, s80, 16
; SI-NEXT: s_or_b32 s15, s4, s5
; SI-NEXT: s_and_b32 s4, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s83, 16
+; SI-NEXT: s_lshl_b32 s5, s37, 16
; SI-NEXT: s_or_b32 s12, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, s82, 16
; SI-NEXT: s_or_b32 s13, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s85, 16
+; SI-NEXT: s_lshl_b32 s5, s39, 16
; SI-NEXT: s_or_b32 s10, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s84, 16
@@ -78149,12 +78131,29 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: s_or_b32 s6, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s96, 16
+; SI-NEXT: s_lshr_b64 s[44:45], s[42:43], 24
; SI-NEXT: s_or_b32 s7, s4, s5
-; SI-NEXT: s_and_b32 s4, s44, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s46, 16
+; SI-NEXT: s_and_b32 s4, s69, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s71, 16
; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: s_and_b32 s5, s98, 0xffff
; SI-NEXT: s_lshl_b32 s45, s99, 16
+; SI-NEXT: s_mov_b32 s94, s37
+; SI-NEXT: s_lshr_b64 s[36:37], s[6:7], 24
+; SI-NEXT: s_or_b32 s5, s5, s45
+; SI-NEXT: s_mov_b32 s37, s94
+; SI-NEXT: s_mov_b32 s94, s39
+; SI-NEXT: s_lshr_b64 s[38:39], s[6:7], 16
+; SI-NEXT: s_mov_b32 s39, s94
+; SI-NEXT: s_mov_b32 vcc_lo, s95
+; SI-NEXT: s_lshr_b64 s[94:95], s[4:5], 24
+; SI-NEXT: s_mov_b32 s95, vcc_lo
+; SI-NEXT: s_mov_b32 vcc_lo, s31
+; SI-NEXT: s_lshr_b64 s[30:31], s[4:5], 16
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 16
+; SI-NEXT: s_lshr_b64 s[58:59], s[42:43], 8
+; SI-NEXT: s_lshr_b64 s[56:57], s[40:41], 24
+; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 8
; SI-NEXT: s_lshr_b64 s[62:63], s[14:15], 24
; SI-NEXT: s_lshr_b64 s[72:73], s[14:15], 16
@@ -78163,7 +78162,9 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: s_lshr_b64 s[90:91], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[92:93], s[12:13], 8
; SI-NEXT: s_lshr_b64 s[88:89], s[10:11], 24
-; SI-NEXT: s_or_b32 s5, s5, s45
+; SI-NEXT: s_mov_b32 s31, vcc_lo
+; SI-NEXT: s_mov_b32 vcc_lo, s35
+; SI-NEXT: s_lshr_b64 s[34:35], s[4:5], 8
; SI-NEXT: s_lshr_b32 s75, s43, 8
; SI-NEXT: s_lshr_b32 s73, s41, 8
; SI-NEXT: s_lshr_b32 s63, s15, 8
@@ -78177,24 +78178,20 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: s_bfe_u32 s89, s80, 0x80008
; SI-NEXT: s_bfe_u32 s91, s82, 0x80008
; SI-NEXT: s_bfe_u32 s93, s84, 0x80008
-; SI-NEXT: s_bfe_u32 s56, s86, 0x80008
-; SI-NEXT: s_bfe_u32 s58, s96, 0x80008
-; SI-NEXT: s_bfe_u32 s60, s99, 0x80008
+; SI-NEXT: s_bfe_u32 s81, s86, 0x80008
+; SI-NEXT: s_bfe_u32 s83, s96, 0x80008
+; SI-NEXT: s_bfe_u32 s85, s99, 0x80008
; SI-NEXT: s_lshr_b64 s[64:65], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[66:67], s[10:11], 8
; SI-NEXT: s_lshr_b64 s[50:51], s[8:9], 24
; SI-NEXT: s_lshr_b64 s[52:53], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 8
-; SI-NEXT: s_lshr_b64 s[36:37], s[6:7], 24
-; SI-NEXT: s_lshr_b64 s[38:39], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[48:49], s[6:7], 8
-; SI-NEXT: s_lshr_b64 s[94:95], s[4:5], 24
-; SI-NEXT: s_lshr_b64 s[30:31], s[4:5], 16
-; SI-NEXT: s_lshr_b64 s[34:35], s[4:5], 8
+; SI-NEXT: s_mov_b32 s35, vcc_lo
; SI-NEXT: s_cbranch_execnz .LBB105_4
; SI-NEXT: .LBB105_2: ; %cmp.true
-; SI-NEXT: v_cvt_f32_f16_e32 v2, s44
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s46
+; SI-NEXT: v_cvt_f32_f16_e32 v2, s69
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s71
; SI-NEXT: v_cvt_f32_f16_e32 v3, s99
; SI-NEXT: v_cvt_f32_f16_e32 v10, s16
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
@@ -78246,7 +78243,7 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v4
; SI-NEXT: v_cvt_f32_f16_e32 v4, s27
; SI-NEXT: v_readfirstlane_b32 s9, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s85
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s39
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
@@ -78266,7 +78263,7 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v5
; SI-NEXT: v_cvt_f32_f16_e32 v5, s25
; SI-NEXT: v_readfirstlane_b32 s11, v6
-; SI-NEXT: v_cvt_f32_f16_e32 v6, s83
+; SI-NEXT: v_cvt_f32_f16_e32 v6, s37
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
@@ -78286,7 +78283,7 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v6
; SI-NEXT: v_cvt_f32_f16_e32 v6, s23
; SI-NEXT: v_readfirstlane_b32 s13, v7
-; SI-NEXT: v_cvt_f32_f16_e32 v7, s81
+; SI-NEXT: v_cvt_f32_f16_e32 v7, s35
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
@@ -78306,7 +78303,7 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v7
; SI-NEXT: v_cvt_f32_f16_e32 v7, s21
; SI-NEXT: v_readfirstlane_b32 s15, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s71
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s31
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
@@ -78326,7 +78323,7 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_readfirstlane_b32 s20, v7
; SI-NEXT: v_cvt_f32_f16_e32 v7, s19
; SI-NEXT: v_cvt_f16_f32_e32 v9, v8
-; SI-NEXT: v_cvt_f32_f16_e32 v8, s69
+; SI-NEXT: v_cvt_f32_f16_e32 v8, s95
; SI-NEXT: s_lshl_b32 s18, s18, 16
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
@@ -78353,14 +78350,14 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: s_lshl_b32 s16, s16, 16
; SI-NEXT: v_readfirstlane_b32 s17, v7
; SI-NEXT: s_or_b32 s43, s17, s16
+; SI-NEXT: s_lshr_b64 s[44:45], s[42:43], 24
+; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 16
+; SI-NEXT: s_lshr_b64 s[58:59], s[42:43], 8
+; SI-NEXT: s_lshr_b64 s[56:57], s[40:41], 24
+; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 8
; SI-NEXT: s_lshr_b64 s[62:63], s[14:15], 24
; SI-NEXT: s_lshr_b64 s[72:73], s[14:15], 16
-; SI-NEXT: s_lshr_b64 s[18:19], s[42:43], 24
-; SI-NEXT: s_lshr_b64 s[20:21], s[42:43], 16
-; SI-NEXT: s_lshr_b64 s[24:25], s[42:43], 8
-; SI-NEXT: s_lshr_b64 s[22:23], s[40:41], 24
-; SI-NEXT: s_lshr_b64 s[26:27], s[40:41], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[14:15], 8
; SI-NEXT: s_lshr_b64 s[78:79], s[12:13], 24
; SI-NEXT: s_lshr_b64 s[90:91], s[12:13], 16
@@ -78395,16 +78392,16 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_bfe_u32 v7, v1, 8, 8
; SI-NEXT: s_branch .LBB105_5
; SI-NEXT: .LBB105_3:
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v19, s4, 0
-; SI-NEXT: v_writelane_b32 v19, s5, 1
-; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr42
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr75
; SI-NEXT: ; implicit-def: $sgpr77
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr74
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr73
; SI-NEXT: ; implicit-def: $sgpr79
; SI-NEXT: ; implicit-def: $sgpr14
@@ -78419,11 +78416,11 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: ; implicit-def: $sgpr59
; SI-NEXT: ; implicit-def: $sgpr93
; SI-NEXT: ; implicit-def: $sgpr57
-; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr81
; SI-NEXT: ; implicit-def: $sgpr47
-; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr83
; SI-NEXT: ; implicit-def: $sgpr45
-; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr85
; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $sgpr78
@@ -78439,28 +78436,12 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: ; implicit-def: $sgpr48
; SI-NEXT: ; implicit-def: $sgpr38
; SI-NEXT: ; implicit-def: $sgpr36
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr34
; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: ; implicit-def: $sgpr94
-; SI-NEXT: v_writelane_b32 v19, s4, 2
-; SI-NEXT: v_writelane_b32 v19, s5, 3
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v19, s4, 4
-; SI-NEXT: v_writelane_b32 v19, s5, 5
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v19, s4, 6
-; SI-NEXT: v_writelane_b32 v19, s5, 7
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v19, s4, 8
-; SI-NEXT: v_writelane_b32 v19, s5, 9
-; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_branch .LBB105_2
; SI-NEXT: .LBB105_4:
-; SI-NEXT: v_readlane_b32 s18, v19, 4
-; SI-NEXT: v_readlane_b32 s20, v19, 2
-; SI-NEXT: v_readlane_b32 s22, v19, 8
-; SI-NEXT: v_readlane_b32 s24, v19, 0
-; SI-NEXT: v_readlane_b32 s26, v19, 6
; SI-NEXT: v_mov_b32_e32 v1, s99
; SI-NEXT: v_mov_b32_e32 v2, s96
; SI-NEXT: v_mov_b32_e32 v3, s86
@@ -78469,26 +78450,21 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_mov_b32_e32 v6, s80
; SI-NEXT: v_mov_b32_e32 v9, s70
; SI-NEXT: v_mov_b32_e32 v12, s68
-; SI-NEXT: v_mov_b32_e32 v7, s60
-; SI-NEXT: v_mov_b32_e32 v8, s58
-; SI-NEXT: v_mov_b32_e32 v10, s56
+; SI-NEXT: v_mov_b32_e32 v7, s85
+; SI-NEXT: v_mov_b32_e32 v8, s83
+; SI-NEXT: v_mov_b32_e32 v10, s81
; SI-NEXT: v_mov_b32_e32 v11, s93
; SI-NEXT: v_mov_b32_e32 v13, s91
; SI-NEXT: v_mov_b32_e32 v14, s89
; SI-NEXT: v_mov_b32_e32 v15, s79
; SI-NEXT: v_mov_b32_e32 v16, s77
-; SI-NEXT: v_readlane_b32 s19, v19, 5
-; SI-NEXT: v_readlane_b32 s21, v19, 3
-; SI-NEXT: v_readlane_b32 s23, v19, 9
-; SI-NEXT: v_readlane_b32 s25, v19, 1
-; SI-NEXT: v_readlane_b32 s27, v19, 7
; SI-NEXT: .LBB105_5: ; %end
; SI-NEXT: s_and_b32 s16, s42, 0xff
-; SI-NEXT: s_lshl_b32 s17, s24, 8
+; SI-NEXT: s_lshl_b32 s17, s58, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s20, 0xff
+; SI-NEXT: s_and_b32 s17, s46, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s18, 24
+; SI-NEXT: s_lshl_b32 s18, s44, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: s_or_b32 s16, s16, s17
@@ -78505,9 +78481,9 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: s_and_b32 s16, s40, 0xff
; SI-NEXT: s_lshl_b32 s17, s74, 8
; SI-NEXT: s_or_b32 s16, s16, s17
-; SI-NEXT: s_and_b32 s17, s26, 0xff
+; SI-NEXT: s_and_b32 s17, s60, 0xff
; SI-NEXT: s_lshl_b32 s17, s17, 16
-; SI-NEXT: s_lshl_b32 s18, s22, 24
+; SI-NEXT: s_lshl_b32 s18, s56, 24
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s17, s18, s17
; SI-NEXT: v_add_i32_e32 v16, vcc, 4, v0
@@ -78711,7 +78687,6 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_readlane_b32 s30, v18, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
index a24315e66392c..1cbc99ca1b667 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
@@ -6870,13 +6870,13 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: v_writelane_b32 v28, s85, 29
; VI-NEXT: v_writelane_b32 v28, s86, 30
; VI-NEXT: v_writelane_b32 v28, s87, 31
-; VI-NEXT: v_readfirstlane_b32 s86, v13
+; VI-NEXT: v_readfirstlane_b32 s87, v13
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: v_readfirstlane_b32 s9, v11
; VI-NEXT: v_readfirstlane_b32 s8, v10
-; VI-NEXT: v_readfirstlane_b32 s87, v9
-; VI-NEXT: v_readfirstlane_b32 s12, v8
-; VI-NEXT: v_readfirstlane_b32 s73, v7
+; VI-NEXT: v_readfirstlane_b32 s10, v9
+; VI-NEXT: v_readfirstlane_b32 s73, v8
+; VI-NEXT: v_readfirstlane_b32 s75, v7
; VI-NEXT: v_readfirstlane_b32 s77, v6
; VI-NEXT: v_readfirstlane_b32 s88, v5
; VI-NEXT: v_readfirstlane_b32 s91, v4
@@ -6892,19 +6892,19 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_lshr_b32 s80, s24, 16
; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_lshr_b32 s85, s22, 16
-; VI-NEXT: s_lshr_b32 s7, s21, 16
-; VI-NEXT: s_lshr_b32 s11, s20, 16
-; VI-NEXT: s_lshr_b32 s13, s19, 16
-; VI-NEXT: s_lshr_b32 s15, s18, 16
-; VI-NEXT: s_lshr_b32 s10, s17, 16
-; VI-NEXT: s_lshr_b32 s75, s16, 16
-; VI-NEXT: s_lshr_b32 s64, s86, 16
+; VI-NEXT: s_lshr_b32 s86, s21, 16
+; VI-NEXT: s_lshr_b32 s7, s20, 16
+; VI-NEXT: s_lshr_b32 s11, s19, 16
+; VI-NEXT: s_lshr_b32 s13, s18, 16
+; VI-NEXT: s_lshr_b32 s15, s17, 16
+; VI-NEXT: s_lshr_b32 s12, s16, 16
+; VI-NEXT: s_lshr_b32 s64, s87, 16
; VI-NEXT: s_lshr_b32 s65, s6, 16
; VI-NEXT: s_lshr_b32 s66, s9, 16
; VI-NEXT: s_lshr_b32 s14, s8, 16
-; VI-NEXT: s_lshr_b32 s72, s87, 16
-; VI-NEXT: s_lshr_b32 s74, s12, 16
-; VI-NEXT: s_lshr_b32 s76, s73, 16
+; VI-NEXT: s_lshr_b32 s72, s10, 16
+; VI-NEXT: s_lshr_b32 s74, s73, 16
+; VI-NEXT: s_lshr_b32 s76, s75, 16
; VI-NEXT: s_lshr_b32 s78, s77, 16
; VI-NEXT: s_lshr_b32 s89, s88, 16
; VI-NEXT: s_lshr_b32 s30, s91, 16
@@ -6914,25 +6914,27 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_lshr_b32 s83, s84, 16
; VI-NEXT: v_readfirstlane_b32 s4, v14
; VI-NEXT: s_cmp_lg_u32 s4, 0
+; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
+; VI-NEXT: v_writelane_b32 v29, s10, 0
; VI-NEXT: s_cbranch_scc0 .LBB15_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s10, 16
+; VI-NEXT: s_lshl_b32 s41, s15, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
; VI-NEXT: s_lshl_b32 s5, s85, 16
@@ -6979,13 +6981,13 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s56, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s73
+; VI-NEXT: s_and_b32 s4, 0xffff, s75
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s57, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s12
+; VI-NEXT: s_and_b32 s4, 0xffff, s73
; VI-NEXT: s_lshl_b32 s5, s74, 16
; VI-NEXT: s_or_b32 s58, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s87
+; VI-NEXT: s_and_b32 s4, 0xffff, s10
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
@@ -6997,39 +6999,39 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s62, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s86
+; VI-NEXT: s_and_b32 s4, 0xffff, s87
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB15_3
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s10, s10, 16
+; VI-NEXT: s_lshl_b32 s10, s15, 16
; VI-NEXT: s_or_b32 s5, s10, s5
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s36, s4, 0x30000
; VI-NEXT: s_add_i32 s37, s5, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s38, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s19, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s21, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s41, s4, 0x30000
@@ -7106,18 +7108,19 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, s77, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s75, s73, 3
+; VI-NEXT: s_add_i32 s75, s75, 3
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s75, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s73, s12, 3
+; VI-NEXT: s_add_i32 s73, s73, 3
; VI-NEXT: s_add_i32 s57, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s73, 0xffff
; VI-NEXT: s_lshl_b32 s5, s74, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s15, s87, 3
; VI-NEXT: s_add_i32 s58, s4, 0x30000
+; VI-NEXT: v_readlane_b32 s4, v29, 0
+; VI-NEXT: s_add_i32 s15, s4, 3
; VI-NEXT: s_and_b32 s4, s15, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -7136,7 +7139,7 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, s9, 0xffff
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s7, s86, 3
+; VI-NEXT: s_add_i32 s7, s87, 3
; VI-NEXT: s_add_i32 s62, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s7, 0xffff
; VI-NEXT: s_lshl_b32 s5, s64, 16
@@ -7210,24 +7213,8 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB15_4:
-; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b32 vcc_lo, s64
-; VI-NEXT: v_writelane_b32 v29, s75, 0
; VI-NEXT: s_mov_b32 vcc_hi, s65
-; VI-NEXT: s_mov_b32 s75, s73
-; VI-NEXT: s_mov_b32 s73, s12
-; VI-NEXT: v_writelane_b32 v29, s25, 1
-; VI-NEXT: s_mov_b32 s25, s91
-; VI-NEXT: s_mov_b32 s91, s26
-; VI-NEXT: s_mov_b32 s26, s27
-; VI-NEXT: s_mov_b32 s27, s88
-; VI-NEXT: s_mov_b32 s88, s28
-; VI-NEXT: s_mov_b32 s28, s77
-; VI-NEXT: s_mov_b32 s77, s29
-; VI-NEXT: s_mov_b32 s29, s15
-; VI-NEXT: s_mov_b32 s15, s87
-; VI-NEXT: s_mov_b32 s87, s85
-; VI-NEXT: s_mov_b32 s85, s82
; VI-NEXT: s_mov_b32 s82, s71
; VI-NEXT: s_mov_b32 s71, s68
; VI-NEXT: s_mov_b32 s68, s35
@@ -7242,15 +7229,12 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s74, s72
; VI-NEXT: s_mov_b32 s72, s14
; VI-NEXT: s_mov_b32 s14, s66
-; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s13
-; VI-NEXT: s_mov_b32 s13, s8
-; VI-NEXT: s_mov_b32 s8, s11
-; VI-NEXT: s_mov_b32 s11, s9
-; VI-NEXT: s_mov_b32 s9, s6
-; VI-NEXT: s_mov_b32 s6, s7
+; VI-NEXT: s_mov_b32 s13, s11
+; VI-NEXT: s_mov_b32 s11, s7
; VI-NEXT: s_mov_b32 s7, s86
-; VI-NEXT: s_mov_b32 s86, s83
+; VI-NEXT: s_mov_b32 s86, s85
+; VI-NEXT: s_mov_b32 s85, s83
; VI-NEXT: s_mov_b32 s83, s80
; VI-NEXT: s_mov_b32 s80, s70
; VI-NEXT: s_mov_b32 s70, s67
@@ -7258,15 +7242,12 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s67, s70
; VI-NEXT: s_mov_b32 s70, s80
; VI-NEXT: s_mov_b32 s80, s83
-; VI-NEXT: s_mov_b32 s83, s86
+; VI-NEXT: s_mov_b32 s83, s85
+; VI-NEXT: s_mov_b32 s85, s86
; VI-NEXT: s_mov_b32 s86, s7
-; VI-NEXT: s_mov_b32 s7, s6
-; VI-NEXT: s_mov_b32 s6, s9
-; VI-NEXT: s_mov_b32 s9, s11
-; VI-NEXT: s_mov_b32 s11, s8
-; VI-NEXT: s_mov_b32 s8, s13
+; VI-NEXT: s_mov_b32 s7, s11
+; VI-NEXT: s_mov_b32 s11, s13
; VI-NEXT: s_mov_b32 s13, s10
-; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s66, s14
; VI-NEXT: s_mov_b32 s14, s72
; VI-NEXT: s_mov_b32 s72, s74
@@ -7281,21 +7262,7 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s35, s68
; VI-NEXT: s_mov_b32 s68, s71
; VI-NEXT: s_mov_b32 s71, s82
-; VI-NEXT: s_mov_b32 s82, s85
-; VI-NEXT: s_mov_b32 s85, s87
-; VI-NEXT: s_mov_b32 s87, s15
-; VI-NEXT: s_mov_b32 s15, s29
-; VI-NEXT: s_mov_b32 s29, s77
-; VI-NEXT: s_mov_b32 s77, s28
-; VI-NEXT: s_mov_b32 s28, s88
-; VI-NEXT: s_mov_b32 s88, s27
-; VI-NEXT: s_mov_b32 s27, s26
-; VI-NEXT: s_mov_b32 s26, s91
-; VI-NEXT: s_mov_b32 s91, s25
-; VI-NEXT: v_readlane_b32 s25, v29, 1
-; VI-NEXT: s_mov_b32 s12, s73
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: v_readlane_b32 s75, v29, 0
+; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_mov_b32 s65, vcc_hi
; VI-NEXT: s_mov_b32 s64, vcc_lo
; VI-NEXT: s_branch .LBB15_2
@@ -11264,7 +11231,6 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s30, 0
; VI-NEXT: v_writelane_b32 v32, s31, 1
@@ -11295,14 +11261,9 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_writelane_b32 v32, s82, 26
; VI-NEXT: v_writelane_b32 v32, s83, 27
; VI-NEXT: v_writelane_b32 v32, s84, 28
+; VI-NEXT: v_readfirstlane_b32 s6, v13
; VI-NEXT: v_readfirstlane_b32 s8, v12
-; VI-NEXT: v_writelane_b32 v32, s85, 29
-; VI-NEXT: s_lshr_b32 s15, s8, 16
; VI-NEXT: v_readfirstlane_b32 s10, v11
-; VI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
-; VI-NEXT: v_writelane_b32 v32, s86, 30
-; VI-NEXT: v_readfirstlane_b32 s6, v13
-; VI-NEXT: s_lshr_b32 s61, s10, 16
; VI-NEXT: v_readfirstlane_b32 s12, v10
; VI-NEXT: v_readfirstlane_b32 s14, v9
; VI-NEXT: v_readfirstlane_b32 s72, v8
@@ -11314,113 +11275,127 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s69, v2
; VI-NEXT: v_readfirstlane_b32 s80, v1
; VI-NEXT: v_readfirstlane_b32 s83, v0
-; VI-NEXT: v_writelane_b32 v33, s15, 0
-; VI-NEXT: v_writelane_b32 v32, s87, 31
+; VI-NEXT: v_writelane_b32 v32, s85, 29
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s75, s28, 16
-; VI-NEXT: s_lshr_b32 s90, s27, 16
-; VI-NEXT: s_lshr_b32 s31, s26, 16
-; VI-NEXT: s_lshr_b32 s68, s25, 16
-; VI-NEXT: s_lshr_b32 s70, s24, 16
-; VI-NEXT: s_lshr_b32 s81, s23, 16
-; VI-NEXT: s_lshr_b32 s84, s22, 16
-; VI-NEXT: s_lshr_b32 s86, s21, 16
-; VI-NEXT: s_lshr_b32 s87, s20, 16
-; VI-NEXT: s_lshr_b32 s7, s19, 16
-; VI-NEXT: s_lshr_b32 s9, s18, 16
-; VI-NEXT: s_lshr_b32 s11, s17, 16
-; VI-NEXT: s_lshr_b32 s13, s16, 16
+; VI-NEXT: s_lshr_b32 s73, s28, 16
+; VI-NEXT: s_lshr_b32 s47, s27, 16
+; VI-NEXT: s_lshr_b32 s46, s26, 16
+; VI-NEXT: s_lshr_b32 s45, s25, 16
+; VI-NEXT: s_lshr_b32 s44, s24, 16
+; VI-NEXT: s_lshr_b32 s43, s23, 16
+; VI-NEXT: s_lshr_b32 s42, s22, 16
+; VI-NEXT: s_lshr_b32 s7, s21, 16
+; VI-NEXT: s_lshr_b32 s9, s20, 16
+; VI-NEXT: s_lshr_b32 s11, s19, 16
+; VI-NEXT: s_lshr_b32 s13, s18, 16
+; VI-NEXT: s_lshr_b32 s41, s17, 16
+; VI-NEXT: s_lshr_b32 s5, s16, 16
; VI-NEXT: s_lshr_b32 s63, s6, 16
+; VI-NEXT: s_lshr_b32 s15, s8, 16
+; VI-NEXT: s_lshr_b32 s61, s10, 16
; VI-NEXT: s_lshr_b32 s60, s12, 16
; VI-NEXT: s_lshr_b32 s59, s14, 16
; VI-NEXT: s_lshr_b32 s58, s72, 16
; VI-NEXT: s_lshr_b32 s57, s74, 16
; VI-NEXT: s_lshr_b32 s62, s76, 16
-; VI-NEXT: s_lshr_b32 s89, s79, 16
-; VI-NEXT: s_lshr_b32 s30, s91, 16
-; VI-NEXT: s_lshr_b32 s35, s34, 16
-; VI-NEXT: s_lshr_b32 s71, s69, 16
-; VI-NEXT: s_lshr_b32 s82, s80, 16
-; VI-NEXT: s_lshr_b32 s85, s83, 16
+; VI-NEXT: s_lshr_b32 s75, s79, 16
+; VI-NEXT: s_lshr_b32 s77, s91, 16
+; VI-NEXT: s_lshr_b32 s78, s34, 16
+; VI-NEXT: s_lshr_b32 s88, s69, 16
+; VI-NEXT: s_lshr_b32 s89, s80, 16
+; VI-NEXT: s_lshr_b32 vcc_lo, s83, 16
; VI-NEXT: v_readfirstlane_b32 s4, v14
-; VI-NEXT: v_writelane_b32 v33, s61, 1
+; VI-NEXT: v_writelane_b32 v32, s86, 30
; VI-NEXT: s_cmp_lg_u32 s4, 0
-; VI-NEXT: v_writelane_b32 v33, s60, 2
-; VI-NEXT: v_writelane_b32 v33, s59, 3
+; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_cbranch_scc0 .LBB19_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_lshl_b32 s5, s5, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s11, 16
+; VI-NEXT: s_mov_b32 s70, s41
+; VI-NEXT: s_lshl_b32 s41, s41, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s86, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
-; VI-NEXT: s_lshl_b32 s5, s84, 16
+; VI-NEXT: s_lshl_b32 s5, s42, 16
+; VI-NEXT: s_mov_b32 s30, s11
+; VI-NEXT: s_mov_b32 s11, s7
+; VI-NEXT: s_mov_b32 s7, s42
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
-; VI-NEXT: s_lshl_b32 s5, s81, 16
+; VI-NEXT: s_lshl_b32 s5, s43, 16
+; VI-NEXT: s_mov_b32 s86, s43
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
-; VI-NEXT: s_lshl_b32 s5, s70, 16
+; VI-NEXT: s_lshl_b32 s5, s44, 16
+; VI-NEXT: s_mov_b32 s84, s44
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
-; VI-NEXT: s_lshl_b32 s5, s68, 16
+; VI-NEXT: s_lshl_b32 s5, s45, 16
+; VI-NEXT: s_mov_b32 s82, s45
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
-; VI-NEXT: s_lshl_b32 s5, s31, 16
+; VI-NEXT: s_lshl_b32 s5, s46, 16
+; VI-NEXT: s_mov_b32 s71, s46
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
-; VI-NEXT: s_lshl_b32 s5, s90, 16
+; VI-NEXT: s_lshl_b32 s5, s47, 16
+; VI-NEXT: s_mov_b32 s68, s47
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s83
-; VI-NEXT: s_lshl_b32 s5, s85, 16
+; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s80
-; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s69
-; VI-NEXT: s_lshl_b32 s5, s71, 16
+; VI-NEXT: s_lshl_b32 s5, s88, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s34
-; VI-NEXT: s_lshl_b32 s5, s35, 16
+; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
-; VI-NEXT: s_lshl_b32 s5, s30, 16
+; VI-NEXT: s_lshl_b32 s5, s77, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s79
-; VI-NEXT: s_lshl_b32 s5, s89, 16
+; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s62, 16
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s90, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s75, s57
+; VI-NEXT: s_mov_b32 s87, s89
+; VI-NEXT: s_mov_b32 s89, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s72
; VI-NEXT: s_lshl_b32 s5, s58, 16
-; VI-NEXT: s_mov_b32 s78, s58
+; VI-NEXT: s_mov_b32 s85, s88
+; VI-NEXT: s_mov_b32 s88, s78
+; VI-NEXT: s_mov_b32 s78, s77
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s58
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s14
; VI-NEXT: s_lshl_b32 s5, s59, 16
@@ -11433,122 +11408,126 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s15, 16
-; VI-NEXT: s_mov_b32 s88, s62
+; VI-NEXT: s_mov_b32 s31, s73
+; VI-NEXT: s_mov_b32 s73, s62
; VI-NEXT: s_or_b32 s62, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s63, 16
+; VI-NEXT: s_mov_b32 s35, s13
+; VI-NEXT: s_mov_b32 s13, s9
+; VI-NEXT: s_mov_b32 s9, vcc_lo
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB19_4
; VI-NEXT: .LBB19_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v27, 0x200
-; VI-NEXT: v_mov_b32_e32 v0, s13
-; VI-NEXT: v_mov_b32_e32 v2, s11
+; VI-NEXT: v_mov_b32_e32 v0, s81
+; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v0, v0, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v27
; VI-NEXT: v_add_f16_sdwa v2, v2, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v27
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
-; VI-NEXT: v_mov_b32_e32 v2, s9
+; VI-NEXT: v_mov_b32_e32 v2, s35
; VI-NEXT: v_add_f16_sdwa v2, v2, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v27
; VI-NEXT: v_or_b32_e32 v2, v3, v2
-; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v3, s30
; VI-NEXT: v_add_f16_sdwa v3, v3, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v27
; VI-NEXT: v_or_b32_e32 v3, v4, v3
-; VI-NEXT: v_mov_b32_e32 v4, s87
+; VI-NEXT: v_mov_b32_e32 v4, s13
; VI-NEXT: v_add_f16_sdwa v4, v4, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v27
; VI-NEXT: v_or_b32_e32 v4, v5, v4
-; VI-NEXT: v_mov_b32_e32 v5, s86
+; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_add_f16_sdwa v5, v5, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v27
; VI-NEXT: v_or_b32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s84
+; VI-NEXT: v_mov_b32_e32 v6, s7
; VI-NEXT: v_add_f16_sdwa v6, v6, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v27
; VI-NEXT: v_or_b32_e32 v6, v7, v6
-; VI-NEXT: v_mov_b32_e32 v7, s81
+; VI-NEXT: v_mov_b32_e32 v7, s86
; VI-NEXT: v_add_f16_sdwa v7, v7, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v27
; VI-NEXT: v_or_b32_e32 v7, v8, v7
-; VI-NEXT: v_mov_b32_e32 v8, s70
+; VI-NEXT: v_mov_b32_e32 v8, s84
; VI-NEXT: v_add_f16_sdwa v8, v8, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v27
; VI-NEXT: v_or_b32_e32 v8, v9, v8
-; VI-NEXT: v_mov_b32_e32 v9, s68
+; VI-NEXT: v_mov_b32_e32 v9, s82
; VI-NEXT: v_add_f16_sdwa v9, v9, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v27
; VI-NEXT: v_or_b32_e32 v9, v10, v9
-; VI-NEXT: v_mov_b32_e32 v10, s31
+; VI-NEXT: v_mov_b32_e32 v10, s71
; VI-NEXT: v_add_f16_sdwa v10, v10, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v27
; VI-NEXT: v_or_b32_e32 v10, v11, v10
-; VI-NEXT: v_mov_b32_e32 v11, s90
+; VI-NEXT: v_mov_b32_e32 v11, s68
; VI-NEXT: v_add_f16_sdwa v11, v11, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v27
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s73
+; VI-NEXT: v_mov_b32_e32 v12, s31
; VI-NEXT: v_add_f16_sdwa v12, v12, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v27
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s77
+; VI-NEXT: v_mov_b32_e32 v13, s90
; VI-NEXT: v_add_f16_sdwa v13, v13, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v27
; VI-NEXT: v_or_b32_e32 v13, v14, v13
-; VI-NEXT: v_mov_b32_e32 v14, s85
+; VI-NEXT: v_mov_b32_e32 v14, s9
; VI-NEXT: v_add_f16_sdwa v14, v14, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s83, v27
; VI-NEXT: v_or_b32_e32 v14, v15, v14
-; VI-NEXT: v_mov_b32_e32 v15, s82
+; VI-NEXT: v_mov_b32_e32 v15, s87
; VI-NEXT: v_add_f16_sdwa v15, v15, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s80, v27
; VI-NEXT: v_or_b32_e32 v15, v16, v15
-; VI-NEXT: v_mov_b32_e32 v16, s71
+; VI-NEXT: v_mov_b32_e32 v16, s85
; VI-NEXT: v_add_f16_sdwa v16, v16, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s69, v27
; VI-NEXT: v_or_b32_e32 v16, v17, v16
-; VI-NEXT: v_mov_b32_e32 v17, s35
+; VI-NEXT: v_mov_b32_e32 v17, s88
; VI-NEXT: v_add_f16_sdwa v17, v17, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s34, v27
; VI-NEXT: v_or_b32_e32 v17, v18, v17
-; VI-NEXT: v_mov_b32_e32 v18, s30
+; VI-NEXT: v_mov_b32_e32 v18, s78
; VI-NEXT: v_add_f16_sdwa v18, v18, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s91, v27
; VI-NEXT: v_or_b32_e32 v18, v19, v18
-; VI-NEXT: v_mov_b32_e32 v19, s89
+; VI-NEXT: v_mov_b32_e32 v19, s77
; VI-NEXT: v_add_f16_sdwa v19, v19, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s79, v27
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s88
+; VI-NEXT: v_mov_b32_e32 v20, s73
; VI-NEXT: v_add_f16_sdwa v20, v20, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s76, v27
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s75
+; VI-NEXT: v_mov_b32_e32 v21, s89
; VI-NEXT: v_add_f16_sdwa v21, v21, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s74, v27
; VI-NEXT: v_or_b32_e32 v21, v22, v21
-; VI-NEXT: v_mov_b32_e32 v22, s78
+; VI-NEXT: v_mov_b32_e32 v22, s75
; VI-NEXT: v_add_f16_sdwa v22, v22, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s72, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 3
+; VI-NEXT: s_lshr_b32 s4, s14, 16
; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_mov_b32_e32 v23, s4
; VI-NEXT: v_add_f16_sdwa v23, v23, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s14, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 2
+; VI-NEXT: s_lshr_b32 s4, s12, 16
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_mov_b32_e32 v24, s4
; VI-NEXT: v_add_f16_sdwa v24, v24, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s12, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 1
+; VI-NEXT: s_lshr_b32 s4, s10, 16
; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: v_mov_b32_e32 v25, s4
; VI-NEXT: v_add_f16_sdwa v25, v25, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, s10, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 0
+; VI-NEXT: s_lshr_b32 s4, s8, 16
; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: v_mov_b32_e32 v26, s4
; VI-NEXT: v_add_f16_sdwa v26, v26, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
@@ -11560,11 +11539,29 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: s_branch .LBB19_5
; VI-NEXT: .LBB19_3:
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s88, s62
-; VI-NEXT: s_mov_b32 s77, s56
-; VI-NEXT: s_mov_b32 s75, s57
-; VI-NEXT: s_mov_b32 s78, s58
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_mov_b32 s70, s41
+; VI-NEXT: s_mov_b32 s35, s13
+; VI-NEXT: s_mov_b32 s30, s11
+; VI-NEXT: s_mov_b32 s13, s9
+; VI-NEXT: s_mov_b32 s11, s7
+; VI-NEXT: s_mov_b32 s9, vcc_lo
+; VI-NEXT: s_mov_b32 s7, s42
+; VI-NEXT: s_mov_b32 s87, s89
+; VI-NEXT: s_mov_b32 s86, s43
+; VI-NEXT: s_mov_b32 s85, s88
+; VI-NEXT: s_mov_b32 s84, s44
+; VI-NEXT: s_mov_b32 s82, s45
+; VI-NEXT: s_mov_b32 s88, s78
+; VI-NEXT: s_mov_b32 s71, s46
+; VI-NEXT: s_mov_b32 s78, s77
+; VI-NEXT: s_mov_b32 s68, s47
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s31, s73
+; VI-NEXT: s_mov_b32 s73, s62
+; VI-NEXT: s_mov_b32 s90, s56
+; VI-NEXT: s_mov_b32 s89, s57
+; VI-NEXT: s_mov_b32 s75, s58
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB19_2
@@ -11636,7 +11633,6 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_readlane_b32 s30, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -18341,13 +18337,13 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: v_writelane_b32 v28, s85, 29
; VI-NEXT: v_writelane_b32 v28, s86, 30
; VI-NEXT: v_writelane_b32 v28, s87, 31
-; VI-NEXT: v_readfirstlane_b32 s86, v13
+; VI-NEXT: v_readfirstlane_b32 s87, v13
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: v_readfirstlane_b32 s9, v11
; VI-NEXT: v_readfirstlane_b32 s8, v10
-; VI-NEXT: v_readfirstlane_b32 s87, v9
-; VI-NEXT: v_readfirstlane_b32 s12, v8
-; VI-NEXT: v_readfirstlane_b32 s73, v7
+; VI-NEXT: v_readfirstlane_b32 s10, v9
+; VI-NEXT: v_readfirstlane_b32 s73, v8
+; VI-NEXT: v_readfirstlane_b32 s75, v7
; VI-NEXT: v_readfirstlane_b32 s77, v6
; VI-NEXT: v_readfirstlane_b32 s88, v5
; VI-NEXT: v_readfirstlane_b32 s91, v4
@@ -18363,19 +18359,19 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_lshr_b32 s80, s24, 16
; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_lshr_b32 s85, s22, 16
-; VI-NEXT: s_lshr_b32 s7, s21, 16
-; VI-NEXT: s_lshr_b32 s11, s20, 16
-; VI-NEXT: s_lshr_b32 s13, s19, 16
-; VI-NEXT: s_lshr_b32 s15, s18, 16
-; VI-NEXT: s_lshr_b32 s10, s17, 16
-; VI-NEXT: s_lshr_b32 s75, s16, 16
-; VI-NEXT: s_lshr_b32 s64, s86, 16
+; VI-NEXT: s_lshr_b32 s86, s21, 16
+; VI-NEXT: s_lshr_b32 s7, s20, 16
+; VI-NEXT: s_lshr_b32 s11, s19, 16
+; VI-NEXT: s_lshr_b32 s13, s18, 16
+; VI-NEXT: s_lshr_b32 s15, s17, 16
+; VI-NEXT: s_lshr_b32 s12, s16, 16
+; VI-NEXT: s_lshr_b32 s64, s87, 16
; VI-NEXT: s_lshr_b32 s65, s6, 16
; VI-NEXT: s_lshr_b32 s66, s9, 16
; VI-NEXT: s_lshr_b32 s14, s8, 16
-; VI-NEXT: s_lshr_b32 s72, s87, 16
-; VI-NEXT: s_lshr_b32 s74, s12, 16
-; VI-NEXT: s_lshr_b32 s76, s73, 16
+; VI-NEXT: s_lshr_b32 s72, s10, 16
+; VI-NEXT: s_lshr_b32 s74, s73, 16
+; VI-NEXT: s_lshr_b32 s76, s75, 16
; VI-NEXT: s_lshr_b32 s78, s77, 16
; VI-NEXT: s_lshr_b32 s89, s88, 16
; VI-NEXT: s_lshr_b32 s30, s91, 16
@@ -18385,25 +18381,27 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_lshr_b32 s83, s84, 16
; VI-NEXT: v_readfirstlane_b32 s4, v14
; VI-NEXT: s_cmp_lg_u32 s4, 0
+; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
+; VI-NEXT: v_writelane_b32 v29, s10, 0
; VI-NEXT: s_cbranch_scc0 .LBB31_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s10, 16
+; VI-NEXT: s_lshl_b32 s41, s15, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
; VI-NEXT: s_lshl_b32 s5, s85, 16
@@ -18450,13 +18448,13 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s56, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s73
+; VI-NEXT: s_and_b32 s4, 0xffff, s75
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s57, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s12
+; VI-NEXT: s_and_b32 s4, 0xffff, s73
; VI-NEXT: s_lshl_b32 s5, s74, 16
; VI-NEXT: s_or_b32 s58, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s87
+; VI-NEXT: s_and_b32 s4, 0xffff, s10
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
@@ -18468,39 +18466,39 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s62, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s86
+; VI-NEXT: s_and_b32 s4, 0xffff, s87
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB31_3
; VI-NEXT: .LBB31_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s10, s10, 16
+; VI-NEXT: s_lshl_b32 s10, s15, 16
; VI-NEXT: s_or_b32 s5, s10, s5
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s36, s4, 0x30000
; VI-NEXT: s_add_i32 s37, s5, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s38, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s19, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s21, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s41, s4, 0x30000
@@ -18577,18 +18575,19 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, s77, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s75, s73, 3
+; VI-NEXT: s_add_i32 s75, s75, 3
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s75, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s73, s12, 3
+; VI-NEXT: s_add_i32 s73, s73, 3
; VI-NEXT: s_add_i32 s57, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s73, 0xffff
; VI-NEXT: s_lshl_b32 s5, s74, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s15, s87, 3
; VI-NEXT: s_add_i32 s58, s4, 0x30000
+; VI-NEXT: v_readlane_b32 s4, v29, 0
+; VI-NEXT: s_add_i32 s15, s4, 3
; VI-NEXT: s_and_b32 s4, s15, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -18607,7 +18606,7 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, s9, 0xffff
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s7, s86, 3
+; VI-NEXT: s_add_i32 s7, s87, 3
; VI-NEXT: s_add_i32 s62, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s7, 0xffff
; VI-NEXT: s_lshl_b32 s5, s64, 16
@@ -18681,24 +18680,8 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB31_4:
-; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b32 vcc_lo, s64
-; VI-NEXT: v_writelane_b32 v29, s75, 0
; VI-NEXT: s_mov_b32 vcc_hi, s65
-; VI-NEXT: s_mov_b32 s75, s73
-; VI-NEXT: s_mov_b32 s73, s12
-; VI-NEXT: v_writelane_b32 v29, s25, 1
-; VI-NEXT: s_mov_b32 s25, s91
-; VI-NEXT: s_mov_b32 s91, s26
-; VI-NEXT: s_mov_b32 s26, s27
-; VI-NEXT: s_mov_b32 s27, s88
-; VI-NEXT: s_mov_b32 s88, s28
-; VI-NEXT: s_mov_b32 s28, s77
-; VI-NEXT: s_mov_b32 s77, s29
-; VI-NEXT: s_mov_b32 s29, s15
-; VI-NEXT: s_mov_b32 s15, s87
-; VI-NEXT: s_mov_b32 s87, s85
-; VI-NEXT: s_mov_b32 s85, s82
; VI-NEXT: s_mov_b32 s82, s71
; VI-NEXT: s_mov_b32 s71, s68
; VI-NEXT: s_mov_b32 s68, s35
@@ -18713,15 +18696,12 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s74, s72
; VI-NEXT: s_mov_b32 s72, s14
; VI-NEXT: s_mov_b32 s14, s66
-; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s13
-; VI-NEXT: s_mov_b32 s13, s8
-; VI-NEXT: s_mov_b32 s8, s11
-; VI-NEXT: s_mov_b32 s11, s9
-; VI-NEXT: s_mov_b32 s9, s6
-; VI-NEXT: s_mov_b32 s6, s7
+; VI-NEXT: s_mov_b32 s13, s11
+; VI-NEXT: s_mov_b32 s11, s7
; VI-NEXT: s_mov_b32 s7, s86
-; VI-NEXT: s_mov_b32 s86, s83
+; VI-NEXT: s_mov_b32 s86, s85
+; VI-NEXT: s_mov_b32 s85, s83
; VI-NEXT: s_mov_b32 s83, s80
; VI-NEXT: s_mov_b32 s80, s70
; VI-NEXT: s_mov_b32 s70, s67
@@ -18729,15 +18709,12 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s67, s70
; VI-NEXT: s_mov_b32 s70, s80
; VI-NEXT: s_mov_b32 s80, s83
-; VI-NEXT: s_mov_b32 s83, s86
+; VI-NEXT: s_mov_b32 s83, s85
+; VI-NEXT: s_mov_b32 s85, s86
; VI-NEXT: s_mov_b32 s86, s7
-; VI-NEXT: s_mov_b32 s7, s6
-; VI-NEXT: s_mov_b32 s6, s9
-; VI-NEXT: s_mov_b32 s9, s11
-; VI-NEXT: s_mov_b32 s11, s8
-; VI-NEXT: s_mov_b32 s8, s13
+; VI-NEXT: s_mov_b32 s7, s11
+; VI-NEXT: s_mov_b32 s11, s13
; VI-NEXT: s_mov_b32 s13, s10
-; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s66, s14
; VI-NEXT: s_mov_b32 s14, s72
; VI-NEXT: s_mov_b32 s72, s74
@@ -18752,21 +18729,7 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s35, s68
; VI-NEXT: s_mov_b32 s68, s71
; VI-NEXT: s_mov_b32 s71, s82
-; VI-NEXT: s_mov_b32 s82, s85
-; VI-NEXT: s_mov_b32 s85, s87
-; VI-NEXT: s_mov_b32 s87, s15
-; VI-NEXT: s_mov_b32 s15, s29
-; VI-NEXT: s_mov_b32 s29, s77
-; VI-NEXT: s_mov_b32 s77, s28
-; VI-NEXT: s_mov_b32 s28, s88
-; VI-NEXT: s_mov_b32 s88, s27
-; VI-NEXT: s_mov_b32 s27, s26
-; VI-NEXT: s_mov_b32 s26, s91
-; VI-NEXT: s_mov_b32 s91, s25
-; VI-NEXT: v_readlane_b32 s25, v29, 1
-; VI-NEXT: s_mov_b32 s12, s73
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: v_readlane_b32 s75, v29, 0
+; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_mov_b32 s65, vcc_hi
; VI-NEXT: s_mov_b32 s64, vcc_lo
; VI-NEXT: s_branch .LBB31_2
@@ -23098,7 +23061,6 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s30, 0
; VI-NEXT: v_writelane_b32 v32, s31, 1
@@ -23129,14 +23091,9 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: v_writelane_b32 v32, s82, 26
; VI-NEXT: v_writelane_b32 v32, s83, 27
; VI-NEXT: v_writelane_b32 v32, s84, 28
+; VI-NEXT: v_readfirstlane_b32 s6, v13
; VI-NEXT: v_readfirstlane_b32 s8, v12
-; VI-NEXT: v_writelane_b32 v32, s85, 29
-; VI-NEXT: s_lshr_b32 s15, s8, 16
; VI-NEXT: v_readfirstlane_b32 s10, v11
-; VI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
-; VI-NEXT: v_writelane_b32 v32, s86, 30
-; VI-NEXT: v_readfirstlane_b32 s6, v13
-; VI-NEXT: s_lshr_b32 s61, s10, 16
; VI-NEXT: v_readfirstlane_b32 s12, v10
; VI-NEXT: v_readfirstlane_b32 s14, v9
; VI-NEXT: v_readfirstlane_b32 s72, v8
@@ -23148,113 +23105,127 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: v_readfirstlane_b32 s69, v2
; VI-NEXT: v_readfirstlane_b32 s80, v1
; VI-NEXT: v_readfirstlane_b32 s83, v0
-; VI-NEXT: v_writelane_b32 v33, s15, 0
-; VI-NEXT: v_writelane_b32 v32, s87, 31
+; VI-NEXT: v_writelane_b32 v32, s85, 29
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s75, s28, 16
-; VI-NEXT: s_lshr_b32 s90, s27, 16
-; VI-NEXT: s_lshr_b32 s31, s26, 16
-; VI-NEXT: s_lshr_b32 s68, s25, 16
-; VI-NEXT: s_lshr_b32 s70, s24, 16
-; VI-NEXT: s_lshr_b32 s81, s23, 16
-; VI-NEXT: s_lshr_b32 s84, s22, 16
-; VI-NEXT: s_lshr_b32 s86, s21, 16
-; VI-NEXT: s_lshr_b32 s87, s20, 16
-; VI-NEXT: s_lshr_b32 s7, s19, 16
-; VI-NEXT: s_lshr_b32 s9, s18, 16
-; VI-NEXT: s_lshr_b32 s11, s17, 16
-; VI-NEXT: s_lshr_b32 s13, s16, 16
+; VI-NEXT: s_lshr_b32 s73, s28, 16
+; VI-NEXT: s_lshr_b32 s47, s27, 16
+; VI-NEXT: s_lshr_b32 s46, s26, 16
+; VI-NEXT: s_lshr_b32 s45, s25, 16
+; VI-NEXT: s_lshr_b32 s44, s24, 16
+; VI-NEXT: s_lshr_b32 s43, s23, 16
+; VI-NEXT: s_lshr_b32 s42, s22, 16
+; VI-NEXT: s_lshr_b32 s7, s21, 16
+; VI-NEXT: s_lshr_b32 s9, s20, 16
+; VI-NEXT: s_lshr_b32 s11, s19, 16
+; VI-NEXT: s_lshr_b32 s13, s18, 16
+; VI-NEXT: s_lshr_b32 s41, s17, 16
+; VI-NEXT: s_lshr_b32 s5, s16, 16
; VI-NEXT: s_lshr_b32 s63, s6, 16
+; VI-NEXT: s_lshr_b32 s15, s8, 16
+; VI-NEXT: s_lshr_b32 s61, s10, 16
; VI-NEXT: s_lshr_b32 s60, s12, 16
; VI-NEXT: s_lshr_b32 s59, s14, 16
; VI-NEXT: s_lshr_b32 s58, s72, 16
; VI-NEXT: s_lshr_b32 s57, s74, 16
; VI-NEXT: s_lshr_b32 s62, s76, 16
-; VI-NEXT: s_lshr_b32 s89, s79, 16
-; VI-NEXT: s_lshr_b32 s30, s91, 16
-; VI-NEXT: s_lshr_b32 s35, s34, 16
-; VI-NEXT: s_lshr_b32 s71, s69, 16
-; VI-NEXT: s_lshr_b32 s82, s80, 16
-; VI-NEXT: s_lshr_b32 s85, s83, 16
+; VI-NEXT: s_lshr_b32 s75, s79, 16
+; VI-NEXT: s_lshr_b32 s77, s91, 16
+; VI-NEXT: s_lshr_b32 s78, s34, 16
+; VI-NEXT: s_lshr_b32 s88, s69, 16
+; VI-NEXT: s_lshr_b32 s89, s80, 16
+; VI-NEXT: s_lshr_b32 vcc_lo, s83, 16
; VI-NEXT: v_readfirstlane_b32 s4, v14
-; VI-NEXT: v_writelane_b32 v33, s61, 1
+; VI-NEXT: v_writelane_b32 v32, s86, 30
; VI-NEXT: s_cmp_lg_u32 s4, 0
-; VI-NEXT: v_writelane_b32 v33, s60, 2
-; VI-NEXT: v_writelane_b32 v33, s59, 3
+; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_cbranch_scc0 .LBB35_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_lshl_b32 s5, s5, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s11, 16
+; VI-NEXT: s_mov_b32 s70, s41
+; VI-NEXT: s_lshl_b32 s41, s41, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s86, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
-; VI-NEXT: s_lshl_b32 s5, s84, 16
+; VI-NEXT: s_lshl_b32 s5, s42, 16
+; VI-NEXT: s_mov_b32 s30, s11
+; VI-NEXT: s_mov_b32 s11, s7
+; VI-NEXT: s_mov_b32 s7, s42
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
-; VI-NEXT: s_lshl_b32 s5, s81, 16
+; VI-NEXT: s_lshl_b32 s5, s43, 16
+; VI-NEXT: s_mov_b32 s86, s43
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
-; VI-NEXT: s_lshl_b32 s5, s70, 16
+; VI-NEXT: s_lshl_b32 s5, s44, 16
+; VI-NEXT: s_mov_b32 s84, s44
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
-; VI-NEXT: s_lshl_b32 s5, s68, 16
+; VI-NEXT: s_lshl_b32 s5, s45, 16
+; VI-NEXT: s_mov_b32 s82, s45
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
-; VI-NEXT: s_lshl_b32 s5, s31, 16
+; VI-NEXT: s_lshl_b32 s5, s46, 16
+; VI-NEXT: s_mov_b32 s71, s46
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
-; VI-NEXT: s_lshl_b32 s5, s90, 16
+; VI-NEXT: s_lshl_b32 s5, s47, 16
+; VI-NEXT: s_mov_b32 s68, s47
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s83
-; VI-NEXT: s_lshl_b32 s5, s85, 16
+; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s80
-; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s69
-; VI-NEXT: s_lshl_b32 s5, s71, 16
+; VI-NEXT: s_lshl_b32 s5, s88, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s34
-; VI-NEXT: s_lshl_b32 s5, s35, 16
+; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
-; VI-NEXT: s_lshl_b32 s5, s30, 16
+; VI-NEXT: s_lshl_b32 s5, s77, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s79
-; VI-NEXT: s_lshl_b32 s5, s89, 16
+; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s62, 16
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s90, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s75, s57
+; VI-NEXT: s_mov_b32 s87, s89
+; VI-NEXT: s_mov_b32 s89, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s72
; VI-NEXT: s_lshl_b32 s5, s58, 16
-; VI-NEXT: s_mov_b32 s78, s58
+; VI-NEXT: s_mov_b32 s85, s88
+; VI-NEXT: s_mov_b32 s88, s78
+; VI-NEXT: s_mov_b32 s78, s77
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s58
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s14
; VI-NEXT: s_lshl_b32 s5, s59, 16
@@ -23267,122 +23238,126 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s15, 16
-; VI-NEXT: s_mov_b32 s88, s62
+; VI-NEXT: s_mov_b32 s31, s73
+; VI-NEXT: s_mov_b32 s73, s62
; VI-NEXT: s_or_b32 s62, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s63, 16
+; VI-NEXT: s_mov_b32 s35, s13
+; VI-NEXT: s_mov_b32 s13, s9
+; VI-NEXT: s_mov_b32 s9, vcc_lo
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v27, 0x200
-; VI-NEXT: v_mov_b32_e32 v0, s13
-; VI-NEXT: v_mov_b32_e32 v2, s11
+; VI-NEXT: v_mov_b32_e32 v0, s81
+; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v0, v0, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v27
; VI-NEXT: v_add_f16_sdwa v2, v2, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v27
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
-; VI-NEXT: v_mov_b32_e32 v2, s9
+; VI-NEXT: v_mov_b32_e32 v2, s35
; VI-NEXT: v_add_f16_sdwa v2, v2, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v27
; VI-NEXT: v_or_b32_e32 v2, v3, v2
-; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v3, s30
; VI-NEXT: v_add_f16_sdwa v3, v3, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v27
; VI-NEXT: v_or_b32_e32 v3, v4, v3
-; VI-NEXT: v_mov_b32_e32 v4, s87
+; VI-NEXT: v_mov_b32_e32 v4, s13
; VI-NEXT: v_add_f16_sdwa v4, v4, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v27
; VI-NEXT: v_or_b32_e32 v4, v5, v4
-; VI-NEXT: v_mov_b32_e32 v5, s86
+; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_add_f16_sdwa v5, v5, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v27
; VI-NEXT: v_or_b32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s84
+; VI-NEXT: v_mov_b32_e32 v6, s7
; VI-NEXT: v_add_f16_sdwa v6, v6, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v27
; VI-NEXT: v_or_b32_e32 v6, v7, v6
-; VI-NEXT: v_mov_b32_e32 v7, s81
+; VI-NEXT: v_mov_b32_e32 v7, s86
; VI-NEXT: v_add_f16_sdwa v7, v7, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v27
; VI-NEXT: v_or_b32_e32 v7, v8, v7
-; VI-NEXT: v_mov_b32_e32 v8, s70
+; VI-NEXT: v_mov_b32_e32 v8, s84
; VI-NEXT: v_add_f16_sdwa v8, v8, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v27
; VI-NEXT: v_or_b32_e32 v8, v9, v8
-; VI-NEXT: v_mov_b32_e32 v9, s68
+; VI-NEXT: v_mov_b32_e32 v9, s82
; VI-NEXT: v_add_f16_sdwa v9, v9, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v27
; VI-NEXT: v_or_b32_e32 v9, v10, v9
-; VI-NEXT: v_mov_b32_e32 v10, s31
+; VI-NEXT: v_mov_b32_e32 v10, s71
; VI-NEXT: v_add_f16_sdwa v10, v10, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v27
; VI-NEXT: v_or_b32_e32 v10, v11, v10
-; VI-NEXT: v_mov_b32_e32 v11, s90
+; VI-NEXT: v_mov_b32_e32 v11, s68
; VI-NEXT: v_add_f16_sdwa v11, v11, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v27
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s73
+; VI-NEXT: v_mov_b32_e32 v12, s31
; VI-NEXT: v_add_f16_sdwa v12, v12, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v27
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s77
+; VI-NEXT: v_mov_b32_e32 v13, s90
; VI-NEXT: v_add_f16_sdwa v13, v13, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v27
; VI-NEXT: v_or_b32_e32 v13, v14, v13
-; VI-NEXT: v_mov_b32_e32 v14, s85
+; VI-NEXT: v_mov_b32_e32 v14, s9
; VI-NEXT: v_add_f16_sdwa v14, v14, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s83, v27
; VI-NEXT: v_or_b32_e32 v14, v15, v14
-; VI-NEXT: v_mov_b32_e32 v15, s82
+; VI-NEXT: v_mov_b32_e32 v15, s87
; VI-NEXT: v_add_f16_sdwa v15, v15, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s80, v27
; VI-NEXT: v_or_b32_e32 v15, v16, v15
-; VI-NEXT: v_mov_b32_e32 v16, s71
+; VI-NEXT: v_mov_b32_e32 v16, s85
; VI-NEXT: v_add_f16_sdwa v16, v16, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s69, v27
; VI-NEXT: v_or_b32_e32 v16, v17, v16
-; VI-NEXT: v_mov_b32_e32 v17, s35
+; VI-NEXT: v_mov_b32_e32 v17, s88
; VI-NEXT: v_add_f16_sdwa v17, v17, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s34, v27
; VI-NEXT: v_or_b32_e32 v17, v18, v17
-; VI-NEXT: v_mov_b32_e32 v18, s30
+; VI-NEXT: v_mov_b32_e32 v18, s78
; VI-NEXT: v_add_f16_sdwa v18, v18, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s91, v27
; VI-NEXT: v_or_b32_e32 v18, v19, v18
-; VI-NEXT: v_mov_b32_e32 v19, s89
+; VI-NEXT: v_mov_b32_e32 v19, s77
; VI-NEXT: v_add_f16_sdwa v19, v19, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s79, v27
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s88
+; VI-NEXT: v_mov_b32_e32 v20, s73
; VI-NEXT: v_add_f16_sdwa v20, v20, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s76, v27
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s75
+; VI-NEXT: v_mov_b32_e32 v21, s89
; VI-NEXT: v_add_f16_sdwa v21, v21, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s74, v27
; VI-NEXT: v_or_b32_e32 v21, v22, v21
-; VI-NEXT: v_mov_b32_e32 v22, s78
+; VI-NEXT: v_mov_b32_e32 v22, s75
; VI-NEXT: v_add_f16_sdwa v22, v22, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s72, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 3
+; VI-NEXT: s_lshr_b32 s4, s14, 16
; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_mov_b32_e32 v23, s4
; VI-NEXT: v_add_f16_sdwa v23, v23, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s14, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 2
+; VI-NEXT: s_lshr_b32 s4, s12, 16
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_mov_b32_e32 v24, s4
; VI-NEXT: v_add_f16_sdwa v24, v24, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s12, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 1
+; VI-NEXT: s_lshr_b32 s4, s10, 16
; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: v_mov_b32_e32 v25, s4
; VI-NEXT: v_add_f16_sdwa v25, v25, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, s10, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 0
+; VI-NEXT: s_lshr_b32 s4, s8, 16
; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: v_mov_b32_e32 v26, s4
; VI-NEXT: v_add_f16_sdwa v26, v26, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
@@ -23394,11 +23369,29 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: s_branch .LBB35_5
; VI-NEXT: .LBB35_3:
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s88, s62
-; VI-NEXT: s_mov_b32 s77, s56
-; VI-NEXT: s_mov_b32 s75, s57
-; VI-NEXT: s_mov_b32 s78, s58
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_mov_b32 s70, s41
+; VI-NEXT: s_mov_b32 s35, s13
+; VI-NEXT: s_mov_b32 s30, s11
+; VI-NEXT: s_mov_b32 s13, s9
+; VI-NEXT: s_mov_b32 s11, s7
+; VI-NEXT: s_mov_b32 s9, vcc_lo
+; VI-NEXT: s_mov_b32 s7, s42
+; VI-NEXT: s_mov_b32 s87, s89
+; VI-NEXT: s_mov_b32 s86, s43
+; VI-NEXT: s_mov_b32 s85, s88
+; VI-NEXT: s_mov_b32 s84, s44
+; VI-NEXT: s_mov_b32 s82, s45
+; VI-NEXT: s_mov_b32 s88, s78
+; VI-NEXT: s_mov_b32 s71, s46
+; VI-NEXT: s_mov_b32 s78, s77
+; VI-NEXT: s_mov_b32 s68, s47
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s31, s73
+; VI-NEXT: s_mov_b32 s73, s62
+; VI-NEXT: s_mov_b32 s90, s56
+; VI-NEXT: s_mov_b32 s89, s57
+; VI-NEXT: s_mov_b32 s75, s58
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB35_2
@@ -23470,7 +23463,6 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: v_readlane_b32 s30, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -28401,13 +28393,13 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: v_writelane_b32 v28, s85, 29
; VI-NEXT: v_writelane_b32 v28, s86, 30
; VI-NEXT: v_writelane_b32 v28, s87, 31
-; VI-NEXT: v_readfirstlane_b32 s86, v13
+; VI-NEXT: v_readfirstlane_b32 s87, v13
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: v_readfirstlane_b32 s9, v11
; VI-NEXT: v_readfirstlane_b32 s8, v10
-; VI-NEXT: v_readfirstlane_b32 s87, v9
-; VI-NEXT: v_readfirstlane_b32 s12, v8
-; VI-NEXT: v_readfirstlane_b32 s73, v7
+; VI-NEXT: v_readfirstlane_b32 s10, v9
+; VI-NEXT: v_readfirstlane_b32 s73, v8
+; VI-NEXT: v_readfirstlane_b32 s75, v7
; VI-NEXT: v_readfirstlane_b32 s77, v6
; VI-NEXT: v_readfirstlane_b32 s88, v5
; VI-NEXT: v_readfirstlane_b32 s91, v4
@@ -28423,19 +28415,19 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_lshr_b32 s80, s24, 16
; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_lshr_b32 s85, s22, 16
-; VI-NEXT: s_lshr_b32 s7, s21, 16
-; VI-NEXT: s_lshr_b32 s11, s20, 16
-; VI-NEXT: s_lshr_b32 s13, s19, 16
-; VI-NEXT: s_lshr_b32 s15, s18, 16
-; VI-NEXT: s_lshr_b32 s10, s17, 16
-; VI-NEXT: s_lshr_b32 s75, s16, 16
-; VI-NEXT: s_lshr_b32 s64, s86, 16
+; VI-NEXT: s_lshr_b32 s86, s21, 16
+; VI-NEXT: s_lshr_b32 s7, s20, 16
+; VI-NEXT: s_lshr_b32 s11, s19, 16
+; VI-NEXT: s_lshr_b32 s13, s18, 16
+; VI-NEXT: s_lshr_b32 s15, s17, 16
+; VI-NEXT: s_lshr_b32 s12, s16, 16
+; VI-NEXT: s_lshr_b32 s64, s87, 16
; VI-NEXT: s_lshr_b32 s65, s6, 16
; VI-NEXT: s_lshr_b32 s66, s9, 16
; VI-NEXT: s_lshr_b32 s14, s8, 16
-; VI-NEXT: s_lshr_b32 s72, s87, 16
-; VI-NEXT: s_lshr_b32 s74, s12, 16
-; VI-NEXT: s_lshr_b32 s76, s73, 16
+; VI-NEXT: s_lshr_b32 s72, s10, 16
+; VI-NEXT: s_lshr_b32 s74, s73, 16
+; VI-NEXT: s_lshr_b32 s76, s75, 16
; VI-NEXT: s_lshr_b32 s78, s77, 16
; VI-NEXT: s_lshr_b32 s89, s88, 16
; VI-NEXT: s_lshr_b32 s30, s91, 16
@@ -28445,25 +28437,27 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_lshr_b32 s83, s84, 16
; VI-NEXT: v_readfirstlane_b32 s4, v14
; VI-NEXT: s_cmp_lg_u32 s4, 0
+; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
+; VI-NEXT: v_writelane_b32 v29, s10, 0
; VI-NEXT: s_cbranch_scc0 .LBB43_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s10, 16
+; VI-NEXT: s_lshl_b32 s41, s15, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
; VI-NEXT: s_lshl_b32 s5, s85, 16
@@ -28510,13 +28504,13 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s56, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s73
+; VI-NEXT: s_and_b32 s4, 0xffff, s75
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s57, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s12
+; VI-NEXT: s_and_b32 s4, 0xffff, s73
; VI-NEXT: s_lshl_b32 s5, s74, 16
; VI-NEXT: s_or_b32 s58, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s87
+; VI-NEXT: s_and_b32 s4, 0xffff, s10
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
@@ -28528,39 +28522,39 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s62, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s86
+; VI-NEXT: s_and_b32 s4, 0xffff, s87
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: .LBB43_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s10, s10, 16
+; VI-NEXT: s_lshl_b32 s10, s15, 16
; VI-NEXT: s_or_b32 s5, s10, s5
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s36, s4, 0x30000
; VI-NEXT: s_add_i32 s37, s5, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s38, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s19, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s21, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s41, s4, 0x30000
@@ -28637,18 +28631,19 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, s77, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s75, s73, 3
+; VI-NEXT: s_add_i32 s75, s75, 3
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s75, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s73, s12, 3
+; VI-NEXT: s_add_i32 s73, s73, 3
; VI-NEXT: s_add_i32 s57, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s73, 0xffff
; VI-NEXT: s_lshl_b32 s5, s74, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s15, s87, 3
; VI-NEXT: s_add_i32 s58, s4, 0x30000
+; VI-NEXT: v_readlane_b32 s4, v29, 0
+; VI-NEXT: s_add_i32 s15, s4, 3
; VI-NEXT: s_and_b32 s4, s15, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -28667,7 +28662,7 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, s9, 0xffff
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s7, s86, 3
+; VI-NEXT: s_add_i32 s7, s87, 3
; VI-NEXT: s_add_i32 s62, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s7, 0xffff
; VI-NEXT: s_lshl_b32 s5, s64, 16
@@ -28741,24 +28736,8 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB43_4:
-; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b32 vcc_lo, s64
-; VI-NEXT: v_writelane_b32 v29, s75, 0
; VI-NEXT: s_mov_b32 vcc_hi, s65
-; VI-NEXT: s_mov_b32 s75, s73
-; VI-NEXT: s_mov_b32 s73, s12
-; VI-NEXT: v_writelane_b32 v29, s25, 1
-; VI-NEXT: s_mov_b32 s25, s91
-; VI-NEXT: s_mov_b32 s91, s26
-; VI-NEXT: s_mov_b32 s26, s27
-; VI-NEXT: s_mov_b32 s27, s88
-; VI-NEXT: s_mov_b32 s88, s28
-; VI-NEXT: s_mov_b32 s28, s77
-; VI-NEXT: s_mov_b32 s77, s29
-; VI-NEXT: s_mov_b32 s29, s15
-; VI-NEXT: s_mov_b32 s15, s87
-; VI-NEXT: s_mov_b32 s87, s85
-; VI-NEXT: s_mov_b32 s85, s82
; VI-NEXT: s_mov_b32 s82, s71
; VI-NEXT: s_mov_b32 s71, s68
; VI-NEXT: s_mov_b32 s68, s35
@@ -28773,15 +28752,12 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s74, s72
; VI-NEXT: s_mov_b32 s72, s14
; VI-NEXT: s_mov_b32 s14, s66
-; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s13
-; VI-NEXT: s_mov_b32 s13, s8
-; VI-NEXT: s_mov_b32 s8, s11
-; VI-NEXT: s_mov_b32 s11, s9
-; VI-NEXT: s_mov_b32 s9, s6
-; VI-NEXT: s_mov_b32 s6, s7
+; VI-NEXT: s_mov_b32 s13, s11
+; VI-NEXT: s_mov_b32 s11, s7
; VI-NEXT: s_mov_b32 s7, s86
-; VI-NEXT: s_mov_b32 s86, s83
+; VI-NEXT: s_mov_b32 s86, s85
+; VI-NEXT: s_mov_b32 s85, s83
; VI-NEXT: s_mov_b32 s83, s80
; VI-NEXT: s_mov_b32 s80, s70
; VI-NEXT: s_mov_b32 s70, s67
@@ -28789,15 +28765,12 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s67, s70
; VI-NEXT: s_mov_b32 s70, s80
; VI-NEXT: s_mov_b32 s80, s83
-; VI-NEXT: s_mov_b32 s83, s86
+; VI-NEXT: s_mov_b32 s83, s85
+; VI-NEXT: s_mov_b32 s85, s86
; VI-NEXT: s_mov_b32 s86, s7
-; VI-NEXT: s_mov_b32 s7, s6
-; VI-NEXT: s_mov_b32 s6, s9
-; VI-NEXT: s_mov_b32 s9, s11
-; VI-NEXT: s_mov_b32 s11, s8
-; VI-NEXT: s_mov_b32 s8, s13
+; VI-NEXT: s_mov_b32 s7, s11
+; VI-NEXT: s_mov_b32 s11, s13
; VI-NEXT: s_mov_b32 s13, s10
-; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s66, s14
; VI-NEXT: s_mov_b32 s14, s72
; VI-NEXT: s_mov_b32 s72, s74
@@ -28812,21 +28785,7 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s35, s68
; VI-NEXT: s_mov_b32 s68, s71
; VI-NEXT: s_mov_b32 s71, s82
-; VI-NEXT: s_mov_b32 s82, s85
-; VI-NEXT: s_mov_b32 s85, s87
-; VI-NEXT: s_mov_b32 s87, s15
-; VI-NEXT: s_mov_b32 s15, s29
-; VI-NEXT: s_mov_b32 s29, s77
-; VI-NEXT: s_mov_b32 s77, s28
-; VI-NEXT: s_mov_b32 s28, s88
-; VI-NEXT: s_mov_b32 s88, s27
-; VI-NEXT: s_mov_b32 s27, s26
-; VI-NEXT: s_mov_b32 s26, s91
-; VI-NEXT: s_mov_b32 s91, s25
-; VI-NEXT: v_readlane_b32 s25, v29, 1
-; VI-NEXT: s_mov_b32 s12, s73
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: v_readlane_b32 s75, v29, 0
+; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_mov_b32 s65, vcc_hi
; VI-NEXT: s_mov_b32 s64, vcc_lo
; VI-NEXT: s_branch .LBB43_2
@@ -32809,7 +32768,6 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s30, 0
; VI-NEXT: v_writelane_b32 v32, s31, 1
@@ -32840,14 +32798,9 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_writelane_b32 v32, s82, 26
; VI-NEXT: v_writelane_b32 v32, s83, 27
; VI-NEXT: v_writelane_b32 v32, s84, 28
+; VI-NEXT: v_readfirstlane_b32 s6, v13
; VI-NEXT: v_readfirstlane_b32 s8, v12
-; VI-NEXT: v_writelane_b32 v32, s85, 29
-; VI-NEXT: s_lshr_b32 s15, s8, 16
; VI-NEXT: v_readfirstlane_b32 s10, v11
-; VI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
-; VI-NEXT: v_writelane_b32 v32, s86, 30
-; VI-NEXT: v_readfirstlane_b32 s6, v13
-; VI-NEXT: s_lshr_b32 s61, s10, 16
; VI-NEXT: v_readfirstlane_b32 s12, v10
; VI-NEXT: v_readfirstlane_b32 s14, v9
; VI-NEXT: v_readfirstlane_b32 s72, v8
@@ -32859,113 +32812,127 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s69, v2
; VI-NEXT: v_readfirstlane_b32 s80, v1
; VI-NEXT: v_readfirstlane_b32 s83, v0
-; VI-NEXT: v_writelane_b32 v33, s15, 0
-; VI-NEXT: v_writelane_b32 v32, s87, 31
+; VI-NEXT: v_writelane_b32 v32, s85, 29
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s75, s28, 16
-; VI-NEXT: s_lshr_b32 s90, s27, 16
-; VI-NEXT: s_lshr_b32 s31, s26, 16
-; VI-NEXT: s_lshr_b32 s68, s25, 16
-; VI-NEXT: s_lshr_b32 s70, s24, 16
-; VI-NEXT: s_lshr_b32 s81, s23, 16
-; VI-NEXT: s_lshr_b32 s84, s22, 16
-; VI-NEXT: s_lshr_b32 s86, s21, 16
-; VI-NEXT: s_lshr_b32 s87, s20, 16
-; VI-NEXT: s_lshr_b32 s7, s19, 16
-; VI-NEXT: s_lshr_b32 s9, s18, 16
-; VI-NEXT: s_lshr_b32 s11, s17, 16
-; VI-NEXT: s_lshr_b32 s13, s16, 16
+; VI-NEXT: s_lshr_b32 s73, s28, 16
+; VI-NEXT: s_lshr_b32 s47, s27, 16
+; VI-NEXT: s_lshr_b32 s46, s26, 16
+; VI-NEXT: s_lshr_b32 s45, s25, 16
+; VI-NEXT: s_lshr_b32 s44, s24, 16
+; VI-NEXT: s_lshr_b32 s43, s23, 16
+; VI-NEXT: s_lshr_b32 s42, s22, 16
+; VI-NEXT: s_lshr_b32 s7, s21, 16
+; VI-NEXT: s_lshr_b32 s9, s20, 16
+; VI-NEXT: s_lshr_b32 s11, s19, 16
+; VI-NEXT: s_lshr_b32 s13, s18, 16
+; VI-NEXT: s_lshr_b32 s41, s17, 16
+; VI-NEXT: s_lshr_b32 s5, s16, 16
; VI-NEXT: s_lshr_b32 s63, s6, 16
+; VI-NEXT: s_lshr_b32 s15, s8, 16
+; VI-NEXT: s_lshr_b32 s61, s10, 16
; VI-NEXT: s_lshr_b32 s60, s12, 16
; VI-NEXT: s_lshr_b32 s59, s14, 16
; VI-NEXT: s_lshr_b32 s58, s72, 16
; VI-NEXT: s_lshr_b32 s57, s74, 16
; VI-NEXT: s_lshr_b32 s62, s76, 16
-; VI-NEXT: s_lshr_b32 s89, s79, 16
-; VI-NEXT: s_lshr_b32 s30, s91, 16
-; VI-NEXT: s_lshr_b32 s35, s34, 16
-; VI-NEXT: s_lshr_b32 s71, s69, 16
-; VI-NEXT: s_lshr_b32 s82, s80, 16
-; VI-NEXT: s_lshr_b32 s85, s83, 16
+; VI-NEXT: s_lshr_b32 s75, s79, 16
+; VI-NEXT: s_lshr_b32 s77, s91, 16
+; VI-NEXT: s_lshr_b32 s78, s34, 16
+; VI-NEXT: s_lshr_b32 s88, s69, 16
+; VI-NEXT: s_lshr_b32 s89, s80, 16
+; VI-NEXT: s_lshr_b32 vcc_lo, s83, 16
; VI-NEXT: v_readfirstlane_b32 s4, v14
-; VI-NEXT: v_writelane_b32 v33, s61, 1
+; VI-NEXT: v_writelane_b32 v32, s86, 30
; VI-NEXT: s_cmp_lg_u32 s4, 0
-; VI-NEXT: v_writelane_b32 v33, s60, 2
-; VI-NEXT: v_writelane_b32 v33, s59, 3
+; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_cbranch_scc0 .LBB47_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_lshl_b32 s5, s5, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s11, 16
+; VI-NEXT: s_mov_b32 s70, s41
+; VI-NEXT: s_lshl_b32 s41, s41, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s86, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
-; VI-NEXT: s_lshl_b32 s5, s84, 16
+; VI-NEXT: s_lshl_b32 s5, s42, 16
+; VI-NEXT: s_mov_b32 s30, s11
+; VI-NEXT: s_mov_b32 s11, s7
+; VI-NEXT: s_mov_b32 s7, s42
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
-; VI-NEXT: s_lshl_b32 s5, s81, 16
+; VI-NEXT: s_lshl_b32 s5, s43, 16
+; VI-NEXT: s_mov_b32 s86, s43
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
-; VI-NEXT: s_lshl_b32 s5, s70, 16
+; VI-NEXT: s_lshl_b32 s5, s44, 16
+; VI-NEXT: s_mov_b32 s84, s44
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
-; VI-NEXT: s_lshl_b32 s5, s68, 16
+; VI-NEXT: s_lshl_b32 s5, s45, 16
+; VI-NEXT: s_mov_b32 s82, s45
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
-; VI-NEXT: s_lshl_b32 s5, s31, 16
+; VI-NEXT: s_lshl_b32 s5, s46, 16
+; VI-NEXT: s_mov_b32 s71, s46
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
-; VI-NEXT: s_lshl_b32 s5, s90, 16
+; VI-NEXT: s_lshl_b32 s5, s47, 16
+; VI-NEXT: s_mov_b32 s68, s47
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s83
-; VI-NEXT: s_lshl_b32 s5, s85, 16
+; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s80
-; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s69
-; VI-NEXT: s_lshl_b32 s5, s71, 16
+; VI-NEXT: s_lshl_b32 s5, s88, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s34
-; VI-NEXT: s_lshl_b32 s5, s35, 16
+; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
-; VI-NEXT: s_lshl_b32 s5, s30, 16
+; VI-NEXT: s_lshl_b32 s5, s77, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s79
-; VI-NEXT: s_lshl_b32 s5, s89, 16
+; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s62, 16
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s90, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s75, s57
+; VI-NEXT: s_mov_b32 s87, s89
+; VI-NEXT: s_mov_b32 s89, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s72
; VI-NEXT: s_lshl_b32 s5, s58, 16
-; VI-NEXT: s_mov_b32 s78, s58
+; VI-NEXT: s_mov_b32 s85, s88
+; VI-NEXT: s_mov_b32 s88, s78
+; VI-NEXT: s_mov_b32 s78, s77
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s58
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s14
; VI-NEXT: s_lshl_b32 s5, s59, 16
@@ -32978,122 +32945,126 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s15, 16
-; VI-NEXT: s_mov_b32 s88, s62
+; VI-NEXT: s_mov_b32 s31, s73
+; VI-NEXT: s_mov_b32 s73, s62
; VI-NEXT: s_or_b32 s62, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s63, 16
+; VI-NEXT: s_mov_b32 s35, s13
+; VI-NEXT: s_mov_b32 s13, s9
+; VI-NEXT: s_mov_b32 s9, vcc_lo
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v27, 0x200
-; VI-NEXT: v_mov_b32_e32 v0, s13
-; VI-NEXT: v_mov_b32_e32 v2, s11
+; VI-NEXT: v_mov_b32_e32 v0, s81
+; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v0, v0, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v27
; VI-NEXT: v_add_f16_sdwa v2, v2, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v27
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
-; VI-NEXT: v_mov_b32_e32 v2, s9
+; VI-NEXT: v_mov_b32_e32 v2, s35
; VI-NEXT: v_add_f16_sdwa v2, v2, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v27
; VI-NEXT: v_or_b32_e32 v2, v3, v2
-; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v3, s30
; VI-NEXT: v_add_f16_sdwa v3, v3, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v27
; VI-NEXT: v_or_b32_e32 v3, v4, v3
-; VI-NEXT: v_mov_b32_e32 v4, s87
+; VI-NEXT: v_mov_b32_e32 v4, s13
; VI-NEXT: v_add_f16_sdwa v4, v4, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v27
; VI-NEXT: v_or_b32_e32 v4, v5, v4
-; VI-NEXT: v_mov_b32_e32 v5, s86
+; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_add_f16_sdwa v5, v5, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v27
; VI-NEXT: v_or_b32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s84
+; VI-NEXT: v_mov_b32_e32 v6, s7
; VI-NEXT: v_add_f16_sdwa v6, v6, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v27
; VI-NEXT: v_or_b32_e32 v6, v7, v6
-; VI-NEXT: v_mov_b32_e32 v7, s81
+; VI-NEXT: v_mov_b32_e32 v7, s86
; VI-NEXT: v_add_f16_sdwa v7, v7, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v27
; VI-NEXT: v_or_b32_e32 v7, v8, v7
-; VI-NEXT: v_mov_b32_e32 v8, s70
+; VI-NEXT: v_mov_b32_e32 v8, s84
; VI-NEXT: v_add_f16_sdwa v8, v8, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v27
; VI-NEXT: v_or_b32_e32 v8, v9, v8
-; VI-NEXT: v_mov_b32_e32 v9, s68
+; VI-NEXT: v_mov_b32_e32 v9, s82
; VI-NEXT: v_add_f16_sdwa v9, v9, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v27
; VI-NEXT: v_or_b32_e32 v9, v10, v9
-; VI-NEXT: v_mov_b32_e32 v10, s31
+; VI-NEXT: v_mov_b32_e32 v10, s71
; VI-NEXT: v_add_f16_sdwa v10, v10, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v27
; VI-NEXT: v_or_b32_e32 v10, v11, v10
-; VI-NEXT: v_mov_b32_e32 v11, s90
+; VI-NEXT: v_mov_b32_e32 v11, s68
; VI-NEXT: v_add_f16_sdwa v11, v11, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v27
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s73
+; VI-NEXT: v_mov_b32_e32 v12, s31
; VI-NEXT: v_add_f16_sdwa v12, v12, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v27
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s77
+; VI-NEXT: v_mov_b32_e32 v13, s90
; VI-NEXT: v_add_f16_sdwa v13, v13, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v27
; VI-NEXT: v_or_b32_e32 v13, v14, v13
-; VI-NEXT: v_mov_b32_e32 v14, s85
+; VI-NEXT: v_mov_b32_e32 v14, s9
; VI-NEXT: v_add_f16_sdwa v14, v14, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s83, v27
; VI-NEXT: v_or_b32_e32 v14, v15, v14
-; VI-NEXT: v_mov_b32_e32 v15, s82
+; VI-NEXT: v_mov_b32_e32 v15, s87
; VI-NEXT: v_add_f16_sdwa v15, v15, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s80, v27
; VI-NEXT: v_or_b32_e32 v15, v16, v15
-; VI-NEXT: v_mov_b32_e32 v16, s71
+; VI-NEXT: v_mov_b32_e32 v16, s85
; VI-NEXT: v_add_f16_sdwa v16, v16, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s69, v27
; VI-NEXT: v_or_b32_e32 v16, v17, v16
-; VI-NEXT: v_mov_b32_e32 v17, s35
+; VI-NEXT: v_mov_b32_e32 v17, s88
; VI-NEXT: v_add_f16_sdwa v17, v17, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s34, v27
; VI-NEXT: v_or_b32_e32 v17, v18, v17
-; VI-NEXT: v_mov_b32_e32 v18, s30
+; VI-NEXT: v_mov_b32_e32 v18, s78
; VI-NEXT: v_add_f16_sdwa v18, v18, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s91, v27
; VI-NEXT: v_or_b32_e32 v18, v19, v18
-; VI-NEXT: v_mov_b32_e32 v19, s89
+; VI-NEXT: v_mov_b32_e32 v19, s77
; VI-NEXT: v_add_f16_sdwa v19, v19, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s79, v27
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s88
+; VI-NEXT: v_mov_b32_e32 v20, s73
; VI-NEXT: v_add_f16_sdwa v20, v20, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s76, v27
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s75
+; VI-NEXT: v_mov_b32_e32 v21, s89
; VI-NEXT: v_add_f16_sdwa v21, v21, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s74, v27
; VI-NEXT: v_or_b32_e32 v21, v22, v21
-; VI-NEXT: v_mov_b32_e32 v22, s78
+; VI-NEXT: v_mov_b32_e32 v22, s75
; VI-NEXT: v_add_f16_sdwa v22, v22, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s72, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 3
+; VI-NEXT: s_lshr_b32 s4, s14, 16
; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_mov_b32_e32 v23, s4
; VI-NEXT: v_add_f16_sdwa v23, v23, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s14, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 2
+; VI-NEXT: s_lshr_b32 s4, s12, 16
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_mov_b32_e32 v24, s4
; VI-NEXT: v_add_f16_sdwa v24, v24, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s12, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 1
+; VI-NEXT: s_lshr_b32 s4, s10, 16
; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: v_mov_b32_e32 v25, s4
; VI-NEXT: v_add_f16_sdwa v25, v25, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, s10, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 0
+; VI-NEXT: s_lshr_b32 s4, s8, 16
; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: v_mov_b32_e32 v26, s4
; VI-NEXT: v_add_f16_sdwa v26, v26, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
@@ -33105,11 +33076,29 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: s_branch .LBB47_5
; VI-NEXT: .LBB47_3:
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s88, s62
-; VI-NEXT: s_mov_b32 s77, s56
-; VI-NEXT: s_mov_b32 s75, s57
-; VI-NEXT: s_mov_b32 s78, s58
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_mov_b32 s70, s41
+; VI-NEXT: s_mov_b32 s35, s13
+; VI-NEXT: s_mov_b32 s30, s11
+; VI-NEXT: s_mov_b32 s13, s9
+; VI-NEXT: s_mov_b32 s11, s7
+; VI-NEXT: s_mov_b32 s9, vcc_lo
+; VI-NEXT: s_mov_b32 s7, s42
+; VI-NEXT: s_mov_b32 s87, s89
+; VI-NEXT: s_mov_b32 s86, s43
+; VI-NEXT: s_mov_b32 s85, s88
+; VI-NEXT: s_mov_b32 s84, s44
+; VI-NEXT: s_mov_b32 s82, s45
+; VI-NEXT: s_mov_b32 s88, s78
+; VI-NEXT: s_mov_b32 s71, s46
+; VI-NEXT: s_mov_b32 s78, s77
+; VI-NEXT: s_mov_b32 s68, s47
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s31, s73
+; VI-NEXT: s_mov_b32 s73, s62
+; VI-NEXT: s_mov_b32 s90, s56
+; VI-NEXT: s_mov_b32 s89, s57
+; VI-NEXT: s_mov_b32 s75, s58
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB47_2
@@ -33181,7 +33170,6 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_readlane_b32 s30, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -37216,13 +37204,13 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: v_writelane_b32 v28, s85, 29
; VI-NEXT: v_writelane_b32 v28, s86, 30
; VI-NEXT: v_writelane_b32 v28, s87, 31
-; VI-NEXT: v_readfirstlane_b32 s86, v13
+; VI-NEXT: v_readfirstlane_b32 s87, v13
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: v_readfirstlane_b32 s9, v11
; VI-NEXT: v_readfirstlane_b32 s8, v10
-; VI-NEXT: v_readfirstlane_b32 s87, v9
-; VI-NEXT: v_readfirstlane_b32 s12, v8
-; VI-NEXT: v_readfirstlane_b32 s73, v7
+; VI-NEXT: v_readfirstlane_b32 s10, v9
+; VI-NEXT: v_readfirstlane_b32 s73, v8
+; VI-NEXT: v_readfirstlane_b32 s75, v7
; VI-NEXT: v_readfirstlane_b32 s77, v6
; VI-NEXT: v_readfirstlane_b32 s88, v5
; VI-NEXT: v_readfirstlane_b32 s91, v4
@@ -37238,19 +37226,19 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_lshr_b32 s80, s24, 16
; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_lshr_b32 s85, s22, 16
-; VI-NEXT: s_lshr_b32 s7, s21, 16
-; VI-NEXT: s_lshr_b32 s11, s20, 16
-; VI-NEXT: s_lshr_b32 s13, s19, 16
-; VI-NEXT: s_lshr_b32 s15, s18, 16
-; VI-NEXT: s_lshr_b32 s10, s17, 16
-; VI-NEXT: s_lshr_b32 s75, s16, 16
-; VI-NEXT: s_lshr_b32 s64, s86, 16
+; VI-NEXT: s_lshr_b32 s86, s21, 16
+; VI-NEXT: s_lshr_b32 s7, s20, 16
+; VI-NEXT: s_lshr_b32 s11, s19, 16
+; VI-NEXT: s_lshr_b32 s13, s18, 16
+; VI-NEXT: s_lshr_b32 s15, s17, 16
+; VI-NEXT: s_lshr_b32 s12, s16, 16
+; VI-NEXT: s_lshr_b32 s64, s87, 16
; VI-NEXT: s_lshr_b32 s65, s6, 16
; VI-NEXT: s_lshr_b32 s66, s9, 16
; VI-NEXT: s_lshr_b32 s14, s8, 16
-; VI-NEXT: s_lshr_b32 s72, s87, 16
-; VI-NEXT: s_lshr_b32 s74, s12, 16
-; VI-NEXT: s_lshr_b32 s76, s73, 16
+; VI-NEXT: s_lshr_b32 s72, s10, 16
+; VI-NEXT: s_lshr_b32 s74, s73, 16
+; VI-NEXT: s_lshr_b32 s76, s75, 16
; VI-NEXT: s_lshr_b32 s78, s77, 16
; VI-NEXT: s_lshr_b32 s89, s88, 16
; VI-NEXT: s_lshr_b32 s30, s91, 16
@@ -37260,25 +37248,27 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_lshr_b32 s83, s84, 16
; VI-NEXT: v_readfirstlane_b32 s4, v14
; VI-NEXT: s_cmp_lg_u32 s4, 0
+; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
+; VI-NEXT: v_writelane_b32 v29, s10, 0
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s10, 16
+; VI-NEXT: s_lshl_b32 s41, s15, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
; VI-NEXT: s_lshl_b32 s5, s85, 16
@@ -37325,13 +37315,13 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s56, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s73
+; VI-NEXT: s_and_b32 s4, 0xffff, s75
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s57, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s12
+; VI-NEXT: s_and_b32 s4, 0xffff, s73
; VI-NEXT: s_lshl_b32 s5, s74, 16
; VI-NEXT: s_or_b32 s58, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s87
+; VI-NEXT: s_and_b32 s4, 0xffff, s10
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
@@ -37343,39 +37333,39 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s62, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s86
+; VI-NEXT: s_and_b32 s4, 0xffff, s87
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s17, 0xffff
-; VI-NEXT: s_lshl_b32 s10, s10, 16
+; VI-NEXT: s_lshl_b32 s10, s15, 16
; VI-NEXT: s_or_b32 s5, s10, s5
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s36, s4, 0x30000
; VI-NEXT: s_add_i32 s37, s5, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s38, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s19, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s21, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s86, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s41, s4, 0x30000
@@ -37452,18 +37442,19 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, s77, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s75, s73, 3
+; VI-NEXT: s_add_i32 s75, s75, 3
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s75, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s73, s12, 3
+; VI-NEXT: s_add_i32 s73, s73, 3
; VI-NEXT: s_add_i32 s57, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s73, 0xffff
; VI-NEXT: s_lshl_b32 s5, s74, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s15, s87, 3
; VI-NEXT: s_add_i32 s58, s4, 0x30000
+; VI-NEXT: v_readlane_b32 s4, v29, 0
+; VI-NEXT: s_add_i32 s15, s4, 3
; VI-NEXT: s_and_b32 s4, s15, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
@@ -37482,7 +37473,7 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, s9, 0xffff
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s7, s86, 3
+; VI-NEXT: s_add_i32 s7, s87, 3
; VI-NEXT: s_add_i32 s62, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s7, 0xffff
; VI-NEXT: s_lshl_b32 s5, s64, 16
@@ -37556,24 +37547,8 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB51_4:
-; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b32 vcc_lo, s64
-; VI-NEXT: v_writelane_b32 v29, s75, 0
; VI-NEXT: s_mov_b32 vcc_hi, s65
-; VI-NEXT: s_mov_b32 s75, s73
-; VI-NEXT: s_mov_b32 s73, s12
-; VI-NEXT: v_writelane_b32 v29, s25, 1
-; VI-NEXT: s_mov_b32 s25, s91
-; VI-NEXT: s_mov_b32 s91, s26
-; VI-NEXT: s_mov_b32 s26, s27
-; VI-NEXT: s_mov_b32 s27, s88
-; VI-NEXT: s_mov_b32 s88, s28
-; VI-NEXT: s_mov_b32 s28, s77
-; VI-NEXT: s_mov_b32 s77, s29
-; VI-NEXT: s_mov_b32 s29, s15
-; VI-NEXT: s_mov_b32 s15, s87
-; VI-NEXT: s_mov_b32 s87, s85
-; VI-NEXT: s_mov_b32 s85, s82
; VI-NEXT: s_mov_b32 s82, s71
; VI-NEXT: s_mov_b32 s71, s68
; VI-NEXT: s_mov_b32 s68, s35
@@ -37588,15 +37563,12 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s74, s72
; VI-NEXT: s_mov_b32 s72, s14
; VI-NEXT: s_mov_b32 s14, s66
-; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s13
-; VI-NEXT: s_mov_b32 s13, s8
-; VI-NEXT: s_mov_b32 s8, s11
-; VI-NEXT: s_mov_b32 s11, s9
-; VI-NEXT: s_mov_b32 s9, s6
-; VI-NEXT: s_mov_b32 s6, s7
+; VI-NEXT: s_mov_b32 s13, s11
+; VI-NEXT: s_mov_b32 s11, s7
; VI-NEXT: s_mov_b32 s7, s86
-; VI-NEXT: s_mov_b32 s86, s83
+; VI-NEXT: s_mov_b32 s86, s85
+; VI-NEXT: s_mov_b32 s85, s83
; VI-NEXT: s_mov_b32 s83, s80
; VI-NEXT: s_mov_b32 s80, s70
; VI-NEXT: s_mov_b32 s70, s67
@@ -37604,15 +37576,12 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s67, s70
; VI-NEXT: s_mov_b32 s70, s80
; VI-NEXT: s_mov_b32 s80, s83
-; VI-NEXT: s_mov_b32 s83, s86
+; VI-NEXT: s_mov_b32 s83, s85
+; VI-NEXT: s_mov_b32 s85, s86
; VI-NEXT: s_mov_b32 s86, s7
-; VI-NEXT: s_mov_b32 s7, s6
-; VI-NEXT: s_mov_b32 s6, s9
-; VI-NEXT: s_mov_b32 s9, s11
-; VI-NEXT: s_mov_b32 s11, s8
-; VI-NEXT: s_mov_b32 s8, s13
+; VI-NEXT: s_mov_b32 s7, s11
+; VI-NEXT: s_mov_b32 s11, s13
; VI-NEXT: s_mov_b32 s13, s10
-; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s66, s14
; VI-NEXT: s_mov_b32 s14, s72
; VI-NEXT: s_mov_b32 s72, s74
@@ -37627,21 +37596,7 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s35, s68
; VI-NEXT: s_mov_b32 s68, s71
; VI-NEXT: s_mov_b32 s71, s82
-; VI-NEXT: s_mov_b32 s82, s85
-; VI-NEXT: s_mov_b32 s85, s87
-; VI-NEXT: s_mov_b32 s87, s15
-; VI-NEXT: s_mov_b32 s15, s29
-; VI-NEXT: s_mov_b32 s29, s77
-; VI-NEXT: s_mov_b32 s77, s28
-; VI-NEXT: s_mov_b32 s28, s88
-; VI-NEXT: s_mov_b32 s88, s27
-; VI-NEXT: s_mov_b32 s27, s26
-; VI-NEXT: s_mov_b32 s26, s91
-; VI-NEXT: s_mov_b32 s91, s25
-; VI-NEXT: v_readlane_b32 s25, v29, 1
-; VI-NEXT: s_mov_b32 s12, s73
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: v_readlane_b32 s75, v29, 0
+; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_mov_b32 s65, vcc_hi
; VI-NEXT: s_mov_b32 s64, vcc_lo
; VI-NEXT: s_branch .LBB51_2
@@ -41868,7 +41823,6 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s30, 0
; VI-NEXT: v_writelane_b32 v32, s31, 1
@@ -41899,14 +41853,9 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: v_writelane_b32 v32, s82, 26
; VI-NEXT: v_writelane_b32 v32, s83, 27
; VI-NEXT: v_writelane_b32 v32, s84, 28
+; VI-NEXT: v_readfirstlane_b32 s6, v13
; VI-NEXT: v_readfirstlane_b32 s8, v12
-; VI-NEXT: v_writelane_b32 v32, s85, 29
-; VI-NEXT: s_lshr_b32 s15, s8, 16
; VI-NEXT: v_readfirstlane_b32 s10, v11
-; VI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
-; VI-NEXT: v_writelane_b32 v32, s86, 30
-; VI-NEXT: v_readfirstlane_b32 s6, v13
-; VI-NEXT: s_lshr_b32 s61, s10, 16
; VI-NEXT: v_readfirstlane_b32 s12, v10
; VI-NEXT: v_readfirstlane_b32 s14, v9
; VI-NEXT: v_readfirstlane_b32 s72, v8
@@ -41918,113 +41867,127 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: v_readfirstlane_b32 s69, v2
; VI-NEXT: v_readfirstlane_b32 s80, v1
; VI-NEXT: v_readfirstlane_b32 s83, v0
-; VI-NEXT: v_writelane_b32 v33, s15, 0
-; VI-NEXT: v_writelane_b32 v32, s87, 31
+; VI-NEXT: v_writelane_b32 v32, s85, 29
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s75, s28, 16
-; VI-NEXT: s_lshr_b32 s90, s27, 16
-; VI-NEXT: s_lshr_b32 s31, s26, 16
-; VI-NEXT: s_lshr_b32 s68, s25, 16
-; VI-NEXT: s_lshr_b32 s70, s24, 16
-; VI-NEXT: s_lshr_b32 s81, s23, 16
-; VI-NEXT: s_lshr_b32 s84, s22, 16
-; VI-NEXT: s_lshr_b32 s86, s21, 16
-; VI-NEXT: s_lshr_b32 s87, s20, 16
-; VI-NEXT: s_lshr_b32 s7, s19, 16
-; VI-NEXT: s_lshr_b32 s9, s18, 16
-; VI-NEXT: s_lshr_b32 s11, s17, 16
-; VI-NEXT: s_lshr_b32 s13, s16, 16
+; VI-NEXT: s_lshr_b32 s73, s28, 16
+; VI-NEXT: s_lshr_b32 s47, s27, 16
+; VI-NEXT: s_lshr_b32 s46, s26, 16
+; VI-NEXT: s_lshr_b32 s45, s25, 16
+; VI-NEXT: s_lshr_b32 s44, s24, 16
+; VI-NEXT: s_lshr_b32 s43, s23, 16
+; VI-NEXT: s_lshr_b32 s42, s22, 16
+; VI-NEXT: s_lshr_b32 s7, s21, 16
+; VI-NEXT: s_lshr_b32 s9, s20, 16
+; VI-NEXT: s_lshr_b32 s11, s19, 16
+; VI-NEXT: s_lshr_b32 s13, s18, 16
+; VI-NEXT: s_lshr_b32 s41, s17, 16
+; VI-NEXT: s_lshr_b32 s5, s16, 16
; VI-NEXT: s_lshr_b32 s63, s6, 16
+; VI-NEXT: s_lshr_b32 s15, s8, 16
+; VI-NEXT: s_lshr_b32 s61, s10, 16
; VI-NEXT: s_lshr_b32 s60, s12, 16
; VI-NEXT: s_lshr_b32 s59, s14, 16
; VI-NEXT: s_lshr_b32 s58, s72, 16
; VI-NEXT: s_lshr_b32 s57, s74, 16
; VI-NEXT: s_lshr_b32 s62, s76, 16
-; VI-NEXT: s_lshr_b32 s89, s79, 16
-; VI-NEXT: s_lshr_b32 s30, s91, 16
-; VI-NEXT: s_lshr_b32 s35, s34, 16
-; VI-NEXT: s_lshr_b32 s71, s69, 16
-; VI-NEXT: s_lshr_b32 s82, s80, 16
-; VI-NEXT: s_lshr_b32 s85, s83, 16
+; VI-NEXT: s_lshr_b32 s75, s79, 16
+; VI-NEXT: s_lshr_b32 s77, s91, 16
+; VI-NEXT: s_lshr_b32 s78, s34, 16
+; VI-NEXT: s_lshr_b32 s88, s69, 16
+; VI-NEXT: s_lshr_b32 s89, s80, 16
+; VI-NEXT: s_lshr_b32 vcc_lo, s83, 16
; VI-NEXT: v_readfirstlane_b32 s4, v14
-; VI-NEXT: v_writelane_b32 v33, s61, 1
+; VI-NEXT: v_writelane_b32 v32, s86, 30
; VI-NEXT: s_cmp_lg_u32 s4, 0
-; VI-NEXT: v_writelane_b32 v33, s60, 2
-; VI-NEXT: v_writelane_b32 v33, s59, 3
+; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_cbranch_scc0 .LBB55_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_lshl_b32 s5, s5, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s7, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s11, 16
+; VI-NEXT: s_mov_b32 s70, s41
+; VI-NEXT: s_lshl_b32 s41, s41, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s86, 16
+; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
-; VI-NEXT: s_lshl_b32 s5, s84, 16
+; VI-NEXT: s_lshl_b32 s5, s42, 16
+; VI-NEXT: s_mov_b32 s30, s11
+; VI-NEXT: s_mov_b32 s11, s7
+; VI-NEXT: s_mov_b32 s7, s42
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
-; VI-NEXT: s_lshl_b32 s5, s81, 16
+; VI-NEXT: s_lshl_b32 s5, s43, 16
+; VI-NEXT: s_mov_b32 s86, s43
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
-; VI-NEXT: s_lshl_b32 s5, s70, 16
+; VI-NEXT: s_lshl_b32 s5, s44, 16
+; VI-NEXT: s_mov_b32 s84, s44
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
-; VI-NEXT: s_lshl_b32 s5, s68, 16
+; VI-NEXT: s_lshl_b32 s5, s45, 16
+; VI-NEXT: s_mov_b32 s82, s45
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
-; VI-NEXT: s_lshl_b32 s5, s31, 16
+; VI-NEXT: s_lshl_b32 s5, s46, 16
+; VI-NEXT: s_mov_b32 s71, s46
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
-; VI-NEXT: s_lshl_b32 s5, s90, 16
+; VI-NEXT: s_lshl_b32 s5, s47, 16
+; VI-NEXT: s_mov_b32 s68, s47
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s83
-; VI-NEXT: s_lshl_b32 s5, s85, 16
+; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s80
-; VI-NEXT: s_lshl_b32 s5, s82, 16
+; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s69
-; VI-NEXT: s_lshl_b32 s5, s71, 16
+; VI-NEXT: s_lshl_b32 s5, s88, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s34
-; VI-NEXT: s_lshl_b32 s5, s35, 16
+; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
-; VI-NEXT: s_lshl_b32 s5, s30, 16
+; VI-NEXT: s_lshl_b32 s5, s77, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s79
-; VI-NEXT: s_lshl_b32 s5, s89, 16
+; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s62, 16
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s90, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s75, s57
+; VI-NEXT: s_mov_b32 s87, s89
+; VI-NEXT: s_mov_b32 s89, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s72
; VI-NEXT: s_lshl_b32 s5, s58, 16
-; VI-NEXT: s_mov_b32 s78, s58
+; VI-NEXT: s_mov_b32 s85, s88
+; VI-NEXT: s_mov_b32 s88, s78
+; VI-NEXT: s_mov_b32 s78, s77
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s58
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s14
; VI-NEXT: s_lshl_b32 s5, s59, 16
@@ -42037,122 +42000,126 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s15, 16
-; VI-NEXT: s_mov_b32 s88, s62
+; VI-NEXT: s_mov_b32 s31, s73
+; VI-NEXT: s_mov_b32 s73, s62
; VI-NEXT: s_or_b32 s62, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s63, 16
+; VI-NEXT: s_mov_b32 s35, s13
+; VI-NEXT: s_mov_b32 s13, s9
+; VI-NEXT: s_mov_b32 s9, vcc_lo
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB55_4
; VI-NEXT: .LBB55_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v27, 0x200
-; VI-NEXT: v_mov_b32_e32 v0, s13
-; VI-NEXT: v_mov_b32_e32 v2, s11
+; VI-NEXT: v_mov_b32_e32 v0, s81
+; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v0, v0, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v27
; VI-NEXT: v_add_f16_sdwa v2, v2, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v27
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
-; VI-NEXT: v_mov_b32_e32 v2, s9
+; VI-NEXT: v_mov_b32_e32 v2, s35
; VI-NEXT: v_add_f16_sdwa v2, v2, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v27
; VI-NEXT: v_or_b32_e32 v2, v3, v2
-; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: v_mov_b32_e32 v3, s30
; VI-NEXT: v_add_f16_sdwa v3, v3, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v27
; VI-NEXT: v_or_b32_e32 v3, v4, v3
-; VI-NEXT: v_mov_b32_e32 v4, s87
+; VI-NEXT: v_mov_b32_e32 v4, s13
; VI-NEXT: v_add_f16_sdwa v4, v4, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v27
; VI-NEXT: v_or_b32_e32 v4, v5, v4
-; VI-NEXT: v_mov_b32_e32 v5, s86
+; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_add_f16_sdwa v5, v5, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v27
; VI-NEXT: v_or_b32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s84
+; VI-NEXT: v_mov_b32_e32 v6, s7
; VI-NEXT: v_add_f16_sdwa v6, v6, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v27
; VI-NEXT: v_or_b32_e32 v6, v7, v6
-; VI-NEXT: v_mov_b32_e32 v7, s81
+; VI-NEXT: v_mov_b32_e32 v7, s86
; VI-NEXT: v_add_f16_sdwa v7, v7, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v27
; VI-NEXT: v_or_b32_e32 v7, v8, v7
-; VI-NEXT: v_mov_b32_e32 v8, s70
+; VI-NEXT: v_mov_b32_e32 v8, s84
; VI-NEXT: v_add_f16_sdwa v8, v8, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v27
; VI-NEXT: v_or_b32_e32 v8, v9, v8
-; VI-NEXT: v_mov_b32_e32 v9, s68
+; VI-NEXT: v_mov_b32_e32 v9, s82
; VI-NEXT: v_add_f16_sdwa v9, v9, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v27
; VI-NEXT: v_or_b32_e32 v9, v10, v9
-; VI-NEXT: v_mov_b32_e32 v10, s31
+; VI-NEXT: v_mov_b32_e32 v10, s71
; VI-NEXT: v_add_f16_sdwa v10, v10, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v27
; VI-NEXT: v_or_b32_e32 v10, v11, v10
-; VI-NEXT: v_mov_b32_e32 v11, s90
+; VI-NEXT: v_mov_b32_e32 v11, s68
; VI-NEXT: v_add_f16_sdwa v11, v11, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v27
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s73
+; VI-NEXT: v_mov_b32_e32 v12, s31
; VI-NEXT: v_add_f16_sdwa v12, v12, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v27
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s77
+; VI-NEXT: v_mov_b32_e32 v13, s90
; VI-NEXT: v_add_f16_sdwa v13, v13, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v27
; VI-NEXT: v_or_b32_e32 v13, v14, v13
-; VI-NEXT: v_mov_b32_e32 v14, s85
+; VI-NEXT: v_mov_b32_e32 v14, s9
; VI-NEXT: v_add_f16_sdwa v14, v14, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s83, v27
; VI-NEXT: v_or_b32_e32 v14, v15, v14
-; VI-NEXT: v_mov_b32_e32 v15, s82
+; VI-NEXT: v_mov_b32_e32 v15, s87
; VI-NEXT: v_add_f16_sdwa v15, v15, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s80, v27
; VI-NEXT: v_or_b32_e32 v15, v16, v15
-; VI-NEXT: v_mov_b32_e32 v16, s71
+; VI-NEXT: v_mov_b32_e32 v16, s85
; VI-NEXT: v_add_f16_sdwa v16, v16, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s69, v27
; VI-NEXT: v_or_b32_e32 v16, v17, v16
-; VI-NEXT: v_mov_b32_e32 v17, s35
+; VI-NEXT: v_mov_b32_e32 v17, s88
; VI-NEXT: v_add_f16_sdwa v17, v17, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s34, v27
; VI-NEXT: v_or_b32_e32 v17, v18, v17
-; VI-NEXT: v_mov_b32_e32 v18, s30
+; VI-NEXT: v_mov_b32_e32 v18, s78
; VI-NEXT: v_add_f16_sdwa v18, v18, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s91, v27
; VI-NEXT: v_or_b32_e32 v18, v19, v18
-; VI-NEXT: v_mov_b32_e32 v19, s89
+; VI-NEXT: v_mov_b32_e32 v19, s77
; VI-NEXT: v_add_f16_sdwa v19, v19, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s79, v27
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s88
+; VI-NEXT: v_mov_b32_e32 v20, s73
; VI-NEXT: v_add_f16_sdwa v20, v20, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s76, v27
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s75
+; VI-NEXT: v_mov_b32_e32 v21, s89
; VI-NEXT: v_add_f16_sdwa v21, v21, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s74, v27
; VI-NEXT: v_or_b32_e32 v21, v22, v21
-; VI-NEXT: v_mov_b32_e32 v22, s78
+; VI-NEXT: v_mov_b32_e32 v22, s75
; VI-NEXT: v_add_f16_sdwa v22, v22, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s72, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 3
+; VI-NEXT: s_lshr_b32 s4, s14, 16
; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_mov_b32_e32 v23, s4
; VI-NEXT: v_add_f16_sdwa v23, v23, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s14, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 2
+; VI-NEXT: s_lshr_b32 s4, s12, 16
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_mov_b32_e32 v24, s4
; VI-NEXT: v_add_f16_sdwa v24, v24, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s12, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 1
+; VI-NEXT: s_lshr_b32 s4, s10, 16
; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: v_mov_b32_e32 v25, s4
; VI-NEXT: v_add_f16_sdwa v25, v25, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, s10, v27
-; VI-NEXT: v_readlane_b32 s4, v33, 0
+; VI-NEXT: s_lshr_b32 s4, s8, 16
; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: v_mov_b32_e32 v26, s4
; VI-NEXT: v_add_f16_sdwa v26, v26, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
@@ -42164,11 +42131,29 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: s_branch .LBB55_5
; VI-NEXT: .LBB55_3:
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s88, s62
-; VI-NEXT: s_mov_b32 s77, s56
-; VI-NEXT: s_mov_b32 s75, s57
-; VI-NEXT: s_mov_b32 s78, s58
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_mov_b32 s70, s41
+; VI-NEXT: s_mov_b32 s35, s13
+; VI-NEXT: s_mov_b32 s30, s11
+; VI-NEXT: s_mov_b32 s13, s9
+; VI-NEXT: s_mov_b32 s11, s7
+; VI-NEXT: s_mov_b32 s9, vcc_lo
+; VI-NEXT: s_mov_b32 s7, s42
+; VI-NEXT: s_mov_b32 s87, s89
+; VI-NEXT: s_mov_b32 s86, s43
+; VI-NEXT: s_mov_b32 s85, s88
+; VI-NEXT: s_mov_b32 s84, s44
+; VI-NEXT: s_mov_b32 s82, s45
+; VI-NEXT: s_mov_b32 s88, s78
+; VI-NEXT: s_mov_b32 s71, s46
+; VI-NEXT: s_mov_b32 s78, s77
+; VI-NEXT: s_mov_b32 s68, s47
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s31, s73
+; VI-NEXT: s_mov_b32 s73, s62
+; VI-NEXT: s_mov_b32 s90, s56
+; VI-NEXT: s_mov_b32 s89, s57
+; VI-NEXT: s_mov_b32 s75, s58
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB55_2
@@ -42240,7 +42225,6 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: v_readlane_b32 s30, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -43990,33 +43974,34 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_lshr_b32 s92, s18, 16
; SI-NEXT: s_lshr_b32 s73, s17, 16
; SI-NEXT: s_lshr_b32 s77, s16, 16
-; SI-NEXT: s_lshr_b32 s78, s54, 16
+; SI-NEXT: s_lshr_b32 s88, s54, 16
; SI-NEXT: s_lshr_b32 s80, s55, 16
-; SI-NEXT: s_lshr_b32 s88, s52, 16
-; SI-NEXT: s_lshr_b32 s91, s53, 16
-; SI-NEXT: s_lshr_b32 s81, s86, 16
+; SI-NEXT: s_lshr_b32 s78, s52, 16
+; SI-NEXT: s_lshr_b32 s71, s53, 16
+; SI-NEXT: s_lshr_b32 s76, s86, 16
; SI-NEXT: s_lshr_b32 s69, s98, 16
-; SI-NEXT: s_lshr_b32 s70, s96, 16
+; SI-NEXT: s_lshr_b32 s91, s96, 16
; SI-NEXT: s_lshr_b32 s67, s83, 16
-; SI-NEXT: s_lshr_b32 s71, s85, 16
+; SI-NEXT: s_lshr_b32 s81, s85, 16
; SI-NEXT: s_lshr_b32 s51, s87, 16
-; SI-NEXT: s_lshr_b32 s68, s82, 16
+; SI-NEXT: s_lshr_b32 s70, s82, 16
; SI-NEXT: s_lshr_b32 s49, s84, 16
-; SI-NEXT: s_lshr_b32 s66, s97, 16
+; SI-NEXT: s_lshr_b32 s68, s97, 16
; SI-NEXT: s_lshr_b32 s39, s99, 16
; SI-NEXT: v_readfirstlane_b32 s4, v14
+; SI-NEXT: s_mov_b32 s66, s22
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB57_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s5, s17, 0xffff
; SI-NEXT: s_lshl_b32 s7, s73, 16
-; SI-NEXT: s_mov_b32 s76, s73
+; SI-NEXT: s_mov_b32 s22, s73
; SI-NEXT: s_or_b32 s73, s5, s7
; SI-NEXT: s_and_b32 s5, s19, 0xffff
; SI-NEXT: s_lshl_b32 s7, s75, 16
; SI-NEXT: s_lshl_b32 s72, s77, 16
-; SI-NEXT: s_mov_b32 s90, s77
+; SI-NEXT: s_mov_b32 s94, s77
; SI-NEXT: s_mov_b32 s77, s75
; SI-NEXT: s_or_b32 s75, s5, s7
; SI-NEXT: s_and_b32 s5, s21, 0xffff
@@ -44035,74 +44020,77 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_lshl_b32 s7, s64, 16
; SI-NEXT: s_or_b32 s47, s5, s7
; SI-NEXT: s_and_b32 s5, s97, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s66, 16
+; SI-NEXT: s_lshl_b32 s7, s68, 16
; SI-NEXT: s_or_b32 s45, s5, s7
; SI-NEXT: s_and_b32 s5, s82, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s68, 16
+; SI-NEXT: s_lshl_b32 s7, s70, 16
; SI-NEXT: s_or_b32 s43, s5, s7
; SI-NEXT: s_and_b32 s5, s85, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s71, 16
+; SI-NEXT: s_lshl_b32 s7, s81, 16
; SI-NEXT: s_or_b32 s41, s5, s7
; SI-NEXT: s_and_b32 s5, s96, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s70, 16
+; SI-NEXT: s_lshl_b32 s7, s91, 16
+; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_or_b32 s15, s5, s7
; SI-NEXT: s_and_b32 s5, s86, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s81, 16
-; SI-NEXT: s_and_b32 s4, s16, 0xffff
-; SI-NEXT: s_or_b32 s13, s5, s7
-; SI-NEXT: s_and_b32 s5, s52, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s88, 16
+; SI-NEXT: s_lshl_b32 s7, s76, 16
; SI-NEXT: s_or_b32 s8, s4, s72
; SI-NEXT: s_and_b32 s4, s18, 0xffff
; SI-NEXT: s_lshl_b32 s74, s92, 16
-; SI-NEXT: s_or_b32 s11, s5, s7
-; SI-NEXT: s_and_b32 s5, s54, 0xffff
+; SI-NEXT: s_or_b32 s13, s5, s7
+; SI-NEXT: s_and_b32 s5, s52, 0xffff
; SI-NEXT: s_lshl_b32 s7, s78, 16
; SI-NEXT: s_mov_b32 s9, s73
; SI-NEXT: s_lshr_b64 s[72:73], s[72:73], 16
; SI-NEXT: s_or_b32 s6, s4, s74
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s62, s93, 16
-; SI-NEXT: s_or_b32 vcc_hi, s5, s7
+; SI-NEXT: s_or_b32 s11, s5, s7
+; SI-NEXT: s_and_b32 s5, s54, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s88, 16
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v29, s72, 0
-; SI-NEXT: s_mov_b32 s7, s75
-; SI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16
; SI-NEXT: s_or_b32 s4, s4, s62
-; SI-NEXT: s_lshl_b32 s60, s95, 16
+; SI-NEXT: s_or_b32 vcc_hi, s5, s7
; SI-NEXT: v_writelane_b32 v29, s73, 1
-; SI-NEXT: s_mov_b32 s73, s76
-; SI-NEXT: s_mov_b32 s75, s77
-; SI-NEXT: s_lshr_b64 s[76:77], s[62:63], 16
-; SI-NEXT: s_and_b32 s62, s22, 0xffff
; SI-NEXT: s_mov_b32 s5, s63
+; SI-NEXT: s_lshr_b64 s[62:63], s[62:63], 16
+; SI-NEXT: v_writelane_b32 v29, s62, 2
+; SI-NEXT: s_lshl_b32 s60, s95, 16
+; SI-NEXT: v_writelane_b32 v29, s63, 3
+; SI-NEXT: s_and_b32 s62, s66, 0xffff
; SI-NEXT: s_or_b32 s62, s62, s60
; SI-NEXT: s_mov_b32 s63, s61
; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16
-; SI-NEXT: v_writelane_b32 v29, s60, 2
+; SI-NEXT: v_writelane_b32 v29, s60, 4
; SI-NEXT: s_lshl_b32 s58, s31, 16
-; SI-NEXT: v_writelane_b32 v29, s61, 3
+; SI-NEXT: v_writelane_b32 v29, s61, 5
; SI-NEXT: s_and_b32 s60, s24, 0xffff
; SI-NEXT: s_or_b32 s60, s60, s58
; SI-NEXT: s_mov_b32 s61, s59
; SI-NEXT: s_lshr_b64 s[58:59], s[58:59], 16
-; SI-NEXT: v_writelane_b32 v29, s58, 4
+; SI-NEXT: v_writelane_b32 v29, s58, 6
; SI-NEXT: s_lshl_b32 s56, s35, 16
-; SI-NEXT: v_writelane_b32 v29, s59, 5
+; SI-NEXT: v_writelane_b32 v29, s59, 7
; SI-NEXT: s_and_b32 s58, s26, 0xffff
-; SI-NEXT: s_or_b32 s58, s58, s56
-; SI-NEXT: s_mov_b32 s59, s57
-; SI-NEXT: s_lshr_b64 s[56:57], s[56:57], 16
-; SI-NEXT: v_writelane_b32 v29, s56, 6
; SI-NEXT: s_lshl_b32 s46, s37, 16
-; SI-NEXT: v_writelane_b32 v29, s57, 7
+; SI-NEXT: s_mov_b32 s73, s22
+; SI-NEXT: s_or_b32 s58, s58, s56
+; SI-NEXT: s_mov_b32 s72, s91
+; SI-NEXT: s_mov_b32 s91, s23
+; SI-NEXT: s_lshr_b64 s[22:23], s[56:57], 16
; SI-NEXT: s_and_b32 s56, s28, 0xffff
+; SI-NEXT: s_mov_b32 s59, s57
; SI-NEXT: s_or_b32 s56, s56, s46
; SI-NEXT: s_mov_b32 s57, s47
; SI-NEXT: s_lshr_b64 s[46:47], s[46:47], 16
; SI-NEXT: s_lshl_b32 s44, s39, 16
+; SI-NEXT: s_mov_b32 s7, s75
+; SI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16
; SI-NEXT: v_writelane_b32 v29, s46, 8
; SI-NEXT: s_lshl_b32 s42, s49, 16
+; SI-NEXT: s_mov_b32 s75, s77
+; SI-NEXT: s_mov_b32 s77, s94
; SI-NEXT: v_writelane_b32 v29, s47, 9
; SI-NEXT: s_and_b32 s46, s99, 0xffff
; SI-NEXT: s_mov_b32 s30, s95
@@ -44125,36 +44113,36 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_and_b32 s40, s83, 0xffff
; SI-NEXT: s_mov_b32 s38, s37
; SI-NEXT: s_lshr_b64 s[36:37], s[14:15], 16
-; SI-NEXT: s_lshl_b32 s10, s91, 16
+; SI-NEXT: s_lshl_b32 s10, s71, 16
; SI-NEXT: s_or_b32 s40, s40, s14
; SI-NEXT: s_mov_b32 s37, s38
; SI-NEXT: s_and_b32 s14, s98, 0xffff
; SI-NEXT: s_mov_b32 s48, s39
; SI-NEXT: s_lshr_b64 s[38:39], s[12:13], 16
; SI-NEXT: s_lshl_b32 vcc_lo, s80, 16
-; SI-NEXT: s_mov_b32 s72, s80
+; SI-NEXT: s_mov_b32 s90, s80
; SI-NEXT: s_mov_b32 s80, s70
-; SI-NEXT: s_mov_b32 s70, s68
-; SI-NEXT: s_mov_b32 s68, s66
-; SI-NEXT: s_mov_b32 s66, s19
+; SI-NEXT: s_mov_b32 s70, s21
; SI-NEXT: s_or_b32 s14, s14, s12
; SI-NEXT: s_mov_b32 s39, s48
; SI-NEXT: s_and_b32 s12, s53, 0xffff
-; SI-NEXT: s_mov_b32 s19, s64
+; SI-NEXT: s_mov_b32 s21, s68
+; SI-NEXT: s_mov_b32 s68, s66
+; SI-NEXT: s_mov_b32 s66, s64
; SI-NEXT: s_mov_b32 s64, s50
; SI-NEXT: s_mov_b32 s50, s49
; SI-NEXT: s_lshr_b64 s[48:49], s[10:11], 16
-; SI-NEXT: s_mov_b32 s77, s90
+; SI-NEXT: s_mov_b32 s23, s91
; SI-NEXT: s_or_b32 s12, s12, s10
; SI-NEXT: s_mov_b32 s49, s50
; SI-NEXT: s_mov_b32 s50, s64
-; SI-NEXT: s_mov_b32 s64, s19
-; SI-NEXT: s_mov_b32 s19, s66
+; SI-NEXT: s_mov_b32 s64, s66
; SI-NEXT: s_mov_b32 s66, s68
-; SI-NEXT: s_mov_b32 s68, s70
+; SI-NEXT: s_mov_b32 s68, s21
+; SI-NEXT: s_mov_b32 s21, s70
; SI-NEXT: s_mov_b32 s70, s80
+; SI-NEXT: s_mov_b32 s80, s90
; SI-NEXT: s_and_b32 s10, s55, 0xffff
-; SI-NEXT: s_mov_b32 s80, s91
; SI-NEXT: s_lshr_b64 s[90:91], vcc, 16
; SI-NEXT: s_mov_b32 s47, s45
; SI-NEXT: s_mov_b32 s45, s43
@@ -44164,8 +44152,7 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_mov_b32 s13, s11
; SI-NEXT: s_or_b32 s10, s10, vcc_lo
; SI-NEXT: s_mov_b32 s11, vcc_hi
-; SI-NEXT: s_mov_b32 s91, s80
-; SI-NEXT: s_mov_b32 s80, s72
+; SI-NEXT: s_mov_b32 s91, s72
; SI-NEXT: s_cbranch_execnz .LBB57_3
; SI-NEXT: .LBB57_2: ; %cmp.true
; SI-NEXT: s_add_i32 s55, s55, 3
@@ -44175,17 +44162,17 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_add_i32 s54, s54, 3
; SI-NEXT: s_add_i32 s10, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s54, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s78, 16
+; SI-NEXT: s_lshl_b32 s5, s88, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s53, s53, 3
; SI-NEXT: s_add_i32 s11, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s53, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s91, 16
+; SI-NEXT: s_lshl_b32 s5, s71, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s52, s52, 3
; SI-NEXT: s_add_i32 s12, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s52, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s88, 16
+; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s98, s98, 3
; SI-NEXT: s_add_i32 s13, s4, 0x30000
@@ -44195,7 +44182,7 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_add_i32 s86, s86, 3
; SI-NEXT: s_add_i32 s14, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s86, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s81, 16
+; SI-NEXT: s_lshl_b32 s5, s76, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s83, s83, 3
; SI-NEXT: s_add_i32 s15, s4, 0x30000
@@ -44205,7 +44192,7 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_add_i32 s96, s96, 3
; SI-NEXT: s_add_i32 s40, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s96, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s70, 16
+; SI-NEXT: s_lshl_b32 s5, s91, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s87, s87, 3
; SI-NEXT: s_add_i32 s41, s4, 0x30000
@@ -44215,7 +44202,7 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_add_i32 s85, s85, 3
; SI-NEXT: s_add_i32 s42, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s85, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s71, 16
+; SI-NEXT: s_lshl_b32 s5, s81, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s84, s84, 3
; SI-NEXT: s_add_i32 s43, s4, 0x30000
@@ -44225,7 +44212,7 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_add_i32 s82, s82, 3
; SI-NEXT: s_add_i32 s44, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s82, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s68, 16
+; SI-NEXT: s_lshl_b32 s5, s70, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s99, s99, 3
; SI-NEXT: s_add_i32 s45, s4, 0x30000
@@ -44235,7 +44222,7 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_add_i32 s97, s97, 3
; SI-NEXT: s_add_i32 s46, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s97, 0xffff
-; SI-NEXT: s_lshl_b32 s5, s66, 16
+; SI-NEXT: s_lshl_b32 s5, s68, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s47, s4, 0x30000
@@ -44267,7 +44254,7 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s50, 16
; SI-NEXT: s_or_b32 s4, s5, s4
-; SI-NEXT: s_add_i32 s22, s22, 3
+; SI-NEXT: s_add_i32 s22, s66, 3
; SI-NEXT: s_add_i32 s61, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
@@ -44305,24 +44292,25 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_add_i32 s8, s8, 0x30000
; SI-NEXT: s_add_i32 s9, s9, 0x30000
; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 16
+; SI-NEXT: s_add_i32 s4, s4, 0x30000
+; SI-NEXT: s_add_i32 s5, s5, 0x30000
; SI-NEXT: v_writelane_b32 v29, s16, 0
; SI-NEXT: v_writelane_b32 v29, s17, 1
-; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 16
; SI-NEXT: v_writelane_b32 v29, s16, 2
; SI-NEXT: v_writelane_b32 v29, s17, 3
-; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[62:63], 16
; SI-NEXT: v_writelane_b32 v29, s16, 4
; SI-NEXT: v_writelane_b32 v29, s17, 5
-; SI-NEXT: s_lshr_b64 s[16:17], s[58:59], 16
+; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 16
; SI-NEXT: s_add_i32 s6, s6, 0x30000
; SI-NEXT: s_add_i32 s7, s7, 0x30000
; SI-NEXT: v_writelane_b32 v29, s16, 6
-; SI-NEXT: s_add_i32 s4, s4, 0x30000
-; SI-NEXT: s_add_i32 s5, s5, 0x30000
; SI-NEXT: s_lshr_b64 s[74:75], s[6:7], 16
; SI-NEXT: v_writelane_b32 v29, s17, 7
; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 16
-; SI-NEXT: s_lshr_b64 s[76:77], s[4:5], 16
+; SI-NEXT: s_lshr_b64 s[90:91], s[10:11], 16
+; SI-NEXT: s_lshr_b64 s[22:23], s[58:59], 16
; SI-NEXT: v_writelane_b32 v29, s16, 8
; SI-NEXT: s_lshr_b64 s[94:95], s[46:47], 16
; SI-NEXT: s_lshr_b64 s[30:31], s[44:45], 16
@@ -44330,7 +44318,6 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_lshr_b64 s[36:37], s[40:41], 16
; SI-NEXT: s_lshr_b64 s[38:39], s[14:15], 16
; SI-NEXT: s_lshr_b64 s[48:49], s[12:13], 16
-; SI-NEXT: s_lshr_b64 s[90:91], s[10:11], 16
; SI-NEXT: s_lshr_b32 s73, s9, 16
; SI-NEXT: s_lshr_b32 s75, s7, 16
; SI-NEXT: s_lshr_b32 s79, s5, 16
@@ -44338,13 +44325,13 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_lshr_b32 s50, s61, 16
; SI-NEXT: s_lshr_b32 s65, s59, 16
; SI-NEXT: s_lshr_b32 s64, s57, 16
-; SI-NEXT: s_lshr_b32 s66, s47, 16
-; SI-NEXT: s_lshr_b32 s68, s45, 16
-; SI-NEXT: s_lshr_b32 s71, s43, 16
-; SI-NEXT: s_lshr_b32 s70, s41, 16
-; SI-NEXT: s_lshr_b32 s81, s15, 16
-; SI-NEXT: s_lshr_b32 s88, s13, 16
-; SI-NEXT: s_lshr_b32 s78, s11, 16
+; SI-NEXT: s_lshr_b32 s68, s47, 16
+; SI-NEXT: s_lshr_b32 s70, s45, 16
+; SI-NEXT: s_lshr_b32 s81, s43, 16
+; SI-NEXT: s_lshr_b32 s91, s41, 16
+; SI-NEXT: s_lshr_b32 s76, s15, 16
+; SI-NEXT: s_lshr_b32 s78, s13, 16
+; SI-NEXT: s_lshr_b32 s88, s11, 16
; SI-NEXT: v_writelane_b32 v29, s17, 9
; SI-NEXT: .LBB57_3: ; %end
; SI-NEXT: v_readlane_b32 s16, v29, 0
@@ -44356,37 +44343,37 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_or_b32 s9, s9, s16
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_lshl_b32 s16, s74, 16
+; SI-NEXT: v_readlane_b32 s17, v29, 1
; SI-NEXT: s_or_b32 s6, s6, s16
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_lshl_b32 s16, s75, 16
; SI-NEXT: s_or_b32 s7, s7, s16
+; SI-NEXT: v_readlane_b32 s16, v29, 2
; SI-NEXT: s_and_b32 s4, s4, 0xffff
-; SI-NEXT: s_lshl_b32 s16, s76, 16
-; SI-NEXT: v_readlane_b32 s17, v29, 1
+; SI-NEXT: s_lshl_b32 s16, s16, 16
+; SI-NEXT: v_readlane_b32 s17, v29, 3
; SI-NEXT: s_or_b32 s4, s4, s16
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s16, s79, 16
-; SI-NEXT: v_readlane_b32 s18, v29, 2
+; SI-NEXT: v_readlane_b32 s18, v29, 4
; SI-NEXT: s_or_b32 s5, s5, s16
; SI-NEXT: s_and_b32 s16, s62, 0xffff
; SI-NEXT: s_lshl_b32 s17, s18, 16
-; SI-NEXT: v_readlane_b32 s19, v29, 3
+; SI-NEXT: v_readlane_b32 s19, v29, 5
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s63, 0xffff
; SI-NEXT: s_lshl_b32 s18, s89, 16
-; SI-NEXT: v_readlane_b32 s20, v29, 4
+; SI-NEXT: v_readlane_b32 s20, v29, 6
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s18, s60, 0xffff
; SI-NEXT: s_lshl_b32 s19, s20, 16
-; SI-NEXT: v_readlane_b32 s21, v29, 5
+; SI-NEXT: v_readlane_b32 s21, v29, 7
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_and_b32 s19, s61, 0xffff
; SI-NEXT: s_lshl_b32 s20, s50, 16
-; SI-NEXT: v_readlane_b32 s22, v29, 6
; SI-NEXT: s_or_b32 s19, s19, s20
; SI-NEXT: s_and_b32 s20, s58, 0xffff
; SI-NEXT: s_lshl_b32 s21, s22, 16
-; SI-NEXT: v_readlane_b32 s23, v29, 7
; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s21, s59, 0xffff
; SI-NEXT: s_lshl_b32 s22, s65, 16
@@ -44403,43 +44390,43 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: s_lshl_b32 s25, s94, 16
; SI-NEXT: s_or_b32 s24, s24, s25
; SI-NEXT: s_and_b32 s25, s47, 0xffff
-; SI-NEXT: s_lshl_b32 s26, s66, 16
+; SI-NEXT: s_lshl_b32 s26, s68, 16
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s44, 0xffff
; SI-NEXT: s_lshl_b32 s27, s30, 16
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s45, 0xffff
-; SI-NEXT: s_lshl_b32 s28, s68, 16
+; SI-NEXT: s_lshl_b32 s28, s70, 16
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s42, 0xffff
; SI-NEXT: s_lshl_b32 s29, s34, 16
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s29, s43, 0xffff
-; SI-NEXT: s_lshl_b32 s42, s71, 16
+; SI-NEXT: s_lshl_b32 s42, s81, 16
; SI-NEXT: s_or_b32 s29, s29, s42
; SI-NEXT: s_and_b32 s40, s40, 0xffff
; SI-NEXT: s_lshl_b32 s42, s36, 16
; SI-NEXT: s_or_b32 s40, s40, s42
; SI-NEXT: s_and_b32 s41, s41, 0xffff
-; SI-NEXT: s_lshl_b32 s42, s70, 16
+; SI-NEXT: s_lshl_b32 s42, s91, 16
; SI-NEXT: s_or_b32 s41, s41, s42
; SI-NEXT: s_and_b32 s14, s14, 0xffff
; SI-NEXT: s_lshl_b32 s42, s38, 16
; SI-NEXT: s_or_b32 s14, s14, s42
; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_lshl_b32 s42, s81, 16
+; SI-NEXT: s_lshl_b32 s42, s76, 16
; SI-NEXT: s_or_b32 s15, s15, s42
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_lshl_b32 s42, s48, 16
; SI-NEXT: s_or_b32 s12, s12, s42
; SI-NEXT: s_and_b32 s13, s13, 0xffff
-; SI-NEXT: s_lshl_b32 s42, s88, 16
+; SI-NEXT: s_lshl_b32 s42, s78, 16
; SI-NEXT: s_or_b32 s13, s13, s42
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_lshl_b32 s42, s90, 16
; SI-NEXT: s_or_b32 s10, s10, s42
; SI-NEXT: s_and_b32 s11, s11, 0xffff
-; SI-NEXT: s_lshl_b32 s42, s78, 16
+; SI-NEXT: s_lshl_b32 s42, s88, 16
; SI-NEXT: s_or_b32 s11, s11, s42
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
@@ -44524,10 +44511,10 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr22
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr94
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
index d6cf0367f1b20..5a5ad885804b1 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
@@ -12031,7 +12031,6 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s30, 0
; VI-NEXT: v_writelane_b32 v32, s31, 1
@@ -12058,29 +12057,17 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_writelane_b32 v32, s70, 22
; VI-NEXT: v_writelane_b32 v32, s71, 23
; VI-NEXT: v_writelane_b32 v32, s80, 24
-; VI-NEXT: v_readfirstlane_b32 s6, v15
; VI-NEXT: v_writelane_b32 v32, s81, 25
-; VI-NEXT: s_lshr_b32 vcc_lo, s6, 16
-; VI-NEXT: v_readfirstlane_b32 s8, v14
-; VI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
; VI-NEXT: v_writelane_b32 v32, s82, 26
-; VI-NEXT: s_lshr_b32 vcc_hi, s8, 16
-; VI-NEXT: v_readfirstlane_b32 s10, v13
-; VI-NEXT: v_writelane_b32 v33, vcc_lo, 0
; VI-NEXT: v_writelane_b32 v32, s83, 27
-; VI-NEXT: s_lshr_b32 s63, s10, 16
-; VI-NEXT: v_readfirstlane_b32 s12, v12
-; VI-NEXT: v_writelane_b32 v33, vcc_hi, 1
; VI-NEXT: v_writelane_b32 v32, s84, 28
-; VI-NEXT: s_lshr_b32 s62, s12, 16
-; VI-NEXT: v_readfirstlane_b32 s14, v11
-; VI-NEXT: v_writelane_b32 v33, s63, 2
; VI-NEXT: v_writelane_b32 v32, s85, 29
-; VI-NEXT: s_lshr_b32 s61, s14, 16
+; VI-NEXT: v_readfirstlane_b32 s6, v15
+; VI-NEXT: v_readfirstlane_b32 s8, v14
+; VI-NEXT: v_readfirstlane_b32 s10, v13
+; VI-NEXT: v_readfirstlane_b32 s12, v12
+; VI-NEXT: v_readfirstlane_b32 s14, v11
; VI-NEXT: v_readfirstlane_b32 s72, v10
-; VI-NEXT: v_writelane_b32 v33, s62, 3
-; VI-NEXT: v_writelane_b32 v32, s86, 30
-; VI-NEXT: s_lshr_b32 s60, s72, 16
; VI-NEXT: v_readfirstlane_b32 s74, v9
; VI-NEXT: v_readfirstlane_b32 s76, v8
; VI-NEXT: v_readfirstlane_b32 s78, v7
@@ -12091,74 +12078,85 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s82, v2
; VI-NEXT: v_readfirstlane_b32 s85, v1
; VI-NEXT: v_readfirstlane_b32 s7, v0
-; VI-NEXT: v_writelane_b32 v33, s61, 4
-; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_lshr_b32 s56, s29, 16
; VI-NEXT: s_lshr_b32 s88, s28, 16
-; VI-NEXT: s_lshr_b32 s31, s27, 16
-; VI-NEXT: s_lshr_b32 s68, s26, 16
-; VI-NEXT: s_lshr_b32 s70, s25, 16
-; VI-NEXT: s_lshr_b32 s81, s24, 16
-; VI-NEXT: s_lshr_b32 s84, s23, 16
-; VI-NEXT: s_lshr_b32 s86, s22, 16
-; VI-NEXT: s_lshr_b32 s9, s21, 16
-; VI-NEXT: s_lshr_b32 s13, s20, 16
-; VI-NEXT: s_lshr_b32 s15, s19, 16
-; VI-NEXT: s_lshr_b32 s73, s18, 16
-; VI-NEXT: s_lshr_b32 s75, s17, 16
-; VI-NEXT: s_lshr_b32 s77, s16, 16
+; VI-NEXT: s_lshr_b32 s47, s27, 16
+; VI-NEXT: s_lshr_b32 s46, s26, 16
+; VI-NEXT: s_lshr_b32 s9, s25, 16
+; VI-NEXT: s_lshr_b32 s11, s24, 16
+; VI-NEXT: s_lshr_b32 s13, s23, 16
+; VI-NEXT: s_lshr_b32 s15, s22, 16
+; VI-NEXT: s_lshr_b32 s42, s21, 16
+; VI-NEXT: s_lshr_b32 s43, s20, 16
+; VI-NEXT: s_lshr_b32 s44, s19, 16
+; VI-NEXT: s_lshr_b32 s45, s18, 16
+; VI-NEXT: s_lshr_b32 s41, s17, 16
+; VI-NEXT: s_lshr_b32 s5, s16, 16
+; VI-NEXT: s_lshr_b32 vcc_lo, s6, 16
+; VI-NEXT: s_lshr_b32 s79, s8, 16
+; VI-NEXT: s_lshr_b32 s63, s10, 16
+; VI-NEXT: s_lshr_b32 s62, s12, 16
+; VI-NEXT: s_lshr_b32 s61, s14, 16
+; VI-NEXT: s_lshr_b32 s60, s72, 16
; VI-NEXT: s_lshr_b32 s59, s74, 16
; VI-NEXT: s_lshr_b32 s58, s76, 16
; VI-NEXT: s_lshr_b32 s57, s78, 16
-; VI-NEXT: s_lshr_b32 s64, s89, 16
-; VI-NEXT: s_lshr_b32 s34, s30, 16
-; VI-NEXT: s_lshr_b32 s69, s35, 16
-; VI-NEXT: s_lshr_b32 s80, s71, 16
-; VI-NEXT: s_lshr_b32 s83, s82, 16
-; VI-NEXT: s_lshr_b32 s87, s85, 16
-; VI-NEXT: s_lshr_b32 s11, s7, 16
+; VI-NEXT: s_lshr_b32 s90, s89, 16
+; VI-NEXT: s_lshr_b32 s91, s30, 16
+; VI-NEXT: s_lshr_b32 vcc_hi, s35, 16
+; VI-NEXT: s_lshr_b32 s31, s71, 16
+; VI-NEXT: s_lshr_b32 s34, s82, 16
+; VI-NEXT: s_lshr_b32 s75, s85, 16
+; VI-NEXT: s_lshr_b32 s77, s7, 16
; VI-NEXT: v_readfirstlane_b32 s4, v16
-; VI-NEXT: v_writelane_b32 v33, s60, 5
+; VI-NEXT: v_writelane_b32 v32, s86, 30
; VI-NEXT: s_cmp_lg_u32 s4, 0
-; VI-NEXT: v_writelane_b32 v33, s59, 6
-; VI-NEXT: v_writelane_b32 v33, s58, 7
+; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_cbranch_scc0 .LBB19_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s77, 16
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_lshl_b32 s5, s5, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s73, 16
+; VI-NEXT: s_lshl_b32 s5, s45, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s44, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s75, 16
+; VI-NEXT: s_mov_b32 s80, s41
+; VI-NEXT: s_lshl_b32 s41, s41, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s43, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_lshl_b32 s5, s42, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
-; VI-NEXT: s_lshl_b32 s5, s86, 16
+; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_mov_b32 s69, s42
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
-; VI-NEXT: s_lshl_b32 s5, s84, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_mov_b32 s83, s43
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
-; VI-NEXT: s_lshl_b32 s5, s81, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_mov_b32 s86, s44
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
-; VI-NEXT: s_lshl_b32 s5, s70, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_mov_b32 s70, s45
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
-; VI-NEXT: s_lshl_b32 s5, s68, 16
+; VI-NEXT: s_lshl_b32 s5, s46, 16
+; VI-NEXT: s_mov_b32 s87, s46
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
-; VI-NEXT: s_lshl_b32 s5, s31, 16
+; VI-NEXT: s_lshl_b32 s5, s47, 16
+; VI-NEXT: s_mov_b32 s84, s47
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
; VI-NEXT: s_lshl_b32 s5, s88, 16
@@ -12167,34 +12165,44 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_lshl_b32 s5, s56, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s7
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s77, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s85
-; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s82
-; VI-NEXT: s_lshl_b32 s5, s83, 16
+; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s71
-; VI-NEXT: s_lshl_b32 s5, s80, 16
+; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s35
-; VI-NEXT: s_lshl_b32 s5, s69, 16
+; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s30
-; VI-NEXT: s_lshl_b32 s5, s34, 16
+; VI-NEXT: s_lshl_b32 s5, s91, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s89
-; VI-NEXT: s_lshl_b32 s5, s64, 16
-; VI-NEXT: s_mov_b32 s91, s56
+; VI-NEXT: s_lshl_b32 s5, s90, 16
+; VI-NEXT: s_mov_b32 s68, s15
+; VI-NEXT: s_mov_b32 s15, s11
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s9, s88
+; VI-NEXT: s_mov_b32 s88, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s78
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s34
+; VI-NEXT: s_mov_b32 s34, s91
+; VI-NEXT: s_mov_b32 s91, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s58, 16
+; VI-NEXT: s_mov_b32 s73, s13
+; VI-NEXT: s_mov_b32 s13, s31
+; VI-NEXT: s_mov_b32 s31, s90
+; VI-NEXT: s_mov_b32 s90, s58
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s59, 16
@@ -12212,88 +12220,90 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
-; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
-; VI-NEXT: s_mov_b32 s90, s64
+; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s64, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
+; VI-NEXT: s_mov_b32 s79, vcc_lo
; VI-NEXT: s_or_b32 s65, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB19_4
; VI-NEXT: .LBB19_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v29, 0x200
-; VI-NEXT: v_mov_b32_e32 v0, s77
-; VI-NEXT: v_mov_b32_e32 v2, s75
+; VI-NEXT: v_mov_b32_e32 v0, s81
+; VI-NEXT: v_mov_b32_e32 v2, s80
; VI-NEXT: v_add_f16_sdwa v0, v0, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v29
; VI-NEXT: v_add_f16_sdwa v2, v2, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v29
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
-; VI-NEXT: v_mov_b32_e32 v2, s73
+; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v2, v2, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v29
; VI-NEXT: v_or_b32_e32 v2, v3, v2
-; VI-NEXT: v_mov_b32_e32 v3, s15
+; VI-NEXT: v_mov_b32_e32 v3, s86
; VI-NEXT: v_add_f16_sdwa v3, v3, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v29
; VI-NEXT: v_or_b32_e32 v3, v4, v3
-; VI-NEXT: v_mov_b32_e32 v4, s13
+; VI-NEXT: v_mov_b32_e32 v4, s83
; VI-NEXT: v_add_f16_sdwa v4, v4, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v29
; VI-NEXT: v_or_b32_e32 v4, v5, v4
-; VI-NEXT: v_mov_b32_e32 v5, s9
+; VI-NEXT: v_mov_b32_e32 v5, s69
; VI-NEXT: v_add_f16_sdwa v5, v5, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v29
; VI-NEXT: v_or_b32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s86
+; VI-NEXT: v_mov_b32_e32 v6, s68
; VI-NEXT: v_add_f16_sdwa v6, v6, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v29
; VI-NEXT: v_or_b32_e32 v6, v7, v6
-; VI-NEXT: v_mov_b32_e32 v7, s84
+; VI-NEXT: v_mov_b32_e32 v7, s73
; VI-NEXT: v_add_f16_sdwa v7, v7, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v29
; VI-NEXT: v_or_b32_e32 v7, v8, v7
-; VI-NEXT: v_mov_b32_e32 v8, s81
+; VI-NEXT: v_mov_b32_e32 v8, s15
; VI-NEXT: v_add_f16_sdwa v8, v8, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v29
; VI-NEXT: v_or_b32_e32 v8, v9, v8
-; VI-NEXT: v_mov_b32_e32 v9, s70
+; VI-NEXT: v_mov_b32_e32 v9, s11
; VI-NEXT: v_add_f16_sdwa v9, v9, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v29
; VI-NEXT: v_or_b32_e32 v9, v10, v9
-; VI-NEXT: v_mov_b32_e32 v10, s68
+; VI-NEXT: v_mov_b32_e32 v10, s87
; VI-NEXT: v_add_f16_sdwa v10, v10, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v29
; VI-NEXT: v_or_b32_e32 v10, v11, v10
-; VI-NEXT: v_mov_b32_e32 v11, s31
+; VI-NEXT: v_mov_b32_e32 v11, s84
; VI-NEXT: v_add_f16_sdwa v11, v11, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v29
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s79
+; VI-NEXT: v_mov_b32_e32 v12, s9
; VI-NEXT: v_add_f16_sdwa v12, v12, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v29
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s91
+; VI-NEXT: v_mov_b32_e32 v13, s88
; VI-NEXT: v_add_f16_sdwa v13, v13, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v29
+; VI-NEXT: s_lshr_b32 s4, s7, 16
; VI-NEXT: v_or_b32_e32 v13, v14, v13
-; VI-NEXT: v_mov_b32_e32 v14, s11
+; VI-NEXT: v_mov_b32_e32 v14, s4
; VI-NEXT: v_add_f16_sdwa v14, v14, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s7, v29
; VI-NEXT: v_or_b32_e32 v14, v15, v14
-; VI-NEXT: v_mov_b32_e32 v15, s87
+; VI-NEXT: v_mov_b32_e32 v15, s77
; VI-NEXT: v_add_f16_sdwa v15, v15, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s85, v29
; VI-NEXT: v_or_b32_e32 v15, v16, v15
-; VI-NEXT: v_mov_b32_e32 v16, s83
+; VI-NEXT: v_mov_b32_e32 v16, s75
; VI-NEXT: v_add_f16_sdwa v16, v16, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s82, v29
; VI-NEXT: v_or_b32_e32 v16, v17, v16
-; VI-NEXT: v_mov_b32_e32 v17, s80
+; VI-NEXT: v_mov_b32_e32 v17, s13
; VI-NEXT: v_add_f16_sdwa v17, v17, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s71, v29
+; VI-NEXT: s_lshr_b32 s4, s35, 16
; VI-NEXT: v_or_b32_e32 v17, v18, v17
-; VI-NEXT: v_mov_b32_e32 v18, s69
+; VI-NEXT: v_mov_b32_e32 v18, s4
; VI-NEXT: v_add_f16_sdwa v18, v18, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s35, v29
; VI-NEXT: v_or_b32_e32 v18, v19, v18
@@ -12301,60 +12311,76 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v19, v19, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s30, v29
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s90
+; VI-NEXT: v_mov_b32_e32 v20, s31
; VI-NEXT: v_add_f16_sdwa v20, v20, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s89, v29
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s88
+; VI-NEXT: v_mov_b32_e32 v21, s91
; VI-NEXT: v_add_f16_sdwa v21, v21, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s78, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 7
; VI-NEXT: v_or_b32_e32 v21, v22, v21
-; VI-NEXT: v_mov_b32_e32 v22, s4
+; VI-NEXT: v_mov_b32_e32 v22, s90
; VI-NEXT: v_add_f16_sdwa v22, v22, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s76, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 6
+; VI-NEXT: s_lshr_b32 s4, s74, 16
; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_mov_b32_e32 v23, s4
; VI-NEXT: v_add_f16_sdwa v23, v23, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s74, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 5
+; VI-NEXT: s_lshr_b32 s4, s72, 16
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_mov_b32_e32 v24, s4
; VI-NEXT: v_add_f16_sdwa v24, v24, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s72, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 4
+; VI-NEXT: s_lshr_b32 s4, s14, 16
; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: v_mov_b32_e32 v25, s4
; VI-NEXT: v_add_f16_sdwa v25, v25, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, s14, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 3
+; VI-NEXT: s_lshr_b32 s4, s12, 16
; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: v_mov_b32_e32 v26, s4
; VI-NEXT: v_add_f16_sdwa v26, v26, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, s12, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 2
+; VI-NEXT: s_lshr_b32 s4, s10, 16
; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: v_mov_b32_e32 v27, s4
; VI-NEXT: v_add_f16_sdwa v27, v27, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v28, s10, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 1
+; VI-NEXT: s_lshr_b32 s4, s8, 16
; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: v_mov_b32_e32 v28, s4
; VI-NEXT: v_add_f16_sdwa v28, v28, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v30, s8, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 0
; VI-NEXT: v_or_b32_e32 v28, v30, v28
-; VI-NEXT: v_mov_b32_e32 v30, s4
+; VI-NEXT: v_mov_b32_e32 v30, s79
; VI-NEXT: v_add_f16_sdwa v30, v30, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v29, s6, v29
; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: s_branch .LBB19_5
; VI-NEXT: .LBB19_3:
-; VI-NEXT: s_mov_b32 s90, s64
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s91, s56
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_mov_b32 s80, s41
+; VI-NEXT: s_mov_b32 s70, s45
+; VI-NEXT: s_mov_b32 s86, s44
+; VI-NEXT: s_mov_b32 s83, s43
+; VI-NEXT: s_mov_b32 s69, s42
+; VI-NEXT: s_mov_b32 s68, s15
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s34
+; VI-NEXT: s_mov_b32 s73, s13
+; VI-NEXT: s_mov_b32 s15, s11
+; VI-NEXT: s_mov_b32 s13, s31
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s87, s46
+; VI-NEXT: s_mov_b32 s34, s91
+; VI-NEXT: s_mov_b32 s84, s47
+; VI-NEXT: s_mov_b32 s31, s90
+; VI-NEXT: s_mov_b32 s9, s88
+; VI-NEXT: s_mov_b32 s88, s56
+; VI-NEXT: s_mov_b32 s91, s57
+; VI-NEXT: s_mov_b32 s90, s58
+; VI-NEXT: s_mov_b32 s79, vcc_lo
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB19_2
; VI-NEXT: .LBB19_4:
@@ -12425,7 +12451,6 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_readlane_b32 s30, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -24708,7 +24733,6 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s30, 0
; VI-NEXT: v_writelane_b32 v32, s31, 1
@@ -24735,29 +24759,17 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: v_writelane_b32 v32, s70, 22
; VI-NEXT: v_writelane_b32 v32, s71, 23
; VI-NEXT: v_writelane_b32 v32, s80, 24
-; VI-NEXT: v_readfirstlane_b32 s6, v15
; VI-NEXT: v_writelane_b32 v32, s81, 25
-; VI-NEXT: s_lshr_b32 vcc_lo, s6, 16
-; VI-NEXT: v_readfirstlane_b32 s8, v14
-; VI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
; VI-NEXT: v_writelane_b32 v32, s82, 26
-; VI-NEXT: s_lshr_b32 vcc_hi, s8, 16
-; VI-NEXT: v_readfirstlane_b32 s10, v13
-; VI-NEXT: v_writelane_b32 v33, vcc_lo, 0
; VI-NEXT: v_writelane_b32 v32, s83, 27
-; VI-NEXT: s_lshr_b32 s63, s10, 16
-; VI-NEXT: v_readfirstlane_b32 s12, v12
-; VI-NEXT: v_writelane_b32 v33, vcc_hi, 1
; VI-NEXT: v_writelane_b32 v32, s84, 28
-; VI-NEXT: s_lshr_b32 s62, s12, 16
-; VI-NEXT: v_readfirstlane_b32 s14, v11
-; VI-NEXT: v_writelane_b32 v33, s63, 2
; VI-NEXT: v_writelane_b32 v32, s85, 29
-; VI-NEXT: s_lshr_b32 s61, s14, 16
+; VI-NEXT: v_readfirstlane_b32 s6, v15
+; VI-NEXT: v_readfirstlane_b32 s8, v14
+; VI-NEXT: v_readfirstlane_b32 s10, v13
+; VI-NEXT: v_readfirstlane_b32 s12, v12
+; VI-NEXT: v_readfirstlane_b32 s14, v11
; VI-NEXT: v_readfirstlane_b32 s72, v10
-; VI-NEXT: v_writelane_b32 v33, s62, 3
-; VI-NEXT: v_writelane_b32 v32, s86, 30
-; VI-NEXT: s_lshr_b32 s60, s72, 16
; VI-NEXT: v_readfirstlane_b32 s74, v9
; VI-NEXT: v_readfirstlane_b32 s76, v8
; VI-NEXT: v_readfirstlane_b32 s78, v7
@@ -24768,74 +24780,85 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: v_readfirstlane_b32 s82, v2
; VI-NEXT: v_readfirstlane_b32 s85, v1
; VI-NEXT: v_readfirstlane_b32 s7, v0
-; VI-NEXT: v_writelane_b32 v33, s61, 4
-; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_lshr_b32 s56, s29, 16
; VI-NEXT: s_lshr_b32 s88, s28, 16
-; VI-NEXT: s_lshr_b32 s31, s27, 16
-; VI-NEXT: s_lshr_b32 s68, s26, 16
-; VI-NEXT: s_lshr_b32 s70, s25, 16
-; VI-NEXT: s_lshr_b32 s81, s24, 16
-; VI-NEXT: s_lshr_b32 s84, s23, 16
-; VI-NEXT: s_lshr_b32 s86, s22, 16
-; VI-NEXT: s_lshr_b32 s9, s21, 16
-; VI-NEXT: s_lshr_b32 s13, s20, 16
-; VI-NEXT: s_lshr_b32 s15, s19, 16
-; VI-NEXT: s_lshr_b32 s73, s18, 16
-; VI-NEXT: s_lshr_b32 s75, s17, 16
-; VI-NEXT: s_lshr_b32 s77, s16, 16
+; VI-NEXT: s_lshr_b32 s47, s27, 16
+; VI-NEXT: s_lshr_b32 s46, s26, 16
+; VI-NEXT: s_lshr_b32 s9, s25, 16
+; VI-NEXT: s_lshr_b32 s11, s24, 16
+; VI-NEXT: s_lshr_b32 s13, s23, 16
+; VI-NEXT: s_lshr_b32 s15, s22, 16
+; VI-NEXT: s_lshr_b32 s42, s21, 16
+; VI-NEXT: s_lshr_b32 s43, s20, 16
+; VI-NEXT: s_lshr_b32 s44, s19, 16
+; VI-NEXT: s_lshr_b32 s45, s18, 16
+; VI-NEXT: s_lshr_b32 s41, s17, 16
+; VI-NEXT: s_lshr_b32 s5, s16, 16
+; VI-NEXT: s_lshr_b32 vcc_lo, s6, 16
+; VI-NEXT: s_lshr_b32 s79, s8, 16
+; VI-NEXT: s_lshr_b32 s63, s10, 16
+; VI-NEXT: s_lshr_b32 s62, s12, 16
+; VI-NEXT: s_lshr_b32 s61, s14, 16
+; VI-NEXT: s_lshr_b32 s60, s72, 16
; VI-NEXT: s_lshr_b32 s59, s74, 16
; VI-NEXT: s_lshr_b32 s58, s76, 16
; VI-NEXT: s_lshr_b32 s57, s78, 16
-; VI-NEXT: s_lshr_b32 s64, s89, 16
-; VI-NEXT: s_lshr_b32 s34, s30, 16
-; VI-NEXT: s_lshr_b32 s69, s35, 16
-; VI-NEXT: s_lshr_b32 s80, s71, 16
-; VI-NEXT: s_lshr_b32 s83, s82, 16
-; VI-NEXT: s_lshr_b32 s87, s85, 16
-; VI-NEXT: s_lshr_b32 s11, s7, 16
+; VI-NEXT: s_lshr_b32 s90, s89, 16
+; VI-NEXT: s_lshr_b32 s91, s30, 16
+; VI-NEXT: s_lshr_b32 vcc_hi, s35, 16
+; VI-NEXT: s_lshr_b32 s31, s71, 16
+; VI-NEXT: s_lshr_b32 s34, s82, 16
+; VI-NEXT: s_lshr_b32 s75, s85, 16
+; VI-NEXT: s_lshr_b32 s77, s7, 16
; VI-NEXT: v_readfirstlane_b32 s4, v16
-; VI-NEXT: v_writelane_b32 v33, s60, 5
+; VI-NEXT: v_writelane_b32 v32, s86, 30
; VI-NEXT: s_cmp_lg_u32 s4, 0
-; VI-NEXT: v_writelane_b32 v33, s59, 6
-; VI-NEXT: v_writelane_b32 v33, s58, 7
+; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_cbranch_scc0 .LBB35_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s77, 16
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_lshl_b32 s5, s5, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s73, 16
+; VI-NEXT: s_lshl_b32 s5, s45, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s44, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s75, 16
+; VI-NEXT: s_mov_b32 s80, s41
+; VI-NEXT: s_lshl_b32 s41, s41, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s43, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_lshl_b32 s5, s42, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
-; VI-NEXT: s_lshl_b32 s5, s86, 16
+; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_mov_b32 s69, s42
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
-; VI-NEXT: s_lshl_b32 s5, s84, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_mov_b32 s83, s43
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
-; VI-NEXT: s_lshl_b32 s5, s81, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_mov_b32 s86, s44
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
-; VI-NEXT: s_lshl_b32 s5, s70, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_mov_b32 s70, s45
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
-; VI-NEXT: s_lshl_b32 s5, s68, 16
+; VI-NEXT: s_lshl_b32 s5, s46, 16
+; VI-NEXT: s_mov_b32 s87, s46
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
-; VI-NEXT: s_lshl_b32 s5, s31, 16
+; VI-NEXT: s_lshl_b32 s5, s47, 16
+; VI-NEXT: s_mov_b32 s84, s47
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
; VI-NEXT: s_lshl_b32 s5, s88, 16
@@ -24844,34 +24867,44 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s56, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s7
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s77, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s85
-; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s82
-; VI-NEXT: s_lshl_b32 s5, s83, 16
+; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s71
-; VI-NEXT: s_lshl_b32 s5, s80, 16
+; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s35
-; VI-NEXT: s_lshl_b32 s5, s69, 16
+; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s30
-; VI-NEXT: s_lshl_b32 s5, s34, 16
+; VI-NEXT: s_lshl_b32 s5, s91, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s89
-; VI-NEXT: s_lshl_b32 s5, s64, 16
-; VI-NEXT: s_mov_b32 s91, s56
+; VI-NEXT: s_lshl_b32 s5, s90, 16
+; VI-NEXT: s_mov_b32 s68, s15
+; VI-NEXT: s_mov_b32 s15, s11
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s9, s88
+; VI-NEXT: s_mov_b32 s88, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s78
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s34
+; VI-NEXT: s_mov_b32 s34, s91
+; VI-NEXT: s_mov_b32 s91, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s58, 16
+; VI-NEXT: s_mov_b32 s73, s13
+; VI-NEXT: s_mov_b32 s13, s31
+; VI-NEXT: s_mov_b32 s31, s90
+; VI-NEXT: s_mov_b32 s90, s58
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s59, 16
@@ -24889,88 +24922,90 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
-; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
-; VI-NEXT: s_mov_b32 s90, s64
+; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s64, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
+; VI-NEXT: s_mov_b32 s79, vcc_lo
; VI-NEXT: s_or_b32 s65, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v29, 0x200
-; VI-NEXT: v_mov_b32_e32 v0, s77
-; VI-NEXT: v_mov_b32_e32 v2, s75
+; VI-NEXT: v_mov_b32_e32 v0, s81
+; VI-NEXT: v_mov_b32_e32 v2, s80
; VI-NEXT: v_add_f16_sdwa v0, v0, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v29
; VI-NEXT: v_add_f16_sdwa v2, v2, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v29
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
-; VI-NEXT: v_mov_b32_e32 v2, s73
+; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v2, v2, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v29
; VI-NEXT: v_or_b32_e32 v2, v3, v2
-; VI-NEXT: v_mov_b32_e32 v3, s15
+; VI-NEXT: v_mov_b32_e32 v3, s86
; VI-NEXT: v_add_f16_sdwa v3, v3, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v29
; VI-NEXT: v_or_b32_e32 v3, v4, v3
-; VI-NEXT: v_mov_b32_e32 v4, s13
+; VI-NEXT: v_mov_b32_e32 v4, s83
; VI-NEXT: v_add_f16_sdwa v4, v4, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v29
; VI-NEXT: v_or_b32_e32 v4, v5, v4
-; VI-NEXT: v_mov_b32_e32 v5, s9
+; VI-NEXT: v_mov_b32_e32 v5, s69
; VI-NEXT: v_add_f16_sdwa v5, v5, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v29
; VI-NEXT: v_or_b32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s86
+; VI-NEXT: v_mov_b32_e32 v6, s68
; VI-NEXT: v_add_f16_sdwa v6, v6, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v29
; VI-NEXT: v_or_b32_e32 v6, v7, v6
-; VI-NEXT: v_mov_b32_e32 v7, s84
+; VI-NEXT: v_mov_b32_e32 v7, s73
; VI-NEXT: v_add_f16_sdwa v7, v7, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v29
; VI-NEXT: v_or_b32_e32 v7, v8, v7
-; VI-NEXT: v_mov_b32_e32 v8, s81
+; VI-NEXT: v_mov_b32_e32 v8, s15
; VI-NEXT: v_add_f16_sdwa v8, v8, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v29
; VI-NEXT: v_or_b32_e32 v8, v9, v8
-; VI-NEXT: v_mov_b32_e32 v9, s70
+; VI-NEXT: v_mov_b32_e32 v9, s11
; VI-NEXT: v_add_f16_sdwa v9, v9, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v29
; VI-NEXT: v_or_b32_e32 v9, v10, v9
-; VI-NEXT: v_mov_b32_e32 v10, s68
+; VI-NEXT: v_mov_b32_e32 v10, s87
; VI-NEXT: v_add_f16_sdwa v10, v10, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v29
; VI-NEXT: v_or_b32_e32 v10, v11, v10
-; VI-NEXT: v_mov_b32_e32 v11, s31
+; VI-NEXT: v_mov_b32_e32 v11, s84
; VI-NEXT: v_add_f16_sdwa v11, v11, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v29
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s79
+; VI-NEXT: v_mov_b32_e32 v12, s9
; VI-NEXT: v_add_f16_sdwa v12, v12, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v29
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s91
+; VI-NEXT: v_mov_b32_e32 v13, s88
; VI-NEXT: v_add_f16_sdwa v13, v13, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v29
+; VI-NEXT: s_lshr_b32 s4, s7, 16
; VI-NEXT: v_or_b32_e32 v13, v14, v13
-; VI-NEXT: v_mov_b32_e32 v14, s11
+; VI-NEXT: v_mov_b32_e32 v14, s4
; VI-NEXT: v_add_f16_sdwa v14, v14, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s7, v29
; VI-NEXT: v_or_b32_e32 v14, v15, v14
-; VI-NEXT: v_mov_b32_e32 v15, s87
+; VI-NEXT: v_mov_b32_e32 v15, s77
; VI-NEXT: v_add_f16_sdwa v15, v15, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s85, v29
; VI-NEXT: v_or_b32_e32 v15, v16, v15
-; VI-NEXT: v_mov_b32_e32 v16, s83
+; VI-NEXT: v_mov_b32_e32 v16, s75
; VI-NEXT: v_add_f16_sdwa v16, v16, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s82, v29
; VI-NEXT: v_or_b32_e32 v16, v17, v16
-; VI-NEXT: v_mov_b32_e32 v17, s80
+; VI-NEXT: v_mov_b32_e32 v17, s13
; VI-NEXT: v_add_f16_sdwa v17, v17, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s71, v29
+; VI-NEXT: s_lshr_b32 s4, s35, 16
; VI-NEXT: v_or_b32_e32 v17, v18, v17
-; VI-NEXT: v_mov_b32_e32 v18, s69
+; VI-NEXT: v_mov_b32_e32 v18, s4
; VI-NEXT: v_add_f16_sdwa v18, v18, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s35, v29
; VI-NEXT: v_or_b32_e32 v18, v19, v18
@@ -24978,60 +25013,76 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v19, v19, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s30, v29
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s90
+; VI-NEXT: v_mov_b32_e32 v20, s31
; VI-NEXT: v_add_f16_sdwa v20, v20, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s89, v29
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s88
+; VI-NEXT: v_mov_b32_e32 v21, s91
; VI-NEXT: v_add_f16_sdwa v21, v21, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s78, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 7
; VI-NEXT: v_or_b32_e32 v21, v22, v21
-; VI-NEXT: v_mov_b32_e32 v22, s4
+; VI-NEXT: v_mov_b32_e32 v22, s90
; VI-NEXT: v_add_f16_sdwa v22, v22, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s76, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 6
+; VI-NEXT: s_lshr_b32 s4, s74, 16
; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_mov_b32_e32 v23, s4
; VI-NEXT: v_add_f16_sdwa v23, v23, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s74, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 5
+; VI-NEXT: s_lshr_b32 s4, s72, 16
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_mov_b32_e32 v24, s4
; VI-NEXT: v_add_f16_sdwa v24, v24, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s72, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 4
+; VI-NEXT: s_lshr_b32 s4, s14, 16
; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: v_mov_b32_e32 v25, s4
; VI-NEXT: v_add_f16_sdwa v25, v25, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, s14, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 3
+; VI-NEXT: s_lshr_b32 s4, s12, 16
; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: v_mov_b32_e32 v26, s4
; VI-NEXT: v_add_f16_sdwa v26, v26, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, s12, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 2
+; VI-NEXT: s_lshr_b32 s4, s10, 16
; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: v_mov_b32_e32 v27, s4
; VI-NEXT: v_add_f16_sdwa v27, v27, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v28, s10, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 1
+; VI-NEXT: s_lshr_b32 s4, s8, 16
; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: v_mov_b32_e32 v28, s4
; VI-NEXT: v_add_f16_sdwa v28, v28, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v30, s8, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 0
; VI-NEXT: v_or_b32_e32 v28, v30, v28
-; VI-NEXT: v_mov_b32_e32 v30, s4
+; VI-NEXT: v_mov_b32_e32 v30, s79
; VI-NEXT: v_add_f16_sdwa v30, v30, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v29, s6, v29
; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: s_branch .LBB35_5
; VI-NEXT: .LBB35_3:
-; VI-NEXT: s_mov_b32 s90, s64
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s91, s56
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_mov_b32 s80, s41
+; VI-NEXT: s_mov_b32 s70, s45
+; VI-NEXT: s_mov_b32 s86, s44
+; VI-NEXT: s_mov_b32 s83, s43
+; VI-NEXT: s_mov_b32 s69, s42
+; VI-NEXT: s_mov_b32 s68, s15
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s34
+; VI-NEXT: s_mov_b32 s73, s13
+; VI-NEXT: s_mov_b32 s15, s11
+; VI-NEXT: s_mov_b32 s13, s31
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s87, s46
+; VI-NEXT: s_mov_b32 s34, s91
+; VI-NEXT: s_mov_b32 s84, s47
+; VI-NEXT: s_mov_b32 s31, s90
+; VI-NEXT: s_mov_b32 s9, s88
+; VI-NEXT: s_mov_b32 s88, s56
+; VI-NEXT: s_mov_b32 s91, s57
+; VI-NEXT: s_mov_b32 s90, s58
+; VI-NEXT: s_mov_b32 s79, vcc_lo
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB35_2
; VI-NEXT: .LBB35_4:
@@ -25102,7 +25153,6 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: v_readlane_b32 s30, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -35100,7 +35150,6 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s30, 0
; VI-NEXT: v_writelane_b32 v32, s31, 1
@@ -35127,29 +35176,17 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_writelane_b32 v32, s70, 22
; VI-NEXT: v_writelane_b32 v32, s71, 23
; VI-NEXT: v_writelane_b32 v32, s80, 24
-; VI-NEXT: v_readfirstlane_b32 s6, v15
; VI-NEXT: v_writelane_b32 v32, s81, 25
-; VI-NEXT: s_lshr_b32 vcc_lo, s6, 16
-; VI-NEXT: v_readfirstlane_b32 s8, v14
-; VI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
; VI-NEXT: v_writelane_b32 v32, s82, 26
-; VI-NEXT: s_lshr_b32 vcc_hi, s8, 16
-; VI-NEXT: v_readfirstlane_b32 s10, v13
-; VI-NEXT: v_writelane_b32 v33, vcc_lo, 0
; VI-NEXT: v_writelane_b32 v32, s83, 27
-; VI-NEXT: s_lshr_b32 s63, s10, 16
-; VI-NEXT: v_readfirstlane_b32 s12, v12
-; VI-NEXT: v_writelane_b32 v33, vcc_hi, 1
; VI-NEXT: v_writelane_b32 v32, s84, 28
-; VI-NEXT: s_lshr_b32 s62, s12, 16
-; VI-NEXT: v_readfirstlane_b32 s14, v11
-; VI-NEXT: v_writelane_b32 v33, s63, 2
; VI-NEXT: v_writelane_b32 v32, s85, 29
-; VI-NEXT: s_lshr_b32 s61, s14, 16
+; VI-NEXT: v_readfirstlane_b32 s6, v15
+; VI-NEXT: v_readfirstlane_b32 s8, v14
+; VI-NEXT: v_readfirstlane_b32 s10, v13
+; VI-NEXT: v_readfirstlane_b32 s12, v12
+; VI-NEXT: v_readfirstlane_b32 s14, v11
; VI-NEXT: v_readfirstlane_b32 s72, v10
-; VI-NEXT: v_writelane_b32 v33, s62, 3
-; VI-NEXT: v_writelane_b32 v32, s86, 30
-; VI-NEXT: s_lshr_b32 s60, s72, 16
; VI-NEXT: v_readfirstlane_b32 s74, v9
; VI-NEXT: v_readfirstlane_b32 s76, v8
; VI-NEXT: v_readfirstlane_b32 s78, v7
@@ -35160,74 +35197,85 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s82, v2
; VI-NEXT: v_readfirstlane_b32 s85, v1
; VI-NEXT: v_readfirstlane_b32 s7, v0
-; VI-NEXT: v_writelane_b32 v33, s61, 4
-; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_lshr_b32 s56, s29, 16
; VI-NEXT: s_lshr_b32 s88, s28, 16
-; VI-NEXT: s_lshr_b32 s31, s27, 16
-; VI-NEXT: s_lshr_b32 s68, s26, 16
-; VI-NEXT: s_lshr_b32 s70, s25, 16
-; VI-NEXT: s_lshr_b32 s81, s24, 16
-; VI-NEXT: s_lshr_b32 s84, s23, 16
-; VI-NEXT: s_lshr_b32 s86, s22, 16
-; VI-NEXT: s_lshr_b32 s9, s21, 16
-; VI-NEXT: s_lshr_b32 s13, s20, 16
-; VI-NEXT: s_lshr_b32 s15, s19, 16
-; VI-NEXT: s_lshr_b32 s73, s18, 16
-; VI-NEXT: s_lshr_b32 s75, s17, 16
-; VI-NEXT: s_lshr_b32 s77, s16, 16
+; VI-NEXT: s_lshr_b32 s47, s27, 16
+; VI-NEXT: s_lshr_b32 s46, s26, 16
+; VI-NEXT: s_lshr_b32 s9, s25, 16
+; VI-NEXT: s_lshr_b32 s11, s24, 16
+; VI-NEXT: s_lshr_b32 s13, s23, 16
+; VI-NEXT: s_lshr_b32 s15, s22, 16
+; VI-NEXT: s_lshr_b32 s42, s21, 16
+; VI-NEXT: s_lshr_b32 s43, s20, 16
+; VI-NEXT: s_lshr_b32 s44, s19, 16
+; VI-NEXT: s_lshr_b32 s45, s18, 16
+; VI-NEXT: s_lshr_b32 s41, s17, 16
+; VI-NEXT: s_lshr_b32 s5, s16, 16
+; VI-NEXT: s_lshr_b32 vcc_lo, s6, 16
+; VI-NEXT: s_lshr_b32 s79, s8, 16
+; VI-NEXT: s_lshr_b32 s63, s10, 16
+; VI-NEXT: s_lshr_b32 s62, s12, 16
+; VI-NEXT: s_lshr_b32 s61, s14, 16
+; VI-NEXT: s_lshr_b32 s60, s72, 16
; VI-NEXT: s_lshr_b32 s59, s74, 16
; VI-NEXT: s_lshr_b32 s58, s76, 16
; VI-NEXT: s_lshr_b32 s57, s78, 16
-; VI-NEXT: s_lshr_b32 s64, s89, 16
-; VI-NEXT: s_lshr_b32 s34, s30, 16
-; VI-NEXT: s_lshr_b32 s69, s35, 16
-; VI-NEXT: s_lshr_b32 s80, s71, 16
-; VI-NEXT: s_lshr_b32 s83, s82, 16
-; VI-NEXT: s_lshr_b32 s87, s85, 16
-; VI-NEXT: s_lshr_b32 s11, s7, 16
+; VI-NEXT: s_lshr_b32 s90, s89, 16
+; VI-NEXT: s_lshr_b32 s91, s30, 16
+; VI-NEXT: s_lshr_b32 vcc_hi, s35, 16
+; VI-NEXT: s_lshr_b32 s31, s71, 16
+; VI-NEXT: s_lshr_b32 s34, s82, 16
+; VI-NEXT: s_lshr_b32 s75, s85, 16
+; VI-NEXT: s_lshr_b32 s77, s7, 16
; VI-NEXT: v_readfirstlane_b32 s4, v16
-; VI-NEXT: v_writelane_b32 v33, s60, 5
+; VI-NEXT: v_writelane_b32 v32, s86, 30
; VI-NEXT: s_cmp_lg_u32 s4, 0
-; VI-NEXT: v_writelane_b32 v33, s59, 6
-; VI-NEXT: v_writelane_b32 v33, s58, 7
+; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_cbranch_scc0 .LBB47_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s77, 16
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_lshl_b32 s5, s5, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s73, 16
+; VI-NEXT: s_lshl_b32 s5, s45, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s44, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s75, 16
+; VI-NEXT: s_mov_b32 s80, s41
+; VI-NEXT: s_lshl_b32 s41, s41, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s43, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_lshl_b32 s5, s42, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
-; VI-NEXT: s_lshl_b32 s5, s86, 16
+; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_mov_b32 s69, s42
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
-; VI-NEXT: s_lshl_b32 s5, s84, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_mov_b32 s83, s43
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
-; VI-NEXT: s_lshl_b32 s5, s81, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_mov_b32 s86, s44
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
-; VI-NEXT: s_lshl_b32 s5, s70, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_mov_b32 s70, s45
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
-; VI-NEXT: s_lshl_b32 s5, s68, 16
+; VI-NEXT: s_lshl_b32 s5, s46, 16
+; VI-NEXT: s_mov_b32 s87, s46
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
-; VI-NEXT: s_lshl_b32 s5, s31, 16
+; VI-NEXT: s_lshl_b32 s5, s47, 16
+; VI-NEXT: s_mov_b32 s84, s47
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
; VI-NEXT: s_lshl_b32 s5, s88, 16
@@ -35236,34 +35284,44 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_lshl_b32 s5, s56, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s7
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s77, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s85
-; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s82
-; VI-NEXT: s_lshl_b32 s5, s83, 16
+; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s71
-; VI-NEXT: s_lshl_b32 s5, s80, 16
+; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s35
-; VI-NEXT: s_lshl_b32 s5, s69, 16
+; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s30
-; VI-NEXT: s_lshl_b32 s5, s34, 16
+; VI-NEXT: s_lshl_b32 s5, s91, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s89
-; VI-NEXT: s_lshl_b32 s5, s64, 16
-; VI-NEXT: s_mov_b32 s91, s56
+; VI-NEXT: s_lshl_b32 s5, s90, 16
+; VI-NEXT: s_mov_b32 s68, s15
+; VI-NEXT: s_mov_b32 s15, s11
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s9, s88
+; VI-NEXT: s_mov_b32 s88, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s78
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s34
+; VI-NEXT: s_mov_b32 s34, s91
+; VI-NEXT: s_mov_b32 s91, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s58, 16
+; VI-NEXT: s_mov_b32 s73, s13
+; VI-NEXT: s_mov_b32 s13, s31
+; VI-NEXT: s_mov_b32 s31, s90
+; VI-NEXT: s_mov_b32 s90, s58
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s59, 16
@@ -35281,88 +35339,90 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
-; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
-; VI-NEXT: s_mov_b32 s90, s64
+; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s64, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
+; VI-NEXT: s_mov_b32 s79, vcc_lo
; VI-NEXT: s_or_b32 s65, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v29, 0x200
-; VI-NEXT: v_mov_b32_e32 v0, s77
-; VI-NEXT: v_mov_b32_e32 v2, s75
+; VI-NEXT: v_mov_b32_e32 v0, s81
+; VI-NEXT: v_mov_b32_e32 v2, s80
; VI-NEXT: v_add_f16_sdwa v0, v0, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v29
; VI-NEXT: v_add_f16_sdwa v2, v2, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v29
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
-; VI-NEXT: v_mov_b32_e32 v2, s73
+; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v2, v2, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v29
; VI-NEXT: v_or_b32_e32 v2, v3, v2
-; VI-NEXT: v_mov_b32_e32 v3, s15
+; VI-NEXT: v_mov_b32_e32 v3, s86
; VI-NEXT: v_add_f16_sdwa v3, v3, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v29
; VI-NEXT: v_or_b32_e32 v3, v4, v3
-; VI-NEXT: v_mov_b32_e32 v4, s13
+; VI-NEXT: v_mov_b32_e32 v4, s83
; VI-NEXT: v_add_f16_sdwa v4, v4, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v29
; VI-NEXT: v_or_b32_e32 v4, v5, v4
-; VI-NEXT: v_mov_b32_e32 v5, s9
+; VI-NEXT: v_mov_b32_e32 v5, s69
; VI-NEXT: v_add_f16_sdwa v5, v5, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v29
; VI-NEXT: v_or_b32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s86
+; VI-NEXT: v_mov_b32_e32 v6, s68
; VI-NEXT: v_add_f16_sdwa v6, v6, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v29
; VI-NEXT: v_or_b32_e32 v6, v7, v6
-; VI-NEXT: v_mov_b32_e32 v7, s84
+; VI-NEXT: v_mov_b32_e32 v7, s73
; VI-NEXT: v_add_f16_sdwa v7, v7, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v29
; VI-NEXT: v_or_b32_e32 v7, v8, v7
-; VI-NEXT: v_mov_b32_e32 v8, s81
+; VI-NEXT: v_mov_b32_e32 v8, s15
; VI-NEXT: v_add_f16_sdwa v8, v8, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v29
; VI-NEXT: v_or_b32_e32 v8, v9, v8
-; VI-NEXT: v_mov_b32_e32 v9, s70
+; VI-NEXT: v_mov_b32_e32 v9, s11
; VI-NEXT: v_add_f16_sdwa v9, v9, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v29
; VI-NEXT: v_or_b32_e32 v9, v10, v9
-; VI-NEXT: v_mov_b32_e32 v10, s68
+; VI-NEXT: v_mov_b32_e32 v10, s87
; VI-NEXT: v_add_f16_sdwa v10, v10, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v29
; VI-NEXT: v_or_b32_e32 v10, v11, v10
-; VI-NEXT: v_mov_b32_e32 v11, s31
+; VI-NEXT: v_mov_b32_e32 v11, s84
; VI-NEXT: v_add_f16_sdwa v11, v11, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v29
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s79
+; VI-NEXT: v_mov_b32_e32 v12, s9
; VI-NEXT: v_add_f16_sdwa v12, v12, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v29
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s91
+; VI-NEXT: v_mov_b32_e32 v13, s88
; VI-NEXT: v_add_f16_sdwa v13, v13, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v29
+; VI-NEXT: s_lshr_b32 s4, s7, 16
; VI-NEXT: v_or_b32_e32 v13, v14, v13
-; VI-NEXT: v_mov_b32_e32 v14, s11
+; VI-NEXT: v_mov_b32_e32 v14, s4
; VI-NEXT: v_add_f16_sdwa v14, v14, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s7, v29
; VI-NEXT: v_or_b32_e32 v14, v15, v14
-; VI-NEXT: v_mov_b32_e32 v15, s87
+; VI-NEXT: v_mov_b32_e32 v15, s77
; VI-NEXT: v_add_f16_sdwa v15, v15, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s85, v29
; VI-NEXT: v_or_b32_e32 v15, v16, v15
-; VI-NEXT: v_mov_b32_e32 v16, s83
+; VI-NEXT: v_mov_b32_e32 v16, s75
; VI-NEXT: v_add_f16_sdwa v16, v16, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s82, v29
; VI-NEXT: v_or_b32_e32 v16, v17, v16
-; VI-NEXT: v_mov_b32_e32 v17, s80
+; VI-NEXT: v_mov_b32_e32 v17, s13
; VI-NEXT: v_add_f16_sdwa v17, v17, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s71, v29
+; VI-NEXT: s_lshr_b32 s4, s35, 16
; VI-NEXT: v_or_b32_e32 v17, v18, v17
-; VI-NEXT: v_mov_b32_e32 v18, s69
+; VI-NEXT: v_mov_b32_e32 v18, s4
; VI-NEXT: v_add_f16_sdwa v18, v18, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s35, v29
; VI-NEXT: v_or_b32_e32 v18, v19, v18
@@ -35370,60 +35430,76 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v19, v19, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s30, v29
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s90
+; VI-NEXT: v_mov_b32_e32 v20, s31
; VI-NEXT: v_add_f16_sdwa v20, v20, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s89, v29
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s88
+; VI-NEXT: v_mov_b32_e32 v21, s91
; VI-NEXT: v_add_f16_sdwa v21, v21, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s78, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 7
; VI-NEXT: v_or_b32_e32 v21, v22, v21
-; VI-NEXT: v_mov_b32_e32 v22, s4
+; VI-NEXT: v_mov_b32_e32 v22, s90
; VI-NEXT: v_add_f16_sdwa v22, v22, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s76, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 6
+; VI-NEXT: s_lshr_b32 s4, s74, 16
; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_mov_b32_e32 v23, s4
; VI-NEXT: v_add_f16_sdwa v23, v23, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s74, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 5
+; VI-NEXT: s_lshr_b32 s4, s72, 16
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_mov_b32_e32 v24, s4
; VI-NEXT: v_add_f16_sdwa v24, v24, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s72, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 4
+; VI-NEXT: s_lshr_b32 s4, s14, 16
; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: v_mov_b32_e32 v25, s4
; VI-NEXT: v_add_f16_sdwa v25, v25, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, s14, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 3
+; VI-NEXT: s_lshr_b32 s4, s12, 16
; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: v_mov_b32_e32 v26, s4
; VI-NEXT: v_add_f16_sdwa v26, v26, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, s12, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 2
+; VI-NEXT: s_lshr_b32 s4, s10, 16
; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: v_mov_b32_e32 v27, s4
; VI-NEXT: v_add_f16_sdwa v27, v27, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v28, s10, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 1
+; VI-NEXT: s_lshr_b32 s4, s8, 16
; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: v_mov_b32_e32 v28, s4
; VI-NEXT: v_add_f16_sdwa v28, v28, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v30, s8, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 0
; VI-NEXT: v_or_b32_e32 v28, v30, v28
-; VI-NEXT: v_mov_b32_e32 v30, s4
+; VI-NEXT: v_mov_b32_e32 v30, s79
; VI-NEXT: v_add_f16_sdwa v30, v30, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v29, s6, v29
; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: s_branch .LBB47_5
; VI-NEXT: .LBB47_3:
-; VI-NEXT: s_mov_b32 s90, s64
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s91, s56
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_mov_b32 s80, s41
+; VI-NEXT: s_mov_b32 s70, s45
+; VI-NEXT: s_mov_b32 s86, s44
+; VI-NEXT: s_mov_b32 s83, s43
+; VI-NEXT: s_mov_b32 s69, s42
+; VI-NEXT: s_mov_b32 s68, s15
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s34
+; VI-NEXT: s_mov_b32 s73, s13
+; VI-NEXT: s_mov_b32 s15, s11
+; VI-NEXT: s_mov_b32 s13, s31
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s87, s46
+; VI-NEXT: s_mov_b32 s34, s91
+; VI-NEXT: s_mov_b32 s84, s47
+; VI-NEXT: s_mov_b32 s31, s90
+; VI-NEXT: s_mov_b32 s9, s88
+; VI-NEXT: s_mov_b32 s88, s56
+; VI-NEXT: s_mov_b32 s91, s57
+; VI-NEXT: s_mov_b32 s90, s58
+; VI-NEXT: s_mov_b32 s79, vcc_lo
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB47_2
; VI-NEXT: .LBB47_4:
@@ -35494,7 +35570,6 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_readlane_b32 s30, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -44844,7 +44919,6 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s30, 0
; VI-NEXT: v_writelane_b32 v32, s31, 1
@@ -44871,29 +44945,17 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: v_writelane_b32 v32, s70, 22
; VI-NEXT: v_writelane_b32 v32, s71, 23
; VI-NEXT: v_writelane_b32 v32, s80, 24
-; VI-NEXT: v_readfirstlane_b32 s6, v15
; VI-NEXT: v_writelane_b32 v32, s81, 25
-; VI-NEXT: s_lshr_b32 vcc_lo, s6, 16
-; VI-NEXT: v_readfirstlane_b32 s8, v14
-; VI-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
; VI-NEXT: v_writelane_b32 v32, s82, 26
-; VI-NEXT: s_lshr_b32 vcc_hi, s8, 16
-; VI-NEXT: v_readfirstlane_b32 s10, v13
-; VI-NEXT: v_writelane_b32 v33, vcc_lo, 0
; VI-NEXT: v_writelane_b32 v32, s83, 27
-; VI-NEXT: s_lshr_b32 s63, s10, 16
-; VI-NEXT: v_readfirstlane_b32 s12, v12
-; VI-NEXT: v_writelane_b32 v33, vcc_hi, 1
; VI-NEXT: v_writelane_b32 v32, s84, 28
-; VI-NEXT: s_lshr_b32 s62, s12, 16
-; VI-NEXT: v_readfirstlane_b32 s14, v11
-; VI-NEXT: v_writelane_b32 v33, s63, 2
; VI-NEXT: v_writelane_b32 v32, s85, 29
-; VI-NEXT: s_lshr_b32 s61, s14, 16
+; VI-NEXT: v_readfirstlane_b32 s6, v15
+; VI-NEXT: v_readfirstlane_b32 s8, v14
+; VI-NEXT: v_readfirstlane_b32 s10, v13
+; VI-NEXT: v_readfirstlane_b32 s12, v12
+; VI-NEXT: v_readfirstlane_b32 s14, v11
; VI-NEXT: v_readfirstlane_b32 s72, v10
-; VI-NEXT: v_writelane_b32 v33, s62, 3
-; VI-NEXT: v_writelane_b32 v32, s86, 30
-; VI-NEXT: s_lshr_b32 s60, s72, 16
; VI-NEXT: v_readfirstlane_b32 s74, v9
; VI-NEXT: v_readfirstlane_b32 s76, v8
; VI-NEXT: v_readfirstlane_b32 s78, v7
@@ -44904,74 +44966,85 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: v_readfirstlane_b32 s82, v2
; VI-NEXT: v_readfirstlane_b32 s85, v1
; VI-NEXT: v_readfirstlane_b32 s7, v0
-; VI-NEXT: v_writelane_b32 v33, s61, 4
-; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_lshr_b32 s56, s29, 16
; VI-NEXT: s_lshr_b32 s88, s28, 16
-; VI-NEXT: s_lshr_b32 s31, s27, 16
-; VI-NEXT: s_lshr_b32 s68, s26, 16
-; VI-NEXT: s_lshr_b32 s70, s25, 16
-; VI-NEXT: s_lshr_b32 s81, s24, 16
-; VI-NEXT: s_lshr_b32 s84, s23, 16
-; VI-NEXT: s_lshr_b32 s86, s22, 16
-; VI-NEXT: s_lshr_b32 s9, s21, 16
-; VI-NEXT: s_lshr_b32 s13, s20, 16
-; VI-NEXT: s_lshr_b32 s15, s19, 16
-; VI-NEXT: s_lshr_b32 s73, s18, 16
-; VI-NEXT: s_lshr_b32 s75, s17, 16
-; VI-NEXT: s_lshr_b32 s77, s16, 16
+; VI-NEXT: s_lshr_b32 s47, s27, 16
+; VI-NEXT: s_lshr_b32 s46, s26, 16
+; VI-NEXT: s_lshr_b32 s9, s25, 16
+; VI-NEXT: s_lshr_b32 s11, s24, 16
+; VI-NEXT: s_lshr_b32 s13, s23, 16
+; VI-NEXT: s_lshr_b32 s15, s22, 16
+; VI-NEXT: s_lshr_b32 s42, s21, 16
+; VI-NEXT: s_lshr_b32 s43, s20, 16
+; VI-NEXT: s_lshr_b32 s44, s19, 16
+; VI-NEXT: s_lshr_b32 s45, s18, 16
+; VI-NEXT: s_lshr_b32 s41, s17, 16
+; VI-NEXT: s_lshr_b32 s5, s16, 16
+; VI-NEXT: s_lshr_b32 vcc_lo, s6, 16
+; VI-NEXT: s_lshr_b32 s79, s8, 16
+; VI-NEXT: s_lshr_b32 s63, s10, 16
+; VI-NEXT: s_lshr_b32 s62, s12, 16
+; VI-NEXT: s_lshr_b32 s61, s14, 16
+; VI-NEXT: s_lshr_b32 s60, s72, 16
; VI-NEXT: s_lshr_b32 s59, s74, 16
; VI-NEXT: s_lshr_b32 s58, s76, 16
; VI-NEXT: s_lshr_b32 s57, s78, 16
-; VI-NEXT: s_lshr_b32 s64, s89, 16
-; VI-NEXT: s_lshr_b32 s34, s30, 16
-; VI-NEXT: s_lshr_b32 s69, s35, 16
-; VI-NEXT: s_lshr_b32 s80, s71, 16
-; VI-NEXT: s_lshr_b32 s83, s82, 16
-; VI-NEXT: s_lshr_b32 s87, s85, 16
-; VI-NEXT: s_lshr_b32 s11, s7, 16
+; VI-NEXT: s_lshr_b32 s90, s89, 16
+; VI-NEXT: s_lshr_b32 s91, s30, 16
+; VI-NEXT: s_lshr_b32 vcc_hi, s35, 16
+; VI-NEXT: s_lshr_b32 s31, s71, 16
+; VI-NEXT: s_lshr_b32 s34, s82, 16
+; VI-NEXT: s_lshr_b32 s75, s85, 16
+; VI-NEXT: s_lshr_b32 s77, s7, 16
; VI-NEXT: v_readfirstlane_b32 s4, v16
-; VI-NEXT: v_writelane_b32 v33, s60, 5
+; VI-NEXT: v_writelane_b32 v32, s86, 30
; VI-NEXT: s_cmp_lg_u32 s4, 0
-; VI-NEXT: v_writelane_b32 v33, s59, 6
-; VI-NEXT: v_writelane_b32 v33, s58, 7
+; VI-NEXT: v_writelane_b32 v32, s87, 31
; VI-NEXT: s_cbranch_scc0 .LBB55_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s77, 16
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_lshl_b32 s5, s5, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
-; VI-NEXT: s_lshl_b32 s5, s73, 16
+; VI-NEXT: s_lshl_b32 s5, s45, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
-; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_lshl_b32 s5, s44, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s17
-; VI-NEXT: s_lshl_b32 s41, s75, 16
+; VI-NEXT: s_mov_b32 s80, s41
+; VI-NEXT: s_lshl_b32 s41, s41, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_lshl_b32 s5, s43, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
-; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_lshl_b32 s5, s42, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
-; VI-NEXT: s_lshl_b32 s5, s86, 16
+; VI-NEXT: s_lshl_b32 s5, s15, 16
+; VI-NEXT: s_mov_b32 s69, s42
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
-; VI-NEXT: s_lshl_b32 s5, s84, 16
+; VI-NEXT: s_lshl_b32 s5, s13, 16
+; VI-NEXT: s_mov_b32 s83, s43
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
-; VI-NEXT: s_lshl_b32 s5, s81, 16
+; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_mov_b32 s86, s44
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
-; VI-NEXT: s_lshl_b32 s5, s70, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
+; VI-NEXT: s_mov_b32 s70, s45
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
-; VI-NEXT: s_lshl_b32 s5, s68, 16
+; VI-NEXT: s_lshl_b32 s5, s46, 16
+; VI-NEXT: s_mov_b32 s87, s46
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
-; VI-NEXT: s_lshl_b32 s5, s31, 16
+; VI-NEXT: s_lshl_b32 s5, s47, 16
+; VI-NEXT: s_mov_b32 s84, s47
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
; VI-NEXT: s_lshl_b32 s5, s88, 16
@@ -44980,34 +45053,44 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: s_lshl_b32 s5, s56, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s7
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s77, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s85
-; VI-NEXT: s_lshl_b32 s5, s87, 16
+; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s82
-; VI-NEXT: s_lshl_b32 s5, s83, 16
+; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s71
-; VI-NEXT: s_lshl_b32 s5, s80, 16
+; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s35
-; VI-NEXT: s_lshl_b32 s5, s69, 16
+; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s30
-; VI-NEXT: s_lshl_b32 s5, s34, 16
+; VI-NEXT: s_lshl_b32 s5, s91, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s89
-; VI-NEXT: s_lshl_b32 s5, s64, 16
-; VI-NEXT: s_mov_b32 s91, s56
+; VI-NEXT: s_lshl_b32 s5, s90, 16
+; VI-NEXT: s_mov_b32 s68, s15
+; VI-NEXT: s_mov_b32 s15, s11
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s9, s88
+; VI-NEXT: s_mov_b32 s88, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s78
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s34
+; VI-NEXT: s_mov_b32 s34, s91
+; VI-NEXT: s_mov_b32 s91, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s58, 16
+; VI-NEXT: s_mov_b32 s73, s13
+; VI-NEXT: s_mov_b32 s13, s31
+; VI-NEXT: s_mov_b32 s31, s90
+; VI-NEXT: s_mov_b32 s90, s58
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s59, 16
@@ -45025,88 +45108,90 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s63, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
-; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
-; VI-NEXT: s_mov_b32 s90, s64
+; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s64, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
+; VI-NEXT: s_mov_b32 s79, vcc_lo
; VI-NEXT: s_or_b32 s65, s4, s5
; VI-NEXT: s_cbranch_execnz .LBB55_4
; VI-NEXT: .LBB55_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v29, 0x200
-; VI-NEXT: v_mov_b32_e32 v0, s77
-; VI-NEXT: v_mov_b32_e32 v2, s75
+; VI-NEXT: v_mov_b32_e32 v0, s81
+; VI-NEXT: v_mov_b32_e32 v2, s80
; VI-NEXT: v_add_f16_sdwa v0, v0, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v29
; VI-NEXT: v_add_f16_sdwa v2, v2, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v29
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
-; VI-NEXT: v_mov_b32_e32 v2, s73
+; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v2, v2, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v29
; VI-NEXT: v_or_b32_e32 v2, v3, v2
-; VI-NEXT: v_mov_b32_e32 v3, s15
+; VI-NEXT: v_mov_b32_e32 v3, s86
; VI-NEXT: v_add_f16_sdwa v3, v3, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v29
; VI-NEXT: v_or_b32_e32 v3, v4, v3
-; VI-NEXT: v_mov_b32_e32 v4, s13
+; VI-NEXT: v_mov_b32_e32 v4, s83
; VI-NEXT: v_add_f16_sdwa v4, v4, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v29
; VI-NEXT: v_or_b32_e32 v4, v5, v4
-; VI-NEXT: v_mov_b32_e32 v5, s9
+; VI-NEXT: v_mov_b32_e32 v5, s69
; VI-NEXT: v_add_f16_sdwa v5, v5, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v29
; VI-NEXT: v_or_b32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s86
+; VI-NEXT: v_mov_b32_e32 v6, s68
; VI-NEXT: v_add_f16_sdwa v6, v6, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v29
; VI-NEXT: v_or_b32_e32 v6, v7, v6
-; VI-NEXT: v_mov_b32_e32 v7, s84
+; VI-NEXT: v_mov_b32_e32 v7, s73
; VI-NEXT: v_add_f16_sdwa v7, v7, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v29
; VI-NEXT: v_or_b32_e32 v7, v8, v7
-; VI-NEXT: v_mov_b32_e32 v8, s81
+; VI-NEXT: v_mov_b32_e32 v8, s15
; VI-NEXT: v_add_f16_sdwa v8, v8, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v29
; VI-NEXT: v_or_b32_e32 v8, v9, v8
-; VI-NEXT: v_mov_b32_e32 v9, s70
+; VI-NEXT: v_mov_b32_e32 v9, s11
; VI-NEXT: v_add_f16_sdwa v9, v9, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v29
; VI-NEXT: v_or_b32_e32 v9, v10, v9
-; VI-NEXT: v_mov_b32_e32 v10, s68
+; VI-NEXT: v_mov_b32_e32 v10, s87
; VI-NEXT: v_add_f16_sdwa v10, v10, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v29
; VI-NEXT: v_or_b32_e32 v10, v11, v10
-; VI-NEXT: v_mov_b32_e32 v11, s31
+; VI-NEXT: v_mov_b32_e32 v11, s84
; VI-NEXT: v_add_f16_sdwa v11, v11, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v29
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s79
+; VI-NEXT: v_mov_b32_e32 v12, s9
; VI-NEXT: v_add_f16_sdwa v12, v12, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v29
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s91
+; VI-NEXT: v_mov_b32_e32 v13, s88
; VI-NEXT: v_add_f16_sdwa v13, v13, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v29
+; VI-NEXT: s_lshr_b32 s4, s7, 16
; VI-NEXT: v_or_b32_e32 v13, v14, v13
-; VI-NEXT: v_mov_b32_e32 v14, s11
+; VI-NEXT: v_mov_b32_e32 v14, s4
; VI-NEXT: v_add_f16_sdwa v14, v14, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s7, v29
; VI-NEXT: v_or_b32_e32 v14, v15, v14
-; VI-NEXT: v_mov_b32_e32 v15, s87
+; VI-NEXT: v_mov_b32_e32 v15, s77
; VI-NEXT: v_add_f16_sdwa v15, v15, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s85, v29
; VI-NEXT: v_or_b32_e32 v15, v16, v15
-; VI-NEXT: v_mov_b32_e32 v16, s83
+; VI-NEXT: v_mov_b32_e32 v16, s75
; VI-NEXT: v_add_f16_sdwa v16, v16, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s82, v29
; VI-NEXT: v_or_b32_e32 v16, v17, v16
-; VI-NEXT: v_mov_b32_e32 v17, s80
+; VI-NEXT: v_mov_b32_e32 v17, s13
; VI-NEXT: v_add_f16_sdwa v17, v17, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s71, v29
+; VI-NEXT: s_lshr_b32 s4, s35, 16
; VI-NEXT: v_or_b32_e32 v17, v18, v17
-; VI-NEXT: v_mov_b32_e32 v18, s69
+; VI-NEXT: v_mov_b32_e32 v18, s4
; VI-NEXT: v_add_f16_sdwa v18, v18, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s35, v29
; VI-NEXT: v_or_b32_e32 v18, v19, v18
@@ -45114,60 +45199,76 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v19, v19, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s30, v29
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s90
+; VI-NEXT: v_mov_b32_e32 v20, s31
; VI-NEXT: v_add_f16_sdwa v20, v20, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s89, v29
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s88
+; VI-NEXT: v_mov_b32_e32 v21, s91
; VI-NEXT: v_add_f16_sdwa v21, v21, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s78, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 7
; VI-NEXT: v_or_b32_e32 v21, v22, v21
-; VI-NEXT: v_mov_b32_e32 v22, s4
+; VI-NEXT: v_mov_b32_e32 v22, s90
; VI-NEXT: v_add_f16_sdwa v22, v22, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s76, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 6
+; VI-NEXT: s_lshr_b32 s4, s74, 16
; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_mov_b32_e32 v23, s4
; VI-NEXT: v_add_f16_sdwa v23, v23, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s74, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 5
+; VI-NEXT: s_lshr_b32 s4, s72, 16
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_mov_b32_e32 v24, s4
; VI-NEXT: v_add_f16_sdwa v24, v24, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s72, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 4
+; VI-NEXT: s_lshr_b32 s4, s14, 16
; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: v_mov_b32_e32 v25, s4
; VI-NEXT: v_add_f16_sdwa v25, v25, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, s14, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 3
+; VI-NEXT: s_lshr_b32 s4, s12, 16
; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: v_mov_b32_e32 v26, s4
; VI-NEXT: v_add_f16_sdwa v26, v26, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, s12, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 2
+; VI-NEXT: s_lshr_b32 s4, s10, 16
; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: v_mov_b32_e32 v27, s4
; VI-NEXT: v_add_f16_sdwa v27, v27, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v28, s10, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 1
+; VI-NEXT: s_lshr_b32 s4, s8, 16
; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: v_mov_b32_e32 v28, s4
; VI-NEXT: v_add_f16_sdwa v28, v28, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v30, s8, v29
-; VI-NEXT: v_readlane_b32 s4, v33, 0
; VI-NEXT: v_or_b32_e32 v28, v30, v28
-; VI-NEXT: v_mov_b32_e32 v30, s4
+; VI-NEXT: v_mov_b32_e32 v30, s79
; VI-NEXT: v_add_f16_sdwa v30, v30, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v29, s6, v29
; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: s_branch .LBB55_5
; VI-NEXT: .LBB55_3:
-; VI-NEXT: s_mov_b32 s90, s64
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s91, s56
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s81, s5
+; VI-NEXT: s_mov_b32 s80, s41
+; VI-NEXT: s_mov_b32 s70, s45
+; VI-NEXT: s_mov_b32 s86, s44
+; VI-NEXT: s_mov_b32 s83, s43
+; VI-NEXT: s_mov_b32 s69, s42
+; VI-NEXT: s_mov_b32 s68, s15
+; VI-NEXT: s_mov_b32 s77, s75
+; VI-NEXT: s_mov_b32 s75, s34
+; VI-NEXT: s_mov_b32 s73, s13
+; VI-NEXT: s_mov_b32 s15, s11
+; VI-NEXT: s_mov_b32 s13, s31
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s87, s46
+; VI-NEXT: s_mov_b32 s34, s91
+; VI-NEXT: s_mov_b32 s84, s47
+; VI-NEXT: s_mov_b32 s31, s90
+; VI-NEXT: s_mov_b32 s9, s88
+; VI-NEXT: s_mov_b32 s88, s56
+; VI-NEXT: s_mov_b32 s91, s57
+; VI-NEXT: s_mov_b32 s90, s58
+; VI-NEXT: s_mov_b32 s79, vcc_lo
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB55_2
; VI-NEXT: .LBB55_4:
@@ -45238,7 +45339,6 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: v_readlane_b32 s30, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -47095,605 +47195,510 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i
; SI-NEXT: v_writelane_b32 v30, s82, 26
; SI-NEXT: v_writelane_b32 v30, s83, 27
; SI-NEXT: v_writelane_b32 v30, s84, 28
-; SI-NEXT: s_lshr_b32 s4, s19, 16
-; SI-NEXT: ; implicit-def: $vgpr31 : SGPR spill to VGPR lane
; SI-NEXT: v_writelane_b32 v30, s85, 29
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v31, s4, 0
-; SI-NEXT: s_lshr_b32 s4, s18, 16
; SI-NEXT: v_writelane_b32 v30, s86, 30
-; SI-NEXT: v_writelane_b32 v31, s4, 1
; SI-NEXT: v_writelane_b32 v30, s87, 31
-; SI-NEXT: v_writelane_b32 v31, s17, 2
-; SI-NEXT: s_lshr_b32 s4, s17, 16
; SI-NEXT: v_writelane_b32 v30, s96, 32
-; SI-NEXT: v_writelane_b32 v31, s4, 3
; SI-NEXT: v_writelane_b32 v30, s97, 33
-; SI-NEXT: v_writelane_b32 v31, s16, 4
-; SI-NEXT: s_lshr_b32 s4, s16, 16
; SI-NEXT: v_writelane_b32 v30, s98, 34
-; SI-NEXT: v_writelane_b32 v31, s4, 5
+; SI-NEXT: s_lshr_b32 s5, s26, 16
+; SI-NEXT: ; implicit-def: $vgpr31 : SGPR spill to VGPR lane
; SI-NEXT: v_writelane_b32 v30, s99, 35
-; SI-NEXT: v_readfirstlane_b32 s75, v15
-; SI-NEXT: v_readfirstlane_b32 s70, v14
-; SI-NEXT: v_readfirstlane_b32 s17, v13
-; SI-NEXT: v_readfirstlane_b32 s48, v12
+; SI-NEXT: s_lshr_b32 s6, s28, 16
+; SI-NEXT: v_readfirstlane_b32 s99, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_writelane_b32 v31, s5, 0
+; SI-NEXT: v_readfirstlane_b32 s98, v2
+; SI-NEXT: s_lshr_b32 s7, s99, 16
+; SI-NEXT: v_writelane_b32 v31, s6, 1
+; SI-NEXT: v_readfirstlane_b32 s64, v4
+; SI-NEXT: s_lshr_b32 s9, s98, 16
+; SI-NEXT: v_writelane_b32 v31, s7, 2
+; SI-NEXT: v_readfirstlane_b32 s66, v6
+; SI-NEXT: s_lshr_b32 s11, s64, 16
+; SI-NEXT: v_writelane_b32 v31, s9, 3
+; SI-NEXT: v_readfirstlane_b32 s68, v8
+; SI-NEXT: s_lshr_b32 s58, s66, 16
+; SI-NEXT: v_writelane_b32 v31, s11, 4
+; SI-NEXT: s_mov_b32 s35, s17
+; SI-NEXT: s_lshr_b32 s77, s17, 16
+; SI-NEXT: v_readfirstlane_b32 s17, v10
+; SI-NEXT: s_lshr_b32 s59, s68, 16
+; SI-NEXT: v_writelane_b32 v31, s58, 5
+; SI-NEXT: s_mov_b32 s37, s16
+; SI-NEXT: s_lshr_b32 s39, s16, 16
+; SI-NEXT: v_readfirstlane_b32 s70, v15
+; SI-NEXT: v_readfirstlane_b32 s16, v14
+; SI-NEXT: v_readfirstlane_b32 s74, v13
+; SI-NEXT: v_readfirstlane_b32 s75, v12
; SI-NEXT: v_readfirstlane_b32 s69, v11
-; SI-NEXT: v_readfirstlane_b32 s37, v10
+; SI-NEXT: s_lshr_b32 s60, s17, 16
; SI-NEXT: v_readfirstlane_b32 s67, v9
-; SI-NEXT: v_readfirstlane_b32 s68, v8
; SI-NEXT: v_readfirstlane_b32 s65, v7
-; SI-NEXT: v_readfirstlane_b32 s66, v6
; SI-NEXT: v_readfirstlane_b32 s96, v5
-; SI-NEXT: v_readfirstlane_b32 s64, v4
; SI-NEXT: v_readfirstlane_b32 s87, v3
-; SI-NEXT: v_readfirstlane_b32 s98, v2
; SI-NEXT: v_readfirstlane_b32 s97, v1
-; SI-NEXT: v_readfirstlane_b32 s99, v0
-; SI-NEXT: v_writelane_b32 v31, s18, 6
-; SI-NEXT: s_mov_b32 s85, s21
-; SI-NEXT: s_lshr_b32 s79, s29, 16
-; SI-NEXT: s_lshr_b32 s92, s28, 16
-; SI-NEXT: s_lshr_b32 s31, s27, 16
-; SI-NEXT: s_lshr_b32 s90, s26, 16
-; SI-NEXT: s_lshr_b32 s95, s25, 16
-; SI-NEXT: s_lshr_b32 s88, s24, 16
-; SI-NEXT: s_lshr_b32 s93, s23, 16
-; SI-NEXT: s_lshr_b32 s49, s22, 16
-; SI-NEXT: s_lshr_b32 s91, s21, 16
-; SI-NEXT: s_lshr_b32 s76, s20, 16
-; SI-NEXT: s_lshr_b32 s86, s75, 16
-; SI-NEXT: s_lshr_b32 s58, s70, 16
-; SI-NEXT: s_lshr_b32 s82, s17, 16
-; SI-NEXT: s_lshr_b32 s78, s48, 16
-; SI-NEXT: s_lshr_b32 s81, s69, 16
-; SI-NEXT: s_lshr_b32 s39, s37, 16
-; SI-NEXT: s_lshr_b32 s80, s67, 16
-; SI-NEXT: s_lshr_b32 s38, s68, 16
-; SI-NEXT: s_lshr_b32 s71, s65, 16
-; SI-NEXT: s_lshr_b32 s36, s66, 16
-; SI-NEXT: s_lshr_b32 s55, s96, 16
-; SI-NEXT: s_lshr_b32 s34, s64, 16
-; SI-NEXT: s_lshr_b32 s53, s87, 16
-; SI-NEXT: s_lshr_b32 s30, s98, 16
-; SI-NEXT: s_lshr_b32 s51, s97, 16
-; SI-NEXT: s_lshr_b32 s21, s99, 16
+; SI-NEXT: v_writelane_b32 v31, s59, 6
+; SI-NEXT: s_lshr_b32 s31, s29, 16
+; SI-NEXT: s_lshr_b32 s95, s27, 16
+; SI-NEXT: s_lshr_b32 s93, s25, 16
+; SI-NEXT: s_lshr_b32 s55, s24, 16
+; SI-NEXT: s_lshr_b32 s91, s23, 16
+; SI-NEXT: s_lshr_b32 s53, s22, 16
+; SI-NEXT: s_lshr_b32 s89, s21, 16
+; SI-NEXT: s_lshr_b32 s51, s20, 16
+; SI-NEXT: s_lshr_b32 s79, s19, 16
+; SI-NEXT: s_lshr_b32 s49, s18, 16
+; SI-NEXT: s_lshr_b32 s86, s70, 16
+; SI-NEXT: s_lshr_b32 s62, s16, 16
+; SI-NEXT: s_lshr_b32 s85, s74, 16
+; SI-NEXT: s_lshr_b32 s61, s75, 16
+; SI-NEXT: s_lshr_b32 s84, s69, 16
+; SI-NEXT: s_lshr_b32 s83, s67, 16
+; SI-NEXT: s_lshr_b32 s82, s65, 16
+; SI-NEXT: s_lshr_b32 s81, s96, 16
+; SI-NEXT: s_lshr_b32 s80, s87, 16
+; SI-NEXT: s_lshr_b32 s71, s97, 16
; SI-NEXT: v_readfirstlane_b32 s4, v16
-; SI-NEXT: v_writelane_b32 v31, s20, 7
-; SI-NEXT: s_mov_b32 s89, s27
-; SI-NEXT: s_mov_b32 s77, s25
-; SI-NEXT: s_mov_b32 s54, s23
+; SI-NEXT: v_writelane_b32 v31, s60, 7
; SI-NEXT: s_cmp_lg_u32 s4, 0
-; SI-NEXT: v_writelane_b32 v31, s22, 8
-; SI-NEXT: v_writelane_b32 v31, s58, 9
+; SI-NEXT: v_writelane_b32 v31, s61, 8
+; SI-NEXT: v_writelane_b32 v31, s62, 9
; SI-NEXT: s_cbranch_scc0 .LBB57_4
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: v_readlane_b32 s5, v31, 2
-; SI-NEXT: v_readlane_b32 s7, v31, 3
-; SI-NEXT: s_and_b32 s5, s5, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_lshl_b32 s12, s5, 16
+; SI-NEXT: s_lshl_b32 s8, s7, 16
+; SI-NEXT: s_and_b32 s5, s35, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s77, 16
; SI-NEXT: s_or_b32 s47, s5, s7
-; SI-NEXT: v_readlane_b32 s7, v31, 0
; SI-NEXT: s_and_b32 s5, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_lshl_b32 s7, s79, 16
; SI-NEXT: s_or_b32 s45, s5, s7
-; SI-NEXT: s_and_b32 s5, s85, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s91, 16
+; SI-NEXT: s_and_b32 s5, s21, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s89, 16
; SI-NEXT: s_or_b32 s43, s5, s7
-; SI-NEXT: s_and_b32 s5, s54, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s93, 16
+; SI-NEXT: s_and_b32 s5, s23, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s91, 16
; SI-NEXT: s_or_b32 s41, s5, s7
-; SI-NEXT: s_and_b32 s5, s77, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s95, 16
+; SI-NEXT: s_and_b32 s5, s25, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s93, 16
; SI-NEXT: s_or_b32 s15, s5, s7
-; SI-NEXT: s_and_b32 s5, s89, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s31, 16
+; SI-NEXT: s_and_b32 s5, s27, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s95, 16
; SI-NEXT: s_or_b32 s13, s5, s7
; SI-NEXT: s_and_b32 s5, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s79, 16
+; SI-NEXT: s_lshl_b32 s7, s31, 16
+; SI-NEXT: s_lshl_b32 s4, s11, 16
; SI-NEXT: s_or_b32 s11, s5, s7
; SI-NEXT: s_and_b32 s5, s97, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s51, 16
+; SI-NEXT: s_lshl_b32 s7, s71, 16
+; SI-NEXT: s_lshl_b32 s10, s6, 16
+; SI-NEXT: s_lshl_b32 s6, s9, 16
; SI-NEXT: s_or_b32 s9, s5, s7
; SI-NEXT: s_and_b32 s5, s87, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s53, 16
+; SI-NEXT: s_lshl_b32 s7, s80, 16
; SI-NEXT: s_or_b32 s7, s5, s7
; SI-NEXT: s_and_b32 s5, s96, 0xffff
-; SI-NEXT: s_lshl_b32 s56, s55, 16
-; SI-NEXT: v_readlane_b32 s4, v31, 5
+; SI-NEXT: s_lshl_b32 s56, s81, 16
; SI-NEXT: s_or_b32 s5, s5, s56
; SI-NEXT: s_and_b32 s56, s65, 0xffff
-; SI-NEXT: s_lshl_b32 s57, s71, 16
-; SI-NEXT: s_lshl_b32 s46, s4, 16
-; SI-NEXT: v_readlane_b32 s4, v31, 1
+; SI-NEXT: s_lshl_b32 s57, s82, 16
; SI-NEXT: s_or_b32 vcc_hi, s56, s57
; SI-NEXT: s_and_b32 s56, s67, 0xffff
-; SI-NEXT: s_lshl_b32 s57, s80, 16
-; SI-NEXT: v_writelane_b32 v31, s70, 26
-; SI-NEXT: s_lshl_b32 s40, s49, 16
-; SI-NEXT: s_lshl_b32 s14, s88, 16
-; SI-NEXT: s_lshl_b32 s12, s90, 16
-; SI-NEXT: s_mov_b32 s83, s71
-; SI-NEXT: s_mov_b32 s71, s90
-; SI-NEXT: s_mov_b32 s90, s88
-; SI-NEXT: s_mov_b32 s88, s49
+; SI-NEXT: s_lshl_b32 s57, s83, 16
+; SI-NEXT: s_lshl_b32 s44, s49, 16
; SI-NEXT: s_or_b32 s49, s56, s57
; SI-NEXT: s_and_b32 s56, s69, 0xffff
-; SI-NEXT: s_lshl_b32 s57, s81, 16
-; SI-NEXT: v_writelane_b32 v31, s75, 27
-; SI-NEXT: s_mov_b32 s23, s80
-; SI-NEXT: s_mov_b32 s80, s51
+; SI-NEXT: s_lshl_b32 s57, s84, 16
+; SI-NEXT: s_lshl_b32 s42, s51, 16
; SI-NEXT: s_or_b32 s51, s56, s57
-; SI-NEXT: s_and_b32 s56, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s57, s82, 16
-; SI-NEXT: v_writelane_b32 v31, s17, 28
-; SI-NEXT: s_lshl_b32 s10, s92, 16
-; SI-NEXT: s_mov_b32 s94, s81
-; SI-NEXT: s_mov_b32 s81, s92
-; SI-NEXT: s_mov_b32 s92, s53
+; SI-NEXT: s_and_b32 s56, s74, 0xffff
+; SI-NEXT: s_lshl_b32 s57, s85, 16
+; SI-NEXT: s_lshl_b32 s40, s53, 16
; SI-NEXT: s_or_b32 s53, s56, s57
-; SI-NEXT: s_and_b32 s56, s75, 0xffff
+; SI-NEXT: s_and_b32 s56, s70, 0xffff
; SI-NEXT: s_lshl_b32 s57, s86, 16
-; SI-NEXT: v_writelane_b32 v31, s69, 29
-; SI-NEXT: s_lshl_b32 s44, s4, 16
-; SI-NEXT: s_lshl_b32 s6, s30, 16
-; SI-NEXT: s_lshl_b32 s4, s34, 16
-; SI-NEXT: s_lshl_b32 vcc_lo, s36, 16
-; SI-NEXT: s_mov_b32 s70, s48
-; SI-NEXT: s_lshl_b32 s48, s38, 16
-; SI-NEXT: s_lshl_b32 s50, s39, 16
-; SI-NEXT: s_mov_b32 s35, s39
-; SI-NEXT: s_mov_b32 s39, s38
-; SI-NEXT: s_mov_b32 s38, s36
-; SI-NEXT: s_mov_b32 s36, s34
-; SI-NEXT: s_mov_b32 s34, s30
-; SI-NEXT: s_mov_b32 s30, s86
-; SI-NEXT: s_mov_b32 s86, s82
-; SI-NEXT: s_mov_b32 s82, s55
+; SI-NEXT: s_lshl_b32 s46, s39, 16
+; SI-NEXT: s_lshl_b32 s14, s55, 16
; SI-NEXT: s_or_b32 s55, s56, s57
-; SI-NEXT: v_readlane_b32 s56, v31, 4
-; SI-NEXT: s_and_b32 s56, s56, 0xffff
+; SI-NEXT: s_and_b32 s56, s37, 0xffff
+; SI-NEXT: s_lshl_b32 s50, s60, 16
+; SI-NEXT: s_lshl_b32 s52, s61, 16
; SI-NEXT: s_or_b32 s60, s56, s46
-; SI-NEXT: s_lshr_b64 s[74:75], s[46:47], 16
+; SI-NEXT: s_mov_b32 s61, s47
+; SI-NEXT: s_lshr_b64 s[46:47], s[46:47], 16
+; SI-NEXT: v_writelane_b32 v31, s46, 10
+; SI-NEXT: v_writelane_b32 v31, s47, 11
; SI-NEXT: s_and_b32 s46, s18, 0xffff
-; SI-NEXT: s_lshl_b32 s42, s76, 16
-; SI-NEXT: s_mov_b32 s25, s19
; SI-NEXT: s_or_b32 s72, s46, s44
-; SI-NEXT: s_lshr_b64 s[18:19], s[44:45], 16
+; SI-NEXT: s_mov_b32 s46, s77
+; SI-NEXT: s_lshr_b64 s[76:77], s[44:45], 16
; SI-NEXT: s_and_b32 s44, s20, 0xffff
+; SI-NEXT: s_lshl_b32 s54, s62, 16
; SI-NEXT: s_or_b32 s62, s44, s42
-; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
+; SI-NEXT: s_mov_b32 s44, s79
+; SI-NEXT: s_lshr_b64 s[78:79], s[42:43], 16
; SI-NEXT: s_and_b32 s42, s22, 0xffff
-; SI-NEXT: s_mov_b32 s69, s67
-; SI-NEXT: s_mov_b32 s67, s65
-; SI-NEXT: s_mov_b32 s65, s96
-; SI-NEXT: s_mov_b32 s96, s87
-; SI-NEXT: s_mov_b32 s87, s97
-; SI-NEXT: s_mov_b32 s97, s29
-; SI-NEXT: s_mov_b32 s29, s54
-; SI-NEXT: s_mov_b32 s27, s85
-; SI-NEXT: s_lshl_b32 s54, s58, 16
+; SI-NEXT: s_lshl_b32 vcc_lo, s58, 16
; SI-NEXT: s_or_b32 s58, s42, s40
-; SI-NEXT: s_lshr_b64 s[84:85], s[40:41], 16
+; SI-NEXT: s_mov_b32 s42, s89
+; SI-NEXT: s_lshr_b64 s[88:89], s[40:41], 16
; SI-NEXT: s_and_b32 s40, s24, 0xffff
; SI-NEXT: s_or_b32 s56, s40, s14
-; SI-NEXT: s_mov_b32 s57, s15
-; SI-NEXT: s_lshr_b64 s[14:15], s[14:15], 16
-; SI-NEXT: v_writelane_b32 v31, s14, 10
-; SI-NEXT: v_writelane_b32 v31, s15, 11
+; SI-NEXT: s_mov_b32 s40, s91
+; SI-NEXT: s_lshr_b64 s[90:91], s[14:15], 16
; SI-NEXT: s_and_b32 s14, s26, 0xffff
-; SI-NEXT: s_mov_b32 s61, s47
+; SI-NEXT: s_mov_b32 s77, s46
; SI-NEXT: s_or_b32 s46, s14, s12
-; SI-NEXT: s_mov_b32 s47, s13
-; SI-NEXT: s_lshr_b64 s[12:13], s[12:13], 16
-; SI-NEXT: v_writelane_b32 v31, s12, 12
-; SI-NEXT: v_writelane_b32 v31, s13, 13
+; SI-NEXT: s_mov_b32 s14, s93
+; SI-NEXT: s_lshr_b64 s[92:93], s[12:13], 16
; SI-NEXT: s_and_b32 s12, s28, 0xffff
-; SI-NEXT: s_mov_b32 s73, s45
+; SI-NEXT: s_mov_b32 s79, s44
; SI-NEXT: s_or_b32 s44, s12, s10
-; SI-NEXT: s_mov_b32 s45, s11
-; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 16
-; SI-NEXT: v_writelane_b32 v31, s10, 14
-; SI-NEXT: s_lshl_b32 s8, s21, 16
-; SI-NEXT: v_writelane_b32 v31, s11, 15
+; SI-NEXT: s_mov_b32 s12, s95
+; SI-NEXT: s_lshr_b64 s[94:95], s[10:11], 16
; SI-NEXT: s_and_b32 s10, s99, 0xffff
-; SI-NEXT: s_mov_b32 s63, s43
+; SI-NEXT: s_mov_b32 s89, s42
; SI-NEXT: s_or_b32 s42, s10, s8
-; SI-NEXT: s_mov_b32 s43, s9
-; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16
-; SI-NEXT: v_writelane_b32 v31, s8, 16
-; SI-NEXT: v_writelane_b32 v31, s9, 17
+; SI-NEXT: s_mov_b32 s10, s31
+; SI-NEXT: s_lshr_b64 s[30:31], s[8:9], 16
; SI-NEXT: s_and_b32 s8, s98, 0xffff
-; SI-NEXT: s_mov_b32 s59, s41
+; SI-NEXT: s_mov_b32 s91, s40
; SI-NEXT: s_or_b32 s40, s8, s6
-; SI-NEXT: s_mov_b32 s41, s7
-; SI-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
-; SI-NEXT: v_writelane_b32 v31, s6, 18
-; SI-NEXT: v_writelane_b32 v31, s7, 19
+; SI-NEXT: s_mov_b32 s8, s35
+; SI-NEXT: s_lshr_b64 s[34:35], s[6:7], 16
; SI-NEXT: s_and_b32 s6, s64, 0xffff
+; SI-NEXT: s_mov_b32 s93, s14
; SI-NEXT: s_or_b32 s14, s6, s4
-; SI-NEXT: s_mov_b32 s15, s5
-; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
-; SI-NEXT: v_writelane_b32 v31, s4, 20
-; SI-NEXT: v_writelane_b32 v31, s5, 21
+; SI-NEXT: s_mov_b32 s6, s37
+; SI-NEXT: s_lshr_b64 s[36:37], s[4:5], 16
; SI-NEXT: s_and_b32 s4, s66, 0xffff
+; SI-NEXT: s_mov_b32 s95, s12
; SI-NEXT: s_or_b32 s12, s4, vcc_lo
-; SI-NEXT: s_lshr_b64 s[4:5], vcc, 16
-; SI-NEXT: v_writelane_b32 v31, s4, 22
-; SI-NEXT: v_writelane_b32 v31, s5, 23
+; SI-NEXT: s_mov_b32 s4, s39
+; SI-NEXT: s_lshr_b64 s[38:39], vcc, 16
+; SI-NEXT: s_lshl_b32 s48, s59, 16
+; SI-NEXT: s_mov_b32 s39, s4
; SI-NEXT: s_and_b32 s4, s68, 0xffff
+; SI-NEXT: s_mov_b32 s31, s10
; SI-NEXT: s_or_b32 s10, s4, s48
-; SI-NEXT: s_lshr_b64 s[4:5], s[48:49], 16
-; SI-NEXT: v_writelane_b32 v31, s4, 24
-; SI-NEXT: v_writelane_b32 v31, s5, 25
-; SI-NEXT: s_mov_b32 s48, s70
-; SI-NEXT: s_and_b32 s4, s37, 0xffff
-; SI-NEXT: s_lshl_b32 s52, s78, 16
-; SI-NEXT: v_readlane_b32 s70, v31, 26
+; SI-NEXT: s_and_b32 s4, s17, 0xffff
+; SI-NEXT: s_mov_b32 s35, s8
; SI-NEXT: s_or_b32 s8, s4, s50
-; SI-NEXT: s_and_b32 s4, s48, 0xffff
+; SI-NEXT: s_and_b32 s4, s75, 0xffff
+; SI-NEXT: s_mov_b32 s37, s6
+; SI-NEXT: s_or_b32 s6, s4, s52
+; SI-NEXT: s_and_b32 s4, s16, 0xffff
+; SI-NEXT: s_mov_b32 s73, s45
+; SI-NEXT: s_mov_b32 s63, s43
+; SI-NEXT: s_mov_b32 s59, s41
+; SI-NEXT: s_mov_b32 s57, s15
+; SI-NEXT: s_mov_b32 s45, s11
+; SI-NEXT: s_mov_b32 s43, s9
+; SI-NEXT: s_mov_b32 s41, s7
+; SI-NEXT: s_mov_b32 s15, s5
+; SI-NEXT: s_mov_b32 s11, s49
+; SI-NEXT: s_lshr_b64 s[48:49], s[48:49], 16
; SI-NEXT: s_mov_b32 s9, s51
; SI-NEXT: s_lshr_b64 s[50:51], s[50:51], 16
-; SI-NEXT: s_or_b32 s6, s4, s52
; SI-NEXT: s_mov_b32 s7, s53
; SI-NEXT: s_lshr_b64 s[52:53], s[52:53], 16
-; SI-NEXT: s_mov_b32 s20, s18
-; SI-NEXT: s_mov_b32 s18, s74
-; SI-NEXT: s_and_b32 s4, s70, 0xffff
-; SI-NEXT: s_lshr_b64 s[74:75], s[54:55], 16
-; SI-NEXT: s_mov_b32 s13, vcc_hi
-; SI-NEXT: s_mov_b32 s11, s49
-; SI-NEXT: s_mov_b32 s49, s88
-; SI-NEXT: s_mov_b32 s88, s90
-; SI-NEXT: s_mov_b32 s90, s71
-; SI-NEXT: s_mov_b32 s71, s83
-; SI-NEXT: s_mov_b32 s51, s80
-; SI-NEXT: s_mov_b32 s80, s23
-; SI-NEXT: s_mov_b32 s53, s92
-; SI-NEXT: s_mov_b32 s92, s81
-; SI-NEXT: s_mov_b32 s81, s94
-; SI-NEXT: s_mov_b32 s22, s16
; SI-NEXT: s_or_b32 s4, s4, s54
; SI-NEXT: s_mov_b32 s5, s55
-; SI-NEXT: s_mov_b32 s55, s82
-; SI-NEXT: s_mov_b32 s82, s86
-; SI-NEXT: s_mov_b32 s86, s30
-; SI-NEXT: s_mov_b32 s30, s34
-; SI-NEXT: s_mov_b32 s34, s36
-; SI-NEXT: s_mov_b32 s36, s38
-; SI-NEXT: s_mov_b32 s38, s39
-; SI-NEXT: s_mov_b32 s39, s35
-; SI-NEXT: s_mov_b32 s19, s25
-; SI-NEXT: s_mov_b32 s85, s27
-; SI-NEXT: s_mov_b32 s54, s29
-; SI-NEXT: s_mov_b32 s29, s97
-; SI-NEXT: s_mov_b32 s97, s87
-; SI-NEXT: s_mov_b32 s87, s96
-; SI-NEXT: s_mov_b32 s96, s65
-; SI-NEXT: s_mov_b32 s65, s67
-; SI-NEXT: s_mov_b32 s67, s69
-; SI-NEXT: v_readlane_b32 s69, v31, 29
-; SI-NEXT: v_readlane_b32 s17, v31, 28
-; SI-NEXT: v_readlane_b32 s75, v31, 27
+; SI-NEXT: s_lshr_b64 s[54:55], s[54:55], 16
+; SI-NEXT: s_mov_b32 s47, s13
+; SI-NEXT: s_mov_b32 s13, vcc_hi
+; SI-NEXT: s_lshr_b32 s49, s18, 16
+; SI-NEXT: s_lshr_b32 s51, s20, 16
+; SI-NEXT: s_lshr_b32 s53, s22, 16
+; SI-NEXT: s_lshr_b32 s55, s24, 16
; SI-NEXT: s_cbranch_execnz .LBB57_3
; SI-NEXT: .LBB57_2: ; %cmp.true
-; SI-NEXT: s_add_i32 s16, s70, 3
+; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: v_readlane_b32 s5, v31, 9
; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_lshl_b32 s5, s5, 16
-; SI-NEXT: s_add_i32 s70, s75, 3
+; SI-NEXT: s_add_i32 s70, s70, 3
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_and_b32 s5, s70, 0xffff
; SI-NEXT: s_lshl_b32 s6, s86, 16
-; SI-NEXT: s_add_i32 s75, s48, 3
+; SI-NEXT: s_add_i32 s75, s75, 3
+; SI-NEXT: v_readlane_b32 s7, v31, 8
; SI-NEXT: s_or_b32 s5, s6, s5
; SI-NEXT: s_and_b32 s6, s75, 0xffff
-; SI-NEXT: s_lshl_b32 s7, s78, 16
-; SI-NEXT: s_add_i32 s74, s17, 3
+; SI-NEXT: s_lshl_b32 s7, s7, 16
+; SI-NEXT: s_add_i32 s74, s74, 3
; SI-NEXT: s_or_b32 s6, s7, s6
; SI-NEXT: s_and_b32 s7, s74, 0xffff
-; SI-NEXT: s_lshl_b32 s8, s82, 16
-; SI-NEXT: s_add_i32 s17, s37, 3
+; SI-NEXT: s_lshl_b32 s8, s85, 16
+; SI-NEXT: s_add_i32 s17, s17, 3
+; SI-NEXT: v_readlane_b32 s9, v31, 7
; SI-NEXT: s_or_b32 s7, s8, s7
; SI-NEXT: s_and_b32 s8, s17, 0xffff
-; SI-NEXT: s_lshl_b32 s9, s39, 16
+; SI-NEXT: s_lshl_b32 s9, s9, 16
; SI-NEXT: s_add_i32 s69, s69, 3
; SI-NEXT: s_or_b32 s8, s9, s8
; SI-NEXT: s_and_b32 s9, s69, 0xffff
-; SI-NEXT: s_lshl_b32 s10, s81, 16
+; SI-NEXT: s_lshl_b32 s10, s84, 16
; SI-NEXT: s_add_i32 s68, s68, 3
+; SI-NEXT: v_readlane_b32 s11, v31, 6
; SI-NEXT: s_or_b32 s9, s10, s9
; SI-NEXT: s_and_b32 s10, s68, 0xffff
-; SI-NEXT: s_lshl_b32 s11, s38, 16
+; SI-NEXT: s_lshl_b32 s11, s11, 16
; SI-NEXT: s_add_i32 s67, s67, 3
; SI-NEXT: s_or_b32 s10, s11, s10
; SI-NEXT: s_and_b32 s11, s67, 0xffff
-; SI-NEXT: s_lshl_b32 s12, s80, 16
+; SI-NEXT: s_lshl_b32 s12, s83, 16
; SI-NEXT: s_add_i32 s66, s66, 3
+; SI-NEXT: v_readlane_b32 s13, v31, 5
; SI-NEXT: s_or_b32 s11, s12, s11
; SI-NEXT: s_and_b32 s12, s66, 0xffff
-; SI-NEXT: s_lshl_b32 s13, s36, 16
+; SI-NEXT: s_lshl_b32 s13, s13, 16
; SI-NEXT: s_add_i32 s65, s65, 3
; SI-NEXT: s_or_b32 s12, s13, s12
; SI-NEXT: s_and_b32 s13, s65, 0xffff
-; SI-NEXT: s_lshl_b32 s14, s71, 16
+; SI-NEXT: s_lshl_b32 s14, s82, 16
; SI-NEXT: s_add_i32 s64, s64, 3
+; SI-NEXT: v_readlane_b32 s15, v31, 4
; SI-NEXT: s_or_b32 s13, s14, s13
; SI-NEXT: s_and_b32 s14, s64, 0xffff
-; SI-NEXT: s_lshl_b32 s15, s34, 16
+; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_add_i32 s96, s96, 3
; SI-NEXT: s_or_b32 s14, s15, s14
; SI-NEXT: s_and_b32 s15, s96, 0xffff
-; SI-NEXT: s_lshl_b32 s16, s55, 16
+; SI-NEXT: s_lshl_b32 s16, s81, 16
; SI-NEXT: s_add_i32 s98, s98, 3
+; SI-NEXT: v_readlane_b32 s17, v31, 3
; SI-NEXT: s_or_b32 s15, s16, s15
; SI-NEXT: s_and_b32 s16, s98, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s30, 16
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s87, s87, 3
; SI-NEXT: s_add_i32 s40, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s87, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s53, 16
+; SI-NEXT: s_lshl_b32 s17, s80, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s99, s99, 3
+; SI-NEXT: v_readlane_b32 s17, v31, 2
; SI-NEXT: s_add_i32 s41, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s99, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s21, 16
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s97, s97, 3
; SI-NEXT: s_add_i32 s42, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s97, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s51, 16
+; SI-NEXT: s_lshl_b32 s17, s71, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s28, s28, 3
+; SI-NEXT: v_readlane_b32 s17, v31, 1
; SI-NEXT: s_add_i32 s43, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s28, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s92, 16
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s44, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s29, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s79, 16
+; SI-NEXT: s_lshl_b32 s17, s31, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s26, s26, 3
+; SI-NEXT: v_readlane_b32 s17, v31, 0
; SI-NEXT: s_add_i32 s45, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s26, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s90, 16
+; SI-NEXT: s_lshl_b32 s17, s17, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s27, s89, 3
+; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s46, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s27, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s31, 16
+; SI-NEXT: s_lshl_b32 s17, s95, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s47, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s24, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s88, 16
+; SI-NEXT: s_lshl_b32 s17, s55, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s25, s77, 3
+; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s56, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s25, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s95, 16
+; SI-NEXT: s_lshl_b32 s17, s93, 16
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s57, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v31, 8
-; SI-NEXT: s_add_i32 s22, s16, 3
; SI-NEXT: s_and_b32 s16, s22, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s49, 16
+; SI-NEXT: s_lshl_b32 s17, s53, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s23, s54, 3
+; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s58, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s23, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s93, 16
+; SI-NEXT: s_lshl_b32 s17, s91, 16
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s59, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v31, 7
-; SI-NEXT: s_add_i32 s20, s16, 3
; SI-NEXT: s_and_b32 s16, s20, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s76, 16
+; SI-NEXT: s_lshl_b32 s17, s51, 16
; SI-NEXT: s_or_b32 s16, s17, s16
-; SI-NEXT: s_add_i32 s21, s85, 3
+; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s62, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s21, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s91, 16
+; SI-NEXT: s_lshl_b32 s17, s89, 16
; SI-NEXT: s_or_b32 s16, s17, s16
+; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s63, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v31, 6
-; SI-NEXT: s_add_i32 s18, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v31, 1
; SI-NEXT: s_and_b32 s16, s18, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s49, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s19, s19, 3
-; SI-NEXT: v_readlane_b32 s17, v31, 0
; SI-NEXT: s_add_i32 s72, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s19, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s79, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s73, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v31, 4
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v31, 5
+; SI-NEXT: s_add_i32 s16, s37, 3
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s39, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s60, s16, 0x30000
-; SI-NEXT: v_readlane_b32 s16, v31, 2
-; SI-NEXT: s_add_i32 s16, s16, 3
-; SI-NEXT: v_readlane_b32 s17, v31, 3
+; SI-NEXT: s_add_i32 s16, s35, 3
; SI-NEXT: s_and_b32 s16, s16, 0xffff
-; SI-NEXT: s_lshl_b32 s17, s17, 16
+; SI-NEXT: s_lshl_b32 s17, s77, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s61, s16, 0x30000
-; SI-NEXT: s_lshr_b64 s[16:17], s[56:57], 16
-; SI-NEXT: v_writelane_b32 v31, s16, 10
-; SI-NEXT: v_writelane_b32 v31, s17, 11
-; SI-NEXT: s_lshr_b64 s[16:17], s[46:47], 16
-; SI-NEXT: v_writelane_b32 v31, s16, 12
-; SI-NEXT: v_writelane_b32 v31, s17, 13
-; SI-NEXT: s_lshr_b64 s[16:17], s[44:45], 16
-; SI-NEXT: v_writelane_b32 v31, s16, 14
-; SI-NEXT: v_writelane_b32 v31, s17, 15
-; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
-; SI-NEXT: v_writelane_b32 v31, s16, 16
-; SI-NEXT: v_writelane_b32 v31, s17, 17
-; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 16
-; SI-NEXT: s_add_i32 s14, s14, 0x30000
-; SI-NEXT: s_add_i32 s15, s15, 0x30000
-; SI-NEXT: v_writelane_b32 v31, s16, 18
-; SI-NEXT: v_writelane_b32 v31, s17, 19
-; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 16
-; SI-NEXT: s_add_i32 s12, s12, 0x30000
-; SI-NEXT: s_add_i32 s13, s13, 0x30000
-; SI-NEXT: v_writelane_b32 v31, s16, 20
-; SI-NEXT: v_writelane_b32 v31, s17, 21
-; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 16
-; SI-NEXT: s_add_i32 s10, s10, 0x30000
-; SI-NEXT: s_add_i32 s11, s11, 0x30000
-; SI-NEXT: v_writelane_b32 v31, s16, 22
-; SI-NEXT: v_writelane_b32 v31, s17, 23
-; SI-NEXT: s_lshr_b64 s[16:17], s[10:11], 16
+; SI-NEXT: s_add_i32 s4, s4, 0x30000
+; SI-NEXT: s_add_i32 s5, s5, 0x30000
; SI-NEXT: s_add_i32 s6, s6, 0x30000
; SI-NEXT: s_add_i32 s7, s7, 0x30000
; SI-NEXT: s_add_i32 s8, s8, 0x30000
; SI-NEXT: s_add_i32 s9, s9, 0x30000
-; SI-NEXT: v_writelane_b32 v31, s16, 24
-; SI-NEXT: s_add_i32 s4, s4, 0x30000
-; SI-NEXT: s_add_i32 s5, s5, 0x30000
-; SI-NEXT: v_writelane_b32 v31, s17, 25
+; SI-NEXT: s_add_i32 s10, s10, 0x30000
+; SI-NEXT: s_add_i32 s11, s11, 0x30000
+; SI-NEXT: s_add_i32 s12, s12, 0x30000
+; SI-NEXT: s_add_i32 s13, s13, 0x30000
+; SI-NEXT: s_add_i32 s14, s14, 0x30000
+; SI-NEXT: s_add_i32 s15, s15, 0x30000
+; SI-NEXT: s_lshr_b64 s[16:17], s[60:61], 16
+; SI-NEXT: s_lshr_b64 s[76:77], s[72:73], 16
+; SI-NEXT: s_lshr_b64 s[78:79], s[62:63], 16
+; SI-NEXT: s_lshr_b64 s[88:89], s[58:59], 16
+; SI-NEXT: s_lshr_b64 s[90:91], s[56:57], 16
+; SI-NEXT: s_lshr_b64 s[92:93], s[46:47], 16
+; SI-NEXT: s_lshr_b64 s[94:95], s[44:45], 16
+; SI-NEXT: s_lshr_b64 s[30:31], s[42:43], 16
+; SI-NEXT: v_writelane_b32 v31, s16, 10
+; SI-NEXT: s_lshr_b64 s[34:35], s[40:41], 16
+; SI-NEXT: s_lshr_b64 s[36:37], s[14:15], 16
+; SI-NEXT: s_lshr_b64 s[38:39], s[12:13], 16
+; SI-NEXT: s_lshr_b64 s[48:49], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[50:51], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[52:53], s[6:7], 16
-; SI-NEXT: s_lshr_b32 s16, s61, 16
-; SI-NEXT: s_lshr_b64 s[18:19], s[60:61], 16
-; SI-NEXT: s_lshr_b64 s[20:21], s[72:73], 16
-; SI-NEXT: s_lshr_b64 s[22:23], s[62:63], 16
-; SI-NEXT: s_lshr_b64 s[84:85], s[58:59], 16
-; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16
-; SI-NEXT: v_writelane_b32 v31, s16, 3
-; SI-NEXT: s_lshr_b32 s16, s73, 16
-; SI-NEXT: s_lshr_b32 s91, s63, 16
-; SI-NEXT: s_lshr_b32 s93, s59, 16
-; SI-NEXT: s_lshr_b32 s95, s57, 16
-; SI-NEXT: s_lshr_b32 s31, s47, 16
-; SI-NEXT: s_lshr_b32 s79, s45, 16
-; SI-NEXT: s_lshr_b32 s51, s43, 16
-; SI-NEXT: s_lshr_b32 s53, s41, 16
-; SI-NEXT: s_lshr_b32 s55, s15, 16
-; SI-NEXT: s_lshr_b32 s71, s13, 16
-; SI-NEXT: s_lshr_b32 s80, s11, 16
-; SI-NEXT: s_lshr_b32 s81, s9, 16
-; SI-NEXT: s_lshr_b32 s82, s7, 16
+; SI-NEXT: s_lshr_b64 s[54:55], s[4:5], 16
+; SI-NEXT: s_lshr_b32 s77, s61, 16
+; SI-NEXT: s_lshr_b32 s79, s73, 16
+; SI-NEXT: s_lshr_b32 s89, s63, 16
+; SI-NEXT: s_lshr_b32 s91, s59, 16
+; SI-NEXT: s_lshr_b32 s93, s57, 16
+; SI-NEXT: s_lshr_b32 s95, s47, 16
+; SI-NEXT: s_lshr_b32 s31, s45, 16
+; SI-NEXT: s_lshr_b32 s71, s43, 16
+; SI-NEXT: s_lshr_b32 s80, s41, 16
+; SI-NEXT: s_lshr_b32 s81, s15, 16
+; SI-NEXT: s_lshr_b32 s82, s13, 16
+; SI-NEXT: s_lshr_b32 s83, s11, 16
+; SI-NEXT: s_lshr_b32 s84, s9, 16
+; SI-NEXT: s_lshr_b32 s85, s7, 16
; SI-NEXT: s_lshr_b32 s86, s5, 16
-; SI-NEXT: v_writelane_b32 v31, s16, 0
+; SI-NEXT: v_writelane_b32 v31, s17, 11
; SI-NEXT: .LBB57_3: ; %end
+; SI-NEXT: v_readlane_b32 s18, v31, 10
; SI-NEXT: s_and_b32 s16, s60, 0xffff
; SI-NEXT: s_lshl_b32 s17, s18, 16
-; SI-NEXT: v_readlane_b32 s18, v31, 3
+; SI-NEXT: v_readlane_b32 s19, v31, 11
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s61, 0xffff
-; SI-NEXT: s_lshl_b32 s18, s18, 16
+; SI-NEXT: s_lshl_b32 s18, s77, 16
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s18, s72, 0xffff
-; SI-NEXT: s_lshl_b32 s19, s20, 16
-; SI-NEXT: v_readlane_b32 s20, v31, 0
+; SI-NEXT: s_lshl_b32 s19, s76, 16
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_and_b32 s19, s73, 0xffff
-; SI-NEXT: s_lshl_b32 s20, s20, 16
+; SI-NEXT: s_lshl_b32 s20, s79, 16
; SI-NEXT: s_or_b32 s19, s19, s20
; SI-NEXT: s_and_b32 s20, s62, 0xffff
-; SI-NEXT: s_lshl_b32 s21, s22, 16
+; SI-NEXT: s_lshl_b32 s21, s78, 16
; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s21, s63, 0xffff
-; SI-NEXT: s_lshl_b32 s22, s91, 16
+; SI-NEXT: s_lshl_b32 s22, s89, 16
; SI-NEXT: s_or_b32 s21, s21, s22
; SI-NEXT: s_and_b32 s22, s58, 0xffff
-; SI-NEXT: s_lshl_b32 s23, s84, 16
+; SI-NEXT: s_lshl_b32 s23, s88, 16
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_and_b32 s23, s59, 0xffff
-; SI-NEXT: s_lshl_b32 s24, s93, 16
-; SI-NEXT: v_readlane_b32 s26, v31, 10
+; SI-NEXT: s_lshl_b32 s24, s91, 16
; SI-NEXT: s_or_b32 s23, s23, s24
; SI-NEXT: s_and_b32 s24, s56, 0xffff
-; SI-NEXT: s_lshl_b32 s25, s26, 16
-; SI-NEXT: v_readlane_b32 s27, v31, 11
+; SI-NEXT: s_lshl_b32 s25, s90, 16
; SI-NEXT: s_or_b32 s24, s24, s25
; SI-NEXT: s_and_b32 s25, s57, 0xffff
-; SI-NEXT: s_lshl_b32 s26, s95, 16
-; SI-NEXT: v_readlane_b32 s28, v31, 12
+; SI-NEXT: s_lshl_b32 s26, s93, 16
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s46, 0xffff
-; SI-NEXT: s_lshl_b32 s27, s28, 16
-; SI-NEXT: v_readlane_b32 s29, v31, 13
+; SI-NEXT: s_lshl_b32 s27, s92, 16
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s47, 0xffff
-; SI-NEXT: s_lshl_b32 s28, s31, 16
-; SI-NEXT: v_readlane_b32 s46, v31, 14
+; SI-NEXT: s_lshl_b32 s28, s95, 16
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s44, 0xffff
-; SI-NEXT: s_lshl_b32 s29, s46, 16
+; SI-NEXT: s_lshl_b32 s29, s94, 16
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s29, s45, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s79, 16
+; SI-NEXT: s_lshl_b32 s44, s31, 16
; SI-NEXT: s_or_b32 s29, s29, s44
-; SI-NEXT: v_readlane_b32 s44, v31, 16
; SI-NEXT: s_and_b32 s42, s42, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s44, 16
-; SI-NEXT: v_readlane_b32 s45, v31, 17
+; SI-NEXT: s_lshl_b32 s44, s30, 16
; SI-NEXT: s_or_b32 s42, s42, s44
; SI-NEXT: s_and_b32 s43, s43, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s51, 16
+; SI-NEXT: s_lshl_b32 s44, s71, 16
; SI-NEXT: s_or_b32 s43, s43, s44
-; SI-NEXT: v_readlane_b32 s44, v31, 18
; SI-NEXT: s_and_b32 s40, s40, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s44, 16
-; SI-NEXT: v_readlane_b32 s45, v31, 19
+; SI-NEXT: s_lshl_b32 s44, s34, 16
; SI-NEXT: s_or_b32 s40, s40, s44
; SI-NEXT: s_and_b32 s41, s41, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s53, 16
+; SI-NEXT: s_lshl_b32 s44, s80, 16
; SI-NEXT: s_or_b32 s41, s41, s44
-; SI-NEXT: v_readlane_b32 s44, v31, 20
; SI-NEXT: s_and_b32 s14, s14, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s44, 16
-; SI-NEXT: v_readlane_b32 s45, v31, 21
+; SI-NEXT: s_lshl_b32 s44, s36, 16
; SI-NEXT: s_or_b32 s14, s14, s44
; SI-NEXT: s_and_b32 s15, s15, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s55, 16
+; SI-NEXT: s_lshl_b32 s44, s81, 16
; SI-NEXT: s_or_b32 s15, s15, s44
-; SI-NEXT: v_readlane_b32 s44, v31, 22
; SI-NEXT: s_and_b32 s12, s12, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s44, 16
-; SI-NEXT: v_readlane_b32 s45, v31, 23
+; SI-NEXT: s_lshl_b32 s44, s38, 16
; SI-NEXT: s_or_b32 s12, s12, s44
; SI-NEXT: s_and_b32 s13, s13, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s71, 16
+; SI-NEXT: s_lshl_b32 s44, s82, 16
; SI-NEXT: s_or_b32 s13, s13, s44
-; SI-NEXT: v_readlane_b32 s44, v31, 24
; SI-NEXT: s_and_b32 s10, s10, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s44, 16
+; SI-NEXT: s_lshl_b32 s44, s48, 16
; SI-NEXT: s_or_b32 s10, s10, s44
; SI-NEXT: s_and_b32 s11, s11, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s80, 16
+; SI-NEXT: s_lshl_b32 s44, s83, 16
; SI-NEXT: s_or_b32 s11, s11, s44
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_lshl_b32 s44, s50, 16
; SI-NEXT: s_or_b32 s8, s8, s44
; SI-NEXT: s_and_b32 s9, s9, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s81, 16
+; SI-NEXT: s_lshl_b32 s44, s84, 16
; SI-NEXT: s_or_b32 s9, s9, s44
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_lshl_b32 s44, s52, 16
; SI-NEXT: s_or_b32 s6, s6, s44
; SI-NEXT: s_and_b32 s7, s7, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s82, 16
+; SI-NEXT: s_lshl_b32 s44, s85, 16
; SI-NEXT: s_or_b32 s7, s7, s44
; SI-NEXT: s_and_b32 s4, s4, 0xffff
-; SI-NEXT: s_lshl_b32 s44, s74, 16
+; SI-NEXT: s_lshl_b32 s44, s54, 16
; SI-NEXT: s_or_b32 s4, s4, s44
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s44, s86, 16
; SI-NEXT: s_or_b32 s5, s5, s44
-; SI-NEXT: v_readlane_b32 s47, v31, 15
-; SI-NEXT: v_readlane_b32 s45, v31, 25
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
@@ -47769,50 +47774,36 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i
; SI-NEXT: .LBB57_4:
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: v_writelane_b32 v31, s4, 10
-; SI-NEXT: v_writelane_b32 v31, s5, 11
-; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr60
-; SI-NEXT: ; implicit-def: $sgpr18
+; SI-NEXT: v_writelane_b32 v31, s5, 11
; SI-NEXT: ; implicit-def: $sgpr72
-; SI-NEXT: ; implicit-def: $sgpr20
+; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr62
-; SI-NEXT: ; implicit-def: $sgpr22
+; SI-NEXT: ; implicit-def: $sgpr78
; SI-NEXT: ; implicit-def: $sgpr58
-; SI-NEXT: ; implicit-def: $sgpr84
+; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr44
+; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr42
+; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: ; implicit-def: $sgpr40
+; SI-NEXT: ; implicit-def: $sgpr34
; SI-NEXT: ; implicit-def: $sgpr14
+; SI-NEXT: ; implicit-def: $sgpr36
; SI-NEXT: ; implicit-def: $sgpr12
+; SI-NEXT: ; implicit-def: $sgpr38
; SI-NEXT: ; implicit-def: $sgpr10
+; SI-NEXT: ; implicit-def: $sgpr48
; SI-NEXT: ; implicit-def: $sgpr8
; SI-NEXT: ; implicit-def: $sgpr50
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr52
-; SI-NEXT: ; implicit-def: $sgpr74
-; SI-NEXT: v_writelane_b32 v31, s4, 12
-; SI-NEXT: v_writelane_b32 v31, s5, 13
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 14
-; SI-NEXT: v_writelane_b32 v31, s5, 15
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 16
-; SI-NEXT: v_writelane_b32 v31, s5, 17
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 18
-; SI-NEXT: v_writelane_b32 v31, s5, 19
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 20
-; SI-NEXT: v_writelane_b32 v31, s5, 21
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 22
-; SI-NEXT: v_writelane_b32 v31, s5, 23
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: v_writelane_b32 v31, s4, 24
-; SI-NEXT: v_writelane_b32 v31, s5, 25
; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr54
; SI-NEXT: s_branch .LBB57_2
;
; VI-LABEL: bitcast_v60i16_to_v60f16_scalar:
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
index 1269b2d0f7367..83b50d93c851f 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
@@ -17,13 +17,13 @@ define void @wobble() #0 {
; CHECK-NEXT: s_or_saveexec_b32 s17, -1
; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b32 exec_lo, s17
-; CHECK-NEXT: v_writelane_b32 v43, s16, 15
+; CHECK-NEXT: v_writelane_b32 v43, s16, 17
+; CHECK-NEXT: s_addk_i32 s32, 0x400
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: v_mov_b32_e32 v41, 0
-; CHECK-NEXT: s_addk_i32 s32, 0x400
; CHECK-NEXT: v_writelane_b32 v43, s30, 0
; CHECK-NEXT: v_writelane_b32 v43, s31, 1
; CHECK-NEXT: v_writelane_b32 v43, s34, 2
@@ -32,15 +32,14 @@ define void @wobble() #0 {
; CHECK-NEXT: v_writelane_b32 v43, s36, 4
; CHECK-NEXT: v_writelane_b32 v43, s37, 5
; CHECK-NEXT: s_mov_b64 s[36:37], s[8:9]
-; CHECK-NEXT: s_mov_b64 s[8:9], src_private_base
-; CHECK-NEXT: v_mov_b32_e32 v42, s9
; CHECK-NEXT: v_writelane_b32 v43, s38, 6
; CHECK-NEXT: v_writelane_b32 v43, s39, 7
; CHECK-NEXT: s_mov_b64 s[38:39], s[6:7]
+; CHECK-NEXT: s_mov_b64 s[6:7], src_private_base
+; CHECK-NEXT: v_mov_b32_e32 v42, s7
; CHECK-NEXT: v_writelane_b32 v43, s48, 8
; CHECK-NEXT: v_writelane_b32 v43, s49, 9
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
-; CHECK-NEXT: s_lshr_b32 s5, s33, 5
; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: v_writelane_b32 v43, s50, 10
; CHECK-NEXT: s_mov_b32 s50, s15
@@ -51,8 +50,13 @@ define void @wobble() #0 {
; CHECK-NEXT: v_writelane_b32 v43, s53, 13
; CHECK-NEXT: s_mov_b32 s53, s12
; CHECK-NEXT: v_writelane_b32 v43, s54, 14
-; CHECK-NEXT: s_add_i32 s54, s5, 16
-; CHECK-NEXT: s_inst_prefetch 0x1
+; CHECK-NEXT: v_writelane_b32 v43, s55, 15
+; CHECK-NEXT: s_getpc_b64 s[54:55]
+; CHECK-NEXT: s_add_u32 s54, s54, foo at rel32@lo+4
+; CHECK-NEXT: s_addc_u32 s55, s55, foo at rel32@hi+12
+; CHECK-NEXT: s_lshr_b32 s5, s33, 5
+; CHECK-NEXT: v_writelane_b32 v43, s64, 16
+; CHECK-NEXT: s_add_i32 s64, s5, 16
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB0_1: ; %bb1
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -71,26 +75,24 @@ define void @wobble() #0 {
; CHECK-NEXT: s_mov_b32 s14, s51
; CHECK-NEXT: s_mov_b32 s15, s50
; CHECK-NEXT: s_cselect_b32 s4, 0, s5
-; CHECK-NEXT: s_cselect_b32 s5, 4, s54
+; CHECK-NEXT: s_cselect_b32 s5, 4, s64
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s5
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, foo at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, foo at rel32@hi+12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
; CHECK-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[54:55]
; CHECK-NEXT: s_mov_b32 s4, 1
; CHECK-NEXT: s_mov_b32 vcc_lo, exec_lo
; CHECK-NEXT: s_cbranch_vccnz .LBB0_1
; CHECK-NEXT: ; %bb.2: ; %DummyReturnBlock
-; CHECK-NEXT: s_inst_prefetch 0x2
; CHECK-NEXT: s_clause 0x2 ; 12-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33
; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4
; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8
+; CHECK-NEXT: v_readlane_b32 s64, v43, 16
+; CHECK-NEXT: v_readlane_b32 s55, v43, 15
; CHECK-NEXT: v_readlane_b32 s54, v43, 14
; CHECK-NEXT: v_readlane_b32 s53, v43, 13
; CHECK-NEXT: v_readlane_b32 s52, v43, 12
@@ -107,7 +109,7 @@ define void @wobble() #0 {
; CHECK-NEXT: v_readlane_b32 s31, v43, 1
; CHECK-NEXT: v_readlane_b32 s30, v43, 0
; CHECK-NEXT: s_mov_b32 s32, s33
-; CHECK-NEXT: v_readlane_b32 s4, v43, 15
+; CHECK-NEXT: v_readlane_b32 s4, v43, 17
; CHECK-NEXT: s_or_saveexec_b32 s5, -1
; CHECK-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
; CHECK-NEXT: s_mov_b32 exec_lo, s5
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
index beeeaa32cacfd..2be1464a96001 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
@@ -3184,76 +3184,76 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; GCN-NEXT: s_load_dword s6, s[4:5], 0x44
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; GCN-NEXT: s_load_dwordx2 s[42:43], s[4:5], 0x24
; GCN-NEXT: ; implicit-def: $vgpr6 : SGPR spill to VGPR lane
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_bfe_u32 s9, s0, 0xf0001
-; GCN-NEXT: s_lshr_b32 s42, s1, 16
-; GCN-NEXT: v_writelane_b32 v6, s4, 0
-; GCN-NEXT: v_writelane_b32 v6, s5, 1
; GCN-NEXT: s_lshr_b32 s4, s0, 16
-; GCN-NEXT: v_writelane_b32 v6, s4, 2
+; GCN-NEXT: v_writelane_b32 v6, s4, 0
; GCN-NEXT: s_lshr_b32 s4, s0, 17
-; GCN-NEXT: v_writelane_b32 v6, s4, 3
+; GCN-NEXT: v_writelane_b32 v6, s4, 1
; GCN-NEXT: s_lshr_b32 s4, s0, 18
-; GCN-NEXT: v_writelane_b32 v6, s4, 4
+; GCN-NEXT: v_writelane_b32 v6, s4, 2
; GCN-NEXT: s_lshr_b32 s4, s0, 19
-; GCN-NEXT: v_writelane_b32 v6, s4, 5
+; GCN-NEXT: v_writelane_b32 v6, s4, 3
; GCN-NEXT: s_lshr_b32 s4, s0, 20
-; GCN-NEXT: v_writelane_b32 v6, s4, 6
+; GCN-NEXT: v_writelane_b32 v6, s4, 4
; GCN-NEXT: s_lshr_b32 s4, s0, 21
-; GCN-NEXT: v_writelane_b32 v6, s4, 7
+; GCN-NEXT: v_writelane_b32 v6, s4, 5
; GCN-NEXT: s_lshr_b32 s4, s0, 22
-; GCN-NEXT: v_writelane_b32 v6, s4, 8
+; GCN-NEXT: v_writelane_b32 v6, s4, 6
; GCN-NEXT: s_lshr_b32 s4, s0, 23
-; GCN-NEXT: v_writelane_b32 v6, s4, 9
+; GCN-NEXT: v_writelane_b32 v6, s4, 7
; GCN-NEXT: s_lshr_b32 s4, s0, 24
-; GCN-NEXT: v_writelane_b32 v6, s4, 10
+; GCN-NEXT: v_writelane_b32 v6, s4, 8
; GCN-NEXT: s_lshr_b32 s4, s0, 25
-; GCN-NEXT: v_writelane_b32 v6, s4, 11
+; GCN-NEXT: v_writelane_b32 v6, s4, 9
; GCN-NEXT: s_lshr_b32 s4, s0, 26
-; GCN-NEXT: v_writelane_b32 v6, s4, 12
+; GCN-NEXT: v_writelane_b32 v6, s4, 10
; GCN-NEXT: s_lshr_b32 s4, s0, 27
-; GCN-NEXT: v_writelane_b32 v6, s4, 13
+; GCN-NEXT: v_writelane_b32 v6, s4, 11
; GCN-NEXT: s_lshr_b32 s4, s0, 28
-; GCN-NEXT: v_writelane_b32 v6, s4, 14
+; GCN-NEXT: v_writelane_b32 v6, s4, 12
; GCN-NEXT: s_lshr_b32 s4, s0, 29
-; GCN-NEXT: v_writelane_b32 v6, s4, 15
+; GCN-NEXT: v_writelane_b32 v6, s4, 13
; GCN-NEXT: s_lshr_b32 s4, s0, 30
-; GCN-NEXT: v_writelane_b32 v6, s4, 16
+; GCN-NEXT: v_writelane_b32 v6, s4, 14
; GCN-NEXT: s_lshr_b32 s4, s0, 31
+; GCN-NEXT: v_writelane_b32 v6, s4, 15
+; GCN-NEXT: s_lshr_b32 s4, s1, 16
+; GCN-NEXT: v_writelane_b32 v6, s4, 16
+; GCN-NEXT: s_lshr_b32 s4, s1, 17
; GCN-NEXT: v_writelane_b32 v6, s4, 17
-; GCN-NEXT: v_writelane_b32 v6, s9, 18
-; GCN-NEXT: s_bfe_u32 s9, s0, 0xe0002
-; GCN-NEXT: v_writelane_b32 v6, s9, 19
-; GCN-NEXT: s_bfe_u32 s9, s0, 0xd0003
-; GCN-NEXT: v_writelane_b32 v6, s9, 20
-; GCN-NEXT: s_bfe_u32 s9, s0, 0xc0004
-; GCN-NEXT: v_writelane_b32 v6, s9, 21
-; GCN-NEXT: s_bfe_u32 s9, s0, 0xb0005
-; GCN-NEXT: v_writelane_b32 v6, s9, 22
-; GCN-NEXT: s_bfe_u32 s9, s0, 0xa0006
-; GCN-NEXT: v_writelane_b32 v6, s9, 23
-; GCN-NEXT: s_bfe_u32 s9, s0, 0x90007
-; GCN-NEXT: v_writelane_b32 v6, s9, 24
-; GCN-NEXT: s_bfe_u32 s9, s0, 0x80008
-; GCN-NEXT: v_writelane_b32 v6, s9, 25
-; GCN-NEXT: s_bfe_u32 s9, s0, 0x70009
-; GCN-NEXT: v_writelane_b32 v6, s9, 26
-; GCN-NEXT: s_bfe_u32 s9, s0, 0x6000a
-; GCN-NEXT: v_writelane_b32 v6, s9, 27
-; GCN-NEXT: s_bfe_u32 s9, s0, 0x5000b
-; GCN-NEXT: v_writelane_b32 v6, s9, 28
-; GCN-NEXT: s_bfe_u32 s9, s0, 0x4000c
-; GCN-NEXT: v_writelane_b32 v6, s9, 29
-; GCN-NEXT: s_bfe_u32 s9, s0, 0x3000d
-; GCN-NEXT: v_writelane_b32 v6, s9, 30
-; GCN-NEXT: s_bfe_u32 s9, s0, 0x2000e
-; GCN-NEXT: v_writelane_b32 v6, s9, 31
-; GCN-NEXT: s_bfe_u32 s9, s0, 0x1000f
-; GCN-NEXT: v_writelane_b32 v6, s9, 32
-; GCN-NEXT: s_bfe_u32 s9, s1, 0xf0001
-; GCN-NEXT: s_lshr_b32 s43, s1, 17
+; GCN-NEXT: s_bfe_u32 s7, s0, 0xe0002
+; GCN-NEXT: v_writelane_b32 v6, s7, 18
+; GCN-NEXT: s_bfe_u32 s7, s0, 0xd0003
+; GCN-NEXT: v_writelane_b32 v6, s7, 19
+; GCN-NEXT: s_bfe_u32 s7, s0, 0xc0004
+; GCN-NEXT: v_writelane_b32 v6, s7, 20
+; GCN-NEXT: s_bfe_u32 s7, s0, 0xb0005
+; GCN-NEXT: v_writelane_b32 v6, s7, 21
+; GCN-NEXT: s_bfe_u32 s7, s0, 0xa0006
+; GCN-NEXT: v_writelane_b32 v6, s7, 22
+; GCN-NEXT: s_bfe_u32 s7, s0, 0x90007
+; GCN-NEXT: v_writelane_b32 v6, s7, 23
+; GCN-NEXT: s_bfe_u32 s7, s0, 0x80008
+; GCN-NEXT: v_writelane_b32 v6, s7, 24
+; GCN-NEXT: s_bfe_u32 s7, s0, 0x70009
+; GCN-NEXT: v_writelane_b32 v6, s7, 25
+; GCN-NEXT: s_bfe_u32 s7, s0, 0x6000a
+; GCN-NEXT: v_writelane_b32 v6, s7, 26
+; GCN-NEXT: s_bfe_u32 s7, s0, 0x5000b
+; GCN-NEXT: v_writelane_b32 v6, s7, 27
+; GCN-NEXT: s_bfe_u32 s7, s0, 0x4000c
+; GCN-NEXT: v_writelane_b32 v6, s7, 28
+; GCN-NEXT: s_bfe_u32 s7, s0, 0x3000d
+; GCN-NEXT: v_writelane_b32 v6, s7, 29
+; GCN-NEXT: s_bfe_u32 s7, s0, 0x2000e
+; GCN-NEXT: v_writelane_b32 v6, s7, 30
+; GCN-NEXT: s_bfe_u32 s7, s0, 0x1000f
+; GCN-NEXT: v_writelane_b32 v6, s7, 31
+; GCN-NEXT: s_bfe_u32 s7, s1, 0xe0002
+; GCN-NEXT: v_writelane_b32 v6, s7, 32
+; GCN-NEXT: s_bfe_u32 s7, s1, 0xd0003
; GCN-NEXT: s_lshr_b32 s45, s1, 18
; GCN-NEXT: s_lshr_b32 s47, s1, 19
; GCN-NEXT: s_lshr_b32 s50, s1, 20
@@ -3281,28 +3281,28 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_lshr_b32 s93, s2, 26
; GCN-NEXT: s_lshr_b32 s94, s2, 27
; GCN-NEXT: s_lshr_b32 vcc_hi, s2, 28
-; GCN-NEXT: s_lshr_b32 s39, s2, 29
+; GCN-NEXT: s_lshr_b32 s40, s2, 29
; GCN-NEXT: s_lshr_b32 s38, s2, 30
; GCN-NEXT: s_lshr_b32 s37, s2, 31
-; GCN-NEXT: s_lshr_b32 s33, s3, 16
-; GCN-NEXT: s_lshr_b32 s31, s3, 17
-; GCN-NEXT: s_lshr_b32 s28, s3, 18
-; GCN-NEXT: s_lshr_b32 s27, s3, 19
-; GCN-NEXT: s_lshr_b32 s24, s3, 20
-; GCN-NEXT: s_lshr_b32 s23, s3, 21
-; GCN-NEXT: s_lshr_b32 s20, s3, 22
-; GCN-NEXT: s_lshr_b32 s19, s3, 23
-; GCN-NEXT: s_lshr_b32 s16, s3, 24
-; GCN-NEXT: s_lshr_b32 s15, s3, 25
-; GCN-NEXT: s_lshr_b32 s12, s3, 26
-; GCN-NEXT: s_lshr_b32 s11, s3, 27
-; GCN-NEXT: s_lshr_b32 s8, s3, 28
-; GCN-NEXT: s_lshr_b32 s7, s3, 29
+; GCN-NEXT: s_lshr_b32 s34, s3, 16
+; GCN-NEXT: s_lshr_b32 s33, s3, 17
+; GCN-NEXT: s_lshr_b32 s29, s3, 18
+; GCN-NEXT: s_lshr_b32 s28, s3, 19
+; GCN-NEXT: s_lshr_b32 s25, s3, 20
+; GCN-NEXT: s_lshr_b32 s24, s3, 21
+; GCN-NEXT: s_lshr_b32 s21, s3, 22
+; GCN-NEXT: s_lshr_b32 s20, s3, 23
+; GCN-NEXT: s_lshr_b32 s17, s3, 24
+; GCN-NEXT: s_lshr_b32 s16, s3, 25
+; GCN-NEXT: s_lshr_b32 s13, s3, 26
+; GCN-NEXT: s_lshr_b32 s12, s3, 27
+; GCN-NEXT: s_lshr_b32 s9, s3, 28
+; GCN-NEXT: s_lshr_b32 s8, s3, 29
; GCN-NEXT: s_lshr_b32 s5, s3, 30
; GCN-NEXT: s_lshr_b32 s4, s3, 31
-; GCN-NEXT: v_writelane_b32 v6, s9, 33
-; GCN-NEXT: s_bfe_u32 s40, s1, 0xe0002
-; GCN-NEXT: s_bfe_u32 s41, s1, 0xd0003
+; GCN-NEXT: s_bfe_u32 s41, s0, 0xf0001
+; GCN-NEXT: s_bfe_u32 s39, s1, 0xf0001
+; GCN-NEXT: v_writelane_b32 v6, s7, 33
; GCN-NEXT: s_bfe_u32 s44, s1, 0xc0004
; GCN-NEXT: s_bfe_u32 s46, s1, 0xb0005
; GCN-NEXT: s_bfe_u32 s48, s1, 0xa0006
@@ -3330,21 +3330,21 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_bfe_u32 s92, s2, 0x3000d
; GCN-NEXT: s_bfe_u32 s95, s2, 0x2000e
; GCN-NEXT: s_bfe_u32 vcc_lo, s2, 0x1000f
-; GCN-NEXT: s_bfe_u32 s36, s3, 0xf0001
-; GCN-NEXT: s_bfe_u32 s35, s3, 0xe0002
-; GCN-NEXT: s_bfe_u32 s34, s3, 0xd0003
-; GCN-NEXT: s_bfe_u32 s30, s3, 0xc0004
-; GCN-NEXT: s_bfe_u32 s29, s3, 0xb0005
-; GCN-NEXT: s_bfe_u32 s26, s3, 0xa0006
-; GCN-NEXT: s_bfe_u32 s25, s3, 0x90007
-; GCN-NEXT: s_bfe_u32 s22, s3, 0x80008
-; GCN-NEXT: s_bfe_u32 s21, s3, 0x70009
-; GCN-NEXT: s_bfe_u32 s18, s3, 0x6000a
-; GCN-NEXT: s_bfe_u32 s17, s3, 0x5000b
-; GCN-NEXT: s_bfe_u32 s14, s3, 0x4000c
-; GCN-NEXT: s_bfe_u32 s13, s3, 0x3000d
-; GCN-NEXT: s_bfe_u32 s10, s3, 0x2000e
-; GCN-NEXT: s_bfe_u32 s9, s3, 0x1000f
+; GCN-NEXT: s_bfe_u32 s7, s3, 0xf0001
+; GCN-NEXT: s_bfe_u32 s36, s3, 0xe0002
+; GCN-NEXT: s_bfe_u32 s35, s3, 0xd0003
+; GCN-NEXT: s_bfe_u32 s31, s3, 0xc0004
+; GCN-NEXT: s_bfe_u32 s30, s3, 0xb0005
+; GCN-NEXT: s_bfe_u32 s27, s3, 0xa0006
+; GCN-NEXT: s_bfe_u32 s26, s3, 0x90007
+; GCN-NEXT: s_bfe_u32 s23, s3, 0x80008
+; GCN-NEXT: s_bfe_u32 s22, s3, 0x70009
+; GCN-NEXT: s_bfe_u32 s19, s3, 0x6000a
+; GCN-NEXT: s_bfe_u32 s18, s3, 0x5000b
+; GCN-NEXT: s_bfe_u32 s15, s3, 0x4000c
+; GCN-NEXT: s_bfe_u32 s14, s3, 0x3000d
+; GCN-NEXT: s_bfe_u32 s11, s3, 0x2000e
+; GCN-NEXT: s_bfe_u32 s10, s3, 0x1000f
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x7f
; GCN-NEXT: s_cselect_b32 s4, s4, 1
; GCN-NEXT: s_lshl_b32 s4, s4, 3
@@ -3354,150 +3354,150 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_lshl_b32 s5, s5, 2
; GCN-NEXT: s_or_b32 s4, s4, s5
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x7d
-; GCN-NEXT: s_cselect_b32 s5, s7, 1
+; GCN-NEXT: s_cselect_b32 s5, s8, 1
; GCN-NEXT: s_lshl_b32 s5, s5, 1
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x7c
-; GCN-NEXT: s_cselect_b32 s7, s8, 1
-; GCN-NEXT: s_and_b32 s7, s7, 1
-; GCN-NEXT: s_or_b32 s5, s7, s5
+; GCN-NEXT: s_cselect_b32 s8, s9, 1
+; GCN-NEXT: s_and_b32 s8, s8, 1
+; GCN-NEXT: s_or_b32 s5, s8, s5
; GCN-NEXT: s_and_b32 s5, s5, 3
; GCN-NEXT: s_or_b32 s4, s5, s4
; GCN-NEXT: s_lshl_b32 s4, s4, 12
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x7b
-; GCN-NEXT: s_cselect_b32 s5, s11, 1
+; GCN-NEXT: s_cselect_b32 s5, s12, 1
; GCN-NEXT: s_lshl_b32 s5, s5, 3
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x7a
-; GCN-NEXT: s_cselect_b32 s7, s12, 1
-; GCN-NEXT: s_and_b32 s7, s7, 1
-; GCN-NEXT: s_lshl_b32 s7, s7, 2
-; GCN-NEXT: s_or_b32 s5, s5, s7
+; GCN-NEXT: s_cselect_b32 s8, s13, 1
+; GCN-NEXT: s_and_b32 s8, s8, 1
+; GCN-NEXT: s_lshl_b32 s8, s8, 2
+; GCN-NEXT: s_or_b32 s5, s5, s8
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x79
-; GCN-NEXT: s_cselect_b32 s7, s15, 1
-; GCN-NEXT: s_lshl_b32 s7, s7, 1
-; GCN-NEXT: s_cmpk_lg_i32 s6, 0x78
; GCN-NEXT: s_cselect_b32 s8, s16, 1
-; GCN-NEXT: s_and_b32 s8, s8, 1
-; GCN-NEXT: s_or_b32 s7, s8, s7
-; GCN-NEXT: s_and_b32 s7, s7, 3
-; GCN-NEXT: s_or_b32 s5, s7, s5
+; GCN-NEXT: s_lshl_b32 s8, s8, 1
+; GCN-NEXT: s_cmpk_lg_i32 s6, 0x78
+; GCN-NEXT: s_cselect_b32 s9, s17, 1
+; GCN-NEXT: s_and_b32 s9, s9, 1
+; GCN-NEXT: s_or_b32 s8, s9, s8
+; GCN-NEXT: s_and_b32 s8, s8, 3
+; GCN-NEXT: s_or_b32 s5, s8, s5
; GCN-NEXT: s_and_b32 s5, s5, 15
; GCN-NEXT: s_lshl_b32 s5, s5, 8
; GCN-NEXT: s_or_b32 s4, s4, s5
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x77
-; GCN-NEXT: s_cselect_b32 s5, s19, 1
+; GCN-NEXT: s_cselect_b32 s5, s20, 1
; GCN-NEXT: s_lshl_b32 s5, s5, 3
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x76
-; GCN-NEXT: s_cselect_b32 s7, s20, 1
-; GCN-NEXT: s_and_b32 s7, s7, 1
-; GCN-NEXT: s_lshl_b32 s7, s7, 2
-; GCN-NEXT: s_or_b32 s5, s5, s7
+; GCN-NEXT: s_cselect_b32 s8, s21, 1
+; GCN-NEXT: s_and_b32 s8, s8, 1
+; GCN-NEXT: s_lshl_b32 s8, s8, 2
+; GCN-NEXT: s_or_b32 s5, s5, s8
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x75
-; GCN-NEXT: s_cselect_b32 s7, s23, 1
-; GCN-NEXT: s_lshl_b32 s7, s7, 1
-; GCN-NEXT: s_cmpk_lg_i32 s6, 0x74
; GCN-NEXT: s_cselect_b32 s8, s24, 1
-; GCN-NEXT: s_and_b32 s8, s8, 1
-; GCN-NEXT: s_or_b32 s7, s8, s7
-; GCN-NEXT: s_and_b32 s7, s7, 3
-; GCN-NEXT: s_or_b32 s5, s7, s5
+; GCN-NEXT: s_lshl_b32 s8, s8, 1
+; GCN-NEXT: s_cmpk_lg_i32 s6, 0x74
+; GCN-NEXT: s_cselect_b32 s9, s25, 1
+; GCN-NEXT: s_and_b32 s9, s9, 1
+; GCN-NEXT: s_or_b32 s8, s9, s8
+; GCN-NEXT: s_and_b32 s8, s8, 3
+; GCN-NEXT: s_or_b32 s5, s8, s5
; GCN-NEXT: s_lshl_b32 s5, s5, 4
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x73
-; GCN-NEXT: s_cselect_b32 s7, s27, 1
-; GCN-NEXT: s_lshl_b32 s7, s7, 3
-; GCN-NEXT: s_cmpk_lg_i32 s6, 0x72
; GCN-NEXT: s_cselect_b32 s8, s28, 1
-; GCN-NEXT: s_and_b32 s8, s8, 1
-; GCN-NEXT: s_lshl_b32 s8, s8, 2
-; GCN-NEXT: s_or_b32 s7, s7, s8
+; GCN-NEXT: s_lshl_b32 s8, s8, 3
+; GCN-NEXT: s_cmpk_lg_i32 s6, 0x72
+; GCN-NEXT: s_cselect_b32 s9, s29, 1
+; GCN-NEXT: s_and_b32 s9, s9, 1
+; GCN-NEXT: s_lshl_b32 s9, s9, 2
+; GCN-NEXT: s_or_b32 s8, s8, s9
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x71
-; GCN-NEXT: s_cselect_b32 s8, s31, 1
-; GCN-NEXT: s_lshl_b32 s8, s8, 1
+; GCN-NEXT: s_cselect_b32 s9, s33, 1
+; GCN-NEXT: s_lshl_b32 s9, s9, 1
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x70
-; GCN-NEXT: s_cselect_b32 s11, s33, 1
-; GCN-NEXT: s_and_b32 s11, s11, 1
-; GCN-NEXT: s_or_b32 s8, s11, s8
-; GCN-NEXT: s_and_b32 s8, s8, 3
-; GCN-NEXT: s_or_b32 s7, s8, s7
-; GCN-NEXT: s_and_b32 s7, s7, 15
-; GCN-NEXT: s_or_b32 s5, s7, s5
+; GCN-NEXT: s_cselect_b32 s12, s34, 1
+; GCN-NEXT: s_and_b32 s12, s12, 1
+; GCN-NEXT: s_or_b32 s9, s12, s9
+; GCN-NEXT: s_and_b32 s9, s9, 3
+; GCN-NEXT: s_or_b32 s8, s9, s8
+; GCN-NEXT: s_and_b32 s8, s8, 15
+; GCN-NEXT: s_or_b32 s5, s8, s5
; GCN-NEXT: s_and_b32 s5, s5, 0xff
; GCN-NEXT: s_or_b32 s4, s5, s4
; GCN-NEXT: s_lshl_b32 s4, s4, 16
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x6f
-; GCN-NEXT: s_cselect_b32 s5, s9, 1
+; GCN-NEXT: s_cselect_b32 s5, s10, 1
; GCN-NEXT: s_lshl_b32 s5, s5, 3
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x6e
-; GCN-NEXT: s_cselect_b32 s7, s10, 1
-; GCN-NEXT: s_and_b32 s7, s7, 1
-; GCN-NEXT: s_lshl_b32 s7, s7, 2
-; GCN-NEXT: s_or_b32 s5, s5, s7
+; GCN-NEXT: s_cselect_b32 s8, s11, 1
+; GCN-NEXT: s_and_b32 s8, s8, 1
+; GCN-NEXT: s_lshl_b32 s8, s8, 2
+; GCN-NEXT: s_or_b32 s5, s5, s8
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x6d
-; GCN-NEXT: s_cselect_b32 s7, s13, 1
-; GCN-NEXT: s_lshl_b32 s7, s7, 1
-; GCN-NEXT: s_cmpk_lg_i32 s6, 0x6c
; GCN-NEXT: s_cselect_b32 s8, s14, 1
-; GCN-NEXT: s_and_b32 s8, s8, 1
-; GCN-NEXT: s_or_b32 s7, s8, s7
-; GCN-NEXT: s_and_b32 s7, s7, 3
-; GCN-NEXT: s_or_b32 s5, s7, s5
+; GCN-NEXT: s_lshl_b32 s8, s8, 1
+; GCN-NEXT: s_cmpk_lg_i32 s6, 0x6c
+; GCN-NEXT: s_cselect_b32 s9, s15, 1
+; GCN-NEXT: s_and_b32 s9, s9, 1
+; GCN-NEXT: s_or_b32 s8, s9, s8
+; GCN-NEXT: s_and_b32 s8, s8, 3
+; GCN-NEXT: s_or_b32 s5, s8, s5
; GCN-NEXT: s_lshl_b32 s5, s5, 12
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x6b
-; GCN-NEXT: s_cselect_b32 s7, s17, 1
-; GCN-NEXT: s_lshl_b32 s7, s7, 3
-; GCN-NEXT: s_cmpk_lg_i32 s6, 0x6a
; GCN-NEXT: s_cselect_b32 s8, s18, 1
-; GCN-NEXT: s_and_b32 s8, s8, 1
-; GCN-NEXT: s_lshl_b32 s8, s8, 2
-; GCN-NEXT: s_or_b32 s7, s7, s8
+; GCN-NEXT: s_lshl_b32 s8, s8, 3
+; GCN-NEXT: s_cmpk_lg_i32 s6, 0x6a
+; GCN-NEXT: s_cselect_b32 s9, s19, 1
+; GCN-NEXT: s_and_b32 s9, s9, 1
+; GCN-NEXT: s_lshl_b32 s9, s9, 2
+; GCN-NEXT: s_or_b32 s8, s8, s9
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x69
-; GCN-NEXT: s_cselect_b32 s8, s21, 1
-; GCN-NEXT: s_lshl_b32 s8, s8, 1
-; GCN-NEXT: s_cmpk_lg_i32 s6, 0x68
; GCN-NEXT: s_cselect_b32 s9, s22, 1
-; GCN-NEXT: s_and_b32 s9, s9, 1
+; GCN-NEXT: s_lshl_b32 s9, s9, 1
+; GCN-NEXT: s_cmpk_lg_i32 s6, 0x68
+; GCN-NEXT: s_cselect_b32 s10, s23, 1
+; GCN-NEXT: s_and_b32 s10, s10, 1
+; GCN-NEXT: s_or_b32 s9, s10, s9
+; GCN-NEXT: s_and_b32 s9, s9, 3
; GCN-NEXT: s_or_b32 s8, s9, s8
-; GCN-NEXT: s_and_b32 s8, s8, 3
-; GCN-NEXT: s_or_b32 s7, s8, s7
-; GCN-NEXT: s_and_b32 s7, s7, 15
-; GCN-NEXT: s_lshl_b32 s7, s7, 8
-; GCN-NEXT: s_or_b32 s5, s5, s7
+; GCN-NEXT: s_and_b32 s8, s8, 15
+; GCN-NEXT: s_lshl_b32 s8, s8, 8
+; GCN-NEXT: s_or_b32 s5, s5, s8
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x67
-; GCN-NEXT: s_cselect_b32 s7, s25, 1
-; GCN-NEXT: s_lshl_b32 s7, s7, 3
-; GCN-NEXT: s_cmpk_lg_i32 s6, 0x66
; GCN-NEXT: s_cselect_b32 s8, s26, 1
-; GCN-NEXT: s_and_b32 s8, s8, 1
-; GCN-NEXT: s_lshl_b32 s8, s8, 2
-; GCN-NEXT: s_or_b32 s7, s7, s8
+; GCN-NEXT: s_lshl_b32 s8, s8, 3
+; GCN-NEXT: s_cmpk_lg_i32 s6, 0x66
+; GCN-NEXT: s_cselect_b32 s9, s27, 1
+; GCN-NEXT: s_and_b32 s9, s9, 1
+; GCN-NEXT: s_lshl_b32 s9, s9, 2
+; GCN-NEXT: s_or_b32 s8, s8, s9
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x65
-; GCN-NEXT: s_cselect_b32 s8, s29, 1
-; GCN-NEXT: s_lshl_b32 s8, s8, 1
-; GCN-NEXT: s_cmpk_lg_i32 s6, 0x64
; GCN-NEXT: s_cselect_b32 s9, s30, 1
-; GCN-NEXT: s_and_b32 s9, s9, 1
+; GCN-NEXT: s_lshl_b32 s9, s9, 1
+; GCN-NEXT: s_cmpk_lg_i32 s6, 0x64
+; GCN-NEXT: s_cselect_b32 s10, s31, 1
+; GCN-NEXT: s_and_b32 s10, s10, 1
+; GCN-NEXT: s_or_b32 s9, s10, s9
+; GCN-NEXT: s_and_b32 s9, s9, 3
; GCN-NEXT: s_or_b32 s8, s9, s8
-; GCN-NEXT: s_and_b32 s8, s8, 3
-; GCN-NEXT: s_or_b32 s7, s8, s7
-; GCN-NEXT: s_lshl_b32 s7, s7, 4
+; GCN-NEXT: s_lshl_b32 s8, s8, 4
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x63
-; GCN-NEXT: s_cselect_b32 s8, s34, 1
-; GCN-NEXT: s_lshl_b32 s8, s8, 3
-; GCN-NEXT: s_cmpk_lg_i32 s6, 0x62
; GCN-NEXT: s_cselect_b32 s9, s35, 1
-; GCN-NEXT: s_and_b32 s9, s9, 1
-; GCN-NEXT: s_lshl_b32 s9, s9, 2
-; GCN-NEXT: s_or_b32 s8, s8, s9
+; GCN-NEXT: s_lshl_b32 s9, s9, 3
+; GCN-NEXT: s_cmpk_lg_i32 s6, 0x62
+; GCN-NEXT: s_cselect_b32 s10, s36, 1
+; GCN-NEXT: s_and_b32 s10, s10, 1
+; GCN-NEXT: s_lshl_b32 s10, s10, 2
+; GCN-NEXT: s_or_b32 s9, s9, s10
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x60
; GCN-NEXT: s_cselect_b32 s3, s3, 1
; GCN-NEXT: s_and_b32 s3, s3, 1
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x61
-; GCN-NEXT: s_cselect_b32 s9, s36, 1
-; GCN-NEXT: s_lshl_b32 s9, s9, 1
-; GCN-NEXT: s_or_b32 s3, s3, s9
+; GCN-NEXT: s_cselect_b32 s7, s7, 1
+; GCN-NEXT: s_lshl_b32 s7, s7, 1
+; GCN-NEXT: s_or_b32 s3, s3, s7
; GCN-NEXT: s_and_b32 s3, s3, 3
-; GCN-NEXT: s_or_b32 s3, s3, s8
+; GCN-NEXT: s_or_b32 s3, s3, s9
; GCN-NEXT: s_and_b32 s3, s3, 15
-; GCN-NEXT: s_or_b32 s3, s3, s7
+; GCN-NEXT: s_or_b32 s3, s3, s8
; GCN-NEXT: s_and_b32 s3, s3, 0xff
; GCN-NEXT: s_or_b32 s3, s3, s5
; GCN-NEXT: s_and_b32 s3, s3, 0xffff
@@ -3511,7 +3511,7 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_lshl_b32 s5, s5, 2
; GCN-NEXT: s_or_b32 s4, s4, s5
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x5d
-; GCN-NEXT: s_cselect_b32 s5, s39, 1
+; GCN-NEXT: s_cselect_b32 s5, s40, 1
; GCN-NEXT: s_lshl_b32 s5, s5, 1
; GCN-NEXT: s_cmpk_lg_i32 s6, 0x5c
; GCN-NEXT: s_cselect_b32 s7, vcc_hi, 1
@@ -3724,10 +3724,12 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_lshl_b32 s8, s8, 2
; GCN-NEXT: s_or_b32 s7, s7, s8
; GCN-NEXT: s_cmp_lg_u32 s6, 49
-; GCN-NEXT: s_cselect_b32 s8, s43, 1
+; GCN-NEXT: v_readlane_b32 s8, v6, 17
+; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_lshl_b32 s8, s8, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 48
-; GCN-NEXT: s_cselect_b32 s9, s42, 1
+; GCN-NEXT: v_readlane_b32 s9, v6, 16
+; GCN-NEXT: s_cselect_b32 s9, s9, 1
; GCN-NEXT: s_and_b32 s9, s9, 1
; GCN-NEXT: s_or_b32 s8, s9, s8
; GCN-NEXT: s_and_b32 s8, s8, 3
@@ -3794,10 +3796,12 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_or_b32 s7, s8, s7
; GCN-NEXT: s_lshl_b32 s7, s7, 4
; GCN-NEXT: s_cmp_lg_u32 s6, 35
-; GCN-NEXT: s_cselect_b32 s8, s41, 1
+; GCN-NEXT: v_readlane_b32 s8, v6, 33
+; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_lshl_b32 s8, s8, 3
; GCN-NEXT: s_cmp_lg_u32 s6, 34
-; GCN-NEXT: s_cselect_b32 s9, s40, 1
+; GCN-NEXT: v_readlane_b32 s9, v6, 32
+; GCN-NEXT: s_cselect_b32 s9, s9, 1
; GCN-NEXT: s_and_b32 s9, s9, 1
; GCN-NEXT: s_lshl_b32 s9, s9, 2
; GCN-NEXT: s_or_b32 s8, s8, s9
@@ -3805,8 +3809,7 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_cselect_b32 s1, s1, 1
; GCN-NEXT: s_and_b32 s1, s1, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 33
-; GCN-NEXT: v_readlane_b32 s9, v6, 33
-; GCN-NEXT: s_cselect_b32 s9, s9, 1
+; GCN-NEXT: s_cselect_b32 s9, s39, 1
; GCN-NEXT: s_lshl_b32 s9, s9, 1
; GCN-NEXT: s_or_b32 s1, s1, s9
; GCN-NEXT: s_and_b32 s1, s1, 3
@@ -3818,21 +3821,21 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_and_b32 s1, s1, 0xffff
; GCN-NEXT: s_or_b32 s1, s1, s4
; GCN-NEXT: s_cmp_lg_u32 s6, 31
-; GCN-NEXT: v_readlane_b32 s4, v6, 17
+; GCN-NEXT: v_readlane_b32 s4, v6, 15
; GCN-NEXT: s_cselect_b32 s4, s4, 1
; GCN-NEXT: s_lshl_b32 s4, s4, 3
; GCN-NEXT: s_cmp_lg_u32 s6, 30
-; GCN-NEXT: v_readlane_b32 s5, v6, 16
+; GCN-NEXT: v_readlane_b32 s5, v6, 14
; GCN-NEXT: s_cselect_b32 s5, s5, 1
; GCN-NEXT: s_and_b32 s5, s5, 1
; GCN-NEXT: s_lshl_b32 s5, s5, 2
; GCN-NEXT: s_or_b32 s4, s4, s5
; GCN-NEXT: s_cmp_lg_u32 s6, 29
-; GCN-NEXT: v_readlane_b32 s5, v6, 15
+; GCN-NEXT: v_readlane_b32 s5, v6, 13
; GCN-NEXT: s_cselect_b32 s5, s5, 1
; GCN-NEXT: s_lshl_b32 s5, s5, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 28
-; GCN-NEXT: v_readlane_b32 s7, v6, 14
+; GCN-NEXT: v_readlane_b32 s7, v6, 12
; GCN-NEXT: s_cselect_b32 s7, s7, 1
; GCN-NEXT: s_and_b32 s7, s7, 1
; GCN-NEXT: s_or_b32 s5, s7, s5
@@ -3840,21 +3843,21 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_or_b32 s4, s5, s4
; GCN-NEXT: s_lshl_b32 s4, s4, 12
; GCN-NEXT: s_cmp_lg_u32 s6, 27
-; GCN-NEXT: v_readlane_b32 s5, v6, 13
+; GCN-NEXT: v_readlane_b32 s5, v6, 11
; GCN-NEXT: s_cselect_b32 s5, s5, 1
; GCN-NEXT: s_lshl_b32 s5, s5, 3
; GCN-NEXT: s_cmp_lg_u32 s6, 26
-; GCN-NEXT: v_readlane_b32 s7, v6, 12
+; GCN-NEXT: v_readlane_b32 s7, v6, 10
; GCN-NEXT: s_cselect_b32 s7, s7, 1
; GCN-NEXT: s_and_b32 s7, s7, 1
; GCN-NEXT: s_lshl_b32 s7, s7, 2
; GCN-NEXT: s_or_b32 s5, s5, s7
; GCN-NEXT: s_cmp_lg_u32 s6, 25
-; GCN-NEXT: v_readlane_b32 s7, v6, 11
+; GCN-NEXT: v_readlane_b32 s7, v6, 9
; GCN-NEXT: s_cselect_b32 s7, s7, 1
; GCN-NEXT: s_lshl_b32 s7, s7, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 24
-; GCN-NEXT: v_readlane_b32 s8, v6, 10
+; GCN-NEXT: v_readlane_b32 s8, v6, 8
; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_and_b32 s8, s8, 1
; GCN-NEXT: s_or_b32 s7, s8, s7
@@ -3864,21 +3867,21 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_lshl_b32 s5, s5, 8
; GCN-NEXT: s_or_b32 s4, s4, s5
; GCN-NEXT: s_cmp_lg_u32 s6, 23
-; GCN-NEXT: v_readlane_b32 s5, v6, 9
+; GCN-NEXT: v_readlane_b32 s5, v6, 7
; GCN-NEXT: s_cselect_b32 s5, s5, 1
; GCN-NEXT: s_lshl_b32 s5, s5, 3
; GCN-NEXT: s_cmp_lg_u32 s6, 22
-; GCN-NEXT: v_readlane_b32 s7, v6, 8
+; GCN-NEXT: v_readlane_b32 s7, v6, 6
; GCN-NEXT: s_cselect_b32 s7, s7, 1
; GCN-NEXT: s_and_b32 s7, s7, 1
; GCN-NEXT: s_lshl_b32 s7, s7, 2
; GCN-NEXT: s_or_b32 s5, s5, s7
; GCN-NEXT: s_cmp_lg_u32 s6, 21
-; GCN-NEXT: v_readlane_b32 s7, v6, 7
+; GCN-NEXT: v_readlane_b32 s7, v6, 5
; GCN-NEXT: s_cselect_b32 s7, s7, 1
; GCN-NEXT: s_lshl_b32 s7, s7, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 20
-; GCN-NEXT: v_readlane_b32 s8, v6, 6
+; GCN-NEXT: v_readlane_b32 s8, v6, 4
; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_and_b32 s8, s8, 1
; GCN-NEXT: s_or_b32 s7, s8, s7
@@ -3886,21 +3889,21 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_or_b32 s5, s7, s5
; GCN-NEXT: s_lshl_b32 s5, s5, 4
; GCN-NEXT: s_cmp_lg_u32 s6, 19
-; GCN-NEXT: v_readlane_b32 s7, v6, 5
+; GCN-NEXT: v_readlane_b32 s7, v6, 3
; GCN-NEXT: s_cselect_b32 s7, s7, 1
; GCN-NEXT: s_lshl_b32 s7, s7, 3
; GCN-NEXT: s_cmp_lg_u32 s6, 18
-; GCN-NEXT: v_readlane_b32 s8, v6, 4
+; GCN-NEXT: v_readlane_b32 s8, v6, 2
; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_and_b32 s8, s8, 1
; GCN-NEXT: s_lshl_b32 s8, s8, 2
; GCN-NEXT: s_or_b32 s7, s7, s8
; GCN-NEXT: s_cmp_lg_u32 s6, 17
-; GCN-NEXT: v_readlane_b32 s8, v6, 3
+; GCN-NEXT: v_readlane_b32 s8, v6, 1
; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_lshl_b32 s8, s8, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 16
-; GCN-NEXT: v_readlane_b32 s9, v6, 2
+; GCN-NEXT: v_readlane_b32 s9, v6, 0
; GCN-NEXT: s_cselect_b32 s9, s9, 1
; GCN-NEXT: s_and_b32 s9, s9, 1
; GCN-NEXT: s_or_b32 s8, s9, s8
@@ -3912,21 +3915,21 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_or_b32 s4, s5, s4
; GCN-NEXT: s_lshl_b32 s4, s4, 16
; GCN-NEXT: s_cmp_lg_u32 s6, 15
-; GCN-NEXT: v_readlane_b32 s5, v6, 32
+; GCN-NEXT: v_readlane_b32 s5, v6, 31
; GCN-NEXT: s_cselect_b32 s5, s5, 1
; GCN-NEXT: s_lshl_b32 s5, s5, 3
; GCN-NEXT: s_cmp_lg_u32 s6, 14
-; GCN-NEXT: v_readlane_b32 s7, v6, 31
+; GCN-NEXT: v_readlane_b32 s7, v6, 30
; GCN-NEXT: s_cselect_b32 s7, s7, 1
; GCN-NEXT: s_and_b32 s7, s7, 1
; GCN-NEXT: s_lshl_b32 s7, s7, 2
; GCN-NEXT: s_or_b32 s5, s5, s7
; GCN-NEXT: s_cmp_lg_u32 s6, 13
-; GCN-NEXT: v_readlane_b32 s7, v6, 30
+; GCN-NEXT: v_readlane_b32 s7, v6, 29
; GCN-NEXT: s_cselect_b32 s7, s7, 1
; GCN-NEXT: s_lshl_b32 s7, s7, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 12
-; GCN-NEXT: v_readlane_b32 s8, v6, 29
+; GCN-NEXT: v_readlane_b32 s8, v6, 28
; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_and_b32 s8, s8, 1
; GCN-NEXT: s_or_b32 s7, s8, s7
@@ -3934,21 +3937,21 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_or_b32 s5, s7, s5
; GCN-NEXT: s_lshl_b32 s5, s5, 12
; GCN-NEXT: s_cmp_lg_u32 s6, 11
-; GCN-NEXT: v_readlane_b32 s7, v6, 28
+; GCN-NEXT: v_readlane_b32 s7, v6, 27
; GCN-NEXT: s_cselect_b32 s7, s7, 1
; GCN-NEXT: s_lshl_b32 s7, s7, 3
; GCN-NEXT: s_cmp_lg_u32 s6, 10
-; GCN-NEXT: v_readlane_b32 s8, v6, 27
+; GCN-NEXT: v_readlane_b32 s8, v6, 26
; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_and_b32 s8, s8, 1
; GCN-NEXT: s_lshl_b32 s8, s8, 2
; GCN-NEXT: s_or_b32 s7, s7, s8
; GCN-NEXT: s_cmp_lg_u32 s6, 9
-; GCN-NEXT: v_readlane_b32 s8, v6, 26
+; GCN-NEXT: v_readlane_b32 s8, v6, 25
; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_lshl_b32 s8, s8, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 8
-; GCN-NEXT: v_readlane_b32 s9, v6, 25
+; GCN-NEXT: v_readlane_b32 s9, v6, 24
; GCN-NEXT: s_cselect_b32 s9, s9, 1
; GCN-NEXT: s_and_b32 s9, s9, 1
; GCN-NEXT: s_or_b32 s8, s9, s8
@@ -3958,21 +3961,21 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_lshl_b32 s7, s7, 8
; GCN-NEXT: s_or_b32 s5, s5, s7
; GCN-NEXT: s_cmp_lg_u32 s6, 7
-; GCN-NEXT: v_readlane_b32 s7, v6, 24
+; GCN-NEXT: v_readlane_b32 s7, v6, 23
; GCN-NEXT: s_cselect_b32 s7, s7, 1
; GCN-NEXT: s_lshl_b32 s7, s7, 3
; GCN-NEXT: s_cmp_lg_u32 s6, 6
-; GCN-NEXT: v_readlane_b32 s8, v6, 23
+; GCN-NEXT: v_readlane_b32 s8, v6, 22
; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_and_b32 s8, s8, 1
; GCN-NEXT: s_lshl_b32 s8, s8, 2
; GCN-NEXT: s_or_b32 s7, s7, s8
; GCN-NEXT: s_cmp_lg_u32 s6, 5
-; GCN-NEXT: v_readlane_b32 s8, v6, 22
+; GCN-NEXT: v_readlane_b32 s8, v6, 21
; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_lshl_b32 s8, s8, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 4
-; GCN-NEXT: v_readlane_b32 s9, v6, 21
+; GCN-NEXT: v_readlane_b32 s9, v6, 20
; GCN-NEXT: s_cselect_b32 s9, s9, 1
; GCN-NEXT: s_and_b32 s9, s9, 1
; GCN-NEXT: s_or_b32 s8, s9, s8
@@ -3980,11 +3983,11 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_or_b32 s7, s8, s7
; GCN-NEXT: s_lshl_b32 s7, s7, 4
; GCN-NEXT: s_cmp_lg_u32 s6, 3
-; GCN-NEXT: v_readlane_b32 s8, v6, 20
+; GCN-NEXT: v_readlane_b32 s8, v6, 19
; GCN-NEXT: s_cselect_b32 s8, s8, 1
; GCN-NEXT: s_lshl_b32 s8, s8, 3
; GCN-NEXT: s_cmp_lg_u32 s6, 2
-; GCN-NEXT: v_readlane_b32 s9, v6, 19
+; GCN-NEXT: v_readlane_b32 s9, v6, 18
; GCN-NEXT: s_cselect_b32 s9, s9, 1
; GCN-NEXT: s_and_b32 s9, s9, 1
; GCN-NEXT: s_lshl_b32 s9, s9, 2
@@ -3993,8 +3996,7 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_cselect_b32 s0, s0, 1
; GCN-NEXT: s_and_b32 s0, s0, 1
; GCN-NEXT: s_cmp_lg_u32 s6, 1
-; GCN-NEXT: v_readlane_b32 s6, v6, 18
-; GCN-NEXT: s_cselect_b32 s6, s6, 1
+; GCN-NEXT: s_cselect_b32 s6, s41, 1
; GCN-NEXT: s_lshl_b32 s6, s6, 1
; GCN-NEXT: s_or_b32 s0, s0, s6
; GCN-NEXT: s_and_b32 s0, s0, 3
@@ -4005,14 +4007,12 @@ define amdgpu_kernel void @bit128_inselt(ptr addrspace(1) %out, <128 x i1> %vec,
; GCN-NEXT: s_or_b32 s0, s0, s5
; GCN-NEXT: s_and_b32 s0, s0, 0xffff
; GCN-NEXT: s_or_b32 s0, s0, s4
+; GCN-NEXT: v_mov_b32_e32 v4, s42
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: v_readlane_b32 s0, v6, 0
-; GCN-NEXT: v_readlane_b32 s1, v6, 1
-; GCN-NEXT: v_mov_b32_e32 v5, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
-; GCN-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NEXT: v_mov_b32_e32 v5, s43
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/issue176578.ll b/llvm/test/CodeGen/AMDGPU/issue176578.ll
index 08986d1f61efd..ce2918db9fc6b 100644
--- a/llvm/test/CodeGen/AMDGPU/issue176578.ll
+++ b/llvm/test/CodeGen/AMDGPU/issue176578.ll
@@ -17,7 +17,7 @@ define <4 x i8> @issue176578() #0 {
; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1
; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
-; CHECK-NEXT: v_writelane_b32 v41, s16, 15
+; CHECK-NEXT: v_writelane_b32 v41, s16, 17
; CHECK-NEXT: v_writelane_b32 v41, s30, 0
; CHECK-NEXT: v_writelane_b32 v41, s31, 1
; CHECK-NEXT: v_writelane_b32 v41, s34, 2
@@ -32,8 +32,11 @@ define <4 x i8> @issue176578() #0 {
; CHECK-NEXT: v_writelane_b32 v41, s51, 11
; CHECK-NEXT: v_writelane_b32 v41, s52, 12
; CHECK-NEXT: v_writelane_b32 v41, s53, 13
-; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: v_writelane_b32 v41, s54, 14
+; CHECK-NEXT: v_writelane_b32 v41, s55, 15
+; CHECK-NEXT: s_addk_i32 s32, 0x400
+; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
+; CHECK-NEXT: v_writelane_b32 v41, s64, 16
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: s_mov_b32 s50, s15
; CHECK-NEXT: s_mov_b32 s51, s14
@@ -43,8 +46,10 @@ define <4 x i8> @issue176578() #0 {
; CHECK-NEXT: s_mov_b64 s[36:37], s[8:9]
; CHECK-NEXT: s_mov_b64 s[38:39], s[6:7]
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
-; CHECK-NEXT: s_mov_b32 s54, 0
-; CHECK-NEXT: s_addk_i32 s32, 0x400
+; CHECK-NEXT: s_mov_b32 s64, 0
+; CHECK-NEXT: s_getpc_b64 s[54:55]
+; CHECK-NEXT: s_add_u32 s54, s54, func at rel32@lo+4
+; CHECK-NEXT: s_addc_u32 s55, s55, func at rel32@hi+12
; CHECK-NEXT: s_branch .LBB0_2
; CHECK-NEXT: .LBB0_1: ; %Flow
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
@@ -53,14 +58,11 @@ define <4 x i8> @issue176578() #0 {
; CHECK-NEXT: .LBB0_2: ; %bb1
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_and_b64 vcc, exec, -1
-; CHECK-NEXT: s_cselect_b32 s54, 0, s54
+; CHECK-NEXT: s_cselect_b32 s64, 0, s64
; CHECK-NEXT: s_mov_b64 s[4:5], -1
; CHECK-NEXT: s_cbranch_execnz .LBB0_1
; CHECK-NEXT: ; %bb.3: ; %bb3
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, func at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, func at rel32@hi+12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
; CHECK-NEXT: s_mov_b64 s[8:9], s[36:37]
@@ -76,15 +78,17 @@ define <4 x i8> @issue176578() #0 {
; CHECK-NEXT: v_mov_b32_e32 v3, 0
; CHECK-NEXT: v_mov_b32_e32 v4, 0
; CHECK-NEXT: v_mov_b32_e32 v5, 0
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[54:55]
; CHECK-NEXT: s_mov_b64 s[4:5], 0
; CHECK-NEXT: s_branch .LBB0_1
; CHECK-NEXT: .LBB0_4: ; %bb4
; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; CHECK-NEXT: v_mov_b32_e32 v0, s54
+; CHECK-NEXT: v_mov_b32_e32 v0, s64
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: v_mov_b32_e32 v2, 0
; CHECK-NEXT: v_mov_b32_e32 v3, 0
+; CHECK-NEXT: v_readlane_b32 s64, v41, 16
+; CHECK-NEXT: v_readlane_b32 s55, v41, 15
; CHECK-NEXT: v_readlane_b32 s54, v41, 14
; CHECK-NEXT: v_readlane_b32 s53, v41, 13
; CHECK-NEXT: v_readlane_b32 s52, v41, 12
@@ -101,7 +105,7 @@ define <4 x i8> @issue176578() #0 {
; CHECK-NEXT: v_readlane_b32 s31, v41, 1
; CHECK-NEXT: v_readlane_b32 s30, v41, 0
; CHECK-NEXT: s_mov_b32 s32, s33
-; CHECK-NEXT: v_readlane_b32 s4, v41, 15
+; CHECK-NEXT: v_readlane_b32 s4, v41, 17
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; CHECK-NEXT: s_mov_b64 exec, s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
index 66683d323837d..912208ef6f8e9 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
@@ -114,7 +114,7 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: v_mov_b32_e32 v1, 12
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_mov_b32_e32 v42, v0
-; CHECK-NEXT: s_mov_b32 s52, exec_lo
+; CHECK-NEXT: s_mov_b32 s54, exec_lo
; CHECK-NEXT: v_cmpx_ne_u32_e32 0, v42
; CHECK-NEXT: s_cbranch_execz .LBB0_25
; CHECK-NEXT: ; %bb.1: ; %.preheader5
@@ -133,7 +133,7 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s4
; CHECK-NEXT: v_add_nc_u32_e32 v45, -1, v42
-; CHECK-NEXT: s_mov_b32 s55, 0
+; CHECK-NEXT: s_mov_b32 s69, 0
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v45
; CHECK-NEXT: s_and_b32 exec_lo, exec_lo, vcc_lo
; CHECK-NEXT: s_cbranch_execz .LBB0_25
@@ -141,55 +141,55 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: v_lshlrev_b32_e32 v43, 10, v43
; CHECK-NEXT: v_add_nc_u32_e32 v46, 0x3c05, v0
; CHECK-NEXT: v_mov_b32_e32 v47, 0
-; CHECK-NEXT: s_mov_b32 s53, 0
+; CHECK-NEXT: s_getpc_b64 s[52:53]
+; CHECK-NEXT: s_add_u32 s52, s52, _Z10atomic_incPU3AS3Vj at rel32@lo+4
+; CHECK-NEXT: s_addc_u32 s53, s53, _Z10atomic_incPU3AS3Vj at rel32@hi+12
+; CHECK-NEXT: s_mov_b32 s55, 0
; CHECK-NEXT: .LBB0_5: ; =>This Loop Header: Depth=1
; CHECK-NEXT: ; Child Loop BB0_8 Depth 2
; CHECK-NEXT: ; Child Loop BB0_20 Depth 2
-; CHECK-NEXT: v_add_nc_u32_e32 v0, s55, v44
-; CHECK-NEXT: s_lshl_b32 s4, s55, 5
-; CHECK-NEXT: s_add_i32 s54, s55, 1
-; CHECK-NEXT: s_add_i32 s5, s55, 5
-; CHECK-NEXT: v_or3_b32 v57, s4, v43, s54
+; CHECK-NEXT: v_add_nc_u32_e32 v0, s69, v44
+; CHECK-NEXT: s_lshl_b32 s4, s69, 5
+; CHECK-NEXT: s_add_i32 s68, s69, 1
+; CHECK-NEXT: s_add_i32 s5, s69, 5
+; CHECK-NEXT: v_or3_b32 v57, s4, v43, s68
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: ds_read_u8 v56, v0
-; CHECK-NEXT: v_mov_b32_e32 v58, s54
-; CHECK-NEXT: s_mov_b32 s68, exec_lo
+; CHECK-NEXT: v_mov_b32_e32 v58, s68
+; CHECK-NEXT: s_mov_b32 s80, exec_lo
; CHECK-NEXT: v_cmpx_lt_u32_e64 s5, v42
; CHECK-NEXT: s_cbranch_execz .LBB0_17
; CHECK-NEXT: ; %bb.6: ; %.preheader2
; CHECK-NEXT: ; in Loop: Header=BB0_5 Depth=1
-; CHECK-NEXT: s_mov_b32 s69, 0
-; CHECK-NEXT: s_mov_b32 s80, 0
+; CHECK-NEXT: s_mov_b32 s81, 0
+; CHECK-NEXT: s_mov_b32 s82, 0
; CHECK-NEXT: s_branch .LBB0_8
; CHECK-NEXT: .LBB0_7: ; in Loop: Header=BB0_8 Depth=2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s81
-; CHECK-NEXT: s_add_i32 s80, s80, 4
-; CHECK-NEXT: s_add_i32 s4, s55, s80
-; CHECK-NEXT: v_add_nc_u32_e32 v0, s80, v57
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s83
+; CHECK-NEXT: s_add_i32 s82, s82, 4
+; CHECK-NEXT: s_add_i32 s4, s69, s82
+; CHECK-NEXT: v_add_nc_u32_e32 v0, s82, v57
; CHECK-NEXT: s_add_i32 s5, s4, 5
; CHECK-NEXT: s_add_i32 s4, s4, 1
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, s5, v42
; CHECK-NEXT: v_mov_b32_e32 v58, s4
-; CHECK-NEXT: s_or_b32 s69, vcc_lo, s69
-; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s69
+; CHECK-NEXT: s_or_b32 s81, vcc_lo, s81
+; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s81
; CHECK-NEXT: s_cbranch_execz .LBB0_16
; CHECK-NEXT: .LBB0_8: ; Parent Loop BB0_5 Depth=1
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NEXT: v_add_nc_u32_e32 v59, s80, v46
-; CHECK-NEXT: v_add_nc_u32_e32 v58, s80, v57
+; CHECK-NEXT: v_add_nc_u32_e32 v59, s82, v46
+; CHECK-NEXT: v_add_nc_u32_e32 v58, s82, v57
; CHECK-NEXT: ds_read_u8 v0, v59
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s4, v56, v0 src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: s_and_saveexec_b32 s81, s4
+; CHECK-NEXT: s_and_saveexec_b32 s83, s4
; CHECK-NEXT: s_cbranch_execz .LBB0_10
; CHECK-NEXT: ; %bb.9: ; in Loop: Header=BB0_8 Depth=2
; CHECK-NEXT: v_mov_b32_e32 v31, v40
; CHECK-NEXT: v_mov_b32_e32 v0, 0x3c00
; CHECK-NEXT: s_add_u32 s8, s34, 40
; CHECK-NEXT: s_addc_u32 s9, s35, 0
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, _Z10atomic_incPU3AS3Vj at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, _Z10atomic_incPU3AS3Vj at rel32@hi+12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
; CHECK-NEXT: s_mov_b64 s[10:11], s[36:37]
@@ -197,24 +197,21 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_mov_b32 s13, s50
; CHECK-NEXT: s_mov_b32 s14, s33
; CHECK-NEXT: v_add_nc_u32_e32 v47, 1, v47
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[52:53]
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CHECK-NEXT: ds_write_b32 v0, v58
; CHECK-NEXT: .LBB0_10: ; in Loop: Header=BB0_8 Depth=2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s81
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s83
; CHECK-NEXT: ds_read_u8 v0, v59 offset:1
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s4, v56, v0 src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: s_and_saveexec_b32 s81, s4
+; CHECK-NEXT: s_and_saveexec_b32 s83, s4
; CHECK-NEXT: s_cbranch_execz .LBB0_12
; CHECK-NEXT: ; %bb.11: ; in Loop: Header=BB0_8 Depth=2
; CHECK-NEXT: v_mov_b32_e32 v31, v40
; CHECK-NEXT: v_mov_b32_e32 v0, 0x3c00
; CHECK-NEXT: s_add_u32 s8, s34, 40
; CHECK-NEXT: s_addc_u32 s9, s35, 0
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, _Z10atomic_incPU3AS3Vj at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, _Z10atomic_incPU3AS3Vj at rel32@hi+12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
; CHECK-NEXT: s_mov_b64 s[10:11], s[36:37]
@@ -223,24 +220,21 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_mov_b32 s14, s33
; CHECK-NEXT: v_add_nc_u32_e32 v60, 1, v58
; CHECK-NEXT: v_add_nc_u32_e32 v47, 1, v47
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[52:53]
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CHECK-NEXT: ds_write_b32 v0, v60
; CHECK-NEXT: .LBB0_12: ; in Loop: Header=BB0_8 Depth=2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s81
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s83
; CHECK-NEXT: ds_read_u8 v0, v59 offset:2
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s4, v56, v0 src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: s_and_saveexec_b32 s81, s4
+; CHECK-NEXT: s_and_saveexec_b32 s83, s4
; CHECK-NEXT: s_cbranch_execz .LBB0_14
; CHECK-NEXT: ; %bb.13: ; in Loop: Header=BB0_8 Depth=2
; CHECK-NEXT: v_mov_b32_e32 v31, v40
; CHECK-NEXT: v_mov_b32_e32 v0, 0x3c00
; CHECK-NEXT: s_add_u32 s8, s34, 40
; CHECK-NEXT: s_addc_u32 s9, s35, 0
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, _Z10atomic_incPU3AS3Vj at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, _Z10atomic_incPU3AS3Vj at rel32@hi+12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
; CHECK-NEXT: s_mov_b64 s[10:11], s[36:37]
@@ -249,24 +243,21 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_mov_b32 s14, s33
; CHECK-NEXT: v_add_nc_u32_e32 v60, 2, v58
; CHECK-NEXT: v_add_nc_u32_e32 v47, 1, v47
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[52:53]
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CHECK-NEXT: ds_write_b32 v0, v60
; CHECK-NEXT: .LBB0_14: ; in Loop: Header=BB0_8 Depth=2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s81
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s83
; CHECK-NEXT: ds_read_u8 v0, v59 offset:3
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s4, v56, v0 src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: s_and_saveexec_b32 s81, s4
+; CHECK-NEXT: s_and_saveexec_b32 s83, s4
; CHECK-NEXT: s_cbranch_execz .LBB0_7
; CHECK-NEXT: ; %bb.15: ; in Loop: Header=BB0_8 Depth=2
; CHECK-NEXT: v_mov_b32_e32 v31, v40
; CHECK-NEXT: v_mov_b32_e32 v0, 0x3c00
; CHECK-NEXT: s_add_u32 s8, s34, 40
; CHECK-NEXT: s_addc_u32 s9, s35, 0
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, _Z10atomic_incPU3AS3Vj at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, _Z10atomic_incPU3AS3Vj at rel32@hi+12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
; CHECK-NEXT: s_mov_b64 s[10:11], s[36:37]
@@ -275,33 +266,33 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_mov_b32 s14, s33
; CHECK-NEXT: v_add_nc_u32_e32 v58, 3, v58
; CHECK-NEXT: v_add_nc_u32_e32 v47, 1, v47
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[52:53]
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CHECK-NEXT: ds_write_b32 v0, v58
; CHECK-NEXT: s_branch .LBB0_7
; CHECK-NEXT: .LBB0_16: ; %Flow43
; CHECK-NEXT: ; in Loop: Header=BB0_5 Depth=1
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s69
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s81
; CHECK-NEXT: v_mov_b32_e32 v57, v0
; CHECK-NEXT: .LBB0_17: ; %Flow44
; CHECK-NEXT: ; in Loop: Header=BB0_5 Depth=1
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s68
-; CHECK-NEXT: s_mov_b32 s55, exec_lo
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s80
+; CHECK-NEXT: s_mov_b32 s69, exec_lo
; CHECK-NEXT: v_cmpx_lt_u32_e64 v58, v42
; CHECK-NEXT: s_cbranch_execz .LBB0_23
; CHECK-NEXT: ; %bb.18: ; %.preheader
; CHECK-NEXT: ; in Loop: Header=BB0_5 Depth=1
-; CHECK-NEXT: s_mov_b32 s68, 0
+; CHECK-NEXT: s_mov_b32 s80, 0
; CHECK-NEXT: s_inst_prefetch 0x1
; CHECK-NEXT: s_branch .LBB0_20
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB0_19: ; in Loop: Header=BB0_20 Depth=2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s69
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s81
; CHECK-NEXT: v_add_nc_u32_e32 v58, 1, v58
; CHECK-NEXT: v_add_nc_u32_e32 v57, 1, v57
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, v58, v42
-; CHECK-NEXT: s_or_b32 s68, vcc_lo, s68
-; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s68
+; CHECK-NEXT: s_or_b32 s80, vcc_lo, s80
+; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s80
; CHECK-NEXT: s_cbranch_execz .LBB0_22
; CHECK-NEXT: .LBB0_20: ; Parent Loop BB0_5 Depth=1
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
@@ -309,16 +300,13 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: ds_read_u8 v0, v0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s4, v56, v0 src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: s_and_saveexec_b32 s69, s4
+; CHECK-NEXT: s_and_saveexec_b32 s81, s4
; CHECK-NEXT: s_cbranch_execz .LBB0_19
; CHECK-NEXT: ; %bb.21: ; in Loop: Header=BB0_20 Depth=2
; CHECK-NEXT: v_mov_b32_e32 v31, v40
; CHECK-NEXT: v_mov_b32_e32 v0, 0x3c00
; CHECK-NEXT: s_add_u32 s8, s34, 40
; CHECK-NEXT: s_addc_u32 s9, s35, 0
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, _Z10atomic_incPU3AS3Vj at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, _Z10atomic_incPU3AS3Vj at rel32@hi+12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
; CHECK-NEXT: s_mov_b64 s[10:11], s[36:37]
@@ -326,29 +314,29 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_mov_b32 s13, s50
; CHECK-NEXT: s_mov_b32 s14, s33
; CHECK-NEXT: v_add_nc_u32_e32 v47, 1, v47
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[52:53]
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CHECK-NEXT: ds_write_b32 v0, v57
; CHECK-NEXT: s_branch .LBB0_19
; CHECK-NEXT: .LBB0_22: ; %Flow41
; CHECK-NEXT: ; in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: s_inst_prefetch 0x2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s68
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s80
; CHECK-NEXT: .LBB0_23: ; %Flow42
; CHECK-NEXT: ; in Loop: Header=BB0_5 Depth=1
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s55
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s69
; CHECK-NEXT: ; %bb.24: ; in Loop: Header=BB0_5 Depth=1
-; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, s54, v45
+; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, s68, v45
; CHECK-NEXT: v_cmp_lt_u32_e64 s4, 59, v47
; CHECK-NEXT: v_add_nc_u32_e32 v46, 1, v46
-; CHECK-NEXT: s_mov_b32 s55, s54
+; CHECK-NEXT: s_mov_b32 s69, s68
; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
; CHECK-NEXT: s_and_b32 s4, exec_lo, s4
-; CHECK-NEXT: s_or_b32 s53, s4, s53
-; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s53
+; CHECK-NEXT: s_or_b32 s55, s4, s55
+; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s55
; CHECK-NEXT: s_cbranch_execnz .LBB0_5
; CHECK-NEXT: .LBB0_25: ; %Flow49
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s52
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s54
; CHECK-NEXT: v_mov_b32_e32 v31, v40
; CHECK-NEXT: v_mov_b32_e32 v0, 1
; CHECK-NEXT: s_add_u32 s8, s34, 40
@@ -370,33 +358,39 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: v_cmpx_gt_u32_e64 v47, v41
; CHECK-NEXT: s_cbranch_execz .LBB0_33
; CHECK-NEXT: ; %bb.26:
-; CHECK-NEXT: s_mov_b32 s52, 0
+; CHECK-NEXT: s_getpc_b64 s[52:53]
+; CHECK-NEXT: s_add_u32 s52, s52, _Z10atomic_addPU3AS1Vjj at rel32@lo+4
+; CHECK-NEXT: s_addc_u32 s53, s53, _Z10atomic_addPU3AS1Vjj at rel32@hi+12
+; CHECK-NEXT: s_mov_b32 s80, 0
+; CHECK-NEXT: s_getpc_b64 s[54:55]
+; CHECK-NEXT: s_add_u32 s54, s54, _Z10atomic_subPU3AS1Vjj at rel32@lo+4
+; CHECK-NEXT: s_addc_u32 s55, s55, _Z10atomic_subPU3AS1Vjj at rel32@hi+12
+; CHECK-NEXT: s_getpc_b64 s[68:69]
+; CHECK-NEXT: s_add_u32 s68, s68, _Z14get_local_sizej at rel32@lo+4
+; CHECK-NEXT: s_addc_u32 s69, s69, _Z14get_local_sizej at rel32@hi+12
; CHECK-NEXT: s_branch .LBB0_28
; CHECK-NEXT: .LBB0_27: ; in Loop: Header=BB0_28 Depth=1
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s53
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s81
; CHECK-NEXT: v_mov_b32_e32 v31, v40
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_add_u32 s8, s34, 40
; CHECK-NEXT: s_addc_u32 s9, s35, 0
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, _Z14get_local_sizej at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, _Z14get_local_sizej at rel32@hi+12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
; CHECK-NEXT: s_mov_b64 s[10:11], s[36:37]
; CHECK-NEXT: s_mov_b32 s12, s51
; CHECK-NEXT: s_mov_b32 s13, s50
; CHECK-NEXT: s_mov_b32 s14, s33
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[68:69]
; CHECK-NEXT: v_add_co_u32 v41, vcc_lo, v0, v41
; CHECK-NEXT: v_add_co_ci_u32_e64 v0, null, 0, v1, vcc_lo
; CHECK-NEXT: v_cmp_le_u32_e32 vcc_lo, v47, v41
-; CHECK-NEXT: s_or_b32 s52, vcc_lo, s52
-; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s52
+; CHECK-NEXT: s_or_b32 s80, vcc_lo, s80
+; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s80
; CHECK-NEXT: s_cbranch_execz .LBB0_33
; CHECK-NEXT: .LBB0_28: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v41
-; CHECK-NEXT: s_mov_b32 s53, exec_lo
+; CHECK-NEXT: s_mov_b32 s81, exec_lo
; CHECK-NEXT: ds_read_b32 v0, v0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v63, 10, v0
@@ -437,16 +431,13 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: v_and_b32_e32 v0, 0xf0, v0
; CHECK-NEXT: v_and_b32_e32 v1, 15, v1
; CHECK-NEXT: s_addc_u32 s9, s35, 0
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, _Z10atomic_addPU3AS1Vjj at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, _Z10atomic_addPU3AS1Vjj at rel32@hi+12
-; CHECK-NEXT: v_or3_b32 v2, v3, v2, v4
; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
+; CHECK-NEXT: v_or3_b32 v2, v3, v2, v4
; CHECK-NEXT: s_mov_b64 s[10:11], s[36:37]
; CHECK-NEXT: s_mov_b32 s12, s51
; CHECK-NEXT: s_mov_b32 s13, s50
-; CHECK-NEXT: v_or3_b32 v73, v2, v0, v1
; CHECK-NEXT: s_mov_b32 s14, s33
+; CHECK-NEXT: v_or3_b32 v73, v2, v0, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v0, 1, v73
; CHECK-NEXT: v_lshlrev_b32_e32 v1, 2, v73
; CHECK-NEXT: v_and_b32_e32 v0, 0x7fffc, v0
@@ -458,7 +449,7 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: v_mov_b32_e32 v0, v42
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: v_mov_b32_e32 v1, v43
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[52:53]
; CHECK-NEXT: v_bfe_u32 v0, v0, v74, 4
; CHECK-NEXT: s_mov_b32 s4, exec_lo
; CHECK-NEXT: v_cmpx_gt_u32_e32 12, v0
@@ -498,16 +489,13 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: v_mov_b32_e32 v2, v44
; CHECK-NEXT: s_add_u32 s8, s34, 40
; CHECK-NEXT: s_addc_u32 s9, s35, 0
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, _Z10atomic_subPU3AS1Vjj at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, _Z10atomic_subPU3AS1Vjj at rel32@hi+12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39]
; CHECK-NEXT: s_mov_b64 s[10:11], s[36:37]
; CHECK-NEXT: s_mov_b32 s12, s51
; CHECK-NEXT: s_mov_b32 s13, s50
; CHECK-NEXT: s_mov_b32 s14, s33
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[54:55]
; CHECK-NEXT: s_branch .LBB0_27
; CHECK-NEXT: .LBB0_33:
; CHECK-NEXT: s_endpgm
@@ -866,22 +854,25 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_mov_b32_e32 v41, v0
; CHECK-NEXT: v_lshlrev_b32_e32 v42, 10, v42
+; CHECK-NEXT: s_getpc_b64 s[52:53]
+; CHECK-NEXT: s_add_u32 s52, s52, _Z10atomic_incPU3AS3Vj at rel32@lo+4
+; CHECK-NEXT: s_addc_u32 s53, s53, _Z10atomic_incPU3AS3Vj at rel32@hi+12
; CHECK-NEXT: s_mov_b32 s4, 0
-; CHECK-NEXT: s_mov_b32 s52, 0
-; CHECK-NEXT: ds_write_b8 v46, v43 offset:15364
+; CHECK-NEXT: s_mov_b32 s54, 0
; CHECK-NEXT: v_add_nc_u32_e32 v45, -1, v41
+; CHECK-NEXT: ds_write_b8 v46, v43 offset:15364
; CHECK-NEXT: .LBB1_1: ; %.37
; CHECK-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NEXT: ; Child Loop BB1_3 Depth 2
; CHECK-NEXT: ; Child Loop BB1_8 Depth 2
; CHECK-NEXT: v_add_nc_u32_e32 v0, s4, v44
; CHECK-NEXT: s_lshl_b32 s5, s4, 5
-; CHECK-NEXT: s_add_i32 s53, s4, 1
+; CHECK-NEXT: s_add_i32 s55, s4, 1
; CHECK-NEXT: s_add_i32 s6, s4, 5
-; CHECK-NEXT: v_or3_b32 v47, s5, v42, s53
+; CHECK-NEXT: v_or3_b32 v47, s5, v42, s55
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: ds_read_u8 v46, v0
-; CHECK-NEXT: v_mov_b32_e32 v56, s53
+; CHECK-NEXT: v_mov_b32_e32 v56, s55
; CHECK-NEXT: s_mov_b32 s5, exec_lo
; CHECK-NEXT: v_cmpx_lt_u32_e64 s6, v41
; CHECK-NEXT: s_cbranch_execz .LBB1_5
@@ -910,23 +901,23 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: .LBB1_5: ; %Flow4
; CHECK-NEXT: ; in Loop: Header=BB1_1 Depth=1
; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; CHECK-NEXT: s_mov_b32 s54, exec_lo
+; CHECK-NEXT: s_mov_b32 s64, exec_lo
; CHECK-NEXT: v_cmpx_lt_u32_e64 v56, v41
; CHECK-NEXT: s_cbranch_execz .LBB1_11
; CHECK-NEXT: ; %bb.6: ; %.103.preheader
; CHECK-NEXT: ; in Loop: Header=BB1_1 Depth=1
-; CHECK-NEXT: s_mov_b32 s55, 0
+; CHECK-NEXT: s_mov_b32 s65, 0
; CHECK-NEXT: s_inst_prefetch 0x1
; CHECK-NEXT: s_branch .LBB1_8
; CHECK-NEXT: .p2align 6
; CHECK-NEXT: .LBB1_7: ; %.114
; CHECK-NEXT: ; in Loop: Header=BB1_8 Depth=2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s64
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s66
; CHECK-NEXT: v_add_nc_u32_e32 v56, 1, v56
; CHECK-NEXT: v_add_nc_u32_e32 v47, 1, v47
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, v56, v41
-; CHECK-NEXT: s_or_b32 s55, vcc_lo, s55
-; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s55
+; CHECK-NEXT: s_or_b32 s65, vcc_lo, s65
+; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s65
; CHECK-NEXT: s_cbranch_execz .LBB1_10
; CHECK-NEXT: .LBB1_8: ; %.103
; CHECK-NEXT: ; Parent Loop BB1_1 Depth=1
@@ -935,7 +926,7 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: ds_read_u8 v0, v0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cmp_eq_u16_sdwa s4, v46, v0 src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: s_and_saveexec_b32 s64, s4
+; CHECK-NEXT: s_and_saveexec_b32 s66, s4
; CHECK-NEXT: s_cbranch_execz .LBB1_7
; CHECK-NEXT: ; %bb.9: ; %.110
; CHECK-NEXT: ; in Loop: Header=BB1_8 Depth=2
@@ -943,9 +934,6 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: v_mov_b32_e32 v0, 0x3c00
; CHECK-NEXT: s_add_u32 s8, s38, 40
; CHECK-NEXT: s_addc_u32 s9, s39, 0
-; CHECK-NEXT: s_getpc_b64 s[16:17]
-; CHECK-NEXT: s_add_u32 s16, s16, _Z10atomic_incPU3AS3Vj at rel32@lo+4
-; CHECK-NEXT: s_addc_u32 s17, s17, _Z10atomic_incPU3AS3Vj at rel32@hi+12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: s_mov_b64 s[6:7], s[36:37]
; CHECK-NEXT: s_mov_b64 s[10:11], s[34:35]
@@ -953,29 +941,29 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt
; CHECK-NEXT: s_mov_b32 s13, s50
; CHECK-NEXT: s_mov_b32 s14, s33
; CHECK-NEXT: v_add_nc_u32_e32 v43, 1, v43
-; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[52:53]
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CHECK-NEXT: ds_write_b32 v0, v47
; CHECK-NEXT: s_branch .LBB1_7
; CHECK-NEXT: .LBB1_10: ; %Flow
; CHECK-NEXT: ; in Loop: Header=BB1_1 Depth=1
; CHECK-NEXT: s_inst_prefetch 0x2
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s55
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s65
; CHECK-NEXT: .LBB1_11: ; %Flow2
; CHECK-NEXT: ; in Loop: Header=BB1_1 Depth=1
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s54
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s64
; CHECK-NEXT: ; %bb.12: ; %.32
; CHECK-NEXT: ; in Loop: Header=BB1_1 Depth=1
-; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, s53, v45
+; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, s55, v45
; CHECK-NEXT: v_cmp_lt_u32_e64 s4, 59, v43
; CHECK-NEXT: s_or_b32 s4, vcc_lo, s4
; CHECK-NEXT: s_and_b32 s4, exec_lo, s4
-; CHECK-NEXT: s_or_b32 s52, s4, s52
-; CHECK-NEXT: s_mov_b32 s4, s53
-; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s52
+; CHECK-NEXT: s_or_b32 s54, s4, s54
+; CHECK-NEXT: s_mov_b32 s4, s55
+; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s54
; CHECK-NEXT: s_cbranch_execnz .LBB1_1
; CHECK-NEXT: ; %bb.13: ; %.119
-; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s52
+; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s54
; CHECK-NEXT: v_mov_b32_e32 v31, v40
; CHECK-NEXT: v_mov_b32_e32 v0, 1
; CHECK-NEXT: s_add_u32 s8, s38, 40
diff --git a/llvm/test/CodeGen/AMDGPU/memcpy_const_compare.ll b/llvm/test/CodeGen/AMDGPU/memcpy_const_compare.ll
index 2e1cc8ed00d87..91934d3c72a78 100644
--- a/llvm/test/CodeGen/AMDGPU/memcpy_const_compare.ll
+++ b/llvm/test/CodeGen/AMDGPU/memcpy_const_compare.ll
@@ -13,37 +13,37 @@ define amdgpu_kernel void @_start() {
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; CHECK-NEXT: s_mov_b64 s[0:1], 0
-; CHECK-NEXT: .LBB0_1: ; %dynamic-memcpy-expansion-main-body
-; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ; %bb.1: ; %dynamic-memcpy-expansion-main-body.preheader
; CHECK-NEXT: s_getpc_b64 s[2:3]
; CHECK-NEXT: s_add_u32 s2, s2, src_array at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s3, s3, src_array at gotpcrel32@hi+12
+; CHECK-NEXT: s_getpc_b64 s[4:5]
+; CHECK-NEXT: s_add_u32 s4, s4, dst_array at gotpcrel32@lo+4
+; CHECK-NEXT: s_addc_u32 s5, s5, dst_array at gotpcrel32@hi+12
; CHECK-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
+; CHECK-NEXT: .LBB0_2: ; %dynamic-memcpy-expansion-main-body
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: s_add_u32 s2, s2, s0
-; CHECK-NEXT: s_addc_u32 s3, s3, s1
-; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
+; CHECK-NEXT: s_add_u32 s6, s2, s0
+; CHECK-NEXT: s_addc_u32 s7, s3, s1
+; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[6:7], s[6:7] op_sel:[0,1]
; CHECK-NEXT: flat_load_dwordx4 v[2:5], v[0:1]
-; CHECK-NEXT: s_getpc_b64 s[2:3]
-; CHECK-NEXT: s_add_u32 s2, s2, dst_array at gotpcrel32@lo+4
-; CHECK-NEXT: s_addc_u32 s3, s3, dst_array at gotpcrel32@hi+12
-; CHECK-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: s_add_u32 s2, s2, s0
-; CHECK-NEXT: s_addc_u32 s3, s3, s1
+; CHECK-NEXT: s_add_u32 s6, s4, s0
+; CHECK-NEXT: s_addc_u32 s7, s5, s1
; CHECK-NEXT: s_add_u32 s0, s0, 16
; CHECK-NEXT: s_addc_u32 s1, s1, 0
-; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
-; CHECK-NEXT: v_cmp_lt_u64_e64 s[2:3], s[0:1], 16
-; CHECK-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[6:7], s[6:7] op_sel:[0,1]
+; CHECK-NEXT: v_cmp_lt_u64_e64 s[6:7], s[0:1], 16
+; CHECK-NEXT: s_and_b64 vcc, exec, s[6:7]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
-; CHECK-NEXT: s_cbranch_vccnz .LBB0_1
-; CHECK-NEXT: ; %bb.2: ; %dynamic-memcpy-expansion-residual-cond
-; FIXME: Compare should be evaluated at compile time
+; CHECK-NEXT: s_cbranch_vccnz .LBB0_2
+; CHECK-NEXT: ; %bb.3: ; %dynamic-memcpy-expansion-residual-cond
; CHECK-NEXT: s_cmp_eq_u64 13, 0
-; CHECK-NEXT: s_cbranch_scc1 .LBB0_5
-; CHECK-NEXT: ; %bb.3: ; %dynamic-memcpy-expansion-residual-body.preheader
+; CHECK-NEXT: s_cbranch_scc1 .LBB0_6
+; CHECK-NEXT: ; %bb.4: ; %dynamic-memcpy-expansion-residual-body.preheader
; CHECK-NEXT: s_sub_u32 s4, 29, 13
; CHECK-NEXT: s_subb_u32 s5, 0, 0
; CHECK-NEXT: s_getpc_b64 s[0:1]
@@ -61,7 +61,7 @@ define amdgpu_kernel void @_start() {
; CHECK-NEXT: s_add_u32 s4, s0, s4
; CHECK-NEXT: s_addc_u32 s5, s1, s5
; CHECK-NEXT: s_mov_b64 s[0:1], 0
-; CHECK-NEXT: .LBB0_4: ; %dynamic-memcpy-expansion-residual-body
+; CHECK-NEXT: .LBB0_5: ; %dynamic-memcpy-expansion-residual-body
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_add_u32 s6, s2, s0
; CHECK-NEXT: s_addc_u32 s7, s3, s1
@@ -76,9 +76,10 @@ define amdgpu_kernel void @_start() {
; CHECK-NEXT: s_and_b64 vcc, exec, s[6:7]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: flat_store_byte v[0:1], v2
-; CHECK-NEXT: s_cbranch_vccnz .LBB0_4
-; CHECK-NEXT: .LBB0_5: ; %dynamic-memcpy-post-expansion
+; CHECK-NEXT: s_cbranch_vccnz .LBB0_5
+; CHECK-NEXT: .LBB0_6: ; %dynamic-memcpy-post-expansion
; CHECK-NEXT: s_endpgm
+; FIXME: Compare should be evaluated at compile time
%src_ptr = getelementptr inbounds [128 x i8], ptr @src_array, i64 0, i64 0
%dst_ptr = getelementptr inbounds [128 x i8], ptr @dst_array, i64 0, i64 0
call void @llvm.memcpy.p0.p0.i64(ptr %dst_ptr, ptr %src_ptr, i64 add (i64 sub (i64 16, i64 ptrtoint (ptr addrspacecast (ptr addrspace(4) null to ptr) to i64)), i64 13), i1 false)
diff --git a/llvm/test/CodeGen/AMDGPU/remat-scc-mir.mir b/llvm/test/CodeGen/AMDGPU/remat-scc-mir.mir
new file mode 100644
index 0000000000000..071cc8ae78002
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/remat-scc-mir.mir
@@ -0,0 +1,220 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs --stress-regalloc=2 -run-pass=greedy -o - %s | FileCheck %s
+
+# Test that SOP2 instructions with dead SCC are rematerialized under register pressure
+
+---
+name: test_remat_s_add_i32
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: test_remat_s_add_i32
+
+ %0:sreg_32 = COPY $sgpr0
+
+ ; CHECK: %0:sreg_32 = COPY $sgpr0
+
+ %1:sreg_32 = S_ADD_I32 %0, %0, implicit-def dead $scc
+
+ ; CHECK-NOT: SI_SPILL_S32_SAVE
+
+ S_NOP 0, implicit-def $sgpr1
+
+ ; CHECK: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: S_ADD_I32 %0, %0, implicit-def dead $scc
+ ; CHECK-NOT: SI_SPILL_S32_RESTORE
+
+ S_ENDPGM 0, implicit %0, implicit %1
+...
+---
+name: test_remat_s_min_i32
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: test_remat_s_min_i32
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_MIN_I32 %0, 100, implicit-def dead $scc
+
+ ; CHECK-NOT: SI_SPILL_S32_SAVE
+
+ S_NOP 0, implicit-def $sgpr1
+
+ ; CHECK: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: S_MIN_I32 %0, 100, implicit-def dead $scc
+ ; CHECK-NOT: SI_SPILL_S32_RESTORE
+
+ S_ENDPGM 0, implicit %0, implicit %1
+...
+---
+name: test_remat_s_max_i32
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: test_remat_s_max_i32
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_MAX_I32 %0, 0, implicit-def dead $scc
+
+ ; CHECK-NOT: SI_SPILL_S32_SAVE
+
+ S_NOP 0, implicit-def $sgpr1
+
+ ; CHECK: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: S_MAX_I32 %0, 0, implicit-def dead $scc
+ ; CHECK-NOT: SI_SPILL_S32_RESTORE
+
+ S_ENDPGM 0, implicit %0, implicit %1
+...
+---
+name: test_remat_s_and_b32
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: test_remat_s_and_b32
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 %0, 255, implicit-def dead $scc
+
+ ; CHECK-NOT: SI_SPILL_S32_SAVE
+
+ S_NOP 0, implicit-def $sgpr1
+
+ ; CHECK: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: S_AND_B32 %0, 255, implicit-def dead $scc
+ ; CHECK-NOT: SI_SPILL_S32_RESTORE
+
+ S_ENDPGM 0, implicit %0, implicit %1
+...
+---
+name: test_remat_s_or_b32
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: test_remat_s_or_b32
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_OR_B32 %0, 4096, implicit-def dead $scc
+
+ ; CHECK-NOT: SI_SPILL_S32_SAVE
+
+ S_NOP 0, implicit-def $sgpr1
+
+ ; CHECK: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: S_OR_B32 %0, 4096, implicit-def dead $scc
+ ; CHECK-NOT: SI_SPILL_S32_RESTORE
+
+ S_ENDPGM 0, implicit %0, implicit %1
+...
+---
+name: test_no_remat_scc_live
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: test_no_remat_scc_live
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_ADD_I32 %0, %0, implicit-def $scc
+
+ ; CHECK: S_ADD_I32
+ ; CHECK-NEXT: SI_SPILL_S32_SAVE
+ S_CMPK_EQ_I32 %0, 42, implicit-def $scc
+
+ S_NOP 0, implicit-def $sgpr1
+
+ ; CHECK: SI_SPILL_S32_RESTORE
+
+ ; Use SCC to keep it live
+ %2:sreg_32 = S_CSELECT_B32 %1, %0, implicit $scc
+ S_ENDPGM 0, implicit %2
+...
+---
+name: test_no_remat_multiple_implicit_defs
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: test_no_remat_multiple_implicit_defs
+
+ %0:sreg_32 = COPY $sgpr0
+ %2:sreg_32 = S_ADD_I32 %0, 1, implicit-def $scc
+ %1:sreg_32 = S_ADDC_U32 %0, %0, implicit-def dead $scc, implicit $scc
+
+ ; CHECK: S_ADDC_U32
+ ; CHECK-NEXT: SI_SPILL_S32_SAVE
+
+ S_NOP 0, implicit-def $sgpr1
+ ; CHECK: SI_SPILL_S32_RESTORE
+
+ S_ENDPGM 0, implicit %0, implicit %1
+...
+---
+name: test_no_remat_exec_def
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $exec
+ ; CHECK-LABEL: name: test_no_remat_exec_def
+ ; Instructions that define EXEC should not be rematerialized
+
+ %0:sreg_64 = COPY $sgpr0_sgpr1
+ %1:sreg_64 = S_AND_SAVEEXEC_B64 %0, implicit-def $exec, implicit-def dead $scc, implicit $exec
+
+ ; CHECK: S_AND_SAVEEXEC_B64
+ ; CHECK-NEXT: SI_SPILL_S64_SAVE
+
+ S_NOP 0, implicit-def $sgpr2_sgpr3
+
+ ; CHECK: SI_SPILL_S64_RESTORE
+
+ S_ENDPGM 0, implicit %0, implicit %1
+...
+---
+name: test_no_remat_addc_different_operands
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: test_no_remat_addc_different_operands
+ ; S_ADDC_U32 uses SCC from previous instruction, cannot be rematerialized
+
+ %0:sreg_32 = COPY $sgpr0
+ dead %2:sreg_32 = S_ADD_I32 %0, 5, implicit-def $scc
+ %1:sreg_32 = S_ADDC_U32 %0, 1, implicit-def dead $scc, implicit $scc
+
+ ; CHECK: S_ADDC_U32
+ ; CHECK-NEXT: SI_SPILL_S32_SAVE
+
+ S_NOP 0, implicit-def $sgpr1
+
+ ; CHECK: SI_SPILL_S32_RESTORE
+
+ S_ENDPGM 0, implicit %0, implicit %1
+...
+---
+name: test_no_remat_scc_chain
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: test_no_remat_scc_chain
+ ; Instruction with live SCC should not be rematerialized
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_ADD_I32 %0, 2, implicit-def $scc
+
+ ; CHECK: S_ADD_I32 %0, 2, implicit-def $scc
+ ; CHECK-NEXT: SI_SPILL_S32_SAVE
+
+ S_NOP 0, implicit-def $sgpr1
+
+ ; CHECK: SI_SPILL_S32_RESTORE
+
+ %2:sreg_32 = S_CSELECT_B32 %1, %0, implicit $scc
+ S_ENDPGM 0, implicit %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
index 6202535561d46..6f1cb27a3f85d 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
@@ -29,49 +29,33 @@
# SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
# SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
# SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-# SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
-# SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
-# SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-# SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
+# SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
# SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
# SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-# SHARE: SI_SPILL_S32_SAVE $sgpr32, %stack.2, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.2, addrspace 5)
+# SHARE: SI_SPILL_S32_SAVE $sgpr32, %stack.1, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.1, addrspace 5)
# SHARE: SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
-# SHARE: SI_SPILL_S64_SAVE killed renamable $sgpr4_sgpr5, %stack.1, implicit $exec, implicit $sgpr32 :: (store (s64) into %stack.1, align 4, addrspace 5)
-# SHARE: renamable $sgpr4_sgpr5 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s64) from %stack.1, align 4, addrspace 5)
-# SHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, @func, csr_amdgpu, implicit undef $vgpr0
-# SHARE: $sgpr32 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.2, addrspace 5)
+# SHARE: $sgpr32 = SI_SPILL_S32_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.1, addrspace 5)
# SHARE: $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5)
-# SHARE: renamable $sgpr4_sgpr5 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s64) from %stack.1, align 4, addrspace 5)
-# SHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, @func, csr_amdgpu, implicit $vgpr0
-# SHARE: $sgpr32 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.2, addrspace 5)
+# SHARE: $sgpr32 = SI_SPILL_S32_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.1, addrspace 5)
# NOSHARE: stack:
# NOSHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
# NOSHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
# NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-# NOSHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
+# NOSHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
# NOSHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
# NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
# NOSHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
# NOSHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
# NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-# NOSHARE: - { id: 3, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
-# NOSHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
-# NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-# NOSHARE: SI_SPILL_S32_SAVE $sgpr32, %stack.2, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.2, addrspace 5)
+# NOSHARE: SI_SPILL_S32_SAVE $sgpr32, %stack.1, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.1, addrspace 5)
# NOSHARE: SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
-# NOSHARE: SI_SPILL_S64_SAVE killed renamable $sgpr4_sgpr5, %stack.1, implicit $exec, implicit $sgpr32 :: (store (s64) into %stack.1, align 4, addrspace 5)
-# NOSHARE: renamable $sgpr4_sgpr5 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s64) from %stack.1, align 4, addrspace 5)
-# NOSHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, @func, csr_amdgpu, implicit undef $vgpr0
-# NOSHARE: $sgpr32 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.2, addrspace 5)
-# NOSHARE: SI_SPILL_S32_SAVE $sgpr32, %stack.3, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.3, addrspace 5)
+# NOSHARE: $sgpr32 = SI_SPILL_S32_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.1, addrspace 5)
+# NOSHARE: SI_SPILL_S32_SAVE $sgpr32, %stack.2, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.2, addrspace 5)
# NOSHARE: $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5)
-# NOSHARE: renamable $sgpr4_sgpr5 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s64) from %stack.1, align 4, addrspace 5)
-# NOSHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, @func, csr_amdgpu, implicit $vgpr0
-# NOSHARE: $sgpr32 = SI_SPILL_S32_RESTORE %stack.3, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.3, addrspace 5)
+# NOSHARE: $sgpr32 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.2, addrspace 5)
...
diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
index 99621bccf06ae..4a6b91ea3a137 100644
--- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
@@ -34,12 +34,8 @@ body: |
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 2, [[DEF]], implicit $sgpr0_sgpr1
; SGPR_SPILLED-NEXT: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; SGPR_SPILLED-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr
- ; SGPR_SPILLED-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) 4, target-flags(amdgpu-rel32-hi) 4, implicit-def dead $scc
- ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr4, 3, [[DEF]], implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5
- ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr5, 4, [[DEF]], implicit killed $sgpr4_sgpr5
; SGPR_SPILLED-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr32
- ; SGPR_SPILLED-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 3, implicit-def $sgpr4_sgpr5
- ; SGPR_SPILLED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
+ ; SGPR_SPILLED-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) 4, target-flags(amdgpu-rel32-hi) 4, implicit-def dead $scc
; SGPR_SPILLED-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, 0, csr_amdgpu, implicit undef $vgpr0
; SGPR_SPILLED-NEXT: $sgpr32 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
@@ -50,8 +46,7 @@ body: |
; SGPR_SPILLED-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr32
; SGPR_SPILLED-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr32
; SGPR_SPILLED-NEXT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
- ; SGPR_SPILLED-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 3, implicit-def $sgpr4_sgpr5
- ; SGPR_SPILLED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
+ ; SGPR_SPILLED-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) 4, target-flags(amdgpu-rel32-hi) 4, implicit-def dead $scc
; SGPR_SPILLED-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, 0, csr_amdgpu, implicit killed $vgpr0
; SGPR_SPILLED-NEXT: $sgpr32 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
; SGPR_SPILLED-NEXT: $sgpr2 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 1, implicit-def $sgpr2_sgpr3
@@ -100,12 +95,8 @@ body: |
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr3, 2, [[DEF]], implicit $sgpr2_sgpr3
; SGPR_SPILLED-NEXT: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; SGPR_SPILLED-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr
- ; SGPR_SPILLED-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) 4, target-flags(amdgpu-rel32-hi) 4, implicit-def dead $scc
- ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr4, 3, [[DEF]], implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5
- ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr5, 4, [[DEF]], implicit killed $sgpr4_sgpr5
; SGPR_SPILLED-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr32
- ; SGPR_SPILLED-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 3, implicit-def $sgpr4_sgpr5
- ; SGPR_SPILLED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
+ ; SGPR_SPILLED-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) 4, target-flags(amdgpu-rel32-hi) 4, implicit-def dead $scc
; SGPR_SPILLED-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, 0, csr_amdgpu, implicit undef $vgpr0
; SGPR_SPILLED-NEXT: $sgpr32 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
@@ -115,8 +106,7 @@ body: |
; SGPR_SPILLED-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr32
; SGPR_SPILLED-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr32
; SGPR_SPILLED-NEXT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
- ; SGPR_SPILLED-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 3, implicit-def $sgpr4_sgpr5
- ; SGPR_SPILLED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
+ ; SGPR_SPILLED-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) 4, target-flags(amdgpu-rel32-hi) 4, implicit-def dead $scc
; SGPR_SPILLED-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, 0, csr_amdgpu, implicit killed $vgpr0
; SGPR_SPILLED-NEXT: $sgpr32 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
; SGPR_SPILLED-NEXT: $sgpr2 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 1
@@ -163,12 +153,8 @@ body: |
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr0, 1, [[DEF]]
; SGPR_SPILLED-NEXT: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; SGPR_SPILLED-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[DEF1]], 0, 0, implicit $exec, implicit $flat_scr
- ; SGPR_SPILLED-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) 4, target-flags(amdgpu-rel32-hi) 4, implicit-def dead $scc
- ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr4, 3, [[DEF]], implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5
- ; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr5, 4, [[DEF]], implicit killed $sgpr4_sgpr5
; SGPR_SPILLED-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr32
- ; SGPR_SPILLED-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 3, implicit-def $sgpr4_sgpr5
- ; SGPR_SPILLED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
+ ; SGPR_SPILLED-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) 4, target-flags(amdgpu-rel32-hi) 4, implicit-def dead $scc
; SGPR_SPILLED-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, 0, csr_amdgpu, implicit undef $vgpr0
; SGPR_SPILLED-NEXT: $sgpr32 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
@@ -178,8 +164,7 @@ body: |
; SGPR_SPILLED-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr32
; SGPR_SPILLED-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr32
; SGPR_SPILLED-NEXT: $vgpr0 = COPY [[FLAT_LOAD_DWORD]]
- ; SGPR_SPILLED-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 3, implicit-def $sgpr4_sgpr5
- ; SGPR_SPILLED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
+ ; SGPR_SPILLED-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) 4, target-flags(amdgpu-rel32-hi) 4, implicit-def dead $scc
; SGPR_SPILLED-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, 0, csr_amdgpu, implicit killed $vgpr0
; SGPR_SPILLED-NEXT: $sgpr32 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
; SGPR_SPILLED-NEXT: $sgpr2 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 1, implicit-def $sgpr2_sgpr3
diff --git a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
index 251908b1b0f94..2d1fc84f040f6 100644
--- a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
+++ b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
@@ -32,13 +32,13 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-LABEL: kernel:
; GLOBALNESS1: ; %bb.0: ; %bb
; GLOBALNESS1-NEXT: s_mov_b64 s[36:37], s[6:7]
-; GLOBALNESS1-NEXT: s_load_dwordx4 s[52:55], s[8:9], 0x0
+; GLOBALNESS1-NEXT: s_load_dwordx4 s[68:71], s[8:9], 0x0
; GLOBALNESS1-NEXT: s_load_dword s6, s[8:9], 0x14
; GLOBALNESS1-NEXT: v_mov_b32_e32 v42, 0
; GLOBALNESS1-NEXT: v_pk_mov_b32 v[44:45], 0, 0
; GLOBALNESS1-NEXT: global_store_dword v[44:45], v42, off
; GLOBALNESS1-NEXT: s_waitcnt lgkmcnt(0)
-; GLOBALNESS1-NEXT: global_load_dword v2, v42, s[52:53]
+; GLOBALNESS1-NEXT: global_load_dword v2, v42, s[68:69]
; GLOBALNESS1-NEXT: s_mov_b64 s[48:49], s[4:5]
; GLOBALNESS1-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x18
; GLOBALNESS1-NEXT: s_load_dword s7, s[8:9], 0x20
@@ -49,7 +49,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: v_mov_b32_e32 v0, 0
; GLOBALNESS1-NEXT: s_addc_u32 s1, s1, 0
; GLOBALNESS1-NEXT: v_mov_b32_e32 v1, 0x40994400
-; GLOBALNESS1-NEXT: s_bitcmp1_b32 s54, 0
+; GLOBALNESS1-NEXT: s_bitcmp1_b32 s70, 0
; GLOBALNESS1-NEXT: s_waitcnt lgkmcnt(0)
; GLOBALNESS1-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[0:1]
; GLOBALNESS1-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[4:5], 0
@@ -67,6 +67,9 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: v_cmp_ne_u32_e64 s[64:65], 1, v0
; GLOBALNESS1-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GLOBALNESS1-NEXT: s_cselect_b64 s[4:5], -1, 0
+; GLOBALNESS1-NEXT: s_getpc_b64 s[6:7]
+; GLOBALNESS1-NEXT: s_add_u32 s6, s6, wobble at gotpcrel32@lo+4
+; GLOBALNESS1-NEXT: s_addc_u32 s7, s7, wobble at gotpcrel32@hi+12
; GLOBALNESS1-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GLOBALNESS1-NEXT: s_mov_b64 s[38:39], s[8:9]
; GLOBALNESS1-NEXT: v_cmp_ne_u32_e64 s[8:9], 1, v1
@@ -76,7 +79,8 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: v_writelane_b32 v57, s8, 0
; GLOBALNESS1-NEXT: v_cmp_ne_u32_e64 s[68:69], 1, v0
; GLOBALNESS1-NEXT: v_writelane_b32 v57, s9, 1
-; GLOBALNESS1-NEXT: v_cmp_ne_u32_e64 s[70:71], 1, v3
+; GLOBALNESS1-NEXT: v_cmp_ne_u32_e64 s[96:97], 1, v3
+; GLOBALNESS1-NEXT: s_load_dwordx2 s[52:53], s[6:7], 0x0
; GLOBALNESS1-NEXT: v_mov_b32_e32 v46, 0x80
; GLOBALNESS1-NEXT: s_mov_b32 s82, s16
; GLOBALNESS1-NEXT: s_mov_b32 s83, s15
@@ -105,8 +109,8 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: v_writelane_b32 v57, s4, 6
; GLOBALNESS1-NEXT: v_writelane_b32 v57, s5, 7
; GLOBALNESS1-NEXT: v_cmp_ne_u32_e64 s[80:81], 1, v1
-; GLOBALNESS1-NEXT: v_writelane_b32 v57, s70, 8
-; GLOBALNESS1-NEXT: v_writelane_b32 v57, s71, 9
+; GLOBALNESS1-NEXT: v_writelane_b32 v57, s96, 8
+; GLOBALNESS1-NEXT: v_writelane_b32 v57, s97, 9
; GLOBALNESS1-NEXT: s_branch .LBB1_4
; GLOBALNESS1-NEXT: .LBB1_1: ; %bb70.i
; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1
@@ -131,10 +135,6 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: buffer_store_dword v42, off, s[0:3], 0
; GLOBALNESS1-NEXT: flat_load_dword v56, v[46:47]
; GLOBALNESS1-NEXT: s_addc_u32 s9, s39, 0
-; GLOBALNESS1-NEXT: s_getpc_b64 s[4:5]
-; GLOBALNESS1-NEXT: s_add_u32 s4, s4, wobble at gotpcrel32@lo+4
-; GLOBALNESS1-NEXT: s_addc_u32 s5, s5, wobble at gotpcrel32@hi+12
-; GLOBALNESS1-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GLOBALNESS1-NEXT: s_mov_b64 s[4:5], s[48:49]
; GLOBALNESS1-NEXT: s_mov_b64 s[6:7], s[36:37]
; GLOBALNESS1-NEXT: s_mov_b64 s[10:11], s[34:35]
@@ -143,8 +143,8 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: s_mov_b32 s14, s82
; GLOBALNESS1-NEXT: v_mov_b32_e32 v31, v41
; GLOBALNESS1-NEXT: s_waitcnt lgkmcnt(0)
-; GLOBALNESS1-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GLOBALNESS1-NEXT: s_and_b64 vcc, exec, s[70:71]
+; GLOBALNESS1-NEXT: s_swappc_b64 s[30:31], s[52:53]
+; GLOBALNESS1-NEXT: s_and_b64 vcc, exec, s[96:97]
; GLOBALNESS1-NEXT: s_mov_b64 s[4:5], -1
; GLOBALNESS1-NEXT: ; implicit-def: $sgpr8_sgpr9
; GLOBALNESS1-NEXT: s_cbranch_vccnz .LBB1_9
@@ -152,12 +152,12 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1
; GLOBALNESS1-NEXT: s_mov_b64 s[8:9], -1
; GLOBALNESS1-NEXT: s_mov_b64 s[4:5], 0
-; GLOBALNESS1-NEXT: s_cmp_lt_i32 s55, 1
+; GLOBALNESS1-NEXT: s_cmp_lt_i32 s71, 1
; GLOBALNESS1-NEXT: s_mov_b64 s[6:7], -1
; GLOBALNESS1-NEXT: s_cbranch_scc1 .LBB1_7
; GLOBALNESS1-NEXT: ; %bb.6: ; %LeafBlock12
; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1
-; GLOBALNESS1-NEXT: s_cmp_lg_u32 s55, 1
+; GLOBALNESS1-NEXT: s_cmp_lg_u32 s71, 1
; GLOBALNESS1-NEXT: s_mov_b64 s[6:7], 0
; GLOBALNESS1-NEXT: s_cselect_b64 s[4:5], -1, 0
; GLOBALNESS1-NEXT: .LBB1_7: ; %Flow26
@@ -166,7 +166,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: s_cbranch_vccnz .LBB1_9
; GLOBALNESS1-NEXT: ; %bb.8: ; %LeafBlock
; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1
-; GLOBALNESS1-NEXT: s_cmp_lg_u32 s55, 0
+; GLOBALNESS1-NEXT: s_cmp_lg_u32 s71, 0
; GLOBALNESS1-NEXT: s_mov_b64 s[8:9], 0
; GLOBALNESS1-NEXT: s_cselect_b64 s[4:5], -1, 0
; GLOBALNESS1-NEXT: .LBB1_9: ; %Flow25
@@ -182,7 +182,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: v_cmp_gt_i32_e64 s[86:87], 0, v0
; GLOBALNESS1-NEXT: v_mov_b32_e32 v0, 0
; GLOBALNESS1-NEXT: v_mov_b32_e32 v1, 0x3ff00000
-; GLOBALNESS1-NEXT: s_and_saveexec_b64 s[52:53], s[86:87]
+; GLOBALNESS1-NEXT: s_and_saveexec_b64 s[54:55], s[86:87]
; GLOBALNESS1-NEXT: s_cbranch_execz .LBB1_25
; GLOBALNESS1-NEXT: ; %bb.11: ; %bb33.i
; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1
@@ -243,10 +243,6 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_16 Depth=2
; GLOBALNESS1-NEXT: s_add_u32 s70, s38, 40
; GLOBALNESS1-NEXT: s_addc_u32 s71, s39, 0
-; GLOBALNESS1-NEXT: s_getpc_b64 s[4:5]
-; GLOBALNESS1-NEXT: s_add_u32 s4, s4, wobble at gotpcrel32@lo+4
-; GLOBALNESS1-NEXT: s_addc_u32 s5, s5, wobble at gotpcrel32@hi+12
-; GLOBALNESS1-NEXT: s_load_dwordx2 s[54:55], s[4:5], 0x0
; GLOBALNESS1-NEXT: s_mov_b64 s[4:5], s[48:49]
; GLOBALNESS1-NEXT: s_mov_b64 s[6:7], s[36:37]
; GLOBALNESS1-NEXT: s_mov_b64 s[8:9], s[70:71]
@@ -255,8 +251,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: s_mov_b32 s13, s83
; GLOBALNESS1-NEXT: s_mov_b32 s14, s82
; GLOBALNESS1-NEXT: v_mov_b32_e32 v31, v41
-; GLOBALNESS1-NEXT: s_waitcnt lgkmcnt(0)
-; GLOBALNESS1-NEXT: s_swappc_b64 s[30:31], s[54:55]
+; GLOBALNESS1-NEXT: s_swappc_b64 s[30:31], s[52:53]
; GLOBALNESS1-NEXT: s_mov_b64 s[4:5], s[48:49]
; GLOBALNESS1-NEXT: s_mov_b64 s[6:7], s[36:37]
; GLOBALNESS1-NEXT: s_mov_b64 s[8:9], s[70:71]
@@ -266,7 +261,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: s_mov_b32 s14, s82
; GLOBALNESS1-NEXT: v_mov_b32_e32 v31, v41
; GLOBALNESS1-NEXT: global_store_dwordx2 v[44:45], v[58:59], off
-; GLOBALNESS1-NEXT: s_swappc_b64 s[30:31], s[54:55]
+; GLOBALNESS1-NEXT: s_swappc_b64 s[30:31], s[52:53]
; GLOBALNESS1-NEXT: s_and_saveexec_b64 s[4:5], s[96:97]
; GLOBALNESS1-NEXT: s_cbranch_execz .LBB1_14
; GLOBALNESS1-NEXT: ; %bb.23: ; %bb62.i
@@ -276,16 +271,16 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS1-NEXT: .LBB1_24: ; %Flow23
; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1
; GLOBALNESS1-NEXT: s_load_dwordx4 s[4:7], s[38:39], 0x0
-; GLOBALNESS1-NEXT: v_readlane_b32 s70, v57, 8
+; GLOBALNESS1-NEXT: v_readlane_b32 s96, v57, 8
; GLOBALNESS1-NEXT: v_readlane_b32 s8, v57, 10
; GLOBALNESS1-NEXT: v_pk_mov_b32 v[0:1], 0, 0
-; GLOBALNESS1-NEXT: v_readlane_b32 s71, v57, 9
+; GLOBALNESS1-NEXT: v_readlane_b32 s97, v57, 9
; GLOBALNESS1-NEXT: s_waitcnt lgkmcnt(0)
-; GLOBALNESS1-NEXT: s_mov_b32 s55, s7
+; GLOBALNESS1-NEXT: s_mov_b32 s71, s7
; GLOBALNESS1-NEXT: v_readlane_b32 s9, v57, 11
; GLOBALNESS1-NEXT: .LBB1_25: ; %Flow24
; GLOBALNESS1-NEXT: ; in Loop: Header=BB1_4 Depth=1
-; GLOBALNESS1-NEXT: s_or_b64 exec, exec, s[52:53]
+; GLOBALNESS1-NEXT: s_or_b64 exec, exec, s[54:55]
; GLOBALNESS1-NEXT: s_and_saveexec_b64 s[4:5], s[86:87]
; GLOBALNESS1-NEXT: s_cbranch_execz .LBB1_2
; GLOBALNESS1-NEXT: ; %bb.26: ; %bb67.i
@@ -343,13 +338,13 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-LABEL: kernel:
; GLOBALNESS0: ; %bb.0: ; %bb
; GLOBALNESS0-NEXT: s_mov_b64 s[36:37], s[6:7]
-; GLOBALNESS0-NEXT: s_load_dwordx4 s[52:55], s[8:9], 0x0
+; GLOBALNESS0-NEXT: s_load_dwordx4 s[96:99], s[8:9], 0x0
; GLOBALNESS0-NEXT: s_load_dword s6, s[8:9], 0x14
; GLOBALNESS0-NEXT: v_mov_b32_e32 v42, 0
; GLOBALNESS0-NEXT: v_pk_mov_b32 v[44:45], 0, 0
; GLOBALNESS0-NEXT: global_store_dword v[44:45], v42, off
; GLOBALNESS0-NEXT: s_waitcnt lgkmcnt(0)
-; GLOBALNESS0-NEXT: global_load_dword v2, v42, s[52:53]
+; GLOBALNESS0-NEXT: global_load_dword v2, v42, s[96:97]
; GLOBALNESS0-NEXT: s_mov_b64 s[48:49], s[4:5]
; GLOBALNESS0-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x18
; GLOBALNESS0-NEXT: s_load_dword s7, s[8:9], 0x20
@@ -360,7 +355,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: v_mov_b32_e32 v0, 0
; GLOBALNESS0-NEXT: s_addc_u32 s1, s1, 0
; GLOBALNESS0-NEXT: v_mov_b32_e32 v1, 0x40994400
-; GLOBALNESS0-NEXT: s_bitcmp1_b32 s54, 0
+; GLOBALNESS0-NEXT: s_bitcmp1_b32 s98, 0
; GLOBALNESS0-NEXT: s_waitcnt lgkmcnt(0)
; GLOBALNESS0-NEXT: v_cmp_ngt_f64_e32 vcc, s[4:5], v[0:1]
; GLOBALNESS0-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[4:5], 0
@@ -378,6 +373,9 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: v_cmp_ne_u32_e64 s[64:65], 1, v0
; GLOBALNESS0-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GLOBALNESS0-NEXT: s_cselect_b64 s[4:5], -1, 0
+; GLOBALNESS0-NEXT: s_getpc_b64 s[6:7]
+; GLOBALNESS0-NEXT: s_add_u32 s6, s6, wobble at gotpcrel32@lo+4
+; GLOBALNESS0-NEXT: s_addc_u32 s7, s7, wobble at gotpcrel32@hi+12
; GLOBALNESS0-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GLOBALNESS0-NEXT: s_mov_b64 s[38:39], s[8:9]
; GLOBALNESS0-NEXT: v_cmp_ne_u32_e64 s[8:9], 1, v1
@@ -388,6 +386,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: v_cmp_ne_u32_e64 s[68:69], 1, v0
; GLOBALNESS0-NEXT: v_writelane_b32 v57, s9, 1
; GLOBALNESS0-NEXT: v_cmp_ne_u32_e64 s[84:85], 1, v3
+; GLOBALNESS0-NEXT: s_load_dwordx2 s[52:53], s[6:7], 0x0
; GLOBALNESS0-NEXT: v_mov_b32_e32 v46, 0x80
; GLOBALNESS0-NEXT: s_mov_b32 s70, s16
; GLOBALNESS0-NEXT: s_mov_b32 s71, s15
@@ -442,10 +441,6 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: buffer_store_dword v42, off, s[0:3], 0
; GLOBALNESS0-NEXT: flat_load_dword v56, v[46:47]
; GLOBALNESS0-NEXT: s_addc_u32 s9, s39, 0
-; GLOBALNESS0-NEXT: s_getpc_b64 s[4:5]
-; GLOBALNESS0-NEXT: s_add_u32 s4, s4, wobble at gotpcrel32@lo+4
-; GLOBALNESS0-NEXT: s_addc_u32 s5, s5, wobble at gotpcrel32@hi+12
-; GLOBALNESS0-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; GLOBALNESS0-NEXT: s_mov_b64 s[4:5], s[48:49]
; GLOBALNESS0-NEXT: s_mov_b64 s[6:7], s[36:37]
; GLOBALNESS0-NEXT: s_mov_b64 s[10:11], s[34:35]
@@ -454,7 +449,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: s_mov_b32 s14, s70
; GLOBALNESS0-NEXT: v_mov_b32_e32 v31, v41
; GLOBALNESS0-NEXT: s_waitcnt lgkmcnt(0)
-; GLOBALNESS0-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GLOBALNESS0-NEXT: s_swappc_b64 s[30:31], s[52:53]
; GLOBALNESS0-NEXT: s_and_b64 vcc, exec, s[84:85]
; GLOBALNESS0-NEXT: s_mov_b64 s[4:5], -1
; GLOBALNESS0-NEXT: ; implicit-def: $sgpr8_sgpr9
@@ -463,12 +458,12 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1
; GLOBALNESS0-NEXT: s_mov_b64 s[8:9], -1
; GLOBALNESS0-NEXT: s_mov_b64 s[4:5], 0
-; GLOBALNESS0-NEXT: s_cmp_lt_i32 s55, 1
+; GLOBALNESS0-NEXT: s_cmp_lt_i32 s99, 1
; GLOBALNESS0-NEXT: s_mov_b64 s[6:7], -1
; GLOBALNESS0-NEXT: s_cbranch_scc1 .LBB1_7
; GLOBALNESS0-NEXT: ; %bb.6: ; %LeafBlock12
; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1
-; GLOBALNESS0-NEXT: s_cmp_lg_u32 s55, 1
+; GLOBALNESS0-NEXT: s_cmp_lg_u32 s99, 1
; GLOBALNESS0-NEXT: s_mov_b64 s[6:7], 0
; GLOBALNESS0-NEXT: s_cselect_b64 s[4:5], -1, 0
; GLOBALNESS0-NEXT: .LBB1_7: ; %Flow26
@@ -477,7 +472,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: s_cbranch_vccnz .LBB1_9
; GLOBALNESS0-NEXT: ; %bb.8: ; %LeafBlock
; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1
-; GLOBALNESS0-NEXT: s_cmp_lg_u32 s55, 0
+; GLOBALNESS0-NEXT: s_cmp_lg_u32 s99, 0
; GLOBALNESS0-NEXT: s_mov_b64 s[8:9], 0
; GLOBALNESS0-NEXT: s_cselect_b64 s[4:5], -1, 0
; GLOBALNESS0-NEXT: .LBB1_9: ; %Flow25
@@ -493,7 +488,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: v_cmp_gt_i32_e64 s[86:87], 0, v0
; GLOBALNESS0-NEXT: v_mov_b32_e32 v0, 0
; GLOBALNESS0-NEXT: v_mov_b32_e32 v1, 0x3ff00000
-; GLOBALNESS0-NEXT: s_and_saveexec_b64 s[52:53], s[86:87]
+; GLOBALNESS0-NEXT: s_and_saveexec_b64 s[54:55], s[86:87]
; GLOBALNESS0-NEXT: s_cbranch_execz .LBB1_25
; GLOBALNESS0-NEXT: ; %bb.11: ; %bb33.i
; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1
@@ -502,7 +497,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: v_writelane_b32 v57, s9, 11
; GLOBALNESS0-NEXT: v_readlane_b32 s4, v57, 2
; GLOBALNESS0-NEXT: v_readlane_b32 s5, v57, 3
-; GLOBALNESS0-NEXT: s_mov_b32 s83, s55
+; GLOBALNESS0-NEXT: s_mov_b32 s83, s99
; GLOBALNESS0-NEXT: s_and_b64 vcc, exec, s[4:5]
; GLOBALNESS0-NEXT: s_cbranch_vccnz .LBB1_13
; GLOBALNESS0-NEXT: ; %bb.12: ; %bb39.i
@@ -555,10 +550,6 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_16 Depth=2
; GLOBALNESS0-NEXT: s_add_u32 s84, s38, 40
; GLOBALNESS0-NEXT: s_addc_u32 s85, s39, 0
-; GLOBALNESS0-NEXT: s_getpc_b64 s[4:5]
-; GLOBALNESS0-NEXT: s_add_u32 s4, s4, wobble at gotpcrel32@lo+4
-; GLOBALNESS0-NEXT: s_addc_u32 s5, s5, wobble at gotpcrel32@hi+12
-; GLOBALNESS0-NEXT: s_load_dwordx2 s[54:55], s[4:5], 0x0
; GLOBALNESS0-NEXT: s_mov_b64 s[4:5], s[48:49]
; GLOBALNESS0-NEXT: s_mov_b64 s[6:7], s[36:37]
; GLOBALNESS0-NEXT: s_mov_b64 s[8:9], s[84:85]
@@ -567,8 +558,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: s_mov_b32 s13, s71
; GLOBALNESS0-NEXT: s_mov_b32 s14, s70
; GLOBALNESS0-NEXT: v_mov_b32_e32 v31, v41
-; GLOBALNESS0-NEXT: s_waitcnt lgkmcnt(0)
-; GLOBALNESS0-NEXT: s_swappc_b64 s[30:31], s[54:55]
+; GLOBALNESS0-NEXT: s_swappc_b64 s[30:31], s[52:53]
; GLOBALNESS0-NEXT: s_mov_b64 s[4:5], s[48:49]
; GLOBALNESS0-NEXT: s_mov_b64 s[6:7], s[36:37]
; GLOBALNESS0-NEXT: s_mov_b64 s[8:9], s[84:85]
@@ -578,7 +568,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: s_mov_b32 s14, s70
; GLOBALNESS0-NEXT: v_mov_b32_e32 v31, v41
; GLOBALNESS0-NEXT: global_store_dwordx2 v[44:45], v[58:59], off
-; GLOBALNESS0-NEXT: s_swappc_b64 s[30:31], s[54:55]
+; GLOBALNESS0-NEXT: s_swappc_b64 s[30:31], s[52:53]
; GLOBALNESS0-NEXT: s_and_saveexec_b64 s[4:5], s[96:97]
; GLOBALNESS0-NEXT: s_cbranch_execz .LBB1_14
; GLOBALNESS0-NEXT: ; %bb.23: ; %bb62.i
@@ -590,12 +580,12 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i
; GLOBALNESS0-NEXT: v_readlane_b32 s84, v57, 8
; GLOBALNESS0-NEXT: v_readlane_b32 s8, v57, 10
; GLOBALNESS0-NEXT: v_pk_mov_b32 v[0:1], 0, 0
-; GLOBALNESS0-NEXT: s_mov_b32 s55, s83
+; GLOBALNESS0-NEXT: s_mov_b32 s99, s83
; GLOBALNESS0-NEXT: v_readlane_b32 s85, v57, 9
; GLOBALNESS0-NEXT: v_readlane_b32 s9, v57, 11
; GLOBALNESS0-NEXT: .LBB1_25: ; %Flow24
; GLOBALNESS0-NEXT: ; in Loop: Header=BB1_4 Depth=1
-; GLOBALNESS0-NEXT: s_or_b64 exec, exec, s[52:53]
+; GLOBALNESS0-NEXT: s_or_b64 exec, exec, s[54:55]
; GLOBALNESS0-NEXT: s_and_saveexec_b64 s[4:5], s[86:87]
; GLOBALNESS0-NEXT: s_cbranch_execz .LBB1_2
; GLOBALNESS0-NEXT: ; %bb.26: ; %bb67.i
diff --git a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
index 26d8a047e6541..d6bfbfca0f647 100644
--- a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
+++ b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
@@ -259,7 +259,7 @@ define hidden void @blam() {
; GCN-NEXT: s_or_saveexec_b64 s[18:19], -1
; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[18:19]
-; GCN-NEXT: v_writelane_b32 v45, s16, 26
+; GCN-NEXT: v_writelane_b32 v45, s16, 28
; GCN-NEXT: s_addk_i32 s32, 0x800
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
@@ -292,6 +292,8 @@ define hidden void @blam() {
; GCN-NEXT: v_writelane_b32 v45, s71, 23
; GCN-NEXT: v_writelane_b32 v45, s80, 24
; GCN-NEXT: v_writelane_b32 v45, s81, 25
+; GCN-NEXT: v_writelane_b32 v45, s82, 26
+; GCN-NEXT: v_writelane_b32 v45, s83, 27
; GCN-NEXT: v_mov_b32_e32 v40, v31
; GCN-NEXT: s_mov_b32 s54, s15
; GCN-NEXT: s_mov_b32 s55, s14
@@ -304,12 +306,15 @@ define hidden void @blam() {
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: v_and_b32_e32 v2, 0x3ff, v40
-; GCN-NEXT: flat_load_dword v43, v[0:1]
; GCN-NEXT: v_mov_b32_e32 v42, 0
+; GCN-NEXT: flat_load_dword v43, v[0:1]
; GCN-NEXT: s_mov_b64 s[66:67], 0
+; GCN-NEXT: s_getpc_b64 s[68:69]
+; GCN-NEXT: s_add_u32 s68, s68, spam at rel32@lo+4
+; GCN-NEXT: s_addc_u32 s69, s69, spam at rel32@hi+12
; GCN-NEXT: v_lshlrev_b32_e32 v41, 2, v2
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_eq_f32_e64 s[68:69], 0, v43
+; GCN-NEXT: v_cmp_eq_f32_e64 s[70:71], 0, v43
; GCN-NEXT: v_cmp_neq_f32_e64 s[50:51], 0, v43
; GCN-NEXT: v_mov_b32_e32 v44, 0x7fc00000
; GCN-NEXT: s_branch .LBB1_2
@@ -329,18 +334,15 @@ define hidden void @blam() {
; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 2, v0
; GCN-NEXT: s_mov_b64 s[4:5], -1
; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc
-; GCN-NEXT: s_xor_b64 s[70:71], exec, s[8:9]
+; GCN-NEXT: s_xor_b64 s[80:81], exec, s[8:9]
; GCN-NEXT: s_cbranch_execz .LBB1_12
; GCN-NEXT: ; %bb.3: ; %bb6
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: v_cmp_eq_u32_e64 s[52:53], 3, v0
-; GCN-NEXT: s_and_saveexec_b64 s[80:81], s[52:53]
+; GCN-NEXT: s_and_saveexec_b64 s[82:83], s[52:53]
; GCN-NEXT: s_cbranch_execz .LBB1_11
; GCN-NEXT: ; %bb.4: ; %bb11
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
-; GCN-NEXT: s_getpc_b64 s[16:17]
-; GCN-NEXT: s_add_u32 s16, s16, spam at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s17, s17, spam at rel32@hi+12
; GCN-NEXT: s_mov_b64 s[4:5], s[48:49]
; GCN-NEXT: s_mov_b64 s[6:7], s[38:39]
; GCN-NEXT: s_mov_b64 s[8:9], s[36:37]
@@ -350,20 +352,20 @@ define hidden void @blam() {
; GCN-NEXT: s_mov_b32 s14, s55
; GCN-NEXT: s_mov_b32 s15, s54
; GCN-NEXT: v_mov_b32_e32 v31, v40
-; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GCN-NEXT: s_swappc_b64 s[30:31], s[68:69]
; GCN-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
; GCN-NEXT: s_mov_b64 s[6:7], 0
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_cbranch_execz .LBB1_10
; GCN-NEXT: ; %bb.5: ; %bb14
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
-; GCN-NEXT: s_mov_b64 s[8:9], s[68:69]
+; GCN-NEXT: s_mov_b64 s[8:9], s[70:71]
; GCN-NEXT: s_and_saveexec_b64 s[6:7], s[50:51]
; GCN-NEXT: s_cbranch_execz .LBB1_7
; GCN-NEXT: ; %bb.6: ; %bb16
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], 0
-; GCN-NEXT: s_or_b64 s[8:9], s[68:69], exec
+; GCN-NEXT: s_or_b64 s[8:9], s[70:71], exec
; GCN-NEXT: .LBB1_7: ; %Flow3
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: s_or_b64 exec, exec, s[6:7]
@@ -388,13 +390,13 @@ define hidden void @blam() {
; GCN-NEXT: s_and_b64 s[6:7], s[6:7], exec
; GCN-NEXT: .LBB1_11: ; %Flow1
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
-; GCN-NEXT: s_or_b64 exec, exec, s[80:81]
+; GCN-NEXT: s_or_b64 exec, exec, s[82:83]
; GCN-NEXT: s_orn2_b64 s[4:5], s[52:53], exec
; GCN-NEXT: s_and_b64 s[6:7], s[6:7], exec
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB1_12: ; %Flow
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
-; GCN-NEXT: s_andn2_saveexec_b64 s[8:9], s[70:71]
+; GCN-NEXT: s_andn2_saveexec_b64 s[8:9], s[80:81]
; GCN-NEXT: s_cbranch_execz .LBB1_16
; GCN-NEXT: ; %bb.13: ; %bb8
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
@@ -427,6 +429,8 @@ define hidden void @blam() {
; GCN-NEXT: s_branch .LBB1_1
; GCN-NEXT: .LBB1_18: ; %DummyReturnBlock
; GCN-NEXT: s_or_b64 exec, exec, s[66:67]
+; GCN-NEXT: v_readlane_b32 s83, v45, 27
+; GCN-NEXT: v_readlane_b32 s82, v45, 26
; GCN-NEXT: v_readlane_b32 s81, v45, 25
; GCN-NEXT: v_readlane_b32 s80, v45, 24
; GCN-NEXT: v_readlane_b32 s71, v45, 23
@@ -459,7 +463,7 @@ define hidden void @blam() {
; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b32 s32, s33
-; GCN-NEXT: v_readlane_b32 s4, v45, 26
+; GCN-NEXT: v_readlane_b32 s4, v45, 28
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b64 exec, s[6:7]
>From 7a716ada7935a7aff50c07c76e6ef83feb99a331 Mon Sep 17 00:00:00 2001
From: Vlad <Vladislav.Romanov at amd.com>
Date: Tue, 7 Apr 2026 03:43:41 -0500
Subject: [PATCH 2/3] Updated checks in test
---
llvm/test/CodeGen/AMDGPU/remat-scc-mir.mir | 134 +++++++++++++--------
1 file changed, 87 insertions(+), 47 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/remat-scc-mir.mir b/llvm/test/CodeGen/AMDGPU/remat-scc-mir.mir
index 071cc8ae78002..9e1c533251251 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-scc-mir.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-scc-mir.mir
@@ -1,4 +1,5 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs --stress-regalloc=2 -run-pass=greedy -o - %s | FileCheck %s
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 --stress-regalloc=2 -run-pass=greedy -o - %s | FileCheck %s
# Test that SOP2 instructions with dead SCC are rematerialized under register pressure
@@ -8,21 +9,22 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: test_remat_s_add_i32
+ ; CHECK-LABEL: name: test_remat_s_add_i32
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY]], implicit-def dead $scc
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[S_ADD_I32_]]
%0:sreg_32 = COPY $sgpr0
- ; CHECK: %0:sreg_32 = COPY $sgpr0
%1:sreg_32 = S_ADD_I32 %0, %0, implicit-def dead $scc
- ; CHECK-NOT: SI_SPILL_S32_SAVE
S_NOP 0, implicit-def $sgpr1
- ; CHECK: S_NOP 0, implicit-def $sgpr1
- ; CHECK-NEXT: S_ADD_I32 %0, %0, implicit-def dead $scc
- ; CHECK-NOT: SI_SPILL_S32_RESTORE
S_ENDPGM 0, implicit %0, implicit %1
...
@@ -32,18 +34,20 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: test_remat_s_min_i32
+ ; CHECK-LABEL: name: test_remat_s_min_i32
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: [[S_MIN_I32_:%[0-9]+]]:sreg_32 = S_MIN_I32 [[COPY]], 100, implicit-def dead $scc
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[S_MIN_I32_]]
%0:sreg_32 = COPY $sgpr0
%1:sreg_32 = S_MIN_I32 %0, 100, implicit-def dead $scc
- ; CHECK-NOT: SI_SPILL_S32_SAVE
S_NOP 0, implicit-def $sgpr1
- ; CHECK: S_NOP 0, implicit-def $sgpr1
- ; CHECK-NEXT: S_MIN_I32 %0, 100, implicit-def dead $scc
- ; CHECK-NOT: SI_SPILL_S32_RESTORE
S_ENDPGM 0, implicit %0, implicit %1
...
@@ -53,18 +57,20 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: test_remat_s_max_i32
+ ; CHECK-LABEL: name: test_remat_s_max_i32
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: [[S_MAX_I32_:%[0-9]+]]:sreg_32 = S_MAX_I32 [[COPY]], 0, implicit-def dead $scc
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[S_MAX_I32_]]
%0:sreg_32 = COPY $sgpr0
%1:sreg_32 = S_MAX_I32 %0, 0, implicit-def dead $scc
- ; CHECK-NOT: SI_SPILL_S32_SAVE
S_NOP 0, implicit-def $sgpr1
- ; CHECK: S_NOP 0, implicit-def $sgpr1
- ; CHECK-NEXT: S_MAX_I32 %0, 0, implicit-def dead $scc
- ; CHECK-NOT: SI_SPILL_S32_RESTORE
S_ENDPGM 0, implicit %0, implicit %1
...
@@ -74,18 +80,20 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: test_remat_s_and_b32
+ ; CHECK-LABEL: name: test_remat_s_and_b32
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 255, implicit-def dead $scc
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[S_AND_B32_]]
%0:sreg_32 = COPY $sgpr0
%1:sreg_32 = S_AND_B32 %0, 255, implicit-def dead $scc
- ; CHECK-NOT: SI_SPILL_S32_SAVE
S_NOP 0, implicit-def $sgpr1
- ; CHECK: S_NOP 0, implicit-def $sgpr1
- ; CHECK-NEXT: S_AND_B32 %0, 255, implicit-def dead $scc
- ; CHECK-NOT: SI_SPILL_S32_RESTORE
S_ENDPGM 0, implicit %0, implicit %1
...
@@ -95,18 +103,20 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: test_remat_s_or_b32
+ ; CHECK-LABEL: name: test_remat_s_or_b32
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], 4096, implicit-def dead $scc
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[S_OR_B32_]]
%0:sreg_32 = COPY $sgpr0
%1:sreg_32 = S_OR_B32 %0, 4096, implicit-def dead $scc
- ; CHECK-NOT: SI_SPILL_S32_SAVE
S_NOP 0, implicit-def $sgpr1
- ; CHECK: S_NOP 0, implicit-def $sgpr1
- ; CHECK-NEXT: S_OR_B32 %0, 4096, implicit-def dead $scc
- ; CHECK-NOT: SI_SPILL_S32_RESTORE
S_ENDPGM 0, implicit %0, implicit %1
...
@@ -116,18 +126,25 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: test_no_remat_scc_live
+ ; CHECK-LABEL: name: test_no_remat_scc_live
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ADD_I32 [[COPY]], [[COPY]], implicit-def $scc
+ ; CHECK-NEXT: SI_SPILL_S32_SAVE [[S_ADD_I32_]], %stack.0, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.0, addrspace 5)
+ ; CHECK-NEXT: S_CMPK_EQ_I32 [[COPY]], 42, implicit-def $scc
+ ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: [[SI_SPILL_S32_RESTORE:%[0-9]+]]:sreg_32_xm0_xexec = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.0, addrspace 5)
+ ; CHECK-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[SI_SPILL_S32_RESTORE]], [[COPY]], implicit $scc
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
%0:sreg_32 = COPY $sgpr0
%1:sreg_32 = S_ADD_I32 %0, %0, implicit-def $scc
- ; CHECK: S_ADD_I32
- ; CHECK-NEXT: SI_SPILL_S32_SAVE
S_CMPK_EQ_I32 %0, 42, implicit-def $scc
S_NOP 0, implicit-def $sgpr1
- ; CHECK: SI_SPILL_S32_RESTORE
; Use SCC to keep it live
%2:sreg_32 = S_CSELECT_B32 %1, %0, implicit $scc
@@ -139,17 +156,23 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: test_no_remat_multiple_implicit_defs
+ ; CHECK-LABEL: name: test_no_remat_multiple_implicit_defs
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: dead [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], 1, implicit-def $scc
+ ; CHECK-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ADDC_U32 [[COPY]], [[COPY]], implicit-def dead $scc, implicit $scc
+ ; CHECK-NEXT: SI_SPILL_S32_SAVE [[S_ADDC_U32_]], %stack.0, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.0, addrspace 5)
+ ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: [[SI_SPILL_S32_RESTORE:%[0-9]+]]:sreg_32_xm0_xexec = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.0, addrspace 5)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[SI_SPILL_S32_RESTORE]]
%0:sreg_32 = COPY $sgpr0
%2:sreg_32 = S_ADD_I32 %0, 1, implicit-def $scc
%1:sreg_32 = S_ADDC_U32 %0, %0, implicit-def dead $scc, implicit $scc
- ; CHECK: S_ADDC_U32
- ; CHECK-NEXT: SI_SPILL_S32_SAVE
S_NOP 0, implicit-def $sgpr1
- ; CHECK: SI_SPILL_S32_RESTORE
S_ENDPGM 0, implicit %0, implicit %1
...
@@ -159,18 +182,23 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $exec
- ; CHECK-LABEL: name: test_no_remat_exec_def
; Instructions that define EXEC should not be rematerialized
+ ; CHECK-LABEL: name: test_no_remat_exec_def
+ ; CHECK: liveins: $sgpr0_sgpr1, $exec
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 [[COPY]], implicit-def $exec, implicit-def dead $scc, implicit $exec
+ ; CHECK-NEXT: SI_SPILL_S64_SAVE [[S_AND_SAVEEXEC_B64_]], %stack.0, implicit $exec, implicit $sp_reg :: (store (s64) into %stack.0, align 4, addrspace 5)
+ ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr2_sgpr3
+ ; CHECK-NEXT: [[SI_SPILL_S64_RESTORE:%[0-9]+]]:sreg_64 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s64) from %stack.0, align 4, addrspace 5)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[SI_SPILL_S64_RESTORE]]
%0:sreg_64 = COPY $sgpr0_sgpr1
%1:sreg_64 = S_AND_SAVEEXEC_B64 %0, implicit-def $exec, implicit-def dead $scc, implicit $exec
- ; CHECK: S_AND_SAVEEXEC_B64
- ; CHECK-NEXT: SI_SPILL_S64_SAVE
S_NOP 0, implicit-def $sgpr2_sgpr3
- ; CHECK: SI_SPILL_S64_RESTORE
S_ENDPGM 0, implicit %0, implicit %1
...
@@ -180,19 +208,25 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: test_no_remat_addc_different_operands
; S_ADDC_U32 uses SCC from previous instruction, cannot be rematerialized
+ ; CHECK-LABEL: name: test_no_remat_addc_different_operands
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: dead [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], 5, implicit-def $scc
+ ; CHECK-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ADDC_U32 [[COPY]], 1, implicit-def dead $scc, implicit $scc
+ ; CHECK-NEXT: SI_SPILL_S32_SAVE [[S_ADDC_U32_]], %stack.0, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.0, addrspace 5)
+ ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: [[SI_SPILL_S32_RESTORE:%[0-9]+]]:sreg_32_xm0_xexec = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.0, addrspace 5)
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[SI_SPILL_S32_RESTORE]]
%0:sreg_32 = COPY $sgpr0
dead %2:sreg_32 = S_ADD_I32 %0, 5, implicit-def $scc
%1:sreg_32 = S_ADDC_U32 %0, 1, implicit-def dead $scc, implicit $scc
- ; CHECK: S_ADDC_U32
- ; CHECK-NEXT: SI_SPILL_S32_SAVE
S_NOP 0, implicit-def $sgpr1
- ; CHECK: SI_SPILL_S32_RESTORE
S_ENDPGM 0, implicit %0, implicit %1
...
@@ -202,18 +236,24 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: test_no_remat_scc_chain
; Instruction with live SCC should not be rematerialized
+ ; CHECK-LABEL: name: test_no_remat_scc_chain
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ADD_I32 [[COPY]], 2, implicit-def $scc
+ ; CHECK-NEXT: SI_SPILL_S32_SAVE [[S_ADD_I32_]], %stack.0, implicit $exec, implicit $sp_reg :: (store (s32) into %stack.0, addrspace 5)
+ ; CHECK-NEXT: S_NOP 0, implicit-def $sgpr1
+ ; CHECK-NEXT: [[SI_SPILL_S32_RESTORE:%[0-9]+]]:sreg_32_xm0_xexec = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s32) from %stack.0, addrspace 5)
+ ; CHECK-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[SI_SPILL_S32_RESTORE]], [[COPY]], implicit $scc
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
%0:sreg_32 = COPY $sgpr0
%1:sreg_32 = S_ADD_I32 %0, 2, implicit-def $scc
- ; CHECK: S_ADD_I32 %0, 2, implicit-def $scc
- ; CHECK-NEXT: SI_SPILL_S32_SAVE
S_NOP 0, implicit-def $sgpr1
- ; CHECK: SI_SPILL_S32_RESTORE
%2:sreg_32 = S_CSELECT_B32 %1, %0, implicit $scc
S_ENDPGM 0, implicit %2
>From 2d40e06fa92ec644af798d96d4f7093f779cea7e Mon Sep 17 00:00:00 2001
From: Vlad <Vladislav.Romanov at amd.com>
Date: Tue, 14 Apr 2026 08:23:28 -0500
Subject: [PATCH 3/3] Adjust comment
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index cb3169aea8346..bc7277c327eca 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -199,7 +199,9 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
}
/// Returns true if this instruction can be safely rematerialized at UseIdx
- /// even if it has implicit physical register defs that are live.
+ /// despite having implicit defs. Targets can use this hook to check whether
+ /// any implicit defs would clobber live values at the rematerialization
+ /// point.
virtual bool isImplicitDefRematerializableAt(const MachineInstr &MI,
SlotIndex UseIdx,
LiveIntervals &LIS) const {
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