[llvm] [LLVM][NVPTX] Add movmatrix intrinsic and PTX instruction support (PR #190109)

[Varad Rahul Kamthe via llvm-commits]

================
@@ -3936,6 +3936,36 @@ an event.
 For more information on the pmevent instructions, refer to the `PTX ISA
 <https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#miscellaneous-instructions-pmevent>`__.
 
+Warp-level Matrix Transpose Intrinsics
+---------------------------------------
+
+'``llvm.nvvm.movmatrix.sync.aligned.m8n8.trans.b16``'
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+
+.. code-block:: llvm
+
+  declare i32 @llvm.nvvm.movmatrix.sync.aligned.m8n8.trans.b16(i32 %src)
+
+Overview:
+"""""""""
+
+The '``@llvm.nvvm.movmatrix.sync.aligned.m8n8.trans.b16``' intrinsic
+transposes an 8x8 matrix of 16-bit elements distributed across all 32
+threads of a warp. Each thread provides a 32-bit register containing two
+packed ``.b16`` elements, and receives back two packed ``.b16`` elements
+from the transposed matrix in the same format.
+
+This is a warp-synchronous operation — all threads in the warp must
+execute the intrinsic together, and the result in each thread depends on
+values provided by other threads.
----------------
varadk27 wrote:

Updated in the latest commit with the exact PTX spec wording.

https://github.com/llvm/llvm-project/pull/190109