[llvm] [AArch64] Fix strict weak ordering violation in regalloc hints sort. (PR #192055)

[Sander de Smalen via llvm-commits]

https://github.com/sdesmalen-arm created https://github.com/llvm/llvm-project/pull/192055

This fixes an error with expensive checks after landing #190139.

The issue was:

  Error: comparison doesn't meet irreflexive requirements, assert(!(a < a)).

because it could have previously returned 'true' in the ordering function if registers A and B were equal.

Also made NFC change to rename 'HandleMatchCmpPredicateHint' -> 'HandleDestructivePredicateHint' (that was missed in the review).

>From 9cf6ac83dd40c3641ee98722b2ca9adba50bed26 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Tue, 14 Apr 2026 12:52:50 +0000
Subject: [PATCH] [AArch64] Fix strict weak ordering violation in regalloc
 hints sort.

This fixes an error with expensive checks after landing #190139.

The issue was:

  Error: comparison doesn't meet irreflexive requirements, assert(!(a < a)).

because it could have previously returned 'true' in the ordering
function if registers A and B were equal.

Also made NFC change to rename 'HandleMatchCmpPredicateHint' ->
'HandleDestructivePredicateHint' (that was missed in the review).
---
 llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index a5b934b152abb..f232fa79c7022 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -1115,7 +1115,7 @@ unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
   }
 }
 
-static bool HandleMatchCmpPredicateHint(
+static bool HandleDestructivePredicateHint(
     Register VirtReg, ArrayRef<MCPhysReg> Order,
     SmallVectorImpl<MCPhysReg> &Hints, const VirtRegMap *VRM,
     const MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
@@ -1158,7 +1158,7 @@ static bool HandleMatchCmpPredicateHint(
 
   Hints.append(Order.begin(), Order.end());
   llvm::stable_sort(Hints, [&](Register A, Register B) {
-    return B == Op1Reg &&
+    return A != B && B == Op1Reg &&
            (!CSRs.contains(A) || !MRI.def_empty(A) || Matrix->isPhysRegUsed(A));
   });
   return true;
@@ -1253,8 +1253,8 @@ bool AArch64RegisterInfo::getRegAllocationHints(
       return ConsiderOnlyHints;
   }
 
-  if (HandleMatchCmpPredicateHint(VirtReg, Order, Hints, VRM, MRI, *TII, ST,
-                                  Matrix))
+  if (HandleDestructivePredicateHint(VirtReg, Order, Hints, VRM, MRI, *TII, ST,
+                                     Matrix))
     return ConsiderOnlyHints;
 
   if (!ST.hasSME() || !ST.isStreaming())