[llvm] [AMDGPU][GlobalISel] Implement missing rules for G_TRUNC legalization (PR #180647)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 14 05:08:18 PDT 2026
================
@@ -0,0 +1,755 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx950 -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX-950 %s
+
+;; BRC trunc tests - exercises UniBRC/DivBRC wildcard rules.
+;; Each pair covers a unique subregister extraction sequence.
+
+; --- sub0: 32-bit from 64-bit ---
+
+define amdgpu_ps void @s_trunc_i64_to_i32(i64 inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i64_to_i32
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD_SADDR [[V_MOV_B32_e32_]], [[COPY3]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s32) into %ir.dst, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %trunc = trunc i64 %src to i32
+ store i32 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i64_to_i32(i64 %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i64_to_i32
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE]], [[COPY]], 0, 0, implicit $exec :: (store (s32) into %ir.dst, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %trunc = trunc i64 %src to i32
+ store i32 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1: 64-bit from 96-bit ---
+
+define amdgpu_ps void @s_trunc_i96_to_i64(i96 inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i96_to_i64
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[COPY4]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into %ir.dst, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %trunc = trunc i96 %src to i64
+ store i64 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i96_to_i64(i96 %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i96_to_i64
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (s64) into %ir.dst, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %trunc = trunc i96 %src to i64
+ store i64 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1_sub2: 96-bit from 128-bit ---
+
+define amdgpu_ps void @s_trunc_i128_to_i96(i128 inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i128_to_i96
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vreg_96_align2 = COPY [[REG_SEQUENCE1]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX3_SADDR [[V_MOV_B32_e32_]], [[COPY5]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %trunc = trunc i128 %src to i96
+ store i96 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i128_to_i96(i128 %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i128_to_i96
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %trunc = trunc i128 %src to i96
+ store i96 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1_sub2_sub3: 128-bit from 160-bit ---
+
+define amdgpu_ps void @s_trunc_i160_to_i128(i160 inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i160_to_i128
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE1]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY6]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %trunc = trunc i160 %src to i128
+ store i128 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i160_to_i128(i160 %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i160_to_i128
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr6
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %trunc = trunc i160 %src to i128
+ store i128 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1_sub2_sub3_sub4: 160-bit from 192-bit ---
+
+define amdgpu_ps void @s_trunc_i192_to_i160(i192 inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i192_to_i160
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr7
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE1]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY7]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD_SADDR [[V_MOV_B32_e32_1]], [[COPY8]], [[REG_SEQUENCE]], 16, 0, implicit $exec :: (store (s32) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %trunc = trunc i192 %src to i160
+ store i160 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+define void @v_trunc_i192_to_i160(i192 %src, ptr addrspace(1) %dst) {
+ ; GFX-950-LABEL: name: v_trunc_i192_to_i160
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr6
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr7
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE]], [[COPY4]], 16, 0, implicit $exec :: (store (s32) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
+ %trunc = trunc i192 %src to i160
+ store i160 %trunc, ptr addrspace(1) %dst
+ ret void
+}
+
+; --- sub0_sub1_sub2_sub3_sub4_sub5: 192-bit from 224-bit ---
+
+define amdgpu_ps void @s_trunc_i224_to_i192(i224 inreg %src, ptr addrspace(1) inreg %dst) {
+ ; GFX-950-LABEL: name: s_trunc_i224_to_i192
+ ; GFX-950: bb.1 (%ir-block.0):
+ ; GFX-950-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8
+ ; GFX-950-NEXT: {{ $}}
+ ; GFX-950-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX-950-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr7
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr8
+ ; GFX-950-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+ ; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_192 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3, [[COPY4]], %subreg.sub4, [[COPY5]], %subreg.sub5
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub4_sub5
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0_sub1, [[COPY9]], %subreg.sub2_sub3
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE2]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY11]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:vreg_64_align2 = COPY [[COPY10]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_1]], [[COPY12]], [[REG_SEQUENCE]], 16, 0, implicit $exec :: (store (<2 x s32>) into %ir.dst + 16, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
+ %trunc = trunc i224 %src to i192
+ store i192 %trunc, ptr addrspace(1) %dst
+ ret void
----------------
petar-avramovic wrote:
Need to be more careful when generating tests, try stopping before instruction-select
you will see there is no G_TRUNC, artifact combiner combines it away.
for example this will generate G_TRUNC
```
define amdgpu_ps void @s_trunc_i224_to_i192(ptr addrspace(1) inreg %src, ptr addrspace(1) inreg %dst) {
%val = load i512, ptr addrspace(1) %src
%trunc = trunc i512 %val to i192
store i192 %trunc, ptr addrspace(1) %dst
ret void
}
```
instructions of interest are
```
early-clobber %15:sgpr_512 = S_LOAD_DWORDX16_IMM_ec %0, 0, 0 :: ("amdgpu-noclobber" load (<16 x s32>) from %ir.src, align 8, addrspace 1)
%7:sgpr_192 = COPY %15.sub0_sub1_sub2_sub3_sub4_sub5
``
https://github.com/llvm/llvm-project/pull/180647
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