[llvm] [AMDGPU][Scheduler] Fix non-monotonic SlotIndex after schedule revert (PR #192039)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 14 04:50:09 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: michaelselehov
<details>
<summary>Changes</summary>
modifyRegionSchedule restores the original instruction order by splicing MIs before RegionEnd. When an MI is already at the expected position (MII == RegionEnd) its SlotIndex was left unchanged, even though earlier splices may have shifted neighboring indices. This could leave a stale, lower-numbered slot on a non-moved MI, breaking SlotIndex monotonicity and corrupting LiveIntervals.
The corruption surfaced as a "register isn't live" assertion in GCNDownwardRPTracker when PreRARematStage's finalizeGCNSchedStage globally reverted regions that were already locally reverted by checkScheduling.
Fix by calling LIS->handleMove for non-moved MIs whose SlotIndex has become non-monotonic (PrevIdx >= MI_Idx). Additionally, track whether checkScheduling already reverted a region and skip the redundant global revert in finalizeGCNSchedStage.
Assisted-by: Claude Opus
---
Patch is 49.88 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/192039.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp (+22-4)
- (modified) llvm/lib/Target/AMDGPU/GCNSchedStrategy.h (+8-2)
- (added) llvm/test/CodeGen/AMDGPU/machine-scheduler-revert-slot-monotonicity.mir (+738)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index c9e7be832ec9c..01f583b224a00 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -1870,7 +1870,8 @@ void PreRARematStage::finalizeGCNRegion() {
// target there is no point in trying to re-schedule further regions.
if (!TargetOcc)
return;
- RegionReverts.emplace_back(RegionIdx, Unsched, PressureBefore);
+ RegionReverts.emplace_back(RegionIdx, Unsched, PressureBefore,
+ ScheduleReverted);
if (DAG.MinOccupancy < *TargetOcc) {
REMAT_DEBUG(dbgs() << "Region " << RegionIdx
<< " cannot meet occupancy target, interrupting "
@@ -1881,6 +1882,7 @@ void PreRARematStage::finalizeGCNRegion() {
void GCNSchedStage::checkScheduling() {
// Check the results of scheduling.
+ ScheduleReverted = false;
PressureAfter = DAG.getRealRegPressure(RegionIdx);
LLVM_DEBUG(dbgs() << "Pressure after scheduling: " << print(PressureAfter));
@@ -1945,7 +1947,8 @@ void GCNSchedStage::checkScheduling() {
// Revert if this region's schedule would cause a drop in occupancy or
// spilling.
- if (shouldRevertScheduling(WavesAfter)) {
+ ScheduleReverted = shouldRevertScheduling(WavesAfter);
+ if (ScheduleReverted) {
modifyRegionSchedule(RegionIdx, Unsched);
std::tie(DAG.RegionBegin, DAG.RegionEnd) = DAG.Regions[RegionIdx];
} else {
@@ -2210,6 +2213,18 @@ void GCNSchedStage::modifyRegionSchedule(unsigned RegionIdx,
if (NonDebugReordered)
DAG.LIS->handleMove(*MI, true);
} else {
+ // MI is already at the expected position. However, earlier splices in
+ // this loop may have changed neighboring slot indices, so this MI's
+ // slot index can become non-monotonic w.r.t. the physical MBB order.
+ // Only re-seat when monotonicity is actually violated to avoid
+ // unnecessary LiveInterval changes that could perturb scheduling.
+ if (!MI->isDebugInstr() && !MI->isBundled() &&
+ DAG.LIS->getSlotIndexes()->hasIndex(*MI)) {
+ SlotIndex MI_Idx = DAG.LIS->getInstructionIndex(*MI);
+ SlotIndex PrevIdx = DAG.LIS->getSlotIndexes()->getIndexBefore(*MI);
+ if (PrevIdx >= MI_Idx)
+ DAG.LIS->handleMove(*MI, true);
+ }
++RegionEnd;
}
if (MI->isDebugInstr()) {
@@ -3182,10 +3197,13 @@ void PreRARematStage::finalizeGCNSchedStage() {
}
// Revert re-scheduling in all affected regions.
- for (const auto &[RegionIdx, OrigMIOrder, MaxPressure] : RegionReverts) {
+ for (const auto &[RegionIdx, OrigMIOrder, MaxPressure, AlreadyReverted] :
+ RegionReverts) {
+ DAG.Pressure[RegionIdx] = MaxPressure;
+ if (AlreadyReverted)
+ continue;
REMAT_DEBUG(dbgs() << "Reverting re-scheduling in region " << RegionIdx
<< '\n');
- DAG.Pressure[RegionIdx] = MaxPressure;
modifyRegionSchedule(RegionIdx, OrigMIOrder);
}
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
index 2cc9e81a65191..2b5e5cfa14ed7 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
@@ -369,6 +369,9 @@ class GCNSchedStage {
// RP after scheduling the current region.
GCNRegPressure PressureAfter;
+ // Whether checkScheduling reverted the schedule for the current region.
+ bool ScheduleReverted = false;
+
std::vector<std::unique_ptr<ScheduleDAGMutation>> SavedMutations;
GCNSchedStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG);
@@ -717,11 +720,14 @@ class PreRARematStage : public GCNSchedStage {
std::vector<MachineInstr *> OrigMIOrder;
/// Maximum pressure recorded in the region.
GCNRegPressure MaxPressure;
+ /// Whether the region was already reverted by per-region checkScheduling.
+ bool AlreadyReverted = false;
RegionSchedRevert(unsigned RegionIdx, ArrayRef<MachineInstr *> OrigMIOrder,
- const GCNRegPressure &MaxPressure)
+ const GCNRegPressure &MaxPressure,
+ bool AlreadyReverted = false)
: RegionIdx(RegionIdx), OrigMIOrder(OrigMIOrder),
- MaxPressure(MaxPressure) {}
+ MaxPressure(MaxPressure), AlreadyReverted(AlreadyReverted) {}
};
/// After re-scheduling, contains pre-re-scheduling data for all re-scheduled
/// regions.
diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-revert-slot-monotonicity.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-revert-slot-monotonicity.mir
new file mode 100644
index 0000000000000..b6f2118b6469f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-revert-slot-monotonicity.mir
@@ -0,0 +1,738 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=machine-scheduler -o /dev/null %s
+# Verify that modifyRegionSchedule does not leave non-monotonic SlotIndexes
+# when reverting a schedule. This used to crash with "register isn't live"
+# in GCNDownwardRPTracker::advanceBeforeNext().
+---
+name: _ZN2ck27kernel_gemm_xdl_cshuffle_v3INS_28GridwiseGemm_xdl_cshuffle_v3INS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_ttfttNS_16tensor_operation12element_wise11PassThroughES8_S8_LNS6_6device18GemmSpecializationE7ELi256ELi128ELi128ELi64ELi4ELi4ELi32ELi32ELi2ELi2ENS_8SequenceIJLi16ELi16ELi1EEEENSB_IJLi0ELi2ELi1EEEESD_Li1ELi8ELi4ELb0ELi0ESC_SD_SD_Li1ELi8ELi4ELb0ELi0ELi1ELi1ENSB_IJLi1ELi16ELi1ELi16EEEELi4ELNS_26BlockGemmPipelineSchedulerE0ELNS_24BlockGemmPipelineVersionE4EttLb0ELb0ELb0EEELb1ELNS_25InMemoryDataOperationEnumE1ELi1ELNS_10TailNumberE0EEEvNT_8ArgumentE
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+noPhis: true
+isSSA: false
+noVRegs: false
+hasFakeUses: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHContTarget: false
+hasEHScopes: false
+hasEHFunclets: false
+isOutlined: false
+debugInstrRef: false
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+ - { id: 0, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 1, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 2, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 3, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 4, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 5, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 6, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 7, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 8, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 9, class: sreg_64_xexec, preferred-register: '', flags: [ ] }
+ - { id: 10, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 11, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 12, class: sreg_64, preferred-register: '', flags: [ ] }
+ - { id: 13, class: sreg_64_xexec, preferred-register: '$vcc', flags: [ ] }
+ - { id: 14, class: sreg_64_xexec, preferred-register: '$vcc', flags: [ ] }
+ - { id: 15, class: sreg_64, preferred-register: '', flags: [ ] }
+ - { id: 16, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 17, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 18, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 19, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 20, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 21, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 22, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 23, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 24, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 25, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 26, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 27, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 28, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 29, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 30, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 31, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 32, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 33, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 34, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 35, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 36, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 37, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 38, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 39, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 40, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 41, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 42, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 43, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 44, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 45, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 46, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 47, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 48, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 49, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 50, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 51, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 52, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 53, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 54, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 55, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 56, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 57, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 58, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 59, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 60, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 61, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 62, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 63, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 64, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 65, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 66, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 67, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 68, class: vreg_1, preferred-register: '', flags: [ ] }
+ - { id: 69, class: vreg_1, preferred-register: '', flags: [ ] }
+ - { id: 70, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 71, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 72, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 73, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 74, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 75, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 76, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 77, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 78, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 79, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 80, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 81, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 82, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 83, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 84, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 85, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 86, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 87, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 88, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 89, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 90, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 91, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 92, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 93, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 94, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 95, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 96, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 97, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 98, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 99, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 100, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 101, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 102, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 103, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 104, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 105, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 106, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 107, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 108, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 109, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 110, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 111, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 112, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 113, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 114, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 115, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 116, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 117, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 118, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 119, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 120, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 121, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 122, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 123, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 124, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 125, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 126, class: sgpr_128, preferred-register: '', flags: [ ] }
+ - { id: 127, class: sgpr_64, preferred-register: '', flags: [ ] }
+ - { id: 128, class: sgpr_64, preferred-register: '', flags: [ ] }
+ - { id: 129, class: sgpr_64, preferred-register: '', flags: [ ] }
+ - { id: 130, class: sgpr_64, preferred-register: '', flags: [ ] }
+ - { id: 131, class: sgpr_64, preferred-register: '', flags: [ ] }
+ - { id: 132, class: sgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 133, class: sgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 134, class: sgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 135, class: sgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 136, class: sreg_64, preferred-register: '', flags: [ ] }
+ - { id: 137, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 138, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 139, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 140, class: sgpr_256, preferred-register: '', flags: [ ] }
+ - { id: 141, class: sreg_64_xexec, preferred-register: '', flags: [ ] }
+ - { id: 142, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 143, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 144, class: sreg_64, preferred-register: '', flags: [ ] }
+ - { id: 145, class: sreg_64, preferred-register: '', flags: [ ] }
+ - { id: 146, class: av_512, preferred-register: '', flags: [ ] }
+ - { id: 147, class: av_512, preferred-register: '', flags: [ ] }
+ - { id: 148, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 149, class: areg_512, preferred-register: '', flags: [ ] }
+ - { id: 150, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 151, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 152, class: areg_512, preferred-register: '', flags: [ ] }
+ - { id: 153, class: areg_512, preferred-register: '', flags: [ ] }
+ - { id: 154, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 155, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 156, class: areg_512, preferred-register: '', flags: [ ] }
+ - { id: 157, class: sreg_64, preferred-register: '', flags: [ ] }
+ - { id: 158, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 159, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 160, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 161, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 162, class: areg_512, preferred-register: '', flags: [ ] }
+ - { id: 163, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 164, class: areg_512, preferred-register: '', flags: [ ] }
+ - { id: 165, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 166, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 167, class: areg_512, preferred-register: '', flags: [ ] }
+ - { id: 168, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 169, class: areg_512, preferred-register: '', flags: [ ] }
+ - { id: 170, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 171, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 172, class: areg_512, preferred-register: '', flags: [ ] }
+ - { id: 173, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 174, class: av_32, preferred-register: '', flags: [ ] }
+ - { id: 175, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 176, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 177, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 178, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 179, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 180, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 181, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 182, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 183, class: sreg_64, preferred-register: '', flags: [ ] }
+ - { id: 184, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 185, class: vreg_64, preferred-register: '', flags: [ ] }
+ - { id: 186, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 187, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 188, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 189, class: sreg_64, preferred-register: '', flags: [ ] }
+ - { id: 190, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 191, class: vreg_64, preferred-register: '', flags: [ ] }
+ - { id: 192, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 193, class: vreg_64, preferred-register: '', flags: [ ] }
+ - { id: 194, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 195, class: sreg_64_xexec, preferred-register: '', flags: [ ] }
+ - { id: 196, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 197, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 198, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 199, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 200, class: sreg_32, preferred-register: '', flags: [ ] }
+ - { id: 201, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 202, class: vgpr_32, preferred-register: '', flags: [ ] }
+ - { id: 203, class: vreg_64, preferred-register: '', flags: [ ] }
+ - { id: 204, class: sreg_32, preferred-register: '', ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/192039
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