[llvm] [SPIR-V] Convert integer vector to bool vector for OpAny/OpAll (PR #191804)

[Arseniy Obolenskiy via llvm-commits]

https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/191804

>From 9b282fa3b49319697d297f7431eb9b07f7a24a34 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Mon, 13 Apr 2026 14:29:18 +0200
Subject: [PATCH 1/2] [SPIR-V] Convert integer vector to bool vector for
 OpAny/OpAll

OpenCL any()/all() builtins receive integer vectors, but OpAny/OpAll require boolean vector inputs per the SPIR-V spec
---
 llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp       | 27 ++++++++++++++++++-
 .../CodeGen/SPIRV/transcoding/OpAllAny.ll     |  1 +
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index db5218ec73bb7..90f739a0d37c3 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -1320,12 +1320,37 @@ static bool generateRelationalInst(const SPIRV::IncomingCall *Call,
   std::tie(CompareRegister, RelationType) =
       buildBoolRegister(MIRBuilder, Call->ReturnType, GR);
 
+  // OpAny/OpAll require a boolean vector input, but OpenCL any()/all()
+  // builtins receive integer vectors. Convert via OpINotEqual against zero.
+  SmallVector<Register> Arguments(Call->Arguments.begin(),
+                                  Call->Arguments.end());
+  if ((Opcode == SPIRV::OpAny || Opcode == SPIRV::OpAll) &&
+      !GR->isScalarOrVectorOfType(Arguments[0], SPIRV::OpTypeBool)) {
+    SPIRVTypeInst ArgType = GR->getSPIRVTypeForVReg(Arguments[0]);
+    unsigned NumElts = ArgType->getOperand(2).getImm();
+    SPIRVTypeInst BoolVecTy = GR->getOrCreateSPIRVVectorType(
+        GR->getOrCreateSPIRVBoolType(MIRBuilder, true), NumElts, MIRBuilder,
+        true);
+    const auto &TII =
+        *cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget()).getInstrInfo();
+    Register ZeroReg = GR->getOrCreateConstVector(
+        uint64_t(0), *MIRBuilder.getMRI()->getVRegDef(Arguments[0]), ArgType,
+        TII);
+    Register BoolVecReg = createVirtualRegister(BoolVecTy, GR, MIRBuilder);
+    MIRBuilder.buildInstr(SPIRV::OpINotEqual)
+        .addDef(BoolVecReg)
+        .addUse(GR->getSPIRVTypeID(BoolVecTy))
+        .addUse(Arguments[0])
+        .addUse(ZeroReg);
+    Arguments[0] = BoolVecReg;
+  }
+
   // Build relational instruction.
   auto MIB = MIRBuilder.buildInstr(Opcode)
                  .addDef(CompareRegister)
                  .addUse(GR->getSPIRVTypeID(RelationType));
 
-  for (auto Argument : Call->Arguments)
+  for (auto Argument : Arguments)
     MIB.addUse(Argument);
 
   // Build select instruction.
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpAllAny.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpAllAny.ll
index 52c893c881e8a..0bb267808606f 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpAllAny.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpAllAny.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
 ;; This test checks SYCL relational builtin any and all with vector input types.
 

>From 36002d4d78df798ccc2a8bf7986a014f621e0eb5 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Tue, 14 Apr 2026 12:02:31 +0200
Subject: [PATCH 2/2] Address review comments

---
 llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 90f739a0d37c3..0e90912ae8506 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -1329,13 +1329,11 @@ static bool generateRelationalInst(const SPIRV::IncomingCall *Call,
     SPIRVTypeInst ArgType = GR->getSPIRVTypeForVReg(Arguments[0]);
     unsigned NumElts = ArgType->getOperand(2).getImm();
     SPIRVTypeInst BoolVecTy = GR->getOrCreateSPIRVVectorType(
-        GR->getOrCreateSPIRVBoolType(MIRBuilder, true), NumElts, MIRBuilder,
-        true);
-    const auto &TII =
-        *cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget()).getInstrInfo();
-    Register ZeroReg = GR->getOrCreateConstVector(
-        uint64_t(0), *MIRBuilder.getMRI()->getVRegDef(Arguments[0]), ArgType,
-        TII);
+        GR->getOrCreateSPIRVBoolType(MIRBuilder, /*EmitIR=*/true), NumElts,
+        MIRBuilder, /*EmitIR=*/true);
+    Register ZeroReg =
+        GR->getOrCreateConsIntVector(uint64_t(0), MIRBuilder, ArgType,
+                                     /*EmitIR=*/true);
     Register BoolVecReg = createVirtualRegister(BoolVecTy, GR, MIRBuilder);
     MIRBuilder.buildInstr(SPIRV::OpINotEqual)
         .addDef(BoolVecReg)