[llvm] [LoongArch][NFC] Pre-commit tests for vector fptrunc from vxf64 to vxf32 (PR #164058)
Zhaoxin Yang via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 14 01:20:03 PDT 2026
https://github.com/ylzsx updated https://github.com/llvm/llvm-project/pull/164058
>From 7ec874f372a971c56f17d4038252e1ef1e329bb3 Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Fri, 17 Oct 2025 17:39:15 +0800
Subject: [PATCH 1/2] [LoongArch][NFC] Pre-commit tests for vector fptrunc from
vxf64 to vxf32
---
.../LoongArch/lasx/ir-instruction/fptrunc.ll | 65 +++++++++++++++++
.../LoongArch/lsx/ir-instruction/fptrunc.ll | 72 +++++++++++++++++++
2 files changed, 137 insertions(+)
create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
create mode 100644 llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
new file mode 100644
index 0000000000000..6ade53d9ef531
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK
+
+;; fptrunc
+define void @fptrunc_v4f64_to_v4f32(ptr %res, ptr %a0) nounwind {
+; CHECK-LABEL: fptrunc_v4f64_to_v4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvpickve.d $xr1, $xr0, 1
+; CHECK-NEXT: fcvt.s.d $fa1, $fa1
+; CHECK-NEXT: xvpickve.d $xr2, $xr0, 0
+; CHECK-NEXT: fcvt.s.d $fa2, $fa2
+; CHECK-NEXT: vextrins.w $vr2, $vr1, 16
+; CHECK-NEXT: xvpickve.d $xr1, $xr0, 2
+; CHECK-NEXT: fcvt.s.d $fa1, $fa1
+; CHECK-NEXT: vextrins.w $vr2, $vr1, 32
+; CHECK-NEXT: xvpickve.d $xr0, $xr0, 3
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: vextrins.w $vr2, $vr0, 48
+; CHECK-NEXT: vst $vr2, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <4 x double>, ptr %a0
+ %trunc = fptrunc <4 x double> %v0 to <4 x float>
+ store <4 x float> %trunc, ptr %res
+ ret void
+}
+
+define void @fptrunc_v8f64_to_v8f32(ptr %res, ptr %a0) nounwind {
+; CHECK-LABEL: fptrunc_v8f64_to_v8f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 32
+; CHECK-NEXT: xvld $xr1, $a1, 0
+; CHECK-NEXT: xvpickve.d $xr2, $xr0, 1
+; CHECK-NEXT: fcvt.s.d $fa2, $fa2
+; CHECK-NEXT: xvpickve.d $xr3, $xr0, 0
+; CHECK-NEXT: fcvt.s.d $fa3, $fa3
+; CHECK-NEXT: vextrins.w $vr3, $vr2, 16
+; CHECK-NEXT: xvpickve.d $xr2, $xr0, 2
+; CHECK-NEXT: fcvt.s.d $fa2, $fa2
+; CHECK-NEXT: vextrins.w $vr3, $vr2, 32
+; CHECK-NEXT: xvpickve.d $xr0, $xr0, 3
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: vextrins.w $vr3, $vr0, 48
+; CHECK-NEXT: xvpickve.d $xr0, $xr1, 1
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: xvpickve.d $xr2, $xr1, 0
+; CHECK-NEXT: fcvt.s.d $fa2, $fa2
+; CHECK-NEXT: vextrins.w $vr2, $vr0, 16
+; CHECK-NEXT: xvpickve.d $xr0, $xr1, 2
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: vextrins.w $vr2, $vr0, 32
+; CHECK-NEXT: xvpickve.d $xr0, $xr1, 3
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: vextrins.w $vr2, $vr0, 48
+; CHECK-NEXT: xvpermi.q $xr2, $xr3, 2
+; CHECK-NEXT: xvst $xr2, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <8 x double>, ptr %a0
+ %trunc = fptrunc <8 x double> %v0 to <8 x float>
+ store <8 x float> %trunc, ptr %res
+ ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
new file mode 100644
index 0000000000000..acd487a889c4e
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
@@ -0,0 +1,72 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+
+;; fptrunc
+define void @fptrunc_v1f64_to_v1f32(ptr %res, ptr %a0) nounwind {
+; CHECK-LABEL: fptrunc_v1f64_to_v1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fld.d $fa0, $a1, 0
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: fst.s $fa0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <1 x double>, ptr %a0
+ %trunc = fptrunc <1 x double> %v0 to <1 x float>
+ store <1 x float> %trunc, ptr %res
+ ret void
+}
+
+define void @fptrunc_v2f64_to_v2f32(ptr %res, ptr %a0) nounwind {
+; LA32-LABEL: fptrunc_v2f64_to_v2f32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vld $vr0, $a1, 0
+; LA32-NEXT: vreplvei.d $vr1, $vr0, 0
+; LA32-NEXT: fcvt.s.d $fa1, $fa1
+; LA32-NEXT: vreplvei.d $vr0, $vr0, 1
+; LA32-NEXT: fcvt.s.d $fa0, $fa0
+; LA32-NEXT: fst.s $fa0, $a0, 4
+; LA32-NEXT: fst.s $fa1, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: fptrunc_v2f64_to_v2f32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vld $vr0, $a1, 0
+; LA64-NEXT: vreplvei.d $vr1, $vr0, 1
+; LA64-NEXT: fcvt.s.d $fa1, $fa1
+; LA64-NEXT: vreplvei.d $vr0, $vr0, 0
+; LA64-NEXT: fcvt.s.d $fa0, $fa0
+; LA64-NEXT: vextrins.w $vr0, $vr1, 16
+; LA64-NEXT: vstelm.d $vr0, $a0, 0, 0
+; LA64-NEXT: ret
+entry:
+ %v0 = load <2 x double>, ptr %a0
+ %trunc = fptrunc <2 x double> %v0 to <2 x float>
+ store <2 x float> %trunc, ptr %res
+ ret void
+}
+
+define void @fptrunc_v4f64_to_v4f32(ptr %res, ptr %a0) nounwind {
+; CHECK-LABEL: fptrunc_v4f64_to_v4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a1, 16
+; CHECK-NEXT: vreplvei.d $vr2, $vr0, 1
+; CHECK-NEXT: fcvt.s.d $fa2, $fa2
+; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: vextrins.w $vr0, $vr2, 16
+; CHECK-NEXT: vreplvei.d $vr2, $vr1, 0
+; CHECK-NEXT: fcvt.s.d $fa2, $fa2
+; CHECK-NEXT: vextrins.w $vr0, $vr2, 32
+; CHECK-NEXT: vreplvei.d $vr1, $vr1, 1
+; CHECK-NEXT: fcvt.s.d $fa1, $fa1
+; CHECK-NEXT: vextrins.w $vr0, $vr1, 48
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <4 x double>, ptr %a0
+ %trunc = fptrunc <4 x double> %v0 to <4 x float>
+ store <4 x float> %trunc, ptr %res
+ ret void
+}
>From f96b79904b667d67129c206bf07d4a21f0dd9aba Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Mon, 13 Apr 2026 14:11:17 +0800
Subject: [PATCH 2/2] add tests according review
---
.../LoongArch/lasx/ir-instruction/fptrunc.ll | 52 +++++++++++++++++++
.../LoongArch/lsx/ir-instruction/fptrunc.ll | 40 ++++++++++++++
2 files changed, 92 insertions(+)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
index 6ade53d9ef531..05c96f554be84 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
@@ -63,3 +63,55 @@ entry:
store <8 x float> %trunc, ptr %res
ret void
}
+
+define void @fptrunc_concat_bitcast(ptr %res, ptr %a0) nounwind {
+; CHECK-LABEL: fptrunc_concat_bitcast:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a1, 32
+; CHECK-NEXT: xvpickve.d $xr2, $xr0, 1
+; CHECK-NEXT: fcvt.s.d $fa2, $fa2
+; CHECK-NEXT: xvpickve.d $xr3, $xr0, 0
+; CHECK-NEXT: fcvt.s.d $fa3, $fa3
+; CHECK-NEXT: vextrins.w $vr3, $vr2, 16
+; CHECK-NEXT: xvpickve.d $xr2, $xr0, 2
+; CHECK-NEXT: fcvt.s.d $fa2, $fa2
+; CHECK-NEXT: vextrins.w $vr3, $vr2, 32
+; CHECK-NEXT: xvpickve.d $xr0, $xr0, 3
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: vextrins.w $vr3, $vr0, 48
+; CHECK-NEXT: xvpickve.d $xr0, $xr1, 1
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: xvpickve.d $xr2, $xr1, 0
+; CHECK-NEXT: fcvt.s.d $fa2, $fa2
+; CHECK-NEXT: vextrins.w $vr2, $vr0, 16
+; CHECK-NEXT: xvpickve.d $xr0, $xr1, 2
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: vextrins.w $vr2, $vr0, 32
+; CHECK-NEXT: xvpickve.d $xr0, $xr1, 3
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: vextrins.w $vr2, $vr0, 48
+; CHECK-NEXT: xvpermi.q $xr3, $xr2, 2
+; CHECK-NEXT: xvst $xr3, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %x = load <8 x double>, ptr %a0
+
+ ; split to 2 x <4 x double>
+ %lo = shufflevector <8 x double> %x, <8 x double> poison,
+ <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %hi = shufflevector <8 x double> %x, <8 x double> poison,
+ <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+
+ %r0 = fptrunc <4 x double> %lo to <4 x float>
+ %r1 = fptrunc <4 x double> %hi to <4 x float>
+
+ %i0 = bitcast <4 x float> %r0 to <2 x i64>
+ %i1 = bitcast <4 x float> %r1 to <2 x i64>
+
+ ; concat as integer vector
+ %cat = shufflevector <2 x i64> %i0, <2 x i64> %i1,
+ <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ store <4 x i64> %cat, ptr %res
+ ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
index acd487a889c4e..dfdc5b8438355 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
@@ -70,3 +70,43 @@ entry:
store <4 x float> %trunc, ptr %res
ret void
}
+
+define void @fptrunc_concat_bitcast(ptr %res, ptr %a0) nounwind {
+; CHECK-LABEL: fptrunc_concat_bitcast:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a1, 16
+; CHECK-NEXT: vreplvei.d $vr2, $vr0, 0
+; CHECK-NEXT: fcvt.s.d $fa2, $fa2
+; CHECK-NEXT: vreplvei.d $vr0, $vr0, 1
+; CHECK-NEXT: fcvt.s.d $fa0, $fa0
+; CHECK-NEXT: vreplvei.d $vr3, $vr1, 1
+; CHECK-NEXT: fcvt.s.d $fa3, $fa3
+; CHECK-NEXT: vreplvei.d $vr1, $vr1, 0
+; CHECK-NEXT: fcvt.s.d $fa1, $fa1
+; CHECK-NEXT: vextrins.w $vr2, $vr0, 16
+; CHECK-NEXT: vextrins.w $vr2, $vr1, 32
+; CHECK-NEXT: vextrins.w $vr2, $vr3, 48
+; CHECK-NEXT: vst $vr2, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %x = load <4 x double>, ptr %a0
+
+ ; split to 2 x <2 x double>
+ %lo = shufflevector <4 x double> %x, <4 x double> poison,
+ <2 x i32> <i32 0, i32 1>
+ %hi = shufflevector <4 x double> %x, <4 x double> poison,
+ <2 x i32> <i32 2, i32 3>
+
+ %r0 = fptrunc <2 x double> %lo to <2 x float>
+ %r1 = fptrunc <2 x double> %hi to <2 x float>
+
+ %i0 = bitcast <2 x float> %r0 to i64
+ %i1 = bitcast <2 x float> %r1 to i64
+
+ ; concat as integer vector
+ %cat0 = insertelement <2 x i64> poison, i64 %i0, i32 0
+ %cat1 = insertelement <2 x i64> %cat0, i64 %i1, i32 1
+ store <2 x i64> %cat1, ptr %res
+ ret void
+}
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