[llvm] [LoongArch][NFC] Add tests for add with negative splat immediates (PR #191965)

[via llvm-commits]

https://github.com/heiher created https://github.com/llvm/llvm-project/pull/191965

None

>From d83372483b6e4d1d9cb135cfc29527600a59ffed Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Tue, 14 Apr 2026 13:18:08 +0800
Subject: [PATCH] [LoongArch][NFC] Add tests for add with negative splat
 immediates

---
 .../LoongArch/lasx/ir-instruction/sub.ll      | 66 +++++++++++++++++++
 .../LoongArch/lsx/ir-instruction/sub.ll       | 66 +++++++++++++++++++
 2 files changed, 132 insertions(+)

diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
index bf9f29b578d7d..b598b1b0324ad 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
@@ -121,3 +121,69 @@ entry:
   store <4 x i64> %v1, ptr %res
   ret void
 }
+
+define <32 x i8> @add_v32i8_n1(<32 x i8> %a) nounwind {
+; CHECK-LABEL: add_v32i8_n1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvrepli.b $xr1, -1
+; CHECK-NEXT:    xvadd.b $xr0, $xr0, $xr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <32 x i8> %a, splat (i8 -1)
+  ret <32 x i8> %0
+}
+
+define <32 x i8> @add_v32i8_n31(<32 x i8> %a) nounwind {
+; CHECK-LABEL: add_v32i8_n31:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvrepli.b $xr1, -31
+; CHECK-NEXT:    xvadd.b $xr0, $xr0, $xr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <32 x i8> %a, splat (i8 -31)
+  ret <32 x i8> %0
+}
+
+define <32 x i8> @add_v32i8_n32(<32 x i8> %a) nounwind {
+; CHECK-LABEL: add_v32i8_n32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvrepli.b $xr1, -32
+; CHECK-NEXT:    xvadd.b $xr0, $xr0, $xr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <32 x i8> %a, splat (i8 -32)
+  ret <32 x i8> %0
+}
+
+define <16 x i16> @add_v16i16_n31(<16 x i16> %a) nounwind {
+; CHECK-LABEL: add_v16i16_n31:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvrepli.h $xr1, -31
+; CHECK-NEXT:    xvadd.h $xr0, $xr0, $xr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <16 x i16> %a, splat (i16 -31)
+  ret <16 x i16> %0
+}
+
+define <8 x i32> @add_v8i32_n31(<8 x i32> %a) nounwind {
+; CHECK-LABEL: add_v8i32_n31:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvrepli.w $xr1, -31
+; CHECK-NEXT:    xvadd.w $xr0, $xr0, $xr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <8 x i32> %a, splat (i32 -31)
+  ret <8 x i32> %0
+}
+
+define <4 x i64> @add_v4i64_n31(<4 x i64> %a) nounwind {
+; CHECK-LABEL: add_v4i64_n31:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvrepli.d $xr1, -31
+; CHECK-NEXT:    xvadd.d $xr0, $xr0, $xr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <4 x i64> %a, splat (i64 -31)
+  ret <4 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
index ab135faa6ee36..52108473e2c85 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
@@ -121,3 +121,69 @@ entry:
   store <2 x i64> %v1, ptr %res
   ret void
 }
+
+define <16 x i8> @add_v16i8_n1(<16 x i8> %a) nounwind {
+; CHECK-LABEL: add_v16i8_n1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vrepli.b $vr1, -1
+; CHECK-NEXT:    vadd.b $vr0, $vr0, $vr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <16 x i8> %a, splat (i8 -1)
+  ret <16 x i8> %0
+}
+
+define <16 x i8> @add_v16i8_n31(<16 x i8> %a) nounwind {
+; CHECK-LABEL: add_v16i8_n31:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vrepli.b $vr1, -31
+; CHECK-NEXT:    vadd.b $vr0, $vr0, $vr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <16 x i8> %a, splat (i8 -31)
+  ret <16 x i8> %0
+}
+
+define <16 x i8> @add_v16i8_n32(<16 x i8> %a) nounwind {
+; CHECK-LABEL: add_v16i8_n32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vrepli.b $vr1, -32
+; CHECK-NEXT:    vadd.b $vr0, $vr0, $vr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <16 x i8> %a, splat (i8 -32)
+  ret <16 x i8> %0
+}
+
+define <8 x i16> @add_v8i16_n31(<8 x i16> %a) nounwind {
+; CHECK-LABEL: add_v8i16_n31:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vrepli.h $vr1, -31
+; CHECK-NEXT:    vadd.h $vr0, $vr0, $vr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <8 x i16> %a, splat (i16 -31)
+  ret <8 x i16> %0
+}
+
+define <4 x i32> @add_v4i32_n31(<4 x i32> %a) nounwind {
+; CHECK-LABEL: add_v4i32_n31:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vrepli.w $vr1, -31
+; CHECK-NEXT:    vadd.w $vr0, $vr0, $vr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <4 x i32> %a, splat (i32 -31)
+  ret <4 x i32> %0
+}
+
+define <2 x i64> @add_v2i64_n31(<2 x i64> %a) nounwind {
+; CHECK-LABEL: add_v2i64_n31:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vrepli.d $vr1, -31
+; CHECK-NEXT:    vadd.d $vr0, $vr0, $vr1
+; CHECK-NEXT:    ret
+entry:
+  %0 = add <2 x i64> %a, splat (i64 -31)
+  ret <2 x i64> %0
+}