[llvm] Handle IMPLICIT_DEF in TripleMBB for WindowScheduler (PR #179190)
Chandana Mudda via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 13 22:51:11 PDT 2026
https://github.com/chandmudda updated https://github.com/llvm/llvm-project/pull/179190
>From e87d1f810c06c1700cbb084e908d4dfe2a61a9cf Mon Sep 17 00:00:00 2001
From: Chandana Mudda <quic_csinderi at quicinc.com>
Date: Sun, 1 Feb 2026 21:48:52 -0800
Subject: [PATCH 1/3] Handle IMPLICIT_DEF in TripleMBB for WindowScheduler
Previously, IMPLICIT_DEF instructions were not copied into the
triple-MBB region used by the WindowScheduler. This left the
machine-level liveness inconsistent with the triplicated code and
could trigger a LiveIntervals assertion:
LiveIntervals::HMEditor::updateRange: Assertion `LR.verify()' failed.
Copy IMPLICIT_DEF into the triple region so that the triplicated
block has a consistent set of defs and LiveIntervals can update
ranges correctly.
---
llvm/lib/CodeGen/WindowScheduler.cpp | 8 +--
.../Hexagon/win-sched-implicit-def.mir | 54 +++++++++++++++++++
2 files changed, 58 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 2492dfc3ca553..0d5794542cd36 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -211,7 +211,7 @@ bool WindowScheduler::initialize() {
};
auto PLI = TII->analyzeLoopForPipelining(MBB);
for (auto &MI : *MBB) {
- if (MI.isMetaInstruction() || MI.isTerminator())
+ if ((MI.isMetaInstruction() && !MI.isImplicitDef()) || MI.isTerminator())
continue;
if (MI.isPHI()) {
if (IsLoopCarried(MI)) {
@@ -297,7 +297,7 @@ void WindowScheduler::generateTripleMBB() {
// DefPairs hold the old and new define register pairs.
DenseMap<Register, Register> DefPairs;
for (auto *MI : OriMIs) {
- if (MI->isMetaInstruction() || MI->isTerminator())
+ if ((MI->isMetaInstruction() && !MI->isImplicitDef()) || MI->isTerminator())
continue;
if (MI->isPHI())
if (Register AntiReg = getAntiRegister(MI))
@@ -312,7 +312,7 @@ void WindowScheduler::generateTripleMBB() {
// are updated accordingly.
for (size_t Cnt = 1; Cnt < DuplicateNum; ++Cnt) {
for (auto *MI : OriMIs) {
- if (MI->isPHI() || MI->isMetaInstruction() ||
+ if (MI->isPHI() || (MI->isMetaInstruction() && !MI->isImplicitDef()) ||
(MI->isTerminator() && Cnt < DuplicateNum - 1))
continue;
auto *NewMI = MF->CloneMachineInstr(MI);
@@ -687,7 +687,7 @@ unsigned WindowScheduler::getOriStage(MachineInstr *OriMI, unsigned Offset) {
// while the rest are set to 1.
unsigned Id = 0;
for (auto *MI : OriMIs) {
- if (MI->isMetaInstruction())
+ if (MI->isMetaInstruction() && !MI->isImplicitDef())
continue;
if (MI == OriMI)
break;
diff --git a/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir b/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
new file mode 100644
index 0000000000000..05c86535ee325
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
@@ -0,0 +1,54 @@
+# RUN: llc -mtriple=hexagon -run-pass pipeliner %s -o - | FileCheck %s
+# REQUIRES: asserts
+# Ensure WindowScheduler copies IMPLICIT_DEF into the triple-MBB region
+# so LiveIntervals no longer hits LR.verify()
+# CHECK: foo
+
+--- |
+ define void @foo() {
+ ret void
+ }
+...
+
+---
+name: foo
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ successors: %bb.1(0x60000000), %bb.2(0x20000000)
+ liveins: $r0, $r1, $r2
+
+ %bb0_e75bf3f0bba6b3ae__1:hvxqr = IMPLICIT_DEF
+ %bb0_e75bf3f0bba6b3ae__2:intregslow8 = IMPLICIT_DEF
+ %bb0_e75bf3f0bba6b3ae__3:predregs = IMPLICIT_DEF
+ %bb0_e75bf3f0bba6b3ae__4:intregs = IMPLICIT_DEF
+ J2_jumpf undef %bb0_e75bf3f0bba6b3ae__3, %bb.2, implicit-def $pc
+ J2_jump %bb.1, implicit-def $pc
+
+ bb.1:
+ successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab)
+
+ J2_jumpt undef %bb0_e75bf3f0bba6b3ae__3, %bb.4, implicit-def $pc
+ J2_jump %bb.2, implicit-def $pc
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ J2_loop0r %bb.3, undef %bb0_e75bf3f0bba6b3ae__4, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+ J2_jump %bb.3, implicit-def $pc
+
+ bb.3 (machine-block-address-taken):
+ successors: %bb.4(0x04000000), %bb.3(0x7c000000)
+
+ %bb3_e75bf3f0bba6b3ae__1:hvxwr = IMPLICIT_DEF
+ %bb3_d787b15822067ced__1:hvxvr = V6_vL32Ub_ai undef %bb0_e75bf3f0bba6b3ae__4, 0 :: (load (s1024), align 8)
+ %bb3_734170929685adbc__1:hvxvr = V6_vlalignb undef %bb3_e75bf3f0bba6b3ae__1.vsub_lo, undef %bb3_d787b15822067ced__1, undef %bb0_e75bf3f0bba6b3ae__2
+ %bb3_ba5a00bd10a880fa__1:hvxvr = V6_vlalignb %bb3_e75bf3f0bba6b3ae__1.vsub_lo, undef %bb3_e75bf3f0bba6b3ae__1.vsub_hi, undef %bb0_e75bf3f0bba6b3ae__2
+ V6_vS32b_qpred_ai undef %bb0_e75bf3f0bba6b3ae__1, undef %bb0_e75bf3f0bba6b3ae__4, 0, %bb3_ba5a00bd10a880fa__1 :: (store (s1024))
+ ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+ J2_jump %bb.4, implicit-def $pc
+
+ bb.4:
+ PS_jmpret $r31, implicit-def $pc
+...
>From fc8913e1b5512df627ae393aca9a2894cc927034 Mon Sep 17 00:00:00 2001
From: Chandana Mudda <quic_csinderi at quicinc.com>
Date: Mon, 16 Feb 2026 23:43:26 -0800
Subject: [PATCH 2/3] Changed isMetaInstruction() to isDebugOrPseudoInstr()
When we were checking with isMetaInstruction() some of the
instructions which impact liveness were skipped.
---
llvm/lib/CodeGen/WindowScheduler.cpp | 8 +-
.../Hexagon/win-sched-implicit-def.mir | 77 ++++++++++++++-----
2 files changed, 61 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 0d5794542cd36..3849a2c2caddf 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -211,7 +211,7 @@ bool WindowScheduler::initialize() {
};
auto PLI = TII->analyzeLoopForPipelining(MBB);
for (auto &MI : *MBB) {
- if ((MI.isMetaInstruction() && !MI.isImplicitDef()) || MI.isTerminator())
+ if (MI.isDebugOrPseudoInstr() || MI.isTerminator())
continue;
if (MI.isPHI()) {
if (IsLoopCarried(MI)) {
@@ -297,7 +297,7 @@ void WindowScheduler::generateTripleMBB() {
// DefPairs hold the old and new define register pairs.
DenseMap<Register, Register> DefPairs;
for (auto *MI : OriMIs) {
- if ((MI->isMetaInstruction() && !MI->isImplicitDef()) || MI->isTerminator())
+ if (MI->isDebugOrPseudoInstr() || MI->isTerminator())
continue;
if (MI->isPHI())
if (Register AntiReg = getAntiRegister(MI))
@@ -312,7 +312,7 @@ void WindowScheduler::generateTripleMBB() {
// are updated accordingly.
for (size_t Cnt = 1; Cnt < DuplicateNum; ++Cnt) {
for (auto *MI : OriMIs) {
- if (MI->isPHI() || (MI->isMetaInstruction() && !MI->isImplicitDef()) ||
+ if (MI->isPHI() || MI->isDebugOrPseudoInstr() ||
(MI->isTerminator() && Cnt < DuplicateNum - 1))
continue;
auto *NewMI = MF->CloneMachineInstr(MI);
@@ -687,7 +687,7 @@ unsigned WindowScheduler::getOriStage(MachineInstr *OriMI, unsigned Offset) {
// while the rest are set to 1.
unsigned Id = 0;
for (auto *MI : OriMIs) {
- if (MI->isMetaInstruction() && !MI->isImplicitDef())
+ if (MI->isDebugOrPseudoInstr())
continue;
if (MI == OriMI)
break;
diff --git a/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir b/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
index 05c86535ee325..29046e3a11da7 100644
--- a/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
+++ b/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
@@ -1,8 +1,8 @@
-# RUN: llc -mtriple=hexagon -run-pass pipeliner %s -o - | FileCheck %s
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=hexagon -run-pass pipeliner -window-sched=force %s -o - | FileCheck %s
# REQUIRES: asserts
# Ensure WindowScheduler copies IMPLICIT_DEF into the triple-MBB region
# so LiveIntervals no longer hits LR.verify()
-# CHECK: foo
--- |
define void @foo() {
@@ -11,44 +11,81 @@
...
---
-name: foo
+name: foo
tracksRegLiveness: true
-body: |
+body: |
+ ; CHECK-LABEL: name: foo
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x60000000), %bb.2(0x20000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead [[DEF:%[0-9]+]]:intregs = IMPLICIT_DEF
+ ; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:predregs = IMPLICIT_DEF
+ ; CHECK-NEXT: dead [[DEF2:%[0-9]+]]:intregslow8 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead [[DEF3:%[0-9]+]]:hvxqr = IMPLICIT_DEF
+ ; CHECK-NEXT: J2_jumpf undef [[DEF1]], %bb.2, implicit-def dead $pc
+ ; CHECK-NEXT: J2_jump %bb.1, implicit-def dead $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: J2_jumpt undef [[DEF1]], %bb.4, implicit-def dead $pc
+ ; CHECK-NEXT: J2_jump %bb.2, implicit-def dead $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: J2_loop0r %bb.3, undef [[DEF]], implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+ ; CHECK-NEXT: J2_jump %bb.3, implicit-def $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3 (machine-block-address-taken):
+ ; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead [[V6_vL32Ub_ai:%[0-9]+]]:hvxvr = V6_vL32Ub_ai undef [[DEF]], 0 :: (load (s1024), align 8)
+ ; CHECK-NEXT: [[DEF4:%[0-9]+]]:hvxwr = IMPLICIT_DEF
+ ; CHECK-NEXT: dead [[V6_vlalignb:%[0-9]+]]:hvxvr = V6_vlalignb undef [[DEF4]].vsub_lo, undef [[V6_vL32Ub_ai]], undef [[DEF2]]
+ ; CHECK-NEXT: [[V6_vlalignb1:%[0-9]+]]:hvxvr = V6_vlalignb [[DEF4]].vsub_lo, undef [[DEF4]].vsub_hi, undef [[DEF2]]
+ ; CHECK-NEXT: V6_vS32b_qpred_ai undef [[DEF3]], undef [[DEF]], 0, [[V6_vlalignb1]] :: (store (s1024))
+ ; CHECK-NEXT: ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+ ; CHECK-NEXT: J2_jump %bb.4, implicit-def dead $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: PS_jmpret $r31, implicit-def dead $pc
bb.0:
successors: %bb.1(0x60000000), %bb.2(0x20000000)
liveins: $r0, $r1, $r2
- %bb0_e75bf3f0bba6b3ae__1:hvxqr = IMPLICIT_DEF
- %bb0_e75bf3f0bba6b3ae__2:intregslow8 = IMPLICIT_DEF
- %bb0_e75bf3f0bba6b3ae__3:predregs = IMPLICIT_DEF
- %bb0_e75bf3f0bba6b3ae__4:intregs = IMPLICIT_DEF
- J2_jumpf undef %bb0_e75bf3f0bba6b3ae__3, %bb.2, implicit-def $pc
- J2_jump %bb.1, implicit-def $pc
+ %104:intregs = IMPLICIT_DEF
+ %105:predregs = IMPLICIT_DEF
+ %106:intregslow8 = IMPLICIT_DEF
+ %107:hvxqr = IMPLICIT_DEF
+ J2_jumpf undef %105, %bb.2, implicit-def dead $pc
+ J2_jump %bb.1, implicit-def dead $pc
bb.1:
successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab)
- J2_jumpt undef %bb0_e75bf3f0bba6b3ae__3, %bb.4, implicit-def $pc
- J2_jump %bb.2, implicit-def $pc
+ J2_jumpt undef %105, %bb.4, implicit-def dead $pc
+ J2_jump %bb.2, implicit-def dead $pc
bb.2:
successors: %bb.3(0x80000000)
- J2_loop0r %bb.3, undef %bb0_e75bf3f0bba6b3ae__4, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+ J2_loop0r %bb.3, undef %104, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
J2_jump %bb.3, implicit-def $pc
bb.3 (machine-block-address-taken):
successors: %bb.4(0x04000000), %bb.3(0x7c000000)
- %bb3_e75bf3f0bba6b3ae__1:hvxwr = IMPLICIT_DEF
- %bb3_d787b15822067ced__1:hvxvr = V6_vL32Ub_ai undef %bb0_e75bf3f0bba6b3ae__4, 0 :: (load (s1024), align 8)
- %bb3_734170929685adbc__1:hvxvr = V6_vlalignb undef %bb3_e75bf3f0bba6b3ae__1.vsub_lo, undef %bb3_d787b15822067ced__1, undef %bb0_e75bf3f0bba6b3ae__2
- %bb3_ba5a00bd10a880fa__1:hvxvr = V6_vlalignb %bb3_e75bf3f0bba6b3ae__1.vsub_lo, undef %bb3_e75bf3f0bba6b3ae__1.vsub_hi, undef %bb0_e75bf3f0bba6b3ae__2
- V6_vS32b_qpred_ai undef %bb0_e75bf3f0bba6b3ae__1, undef %bb0_e75bf3f0bba6b3ae__4, 0, %bb3_ba5a00bd10a880fa__1 :: (store (s1024))
+ %8:hvxvr = V6_vL32Ub_ai undef %104, 0 :: (load (s1024), align 8)
+ %9:hvxwr = IMPLICIT_DEF
+ %48:hvxvr = V6_vlalignb undef %9.vsub_lo, undef %8, undef %106
+ %56:hvxvr = V6_vlalignb %9.vsub_lo, undef %9.vsub_hi, undef %106
+ V6_vS32b_qpred_ai undef %107, undef %104, 0, %56 :: (store (s1024))
ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
- J2_jump %bb.4, implicit-def $pc
+ J2_jump %bb.4, implicit-def dead $pc
bb.4:
- PS_jmpret $r31, implicit-def $pc
+ PS_jmpret $r31, implicit-def dead $pc
...
>From 7e1622b61c065b8d89fb1d38617eae903a8918bd Mon Sep 17 00:00:00 2001
From: Chandana Mudda <quic_csinderi at quicinc.com>
Date: Mon, 13 Apr 2026 22:46:23 -0700
Subject: [PATCH 3/3] Made small changes in test case
Changed register numbers and avoided unnecessary undef.
---
.../Hexagon/win-sched-implicit-def.mir | 48 +++++++++----------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir b/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
index 29046e3a11da7..7d5cd6326812a 100644
--- a/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
+++ b/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=hexagon -run-pass pipeliner -window-sched=force %s -o - | FileCheck %s
+# RUN: llc -mtriple=hexagon -run-pass=pipeliner -window-sched=force %s -o - | FileCheck %s
# REQUIRES: asserts
# Ensure WindowScheduler copies IMPLICIT_DEF into the triple-MBB region
# so LiveIntervals no longer hits LR.verify()
@@ -20,33 +20,33 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x60000000), %bb.2(0x20000000)
; CHECK-NEXT: liveins: $r0, $r1, $r2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead [[DEF:%[0-9]+]]:intregs = IMPLICIT_DEF
- ; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:predregs = IMPLICIT_DEF
- ; CHECK-NEXT: dead [[DEF2:%[0-9]+]]:intregslow8 = IMPLICIT_DEF
- ; CHECK-NEXT: dead [[DEF3:%[0-9]+]]:hvxqr = IMPLICIT_DEF
- ; CHECK-NEXT: J2_jumpf undef [[DEF1]], %bb.2, implicit-def dead $pc
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:intregs = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:predregs = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:intregslow8 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF3:%[0-9]+]]:hvxqr = IMPLICIT_DEF
+ ; CHECK-NEXT: J2_jumpf [[DEF1]], %bb.2, implicit-def dead $pc
; CHECK-NEXT: J2_jump %bb.1, implicit-def dead $pc
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: J2_jumpt undef [[DEF1]], %bb.4, implicit-def dead $pc
+ ; CHECK-NEXT: J2_jumpt [[DEF1]], %bb.4, implicit-def dead $pc
; CHECK-NEXT: J2_jump %bb.2, implicit-def dead $pc
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: J2_loop0r %bb.3, undef [[DEF]], implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+ ; CHECK-NEXT: J2_loop0r %bb.3, [[DEF]], implicit-def $lc0, implicit-def $sa0, implicit-def $usr
; CHECK-NEXT: J2_jump %bb.3, implicit-def $pc
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3 (machine-block-address-taken):
; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead [[V6_vL32Ub_ai:%[0-9]+]]:hvxvr = V6_vL32Ub_ai undef [[DEF]], 0 :: (load (s1024), align 8)
+ ; CHECK-NEXT: [[V6_vL32Ub_ai:%[0-9]+]]:hvxvr = V6_vL32Ub_ai [[DEF]], 0 :: (load (s1024), align 8)
; CHECK-NEXT: [[DEF4:%[0-9]+]]:hvxwr = IMPLICIT_DEF
- ; CHECK-NEXT: dead [[V6_vlalignb:%[0-9]+]]:hvxvr = V6_vlalignb undef [[DEF4]].vsub_lo, undef [[V6_vL32Ub_ai]], undef [[DEF2]]
- ; CHECK-NEXT: [[V6_vlalignb1:%[0-9]+]]:hvxvr = V6_vlalignb [[DEF4]].vsub_lo, undef [[DEF4]].vsub_hi, undef [[DEF2]]
- ; CHECK-NEXT: V6_vS32b_qpred_ai undef [[DEF3]], undef [[DEF]], 0, [[V6_vlalignb1]] :: (store (s1024))
+ ; CHECK-NEXT: dead [[V6_vlalignb:%[0-9]+]]:hvxvr = V6_vlalignb [[DEF4]].vsub_lo, [[V6_vL32Ub_ai]], [[DEF2]]
+ ; CHECK-NEXT: [[V6_vlalignb1:%[0-9]+]]:hvxvr = V6_vlalignb [[DEF4]].vsub_lo, [[DEF4]].vsub_hi, [[DEF2]]
+ ; CHECK-NEXT: V6_vS32b_qpred_ai [[DEF3]], [[DEF]], 0, [[V6_vlalignb1]] :: (store (s1024))
; CHECK-NEXT: ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
; CHECK-NEXT: J2_jump %bb.4, implicit-def dead $pc
; CHECK-NEXT: {{ $}}
@@ -56,33 +56,33 @@ body: |
successors: %bb.1(0x60000000), %bb.2(0x20000000)
liveins: $r0, $r1, $r2
- %104:intregs = IMPLICIT_DEF
- %105:predregs = IMPLICIT_DEF
- %106:intregslow8 = IMPLICIT_DEF
- %107:hvxqr = IMPLICIT_DEF
- J2_jumpf undef %105, %bb.2, implicit-def dead $pc
+ %0:intregs = IMPLICIT_DEF
+ %1:predregs = IMPLICIT_DEF
+ %2:intregslow8 = IMPLICIT_DEF
+ %3:hvxqr = IMPLICIT_DEF
+ J2_jumpf %1, %bb.2, implicit-def dead $pc
J2_jump %bb.1, implicit-def dead $pc
bb.1:
successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab)
- J2_jumpt undef %105, %bb.4, implicit-def dead $pc
+ J2_jumpt %1, %bb.4, implicit-def dead $pc
J2_jump %bb.2, implicit-def dead $pc
bb.2:
successors: %bb.3(0x80000000)
- J2_loop0r %bb.3, undef %104, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+ J2_loop0r %bb.3, %0, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
J2_jump %bb.3, implicit-def $pc
bb.3 (machine-block-address-taken):
successors: %bb.4(0x04000000), %bb.3(0x7c000000)
- %8:hvxvr = V6_vL32Ub_ai undef %104, 0 :: (load (s1024), align 8)
- %9:hvxwr = IMPLICIT_DEF
- %48:hvxvr = V6_vlalignb undef %9.vsub_lo, undef %8, undef %106
- %56:hvxvr = V6_vlalignb %9.vsub_lo, undef %9.vsub_hi, undef %106
- V6_vS32b_qpred_ai undef %107, undef %104, 0, %56 :: (store (s1024))
+ %4:hvxvr = V6_vL32Ub_ai %0, 0 :: (load (s1024), align 8)
+ %5:hvxwr = IMPLICIT_DEF
+ %6:hvxvr = V6_vlalignb %5.vsub_lo, %4, %2
+ %7:hvxvr = V6_vlalignb %5.vsub_lo, %5.vsub_hi, %2
+ V6_vS32b_qpred_ai %3, %0, 0, %7 :: (store (s1024))
ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
J2_jump %bb.4, implicit-def dead $pc
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