[llvm] [ARM] Have ARMISelLowering, not TableGen, optimize cmpz to cmn (PR #191915)
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Mon Apr 13 16:59:19 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: SiliconA-Z
<details>
<summary>Changes</summary>
We can get rid of more rules this way and be closer to removing the cmpz node entirely.
---
Full diff: https://github.com/llvm/llvm-project/pull/191915.diff
4 Files Affected:
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+2-7)
- (modified) llvm/lib/Target/ARM/ARMInstrInfo.td (-4)
- (modified) llvm/lib/Target/ARM/ARMInstrThumb2.td (-6)
- (modified) llvm/test/CodeGen/Thumb2/thumb2-cmn.ll (+71-20)
``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 0ad6c07f36868..b100fe352a1d0 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4616,15 +4616,10 @@ SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
break;
}
- // TODO: Remove CMPZ check once we generalize and remove the CMPZ enum from
- // the codebase.
-
- // TODO: When we have a solution to the vselect predicate not allowing pl/mi
- // all the time, allow those cases to be cmn too no matter what.
- if (CompareType != ARMISD::CMPZ && isCMN(RHS, CC, DAG)) {
+ if (isCMN(RHS, CC, DAG)) {
CompareType = ARMISD::CMN;
RHS = RHS.getOperand(1);
- } else if (CompareType != ARMISD::CMPZ && isCMN(LHS, CC, DAG)) {
+ } else if (isCMN(LHS, CC, DAG)) {
CompareType = ARMISD::CMN;
LHS = LHS.getOperand(1);
CondCode = IntCCToARMCC(ISD::getSetCCSwappedOperands(CC));
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index c74c84a2602b1..b003fea50795d 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -5140,12 +5140,8 @@ def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
(CMNri GPR:$src, mod_imm_neg:$imm)>;
def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
(CMNri GPR:$src, mod_imm_neg:$imm)>;
-def : ARMPat<(ARMcmpZ GPR:$src, (ineg GPR:$rhs)),
- (CMNrr GPR:$src, GPR:$rhs)>;
def : ARMPat<(ARMcmpZ GPR:$src, (ineg so_reg_imm:$rhs)),
(CMNrsi GPR:$src, so_reg_imm:$rhs)>;
-def : ARMPat<(ARMcmpZ GPRnopc:$src, (ineg so_reg_reg:$rhs)),
- (CMNrsr GPRnopc:$src, so_reg_reg:$rhs)>;
// Note that TST/TEQ don't set all the same flags that CMP does!
defm TST : AI1_cmp_irs<0b1000, "tst",
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 4f0cea8b00aac..35aa5babbe7a3 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -3551,12 +3551,6 @@ def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
(t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
-// Fold compare-to-zero of a negated register into CMN register forms.
-def : T2Pat<(ARMcmpZ GPRnopc:$Rn, (ineg rGPR:$Rm)),
- (t2CMNrr GPRnopc:$Rn, rGPR:$Rm)>;
-def : T2Pat<(ARMcmpZ GPRnopc:$Rn, (ineg t2_so_reg:$ShiftedRm)),
- (t2CMNrs GPRnopc:$Rn, t2_so_reg:$ShiftedRm)>;
-
defm t2TST : T2I_cmp_irs<0b0000, "tst", rGPR,
IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-cmn.ll b/llvm/test/CodeGen/Thumb2/thumb2-cmn.ll
index 868ca733318a9..4c58270b4df24 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-cmn.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-cmn.ll
@@ -1,75 +1,126 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
; These tests could be improved by 'movs r0, #0' being rematerialized below the
; test as 'mov.w r0, #0'.
define i32 @f1(i32 %a, i32 %b) {
+; CHECK-LABEL: f1:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r2, #24
+; CHECK-NEXT: cmn r0, r1
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r2, #42
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
%nb = sub i32 0, %b
%tmp = icmp ne i32 %a, %nb
%ret = select i1 %tmp, i32 42, i32 24
ret i32 %ret
}
-; CHECK-LABEL: f1:
-; CHECK: cmn {{.*}}, r1
define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r2, #24
+; CHECK-NEXT: cmn r1, r0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r2, #42
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
%nb = sub i32 0, %b
%tmp = icmp ne i32 %nb, %a
%ret = select i1 %tmp, i32 42, i32 24
ret i32 %ret
}
-; CHECK-LABEL: f2:
-; CHECK: cmn {{.*}}, r1
define i32 @f3(i32 %a, i32 %b) {
+; CHECK-LABEL: f3:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r2, #24
+; CHECK-NEXT: cmn r0, r1
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq r2, #42
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
%nb = sub i32 0, %b
%tmp = icmp eq i32 %a, %nb
%ret = select i1 %tmp, i32 42, i32 24
ret i32 %ret
}
-; CHECK-LABEL: f3:
-; CHECK: cmn {{.*}}, r1
define i32 @f4(i32 %a, i32 %b) {
+; CHECK-LABEL: f4:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r2, #24
+; CHECK-NEXT: cmn r1, r0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq r2, #42
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
%nb = sub i32 0, %b
%tmp = icmp eq i32 %nb, %a
%ret = select i1 %tmp, i32 42, i32 24
ret i32 %ret
}
-; CHECK-LABEL: f4:
-; CHECK: cmn {{.*}}, r1
define i32 @f5(i32 %a, i32 %b) {
+; CHECK-LABEL: f5:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r2, #24
+; CHECK-NEXT: cmn.w r0, r1, lsl #5
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq r2, #42
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
%tmp = shl i32 %b, 5
%nb = sub i32 0, %tmp
%tmp1 = icmp eq i32 %nb, %a
%ret = select i1 %tmp1, i32 42, i32 24
ret i32 %ret
}
-; CHECK-LABEL: f5:
-; CHECK: cmn.w {{.*}}, r1, lsl #5
define i32 @f6(i32 %a, i32 %b) {
+; CHECK-LABEL: f6:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r2, #24
+; CHECK-NEXT: cmn.w r0, r1, lsr #6
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r2, #42
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
%tmp = lshr i32 %b, 6
%nb = sub i32 0, %tmp
%tmp1 = icmp ne i32 %nb, %a
%ret = select i1 %tmp1, i32 42, i32 24
ret i32 %ret
}
-; CHECK-LABEL: f6:
-; CHECK: cmn.w {{.*}}, r1, lsr #6
define i32 @f7(i32 %a, i32 %b) {
+; CHECK-LABEL: f7:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r2, #24
+; CHECK-NEXT: cmn.w r0, r1, asr #7
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq r2, #42
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
%tmp = ashr i32 %b, 7
%nb = sub i32 0, %tmp
%tmp1 = icmp eq i32 %a, %nb
%ret = select i1 %tmp1, i32 42, i32 24
ret i32 %ret
}
-; CHECK-LABEL: f7:
-; CHECK: cmn.w {{.*}}, r1, asr #7
define i32 @f8(i32 %a, i32 %b) {
+; CHECK-LABEL: f8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r1, #24
+; CHECK-NEXT: cmn.w r0, r0, ror #8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r1, #42
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: bx lr
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
%tmp = or i32 %l8, %r8
@@ -78,16 +129,16 @@ define i32 @f8(i32 %a, i32 %b) {
%ret = select i1 %tmp1, i32 42, i32 24
ret i32 %ret
}
-; CHECK-LABEL: f8:
-; CHECK: cmn.w {{.*}}, {{.*}}, ror #8
-
define void @f9(i32 %a, i32 %b) nounwind optsize {
+; CHECK-LABEL: f9:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @APP
+; CHECK-NEXT: cmn.w r0, r1
+; CHECK-NEXT: @NO_APP
+; CHECK-NEXT: bx lr
tail call void asm sideeffect "cmn.w r0, r1", ""() nounwind, !srcloc !0
ret void
}
!0 = !{i32 81}
-
-; CHECK-LABEL: f9:
-; CHECK: cmn.w r0, r1
``````````
</details>
https://github.com/llvm/llvm-project/pull/191915
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