[llvm] [RISCV] Remove codegen for vp_fadd, vp_fmul (PR #191842)

[Luke Lau via llvm-commits]

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@@ -21,28 +21,19 @@ define <vscale x 1 x double> @test1(<vscale x 1 x double> %a, <vscale x 1 x doub
 define <vscale x 1 x double> @test2(<vscale x 1 x double> %a, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; RV32-LABEL: test2:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    lui a1, %hi(.LCPI1_0)
-; RV32-NEXT:    fld fa5, %lo(.LCPI1_0)(a1)
-; RV32-NEXT:    lui a1, %hi(.LCPI1_1)
-; RV32-NEXT:    fld fa4, %lo(.LCPI1_1)(a1)
-; RV32-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT:    vfmul.vf v9, v8, fa5, v0.t
+; RV32-NEXT:    lui a0, %hi(.LCPI1_0)
+; RV32-NEXT:    fld fa5, %lo(.LCPI1_0)(a0)
 ; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
-; RV32-NEXT:    vfmadd.vf v8, fa4, v9
+; RV32-NEXT:    vfmul.vf v8, v8, fa5
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test2:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    li a1, 1
-; RV64-NEXT:    slli a1, a1, 62
-; RV64-NEXT:    fmv.d.x fa5, a1
-; RV64-NEXT:    li a1, 1025
-; RV64-NEXT:    slli a1, a1, 52
-; RV64-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT:    vfmul.vf v9, v8, fa5, v0.t
-; RV64-NEXT:    fmv.d.x fa5, a1
+; RV64-NEXT:    lui a0, 2051
+; RV64-NEXT:    slli a0, a0, 39
+; RV64-NEXT:    fmv.d.x fa5, a0
 ; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
-; RV64-NEXT:    vfmadd.vf v8, fa5, v9
+; RV64-NEXT:    vfmul.vf v8, v8, fa5
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lukel97 wrote:

Here's a combine we were missing on the equivalent vp nodes, `a * 4 + (a * 2) -> a * 6`

https://github.com/llvm/llvm-project/pull/191842