[llvm] [RISCV] Remove codegen for vp_bitreverse, vp_bswap (PR #191643)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 13 08:47:20 PDT 2026
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/191643
>From 1ed3d524f064c8467cc7978ef14ea7531905fd0e Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Sun, 12 Apr 2026 00:31:27 +0800
Subject: [PATCH] [RISCV] Remove codegen for vp_bitreverse, vp_bswap
Part of the work to remove trivial VP intrinsics from the RISC-V backend, see https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off 2 intrinsics from #179622.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 +-
.../Target/RISCV/RISCVTargetTransformInfo.h | 2 -
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll | 3444 ++++++++---------
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll | 1720 ++++----
.../RISCV/rvv/fixed-vectors-bitreverse-vp.ll | 2958 +++++++-------
.../RISCV/rvv/fixed-vectors-bswap-vp.ll | 1441 +++----
6 files changed, 4424 insertions(+), 5151 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ce8cd0f6f5776..755aa536da285 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1087,17 +1087,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.hasStdExtZvkb()) {
setOperationAction(ISD::BSWAP, VT, Legal);
- setOperationAction(ISD::VP_BSWAP, VT, Custom);
} else {
- setOperationAction({ISD::BSWAP, ISD::VP_BSWAP}, VT, Expand);
+ setOperationAction(ISD::BSWAP, VT, Expand);
setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand);
}
if (Subtarget.hasStdExtZvbb()) {
setOperationAction(ISD::BITREVERSE, VT, Legal);
- setOperationAction(ISD::VP_BITREVERSE, VT, Custom);
} else {
- setOperationAction({ISD::BITREVERSE, ISD::VP_BITREVERSE}, VT, Expand);
+ setOperationAction(ISD::BITREVERSE, VT, Expand);
setOperationAction({ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}, VT, Expand);
// Lower CTLZ_ZERO_UNDEF and CTTZ_ZERO_UNDEF if element of VT in the
@@ -7555,12 +7553,10 @@ static unsigned getRISCVVLOp(SDValue Op) {
VP_CASE(UMIN) // VP_UMIN
VP_CASE(UMAX) // VP_UMAX
VP_CASE(SETCC) // VP_SETCC
- VP_CASE(BITREVERSE) // VP_BITREVERSE
VP_CASE(SADDSAT) // VP_SADDSAT
VP_CASE(UADDSAT) // VP_UADDSAT
VP_CASE(SSUBSAT) // VP_SSUBSAT
VP_CASE(USUBSAT) // VP_USUBSAT
- VP_CASE(BSWAP) // VP_BSWAP
case ISD::CTLZ_ZERO_UNDEF:
return RISCVISD::CTLZ_VL;
case ISD::CTTZ_ZERO_UNDEF:
@@ -8991,8 +8987,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_SMAX:
case ISD::VP_UMIN:
case ISD::VP_UMAX:
- case ISD::VP_BITREVERSE:
- case ISD::VP_BSWAP:
return lowerVPOp(Op, DAG);
case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
return lowerVPStridedLoad(Op, DAG);
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index c582a678ecb16..7385ef99c2628 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -373,8 +373,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_add,
Intrinsic::vp_and,
Intrinsic::vp_ashr,
- Intrinsic::vp_bitreverse,
- Intrinsic::vp_bswap,
Intrinsic::vp_cttz_elts,
Intrinsic::vp_fadd,
Intrinsic::vp_fcmp,
diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
index 09b8fdbf11d26..710a781c939f1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
@@ -11,30 +11,28 @@
define <vscale x 1 x i8> @vp_bitreverse_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsll.vi v9, v8, 4
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i8:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.bitreverse.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -43,12 +41,10 @@ define <vscale x 1 x i8> @vp_bitreverse_nxv1i8(<vscale x 1 x i8> %va, <vscale x
define <vscale x 1 x i8> @vp_bitreverse_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv1i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsll.vi v9, v8, 4
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4
-; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: vsrl.vi v9, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
@@ -65,7 +61,7 @@ define <vscale x 1 x i8> @vp_bitreverse_nxv1i8_unmasked(<vscale x 1 x i8> %va, i
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i8_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.bitreverse.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -75,30 +71,28 @@ define <vscale x 1 x i8> @vp_bitreverse_nxv1i8_unmasked(<vscale x 1 x i8> %va, i
define <vscale x 2 x i8> @vp_bitreverse_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsll.vi v9, v8, 4
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i8:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.bitreverse.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
@@ -107,12 +101,10 @@ define <vscale x 2 x i8> @vp_bitreverse_nxv2i8(<vscale x 2 x i8> %va, <vscale x
define <vscale x 2 x i8> @vp_bitreverse_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsll.vi v9, v8, 4
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4
-; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: vsrl.vi v9, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
@@ -129,7 +121,7 @@ define <vscale x 2 x i8> @vp_bitreverse_nxv2i8_unmasked(<vscale x 2 x i8> %va, i
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i8_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.bitreverse.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -139,30 +131,28 @@ define <vscale x 2 x i8> @vp_bitreverse_nxv2i8_unmasked(<vscale x 2 x i8> %va, i
define <vscale x 4 x i8> @vp_bitreverse_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsll.vi v9, v8, 4
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i8:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.bitreverse.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -171,12 +161,10 @@ define <vscale x 4 x i8> @vp_bitreverse_nxv4i8(<vscale x 4 x i8> %va, <vscale x
define <vscale x 4 x i8> @vp_bitreverse_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsll.vi v9, v8, 4
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4
-; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: vsrl.vi v9, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
@@ -193,7 +181,7 @@ define <vscale x 4 x i8> @vp_bitreverse_nxv4i8_unmasked(<vscale x 4 x i8> %va, i
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i8_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.bitreverse.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -203,30 +191,28 @@ define <vscale x 4 x i8> @vp_bitreverse_nxv4i8_unmasked(<vscale x 4 x i8> %va, i
define <vscale x 8 x i8> @vp_bitreverse_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsll.vi v9, v8, 4
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i8:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.bitreverse.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
@@ -235,12 +221,10 @@ define <vscale x 8 x i8> @vp_bitreverse_nxv8i8(<vscale x 8 x i8> %va, <vscale x
define <vscale x 8 x i8> @vp_bitreverse_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsll.vi v9, v8, 4
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4
-; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: vsrl.vi v9, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
@@ -257,7 +241,7 @@ define <vscale x 8 x i8> @vp_bitreverse_nxv8i8_unmasked(<vscale x 8 x i8> %va, i
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i8_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.bitreverse.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -267,30 +251,28 @@ define <vscale x 8 x i8> @vp_bitreverse_nxv8i8_unmasked(<vscale x 8 x i8> %va, i
define <vscale x 16 x i8> @vp_bitreverse_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vand.vi v10, v8, 15, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsll.vi v10, v8, 4
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v10, v10, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: vsrl.vi v10, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v10, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i8:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.bitreverse.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v
@@ -299,12 +281,10 @@ define <vscale x 16 x i8> @vp_bitreverse_nxv16i8(<vscale x 16 x i8> %va, <vscale
define <vscale x 16 x i8> @vp_bitreverse_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vand.vi v10, v8, 15
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsll.vi v10, v8, 4
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v10, v10, 4
-; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: vsrl.vi v10, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
@@ -321,7 +301,7 @@ define <vscale x 16 x i8> @vp_bitreverse_nxv16i8_unmasked(<vscale x 16 x i8> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i8_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.bitreverse.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -331,30 +311,28 @@ define <vscale x 16 x i8> @vp_bitreverse_nxv16i8_unmasked(<vscale x 16 x i8> %va
define <vscale x 32 x i8> @vp_bitreverse_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vand.vi v12, v8, 15, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vsll.vi v12, v8, 4
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v12, v12, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: vsrl.vi v12, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v12, v8
+; CHECK-NEXT: vsrl.vi v12, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v12, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv32i8:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.bitreverse.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v
@@ -363,12 +341,10 @@ define <vscale x 32 x i8> @vp_bitreverse_nxv32i8(<vscale x 32 x i8> %va, <vscale
define <vscale x 32 x i8> @vp_bitreverse_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv32i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vand.vi v12, v8, 15
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vsll.vi v12, v8, 4
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v12, v12, 4
-; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: vsrl.vi v12, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
@@ -385,7 +361,7 @@ define <vscale x 32 x i8> @vp_bitreverse_nxv32i8_unmasked(<vscale x 32 x i8> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv32i8_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.bitreverse.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -395,30 +371,28 @@ define <vscale x 32 x i8> @vp_bitreverse_nxv32i8_unmasked(<vscale x 32 x i8> %va
define <vscale x 64 x i8> @vp_bitreverse_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv64i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vand.vi v16, v8, 15, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsll.vi v16, v8, 4
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v8, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v16
+; CHECK-NEXT: vsrl.vi v16, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v16, v8
+; CHECK-NEXT: vsrl.vi v16, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v16, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i8:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.bitreverse.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v
@@ -427,12 +401,10 @@ define <vscale x 64 x i8> @vp_bitreverse_nxv64i8(<vscale x 64 x i8> %va, <vscale
define <vscale x 64 x i8> @vp_bitreverse_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv64i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vand.vi v16, v8, 15
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsll.vi v16, v8, 4
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v16, v16, 4
-; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsrl.vi v16, v8, 2
; CHECK-NEXT: vand.vx v8, v8, a0
@@ -449,7 +421,7 @@ define <vscale x 64 x i8> @vp_bitreverse_nxv64i8_unmasked(<vscale x 64 x i8> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i8_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.bitreverse.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> splat (i1 true), i32 %evl)
@@ -459,37 +431,37 @@ define <vscale x 64 x i8> @vp_bitreverse_nxv64i8_unmasked(<vscale x 64 x i8> %va
define <vscale x 1 x i16> @vp_bitreverse_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.bitreverse.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -498,7 +470,7 @@ define <vscale x 1 x i16> @vp_bitreverse_nxv1i16(<vscale x 1 x i16> %va, <vscale
define <vscale x 1 x i16> @vp_bitreverse_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
@@ -527,7 +499,7 @@ define <vscale x 1 x i16> @vp_bitreverse_nxv1i16_unmasked(<vscale x 1 x i16> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i16_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.bitreverse.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -537,37 +509,37 @@ define <vscale x 1 x i16> @vp_bitreverse_nxv1i16_unmasked(<vscale x 1 x i16> %va
define <vscale x 2 x i16> @vp_bitreverse_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.bitreverse.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -576,7 +548,7 @@ define <vscale x 2 x i16> @vp_bitreverse_nxv2i16(<vscale x 2 x i16> %va, <vscale
define <vscale x 2 x i16> @vp_bitreverse_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
@@ -605,7 +577,7 @@ define <vscale x 2 x i16> @vp_bitreverse_nxv2i16_unmasked(<vscale x 2 x i16> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i16_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.bitreverse.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -615,37 +587,37 @@ define <vscale x 2 x i16> @vp_bitreverse_nxv2i16_unmasked(<vscale x 2 x i16> %va
define <vscale x 4 x i16> @vp_bitreverse_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.bitreverse.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -654,7 +626,7 @@ define <vscale x 4 x i16> @vp_bitreverse_nxv4i16(<vscale x 4 x i16> %va, <vscale
define <vscale x 4 x i16> @vp_bitreverse_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
@@ -683,7 +655,7 @@ define <vscale x 4 x i16> @vp_bitreverse_nxv4i16_unmasked(<vscale x 4 x i16> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i16_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.bitreverse.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -693,37 +665,37 @@ define <vscale x 4 x i16> @vp_bitreverse_nxv4i16_unmasked(<vscale x 4 x i16> %va
define <vscale x 8 x i16> @vp_bitreverse_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsrl.vi v10, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsrl.vi v10, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v10, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.bitreverse.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -732,7 +704,7 @@ define <vscale x 8 x i16> @vp_bitreverse_nxv8i16(<vscale x 8 x i16> %va, <vscale
define <vscale x 8 x i16> @vp_bitreverse_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
@@ -761,7 +733,7 @@ define <vscale x 8 x i16> @vp_bitreverse_nxv8i16_unmasked(<vscale x 8 x i16> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i16_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.bitreverse.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -771,37 +743,37 @@ define <vscale x 8 x i16> @vp_bitreverse_nxv8i16_unmasked(<vscale x 8 x i16> %va
define <vscale x 16 x i16> @vp_bitreverse_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vsrl.vi v12, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsrl.vi v12, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v12, v8
+; CHECK-NEXT: vsrl.vi v12, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v12, v8
+; CHECK-NEXT: vsrl.vi v12, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v12, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.bitreverse.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -810,7 +782,7 @@ define <vscale x 16 x i16> @vp_bitreverse_nxv16i16(<vscale x 16 x i16> %va, <vsc
define <vscale x 16 x i16> @vp_bitreverse_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
@@ -839,7 +811,7 @@ define <vscale x 16 x i16> @vp_bitreverse_nxv16i16_unmasked(<vscale x 16 x i16>
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i16_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.bitreverse.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -849,37 +821,37 @@ define <vscale x 16 x i16> @vp_bitreverse_nxv16i16_unmasked(<vscale x 16 x i16>
define <vscale x 32 x i16> @vp_bitreverse_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v16, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v8, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vsrl.vi v16, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v8, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v16, v8
+; CHECK-NEXT: vsrl.vi v16, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v16, v8
+; CHECK-NEXT: vsrl.vi v16, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v16, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv32i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.bitreverse.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -888,7 +860,7 @@ define <vscale x 32 x i16> @vp_bitreverse_nxv32i16(<vscale x 32 x i16> %va, <vsc
define <vscale x 32 x i16> @vp_bitreverse_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
@@ -917,7 +889,7 @@ define <vscale x 32 x i16> @vp_bitreverse_nxv32i16_unmasked(<vscale x 32 x i16>
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv32i16_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.bitreverse.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -927,45 +899,45 @@ define <vscale x 32 x i16> @vp_bitreverse_nxv32i16_unmasked(<vscale x 32 x i16>
define <vscale x 1 x i32> @vp_bitreverse_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vor.vv v9, v9, v10
+; CHECK-NEXT: vsll.vi v10, v8, 24
+; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i32:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.bitreverse.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -974,7 +946,7 @@ define <vscale x 1 x i32> @vp_bitreverse_nxv1i32(<vscale x 1 x i32> %va, <vscale
define <vscale x 1 x i32> @vp_bitreverse_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v10, v8, 24
@@ -1011,7 +983,7 @@ define <vscale x 1 x i32> @vp_bitreverse_nxv1i32_unmasked(<vscale x 1 x i32> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i32_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.bitreverse.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1021,45 +993,45 @@ define <vscale x 1 x i32> @vp_bitreverse_nxv1i32_unmasked(<vscale x 1 x i32> %va
define <vscale x 2 x i32> @vp_bitreverse_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vor.vv v9, v9, v10
+; CHECK-NEXT: vsll.vi v10, v8, 24
+; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i32:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.bitreverse.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -1068,7 +1040,7 @@ define <vscale x 2 x i32> @vp_bitreverse_nxv2i32(<vscale x 2 x i32> %va, <vscale
define <vscale x 2 x i32> @vp_bitreverse_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v10, v8, 24
@@ -1105,7 +1077,7 @@ define <vscale x 2 x i32> @vp_bitreverse_nxv2i32_unmasked(<vscale x 2 x i32> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i32_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.bitreverse.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1115,45 +1087,45 @@ define <vscale x 2 x i32> @vp_bitreverse_nxv2i32_unmasked(<vscale x 2 x i32> %va
define <vscale x 4 x i32> @vp_bitreverse_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v12, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v10, v10, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0
+; CHECK-NEXT: vor.vv v10, v10, v12
+; CHECK-NEXT: vsll.vi v12, v8, 24
+; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v12, v8
+; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: vsrl.vi v10, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v10, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i32:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.bitreverse.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -1162,7 +1134,7 @@ define <vscale x 4 x i32> @vp_bitreverse_nxv4i32(<vscale x 4 x i32> %va, <vscale
define <vscale x 4 x i32> @vp_bitreverse_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v12, v8, 24
@@ -1199,7 +1171,7 @@ define <vscale x 4 x i32> @vp_bitreverse_nxv4i32_unmasked(<vscale x 4 x i32> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i32_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.bitreverse.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -1209,45 +1181,45 @@ define <vscale x 4 x i32> @vp_bitreverse_nxv4i32_unmasked(<vscale x 4 x i32> %va
define <vscale x 8 x i32> @vp_bitreverse_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v16, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v12, v12, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0
+; CHECK-NEXT: vor.vv v12, v12, v16
+; CHECK-NEXT: vsll.vi v16, v8, 24
+; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v16, v8
+; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: vsrl.vi v12, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v12, v8
+; CHECK-NEXT: vsrl.vi v12, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v12, v8
+; CHECK-NEXT: vsrl.vi v12, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v12, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i32:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.bitreverse.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -1256,7 +1228,7 @@ define <vscale x 8 x i32> @vp_bitreverse_nxv8i32(<vscale x 8 x i32> %va, <vscale
define <vscale x 8 x i32> @vp_bitreverse_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v16, v8, 24
@@ -1293,7 +1265,7 @@ define <vscale x 8 x i32> @vp_bitreverse_nxv8i32_unmasked(<vscale x 8 x i32> %va
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i32_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.bitreverse.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1303,45 +1275,45 @@ define <vscale x 8 x i32> @vp_bitreverse_nxv8i32_unmasked(<vscale x 8 x i32> %va
define <vscale x 16 x i32> @vp_bitreverse_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v24, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
-; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: vor.vv v16, v16, v24
+; CHECK-NEXT: vsll.vi v24, v8, 24
+; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v24, v24, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
-; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v8, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vor.vv v8, v8, v16
+; CHECK-NEXT: vsrl.vi v16, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v8, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v16, v8
+; CHECK-NEXT: vsrl.vi v16, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v16, v8
+; CHECK-NEXT: vsrl.vi v16, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v16, v8
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i32:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.bitreverse.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -1350,7 +1322,7 @@ define <vscale x 16 x i32> @vp_bitreverse_nxv16i32(<vscale x 16 x i32> %va, <vsc
define <vscale x 16 x i32> @vp_bitreverse_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v24, v8, 24
@@ -1387,7 +1359,7 @@ define <vscale x 16 x i32> @vp_bitreverse_nxv16i32_unmasked(<vscale x 16 x i32>
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i32_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.bitreverse.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -1399,136 +1371,136 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64(<vscale x 1 x i64> %va, <vscale
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
+; RV32-NEXT: lui a3, 16
+; RV32-NEXT: vsetvli a4, zero, e64, m1, ta, ma
+; RV32-NEXT: vsrl.vi v9, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vlse64.v v9, (a6), zero
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: vsll.vx v10, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v11, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v11, v11, a2, v0.t
-; RV32-NEXT: vor.vv v10, v10, v11, v0.t
-; RV32-NEXT: vand.vx v11, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v11, v11, 24, v0.t
-; RV32-NEXT: vand.vv v12, v8, v9, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV32-NEXT: vor.vv v11, v11, v12, v0.t
-; RV32-NEXT: vor.vv v10, v10, v11, v0.t
-; RV32-NEXT: vsrl.vx v11, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v10, v8, a1
+; RV32-NEXT: vsrl.vx v11, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v12, v8, a1
+; RV32-NEXT: vand.vx v11, v11, a0
+; RV32-NEXT: vlse64.v v13, (a5), zero
+; RV32-NEXT: vor.vv v10, v11, v10
+; RV32-NEXT: vand.vx v11, v8, a0
+; RV32-NEXT: vsll.vx v11, v11, a2
+; RV32-NEXT: vor.vv v11, v12, v11
+; RV32-NEXT: vsrl.vi v12, v8, 8
+; RV32-NEXT: vand.vx v9, v9, a4
+; RV32-NEXT: vand.vv v12, v12, v13
+; RV32-NEXT: vor.vv v9, v12, v9
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vand.vv v12, v8, v13
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v12, v12, a5, v0.t
-; RV32-NEXT: vor.vv v11, v12, v11, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
-; RV32-NEXT: vand.vx v12, v12, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v9, a4
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v12, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v11, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vor.vv v9, v9, v10
+; RV32-NEXT: vsetvli a3, zero, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; RV32-NEXT: vsll.vi v12, v12, 8
+; RV32-NEXT: vor.vv v8, v8, v12
+; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; RV32-NEXT: vor.vv v8, v11, v8
+; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v11, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
-; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t
-; RV32-NEXT: vand.vv v10, v10, v9, v0.t
-; RV32-NEXT: vand.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
-; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
-; RV32-NEXT: vand.vv v9, v9, v12, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v9, v8, v0.t
-; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
-; RV32-NEXT: vand.vv v9, v9, v11, v0.t
-; RV32-NEXT: vand.vv v8, v8, v11, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v9, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v9
+; RV32-NEXT: vsrl.vi v9, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v10
+; RV32-NEXT: vand.vv v9, v9, v10
+; RV32-NEXT: vsll.vi v8, v8, 4
+; RV32-NEXT: vor.vv v8, v9, v8
+; RV32-NEXT: vsrl.vi v9, v8, 2
+; RV32-NEXT: vand.vv v8, v8, v12
+; RV32-NEXT: vand.vv v9, v9, v12
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vor.vv v8, v9, v8
+; RV32-NEXT: vsrl.vi v9, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v11
+; RV32-NEXT: vand.vv v9, v9, v11
+; RV32-NEXT: vadd.vv v8, v8, v8
+; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bitreverse_nxv1i64:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v9, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
-; RV64-NEXT: vand.vx v10, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
-; RV64-NEXT: vor.vv v9, v9, v10, v0.t
-; RV64-NEXT: vsll.vx v10, v8, a2, v0.t
-; RV64-NEXT: vand.vx v11, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v11, v11, a7, v0.t
-; RV64-NEXT: vor.vv v10, v10, v11, v0.t
-; RV64-NEXT: vor.vv v9, v10, v9, v0.t
-; RV64-NEXT: vsrl.vx v10, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v11, v8, a7, v0.t
-; RV64-NEXT: vand.vx v11, v11, a0, v0.t
-; RV64-NEXT: vor.vv v10, v11, v10, v0.t
-; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t
-; RV64-NEXT: vand.vx v11, v11, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vor.vv v8, v8, v11, v0.t
-; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
-; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
-; RV64-NEXT: vand.vx v9, v9, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
-; RV64-NEXT: vsrl.vi v9, v8, 2, v0.t
-; RV64-NEXT: vand.vx v9, v9, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
-; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t
-; RV64-NEXT: vand.vx v9, v9, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m1, ta, ma
+; RV64-NEXT: vsrl.vi v9, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v10, v8, a1
+; RV64-NEXT: vsrl.vx v11, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v11, v11, a2
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsrl.vi v11, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v9, v9, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v11, v11, a4
+; RV64-NEXT: vor.vv v9, v11, v9
+; RV64-NEXT: vand.vx v11, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v9, v9, v10
+; RV64-NEXT: vand.vx v10, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v11, v11, 24
+; RV64-NEXT: vsll.vi v10, v10, 8
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsll.vx v11, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v11, v8
+; RV64-NEXT: vor.vv v8, v8, v10
+; RV64-NEXT: vor.vv v8, v8, v9
+; RV64-NEXT: vsrl.vi v9, v8, 4
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v9, v9, a2
+; RV64-NEXT: vsll.vi v8, v8, 4
+; RV64-NEXT: vor.vv v8, v9, v8
+; RV64-NEXT: vsrl.vi v9, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v9, v9, a0
+; RV64-NEXT: vsll.vi v8, v8, 2
+; RV64-NEXT: vor.vv v8, v9, v8
+; RV64-NEXT: vsrl.vi v9, v8, 1
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v9, v9, a1
+; RV64-NEXT: vadd.vv v8, v8, v8
+; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i64:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.bitreverse.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
@@ -1539,66 +1511,66 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64_unmasked(<vscale x 1 x i64> %va
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a4, zero, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v10, v8, a2
-; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: vsrl.vx v11, v8, a2
-; RV32-NEXT: vsrl.vx v12, v8, a4
-; RV32-NEXT: vand.vx v13, v8, a1
-; RV32-NEXT: vand.vx v12, v12, a1
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v12, v8, a1
+; RV32-NEXT: vand.vx v11, v11, a0
+; RV32-NEXT: vlse64.v v13, (a5), zero
+; RV32-NEXT: vor.vv v10, v11, v10
+; RV32-NEXT: vand.vx v11, v8, a0
+; RV32-NEXT: vsll.vx v11, v11, a2
; RV32-NEXT: vor.vv v11, v12, v11
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: vsll.vx v13, v13, a4
-; RV32-NEXT: vor.vv v10, v10, v13
-; RV32-NEXT: vsrl.vi v13, v8, 8
-; RV32-NEXT: vand.vx v9, v9, a5
-; RV32-NEXT: vand.vv v13, v13, v12
-; RV32-NEXT: vor.vv v9, v13, v9
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vand.vv v12, v8, v12
-; RV32-NEXT: vand.vx v8, v8, a5
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vsrl.vi v12, v8, 8
+; RV32-NEXT: vand.vx v9, v9, a4
+; RV32-NEXT: vand.vv v12, v12, v13
+; RV32-NEXT: vor.vv v9, v12, v9
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vand.vv v12, v8, v13
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vor.vv v9, v9, v10
+; RV32-NEXT: vsetvli a3, zero, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vor.vv v8, v8, v12
-; RV32-NEXT: vsetvli a4, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v12, a1
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v9, v9, v11
-; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; RV32-NEXT: vor.vv v8, v11, v8
+; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v11, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v8, v10, v8
-; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v10, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vsrl.vi v9, v8, 4
-; RV32-NEXT: vand.vv v8, v8, v12
-; RV32-NEXT: vand.vv v9, v9, v12
+; RV32-NEXT: vand.vv v8, v8, v10
+; RV32-NEXT: vand.vv v9, v9, v10
; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: vsrl.vi v9, v8, 2
-; RV32-NEXT: vand.vv v8, v8, v11
-; RV32-NEXT: vand.vv v9, v9, v11
+; RV32-NEXT: vand.vv v8, v8, v12
+; RV32-NEXT: vand.vv v9, v9, v12
; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: vsrl.vi v9, v8, 1
-; RV32-NEXT: vand.vv v8, v8, v10
-; RV32-NEXT: vand.vv v9, v9, v10
+; RV32-NEXT: vand.vv v8, v8, v11
+; RV32-NEXT: vand.vv v9, v9, v11
; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16
@@ -1607,67 +1579,67 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64_unmasked(<vscale x 1 x i64> %va
;
; RV64-LABEL: vp_bitreverse_nxv1i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 24
-; RV64-NEXT: vsrl.vi v10, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v11, v8, a3
-; RV64-NEXT: vsrl.vx v12, v8, a5
-; RV64-NEXT: vand.vx v12, v12, a0
-; RV64-NEXT: vor.vv v11, v12, v11
-; RV64-NEXT: vand.vx v12, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v9, v9, a1
-; RV64-NEXT: vsll.vi v12, v12, 24
-; RV64-NEXT: vand.vx v10, v10, a2
-; RV64-NEXT: vor.vv v9, v10, v9
-; RV64-NEXT: vand.vx v10, v8, a2
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v10, v8, a1
+; RV64-NEXT: vsrl.vx v11, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v11, v11, a2
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsrl.vi v11, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v9, v9, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v11, v11, a4
+; RV64-NEXT: vor.vv v9, v11, v9
+; RV64-NEXT: vand.vx v11, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v9, v9, v10
+; RV64-NEXT: vand.vx v10, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v11, v11, 24
; RV64-NEXT: vsll.vi v10, v10, 8
-; RV64-NEXT: vor.vv v10, v12, v10
-; RV64-NEXT: vsll.vx v12, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v12, v8
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: vor.vv v9, v9, v11
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsll.vx v11, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v11, v8
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v9, v9, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v9, v9, a2
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: vsrl.vi v9, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vand.vx v9, v9, a1
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: vsrl.vi v9, v8, 1
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vand.vx v9, v9, a2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i64_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.bitreverse.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -1679,136 +1651,136 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64(<vscale x 2 x i64> %va, <vscale
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
+; RV32-NEXT: lui a3, 16
+; RV32-NEXT: vsetvli a4, zero, e64, m2, ta, ma
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vlse64.v v10, (a6), zero
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: vsll.vx v12, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v14, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v14, v14, a2, v0.t
-; RV32-NEXT: vor.vv v12, v12, v14, v0.t
-; RV32-NEXT: vand.vx v14, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v14, v14, 24, v0.t
-; RV32-NEXT: vand.vv v16, v8, v10, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v14, v14, v16, v0.t
-; RV32-NEXT: vor.vv v12, v12, v14, v0.t
-; RV32-NEXT: vsrl.vx v14, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v10, v8, a1
+; RV32-NEXT: vsrl.vx v12, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v18, v8, a1
+; RV32-NEXT: vand.vx v12, v12, a0
+; RV32-NEXT: vlse64.v v14, (a5), zero
+; RV32-NEXT: vor.vv v12, v12, v10
+; RV32-NEXT: vand.vx v10, v8, a0
+; RV32-NEXT: vsll.vx v10, v10, a2
+; RV32-NEXT: vor.vv v10, v18, v10
+; RV32-NEXT: vsrl.vi v18, v8, 8
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vand.vv v18, v18, v14
+; RV32-NEXT: vor.vv v16, v18, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vand.vv v14, v8, v14
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v16, v16, a5, v0.t
-; RV32-NEXT: vor.vv v14, v16, v14, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV32-NEXT: vand.vx v16, v16, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v10, a4
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v14, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v14, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
-; RV32-NEXT: vand.vv v12, v12, v10, v0.t
-; RV32-NEXT: vand.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
-; RV32-NEXT: vand.vv v10, v10, v16, v0.t
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
-; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
-; RV32-NEXT: vand.vv v10, v10, v14, v0.t
-; RV32-NEXT: vand.vv v8, v8, v14, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vor.vv v12, v16, v12
+; RV32-NEXT: vsetvli a3, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vsll.vi v14, v14, 8
+; RV32-NEXT: vor.vv v8, v8, v14
+; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.x v14, a1
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vor.vv v8, v10, v8
+; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.x v10, a2
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v12
+; RV32-NEXT: vsrl.vi v12, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: vand.vv v12, v12, v16
+; RV32-NEXT: vsll.vi v8, v8, 4
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vsrl.vi v12, v8, 2
+; RV32-NEXT: vand.vv v8, v8, v14
+; RV32-NEXT: vand.vv v12, v12, v14
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vsrl.vi v12, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v10
+; RV32-NEXT: vand.vv v10, v12, v10
+; RV32-NEXT: vadd.vv v8, v8, v8
+; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bitreverse_nxv2i64:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vand.vx v10, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV64-NEXT: vand.vx v12, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV64-NEXT: vor.vv v10, v10, v12, v0.t
-; RV64-NEXT: vsll.vx v12, v8, a2, v0.t
-; RV64-NEXT: vand.vx v14, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v14, v14, a7, v0.t
-; RV64-NEXT: vor.vv v12, v12, v14, v0.t
-; RV64-NEXT: vor.vv v10, v12, v10, v0.t
-; RV64-NEXT: vsrl.vx v12, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v14, v8, a7, v0.t
-; RV64-NEXT: vand.vx v14, v14, a0, v0.t
-; RV64-NEXT: vor.vv v12, v14, v12, v0.t
-; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t
-; RV64-NEXT: vand.vx v14, v14, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vor.vv v8, v8, v14, v0.t
-; RV64-NEXT: vor.vv v8, v8, v12, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
-; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
-; RV64-NEXT: vand.vx v10, v10, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
-; RV64-NEXT: vsrl.vi v10, v8, 2, v0.t
-; RV64-NEXT: vand.vx v10, v10, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
-; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t
-; RV64-NEXT: vand.vx v10, v10, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m2, ta, ma
+; RV64-NEXT: vsrl.vi v10, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a1
+; RV64-NEXT: vsrl.vx v14, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v14, v14, a2
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsrl.vi v14, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v10, v10, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v14, v14, a4
+; RV64-NEXT: vor.vv v10, v14, v10
+; RV64-NEXT: vand.vx v14, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v10, v10, v12
+; RV64-NEXT: vand.vx v12, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v14, v14, 24
+; RV64-NEXT: vsll.vi v12, v12, 8
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsll.vx v14, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v14, v8
+; RV64-NEXT: vor.vv v8, v8, v12
+; RV64-NEXT: vor.vv v8, v8, v10
+; RV64-NEXT: vsrl.vi v10, v8, 4
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v10, v10, a2
+; RV64-NEXT: vsll.vi v8, v8, 4
+; RV64-NEXT: vor.vv v8, v10, v8
+; RV64-NEXT: vsrl.vi v10, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v10, v10, a0
+; RV64-NEXT: vsll.vi v8, v8, 2
+; RV64-NEXT: vor.vv v8, v10, v8
+; RV64-NEXT: vsrl.vi v10, v8, 1
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v10, v10, a1
+; RV64-NEXT: vadd.vv v8, v8, v8
+; RV64-NEXT: vor.vv v8, v10, v8
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i64:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.bitreverse.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -1819,66 +1791,66 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64_unmasked(<vscale x 2 x i64> %va
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsrl.vi v14, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: vsetvli a4, zero, e64, m2, ta, ma
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v12, v8, a2
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vsrl.vx v10, v8, a2
-; RV32-NEXT: vsrl.vx v16, v8, a4
-; RV32-NEXT: vand.vx v18, v8, a1
-; RV32-NEXT: vand.vx v16, v16, a1
-; RV32-NEXT: vor.vv v10, v16, v10
-; RV32-NEXT: vlse64.v v16, (a6), zero
-; RV32-NEXT: vsll.vx v18, v18, a4
-; RV32-NEXT: vor.vv v12, v12, v18
+; RV32-NEXT: vsrl.vx v10, v8, a1
+; RV32-NEXT: vsrl.vx v12, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v18, v8, a1
+; RV32-NEXT: vand.vx v12, v12, a0
+; RV32-NEXT: vlse64.v v14, (a5), zero
+; RV32-NEXT: vor.vv v12, v12, v10
+; RV32-NEXT: vand.vx v10, v8, a0
+; RV32-NEXT: vsll.vx v10, v10, a2
+; RV32-NEXT: vor.vv v10, v18, v10
; RV32-NEXT: vsrl.vi v18, v8, 8
-; RV32-NEXT: vand.vx v14, v14, a5
-; RV32-NEXT: vand.vv v18, v18, v16
-; RV32-NEXT: vor.vv v14, v18, v14
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vand.vv v16, v8, v16
-; RV32-NEXT: vand.vx v8, v8, a5
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vand.vv v18, v18, v14
+; RV32-NEXT: vor.vv v16, v18, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vand.vv v14, v8, v14
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v16, v16, 8
-; RV32-NEXT: vor.vv v8, v8, v16
-; RV32-NEXT: vsetvli a4, zero, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v10, v14, v10
-; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v14, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v12, v8
-; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v12, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v10
-; RV32-NEXT: vsrl.vi v10, v8, 4
+; RV32-NEXT: vor.vv v12, v16, v12
+; RV32-NEXT: vsetvli a3, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vsll.vi v14, v14, 8
+; RV32-NEXT: vor.vv v8, v8, v14
+; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.x v14, a1
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vor.vv v8, v10, v8
+; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.x v10, a2
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v12
+; RV32-NEXT: vsrl.vi v12, v8, 4
; RV32-NEXT: vand.vv v8, v8, v16
-; RV32-NEXT: vand.vv v10, v10, v16
+; RV32-NEXT: vand.vv v12, v12, v16
; RV32-NEXT: vsll.vi v8, v8, 4
-; RV32-NEXT: vor.vv v8, v10, v8
-; RV32-NEXT: vsrl.vi v10, v8, 2
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vsrl.vi v12, v8, 2
; RV32-NEXT: vand.vv v8, v8, v14
-; RV32-NEXT: vand.vv v10, v10, v14
+; RV32-NEXT: vand.vv v12, v12, v14
; RV32-NEXT: vsll.vi v8, v8, 2
-; RV32-NEXT: vor.vv v8, v10, v8
-; RV32-NEXT: vsrl.vi v10, v8, 1
-; RV32-NEXT: vand.vv v8, v8, v12
-; RV32-NEXT: vand.vv v10, v10, v12
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vsrl.vi v12, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v10
+; RV32-NEXT: vand.vv v10, v12, v10
; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16
@@ -1887,67 +1859,67 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64_unmasked(<vscale x 2 x i64> %va
;
; RV64-LABEL: vp_bitreverse_nxv2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vsrl.vi v12, v8, 24
-; RV64-NEXT: vsrl.vi v14, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v10, v8, a3
-; RV64-NEXT: vsrl.vx v16, v8, a5
-; RV64-NEXT: vand.vx v16, v16, a0
-; RV64-NEXT: vor.vv v10, v16, v10
-; RV64-NEXT: vand.vx v16, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v12, v12, a1
-; RV64-NEXT: vsll.vi v16, v16, 24
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m2, ta, ma
+; RV64-NEXT: vsrl.vi v10, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a1
+; RV64-NEXT: vsrl.vx v14, v8, a0
+; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v14, v14, a2
; RV64-NEXT: vor.vv v12, v14, v12
-; RV64-NEXT: vand.vx v14, v8, a2
-; RV64-NEXT: vsll.vi v14, v14, 8
-; RV64-NEXT: vor.vv v14, v16, v14
-; RV64-NEXT: vsll.vx v16, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: vor.vv v10, v12, v10
-; RV64-NEXT: vor.vv v8, v8, v14
+; RV64-NEXT: vsrl.vi v14, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v10, v10, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v14, v14, a4
+; RV64-NEXT: vor.vv v10, v14, v10
+; RV64-NEXT: vand.vx v14, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v10, v10, v12
+; RV64-NEXT: vand.vx v12, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v14, v14, 24
+; RV64-NEXT: vsll.vi v12, v12, 8
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsll.vx v14, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v14, v8
+; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vsrl.vi v10, v8, 4
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v10, v10, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v10, v10, a2
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v10, v8
; RV64-NEXT: vsrl.vi v10, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vand.vx v10, v10, a1
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v10, v8
; RV64-NEXT: vsrl.vi v10, v8, 1
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vand.vx v10, v10, a2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v10, v10, a1
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vor.vv v8, v10, v8
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i64_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.bitreverse.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -1959,136 +1931,136 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64(<vscale x 4 x i64> %va, <vscale
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
+; RV32-NEXT: lui a3, 16
+; RV32-NEXT: vsetvli a4, zero, e64, m4, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: vsll.vx v16, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v20, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v20, v20, a2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vand.vx v20, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v20, v20, 24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v12, v0.t
-; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV32-NEXT: vor.vv v20, v20, v24, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vx v20, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v12, v8, a1
+; RV32-NEXT: vsrl.vx v16, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v28, v8, a1
+; RV32-NEXT: vand.vx v16, v16, a0
+; RV32-NEXT: vlse64.v v20, (a5), zero
+; RV32-NEXT: vor.vv v16, v16, v12
+; RV32-NEXT: vand.vx v12, v8, a0
+; RV32-NEXT: vsll.vx v12, v12, a2
+; RV32-NEXT: vor.vv v12, v28, v12
+; RV32-NEXT: vsrl.vi v28, v8, 8
+; RV32-NEXT: vand.vx v24, v24, a4
+; RV32-NEXT: vand.vv v28, v28, v20
+; RV32-NEXT: vor.vv v24, v28, v24
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vand.vv v20, v8, v20
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v24, v24, a5, v0.t
-; RV32-NEXT: vor.vv v20, v24, v20, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v28, a4
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v20, v8, v20, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vi v20, v16, 4, v0.t
-; RV32-NEXT: vand.vv v20, v20, v28, v0.t
-; RV32-NEXT: vand.vv v16, v16, v28, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 4, v0.t
-; RV32-NEXT: vor.vv v16, v20, v16, v0.t
-; RV32-NEXT: vsrl.vi v20, v16, 2, v0.t
-; RV32-NEXT: vand.vv v20, v20, v12, v0.t
-; RV32-NEXT: vand.vv v12, v16, v12, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 2, v0.t
-; RV32-NEXT: vor.vv v12, v20, v12, v0.t
-; RV32-NEXT: vsrl.vi v16, v12, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v8, v12, v8, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
-; RV32-NEXT: addi sp, sp, 16
-; RV32-NEXT: .cfi_def_cfa_offset 0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vp_bitreverse_nxv4i64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-NEXT: vand.vx v12, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV64-NEXT: vand.vx v16, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV64-NEXT: vor.vv v12, v12, v16, v0.t
-; RV64-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV64-NEXT: vand.vx v20, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v20, v20, a7, v0.t
-; RV64-NEXT: vor.vv v16, v16, v20, v0.t
-; RV64-NEXT: vor.vv v12, v16, v12, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v20, v8, a7, v0.t
-; RV64-NEXT: vand.vx v20, v20, a0, v0.t
-; RV64-NEXT: vor.vv v16, v20, v16, v0.t
-; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t
-; RV64-NEXT: vand.vx v20, v20, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vor.vv v8, v8, v20, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
-; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
-; RV64-NEXT: vand.vx v12, v12, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
-; RV64-NEXT: vsrl.vi v12, v8, 2, v0.t
-; RV64-NEXT: vand.vx v12, v12, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
-; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t
-; RV64-NEXT: vand.vx v12, v12, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
-; RV64-NEXT: ret
-;
-; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i64:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, ma
+; RV32-NEXT: vmv.v.x v24, a0
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV32-NEXT: vsll.vi v20, v20, 8
+; RV32-NEXT: vor.vv v8, v8, v20
+; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; RV32-NEXT: vmv.v.x v20, a1
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; RV32-NEXT: vmv.v.x v12, a2
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vsrl.vi v16, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v24
+; RV32-NEXT: vand.vv v16, v16, v24
+; RV32-NEXT: vsll.vi v8, v8, 4
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 2
+; RV32-NEXT: vand.vv v8, v8, v20
+; RV32-NEXT: vand.vv v16, v16, v20
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v12
+; RV32-NEXT: vand.vv v12, v16, v12
+; RV32-NEXT: vadd.vv v8, v8, v8
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: .cfi_def_cfa_offset 0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vp_bitreverse_nxv4i64:
+; RV64: # %bb.0:
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m4, ta, ma
+; RV64-NEXT: vsrl.vi v16, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a1
+; RV64-NEXT: vsrl.vx v20, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v20, v20, a2
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vsrl.vi v20, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v16, v16, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v20, v20, a4
+; RV64-NEXT: vor.vv v20, v20, v16
+; RV64-NEXT: vand.vx v16, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vand.vx v20, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v16, v16, 24
+; RV64-NEXT: vsll.vi v20, v20, 8
+; RV64-NEXT: vor.vv v16, v16, v20
+; RV64-NEXT: vsll.vx v20, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v20, v8
+; RV64-NEXT: vor.vv v8, v8, v16
+; RV64-NEXT: vor.vv v8, v8, v12
+; RV64-NEXT: vsrl.vi v12, v8, 4
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v12, v12, a2
+; RV64-NEXT: vsll.vi v8, v8, 4
+; RV64-NEXT: vor.vv v8, v12, v8
+; RV64-NEXT: vsrl.vi v12, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v12, v12, a0
+; RV64-NEXT: vsll.vi v8, v8, 2
+; RV64-NEXT: vor.vv v8, v12, v8
+; RV64-NEXT: vsrl.vi v12, v8, 1
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v12, v12, a1
+; RV64-NEXT: vadd.vv v8, v8, v8
+; RV64-NEXT: vor.vv v8, v12, v8
+; RV64-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i64:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.bitreverse.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -2099,66 +2071,66 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64_unmasked(<vscale x 4 x i64> %va
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsrl.vi v20, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: vsetvli a4, zero, e64, m4, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v16, v8, a2
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vsrl.vx v12, v8, a2
-; RV32-NEXT: vsrl.vx v24, v8, a4
-; RV32-NEXT: vand.vx v28, v8, a1
-; RV32-NEXT: vand.vx v24, v24, a1
-; RV32-NEXT: vor.vv v12, v24, v12
-; RV32-NEXT: vlse64.v v24, (a6), zero
-; RV32-NEXT: vsll.vx v28, v28, a4
-; RV32-NEXT: vor.vv v16, v16, v28
+; RV32-NEXT: vsrl.vx v12, v8, a1
+; RV32-NEXT: vsrl.vx v16, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v28, v8, a1
+; RV32-NEXT: vand.vx v16, v16, a0
+; RV32-NEXT: vlse64.v v20, (a5), zero
+; RV32-NEXT: vor.vv v16, v16, v12
+; RV32-NEXT: vand.vx v12, v8, a0
+; RV32-NEXT: vsll.vx v12, v12, a2
+; RV32-NEXT: vor.vv v12, v28, v12
; RV32-NEXT: vsrl.vi v28, v8, 8
-; RV32-NEXT: vand.vx v20, v20, a5
-; RV32-NEXT: vand.vv v28, v28, v24
-; RV32-NEXT: vor.vv v20, v28, v20
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vand.vv v24, v8, v24
-; RV32-NEXT: vand.vx v8, v8, a5
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vand.vx v24, v24, a4
+; RV32-NEXT: vand.vv v28, v28, v20
+; RV32-NEXT: vor.vv v24, v28, v24
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vand.vv v20, v8, v20
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v24, v24, 8
-; RV32-NEXT: vor.vv v8, v8, v24
-; RV32-NEXT: vsetvli a4, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v12, v20, v12
-; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v20, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v12
-; RV32-NEXT: vsrl.vi v12, v8, 4
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, ma
+; RV32-NEXT: vmv.v.x v24, a0
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV32-NEXT: vsll.vi v20, v20, 8
+; RV32-NEXT: vor.vv v8, v8, v20
+; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; RV32-NEXT: vmv.v.x v20, a1
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; RV32-NEXT: vmv.v.x v12, a2
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: vand.vv v8, v8, v24
-; RV32-NEXT: vand.vv v12, v12, v24
+; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vsll.vi v8, v8, 4
-; RV32-NEXT: vor.vv v8, v12, v8
-; RV32-NEXT: vsrl.vi v12, v8, 2
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 2
; RV32-NEXT: vand.vv v8, v8, v20
-; RV32-NEXT: vand.vv v12, v12, v20
+; RV32-NEXT: vand.vv v16, v16, v20
; RV32-NEXT: vsll.vi v8, v8, 2
-; RV32-NEXT: vor.vv v8, v12, v8
-; RV32-NEXT: vsrl.vi v12, v8, 1
-; RV32-NEXT: vand.vv v8, v8, v16
-; RV32-NEXT: vand.vv v12, v12, v16
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v12
+; RV32-NEXT: vand.vv v12, v16, v12
; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16
@@ -2167,67 +2139,67 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64_unmasked(<vscale x 4 x i64> %va
;
; RV64-LABEL: vp_bitreverse_nxv4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m4, ta, ma
; RV64-NEXT: vsrl.vi v16, v8, 24
-; RV64-NEXT: vsrl.vi v20, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v12, v8, a3
-; RV64-NEXT: vsrl.vx v24, v8, a5
-; RV64-NEXT: vand.vx v24, v24, a0
-; RV64-NEXT: vor.vv v12, v24, v12
-; RV64-NEXT: vand.vx v24, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v16, v16, a1
-; RV64-NEXT: vsll.vi v24, v24, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a1
+; RV64-NEXT: vsrl.vx v20, v8, a0
+; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v20, v20, a2
-; RV64-NEXT: vor.vv v16, v20, v16
-; RV64-NEXT: vand.vx v20, v8, a2
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vsrl.vi v20, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v16, v16, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v20, v20, a4
+; RV64-NEXT: vor.vv v20, v20, v16
+; RV64-NEXT: vand.vx v16, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vand.vx v20, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v16, v16, 24
; RV64-NEXT: vsll.vi v20, v20, 8
-; RV64-NEXT: vor.vv v20, v24, v20
-; RV64-NEXT: vsll.vx v24, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v24, v8
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: vor.vv v12, v16, v12
-; RV64-NEXT: vor.vv v8, v8, v20
+; RV64-NEXT: vor.vv v16, v16, v20
+; RV64-NEXT: vsll.vx v20, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v20, v8
+; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vsrl.vi v12, v8, 4
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v12, v12, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v12, v12, a2
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v12, v8
; RV64-NEXT: vsrl.vi v12, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vand.vx v12, v12, a1
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v12, v12, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v12, v8
; RV64-NEXT: vsrl.vi v12, v8, 1
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vand.vx v12, v12, a2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v12, v12, a1
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vor.vv v8, v12, v8
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i64_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.bitreverse.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -2239,115 +2211,88 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a4, 4080
; RV32-NEXT: addi a5, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vsrl.vi v24, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: vand.vv v16, v24, v16
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 4, v0.t
-; RV32-NEXT: vor.vv v24, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsll.vi v8, v8, 4
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 2
+; RV32-NEXT: vand.vv v8, v8, v24
+; RV32-NEXT: vand.vv v16, v16, v24
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v24
+; RV32-NEXT: vand.vv v16, v16, v24
+; RV32-NEXT: vadd.vv v8, v8, v8
+; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -2356,86 +2301,68 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale
;
; RV64-LABEL: vp_bitreverse_nxv7i64:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vand.vx v8, v8, a0, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vand.vx v8, v8, a1, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a1
+; RV64-NEXT: vsrl.vx v0, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vsrl.vi v0, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v0, v0, v24
+; RV64-NEXT: vand.vx v24, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vand.vx v0, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v24, v24, 24
+; RV64-NEXT: vsll.vi v0, v0, 8
+; RV64-NEXT: vor.vv v24, v24, v0
+; RV64-NEXT: vsll.vx v0, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
+; RV64-NEXT: vor.vv v8, v8, v16
+; RV64-NEXT: vsrl.vi v16, v8, 4
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v16, v16, a2
+; RV64-NEXT: vsll.vi v8, v8, 4
+; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: vsrl.vi v16, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v16, v16, a0
+; RV64-NEXT: vsll.vi v8, v8, 2
+; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: vsrl.vi v16, v8, 1
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v16, v16, a1
+; RV64-NEXT: vadd.vv v8, v8, v8
+; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv7i64:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.bitreverse.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v
@@ -2446,79 +2373,79 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64_unmasked(<vscale x 7 x i64> %va
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2
-; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vsrl.vx v24, v8, a2
-; RV32-NEXT: vsrl.vx v0, v8, a4
-; RV32-NEXT: vand.vx v0, v0, a1
-; RV32-NEXT: vor.vv v24, v0, v24
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vand.vx v24, v8, a1
-; RV32-NEXT: vsll.vx v24, v24, a4
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v24, (a6), zero
-; RV32-NEXT: vsrl.vi v16, v8, 24
-; RV32-NEXT: vand.vx v16, v16, a5
-; RV32-NEXT: vsrl.vi v0, v8, 8
-; RV32-NEXT: vand.vv v0, v0, v24
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
; RV32-NEXT: vor.vv v16, v0, v16
-; RV32-NEXT: vand.vv v24, v8, v24
-; RV32-NEXT: vand.vx v8, v8, a5
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v24, v24, 8
-; RV32-NEXT: vor.vv v24, v8, v24
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 3
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vsrl.vi v24, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: vand.vv v16, v24, v16
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: vsrl.vi v16, v8, 4
-; RV32-NEXT: vand.vv v8, v8, v24
-; RV32-NEXT: vand.vv v16, v16, v24
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 2
; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vand.vv v16, v16, v24
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 1
@@ -2536,83 +2463,67 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64_unmasked(<vscale x 7 x i64> %va
;
; RV64-LABEL: vp_bitreverse_nxv7i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v16, v8, a3
-; RV64-NEXT: vsrl.vx v0, v8, a5
-; RV64-NEXT: vand.vx v0, v0, a0
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a1
+; RV64-NEXT: vsrl.vx v0, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vsrl.vi v0, v8, 8
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v24, v24, a1
-; RV64-NEXT: vand.vx v0, v0, a2
-; RV64-NEXT: vor.vv v24, v0, v24
-; RV64-NEXT: vand.vx v0, v8, a1
-; RV64-NEXT: vsll.vi v0, v0, 24
-; RV64-NEXT: vand.vx v16, v8, a2
-; RV64-NEXT: vsll.vi v16, v16, 8
-; RV64-NEXT: vor.vv v0, v0, v16
-; RV64-NEXT: vsll.vx v16, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v24, v16
-; RV64-NEXT: vor.vv v8, v8, v0
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v0, v0, v24
+; RV64-NEXT: vand.vx v24, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vand.vx v0, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v24, v24, 24
+; RV64-NEXT: vsll.vi v0, v0, 8
+; RV64-NEXT: vor.vv v24, v24, v0
+; RV64-NEXT: vsll.vx v0, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 4
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v16, v16, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v16, v16, a2
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: vsrl.vi v16, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vand.vx v16, v16, a1
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: vsrl.vi v16, v8, 1
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vand.vx v16, v16, a2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v16, v16, a1
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv7i64_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.bitreverse.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)
@@ -2624,115 +2535,88 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a4, 4080
; RV32-NEXT: addi a5, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vsrl.vi v24, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: vand.vv v16, v24, v16
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 4, v0.t
-; RV32-NEXT: vor.vv v24, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsll.vi v8, v8, 4
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 2
+; RV32-NEXT: vand.vv v8, v8, v24
+; RV32-NEXT: vand.vv v16, v16, v24
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v24
+; RV32-NEXT: vand.vv v16, v16, v24
+; RV32-NEXT: vadd.vv v8, v8, v8
+; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -2741,86 +2625,68 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale
;
; RV64-LABEL: vp_bitreverse_nxv8i64:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vand.vx v8, v8, a0, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vand.vx v8, v8, a1, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a1
+; RV64-NEXT: vsrl.vx v0, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vsrl.vi v0, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v0, v0, v24
+; RV64-NEXT: vand.vx v24, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vand.vx v0, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v24, v24, 24
+; RV64-NEXT: vsll.vi v0, v0, 8
+; RV64-NEXT: vor.vv v24, v24, v0
+; RV64-NEXT: vsll.vx v0, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
+; RV64-NEXT: vor.vv v8, v8, v16
+; RV64-NEXT: vsrl.vi v16, v8, 4
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v16, v16, a2
+; RV64-NEXT: vsll.vi v8, v8, 4
+; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: vsrl.vi v16, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v16, v16, a0
+; RV64-NEXT: vsll.vi v8, v8, 2
+; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: vsrl.vi v16, v8, 1
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v16, v16, a1
+; RV64-NEXT: vadd.vv v8, v8, v8
+; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i64:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.bitreverse.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -2831,79 +2697,79 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2
-; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vsrl.vx v24, v8, a2
-; RV32-NEXT: vsrl.vx v0, v8, a4
-; RV32-NEXT: vand.vx v0, v0, a1
-; RV32-NEXT: vor.vv v24, v0, v24
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vand.vx v24, v8, a1
-; RV32-NEXT: vsll.vx v24, v24, a4
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v24, (a6), zero
-; RV32-NEXT: vsrl.vi v16, v8, 24
-; RV32-NEXT: vand.vx v16, v16, a5
-; RV32-NEXT: vsrl.vi v0, v8, 8
-; RV32-NEXT: vand.vv v0, v0, v24
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
; RV32-NEXT: vor.vv v16, v0, v16
-; RV32-NEXT: vand.vv v24, v8, v24
-; RV32-NEXT: vand.vx v8, v8, a5
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v24, v24, 8
-; RV32-NEXT: vor.vv v24, v8, v24
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 3
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vsrl.vi v24, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: vand.vv v16, v24, v16
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: vsrl.vi v16, v8, 4
-; RV32-NEXT: vand.vv v8, v8, v24
-; RV32-NEXT: vand.vv v16, v16, v24
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 2
; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vand.vv v16, v16, v24
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 1
@@ -2921,83 +2787,67 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va
;
; RV64-LABEL: vp_bitreverse_nxv8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v16, v8, a3
-; RV64-NEXT: vsrl.vx v0, v8, a5
-; RV64-NEXT: vand.vx v0, v0, a0
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a1
+; RV64-NEXT: vsrl.vx v0, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vsrl.vi v0, v8, 8
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v24, v24, a1
-; RV64-NEXT: vand.vx v0, v0, a2
-; RV64-NEXT: vor.vv v24, v0, v24
-; RV64-NEXT: vand.vx v0, v8, a1
-; RV64-NEXT: vsll.vi v0, v0, 24
-; RV64-NEXT: vand.vx v16, v8, a2
-; RV64-NEXT: vsll.vi v16, v16, 8
-; RV64-NEXT: vor.vv v0, v0, v16
-; RV64-NEXT: vsll.vx v16, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v24, v16
-; RV64-NEXT: vor.vv v8, v8, v0
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v0, v0, v24
+; RV64-NEXT: vand.vx v24, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vand.vx v0, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v24, v24, 24
+; RV64-NEXT: vsll.vi v0, v0, 8
+; RV64-NEXT: vor.vv v24, v24, v0
+; RV64-NEXT: vsll.vx v0, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 4
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v16, v16, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v16, v16, a2
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: vsrl.vi v16, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vand.vx v16, v16, a1
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: vsrl.vi v16, v8, 1
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vand.vx v16, v16, a2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v16, v16, a1
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i64_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.bitreverse.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -3009,88 +2859,56 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va
define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv64i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: lui a1, 1
-; CHECK-NEXT: lui a2, 3
-; CHECK-NEXT: srli a4, a3, 1
-; CHECK-NEXT: slli a3, a3, 2
-; CHECK-NEXT: vslidedown.vx v0, v0, a4
-; CHECK-NEXT: sub a4, a0, a3
-; CHECK-NEXT: sltu a5, a0, a4
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: and a5, a5, a4
-; CHECK-NEXT: lui a6, 5
-; CHECK-NEXT: addi a4, a1, -241
-; CHECK-NEXT: addi a2, a2, 819
-; CHECK-NEXT: addi a1, a6, 1365
-; CHECK-NEXT: vsetvli zero, a5, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
-; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a4, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a4, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
-; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: bltu a0, a3, .LBB46_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a3
-; CHECK-NEXT: .LBB46_2:
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a4, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a4, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v24, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: lui a0, 1
+; CHECK-NEXT: lui a1, 3
+; CHECK-NEXT: lui a2, 5
+; CHECK-NEXT: vor.vv v8, v8, v24
+; CHECK-NEXT: vsrl.vi v24, v16, 8
+; CHECK-NEXT: vsll.vi v16, v16, 8
+; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: addi a1, a1, 819
+; CHECK-NEXT: addi a2, a2, 1365
+; CHECK-NEXT: vor.vv v16, v16, v24
+; CHECK-NEXT: vsrl.vi v24, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v24, v24, a0
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vsrl.vi v24, v16, 4
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: vand.vx v24, v24, a0
+; CHECK-NEXT: vsll.vi v16, v16, 4
+; CHECK-NEXT: vor.vv v16, v24, v16
+; CHECK-NEXT: vsrl.vi v24, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vand.vx v24, v24, a1
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vsrl.vi v24, v16, 2
+; CHECK-NEXT: vand.vx v16, v16, a1
+; CHECK-NEXT: vand.vx v24, v24, a1
+; CHECK-NEXT: vsll.vi v16, v16, 2
+; CHECK-NEXT: vor.vv v16, v24, v16
+; CHECK-NEXT: vsrl.vi v24, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a2
+; CHECK-NEXT: vand.vx v24, v24, a2
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vsrl.vi v24, v16, 1
+; CHECK-NEXT: vand.vx v16, v16, a2
+; CHECK-NEXT: vand.vx v24, v24, a2
+; CHECK-NEXT: vadd.vv v16, v16, v16
+; CHECK-NEXT: vor.vv v16, v24, v16
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 1
-; CHECK-ZVBB-NEXT: slli a1, a1, 2
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sub a2, a0, a1
-; CHECK-ZVBB-NEXT: sltu a3, a0, a2
-; CHECK-ZVBB-NEXT: addi a3, a3, -1
-; CHECK-ZVBB-NEXT: and a2, a3, a2
-; CHECK-ZVBB-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v16, v16, v0.t
-; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
-; CHECK-ZVBB-NEXT: # %bb.1:
-; CHECK-ZVBB-NEXT: mv a0, a1
-; CHECK-ZVBB-NEXT: .LBB46_2:
-; CHECK-ZVBB-NEXT: vmv1r.v v0, v24
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
+; CHECK-ZVBB-NEXT: vbrev.v v16, v16
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 64 x i16> @llvm.vp.bitreverse.nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i16> %v
@@ -3099,78 +2917,56 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
define <vscale x 64 x i16> @vp_bitreverse_nxv64i16_unmasked(<vscale x 64 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv64i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: lui a1, 1
-; CHECK-NEXT: lui a2, 3
-; CHECK-NEXT: slli a3, a3, 2
-; CHECK-NEXT: sub a4, a0, a3
-; CHECK-NEXT: sltu a5, a0, a4
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: and a5, a5, a4
-; CHECK-NEXT: lui a6, 5
-; CHECK-NEXT: addi a4, a1, -241
-; CHECK-NEXT: addi a2, a2, 819
-; CHECK-NEXT: addi a1, a6, 1365
-; CHECK-NEXT: vsetvli zero, a5, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v24, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: lui a0, 1
+; CHECK-NEXT: lui a1, 3
+; CHECK-NEXT: lui a2, 5
+; CHECK-NEXT: vor.vv v8, v8, v24
; CHECK-NEXT: vsrl.vi v24, v16, 8
; CHECK-NEXT: vsll.vi v16, v16, 8
+; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: addi a1, a1, 819
+; CHECK-NEXT: addi a2, a2, 1365
; CHECK-NEXT: vor.vv v16, v16, v24
+; CHECK-NEXT: vsrl.vi v24, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v24, v24, a0
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v24, v8
; CHECK-NEXT: vsrl.vi v24, v16, 4
-; CHECK-NEXT: vand.vx v16, v16, a4
-; CHECK-NEXT: vand.vx v24, v24, a4
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: vand.vx v24, v24, a0
; CHECK-NEXT: vsll.vi v16, v16, 4
; CHECK-NEXT: vor.vv v16, v24, v16
+; CHECK-NEXT: vsrl.vi v24, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vand.vx v24, v24, a1
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v24, v8
; CHECK-NEXT: vsrl.vi v24, v16, 2
-; CHECK-NEXT: vand.vx v16, v16, a2
-; CHECK-NEXT: vand.vx v24, v24, a2
-; CHECK-NEXT: vsll.vi v16, v16, 2
-; CHECK-NEXT: vor.vv v16, v24, v16
-; CHECK-NEXT: vsrl.vi v24, v16, 1
; CHECK-NEXT: vand.vx v16, v16, a1
; CHECK-NEXT: vand.vx v24, v24, a1
-; CHECK-NEXT: vadd.vv v16, v16, v16
+; CHECK-NEXT: vsll.vi v16, v16, 2
; CHECK-NEXT: vor.vv v16, v24, v16
-; CHECK-NEXT: bltu a0, a3, .LBB47_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a3
-; CHECK-NEXT: .LBB47_2:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v8, 8
-; CHECK-NEXT: vsll.vi v8, v8, 8
-; CHECK-NEXT: vor.vv v8, v8, v24
-; CHECK-NEXT: vsrl.vi v24, v8, 4
-; CHECK-NEXT: vand.vx v8, v8, a4
-; CHECK-NEXT: vand.vx v24, v24, a4
-; CHECK-NEXT: vsll.vi v8, v8, 4
-; CHECK-NEXT: vor.vv v8, v24, v8
-; CHECK-NEXT: vsrl.vi v24, v8, 2
+; CHECK-NEXT: vsrl.vi v24, v8, 1
; CHECK-NEXT: vand.vx v8, v8, a2
; CHECK-NEXT: vand.vx v24, v24, a2
-; CHECK-NEXT: vsll.vi v8, v8, 2
-; CHECK-NEXT: vor.vv v8, v24, v8
-; CHECK-NEXT: vsrl.vi v24, v8, 1
-; CHECK-NEXT: vand.vx v8, v8, a1
-; CHECK-NEXT: vand.vx v24, v24, a1
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vsrl.vi v24, v16, 1
+; CHECK-NEXT: vand.vx v16, v16, a2
+; CHECK-NEXT: vand.vx v24, v24, a2
+; CHECK-NEXT: vadd.vv v16, v16, v16
+; CHECK-NEXT: vor.vv v16, v24, v16
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i16_unmasked:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: slli a1, a1, 2
-; CHECK-ZVBB-NEXT: sub a2, a0, a1
-; CHECK-ZVBB-NEXT: sltu a3, a0, a2
-; CHECK-ZVBB-NEXT: addi a3, a3, -1
-; CHECK-ZVBB-NEXT: and a2, a3, a2
-; CHECK-ZVBB-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v16, v16
-; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB47_2
-; CHECK-ZVBB-NEXT: # %bb.1:
-; CHECK-ZVBB-NEXT: mv a0, a1
-; CHECK-ZVBB-NEXT: .LBB47_2:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v8, v8
+; CHECK-ZVBB-NEXT: vbrev.v v16, v16
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 64 x i16> @llvm.vp.bitreverse.nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> splat (i1 true), i32 %evl)
ret <vscale x 64 x i16> %v
@@ -3180,39 +2976,39 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16_unmasked(<vscale x 64 x i16>
define <vscale x 1 x i9> @vp_bitreverse_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv1i9:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 7, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v8, v8, 7
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i9:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t
-; CHECK-ZVBB-NEXT: vsrl.vi v8, v8, 7, v0.t
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vbrev.v v8, v8
+; CHECK-ZVBB-NEXT: vsrl.vi v8, v8, 7
; CHECK-ZVBB-NEXT: ret
%v = call <vscale x 1 x i9> @llvm.vp.bitreverse.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i9> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
index 0177b8cfd4393..0044bf82014f4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
@@ -11,16 +11,16 @@
define <vscale x 1 x i16> @vp_bswap_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv1i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.bswap.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -29,7 +29,7 @@ define <vscale x 1 x i16> @vp_bswap_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
define <vscale x 1 x i16> @vp_bswap_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v9
@@ -37,7 +37,7 @@ define <vscale x 1 x i16> @vp_bswap_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv1i16_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.bswap.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -47,16 +47,16 @@ define <vscale x 1 x i16> @vp_bswap_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32
define <vscale x 2 x i16> @vp_bswap_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv2i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.bswap.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -65,7 +65,7 @@ define <vscale x 2 x i16> @vp_bswap_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
define <vscale x 2 x i16> @vp_bswap_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v9
@@ -73,7 +73,7 @@ define <vscale x 2 x i16> @vp_bswap_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv2i16_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.bswap.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -83,16 +83,16 @@ define <vscale x 2 x i16> @vp_bswap_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32
define <vscale x 4 x i16> @vp_bswap_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv4i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.bswap.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -101,7 +101,7 @@ define <vscale x 4 x i16> @vp_bswap_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
define <vscale x 4 x i16> @vp_bswap_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v9
@@ -109,7 +109,7 @@ define <vscale x 4 x i16> @vp_bswap_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv4i16_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.bswap.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -119,16 +119,16 @@ define <vscale x 4 x i16> @vp_bswap_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32
define <vscale x 8 x i16> @vp_bswap_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsrl.vi v10, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv8i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.bswap.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -137,7 +137,7 @@ define <vscale x 8 x i16> @vp_bswap_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
define <vscale x 8 x i16> @vp_bswap_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v10
@@ -145,7 +145,7 @@ define <vscale x 8 x i16> @vp_bswap_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv8i16_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.bswap.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -155,16 +155,16 @@ define <vscale x 8 x i16> @vp_bswap_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32
define <vscale x 16 x i16> @vp_bswap_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vsrl.vi v12, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv16i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.bswap.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v
@@ -173,7 +173,7 @@ define <vscale x 16 x i16> @vp_bswap_nxv16i16(<vscale x 16 x i16> %va, <vscale x
define <vscale x 16 x i16> @vp_bswap_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v12
@@ -181,7 +181,7 @@ define <vscale x 16 x i16> @vp_bswap_nxv16i16_unmasked(<vscale x 16 x i16> %va,
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv16i16_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.bswap.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -191,16 +191,16 @@ define <vscale x 16 x i16> @vp_bswap_nxv16i16_unmasked(<vscale x 16 x i16> %va,
define <vscale x 32 x i16> @vp_bswap_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v16, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv32i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.bswap.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v
@@ -209,7 +209,7 @@ define <vscale x 32 x i16> @vp_bswap_nxv32i16(<vscale x 32 x i16> %va, <vscale x
define <vscale x 32 x i16> @vp_bswap_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv32i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v16
@@ -217,7 +217,7 @@ define <vscale x 32 x i16> @vp_bswap_nxv32i16_unmasked(<vscale x 32 x i16> %va,
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv32i16_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.bswap.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)
@@ -227,24 +227,24 @@ define <vscale x 32 x i16> @vp_bswap_nxv32i16_unmasked(<vscale x 32 x i16> %va,
define <vscale x 1 x i32> @vp_bswap_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vor.vv v9, v9, v10
+; CHECK-NEXT: vand.vx v10, v8, a0
+; CHECK-NEXT: vsll.vi v10, v10, 8
+; CHECK-NEXT: vsll.vi v8, v8, 24
+; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv1i32:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.bswap.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -253,7 +253,7 @@ define <vscale x 1 x i32> @vp_bswap_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
define <vscale x 1 x i32> @vp_bswap_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv1i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v10, v8, 24
@@ -269,7 +269,7 @@ define <vscale x 1 x i32> @vp_bswap_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv1i32_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.bswap.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -279,24 +279,24 @@ define <vscale x 1 x i32> @vp_bswap_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32
define <vscale x 2 x i32> @vp_bswap_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vor.vv v9, v9, v10
+; CHECK-NEXT: vand.vx v10, v8, a0
+; CHECK-NEXT: vsll.vi v10, v10, 8
+; CHECK-NEXT: vsll.vi v8, v8, 24
+; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv2i32:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.bswap.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -305,7 +305,7 @@ define <vscale x 2 x i32> @vp_bswap_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
define <vscale x 2 x i32> @vp_bswap_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v10, v8, 24
@@ -321,7 +321,7 @@ define <vscale x 2 x i32> @vp_bswap_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv2i32_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.bswap.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -331,24 +331,24 @@ define <vscale x 2 x i32> @vp_bswap_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32
define <vscale x 4 x i32> @vp_bswap_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v12, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v10, v10, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0
+; CHECK-NEXT: vor.vv v10, v10, v12
+; CHECK-NEXT: vand.vx v12, v8, a0
+; CHECK-NEXT: vsll.vi v12, v12, 8
+; CHECK-NEXT: vsll.vi v8, v8, 24
+; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv4i32:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.bswap.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -357,7 +357,7 @@ define <vscale x 4 x i32> @vp_bswap_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
define <vscale x 4 x i32> @vp_bswap_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v12, v8, 24
@@ -373,7 +373,7 @@ define <vscale x 4 x i32> @vp_bswap_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv4i32_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.bswap.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -383,24 +383,24 @@ define <vscale x 4 x i32> @vp_bswap_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32
define <vscale x 8 x i32> @vp_bswap_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v16, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v12, v12, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0
+; CHECK-NEXT: vor.vv v12, v12, v16
+; CHECK-NEXT: vand.vx v16, v8, a0
+; CHECK-NEXT: vsll.vi v16, v16, 8
+; CHECK-NEXT: vsll.vi v8, v8, 24
+; CHECK-NEXT: vor.vv v8, v8, v16
+; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv8i32:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.bswap.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -409,7 +409,7 @@ define <vscale x 8 x i32> @vp_bswap_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
define <vscale x 8 x i32> @vp_bswap_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v16, v8, 24
@@ -425,7 +425,7 @@ define <vscale x 8 x i32> @vp_bswap_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv8i32_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.bswap.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -435,24 +435,24 @@ define <vscale x 8 x i32> @vp_bswap_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32
define <vscale x 16 x i32> @vp_bswap_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v24, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
-; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v24, v24, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: vor.vv v16, v16, v24
+; CHECK-NEXT: vand.vx v24, v8, a0
+; CHECK-NEXT: vsll.vi v24, v24, 8
+; CHECK-NEXT: vsll.vi v8, v8, 24
+; CHECK-NEXT: vor.vv v8, v8, v24
+; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv16i32:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.bswap.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v
@@ -461,7 +461,7 @@ define <vscale x 16 x i32> @vp_bswap_nxv16i32(<vscale x 16 x i32> %va, <vscale x
define <vscale x 16 x i32> @vp_bswap_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v24, v8, 24
@@ -477,7 +477,7 @@ define <vscale x 16 x i32> @vp_bswap_nxv16i32_unmasked(<vscale x 16 x i32> %va,
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv16i32_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.bswap.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
@@ -489,79 +489,79 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: vsetvli a4, zero, e64, m1, ta, ma
+; RV32-NEXT: vsrl.vi v9, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v9, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v10, v8, a1
+; RV32-NEXT: vsrl.vx v11, v8, a2
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v10, v8, a0, v0.t
-; RV32-NEXT: vlse64.v v11, (a6), zero
-; RV32-NEXT: vsll.vx v10, v10, a4, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vand.vx v10, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV32-NEXT: vand.vv v12, v8, v11, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t
-; RV32-NEXT: vand.vx v12, v12, a0, v0.t
-; RV32-NEXT: vor.vv v10, v12, v10, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
-; RV32-NEXT: vand.vx v12, v12, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v11, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v8, v10, v0.t
-; RV32-NEXT: vor.vv v8, v9, v8, v0.t
+; RV32-NEXT: vsll.vx v12, v8, a1
+; RV32-NEXT: vand.vx v11, v11, a0
+; RV32-NEXT: vlse64.v v13, (a5), zero
+; RV32-NEXT: vor.vv v10, v11, v10
+; RV32-NEXT: vand.vx v11, v8, a0
+; RV32-NEXT: vsll.vx v11, v11, a2
+; RV32-NEXT: vor.vv v11, v12, v11
+; RV32-NEXT: vsrl.vi v12, v8, 8
+; RV32-NEXT: vand.vx v9, v9, a4
+; RV32-NEXT: vand.vv v12, v12, v13
+; RV32-NEXT: vor.vv v9, v12, v9
+; RV32-NEXT: vand.vv v12, v8, v13
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v12, v12, 8
+; RV32-NEXT: vor.vv v9, v9, v10
+; RV32-NEXT: vor.vv v8, v8, v12
+; RV32-NEXT: vor.vv v8, v11, v8
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bswap_nxv1i64:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v9, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
-; RV64-NEXT: vand.vx v10, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
-; RV64-NEXT: vor.vv v9, v9, v10, v0.t
-; RV64-NEXT: vsll.vx v10, v8, a3, v0.t
-; RV64-NEXT: vand.vx v11, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v11, v11, a5, v0.t
-; RV64-NEXT: vor.vv v10, v10, v11, v0.t
-; RV64-NEXT: vor.vv v9, v10, v9, v0.t
-; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v11, v8, a5, v0.t
-; RV64-NEXT: vand.vx v11, v11, a0, v0.t
-; RV64-NEXT: vor.vv v10, v11, v10, v0.t
-; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t
-; RV64-NEXT: vand.vx v11, v11, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v11, v0.t
-; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m1, ta, ma
+; RV64-NEXT: vsrl.vi v9, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v10, v8, a0
+; RV64-NEXT: vsrl.vx v11, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v11, v11, a2
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsrl.vi v11, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v9, v9, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v11, v11, a4
+; RV64-NEXT: vor.vv v9, v11, v9
+; RV64-NEXT: vand.vx v11, v8, a3
+; RV64-NEXT: vsll.vi v11, v11, 24
+; RV64-NEXT: vor.vv v9, v9, v10
+; RV64-NEXT: vand.vx v10, v8, a4
+; RV64-NEXT: vsll.vi v10, v10, 8
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsll.vx v11, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v11, v8
+; RV64-NEXT: vor.vv v8, v8, v10
+; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv1i64:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.bswap.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v
@@ -572,37 +572,37 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vsetvli a4, zero, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v10, v8, a2
-; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: vsrl.vx v11, v8, a2
-; RV32-NEXT: vsrl.vx v12, v8, a4
-; RV32-NEXT: vand.vx v13, v8, a0
-; RV32-NEXT: vand.vx v12, v12, a0
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v12, v8, a1
+; RV32-NEXT: vand.vx v11, v11, a0
+; RV32-NEXT: vlse64.v v13, (a5), zero
+; RV32-NEXT: vor.vv v10, v11, v10
+; RV32-NEXT: vand.vx v11, v8, a0
+; RV32-NEXT: vsll.vx v11, v11, a2
; RV32-NEXT: vor.vv v11, v12, v11
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: vsll.vx v13, v13, a4
-; RV32-NEXT: vor.vv v10, v10, v13
-; RV32-NEXT: vsrl.vi v13, v8, 8
-; RV32-NEXT: vand.vx v9, v9, a5
-; RV32-NEXT: vand.vv v13, v13, v12
-; RV32-NEXT: vor.vv v9, v13, v9
-; RV32-NEXT: vand.vv v12, v8, v12
-; RV32-NEXT: vand.vx v8, v8, a5
+; RV32-NEXT: vsrl.vi v12, v8, 8
+; RV32-NEXT: vand.vx v9, v9, a4
+; RV32-NEXT: vand.vv v12, v12, v13
+; RV32-NEXT: vor.vv v9, v12, v9
+; RV32-NEXT: vand.vv v12, v8, v13
+; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v12, v12, 8
+; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vor.vv v8, v8, v12
-; RV32-NEXT: vor.vv v8, v10, v8
-; RV32-NEXT: vor.vv v9, v9, v11
+; RV32-NEXT: vor.vv v8, v11, v8
; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -610,40 +610,40 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32
;
; RV64-LABEL: vp_bswap_nxv1i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 24
-; RV64-NEXT: vsrl.vi v10, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v11, v8, a3
-; RV64-NEXT: vsrl.vx v12, v8, a5
-; RV64-NEXT: vand.vx v12, v12, a0
-; RV64-NEXT: vor.vv v11, v12, v11
-; RV64-NEXT: vand.vx v12, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v9, v9, a1
-; RV64-NEXT: vsll.vi v12, v12, 24
-; RV64-NEXT: vand.vx v10, v10, a2
-; RV64-NEXT: vor.vv v9, v10, v9
-; RV64-NEXT: vand.vx v10, v8, a2
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v10, v8, a0
+; RV64-NEXT: vsrl.vx v11, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v11, v11, a2
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsrl.vi v11, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v9, v9, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v11, v11, a4
+; RV64-NEXT: vor.vv v9, v11, v9
+; RV64-NEXT: vand.vx v11, v8, a3
+; RV64-NEXT: vsll.vi v11, v11, 24
+; RV64-NEXT: vor.vv v9, v9, v10
+; RV64-NEXT: vand.vx v10, v8, a4
; RV64-NEXT: vsll.vi v10, v10, 8
-; RV64-NEXT: vor.vv v10, v12, v10
-; RV64-NEXT: vsll.vx v12, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v12, v8
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsll.vx v11, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v11, v8
; RV64-NEXT: vor.vv v8, v8, v10
-; RV64-NEXT: vor.vv v9, v9, v11
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv1i64_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.bswap.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
@@ -655,79 +655,79 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: vsetvli a4, zero, e64, m2, ta, ma
+; RV32-NEXT: vsrl.vi v10, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsll.vx v10, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v12, v8, a1
+; RV32-NEXT: vsrl.vx v14, v8, a2
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v12, v8, a0, v0.t
-; RV32-NEXT: vlse64.v v14, (a6), zero
-; RV32-NEXT: vsll.vx v12, v12, a4, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vand.vx v12, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV32-NEXT: vand.vv v16, v8, v14, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v12, v12, v16, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t
-; RV32-NEXT: vand.vx v16, v16, a0, v0.t
-; RV32-NEXT: vor.vv v12, v16, v12, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV32-NEXT: vand.vx v16, v16, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v14, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vsll.vx v16, v8, a1
+; RV32-NEXT: vand.vx v14, v14, a0
+; RV32-NEXT: vlse64.v v18, (a5), zero
+; RV32-NEXT: vor.vv v12, v14, v12
+; RV32-NEXT: vand.vx v14, v8, a0
+; RV32-NEXT: vsll.vx v14, v14, a2
+; RV32-NEXT: vor.vv v14, v16, v14
+; RV32-NEXT: vsrl.vi v16, v8, 8
+; RV32-NEXT: vand.vx v10, v10, a4
+; RV32-NEXT: vand.vv v16, v16, v18
+; RV32-NEXT: vor.vv v10, v16, v10
+; RV32-NEXT: vand.vv v16, v8, v18
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v10, v10, v12
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vor.vv v8, v14, v8
+; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bswap_nxv2i64:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vand.vx v10, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV64-NEXT: vand.vx v12, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV64-NEXT: vor.vv v10, v10, v12, v0.t
-; RV64-NEXT: vsll.vx v12, v8, a3, v0.t
-; RV64-NEXT: vand.vx v14, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v14, v14, a5, v0.t
-; RV64-NEXT: vor.vv v12, v12, v14, v0.t
-; RV64-NEXT: vor.vv v10, v12, v10, v0.t
-; RV64-NEXT: vsrl.vx v12, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v14, v8, a5, v0.t
-; RV64-NEXT: vand.vx v14, v14, a0, v0.t
-; RV64-NEXT: vor.vv v12, v14, v12, v0.t
-; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t
-; RV64-NEXT: vand.vx v14, v14, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v14, v0.t
-; RV64-NEXT: vor.vv v8, v8, v12, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m2, ta, ma
+; RV64-NEXT: vsrl.vi v10, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a0
+; RV64-NEXT: vsrl.vx v14, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v14, v14, a2
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsrl.vi v14, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v10, v10, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v14, v14, a4
+; RV64-NEXT: vor.vv v10, v14, v10
+; RV64-NEXT: vand.vx v14, v8, a3
+; RV64-NEXT: vsll.vi v14, v14, 24
+; RV64-NEXT: vor.vv v10, v10, v12
+; RV64-NEXT: vand.vx v12, v8, a4
+; RV64-NEXT: vsll.vi v12, v12, 8
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsll.vx v14, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v14, v8
+; RV64-NEXT: vor.vv v8, v8, v12
+; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv2i64:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.bswap.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v
@@ -738,37 +738,37 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; RV32-NEXT: vsetvli a4, zero, e64, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v12, v8, a2
-; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: vsrl.vx v14, v8, a2
-; RV32-NEXT: vsrl.vx v16, v8, a4
-; RV32-NEXT: vand.vx v18, v8, a0
-; RV32-NEXT: vand.vx v16, v16, a0
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v16, v8, a1
+; RV32-NEXT: vand.vx v14, v14, a0
+; RV32-NEXT: vlse64.v v18, (a5), zero
+; RV32-NEXT: vor.vv v12, v14, v12
+; RV32-NEXT: vand.vx v14, v8, a0
+; RV32-NEXT: vsll.vx v14, v14, a2
; RV32-NEXT: vor.vv v14, v16, v14
-; RV32-NEXT: vlse64.v v16, (a6), zero
-; RV32-NEXT: vsll.vx v18, v18, a4
-; RV32-NEXT: vor.vv v12, v12, v18
-; RV32-NEXT: vsrl.vi v18, v8, 8
-; RV32-NEXT: vand.vx v10, v10, a5
-; RV32-NEXT: vand.vv v18, v18, v16
-; RV32-NEXT: vor.vv v10, v18, v10
-; RV32-NEXT: vand.vv v16, v8, v16
-; RV32-NEXT: vand.vx v8, v8, a5
+; RV32-NEXT: vsrl.vi v16, v8, 8
+; RV32-NEXT: vand.vx v10, v10, a4
+; RV32-NEXT: vand.vv v16, v16, v18
+; RV32-NEXT: vor.vv v10, v16, v10
+; RV32-NEXT: vand.vv v16, v8, v18
+; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vor.vv v8, v8, v16
-; RV32-NEXT: vor.vv v8, v12, v8
-; RV32-NEXT: vor.vv v10, v10, v14
+; RV32-NEXT: vor.vv v8, v14, v8
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -776,40 +776,40 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32
;
; RV64-LABEL: vp_bswap_nxv2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m2, ta, ma
; RV64-NEXT: vsrl.vi v10, v8, 24
-; RV64-NEXT: vsrl.vi v12, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v14, v8, a3
-; RV64-NEXT: vsrl.vx v16, v8, a5
-; RV64-NEXT: vand.vx v16, v16, a0
-; RV64-NEXT: vor.vv v14, v16, v14
-; RV64-NEXT: vand.vx v16, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v10, v10, a1
-; RV64-NEXT: vsll.vi v16, v16, 24
-; RV64-NEXT: vand.vx v12, v12, a2
-; RV64-NEXT: vor.vv v10, v12, v10
-; RV64-NEXT: vand.vx v12, v8, a2
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a0
+; RV64-NEXT: vsrl.vx v14, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v14, v14, a2
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsrl.vi v14, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v10, v10, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v14, v14, a4
+; RV64-NEXT: vor.vv v10, v14, v10
+; RV64-NEXT: vand.vx v14, v8, a3
+; RV64-NEXT: vsll.vi v14, v14, 24
+; RV64-NEXT: vor.vv v10, v10, v12
+; RV64-NEXT: vand.vx v12, v8, a4
; RV64-NEXT: vsll.vi v12, v12, 8
-; RV64-NEXT: vor.vv v12, v16, v12
-; RV64-NEXT: vsll.vx v16, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsll.vx v14, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v14, v8
; RV64-NEXT: vor.vv v8, v8, v12
-; RV64-NEXT: vor.vv v10, v10, v14
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv2i64_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.bswap.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
@@ -821,79 +821,79 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: vsetvli a4, zero, e64, m4, ta, ma
+; RV32-NEXT: vsrl.vi v12, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v20, v8, a2
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v20, v8, a0, v0.t
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: vsll.vx v20, v20, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vand.vx v20, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v20, v20, 24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v12, v0.t
-; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV32-NEXT: vor.vv v20, v20, v24, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a0, v0.t
-; RV32-NEXT: vor.vv v20, v24, v20, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vor.vv v8, v8, v20, v0.t
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsll.vx v24, v8, a1
+; RV32-NEXT: vand.vx v20, v20, a0
+; RV32-NEXT: vlse64.v v28, (a5), zero
+; RV32-NEXT: vor.vv v16, v20, v16
+; RV32-NEXT: vand.vx v20, v8, a0
+; RV32-NEXT: vsll.vx v20, v20, a2
+; RV32-NEXT: vor.vv v20, v24, v20
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vx v12, v12, a4
+; RV32-NEXT: vand.vv v24, v24, v28
+; RV32-NEXT: vor.vv v12, v24, v12
+; RV32-NEXT: vand.vv v24, v8, v28
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v24, v24, 8
+; RV32-NEXT: vor.vv v12, v12, v16
+; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vor.vv v8, v20, v8
+; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bswap_nxv4i64:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-NEXT: vand.vx v12, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV64-NEXT: vand.vx v16, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV64-NEXT: vor.vv v12, v12, v16, v0.t
-; RV64-NEXT: vsll.vx v16, v8, a3, v0.t
-; RV64-NEXT: vand.vx v20, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v20, v20, a5, v0.t
-; RV64-NEXT: vor.vv v16, v16, v20, v0.t
-; RV64-NEXT: vor.vv v12, v16, v12, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v20, v8, a5, v0.t
-; RV64-NEXT: vand.vx v20, v20, a0, v0.t
-; RV64-NEXT: vor.vv v16, v20, v16, v0.t
-; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t
-; RV64-NEXT: vand.vx v20, v20, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v20, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m4, ta, ma
+; RV64-NEXT: vsrl.vi v12, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v20, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v20, v20, a2
+; RV64-NEXT: vor.vv v16, v20, v16
+; RV64-NEXT: vsrl.vi v20, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v12, v12, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v20, v20, a4
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vand.vx v20, v8, a3
+; RV64-NEXT: vsll.vi v20, v20, 24
+; RV64-NEXT: vor.vv v12, v12, v16
+; RV64-NEXT: vand.vx v16, v8, a4
+; RV64-NEXT: vsll.vi v16, v16, 8
+; RV64-NEXT: vor.vv v16, v20, v16
+; RV64-NEXT: vsll.vx v20, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v20, v8
+; RV64-NEXT: vor.vv v8, v8, v16
+; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv4i64:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.bswap.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v
@@ -904,37 +904,37 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV32-NEXT: vsetvli a4, zero, e64, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v16, v8, a2
-; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vsrl.vx v20, v8, a2
-; RV32-NEXT: vsrl.vx v24, v8, a4
-; RV32-NEXT: vand.vx v28, v8, a0
-; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v24, v8, a1
+; RV32-NEXT: vand.vx v20, v20, a0
+; RV32-NEXT: vlse64.v v28, (a5), zero
+; RV32-NEXT: vor.vv v16, v20, v16
+; RV32-NEXT: vand.vx v20, v8, a0
+; RV32-NEXT: vsll.vx v20, v20, a2
; RV32-NEXT: vor.vv v20, v24, v20
-; RV32-NEXT: vlse64.v v24, (a6), zero
-; RV32-NEXT: vsll.vx v28, v28, a4
-; RV32-NEXT: vor.vv v16, v16, v28
-; RV32-NEXT: vsrl.vi v28, v8, 8
-; RV32-NEXT: vand.vx v12, v12, a5
-; RV32-NEXT: vand.vv v28, v28, v24
-; RV32-NEXT: vor.vv v12, v28, v12
-; RV32-NEXT: vand.vv v24, v8, v24
-; RV32-NEXT: vand.vx v8, v8, a5
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vx v12, v12, a4
+; RV32-NEXT: vand.vv v24, v24, v28
+; RV32-NEXT: vor.vv v12, v24, v12
+; RV32-NEXT: vand.vv v24, v8, v28
+; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v24, v24, 8
+; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vor.vv v8, v8, v24
-; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: vor.vv v12, v12, v20
+; RV32-NEXT: vor.vv v8, v20, v8
; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -942,40 +942,40 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32
;
; RV64-LABEL: vp_bswap_nxv4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m4, ta, ma
; RV64-NEXT: vsrl.vi v12, v8, 24
-; RV64-NEXT: vsrl.vi v16, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v20, v8, a3
-; RV64-NEXT: vsrl.vx v24, v8, a5
-; RV64-NEXT: vand.vx v24, v24, a0
-; RV64-NEXT: vor.vv v20, v24, v20
-; RV64-NEXT: vand.vx v24, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v12, v12, a1
-; RV64-NEXT: vsll.vi v24, v24, 24
-; RV64-NEXT: vand.vx v16, v16, a2
-; RV64-NEXT: vor.vv v12, v16, v12
-; RV64-NEXT: vand.vx v16, v8, a2
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v20, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v20, v20, a2
+; RV64-NEXT: vor.vv v16, v20, v16
+; RV64-NEXT: vsrl.vi v20, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v12, v12, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v20, v20, a4
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vand.vx v20, v8, a3
+; RV64-NEXT: vsll.vi v20, v20, 24
+; RV64-NEXT: vor.vv v12, v12, v16
+; RV64-NEXT: vand.vx v16, v8, a4
; RV64-NEXT: vsll.vi v16, v16, 8
-; RV64-NEXT: vor.vv v16, v24, v16
-; RV64-NEXT: vsll.vx v24, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v24, v8
+; RV64-NEXT: vor.vv v16, v20, v16
+; RV64-NEXT: vsll.vx v20, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v20, v8
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: vor.vv v12, v12, v20
; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv4i64_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.bswap.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
@@ -987,85 +987,58 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a4, 4080
; RV32-NEXT: addi a5, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a0, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a1, 4080
-; RV32-NEXT: vand.vx v16, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a0, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -1074,59 +1047,41 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
;
; RV64-LABEL: vp_bswap_nxv7i64:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v0, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vsrl.vi v0, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vand.vx v0, v8, a3
+; RV64-NEXT: vsll.vi v0, v0, 24
+; RV64-NEXT: vor.vv v16, v24, v16
+; RV64-NEXT: vand.vx v24, v8, a4
+; RV64-NEXT: vsll.vi v24, v24, 8
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vsll.vx v0, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
+; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv7i64:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.bswap.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v
@@ -1137,55 +1092,56 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v24, v8, a2
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vsrl.vx v16, v8, a2
-; RV32-NEXT: vsrl.vx v0, v8, a4
-; RV32-NEXT: vand.vx v0, v0, a0
-; RV32-NEXT: vor.vv v16, v0, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vand.vx v0, v8, a0
-; RV32-NEXT: vsll.vx v0, v0, a4
-; RV32-NEXT: vor.vv v16, v24, v0
-; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v0, (a6), zero
+; RV32-NEXT: vlse64.v v0, (a5), zero
; RV32-NEXT: vsrl.vi v16, v8, 24
-; RV32-NEXT: vand.vx v16, v16, a5
+; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v24, v24, v0
; RV32-NEXT: vor.vv v16, v24, v16
-; RV32-NEXT: vand.vv v24, v8, v0
-; RV32-NEXT: vand.vx v8, v8, a5
-; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v24, v24, 8
-; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v24, v8
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
@@ -1196,56 +1152,40 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32
;
; RV64-LABEL: vp_bswap_nxv7i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v16, v8, a3
-; RV64-NEXT: vsrl.vx v0, v8, a5
-; RV64-NEXT: vand.vx v0, v0, a0
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v0, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vsrl.vi v0, v8, 8
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v24, v24, a1
-; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
; RV64-NEXT: vor.vv v24, v0, v24
-; RV64-NEXT: vand.vx v0, v8, a1
+; RV64-NEXT: vand.vx v0, v8, a3
; RV64-NEXT: vsll.vi v0, v0, 24
-; RV64-NEXT: vand.vx v16, v8, a2
-; RV64-NEXT: vsll.vi v16, v16, 8
-; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: vsll.vx v0, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v0, v8
-; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v16, v24, v16
+; RV64-NEXT: vand.vx v24, v8, a4
+; RV64-NEXT: vsll.vi v24, v24, 8
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vsll.vx v0, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv7i64_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.bswap.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)
@@ -1257,85 +1197,58 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a4, 4080
; RV32-NEXT: addi a5, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a0, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a1, 4080
-; RV32-NEXT: vand.vx v16, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a0, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -1344,59 +1257,41 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
;
; RV64-LABEL: vp_bswap_nxv8i64:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v0, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vsrl.vi v0, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vand.vx v0, v8, a3
+; RV64-NEXT: vsll.vi v0, v0, 24
+; RV64-NEXT: vor.vv v16, v24, v16
+; RV64-NEXT: vand.vx v24, v8, a4
+; RV64-NEXT: vsll.vi v24, v24, 8
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vsll.vx v0, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
+; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv8i64:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.bswap.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v
@@ -1407,55 +1302,56 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v24, v8, a2
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vsrl.vx v16, v8, a2
-; RV32-NEXT: vsrl.vx v0, v8, a4
-; RV32-NEXT: vand.vx v0, v0, a0
-; RV32-NEXT: vor.vv v16, v0, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vand.vx v0, v8, a0
-; RV32-NEXT: vsll.vx v0, v0, a4
-; RV32-NEXT: vor.vv v16, v24, v0
-; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v0, (a6), zero
+; RV32-NEXT: vlse64.v v0, (a5), zero
; RV32-NEXT: vsrl.vi v16, v8, 24
-; RV32-NEXT: vand.vx v16, v16, a5
+; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v24, v24, v0
; RV32-NEXT: vor.vv v16, v24, v16
-; RV32-NEXT: vand.vv v24, v8, v0
-; RV32-NEXT: vand.vx v8, v8, a5
-; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v24, v24, 8
-; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v24, v8
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
@@ -1466,56 +1362,40 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
;
; RV64-LABEL: vp_bswap_nxv8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v16, v8, a3
-; RV64-NEXT: vsrl.vx v0, v8, a5
-; RV64-NEXT: vand.vx v0, v0, a0
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v0, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vsrl.vi v0, v8, 8
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v24, v24, a1
-; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
; RV64-NEXT: vor.vv v24, v0, v24
-; RV64-NEXT: vand.vx v0, v8, a1
+; RV64-NEXT: vand.vx v0, v8, a3
; RV64-NEXT: vsll.vi v0, v0, 24
-; RV64-NEXT: vand.vx v16, v8, a2
-; RV64-NEXT: vsll.vi v16, v16, 8
-; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: vsll.vx v0, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v0, v8
-; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v16, v24, v16
+; RV64-NEXT: vand.vx v24, v8, a4
+; RV64-NEXT: vsll.vi v24, v24, 8
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vsll.vx v0, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv8i64_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.bswap.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
@@ -1527,52 +1407,20 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv64i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
-; CHECK-NEXT: bltu a0, a1, .LBB32_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v24, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v24
+; CHECK-NEXT: vsrl.vi v24, v16, 8
+; CHECK-NEXT: vsll.vi v16, v16, 8
+; CHECK-NEXT: vor.vv v16, v16, v24
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-ZVKB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVKB-NEXT: csrr a1, vlenb
-; CHECK-ZVKB-NEXT: srli a2, a1, 1
-; CHECK-ZVKB-NEXT: slli a1, a1, 2
-; CHECK-ZVKB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVKB-NEXT: sub a2, a0, a1
-; CHECK-ZVKB-NEXT: sltu a3, a0, a2
-; CHECK-ZVKB-NEXT: addi a3, a3, -1
-; CHECK-ZVKB-NEXT: and a2, a3, a2
-; CHECK-ZVKB-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v16, v16, v0.t
-; CHECK-ZVKB-NEXT: bltu a0, a1, .LBB32_2
-; CHECK-ZVKB-NEXT: # %bb.1:
-; CHECK-ZVKB-NEXT: mv a0, a1
-; CHECK-ZVKB-NEXT: .LBB32_2:
-; CHECK-ZVKB-NEXT: vmv1r.v v0, v24
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: vrev8.v v16, v16
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 64 x i16> @llvm.vp.bswap.nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i16> %v
@@ -1581,42 +1429,20 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
define <vscale x 64 x i16> @vp_bswap_nxv64i16_unmasked(<vscale x 64 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv64i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 8
-; CHECK-NEXT: vsll.vi v16, v16, 8
-; CHECK-NEXT: vor.vv v16, v16, v24
-; CHECK-NEXT: bltu a0, a1, .LBB33_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB33_2:
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v24
+; CHECK-NEXT: vsrl.vi v24, v16, 8
+; CHECK-NEXT: vsll.vi v16, v16, 8
+; CHECK-NEXT: vor.vv v16, v16, v24
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16_unmasked:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: csrr a1, vlenb
-; CHECK-ZVKB-NEXT: slli a1, a1, 2
-; CHECK-ZVKB-NEXT: sub a2, a0, a1
-; CHECK-ZVKB-NEXT: sltu a3, a0, a2
-; CHECK-ZVKB-NEXT: addi a3, a3, -1
-; CHECK-ZVKB-NEXT: and a2, a3, a2
-; CHECK-ZVKB-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v16, v16
-; CHECK-ZVKB-NEXT: bltu a0, a1, .LBB33_2
-; CHECK-ZVKB-NEXT: # %bb.1:
-; CHECK-ZVKB-NEXT: mv a0, a1
-; CHECK-ZVKB-NEXT: .LBB33_2:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: vrev8.v v16, v16
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 64 x i16> @llvm.vp.bswap.nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> splat (i1 true), i32 %evl)
ret <vscale x 64 x i16> %v
@@ -1628,82 +1454,72 @@ define <vscale x 1 x i48> @vp_bswap_nxv1i48(<vscale x 1 x i48> %va, <vscale x 1
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: lui a2, 16
+; RV32-NEXT: vsetvli a3, zero, e64, m1, ta, ma
+; RV32-NEXT: vsll.vx v9, v8, a1
+; RV32-NEXT: li a1, 40
+; RV32-NEXT: addi a2, a2, -256
+; RV32-NEXT: vand.vx v10, v8, a2
+; RV32-NEXT: addi a2, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v9, v8, a2, v0.t
-; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v10, v8, a0, v0.t
-; RV32-NEXT: vlse64.v v11, (a6), zero
-; RV32-NEXT: vsll.vx v10, v10, a4, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vand.vx v10, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV32-NEXT: vand.vv v12, v8, v11, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t
-; RV32-NEXT: vand.vx v12, v12, a0, v0.t
-; RV32-NEXT: vor.vv v10, v12, v10, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
-; RV32-NEXT: vand.vx v12, v12, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v11, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v8, v10, v0.t
-; RV32-NEXT: vor.vv v8, v9, v8, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 16, v0.t
+; RV32-NEXT: vlse64.v v11, (a2), zero
+; RV32-NEXT: lui a0, 4080
+; RV32-NEXT: vsrl.vi v12, v8, 24
+; RV32-NEXT: vsll.vx v10, v10, a1
+; RV32-NEXT: vor.vv v9, v9, v10
+; RV32-NEXT: vsrl.vi v10, v8, 8
+; RV32-NEXT: vand.vv v10, v10, v11
+; RV32-NEXT: vand.vv v11, v8, v11
+; RV32-NEXT: vand.vx v8, v8, a0
+; RV32-NEXT: vand.vx v12, v12, a0
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v11, v11, 8
+; RV32-NEXT: vor.vv v8, v8, v11
+; RV32-NEXT: vor.vv v8, v9, v8
+; RV32-NEXT: vor.vv v9, v10, v12
+; RV32-NEXT: vor.vv v8, v8, v9
+; RV32-NEXT: vsrl.vi v8, v8, 16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bswap_nxv1i48:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v9, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
-; RV64-NEXT: vand.vx v10, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
-; RV64-NEXT: vor.vv v9, v9, v10, v0.t
-; RV64-NEXT: vsll.vx v10, v8, a3, v0.t
-; RV64-NEXT: vand.vx v11, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v11, v11, a5, v0.t
-; RV64-NEXT: vor.vv v10, v10, v11, v0.t
-; RV64-NEXT: vor.vv v9, v10, v9, v0.t
-; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v11, v8, a5, v0.t
-; RV64-NEXT: vand.vx v11, v11, a0, v0.t
-; RV64-NEXT: vor.vv v10, v11, v10, v0.t
-; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t
-; RV64-NEXT: vand.vx v11, v11, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v11, v0.t
-; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 16, v0.t
+; RV64-NEXT: lui a0, 4080
+; RV64-NEXT: li a1, 255
+; RV64-NEXT: li a2, 56
+; RV64-NEXT: vsetvli a3, zero, e64, m1, ta, ma
+; RV64-NEXT: vsll.vx v9, v8, a2
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vand.vx v10, v8, a0
+; RV64-NEXT: slli a1, a1, 24
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vsll.vi v10, v10, 24
+; RV64-NEXT: vand.vx v11, v8, a1
+; RV64-NEXT: vsll.vi v11, v11, 8
+; RV64-NEXT: vor.vv v10, v10, v11
+; RV64-NEXT: vand.vx v11, v8, a2
+; RV64-NEXT: li a2, 40
+; RV64-NEXT: vsll.vx v11, v11, a2
+; RV64-NEXT: vor.vv v9, v9, v11
+; RV64-NEXT: vsrl.vi v11, v8, 24
+; RV64-NEXT: vsrl.vi v8, v8, 8
+; RV64-NEXT: vand.vx v11, v11, a0
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vor.vv v9, v9, v10
+; RV64-NEXT: vor.vv v8, v8, v11
+; RV64-NEXT: vor.vv v8, v9, v8
+; RV64-NEXT: vsrl.vi v8, v8, 16
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv1i48:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t
-; CHECK-ZVKB-NEXT: vsrl.vi v8, v8, 16, v0.t
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: vsrl.vi v8, v8, 16
; CHECK-ZVKB-NEXT: ret
%v = call <vscale x 1 x i48> @llvm.vp.bswap.nxv1i48(<vscale x 1 x i48> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i48> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
index f436bbb9a66ca..05027b49da17c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
@@ -7,24 +7,24 @@
define <2 x i8> @vp_bitreverse_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vand.vi v9, v8, 15
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v9, v9, 4
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.bitreverse.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -33,7 +33,7 @@ define <2 x i8> @vp_bitreverse_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl)
define <2 x i8> @vp_bitreverse_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v2i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
@@ -59,24 +59,24 @@ define <2 x i8> @vp_bitreverse_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
define <4 x i8> @vp_bitreverse_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vand.vi v9, v8, 15
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v9, v9, 4
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.bitreverse.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v
@@ -85,7 +85,7 @@ define <4 x i8> @vp_bitreverse_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl)
define <4 x i8> @vp_bitreverse_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v4i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
@@ -111,24 +111,24 @@ define <4 x i8> @vp_bitreverse_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
define <8 x i8> @vp_bitreverse_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vand.vi v9, v8, 15
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v9, v9, 4
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.bitreverse.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v
@@ -137,7 +137,7 @@ define <8 x i8> @vp_bitreverse_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i8> @vp_bitreverse_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v8i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
@@ -163,24 +163,24 @@ define <8 x i8> @vp_bitreverse_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
define <16 x i8> @vp_bitreverse_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vand.vi v9, v8, 15
+; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
-; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v9, v9, 4
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.bitreverse.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v
@@ -189,7 +189,7 @@ define <16 x i8> @vp_bitreverse_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %
define <16 x i8> @vp_bitreverse_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v16i8_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15
; CHECK-NEXT: vsrl.vi v8, v8, 4
; CHECK-NEXT: li a0, 51
@@ -215,31 +215,31 @@ define <16 x i8> @vp_bitreverse_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl)
define <2 x i16> @vp_bitreverse_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.bitreverse.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -248,7 +248,7 @@ define <2 x i16> @vp_bitreverse_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %e
define <2 x i16> @vp_bitreverse_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
@@ -281,31 +281,31 @@ define <2 x i16> @vp_bitreverse_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl)
define <4 x i16> @vp_bitreverse_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.bitreverse.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -314,7 +314,7 @@ define <4 x i16> @vp_bitreverse_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %e
define <4 x i16> @vp_bitreverse_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
@@ -347,31 +347,31 @@ define <4 x i16> @vp_bitreverse_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl)
define <8 x i16> @vp_bitreverse_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.bitreverse.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -380,7 +380,7 @@ define <8 x i16> @vp_bitreverse_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %e
define <8 x i16> @vp_bitreverse_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
@@ -413,31 +413,31 @@ define <8 x i16> @vp_bitreverse_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl)
define <16 x i16> @vp_bitreverse_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vsrl.vi v10, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsrl.vi v10, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v10, v8
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.bitreverse.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -446,7 +446,7 @@ define <16 x i16> @vp_bitreverse_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroex
define <16 x i16> @vp_bitreverse_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: lui a0, 1
@@ -479,39 +479,39 @@ define <16 x i16> @vp_bitreverse_v16i16_unmasked(<16 x i16> %va, i32 zeroext %ev
define <2 x i32> @vp_bitreverse_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vor.vv v9, v9, v10
+; CHECK-NEXT: vsll.vi v10, v8, 24
+; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.bitreverse.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -520,7 +520,7 @@ define <2 x i32> @vp_bitreverse_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %e
define <2 x i32> @vp_bitreverse_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v10, v8, 24
@@ -561,39 +561,39 @@ define <2 x i32> @vp_bitreverse_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl)
define <4 x i32> @vp_bitreverse_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vor.vv v9, v9, v10
+; CHECK-NEXT: vsll.vi v10, v8, 24
+; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.bitreverse.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -602,7 +602,7 @@ define <4 x i32> @vp_bitreverse_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %e
define <4 x i32> @vp_bitreverse_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v10, v8, 24
@@ -643,39 +643,39 @@ define <4 x i32> @vp_bitreverse_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl)
define <8 x i32> @vp_bitreverse_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v12, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v10, v10, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0
+; CHECK-NEXT: vor.vv v10, v10, v12
+; CHECK-NEXT: vsll.vi v12, v8, 24
+; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v12, v8
+; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: vsrl.vi v10, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v10, v10, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v10, v8
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.bitreverse.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -684,7 +684,7 @@ define <8 x i32> @vp_bitreverse_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %e
define <8 x i32> @vp_bitreverse_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v12, v8, 24
@@ -725,39 +725,39 @@ define <8 x i32> @vp_bitreverse_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl)
define <16 x i32> @vp_bitreverse_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v16, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v12, v12, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0
+; CHECK-NEXT: vor.vv v12, v12, v16
+; CHECK-NEXT: vsll.vi v16, v8, 24
+; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v16, v8
+; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: vsrl.vi v12, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v12, v8
+; CHECK-NEXT: vsrl.vi v12, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v12, v8
+; CHECK-NEXT: vsrl.vi v12, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v12, v12, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v12, v8
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.bitreverse.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -766,7 +766,7 @@ define <16 x i32> @vp_bitreverse_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroex
define <16 x i32> @vp_bitreverse_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v16, v8, 24
@@ -809,203 +809,200 @@ define <2 x i64> @vp_bitreverse_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %e
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: lui a3, 16
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vlse64.v v9, (a6), zero
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v10, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v11, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v11, v11, a2, v0.t
-; RV32-NEXT: vor.vv v10, v10, v11, v0.t
-; RV32-NEXT: vand.vx v11, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v11, v11, 24, v0.t
-; RV32-NEXT: vand.vv v12, v8, v9, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV32-NEXT: vor.vv v11, v11, v12, v0.t
-; RV32-NEXT: vor.vv v10, v10, v11, v0.t
-; RV32-NEXT: vsrl.vx v11, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
+; RV32-NEXT: vsrl.vi v9, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsrl.vx v10, v8, a1
+; RV32-NEXT: vsrl.vx v11, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v12, v8, a1
+; RV32-NEXT: vand.vx v11, v11, a0
+; RV32-NEXT: vlse64.v v13, (a5), zero
+; RV32-NEXT: vor.vv v10, v11, v10
+; RV32-NEXT: vand.vx v11, v8, a0
+; RV32-NEXT: vsll.vx v11, v11, a2
+; RV32-NEXT: vor.vv v11, v12, v11
+; RV32-NEXT: vsrl.vi v12, v8, 8
+; RV32-NEXT: vand.vx v9, v9, a4
+; RV32-NEXT: vand.vv v12, v12, v13
+; RV32-NEXT: vor.vv v9, v12, v9
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vand.vv v12, v8, v13
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v12, v12, a5, v0.t
-; RV32-NEXT: vor.vv v11, v12, v11, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
-; RV32-NEXT: vand.vx v12, v12, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v9, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v9, a4
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32-NEXT: vsll.vi v12, v12, 8
+; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v12, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v11, v0.t
+; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32-NEXT: vor.vv v8, v11, v8
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v11, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
-; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t
-; RV32-NEXT: vand.vv v10, v10, v9, v0.t
-; RV32-NEXT: vand.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
-; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
-; RV32-NEXT: vand.vv v9, v9, v12, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v9, v8, v0.t
-; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
-; RV32-NEXT: vand.vv v9, v9, v11, v0.t
-; RV32-NEXT: vand.vv v8, v8, v11, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v9, v8, v0.t
-; RV32-NEXT: addi sp, sp, 16
-; RV32-NEXT: .cfi_def_cfa_offset 0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vp_bitreverse_v2i64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v9, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
-; RV64-NEXT: vand.vx v10, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
-; RV64-NEXT: vor.vv v9, v9, v10, v0.t
-; RV64-NEXT: vsll.vx v10, v8, a2, v0.t
-; RV64-NEXT: vand.vx v11, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v11, v11, a7, v0.t
-; RV64-NEXT: vor.vv v10, v10, v11, v0.t
-; RV64-NEXT: vor.vv v9, v10, v9, v0.t
-; RV64-NEXT: vsrl.vx v10, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v11, v8, a7, v0.t
-; RV64-NEXT: vand.vx v11, v11, a0, v0.t
-; RV64-NEXT: vor.vv v10, v11, v10, v0.t
-; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t
-; RV64-NEXT: vand.vx v11, v11, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vor.vv v8, v8, v11, v0.t
-; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
-; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
-; RV64-NEXT: vand.vx v9, v9, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
-; RV64-NEXT: vsrl.vi v9, v8, 2, v0.t
-; RV64-NEXT: vand.vx v9, v9, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
-; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t
-; RV64-NEXT: vand.vx v9, v9, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
-; RV64-NEXT: ret
- %v = call <2 x i64> @llvm.vp.bitreverse.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl)
- ret <2 x i64> %v
-}
-
-define <2 x i64> @vp_bitreverse_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
-; RV32-LABEL: vp_bitreverse_v2i64_unmasked:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v9
+; RV32-NEXT: vsrl.vi v9, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v10
+; RV32-NEXT: vand.vv v9, v9, v10
+; RV32-NEXT: vsll.vi v8, v8, 4
+; RV32-NEXT: vor.vv v8, v9, v8
+; RV32-NEXT: vsrl.vi v9, v8, 2
+; RV32-NEXT: vand.vv v8, v8, v12
+; RV32-NEXT: vand.vv v9, v9, v12
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vor.vv v8, v9, v8
+; RV32-NEXT: vsrl.vi v9, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v11
+; RV32-NEXT: vand.vv v9, v9, v11
+; RV32-NEXT: vadd.vv v8, v8, v8
+; RV32-NEXT: vor.vv v8, v9, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: .cfi_def_cfa_offset 0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vp_bitreverse_v2i64:
+; RV64: # %bb.0:
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64-NEXT: vsrl.vi v9, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v10, v8, a1
+; RV64-NEXT: vsrl.vx v11, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v11, v11, a2
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsrl.vi v11, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v9, v9, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v11, v11, a4
+; RV64-NEXT: vor.vv v9, v11, v9
+; RV64-NEXT: vand.vx v11, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v9, v9, v10
+; RV64-NEXT: vand.vx v10, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v11, v11, 24
+; RV64-NEXT: vsll.vi v10, v10, 8
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsll.vx v11, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v11, v8
+; RV64-NEXT: vor.vv v8, v8, v10
+; RV64-NEXT: vor.vv v8, v8, v9
+; RV64-NEXT: vsrl.vi v9, v8, 4
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v9, v9, a2
+; RV64-NEXT: vsll.vi v8, v8, 4
+; RV64-NEXT: vor.vv v8, v9, v8
+; RV64-NEXT: vsrl.vi v9, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v9, v9, a0
+; RV64-NEXT: vsll.vi v8, v8, 2
+; RV64-NEXT: vor.vv v8, v9, v8
+; RV64-NEXT: vsrl.vi v9, v8, 1
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v9, v9, a1
+; RV64-NEXT: vadd.vv v8, v8, v8
+; RV64-NEXT: vor.vv v8, v9, v8
+; RV64-NEXT: ret
+ %v = call <2 x i64> @llvm.vp.bitreverse.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl)
+ ret <2 x i64> %v
+}
+
+define <2 x i64> @vp_bitreverse_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
+; RV32-LABEL: vp_bitreverse_v2i64_unmasked:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v10, v8, a2
-; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: vsrl.vx v11, v8, a2
-; RV32-NEXT: vsrl.vx v12, v8, a4
-; RV32-NEXT: vand.vx v13, v8, a1
-; RV32-NEXT: vand.vx v12, v12, a1
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v12, v8, a1
+; RV32-NEXT: vand.vx v11, v11, a0
+; RV32-NEXT: vlse64.v v13, (a5), zero
+; RV32-NEXT: vor.vv v10, v11, v10
+; RV32-NEXT: vand.vx v11, v8, a0
+; RV32-NEXT: vsll.vx v11, v11, a2
; RV32-NEXT: vor.vv v11, v12, v11
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v13, v13, a4
-; RV32-NEXT: vor.vv v10, v10, v13
-; RV32-NEXT: vsrl.vi v13, v8, 8
-; RV32-NEXT: vand.vx v9, v9, a5
-; RV32-NEXT: vand.vv v13, v13, v12
-; RV32-NEXT: vor.vv v9, v13, v9
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vand.vv v12, v8, v12
-; RV32-NEXT: vand.vx v8, v8, a5
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vsrl.vi v12, v8, 8
+; RV32-NEXT: vand.vx v9, v9, a4
+; RV32-NEXT: vand.vv v12, v12, v13
+; RV32-NEXT: vor.vv v9, v12, v9
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vand.vv v12, v8, v13
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vor.vv v9, v9, v10
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v12, a1
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v9, v9, v11
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32-NEXT: vor.vv v8, v11, v8
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v11, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v8, v10, v8
-; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v10, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vsrl.vi v9, v8, 4
-; RV32-NEXT: vand.vv v8, v8, v12
-; RV32-NEXT: vand.vv v9, v9, v12
+; RV32-NEXT: vand.vv v8, v8, v10
+; RV32-NEXT: vand.vv v9, v9, v10
; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: vsrl.vi v9, v8, 2
-; RV32-NEXT: vand.vv v8, v8, v11
-; RV32-NEXT: vand.vv v9, v9, v11
+; RV32-NEXT: vand.vv v8, v8, v12
+; RV32-NEXT: vand.vv v9, v9, v12
; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: vsrl.vi v9, v8, 1
-; RV32-NEXT: vand.vv v8, v8, v10
-; RV32-NEXT: vand.vv v9, v9, v10
+; RV32-NEXT: vand.vv v8, v8, v11
+; RV32-NEXT: vand.vv v9, v9, v11
; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16
@@ -1014,60 +1011,60 @@ define <2 x i64> @vp_bitreverse_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl)
;
; RV64-LABEL: vp_bitreverse_v2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 24
-; RV64-NEXT: vsrl.vi v10, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v11, v8, a3
-; RV64-NEXT: vsrl.vx v12, v8, a5
-; RV64-NEXT: vand.vx v12, v12, a0
-; RV64-NEXT: vor.vv v11, v12, v11
-; RV64-NEXT: vand.vx v12, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v9, v9, a1
-; RV64-NEXT: vsll.vi v12, v12, 24
-; RV64-NEXT: vand.vx v10, v10, a2
-; RV64-NEXT: vor.vv v9, v10, v9
-; RV64-NEXT: vand.vx v10, v8, a2
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v10, v8, a1
+; RV64-NEXT: vsrl.vx v11, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v11, v11, a2
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsrl.vi v11, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v9, v9, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v11, v11, a4
+; RV64-NEXT: vor.vv v9, v11, v9
+; RV64-NEXT: vand.vx v11, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v9, v9, v10
+; RV64-NEXT: vand.vx v10, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v11, v11, 24
; RV64-NEXT: vsll.vi v10, v10, 8
-; RV64-NEXT: vor.vv v10, v12, v10
-; RV64-NEXT: vsll.vx v12, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v12, v8
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: vor.vv v9, v9, v11
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsll.vx v11, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v11, v8
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v9, v9, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v9, v9, a2
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: vsrl.vi v9, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vand.vx v9, v9, a1
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: vsrl.vi v9, v8, 1
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vand.vx v9, v9, a2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: ret
@@ -1080,131 +1077,130 @@ define <4 x i64> @vp_bitreverse_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %e
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: lui a3, 16
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vlse64.v v10, (a6), zero
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsll.vx v12, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v14, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v14, v14, a2, v0.t
-; RV32-NEXT: vor.vv v12, v12, v14, v0.t
-; RV32-NEXT: vand.vx v14, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v14, v14, 24, v0.t
-; RV32-NEXT: vand.vv v16, v8, v10, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v14, v14, v16, v0.t
-; RV32-NEXT: vor.vv v12, v12, v14, v0.t
-; RV32-NEXT: vsrl.vx v14, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsrl.vx v10, v8, a1
+; RV32-NEXT: vsrl.vx v12, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v18, v8, a1
+; RV32-NEXT: vand.vx v12, v12, a0
+; RV32-NEXT: vlse64.v v14, (a5), zero
+; RV32-NEXT: vor.vv v12, v12, v10
+; RV32-NEXT: vand.vx v10, v8, a0
+; RV32-NEXT: vsll.vx v10, v10, a2
+; RV32-NEXT: vor.vv v10, v18, v10
+; RV32-NEXT: vsrl.vi v18, v8, 8
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vand.vv v18, v18, v14
+; RV32-NEXT: vor.vv v16, v18, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vand.vv v14, v8, v14
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v16, v16, a5, v0.t
-; RV32-NEXT: vor.vv v14, v16, v14, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV32-NEXT: vand.vx v16, v16, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v10, a4
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vsll.vi v14, v14, 8
+; RV32-NEXT: vor.vv v8, v8, v14
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v14, v0.t
+; RV32-NEXT: vmv.v.x v14, a1
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v14, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
-; RV32-NEXT: vand.vv v12, v12, v10, v0.t
-; RV32-NEXT: vand.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
-; RV32-NEXT: vand.vv v10, v10, v16, v0.t
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
-; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
-; RV32-NEXT: vand.vv v10, v10, v14, v0.t
-; RV32-NEXT: vand.vv v8, v8, v14, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vmv.v.x v10, a2
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v12
+; RV32-NEXT: vsrl.vi v12, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: vand.vv v12, v12, v16
+; RV32-NEXT: vsll.vi v8, v8, 4
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vsrl.vi v12, v8, 2
+; RV32-NEXT: vand.vv v8, v8, v14
+; RV32-NEXT: vand.vv v12, v12, v14
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vsrl.vi v12, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v10
+; RV32-NEXT: vand.vv v10, v12, v10
+; RV32-NEXT: vadd.vv v8, v8, v8
+; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bitreverse_v4i64:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vand.vx v10, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV64-NEXT: vand.vx v12, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV64-NEXT: vor.vv v10, v10, v12, v0.t
-; RV64-NEXT: vsll.vx v12, v8, a2, v0.t
-; RV64-NEXT: vand.vx v14, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v14, v14, a7, v0.t
-; RV64-NEXT: vor.vv v12, v12, v14, v0.t
-; RV64-NEXT: vor.vv v10, v12, v10, v0.t
-; RV64-NEXT: vsrl.vx v12, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v14, v8, a7, v0.t
-; RV64-NEXT: vand.vx v14, v14, a0, v0.t
-; RV64-NEXT: vor.vv v12, v14, v12, v0.t
-; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t
-; RV64-NEXT: vand.vx v14, v14, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vor.vv v8, v8, v14, v0.t
-; RV64-NEXT: vor.vv v8, v8, v12, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
-; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
-; RV64-NEXT: vand.vx v10, v10, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
-; RV64-NEXT: vsrl.vi v10, v8, 2, v0.t
-; RV64-NEXT: vand.vx v10, v10, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
-; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t
-; RV64-NEXT: vand.vx v10, v10, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vsrl.vi v10, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a1
+; RV64-NEXT: vsrl.vx v14, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v14, v14, a2
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsrl.vi v14, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v10, v10, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v14, v14, a4
+; RV64-NEXT: vor.vv v10, v14, v10
+; RV64-NEXT: vand.vx v14, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v10, v10, v12
+; RV64-NEXT: vand.vx v12, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v14, v14, 24
+; RV64-NEXT: vsll.vi v12, v12, 8
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsll.vx v14, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v14, v8
+; RV64-NEXT: vor.vv v8, v8, v12
+; RV64-NEXT: vor.vv v8, v8, v10
+; RV64-NEXT: vsrl.vi v10, v8, 4
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v10, v10, a2
+; RV64-NEXT: vsll.vi v8, v8, 4
+; RV64-NEXT: vor.vv v8, v10, v8
+; RV64-NEXT: vsrl.vi v10, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v10, v10, a0
+; RV64-NEXT: vsll.vi v8, v8, 2
+; RV64-NEXT: vor.vv v8, v10, v8
+; RV64-NEXT: vsrl.vi v10, v8, 1
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v10, v10, a1
+; RV64-NEXT: vadd.vv v8, v8, v8
+; RV64-NEXT: vor.vv v8, v10, v8
; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.bitreverse.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -1215,68 +1211,66 @@ define <4 x i64> @vp_bitreverse_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl)
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsrl.vi v14, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v12, v8, a2
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vsrl.vx v10, v8, a2
-; RV32-NEXT: vsrl.vx v16, v8, a4
-; RV32-NEXT: vand.vx v18, v8, a1
-; RV32-NEXT: vand.vx v16, v16, a1
-; RV32-NEXT: vor.vv v10, v16, v10
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vlse64.v v16, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsll.vx v18, v18, a4
-; RV32-NEXT: vor.vv v12, v12, v18
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsrl.vx v10, v8, a1
+; RV32-NEXT: vsrl.vx v12, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v18, v8, a1
+; RV32-NEXT: vand.vx v12, v12, a0
+; RV32-NEXT: vlse64.v v14, (a5), zero
+; RV32-NEXT: vor.vv v12, v12, v10
+; RV32-NEXT: vand.vx v10, v8, a0
+; RV32-NEXT: vsll.vx v10, v10, a2
+; RV32-NEXT: vor.vv v10, v18, v10
; RV32-NEXT: vsrl.vi v18, v8, 8
-; RV32-NEXT: vand.vx v14, v14, a5
-; RV32-NEXT: vand.vv v18, v18, v16
-; RV32-NEXT: vor.vv v14, v18, v14
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vand.vv v16, v8, v16
-; RV32-NEXT: vand.vx v8, v8, a5
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vand.vv v18, v18, v14
+; RV32-NEXT: vor.vv v16, v18, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vand.vv v14, v8, v14
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v16, v16, 8
-; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v10, v14, v10
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vsll.vi v14, v14, 8
+; RV32-NEXT: vor.vv v8, v8, v14
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v14, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vmv.v.x v14, a1
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v12, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v10
-; RV32-NEXT: vsrl.vi v10, v8, 4
+; RV32-NEXT: vmv.v.x v10, a2
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v12
+; RV32-NEXT: vsrl.vi v12, v8, 4
; RV32-NEXT: vand.vv v8, v8, v16
-; RV32-NEXT: vand.vv v10, v10, v16
+; RV32-NEXT: vand.vv v12, v12, v16
; RV32-NEXT: vsll.vi v8, v8, 4
-; RV32-NEXT: vor.vv v8, v10, v8
-; RV32-NEXT: vsrl.vi v10, v8, 2
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vsrl.vi v12, v8, 2
; RV32-NEXT: vand.vv v8, v8, v14
-; RV32-NEXT: vand.vv v10, v10, v14
+; RV32-NEXT: vand.vv v12, v12, v14
; RV32-NEXT: vsll.vi v8, v8, 2
-; RV32-NEXT: vor.vv v8, v10, v8
-; RV32-NEXT: vsrl.vi v10, v8, 1
-; RV32-NEXT: vand.vv v8, v8, v12
-; RV32-NEXT: vand.vv v10, v10, v12
+; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vsrl.vi v12, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v10
+; RV32-NEXT: vand.vv v10, v12, v10
; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16
@@ -1285,60 +1279,60 @@ define <4 x i64> @vp_bitreverse_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl)
;
; RV64-LABEL: vp_bitreverse_v4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vsrl.vi v12, v8, 24
-; RV64-NEXT: vsrl.vi v14, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v10, v8, a3
-; RV64-NEXT: vsrl.vx v16, v8, a5
-; RV64-NEXT: vand.vx v16, v16, a0
-; RV64-NEXT: vor.vv v10, v16, v10
-; RV64-NEXT: vand.vx v16, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v12, v12, a1
-; RV64-NEXT: vsll.vi v16, v16, 24
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vsrl.vi v10, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a1
+; RV64-NEXT: vsrl.vx v14, v8, a0
+; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v14, v14, a2
; RV64-NEXT: vor.vv v12, v14, v12
-; RV64-NEXT: vand.vx v14, v8, a2
-; RV64-NEXT: vsll.vi v14, v14, 8
-; RV64-NEXT: vor.vv v14, v16, v14
-; RV64-NEXT: vsll.vx v16, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: vor.vv v10, v12, v10
-; RV64-NEXT: vor.vv v8, v8, v14
+; RV64-NEXT: vsrl.vi v14, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v10, v10, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v14, v14, a4
+; RV64-NEXT: vor.vv v10, v14, v10
+; RV64-NEXT: vand.vx v14, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v10, v10, v12
+; RV64-NEXT: vand.vx v12, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v14, v14, 24
+; RV64-NEXT: vsll.vi v12, v12, 8
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsll.vx v14, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v14, v8
+; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vsrl.vi v10, v8, 4
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v10, v10, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v10, v10, a2
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v10, v8
; RV64-NEXT: vsrl.vi v10, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vand.vx v10, v10, a1
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v10, v8
; RV64-NEXT: vsrl.vi v10, v8, 1
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vand.vx v10, v10, a2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v10, v10, a1
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vor.vv v8, v10, v8
; RV64-NEXT: ret
@@ -1351,131 +1345,130 @@ define <8 x i64> @vp_bitreverse_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %e
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: lui a3, 16
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v20, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v20, v20, a2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vand.vx v20, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v20, v20, 24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v12, v0.t
-; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV32-NEXT: vor.vv v20, v20, v24, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vx v20, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsrl.vx v12, v8, a1
+; RV32-NEXT: vsrl.vx v16, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v28, v8, a1
+; RV32-NEXT: vand.vx v16, v16, a0
+; RV32-NEXT: vlse64.v v20, (a5), zero
+; RV32-NEXT: vor.vv v16, v16, v12
+; RV32-NEXT: vand.vx v12, v8, a0
+; RV32-NEXT: vsll.vx v12, v12, a2
+; RV32-NEXT: vor.vv v12, v28, v12
+; RV32-NEXT: vsrl.vi v28, v8, 8
+; RV32-NEXT: vand.vx v24, v24, a4
+; RV32-NEXT: vand.vv v28, v28, v20
+; RV32-NEXT: vor.vv v24, v28, v24
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vand.vv v20, v8, v20
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v24, v24, a5, v0.t
-; RV32-NEXT: vor.vv v20, v24, v20, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v28, a4
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv.v.x v24, a0
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vsll.vi v20, v20, 8
+; RV32-NEXT: vor.vv v8, v8, v20
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v20, v8, v20, v0.t
+; RV32-NEXT: vmv.v.x v20, a1
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vi v20, v16, 4, v0.t
-; RV32-NEXT: vand.vv v20, v20, v28, v0.t
-; RV32-NEXT: vand.vv v16, v16, v28, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 4, v0.t
-; RV32-NEXT: vor.vv v16, v20, v16, v0.t
-; RV32-NEXT: vsrl.vi v20, v16, 2, v0.t
-; RV32-NEXT: vand.vv v20, v20, v12, v0.t
-; RV32-NEXT: vand.vv v12, v16, v12, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 2, v0.t
-; RV32-NEXT: vor.vv v12, v20, v12, v0.t
-; RV32-NEXT: vsrl.vi v16, v12, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v8, v12, v8, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vmv.v.x v12, a2
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vsrl.vi v16, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v24
+; RV32-NEXT: vand.vv v16, v16, v24
+; RV32-NEXT: vsll.vi v8, v8, 4
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 2
+; RV32-NEXT: vand.vv v8, v8, v20
+; RV32-NEXT: vand.vv v16, v16, v20
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v12
+; RV32-NEXT: vand.vv v12, v16, v12
+; RV32-NEXT: vadd.vv v8, v8, v8
+; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bitreverse_v8i64:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-NEXT: vand.vx v12, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV64-NEXT: vand.vx v16, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV64-NEXT: vor.vv v12, v12, v16, v0.t
-; RV64-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV64-NEXT: vand.vx v20, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v20, v20, a7, v0.t
-; RV64-NEXT: vor.vv v16, v16, v20, v0.t
-; RV64-NEXT: vor.vv v12, v16, v12, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v20, v8, a7, v0.t
-; RV64-NEXT: vand.vx v20, v20, a0, v0.t
-; RV64-NEXT: vor.vv v16, v20, v16, v0.t
-; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t
-; RV64-NEXT: vand.vx v20, v20, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vor.vv v8, v8, v20, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
-; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
-; RV64-NEXT: vand.vx v12, v12, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
-; RV64-NEXT: vsrl.vi v12, v8, 2, v0.t
-; RV64-NEXT: vand.vx v12, v12, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
-; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t
-; RV64-NEXT: vand.vx v12, v12, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vsrl.vi v16, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a1
+; RV64-NEXT: vsrl.vx v20, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v20, v20, a2
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vsrl.vi v20, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v16, v16, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v20, v20, a4
+; RV64-NEXT: vor.vv v20, v20, v16
+; RV64-NEXT: vand.vx v16, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vand.vx v20, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v16, v16, 24
+; RV64-NEXT: vsll.vi v20, v20, 8
+; RV64-NEXT: vor.vv v16, v16, v20
+; RV64-NEXT: vsll.vx v20, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v20, v8
+; RV64-NEXT: vor.vv v8, v8, v16
+; RV64-NEXT: vor.vv v8, v8, v12
+; RV64-NEXT: vsrl.vi v12, v8, 4
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v12, v12, a2
+; RV64-NEXT: vsll.vi v8, v8, 4
+; RV64-NEXT: vor.vv v8, v12, v8
+; RV64-NEXT: vsrl.vi v12, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v12, v12, a0
+; RV64-NEXT: vsll.vi v8, v8, 2
+; RV64-NEXT: vor.vv v8, v12, v8
+; RV64-NEXT: vsrl.vi v12, v8, 1
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v12, v12, a1
+; RV64-NEXT: vadd.vv v8, v8, v8
+; RV64-NEXT: vor.vv v8, v12, v8
; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.bitreverse.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -1486,68 +1479,66 @@ define <8 x i64> @vp_bitreverse_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl)
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsrl.vi v20, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v16, v8, a2
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vsrl.vx v12, v8, a2
-; RV32-NEXT: vsrl.vx v24, v8, a4
-; RV32-NEXT: vand.vx v28, v8, a1
-; RV32-NEXT: vand.vx v24, v24, a1
-; RV32-NEXT: vor.vv v12, v24, v12
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vlse64.v v24, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsll.vx v28, v28, a4
-; RV32-NEXT: vor.vv v16, v16, v28
+; RV32-NEXT: vsrl.vi v24, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsrl.vx v12, v8, a1
+; RV32-NEXT: vsrl.vx v16, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v28, v8, a1
+; RV32-NEXT: vand.vx v16, v16, a0
+; RV32-NEXT: vlse64.v v20, (a5), zero
+; RV32-NEXT: vor.vv v16, v16, v12
+; RV32-NEXT: vand.vx v12, v8, a0
+; RV32-NEXT: vsll.vx v12, v12, a2
+; RV32-NEXT: vor.vv v12, v28, v12
; RV32-NEXT: vsrl.vi v28, v8, 8
-; RV32-NEXT: vand.vx v20, v20, a5
-; RV32-NEXT: vand.vv v28, v28, v24
-; RV32-NEXT: vor.vv v20, v28, v20
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vand.vv v24, v8, v24
-; RV32-NEXT: vand.vx v8, v8, a5
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vand.vx v24, v24, a4
+; RV32-NEXT: vand.vv v28, v28, v20
+; RV32-NEXT: vor.vv v24, v28, v24
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vand.vv v20, v8, v20
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v24, v24, 8
-; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v12, v20, v12
+; RV32-NEXT: vmv.v.x v24, a0
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vsll.vi v20, v20, 8
+; RV32-NEXT: vor.vv v8, v8, v20
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v20, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vmv.v.x v20, a1
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v12
-; RV32-NEXT: vsrl.vi v12, v8, 4
+; RV32-NEXT: vmv.v.x v12, a2
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: vand.vv v8, v8, v24
-; RV32-NEXT: vand.vv v12, v12, v24
+; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vsll.vi v8, v8, 4
-; RV32-NEXT: vor.vv v8, v12, v8
-; RV32-NEXT: vsrl.vi v12, v8, 2
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 2
; RV32-NEXT: vand.vv v8, v8, v20
-; RV32-NEXT: vand.vv v12, v12, v20
+; RV32-NEXT: vand.vv v16, v16, v20
; RV32-NEXT: vsll.vi v8, v8, 2
-; RV32-NEXT: vor.vv v8, v12, v8
-; RV32-NEXT: vsrl.vi v12, v8, 1
-; RV32-NEXT: vand.vv v8, v8, v16
-; RV32-NEXT: vand.vv v12, v12, v16
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v12
+; RV32-NEXT: vand.vv v12, v16, v12
; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16
@@ -1556,60 +1547,60 @@ define <8 x i64> @vp_bitreverse_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl)
;
; RV64-LABEL: vp_bitreverse_v8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vsrl.vi v16, v8, 24
-; RV64-NEXT: vsrl.vi v20, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v12, v8, a3
-; RV64-NEXT: vsrl.vx v24, v8, a5
-; RV64-NEXT: vand.vx v24, v24, a0
-; RV64-NEXT: vor.vv v12, v24, v12
-; RV64-NEXT: vand.vx v24, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v16, v16, a1
-; RV64-NEXT: vsll.vi v24, v24, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a1
+; RV64-NEXT: vsrl.vx v20, v8, a0
+; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v20, v20, a2
-; RV64-NEXT: vor.vv v16, v20, v16
-; RV64-NEXT: vand.vx v20, v8, a2
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vsrl.vi v20, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v16, v16, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v20, v20, a4
+; RV64-NEXT: vor.vv v20, v20, v16
+; RV64-NEXT: vand.vx v16, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vand.vx v20, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v16, v16, 24
; RV64-NEXT: vsll.vi v20, v20, 8
-; RV64-NEXT: vor.vv v20, v24, v20
-; RV64-NEXT: vsll.vx v24, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v24, v8
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: vor.vv v12, v16, v12
-; RV64-NEXT: vor.vv v8, v8, v20
+; RV64-NEXT: vor.vv v16, v16, v20
+; RV64-NEXT: vsll.vx v20, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v20, v8
+; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vsrl.vi v12, v8, 4
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v12, v12, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v12, v12, a2
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v12, v8
; RV64-NEXT: vsrl.vi v12, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vand.vx v12, v12, a1
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v12, v12, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v12, v8
; RV64-NEXT: vsrl.vi v12, v8, 1
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vand.vx v12, v12, a2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v12, v12, a1
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vor.vv v8, v12, v8
; RV64-NEXT: ret
@@ -1622,117 +1613,88 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a4, 4080
; RV32-NEXT: addi a5, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vsrl.vi v24, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: vand.vv v16, v24, v16
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 4, v0.t
-; RV32-NEXT: vor.vv v24, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vsll.vi v8, v8, 4
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 2
+; RV32-NEXT: vand.vv v8, v8, v24
+; RV32-NEXT: vand.vv v16, v16, v24
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v24
+; RV32-NEXT: vand.vv v16, v16, v24
+; RV32-NEXT: vadd.vv v8, v8, v8
+; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -1741,80 +1703,62 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
;
; RV64-LABEL: vp_bitreverse_v15i64:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vand.vx v8, v8, a0, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vand.vx v8, v8, a1, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a1
+; RV64-NEXT: vsrl.vx v0, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vsrl.vi v0, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v0, v0, v24
+; RV64-NEXT: vand.vx v24, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vand.vx v0, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v24, v24, 24
+; RV64-NEXT: vsll.vi v0, v0, 8
+; RV64-NEXT: vor.vv v24, v24, v0
+; RV64-NEXT: vsll.vx v0, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
+; RV64-NEXT: vor.vv v8, v8, v16
+; RV64-NEXT: vsrl.vi v16, v8, 4
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v16, v16, a2
+; RV64-NEXT: vsll.vi v8, v8, 4
+; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: vsrl.vi v16, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v16, v16, a0
+; RV64-NEXT: vsll.vi v8, v8, 2
+; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: vsrl.vi v16, v8, 1
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v16, v16, a1
+; RV64-NEXT: vadd.vv v8, v8, v8
+; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.bitreverse.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v
@@ -1825,81 +1769,79 @@ define <15 x i64> @vp_bitreverse_v15i64_unmasked(<15 x i64> %va, i32 zeroext %ev
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2
-; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vsrl.vx v24, v8, a2
-; RV32-NEXT: vsrl.vx v0, v8, a4
-; RV32-NEXT: vand.vx v0, v0, a1
-; RV32-NEXT: vor.vv v24, v0, v24
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vand.vx v24, v8, a1
-; RV32-NEXT: vsll.vx v24, v24, a4
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v24, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 24
-; RV32-NEXT: vand.vx v16, v16, a5
-; RV32-NEXT: vsrl.vi v0, v8, 8
-; RV32-NEXT: vand.vv v0, v0, v24
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
; RV32-NEXT: vor.vv v16, v0, v16
-; RV32-NEXT: vand.vv v24, v8, v24
-; RV32-NEXT: vand.vx v8, v8, a5
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v24, v24, 8
-; RV32-NEXT: vor.vv v24, v8, v24
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 3
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vsrl.vi v24, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: vand.vv v16, v24, v16
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: vsrl.vi v16, v8, 4
-; RV32-NEXT: vand.vv v8, v8, v24
-; RV32-NEXT: vand.vv v16, v16, v24
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 2
; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vand.vv v16, v16, v24
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 1
@@ -1917,78 +1859,62 @@ define <15 x i64> @vp_bitreverse_v15i64_unmasked(<15 x i64> %va, i32 zeroext %ev
;
; RV64-LABEL: vp_bitreverse_v15i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v16, v8, a3
-; RV64-NEXT: vsrl.vx v0, v8, a5
-; RV64-NEXT: vand.vx v0, v0, a0
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a1
+; RV64-NEXT: vsrl.vx v0, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vsrl.vi v0, v8, 8
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v24, v24, a1
-; RV64-NEXT: vand.vx v0, v0, a2
-; RV64-NEXT: vor.vv v24, v0, v24
-; RV64-NEXT: vand.vx v0, v8, a1
-; RV64-NEXT: vsll.vi v0, v0, 24
-; RV64-NEXT: vand.vx v16, v8, a2
-; RV64-NEXT: vsll.vi v16, v16, 8
-; RV64-NEXT: vor.vv v0, v0, v16
-; RV64-NEXT: vsll.vx v16, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v24, v16
-; RV64-NEXT: vor.vv v8, v8, v0
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v0, v0, v24
+; RV64-NEXT: vand.vx v24, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vand.vx v0, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v24, v24, 24
+; RV64-NEXT: vsll.vi v0, v0, 8
+; RV64-NEXT: vor.vv v24, v24, v0
+; RV64-NEXT: vsll.vx v0, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 4
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v16, v16, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v16, v16, a2
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: vsrl.vi v16, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vand.vx v16, v16, a1
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: vsrl.vi v16, v8, 1
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vand.vx v16, v16, a2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v16, v16, a1
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.bitreverse.v15i64(<15 x i64> %va, <15 x i1> splat (i1 true), i32 %evl)
ret <15 x i64> %v
@@ -1999,117 +1925,88 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a4, 4080
; RV32-NEXT: addi a5, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vsrl.vi v24, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: vand.vv v16, v24, v16
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 4, v0.t
-; RV32-NEXT: vor.vv v24, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vsll.vi v8, v8, 4
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 2
+; RV32-NEXT: vand.vv v8, v8, v24
+; RV32-NEXT: vand.vv v16, v16, v24
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vsrl.vi v16, v8, 1
+; RV32-NEXT: vand.vv v8, v8, v24
+; RV32-NEXT: vand.vv v16, v16, v24
+; RV32-NEXT: vadd.vv v8, v8, v8
+; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -2118,80 +2015,62 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
;
; RV64-LABEL: vp_bitreverse_v16i64:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vand.vx v8, v8, a0, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vand.vx v8, v8, a1, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a1
+; RV64-NEXT: vsrl.vx v0, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vsrl.vi v0, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v0, v0, v24
+; RV64-NEXT: vand.vx v24, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vand.vx v0, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v24, v24, 24
+; RV64-NEXT: vsll.vi v0, v0, 8
+; RV64-NEXT: vor.vv v24, v24, v0
+; RV64-NEXT: vsll.vx v0, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
+; RV64-NEXT: vor.vv v8, v8, v16
+; RV64-NEXT: vsrl.vi v16, v8, 4
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v16, v16, a2
+; RV64-NEXT: vsll.vi v8, v8, 4
+; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: vsrl.vi v16, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v16, v16, a0
+; RV64-NEXT: vsll.vi v8, v8, 2
+; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: vsrl.vi v16, v8, 1
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v16, v16, a1
+; RV64-NEXT: vadd.vv v8, v8, v8
+; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.bitreverse.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -2202,81 +2081,79 @@ define <16 x i64> @vp_bitreverse_v16i64_unmasked(<16 x i64> %va, i32 zeroext %ev
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2
-; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vsrl.vx v24, v8, a2
-; RV32-NEXT: vsrl.vx v0, v8, a4
-; RV32-NEXT: vand.vx v0, v0, a1
-; RV32-NEXT: vor.vv v24, v0, v24
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vand.vx v24, v8, a1
-; RV32-NEXT: vsll.vx v24, v24, a4
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v24, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 24
-; RV32-NEXT: vand.vx v16, v16, a5
-; RV32-NEXT: vsrl.vi v0, v8, 8
-; RV32-NEXT: vand.vv v0, v0, v24
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
; RV32-NEXT: vor.vv v16, v0, v16
-; RV32-NEXT: vand.vv v24, v8, v24
-; RV32-NEXT: vand.vx v8, v8, a5
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v24, v24, 8
-; RV32-NEXT: vor.vv v24, v8, v24
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: addi a2, a2, 1365
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: lui a1, 61681
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: addi a1, a1, -241
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 3
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vsrl.vi v24, v8, 4
+; RV32-NEXT: vand.vv v8, v8, v16
+; RV32-NEXT: vand.vv v16, v24, v16
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: vsrl.vi v16, v8, 4
-; RV32-NEXT: vand.vv v8, v8, v24
-; RV32-NEXT: vand.vv v16, v16, v24
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 2
; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vand.vv v16, v16, v24
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 1
@@ -2294,78 +2171,62 @@ define <16 x i64> @vp_bitreverse_v16i64_unmasked(<16 x i64> %va, i32 zeroext %ev
;
; RV64-LABEL: vp_bitreverse_v16i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: li a1, 56
+; RV64-NEXT: li a0, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v16, v8, a3
-; RV64-NEXT: vsrl.vx v0, v8, a5
-; RV64-NEXT: vand.vx v0, v0, a0
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a1
+; RV64-NEXT: vsrl.vx v0, v8, a0
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vsrl.vi v0, v8, 8
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v24, v24, a1
-; RV64-NEXT: vand.vx v0, v0, a2
-; RV64-NEXT: vor.vv v24, v0, v24
-; RV64-NEXT: vand.vx v0, v8, a1
-; RV64-NEXT: vsll.vi v0, v0, 24
-; RV64-NEXT: vand.vx v16, v8, a2
-; RV64-NEXT: vsll.vi v16, v16, 8
-; RV64-NEXT: vor.vv v0, v0, v16
-; RV64-NEXT: vsll.vx v16, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: lui a1, 209715
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: addi a0, a0, -241
-; RV64-NEXT: addi a1, a1, 819
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: slli a4, a1, 32
-; RV64-NEXT: add a0, a0, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a1, a1, a4
-; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v24, v16
-; RV64-NEXT: vor.vv v8, v8, v0
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v0, v0, v24
+; RV64-NEXT: vand.vx v24, v8, a3
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vand.vx v0, v8, a4
+; RV64-NEXT: lui a4, 209715
+; RV64-NEXT: vsll.vi v24, v24, 24
+; RV64-NEXT: vsll.vi v0, v0, 8
+; RV64-NEXT: vor.vv v24, v24, v0
+; RV64-NEXT: vsll.vx v0, v8, a1
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 819
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: vsll.vx v8, v8, a0
+; RV64-NEXT: slli a0, a4, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a1, 32
+; RV64-NEXT: add a0, a4, a0
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 4
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v16, v16, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vand.vx v16, v16, a2
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: vsrl.vi v16, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vand.vx v16, v16, a1
+; RV64-NEXT: vand.vx v8, v8, a0
+; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v16, v8
; RV64-NEXT: vsrl.vi v16, v8, 1
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vand.vx v16, v16, a2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vand.vx v16, v16, a1
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.bitreverse.v16i64(<16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i64> %v
@@ -2374,63 +2235,50 @@ define <16 x i64> @vp_bitreverse_v16i64_unmasked(<16 x i64> %va, i32 zeroext %ev
define <128 x i16> @vp_bitreverse_v128i16(<128 x i16> %va, <128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v128i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v7, v0, 8
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB34_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: .LBB34_2:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t
+; CHECK-NEXT: li a0, 64
; CHECK-NEXT: lui a1, 1
; CHECK-NEXT: lui a2, 3
-; CHECK-NEXT: addi a3, a0, -64
-; CHECK-NEXT: sltu a0, a0, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a3, a0, a3
-; CHECK-NEXT: lui a0, 5
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a1, a1, -241
-; CHECK-NEXT: addi a2, a2, 819
-; CHECK-NEXT: addi a0, a0, 1365
-; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
-; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
-; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
-; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
+; CHECK-NEXT: lui a3, 5
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v24, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: addi a0, a1, -241
+; CHECK-NEXT: addi a1, a2, 819
+; CHECK-NEXT: addi a2, a3, 1365
+; CHECK-NEXT: vor.vv v8, v8, v24
+; CHECK-NEXT: vsrl.vi v24, v16, 8
+; CHECK-NEXT: vsll.vi v16, v16, 8
+; CHECK-NEXT: vor.vv v16, v16, v24
+; CHECK-NEXT: vsrl.vi v24, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v24, v24, a0
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vsrl.vi v24, v16, 4
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: vand.vx v24, v24, a0
+; CHECK-NEXT: vsll.vi v16, v16, 4
+; CHECK-NEXT: vor.vv v16, v24, v16
+; CHECK-NEXT: vsrl.vi v24, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vand.vx v24, v24, a1
+; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vsrl.vi v24, v16, 2
+; CHECK-NEXT: vand.vx v16, v16, a1
+; CHECK-NEXT: vand.vx v24, v24, a1
+; CHECK-NEXT: vsll.vi v16, v16, 2
+; CHECK-NEXT: vor.vv v16, v24, v16
+; CHECK-NEXT: vsrl.vi v24, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a2
+; CHECK-NEXT: vand.vx v24, v24, a2
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vsrl.vi v24, v16, 1
+; CHECK-NEXT: vand.vx v16, v16, a2
+; CHECK-NEXT: vand.vx v24, v24, a2
+; CHECK-NEXT: vadd.vv v16, v16, v16
+; CHECK-NEXT: vor.vv v16, v24, v16
; CHECK-NEXT: ret
%v = call <128 x i16> @llvm.vp.bitreverse.v128i16(<128 x i16> %va, <128 x i1> %m, i32 %evl)
ret <128 x i16> %v
@@ -2439,62 +2287,48 @@ define <128 x i16> @vp_bitreverse_v128i16(<128 x i16> %va, <128 x i1> %m, i32 ze
define <128 x i16> @vp_bitreverse_v128i16_unmasked(<128 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_v128i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB35_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: .LBB35_2:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: li a0, 64
+; CHECK-NEXT: lui a1, 1
+; CHECK-NEXT: lui a2, 3
+; CHECK-NEXT: lui a3, 5
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
-; CHECK-NEXT: lui a2, 1
-; CHECK-NEXT: lui a3, 3
-; CHECK-NEXT: addi a4, a0, -64
-; CHECK-NEXT: sltu a0, a0, a4
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a4
-; CHECK-NEXT: lui a4, 5
+; CHECK-NEXT: addi a0, a1, -241
+; CHECK-NEXT: addi a1, a2, 819
+; CHECK-NEXT: addi a2, a3, 1365
; CHECK-NEXT: vor.vv v8, v8, v24
-; CHECK-NEXT: addi a2, a2, -241
-; CHECK-NEXT: addi a3, a3, 819
-; CHECK-NEXT: addi a4, a4, 1365
-; CHECK-NEXT: vsrl.vi v24, v8, 4
-; CHECK-NEXT: vand.vx v8, v8, a2
-; CHECK-NEXT: vand.vx v24, v24, a2
-; CHECK-NEXT: vsll.vi v8, v8, 4
-; CHECK-NEXT: vor.vv v8, v24, v8
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 8
; CHECK-NEXT: vsll.vi v16, v16, 8
; CHECK-NEXT: vor.vv v16, v16, v24
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v8, 2
-; CHECK-NEXT: vand.vx v8, v8, a3
-; CHECK-NEXT: vand.vx v24, v24, a3
-; CHECK-NEXT: vsll.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v24, v8, 4
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vand.vx v24, v24, a0
+; CHECK-NEXT: vsll.vi v8, v8, 4
; CHECK-NEXT: vor.vv v8, v24, v8
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 4
-; CHECK-NEXT: vand.vx v16, v16, a2
-; CHECK-NEXT: vand.vx v24, v24, a2
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: vand.vx v24, v24, a0
; CHECK-NEXT: vsll.vi v16, v16, 4
; CHECK-NEXT: vor.vv v16, v24, v16
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v8, 1
-; CHECK-NEXT: vand.vx v8, v8, a4
-; CHECK-NEXT: vand.vx v24, v24, a4
-; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vsrl.vi v24, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vand.vx v24, v24, a1
+; CHECK-NEXT: vsll.vi v8, v8, 2
; CHECK-NEXT: vor.vv v8, v24, v8
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 2
-; CHECK-NEXT: vand.vx v16, v16, a3
-; CHECK-NEXT: vand.vx v24, v24, a3
+; CHECK-NEXT: vand.vx v16, v16, a1
+; CHECK-NEXT: vand.vx v24, v24, a1
; CHECK-NEXT: vsll.vi v16, v16, 2
; CHECK-NEXT: vor.vv v16, v24, v16
+; CHECK-NEXT: vsrl.vi v24, v8, 1
+; CHECK-NEXT: vand.vx v8, v8, a2
+; CHECK-NEXT: vand.vx v24, v24, a2
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vor.vv v8, v24, v8
; CHECK-NEXT: vsrl.vi v24, v16, 1
-; CHECK-NEXT: vand.vx v16, v16, a4
-; CHECK-NEXT: vand.vx v24, v24, a4
+; CHECK-NEXT: vand.vx v16, v16, a2
+; CHECK-NEXT: vand.vx v24, v24, a2
; CHECK-NEXT: vadd.vv v16, v16, v16
; CHECK-NEXT: vor.vv v16, v24, v16
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
index eca94ccb9bf7f..c946d55d21b7f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
@@ -7,10 +7,10 @@
define <2 x i16> @vp_bswap_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.bswap.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -19,7 +19,7 @@ define <2 x i16> @vp_bswap_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i16> @vp_bswap_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v9
@@ -31,10 +31,10 @@ define <2 x i16> @vp_bswap_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
define <4 x i16> @vp_bswap_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.bswap.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -43,7 +43,7 @@ define <4 x i16> @vp_bswap_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i16> @vp_bswap_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v4i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v9
@@ -55,10 +55,10 @@ define <4 x i16> @vp_bswap_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
define <8 x i16> @vp_bswap_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.bswap.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -67,7 +67,7 @@ define <8 x i16> @vp_bswap_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i16> @vp_bswap_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v8i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v9
@@ -79,10 +79,10 @@ define <8 x i16> @vp_bswap_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
define <16 x i16> @vp_bswap_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vsrl.vi v10, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.bswap.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v
@@ -91,7 +91,7 @@ define <16 x i16> @vp_bswap_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %ev
define <16 x i16> @vp_bswap_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v16i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v10
@@ -103,18 +103,18 @@ define <16 x i16> @vp_bswap_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
define <2 x i32> @vp_bswap_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vor.vv v9, v9, v10
+; CHECK-NEXT: vand.vx v10, v8, a0
+; CHECK-NEXT: vsll.vi v10, v10, 8
+; CHECK-NEXT: vsll.vi v8, v8, 24
+; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.bswap.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -123,7 +123,7 @@ define <2 x i32> @vp_bswap_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
define <2 x i32> @vp_bswap_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v10, v8, 24
@@ -143,18 +143,18 @@ define <2 x i32> @vp_bswap_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
define <4 x i32> @vp_bswap_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0
+; CHECK-NEXT: vor.vv v9, v9, v10
+; CHECK-NEXT: vand.vx v10, v8, a0
+; CHECK-NEXT: vsll.vi v10, v10, 8
+; CHECK-NEXT: vsll.vi v8, v8, 24
+; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.bswap.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -163,7 +163,7 @@ define <4 x i32> @vp_bswap_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
define <4 x i32> @vp_bswap_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v4i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v10, v8, 24
@@ -183,18 +183,18 @@ define <4 x i32> @vp_bswap_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
define <8 x i32> @vp_bswap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v12, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v10, v10, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0
+; CHECK-NEXT: vor.vv v10, v10, v12
+; CHECK-NEXT: vand.vx v12, v8, a0
+; CHECK-NEXT: vsll.vi v12, v12, 8
+; CHECK-NEXT: vsll.vi v8, v8, 24
+; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.bswap.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -203,7 +203,7 @@ define <8 x i32> @vp_bswap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i32> @vp_bswap_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v8i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v12, v8, 24
@@ -223,18 +223,18 @@ define <8 x i32> @vp_bswap_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
define <16 x i32> @vp_bswap_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v16, v8, 24
; CHECK-NEXT: addi a0, a0, -256
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v12, v12, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0
+; CHECK-NEXT: vor.vv v12, v12, v16
+; CHECK-NEXT: vand.vx v16, v8, a0
+; CHECK-NEXT: vsll.vi v16, v16, 8
+; CHECK-NEXT: vsll.vi v8, v8, 24
+; CHECK-NEXT: vor.vv v8, v8, v16
+; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.bswap.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v
@@ -243,7 +243,7 @@ define <16 x i32> @vp_bswap_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %ev
define <16 x i32> @vp_bswap_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v16i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: vsrl.vi v16, v8, 24
@@ -265,75 +265,73 @@ define <2 x i64> @vp_bswap_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v9, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v10, v8, a1, v0.t
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vlse64.v v11, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v10, v10, a4, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vand.vx v10, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV32-NEXT: vand.vv v12, v8, v11, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t
-; RV32-NEXT: vand.vx v12, v12, a1, v0.t
-; RV32-NEXT: vor.vv v10, v12, v10, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
-; RV32-NEXT: vand.vx v12, v12, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v11, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v8, v10, v0.t
-; RV32-NEXT: vor.vv v8, v9, v8, v0.t
+; RV32-NEXT: vsrl.vi v9, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsrl.vx v10, v8, a1
+; RV32-NEXT: vsrl.vx v11, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v12, v8, a1
+; RV32-NEXT: vand.vx v11, v11, a0
+; RV32-NEXT: vlse64.v v13, (a5), zero
+; RV32-NEXT: vor.vv v10, v11, v10
+; RV32-NEXT: vand.vx v11, v8, a0
+; RV32-NEXT: vsll.vx v11, v11, a2
+; RV32-NEXT: vor.vv v11, v12, v11
+; RV32-NEXT: vsrl.vi v12, v8, 8
+; RV32-NEXT: vand.vx v9, v9, a4
+; RV32-NEXT: vand.vv v12, v12, v13
+; RV32-NEXT: vor.vv v9, v12, v9
+; RV32-NEXT: vand.vv v12, v8, v13
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v12, v12, 8
+; RV32-NEXT: vor.vv v9, v9, v10
+; RV32-NEXT: vor.vv v8, v8, v12
+; RV32-NEXT: vor.vv v8, v11, v8
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bswap_v2i64:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v9, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
-; RV64-NEXT: vand.vx v10, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
-; RV64-NEXT: vor.vv v9, v9, v10, v0.t
-; RV64-NEXT: vsll.vx v10, v8, a3, v0.t
-; RV64-NEXT: vand.vx v11, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v11, v11, a5, v0.t
-; RV64-NEXT: vor.vv v10, v10, v11, v0.t
-; RV64-NEXT: vor.vv v9, v10, v9, v0.t
-; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v11, v8, a5, v0.t
-; RV64-NEXT: vand.vx v11, v11, a0, v0.t
-; RV64-NEXT: vor.vv v10, v11, v10, v0.t
-; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t
-; RV64-NEXT: vand.vx v11, v11, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v11, v0.t
-; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64-NEXT: vsrl.vi v9, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v10, v8, a0
+; RV64-NEXT: vsrl.vx v11, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v11, v11, a2
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsrl.vi v11, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v9, v9, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v11, v11, a4
+; RV64-NEXT: vor.vv v9, v11, v9
+; RV64-NEXT: vand.vx v11, v8, a3
+; RV64-NEXT: vsll.vi v11, v11, 24
+; RV64-NEXT: vor.vv v9, v9, v10
+; RV64-NEXT: vand.vx v10, v8, a4
+; RV64-NEXT: vsll.vi v10, v10, 8
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsll.vx v11, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v11, v8
+; RV64-NEXT: vor.vv v8, v8, v10
+; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.bswap.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v
@@ -344,39 +342,37 @@ define <2 x i64> @vp_bswap_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v10, v8, a2
-; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: vsrl.vx v11, v8, a2
-; RV32-NEXT: vsrl.vx v12, v8, a4
-; RV32-NEXT: vand.vx v13, v8, a1
-; RV32-NEXT: vand.vx v12, v12, a1
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v12, v8, a1
+; RV32-NEXT: vand.vx v11, v11, a0
+; RV32-NEXT: vlse64.v v13, (a5), zero
+; RV32-NEXT: vor.vv v10, v11, v10
+; RV32-NEXT: vand.vx v11, v8, a0
+; RV32-NEXT: vsll.vx v11, v11, a2
; RV32-NEXT: vor.vv v11, v12, v11
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v13, v13, a4
-; RV32-NEXT: vor.vv v10, v10, v13
-; RV32-NEXT: vsrl.vi v13, v8, 8
-; RV32-NEXT: vand.vx v9, v9, a5
-; RV32-NEXT: vand.vv v13, v13, v12
-; RV32-NEXT: vor.vv v9, v13, v9
-; RV32-NEXT: vand.vv v12, v8, v12
-; RV32-NEXT: vand.vx v8, v8, a5
+; RV32-NEXT: vsrl.vi v12, v8, 8
+; RV32-NEXT: vand.vx v9, v9, a4
+; RV32-NEXT: vand.vv v12, v12, v13
+; RV32-NEXT: vor.vv v9, v12, v9
+; RV32-NEXT: vand.vv v12, v8, v13
+; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v12, v12, 8
+; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vor.vv v8, v8, v12
-; RV32-NEXT: vor.vv v8, v10, v8
-; RV32-NEXT: vor.vv v9, v9, v11
+; RV32-NEXT: vor.vv v8, v11, v8
; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -384,34 +380,34 @@ define <2 x i64> @vp_bswap_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
;
; RV64-LABEL: vp_bswap_v2i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 24
-; RV64-NEXT: vsrl.vi v10, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v11, v8, a3
-; RV64-NEXT: vsrl.vx v12, v8, a5
-; RV64-NEXT: vand.vx v12, v12, a0
-; RV64-NEXT: vor.vv v11, v12, v11
-; RV64-NEXT: vand.vx v12, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v9, v9, a1
-; RV64-NEXT: vsll.vi v12, v12, 24
-; RV64-NEXT: vand.vx v10, v10, a2
-; RV64-NEXT: vor.vv v9, v10, v9
-; RV64-NEXT: vand.vx v10, v8, a2
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v10, v8, a0
+; RV64-NEXT: vsrl.vx v11, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v11, v11, a2
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsrl.vi v11, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v9, v9, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v11, v11, a4
+; RV64-NEXT: vor.vv v9, v11, v9
+; RV64-NEXT: vand.vx v11, v8, a3
+; RV64-NEXT: vsll.vi v11, v11, 24
+; RV64-NEXT: vor.vv v9, v9, v10
+; RV64-NEXT: vand.vx v10, v8, a4
; RV64-NEXT: vsll.vi v10, v10, 8
-; RV64-NEXT: vor.vv v10, v12, v10
-; RV64-NEXT: vsll.vx v12, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v12, v8
+; RV64-NEXT: vor.vv v10, v11, v10
+; RV64-NEXT: vsll.vx v11, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v11, v8
; RV64-NEXT: vor.vv v8, v8, v10
-; RV64-NEXT: vor.vv v9, v9, v11
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.bswap.v2i64(<2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl)
@@ -423,75 +419,73 @@ define <4 x i64> @vp_bswap_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsll.vx v10, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v12, v8, a1, v0.t
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vlse64.v v14, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsll.vx v12, v12, a4, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vand.vx v12, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV32-NEXT: vand.vv v16, v8, v14, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v12, v12, v16, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t
-; RV32-NEXT: vand.vx v16, v16, a1, v0.t
-; RV32-NEXT: vor.vv v12, v16, v12, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV32-NEXT: vand.vx v16, v16, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v14, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsrl.vx v12, v8, a1
+; RV32-NEXT: vsrl.vx v14, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v16, v8, a1
+; RV32-NEXT: vand.vx v14, v14, a0
+; RV32-NEXT: vlse64.v v18, (a5), zero
+; RV32-NEXT: vor.vv v12, v14, v12
+; RV32-NEXT: vand.vx v14, v8, a0
+; RV32-NEXT: vsll.vx v14, v14, a2
+; RV32-NEXT: vor.vv v14, v16, v14
+; RV32-NEXT: vsrl.vi v16, v8, 8
+; RV32-NEXT: vand.vx v10, v10, a4
+; RV32-NEXT: vand.vv v16, v16, v18
+; RV32-NEXT: vor.vv v10, v16, v10
+; RV32-NEXT: vand.vv v16, v8, v18
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v10, v10, v12
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vor.vv v8, v14, v8
+; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bswap_v4i64:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vand.vx v10, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV64-NEXT: vand.vx v12, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV64-NEXT: vor.vv v10, v10, v12, v0.t
-; RV64-NEXT: vsll.vx v12, v8, a3, v0.t
-; RV64-NEXT: vand.vx v14, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v14, v14, a5, v0.t
-; RV64-NEXT: vor.vv v12, v12, v14, v0.t
-; RV64-NEXT: vor.vv v10, v12, v10, v0.t
-; RV64-NEXT: vsrl.vx v12, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v14, v8, a5, v0.t
-; RV64-NEXT: vand.vx v14, v14, a0, v0.t
-; RV64-NEXT: vor.vv v12, v14, v12, v0.t
-; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t
-; RV64-NEXT: vand.vx v14, v14, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v14, v0.t
-; RV64-NEXT: vor.vv v8, v8, v12, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vsrl.vi v10, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a0
+; RV64-NEXT: vsrl.vx v14, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v14, v14, a2
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsrl.vi v14, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v10, v10, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v14, v14, a4
+; RV64-NEXT: vor.vv v10, v14, v10
+; RV64-NEXT: vand.vx v14, v8, a3
+; RV64-NEXT: vsll.vi v14, v14, 24
+; RV64-NEXT: vor.vv v10, v10, v12
+; RV64-NEXT: vand.vx v12, v8, a4
+; RV64-NEXT: vsll.vi v12, v12, 8
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsll.vx v14, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v14, v8
+; RV64-NEXT: vor.vv v8, v8, v12
+; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.bswap.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -502,39 +496,37 @@ define <4 x i64> @vp_bswap_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v12, v8, a2
-; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: vsrl.vx v14, v8, a2
-; RV32-NEXT: vsrl.vx v16, v8, a4
-; RV32-NEXT: vand.vx v18, v8, a1
-; RV32-NEXT: vand.vx v16, v16, a1
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v16, v8, a1
+; RV32-NEXT: vand.vx v14, v14, a0
+; RV32-NEXT: vlse64.v v18, (a5), zero
+; RV32-NEXT: vor.vv v12, v14, v12
+; RV32-NEXT: vand.vx v14, v8, a0
+; RV32-NEXT: vsll.vx v14, v14, a2
; RV32-NEXT: vor.vv v14, v16, v14
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vlse64.v v16, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsll.vx v18, v18, a4
-; RV32-NEXT: vor.vv v12, v12, v18
-; RV32-NEXT: vsrl.vi v18, v8, 8
-; RV32-NEXT: vand.vx v10, v10, a5
-; RV32-NEXT: vand.vv v18, v18, v16
-; RV32-NEXT: vor.vv v10, v18, v10
-; RV32-NEXT: vand.vv v16, v8, v16
-; RV32-NEXT: vand.vx v8, v8, a5
+; RV32-NEXT: vsrl.vi v16, v8, 8
+; RV32-NEXT: vand.vx v10, v10, a4
+; RV32-NEXT: vand.vv v16, v16, v18
+; RV32-NEXT: vor.vv v10, v16, v10
+; RV32-NEXT: vand.vv v16, v8, v18
+; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vor.vv v8, v8, v16
-; RV32-NEXT: vor.vv v8, v12, v8
-; RV32-NEXT: vor.vv v10, v10, v14
+; RV32-NEXT: vor.vv v8, v14, v8
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -542,34 +534,34 @@ define <4 x i64> @vp_bswap_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
;
; RV64-LABEL: vp_bswap_v4i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vsrl.vi v10, v8, 24
-; RV64-NEXT: vsrl.vi v12, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v14, v8, a3
-; RV64-NEXT: vsrl.vx v16, v8, a5
-; RV64-NEXT: vand.vx v16, v16, a0
-; RV64-NEXT: vor.vv v14, v16, v14
-; RV64-NEXT: vand.vx v16, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v10, v10, a1
-; RV64-NEXT: vsll.vi v16, v16, 24
-; RV64-NEXT: vand.vx v12, v12, a2
-; RV64-NEXT: vor.vv v10, v12, v10
-; RV64-NEXT: vand.vx v12, v8, a2
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v12, v8, a0
+; RV64-NEXT: vsrl.vx v14, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v14, v14, a2
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsrl.vi v14, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v10, v10, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v14, v14, a4
+; RV64-NEXT: vor.vv v10, v14, v10
+; RV64-NEXT: vand.vx v14, v8, a3
+; RV64-NEXT: vsll.vi v14, v14, 24
+; RV64-NEXT: vor.vv v10, v10, v12
+; RV64-NEXT: vand.vx v12, v8, a4
; RV64-NEXT: vsll.vi v12, v12, 8
-; RV64-NEXT: vor.vv v12, v16, v12
-; RV64-NEXT: vsll.vx v16, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: vor.vv v12, v14, v12
+; RV64-NEXT: vsll.vx v14, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v14, v8
; RV64-NEXT: vor.vv v8, v8, v12
-; RV64-NEXT: vor.vv v10, v10, v14
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.bswap.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)
@@ -581,75 +573,73 @@ define <8 x i64> @vp_bswap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v20, v8, a1, v0.t
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsll.vx v20, v20, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vand.vx v20, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v20, v20, 24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v12, v0.t
-; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV32-NEXT: vor.vv v20, v20, v24, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v20, v24, v20, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vor.vv v8, v8, v20, v0.t
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 24
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v20, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v24, v8, a1
+; RV32-NEXT: vand.vx v20, v20, a0
+; RV32-NEXT: vlse64.v v28, (a5), zero
+; RV32-NEXT: vor.vv v16, v20, v16
+; RV32-NEXT: vand.vx v20, v8, a0
+; RV32-NEXT: vsll.vx v20, v20, a2
+; RV32-NEXT: vor.vv v20, v24, v20
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vx v12, v12, a4
+; RV32-NEXT: vand.vv v24, v24, v28
+; RV32-NEXT: vor.vv v12, v24, v12
+; RV32-NEXT: vand.vv v24, v8, v28
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v24, v24, 8
+; RV32-NEXT: vor.vv v12, v12, v16
+; RV32-NEXT: vor.vv v8, v8, v24
+; RV32-NEXT: vor.vv v8, v20, v8
+; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_bswap_v8i64:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-NEXT: vand.vx v12, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV64-NEXT: vand.vx v16, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV64-NEXT: vor.vv v12, v12, v16, v0.t
-; RV64-NEXT: vsll.vx v16, v8, a3, v0.t
-; RV64-NEXT: vand.vx v20, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v20, v20, a5, v0.t
-; RV64-NEXT: vor.vv v16, v16, v20, v0.t
-; RV64-NEXT: vor.vv v12, v16, v12, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v20, v8, a5, v0.t
-; RV64-NEXT: vand.vx v20, v20, a0, v0.t
-; RV64-NEXT: vor.vv v16, v20, v16, v0.t
-; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t
-; RV64-NEXT: vand.vx v20, v20, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v20, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vsrl.vi v12, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v20, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v20, v20, a2
+; RV64-NEXT: vor.vv v16, v20, v16
+; RV64-NEXT: vsrl.vi v20, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v12, v12, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v20, v20, a4
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vand.vx v20, v8, a3
+; RV64-NEXT: vsll.vi v20, v20, 24
+; RV64-NEXT: vor.vv v12, v12, v16
+; RV64-NEXT: vand.vx v16, v8, a4
+; RV64-NEXT: vsll.vi v16, v16, 8
+; RV64-NEXT: vor.vv v16, v20, v16
+; RV64-NEXT: vsll.vx v20, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v20, v8
+; RV64-NEXT: vor.vv v8, v8, v16
+; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.bswap.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -660,39 +650,37 @@ define <8 x i64> @vp_bswap_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 24
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsll.vx v16, v8, a2
-; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vsrl.vx v20, v8, a2
-; RV32-NEXT: vsrl.vx v24, v8, a4
-; RV32-NEXT: vand.vx v28, v8, a1
-; RV32-NEXT: vand.vx v24, v24, a1
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v24, v8, a1
+; RV32-NEXT: vand.vx v20, v20, a0
+; RV32-NEXT: vlse64.v v28, (a5), zero
+; RV32-NEXT: vor.vv v16, v20, v16
+; RV32-NEXT: vand.vx v20, v8, a0
+; RV32-NEXT: vsll.vx v20, v20, a2
; RV32-NEXT: vor.vv v20, v24, v20
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vlse64.v v24, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsll.vx v28, v28, a4
-; RV32-NEXT: vor.vv v16, v16, v28
-; RV32-NEXT: vsrl.vi v28, v8, 8
-; RV32-NEXT: vand.vx v12, v12, a5
-; RV32-NEXT: vand.vv v28, v28, v24
-; RV32-NEXT: vor.vv v12, v28, v12
-; RV32-NEXT: vand.vv v24, v8, v24
-; RV32-NEXT: vand.vx v8, v8, a5
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vx v12, v12, a4
+; RV32-NEXT: vand.vv v24, v24, v28
+; RV32-NEXT: vor.vv v12, v24, v12
+; RV32-NEXT: vand.vv v24, v8, v28
+; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v24, v24, 8
+; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vor.vv v8, v8, v24
-; RV32-NEXT: vor.vv v8, v16, v8
-; RV32-NEXT: vor.vv v12, v12, v20
+; RV32-NEXT: vor.vv v8, v20, v8
; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -700,34 +688,34 @@ define <8 x i64> @vp_bswap_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
;
; RV64-LABEL: vp_bswap_v8i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vsrl.vi v12, v8, 24
-; RV64-NEXT: vsrl.vi v16, v8, 8
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v20, v8, a3
-; RV64-NEXT: vsrl.vx v24, v8, a5
-; RV64-NEXT: vand.vx v24, v24, a0
-; RV64-NEXT: vor.vv v20, v24, v20
-; RV64-NEXT: vand.vx v24, v8, a1
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v12, v12, a1
-; RV64-NEXT: vsll.vi v24, v24, 24
-; RV64-NEXT: vand.vx v16, v16, a2
-; RV64-NEXT: vor.vv v12, v16, v12
-; RV64-NEXT: vand.vx v16, v8, a2
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v20, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v20, v20, a2
+; RV64-NEXT: vor.vv v16, v20, v16
+; RV64-NEXT: vsrl.vi v20, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v12, v12, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v20, v20, a4
+; RV64-NEXT: vor.vv v12, v20, v12
+; RV64-NEXT: vand.vx v20, v8, a3
+; RV64-NEXT: vsll.vi v20, v20, 24
+; RV64-NEXT: vor.vv v12, v12, v16
+; RV64-NEXT: vand.vx v16, v8, a4
; RV64-NEXT: vsll.vi v16, v16, 8
-; RV64-NEXT: vor.vv v16, v24, v16
-; RV64-NEXT: vsll.vx v24, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v24, v8
+; RV64-NEXT: vor.vv v16, v20, v16
+; RV64-NEXT: vsll.vx v20, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v20, v8
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: vor.vv v12, v12, v20
; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.bswap.v8i64(<8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl)
@@ -739,87 +727,58 @@ define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %ev
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a4, 4080
; RV32-NEXT: addi a5, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -828,53 +787,35 @@ define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %ev
;
; RV64-LABEL: vp_bswap_v15i64:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v0, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vsrl.vi v0, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vand.vx v0, v8, a3
+; RV64-NEXT: vsll.vi v0, v0, 24
+; RV64-NEXT: vor.vv v16, v24, v16
+; RV64-NEXT: vand.vx v24, v8, a4
+; RV64-NEXT: vsll.vi v24, v24, 8
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vsll.vx v0, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
+; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.bswap.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v
@@ -885,58 +826,56 @@ define <15 x i64> @vp_bswap_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v24, v8, a2
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vsrl.vx v16, v8, a2
-; RV32-NEXT: vsrl.vx v0, v8, a4
-; RV32-NEXT: vand.vx v0, v0, a1
-; RV32-NEXT: vor.vv v16, v0, v16
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vand.vx v0, v8, a1
-; RV32-NEXT: vsll.vx v0, v0, a4
-; RV32-NEXT: vor.vv v16, v24, v0
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v0, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
; RV32-NEXT: vsrl.vi v16, v8, 24
-; RV32-NEXT: vand.vx v16, v16, a5
+; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v24, v24, v0
; RV32-NEXT: vor.vv v16, v24, v16
-; RV32-NEXT: vand.vv v24, v8, v0
-; RV32-NEXT: vand.vx v8, v8, a5
-; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v24, v24, 8
-; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v24, v8
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
@@ -947,51 +886,35 @@ define <15 x i64> @vp_bswap_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
;
; RV64-LABEL: vp_bswap_v15i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v16, v8, a3
-; RV64-NEXT: vsrl.vx v0, v8, a5
-; RV64-NEXT: vand.vx v0, v0, a0
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v0, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vsrl.vi v0, v8, 8
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v24, v24, a1
-; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
; RV64-NEXT: vor.vv v24, v0, v24
-; RV64-NEXT: vand.vx v0, v8, a1
+; RV64-NEXT: vand.vx v0, v8, a3
; RV64-NEXT: vsll.vi v0, v0, 24
-; RV64-NEXT: vand.vx v16, v8, a2
-; RV64-NEXT: vsll.vi v16, v16, 8
-; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: vsll.vx v0, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v0, v8
-; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v16, v24, v16
+; RV64-NEXT: vand.vx v24, v8, a4
+; RV64-NEXT: vsll.vi v24, v24, 8
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vsll.vx v0, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.bswap.v15i64(<15 x i64> %va, <15 x i1> splat (i1 true), i32 %evl)
ret <15 x i64> %v
@@ -1002,87 +925,58 @@ define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a4, 4080
; RV32-NEXT: addi a5, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vlse64.v v0, (a5), zero
+; RV32-NEXT: vsrl.vi v16, v8, 24
+; RV32-NEXT: vand.vx v16, v16, a4
+; RV32-NEXT: vsrl.vi v24, v8, 8
+; RV32-NEXT: vand.vv v24, v24, v0
+; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -1091,53 +985,35 @@ define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
;
; RV64-LABEL: vp_bswap_v16i64:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 24
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v0, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: vor.vv v16, v0, v16
+; RV64-NEXT: vsrl.vi v0, v8, 8
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vand.vx v0, v8, a3
+; RV64-NEXT: vsll.vi v0, v0, 24
+; RV64-NEXT: vor.vv v16, v24, v16
+; RV64-NEXT: vand.vx v24, v8, a4
+; RV64-NEXT: vsll.vi v24, v24, 8
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vsll.vx v0, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
+; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.bswap.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v
@@ -1148,58 +1024,56 @@ define <16 x i64> @vp_bswap_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: li a2, 40
; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: lui a5, 4080
-; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: lui a4, 4080
+; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v24, v8, a2
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vsrl.vx v16, v8, a2
-; RV32-NEXT: vsrl.vx v0, v8, a4
-; RV32-NEXT: vand.vx v0, v0, a1
-; RV32-NEXT: vor.vv v16, v0, v16
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vand.vx v0, v8, a1
-; RV32-NEXT: vsll.vx v0, v0, a4
-; RV32-NEXT: vor.vv v16, v24, v0
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1
+; RV32-NEXT: vsrl.vx v24, v8, a2
+; RV32-NEXT: addi a0, a3, -256
+; RV32-NEXT: vsll.vx v0, v8, a1
+; RV32-NEXT: vand.vx v24, v24, a0
+; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v0, (a6), zero
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vand.vx v16, v8, a0
+; RV32-NEXT: vsll.vx v16, v16, a2
+; RV32-NEXT: vor.vv v16, v0, v16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vlse64.v v0, (a5), zero
; RV32-NEXT: vsrl.vi v16, v8, 24
-; RV32-NEXT: vand.vx v16, v16, a5
+; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v24, v24, v0
; RV32-NEXT: vor.vv v16, v24, v16
-; RV32-NEXT: vand.vv v24, v8, v0
-; RV32-NEXT: vand.vx v8, v8, a5
-; RV32-NEXT: vsll.vi v8, v8, 24
-; RV32-NEXT: vsll.vi v24, v24, 8
-; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v24, v8
+; RV32-NEXT: vor.vv v24, v16, v24
+; RV32-NEXT: vand.vv v16, v8, v0
+; RV32-NEXT: vand.vx v8, v8, a4
+; RV32-NEXT: vsll.vi v8, v8, 24
+; RV32-NEXT: vsll.vi v16, v16, 8
+; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v16, v24
-; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v16, v8
+; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0
@@ -1210,51 +1084,35 @@ define <16 x i64> @vp_bswap_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
;
; RV64-LABEL: vp_bswap_v16i64_unmasked:
; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: .cfi_def_cfa_offset 16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: lui a4, 16
-; RV64-NEXT: li a5, 40
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a1, 40
+; RV64-NEXT: lui a2, 16
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
-; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsrl.vx v16, v8, a3
-; RV64-NEXT: vsrl.vx v0, v8, a5
-; RV64-NEXT: vand.vx v0, v0, a0
+; RV64-NEXT: lui a3, 4080
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsrl.vx v0, v8, a1
+; RV64-NEXT: addi a2, a2, -256
+; RV64-NEXT: vand.vx v0, v0, a2
; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vsrl.vi v0, v8, 8
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: vand.vx v24, v24, a1
-; RV64-NEXT: vand.vx v0, v0, a2
+; RV64-NEXT: li a4, 255
+; RV64-NEXT: vand.vx v24, v24, a3
+; RV64-NEXT: slli a4, a4, 24
+; RV64-NEXT: vand.vx v0, v0, a4
; RV64-NEXT: vor.vv v24, v0, v24
-; RV64-NEXT: vand.vx v0, v8, a1
+; RV64-NEXT: vand.vx v0, v8, a3
; RV64-NEXT: vsll.vi v0, v0, 24
-; RV64-NEXT: vand.vx v16, v8, a2
-; RV64-NEXT: vsll.vi v16, v16, 8
-; RV64-NEXT: vor.vv v16, v0, v16
-; RV64-NEXT: vsll.vx v0, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vsll.vx v8, v8, a5
-; RV64-NEXT: vor.vv v8, v0, v8
-; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v16, v24, v16
+; RV64-NEXT: vand.vx v24, v8, a4
+; RV64-NEXT: vsll.vi v24, v24, 8
+; RV64-NEXT: vor.vv v24, v0, v24
+; RV64-NEXT: vsll.vx v0, v8, a0
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vsll.vx v8, v8, a1
+; RV64-NEXT: vor.vv v8, v0, v8
+; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 16
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.bswap.v16i64(<16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl)
ret <16 x i64> %v
@@ -1263,27 +1121,14 @@ define <16 x i64> @vp_bswap_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
define <128 x i16> @vp_bswap_v128i16(<128 x i16> %va, <128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v128i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v7, v0, 8
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB26_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: .LBB26_2:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
-; CHECK-NEXT: addi a1, a0, -64
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vsrl.vi v24, v8, 8
+; CHECK-NEXT: vsll.vi v8, v8, 8
+; CHECK-NEXT: vor.vv v8, v8, v24
+; CHECK-NEXT: vsrl.vi v24, v16, 8
+; CHECK-NEXT: vsll.vi v16, v16, 8
+; CHECK-NEXT: vor.vv v16, v16, v24
; CHECK-NEXT: ret
%v = call <128 x i16> @llvm.vp.bswap.v128i16(<128 x i16> %va, <128 x i1> %m, i32 %evl)
ret <128 x i16> %v
@@ -1292,21 +1137,11 @@ define <128 x i16> @vp_bswap_v128i16(<128 x i16> %va, <128 x i1> %m, i32 zeroext
define <128 x i16> @vp_bswap_v128i16_unmasked(<128 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v128i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB27_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: .LBB27_2:
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: li a0, 64
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 8
; CHECK-NEXT: vsll.vi v8, v8, 8
; CHECK-NEXT: vor.vv v8, v8, v24
-; CHECK-NEXT: addi a1, a0, -64
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 8
; CHECK-NEXT: vsll.vi v16, v16, 8
; CHECK-NEXT: vor.vv v16, v16, v24
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