[llvm] f058eaa - [NFC][UniformityAnalysis] Rename variables in uniformity analysis to follow LLVM conventions (#191134)
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Mon Apr 13 08:37:28 PDT 2026
Author: Pankaj Dwivedi
Date: 2026-04-13T21:07:22+05:30
New Revision: f058eaa7c56e1a23c69815ca89ad8148c6e84ebe
URL: https://github.com/llvm/llvm-project/commit/f058eaa7c56e1a23c69815ca89ad8148c6e84ebe
DIFF: https://github.com/llvm/llvm-project/commit/f058eaa7c56e1a23c69815ca89ad8148c6e84ebe.diff
LOG: [NFC][UniformityAnalysis] Rename variables in uniformity analysis to follow LLVM conventions (#191134)
Follow-up to
#[189948](https://github.com/llvm/llvm-project/pull/189948#discussion_r3027394937).
Addresses review feedback
Co-authored-by: padivedi <padivedi at amd.com>
Added:
Modified:
llvm/include/llvm/ADT/GenericUniformityImpl.h
llvm/include/llvm/Analysis/UniformityAnalysis.h
llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
llvm/lib/Analysis/UniformityAnalysis.cpp
llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/ADT/GenericUniformityImpl.h b/llvm/include/llvm/ADT/GenericUniformityImpl.h
index d5859981ce1a7..a363b2a3c1702 100644
--- a/llvm/include/llvm/ADT/GenericUniformityImpl.h
+++ b/llvm/include/llvm/ADT/GenericUniformityImpl.h
@@ -98,21 +98,21 @@ template <typename ContextT> class ModifiedPostOrder {
ModifiedPostOrder(const ContextT &C) : Context(C) {}
- bool empty() const { return m_order.empty(); }
- size_t size() const { return m_order.size(); }
+ bool empty() const { return Order.empty(); }
+ size_t size() const { return Order.size(); }
- void clear() { m_order.clear(); }
+ void clear() { Order.clear(); }
void compute(const CycleInfoT &CI);
unsigned count(BlockT *BB) const { return POIndex.count(BB); }
- const BlockT *operator[](size_t idx) const { return m_order[idx]; }
+ const BlockT *operator[](size_t Idx) const { return Order[Idx]; }
- void appendBlock(const BlockT &BB, bool isReducibleCycleHeader = false) {
- POIndex[&BB] = m_order.size();
- m_order.push_back(&BB);
+ void appendBlock(const BlockT &BB, bool IsReducibleCycleHeader = false) {
+ POIndex[&BB] = Order.size();
+ Order.push_back(&BB);
LLVM_DEBUG(dbgs() << "ModifiedPO(" << POIndex[&BB]
<< "): " << Context.print(&BB) << "\n");
- if (isReducibleCycleHeader)
+ if (IsReducibleCycleHeader)
ReducibleCycleHeaders.insert(&BB);
}
@@ -126,7 +126,7 @@ template <typename ContextT> class ModifiedPostOrder {
}
private:
- SmallVector<const BlockT *> m_order;
+ SmallVector<const BlockT *> Order;
DenseMap<const BlockT *, unsigned> POIndex;
SmallPtrSet<const BlockT *, 32> ReducibleCycleHeaders;
const ContextT &Context;
@@ -411,11 +411,11 @@ template <typename ContextT> class GenericUniformityAnalysisImpl {
return DivergentTermBlocks.contains(&B);
}
- void print(raw_ostream &out) const;
+ void print(raw_ostream &Out) const;
/// Print divergent arguments and return true if any were found.
/// IR specialization iterates F.args(); default is a no-op.
- bool printDivergentArgs(raw_ostream &out) const;
+ bool printDivergentArgs(raw_ostream &Out) const;
SmallVector<TemporalDivergenceTuple, 8> TemporalDivergenceList;
@@ -788,7 +788,7 @@ auto llvm::GenericSyncDependenceAnalysis<ContextT>::getJoinBlocks(
DivergencePropagatorT Propagator(CyclePO, DT, CI, *DivTermBlock);
auto DivDesc = Propagator.computeJoinPoints();
- auto printBlockSet = [&](ConstBlockSet &Blocks) {
+ auto PrintBlockSet = [&](ConstBlockSet &Blocks) {
return Printable([&](raw_ostream &Out) {
Out << "[";
ListSeparator LS;
@@ -801,10 +801,10 @@ auto llvm::GenericSyncDependenceAnalysis<ContextT>::getJoinBlocks(
LLVM_DEBUG(
dbgs() << "\nResult (" << CI.getSSAContext().print(DivTermBlock)
- << "):\n JoinDivBlocks: " << printBlockSet(DivDesc->JoinDivBlocks)
- << " CycleDivBlocks: " << printBlockSet(DivDesc->CycleDivBlocks)
+ << "):\n JoinDivBlocks: " << PrintBlockSet(DivDesc->JoinDivBlocks)
+ << " CycleDivBlocks: " << PrintBlockSet(DivDesc->CycleDivBlocks)
<< "\n");
- (void)printBlockSet;
+ (void)PrintBlockSet;
auto ItInserted =
CachedControlDivDescs.try_emplace(DivTermBlock, std::move(DivDesc));
@@ -1213,16 +1213,16 @@ void GenericUniformityAnalysisImpl<ContextT>::print(raw_ostream &OS) const {
if (!AssumedDivergent.empty()) {
FoundDivergence = true;
OS << "CYCLES ASSUMED DIVERGENT:\n";
- for (const CycleT *cycle : AssumedDivergent) {
- OS << " " << cycle->print(Context) << '\n';
+ for (const CycleT *Cycle : AssumedDivergent) {
+ OS << " " << Cycle->print(Context) << '\n';
}
}
if (!DivergentExitCycles.empty()) {
FoundDivergence = true;
OS << "CYCLES WITH DIVERGENT EXIT:\n";
- for (const CycleT *cycle : DivergentExitCycles) {
- OS << " " << cycle->print(Context) << '\n';
+ for (const CycleT *Cycle : DivergentExitCycles) {
+ OS << " " << Cycle->print(Context) << '\n';
}
}
@@ -1237,30 +1237,30 @@ void GenericUniformityAnalysisImpl<ContextT>::print(raw_ostream &OS) const {
}
}
- for (auto &block : F) {
- OS << "\nBLOCK " << Context.print(&block) << '\n';
+ for (auto &Block : F) {
+ OS << "\nBLOCK " << Context.print(&Block) << '\n';
OS << "DEFINITIONS\n";
- SmallVector<ConstValueRefT, 16> defs;
- Context.appendBlockDefs(defs, block);
- for (auto value : defs) {
- if (isDivergent(value)) {
+ SmallVector<ConstValueRefT, 16> Defs;
+ Context.appendBlockDefs(Defs, Block);
+ for (auto Value : Defs) {
+ if (isDivergent(Value)) {
FoundDivergence = true;
OS << " DIVERGENT: ";
} else {
OS << " ";
}
- OS << Context.print(value) << NewLine;
+ OS << Context.print(Value) << NewLine;
}
OS << "TERMINATORS\n";
- SmallVector<const InstructionT *, 8> terms;
- Context.appendBlockTerms(terms, block);
- bool divergentTerminators = hasDivergentTerminator(block);
- if (divergentTerminators)
+ SmallVector<const InstructionT *, 8> Terms;
+ Context.appendBlockTerms(Terms, Block);
+ bool DivergentTerminators = hasDivergentTerminator(Block);
+ if (DivergentTerminators)
FoundDivergence = true;
- for (auto *T : terms) {
- if (divergentTerminators)
+ for (auto *T : Terms) {
+ if (DivergentTerminators)
OS << " DIVERGENT: ";
else
OS << " ";
@@ -1313,12 +1313,12 @@ bool GenericUniformityInfo<ContextT>::hasDivergentTerminator(const BlockT &B) {
/// \brief T helper function for printing.
template <typename ContextT>
-void GenericUniformityInfo<ContextT>::print(raw_ostream &out) const {
+void GenericUniformityInfo<ContextT>::print(raw_ostream &Out) const {
if (!DA) {
- out << " Uniformity analysis not computed (no branch divergence).\n";
+ Out << " Uniformity analysis not computed (no branch divergence).\n";
return;
}
- DA->print(out);
+ DA->print(Out);
}
template <typename ContextT>
diff --git a/llvm/include/llvm/Analysis/UniformityAnalysis.h b/llvm/include/llvm/Analysis/UniformityAnalysis.h
index a067a9b42893c..15715c837dd23 100644
--- a/llvm/include/llvm/Analysis/UniformityAnalysis.h
+++ b/llvm/include/llvm/Analysis/UniformityAnalysis.h
@@ -55,16 +55,16 @@ class UniformityInfoPrinterPass
/// Legacy analysis pass which computes a \ref CycleInfo.
class UniformityInfoWrapperPass : public FunctionPass {
- Function *m_function = nullptr;
- UniformityInfo m_uniformityInfo;
+ Function *Fn = nullptr;
+ UniformityInfo UI;
public:
static char ID;
UniformityInfoWrapperPass();
- UniformityInfo &getUniformityInfo() { return m_uniformityInfo; }
- const UniformityInfo &getUniformityInfo() const { return m_uniformityInfo; }
+ UniformityInfo &getUniformityInfo() { return UI; }
+ const UniformityInfo &getUniformityInfo() const { return UI; }
bool runOnFunction(Function &F) override;
void getAnalysisUsage(AnalysisUsage &AU) const override;
diff --git a/llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h b/llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
index e8c0dc9b43823..ad37204f12534 100644
--- a/llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
+++ b/llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
@@ -29,9 +29,10 @@ using MachineUniformityInfo = GenericUniformityInfo<MachineSSAContext>;
///
/// If \p HasBranchDivergence is false, produces a dummy result which assumes
/// everything is uniform.
-MachineUniformityInfo computeMachineUniformityInfo(
- MachineFunction &F, const MachineCycleInfo &cycleInfo,
- const MachineDominatorTree &domTree, bool HasBranchDivergence);
+MachineUniformityInfo
+computeMachineUniformityInfo(MachineFunction &F, const MachineCycleInfo &CI,
+ const MachineDominatorTree &DT,
+ bool HasBranchDivergence);
/// Legacy analysis pass which computes a \ref MachineUniformityInfo.
class MachineUniformityAnalysisPass : public MachineFunctionPass {
diff --git a/llvm/lib/Analysis/UniformityAnalysis.cpp b/llvm/lib/Analysis/UniformityAnalysis.cpp
index 41519bcd09baa..73b6476fb7b6d 100644
--- a/llvm/lib/Analysis/UniformityAnalysis.cpp
+++ b/llvm/lib/Analysis/UniformityAnalysis.cpp
@@ -52,17 +52,17 @@ void llvm::GenericUniformityAnalysisImpl<SSAContext>::pushUsers(
template <>
bool llvm::GenericUniformityAnalysisImpl<SSAContext>::printDivergentArgs(
raw_ostream &OS) const {
- bool haveDivergentArgs = false;
+ bool HaveDivergentArgs = false;
for (const auto &Arg : F.args()) {
if (isDivergent(&Arg)) {
- if (!haveDivergentArgs) {
+ if (!HaveDivergentArgs) {
OS << "DIVERGENT ARGUMENTS:\n";
- haveDivergentArgs = true;
+ HaveDivergentArgs = true;
}
OS << " DIVERGENT: " << Context.print(&Arg) << '\n';
}
}
- return haveDivergentArgs;
+ return HaveDivergentArgs;
}
template <> void llvm::GenericUniformityAnalysisImpl<SSAContext>::initialize() {
@@ -167,11 +167,11 @@ template struct llvm::GenericUniformityAnalysisImplDeleter<
llvm::UniformityInfo UniformityInfoAnalysis::run(Function &F,
FunctionAnalysisManager &FAM) {
- auto &TTI = FAM.getResult<TargetIRAnalysis>(F);
+ TargetTransformInfo &TTI = FAM.getResult<TargetIRAnalysis>(F);
if (!TTI.hasBranchDivergence(&F))
return UniformityInfo{};
- auto &DT = FAM.getResult<DominatorTreeAnalysis>(F);
- auto &CI = FAM.getResult<CycleAnalysis>(F);
+ DominatorTree &DT = FAM.getResult<DominatorTreeAnalysis>(F);
+ CycleInfo &CI = FAM.getResult<CycleAnalysis>(F);
UniformityInfo UI{DT, CI, &TTI};
UI.compute();
return UI;
@@ -214,29 +214,29 @@ void UniformityInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
}
bool UniformityInfoWrapperPass::runOnFunction(Function &F) {
- auto &targetTransformInfo =
+ TargetTransformInfo &TTI =
getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
- m_function = &F;
+ Fn = &F;
- if (!targetTransformInfo.hasBranchDivergence(m_function)) {
- m_uniformityInfo = UniformityInfo{};
+ if (!TTI.hasBranchDivergence(Fn)) {
+ UI = UniformityInfo{};
return false;
}
- auto &cycleInfo = getAnalysis<CycleInfoWrapperPass>().getResult();
- auto &domTree = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
- m_uniformityInfo = UniformityInfo{domTree, cycleInfo, &targetTransformInfo};
- m_uniformityInfo.compute();
+ CycleInfo &CI = getAnalysis<CycleInfoWrapperPass>().getResult();
+ DominatorTree &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
+ UI = UniformityInfo{DT, CI, &TTI};
+ UI.compute();
return false;
}
void UniformityInfoWrapperPass::print(raw_ostream &OS, const Module *) const {
- OS << "UniformityInfo for function '" << m_function->getName() << "':\n";
- m_uniformityInfo.print(OS);
+ OS << "UniformityInfo for function '" << Fn->getName() << "':\n";
+ UI.print(OS);
}
void UniformityInfoWrapperPass::releaseMemory() {
- m_uniformityInfo = UniformityInfo{};
- m_function = nullptr;
+ UI = UniformityInfo{};
+ Fn = nullptr;
}
diff --git a/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp b/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
index aa85b95a96d09..03a046ea995ed 100644
--- a/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+++ b/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
@@ -21,8 +21,8 @@ using namespace llvm;
template <>
bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::hasDivergentDefs(
const MachineInstr &I) const {
- for (auto &op : I.all_defs()) {
- if (isDivergent(op.getReg()))
+ for (auto &Op : I.all_defs()) {
+ if (isDivergent(Op.getReg()))
return true;
}
return false;
@@ -31,19 +31,19 @@ bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::hasDivergentDefs(
template <>
bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::markDefsDivergent(
const MachineInstr &Instr) {
- bool insertedDivergent = false;
+ bool InsertedDivergent = false;
const auto &MRI = F.getRegInfo();
const auto &RBI = *F.getSubtarget().getRegBankInfo();
const auto &TRI = *MRI.getTargetRegisterInfo();
- for (auto &op : Instr.all_defs()) {
- if (!op.getReg().isVirtual())
+ for (auto &Op : Instr.all_defs()) {
+ if (!Op.getReg().isVirtual())
continue;
- assert(!op.getSubReg());
- if (TRI.isUniformReg(MRI, RBI, op.getReg()))
+ assert(!Op.getSubReg());
+ if (TRI.isUniformReg(MRI, RBI, Op.getReg()))
continue;
- insertedDivergent |= markDivergent(op.getReg());
+ InsertedDivergent |= markDivergent(Op.getReg());
}
- return insertedDivergent;
+ return InsertedDivergent;
}
template <>
@@ -64,16 +64,16 @@ void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::initialize() {
const auto &InstrInfo = *F.getSubtarget().getInstrInfo();
- for (const MachineBasicBlock &block : F) {
- for (const MachineInstr &instr : block) {
- auto uniformity = InstrInfo.getValueUniformity(instr);
+ for (const MachineBasicBlock &MBB : F) {
+ for (const MachineInstr &MI : MBB) {
+ ValueUniformity VU = InstrInfo.getValueUniformity(MI);
- switch (uniformity) {
+ switch (VU) {
case ValueUniformity::AlwaysUniform:
- addUniformOverride(instr);
+ addUniformOverride(MI);
break;
case ValueUniformity::NeverUniform:
- markDivergent(instr);
+ markDivergent(MI);
break;
case ValueUniformity::Custom:
break;
@@ -100,8 +100,8 @@ void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::pushUsers(
assert(!isAlwaysUniform(Instr));
if (Instr.isTerminator())
return;
- for (const MachineOperand &op : Instr.all_defs()) {
- auto Reg = op.getReg();
+ for (const MachineOperand &Op : Instr.all_defs()) {
+ auto Reg = Op.getReg();
if (isDivergent(Reg))
pushUsers(Reg);
}
@@ -180,10 +180,10 @@ template struct llvm::GenericUniformityAnalysisImplDeleter<
llvm::GenericUniformityAnalysisImpl<MachineSSAContext>>;
MachineUniformityInfo llvm::computeMachineUniformityInfo(
- MachineFunction &F, const MachineCycleInfo &cycleInfo,
- const MachineDominatorTree &domTree, bool HasBranchDivergence) {
+ MachineFunction &F, const MachineCycleInfo &CI,
+ const MachineDominatorTree &DT, bool HasBranchDivergence) {
assert(F.getRegInfo().isSSA() && "Expected to be run on SSA form!");
- MachineUniformityInfo UI(domTree, cycleInfo);
+ MachineUniformityInfo UI(DT, CI);
if (HasBranchDivergence)
UI.compute();
return UI;
@@ -208,20 +208,20 @@ AnalysisKey MachineUniformityAnalysis::Key;
MachineUniformityAnalysis::Result
MachineUniformityAnalysis::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
- auto &DomTree = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
- auto &CI = MFAM.getResult<MachineCycleAnalysis>(MF);
- auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
- .getManager();
- auto &F = MF.getFunction();
- auto &TTI = FAM.getResult<TargetIRAnalysis>(F);
- return computeMachineUniformityInfo(MF, CI, DomTree,
- TTI.hasBranchDivergence(&F));
+ MachineDominatorTree &DT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ MachineCycleInfo &CI = MFAM.getResult<MachineCycleAnalysis>(MF);
+ FunctionAnalysisManager &FAM =
+ MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+ .getManager();
+ Function &F = MF.getFunction();
+ TargetTransformInfo &TTI = FAM.getResult<TargetIRAnalysis>(F);
+ return computeMachineUniformityInfo(MF, CI, DT, TTI.hasBranchDivergence(&F));
}
PreservedAnalyses
MachineUniformityPrinterPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
- auto &MUI = MFAM.getResult<MachineUniformityAnalysis>(MF);
+ MachineUniformityInfo &MUI = MFAM.getResult<MachineUniformityAnalysis>(MF);
OS << "MachineUniformityInfo for function: ";
MF.getFunction().printAsOperand(OS, /*PrintType=*/false);
OS << '\n';
@@ -249,11 +249,13 @@ void MachineUniformityAnalysisPass::getAnalysisUsage(AnalysisUsage &AU) const {
}
bool MachineUniformityAnalysisPass::runOnMachineFunction(MachineFunction &MF) {
- auto &DomTree = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- auto &CI = getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
+ MachineDominatorTree &DT =
+ getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ MachineCycleInfo &CI =
+ getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
// FIXME: Query TTI::hasBranchDivergence. -run-pass seems to end up with a
// default NoTTI
- UI = computeMachineUniformityInfo(MF, CI, DomTree, true);
+ UI = computeMachineUniformityInfo(MF, CI, DT, true);
return false;
}
@@ -287,7 +289,8 @@ void MachineUniformityInfoPrinterPass::getAnalysisUsage(
bool MachineUniformityInfoPrinterPass::runOnMachineFunction(
MachineFunction &F) {
- auto &UI = getAnalysis<MachineUniformityAnalysisPass>();
+ MachineUniformityAnalysisPass &UI =
+ getAnalysis<MachineUniformityAnalysisPass>();
UI.print(errs());
return false;
}
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