[llvm] [WIP][SPARC] Use hardware byteswapper when we have V9 (PR #191720)

[via llvm-commits]

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@@ -3001,6 +3004,37 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
   return DAG.getMergeValues(Ops, dl);
 }
 
+SDValue SparcTargetLowering::LowerBSWAP(SDValue Op, SelectionDAG &DAG) const {
+  // We don't have an in-register bswap, so expand bswap(x) into
+  // load(store-swapped(x)). The reason the swap is done during the store is
+  // that on some implementations (mainly older ones) ASI-tagged memory
+  // operations are not pipelined, and generally stores finish faster than
+  // loads.
+
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+  auto PtrVT = getPointerTy(DAG.getDataLayout());
+  SDValue Chain = DAG.getEntryNode();
+  bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
+  SDLoc DL(Op);
+
+  SDValue BSwapOp = Op.getOperand(0);
+  EVT BSwapVT = BSwapOp.getValueType();
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koachan wrote:

I see, so it's actually a `ld`+`srl` pair that got combined into `lduh`?
Though, yeah, after some testing it seems to be lowered correctly; I see that the result is the same as the bitops and GCC's lowering for all `uint16_t`.

As far as performance is concerned, I think `stha`+`lduh` pair would be ideal, but even this lowering is already faster than the bitops lowering, so I'm satisfied enough for now~

In any case I'll taking the WIP tag off, thank you!

https://github.com/llvm/llvm-project/pull/191720