[llvm] [ARM][GISel] Enable extended LLT (PR #191830)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 13 07:53:40 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/191830
This adds the basic enablement for extended LLT for Arm GISel. This is relatively basic, with no direct use of fp16/bf16 yet. Most of the changes involved updating the tests and some minor updates to handle bitcast and merge/unmerge correctly.
>From f68df5195a94be063d751f27c57eb72c78059f5d Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 13 Apr 2026 15:52:20 +0100
Subject: [PATCH] [ARM][GISel] Enable extended LLT
This adds the basic enablement for extended LLT for Arm GISel. This is
relatively basic, with no direct use of fp16/bf16 yet. Most of the changes
involved updating the tests and some minor updates to handle bitcast and
merge/unmerge correctly.
---
.../lib/Target/ARM/ARMInstructionSelector.cpp | 3 +
llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 53 +-
llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 3 +
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 2 +
llvm/lib/Target/ARM/CMakeLists.txt | 2 +-
.../arm-instruction-select-combos.mir | 248 +-
.../ARM/GlobalISel/arm-instruction-select.mir | 302 +--
.../ARM/GlobalISel/arm-irtranslator.ll | 861 ++++---
.../ARM/GlobalISel/arm-legalize-fp.mir | 2198 +++++++++--------
.../GlobalISel/arm-legalize-load-store.mir | 38 +-
.../ARM/GlobalISel/arm-legalize-vfp4.mir | 40 +-
.../ARM/GlobalISel/arm-param-lowering.ll | 228 +-
.../arm-select-copy_to_regclass-of-fptosi.mir | 6 +-
.../CodeGen/ARM/GlobalISel/arm-unsupported.ll | 2 +-
.../irtranslator-varargs-lowering.ll | 43 +-
.../CodeGen/ARM/GlobalISel/select-clz.mir | 6 +-
.../CodeGen/ARM/GlobalISel/select-dbg.mir | 16 +-
.../test/CodeGen/ARM/GlobalISel/select-fp.mir | 172 +-
.../CodeGen/ARM/GlobalISel/select-neon.mir | 16 +-
.../CodeGen/ARM/GlobalISel/select-pkhbt.mir | 108 +-
.../CodeGen/ARM/GlobalISel/select-pr35926.mir | 14 +-
.../CodeGen/ARM/GlobalISel/select-revsh.mir | 66 +-
.../thumb-select-arithmetic-ops.mir | 84 +-
.../GlobalISel/thumb-select-logical-ops.mir | 64 +-
24 files changed, 2482 insertions(+), 2093 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index c2ee75205d888..0e551b66a8786 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -1037,6 +1037,9 @@ bool ARMInstructionSelector::select(MachineInstr &I) {
I.setDesc(TII.get(COPY));
return selectCopy(I, TII, MRI, TRI, RBI);
}
+ case TargetOpcode::G_BITCAST:
+ I.setDesc(TII.get(COPY));
+ return selectCopy(I, TII, MRI, TRI, RBI);
case G_SELECT:
return selectSelect(MIB, MRI);
case G_ICMP: {
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index ad3e4f116321b..769e4013be660 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -40,6 +40,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
const LLT s32 = LLT::scalar(32);
const LLT s64 = LLT::scalar(64);
+ const LLT f32 = LLT::float32();
+ const LLT f64 = LLT::float64();
+
auto &LegacyInfo = getLegacyLegalizerInfo();
if (ST.isThumb1Only()) {
// Thumb1 is not supported yet.
@@ -48,6 +51,13 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
return;
}
+ getActionDefinitionsBuilder(G_BITCAST)
+ .legalForCartesianProduct({s32})
+ .legalForCartesianProduct({s64});
+
+ getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}});
+ getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}});
+
getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
.legalForCartesianProduct({s8, s16, s32}, {s1, s8, s16});
@@ -138,7 +148,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
if (!ST.useSoftFloat() && ST.hasVFP2Base()) {
getActionDefinitionsBuilder(
{G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
- .legalFor({s32, s64});
+ .legalFor({f32, f64});
LoadStoreBuilder
.legalForTypesWithMemDesc({{s64, p0, s64, 32}})
@@ -146,18 +156,15 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
PhiBuilder.legalFor({s64});
getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1},
- {s32, s64});
-
- getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}});
- getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}});
+ {f32, f64});
- getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}});
- getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}});
+ getActionDefinitionsBuilder(G_FPEXT).legalFor({{f64, f32}});
+ getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{f32, f64}});
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
- .legalForCartesianProduct({s32}, {s32, s64});
+ .legalForCartesianProduct({s32}, {f32, f64});
getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
- .legalForCartesianProduct({s32, s64}, {s32});
+ .legalForCartesianProduct({f32, f64}, {s32});
getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV, G_GET_FPMODE})
.legalFor({s32});
@@ -166,7 +173,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
getActionDefinitionsBuilder(G_RESET_FPMODE).custom();
} else {
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
- .libcallFor({s32, s64});
+ .libcallFor({f32, f64});
LoadStoreBuilder.maxScalar(0, s32);
@@ -175,20 +182,20 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64});
getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1},
- {s32, s64});
+ {f32, f64});
if (AEABI(ST))
setFCmpLibcallsAEABI();
else
setFCmpLibcallsGNU();
- getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}});
- getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}});
+ getActionDefinitionsBuilder(G_FPEXT).libcallFor({{f64, f32}});
+ getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{f32, f64}});
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
- .libcallForCartesianProduct({s32}, {s32, s64});
+ .libcallForCartesianProduct({s32}, {f32, f64});
getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
- .libcallForCartesianProduct({s32, s64}, {s32});
+ .libcallForCartesianProduct({f32, f64}, {s32});
getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV})
.libcall();
@@ -200,11 +207,11 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
LoadStoreBuilder.lower();
if (!ST.useSoftFloat() && ST.hasVFP4Base())
- getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64});
+ getActionDefinitionsBuilder(G_FMA).legalFor({f32, f64});
else
- getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64});
+ getActionDefinitionsBuilder(G_FMA).libcallFor({f32, f64});
- getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
+ getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({f32, f64});
if (ST.hasV5TOps() && !ST.isThumb1Only()) {
getActionDefinitionsBuilder(G_CTLZ)
@@ -363,7 +370,7 @@ bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
// destination of the original instruction for the remainder.
Type *ArgTy = Type::getInt32Ty(Ctx);
StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
- Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
+ Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::integer(32)),
OriginalResult};
auto Status = Helper.createLibcall(Libcall, {RetRegs, RetTy, 0},
{{MI.getOperand(1).getReg(), ArgTy, 0},
@@ -400,7 +407,7 @@ bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
SmallVector<Register, 2> Results;
for (auto Libcall : Libcalls) {
- auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
+ auto LibcallResult = MRI.createGenericVirtualRegister(LLT::integer(32));
auto Status =
Helper.createLibcall(Libcall.LibcallID, {LibcallResult, RetTy, 0},
{{MI.getOperand(2).getReg(), ArgTy, 0},
@@ -426,7 +433,7 @@ bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
} else {
// We need to compare against 0.
assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
- auto Zero = MIRBuilder.buildConstant(LLT::scalar(32), 0);
+ auto Zero = MIRBuilder.buildConstant(LLT::integer(32), 0);
MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
}
Results.push_back(ProcessedResult);
@@ -455,7 +462,7 @@ bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
}
case G_SET_FPMODE: {
// New FPSCR = (FPSCR & FPStatusBits) | (Modes & ~FPStatusBits)
- LLT FPEnvTy = LLT::scalar(32);
+ LLT FPEnvTy = LLT::integer(32);
auto FPEnv = MRI.createGenericVirtualRegister(FPEnvTy);
Register Modes = MI.getOperand(0).getReg();
MIRBuilder.buildGetFPEnv(FPEnv);
@@ -471,7 +478,7 @@ bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
case G_RESET_FPMODE: {
// To get the default FP mode all control bits are cleared:
// FPSCR = FPSCR & (FPStatusBits | FPReservedBits)
- LLT FPEnvTy = LLT::scalar(32);
+ LLT FPEnvTy = LLT::integer(32);
auto FPEnv = MIRBuilder.buildGetFPEnv(FPEnvTy);
auto NotModeBitMask = MIRBuilder.buildConstant(
FPEnvTy, ARM::FPStatusBits | ARM::FPReservedBits);
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index 0493fd9e317d5..616d22c895910 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -436,6 +436,9 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case G_RESET_FPENV:
OperandsMapping = getOperandsMapping({nullptr});
break;
+ case G_BITCAST:
+ OperandsMapping = &ARM::ValueMappings[ARM::SPR3OpsIdx];
+ break;
default:
return getInvalidInstructionMapping();
}
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index f8dbc7907f64b..423f497429cac 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -190,6 +190,8 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
initAsmInfo();
+ LLT::setUseExtended(true);
+
// ARM supports the MachineOutliner.
setMachineOutliner(true);
setSupportsDefaultOutlining(true);
diff --git a/llvm/lib/Target/ARM/CMakeLists.txt b/llvm/lib/Target/ARM/CMakeLists.txt
index d99368e1d3b2b..db6693953ffaa 100644
--- a/llvm/lib/Target/ARM/CMakeLists.txt
+++ b/llvm/lib/Target/ARM/CMakeLists.txt
@@ -8,7 +8,7 @@ tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel -gisel-extended-llt)
tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
index 4dd8af01f873d..48ed606033832 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
@@ -61,14 +61,14 @@ body: |
; CHECK: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MLA]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
+ %2(i32) = COPY $r2
- %3(s32) = G_MUL %0, %1
- %4(s32) = G_ADD %3, %2
+ %3(i32) = G_MUL %0, %1
+ %4(i32) = G_ADD %3, %2
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -94,14 +94,14 @@ body: |
; CHECK: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MLA]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
+ %2(i32) = COPY $r2
- %3(s32) = G_MUL %0, %1
- %4(s32) = G_ADD %2, %3
+ %3(i32) = G_MUL %0, %1
+ %4(i32) = G_ADD %2, %3
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -127,14 +127,14 @@ body: |
; CHECK: early-clobber %4:gprnopc = MLAv5 [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY %4
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
+ %2(i32) = COPY $r2
- %3(s32) = G_MUL %0, %1
- %4(s32) = G_ADD %3, %2
+ %3(i32) = G_MUL %0, %1
+ %4(i32) = G_ADD %3, %2
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -160,14 +160,14 @@ body: |
; CHECK: [[MLS:%[0-9]+]]:gpr = MLS [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[MLS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
+ %2(i32) = COPY $r2
- %3(s32) = G_MUL %0, %1
- %4(s32) = G_SUB %2, %3
+ %3(i32) = G_MUL %0, %1
+ %4(i32) = G_SUB %2, %3
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -194,14 +194,14 @@ body: |
; CHECK: [[SUBrr:%[0-9]+]]:gpr = SUBrr [[COPY2]], %3, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[SUBrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
+ %2(i32) = COPY $r2
- %3(s32) = G_MUL %0, %1
- %4(s32) = G_SUB %2, %3
+ %3(i32) = G_MUL %0, %1
+ %4(i32) = G_SUB %2, %3
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -226,14 +226,14 @@ body: |
; CHECK: [[BICrr:%[0-9]+]]:gpr = BICrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
- %2(s32) = G_CONSTANT i32 -1
- %3(s32) = G_XOR %1, %2
- %4(s32) = G_AND %0, %3
+ %2(i32) = G_CONSTANT i32 -1
+ %3(i32) = G_XOR %1, %2
+ %4(i32) = G_AND %0, %3
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -258,14 +258,14 @@ body: |
; CHECK: [[BICrr:%[0-9]+]]:gpr = BICrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
- %2(s32) = G_CONSTANT i32 -1
- %3(s32) = G_XOR %1, %2
- %4(s32) = G_AND %3, %0
+ %2(i32) = G_CONSTANT i32 -1
+ %3(i32) = G_XOR %1, %2
+ %4(i32) = G_AND %3, %0
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -289,20 +289,20 @@ body: |
; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
; This test and the following ones are a bit contrived, since they use a
; G_XOR that can be constant-folded. They exist mostly to validate the
; TableGen pattern that defines BICri. We also have a pattern for matching a
; G_AND with a G_CONSTANT operand directly, which is the more common case,
; but that will be covered by different tests.
- %1(s32) = G_CONSTANT i32 192
+ %1(i32) = G_CONSTANT i32 192
- %2(s32) = G_CONSTANT i32 -1
- %3(s32) = G_XOR %1, %2
- %4(s32) = G_AND %0, %3
+ %2(i32) = G_CONSTANT i32 -1
+ %3(i32) = G_XOR %1, %2
+ %4(i32) = G_AND %0, %3
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -326,15 +326,15 @@ body: |
; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 192
+ %1(i32) = G_CONSTANT i32 192
- %2(s32) = G_CONSTANT i32 -1
- %3(s32) = G_XOR %2, %1
- %4(s32) = G_AND %0, %3
+ %2(i32) = G_CONSTANT i32 -1
+ %3(i32) = G_XOR %2, %1
+ %4(i32) = G_AND %0, %3
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -358,15 +358,15 @@ body: |
; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 192
+ %1(i32) = G_CONSTANT i32 192
- %2(s32) = G_CONSTANT i32 -1
- %3(s32) = G_XOR %1, %2
- %4(s32) = G_AND %3, %0
+ %2(i32) = G_CONSTANT i32 -1
+ %3(i32) = G_XOR %1, %2
+ %4(i32) = G_AND %3, %0
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -390,15 +390,15 @@ body: |
; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[BICri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 192
+ %1(i32) = G_CONSTANT i32 192
- %2(s32) = G_CONSTANT i32 -1
- %3(s32) = G_XOR %2, %1
- %4(s32) = G_AND %3, %0
+ %2(i32) = G_CONSTANT i32 -1
+ %3(i32) = G_XOR %2, %1
+ %4(i32) = G_AND %3, %0
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -420,13 +420,13 @@ body: |
; CHECK: [[MOVTi16_:%[0-9]+]]:gprnopc = MOVTi16 [[COPY]], 65535, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[MOVTi16_]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %1(i32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
- %2(s32) = G_OR %0, %1
+ %2(i32) = G_OR %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -450,13 +450,13 @@ body: |
; CHECK: [[VNMULS:%[0-9]+]]:spr = nofpexcept VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
; CHECK: $s0 = COPY [[VNMULS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
- %2(s32) = G_FMUL %0, %1
- %3(s32) = G_FNEG %2
+ %2(f32) = G_FMUL %0, %1
+ %3(f32) = G_FNEG %2
- $s0 = COPY %3(s32)
+ $s0 = COPY %3(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -480,13 +480,13 @@ body: |
; CHECK: [[VNMULS:%[0-9]+]]:spr = nofpexcept VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
; CHECK: $s0 = COPY [[VNMULS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
- %2(s32) = G_FNEG %0
- %3(s32) = G_FMUL %1, %2
+ %2(f32) = G_FNEG %0
+ %3(f32) = G_FMUL %1, %2
- $s0 = COPY %3(s32)
+ $s0 = COPY %3(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -510,13 +510,13 @@ body: |
; CHECK: [[VNMULD:%[0-9]+]]:dpr = nofpexcept VNMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
; CHECK: $d0 = COPY [[VNMULD]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
- %2(s64) = G_FMUL %0, %1
- %3(s64) = G_FNEG %2
+ %2(f64) = G_FMUL %0, %1
+ %3(f64) = G_FNEG %2
- $d0 = COPY %3(s64)
+ $d0 = COPY %3(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -542,14 +542,14 @@ body: |
; CHECK: [[VFNMAS:%[0-9]+]]:spr = nofpexcept VFNMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
; CHECK: $s0 = COPY [[VFNMAS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = COPY $s2
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = COPY $s2
- %3(s32) = G_FMA %0, %1, %2
- %4(s32) = G_FNEG %3
+ %3(f32) = G_FMA %0, %1, %2
+ %4(f32) = G_FNEG %3
- $s0 = COPY %4(s32)
+ $s0 = COPY %4(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -576,15 +576,15 @@ body: |
; CHECK: [[VFNMAD:%[0-9]+]]:dpr = nofpexcept VFNMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
; CHECK: $d0 = COPY [[VFNMAD]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
- %2(s64) = COPY $d2
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
+ %2(f64) = COPY $d2
- %3(s64) = G_FNEG %0
- %4(s64) = G_FNEG %2
- %5(s64) = G_FMA %3, %1, %4
+ %3(f64) = G_FNEG %0
+ %4(f64) = G_FNEG %2
+ %5(f64) = G_FMA %3, %1, %4
- $d0 = COPY %5(s64)
+ $d0 = COPY %5(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -610,14 +610,14 @@ body: |
; CHECK: [[VFMSS:%[0-9]+]]:spr = nofpexcept VFMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
; CHECK: $s0 = COPY [[VFMSS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = COPY $s2
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = COPY $s2
- %3(s32) = G_FNEG %0
- %4(s32) = G_FMA %3, %1, %2
+ %3(f32) = G_FNEG %0
+ %4(f32) = G_FMA %3, %1, %2
- $s0 = COPY %4(s32)
+ $s0 = COPY %4(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -643,14 +643,14 @@ body: |
; CHECK: [[VFMSD:%[0-9]+]]:dpr = nofpexcept VFMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr
; CHECK: $d0 = COPY [[VFMSD]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
- %1(s64) = COPY $d1
- %2(s64) = COPY $d2
+ %0(f64) = COPY $d0
+ %1(f64) = COPY $d1
+ %2(f64) = COPY $d2
- %3(s64) = G_FNEG %1
- %4(s64) = G_FMA %0, %3, %2
+ %3(f64) = G_FNEG %1
+ %4(f64) = G_FMA %0, %3, %2
- $d0 = COPY %4(s64)
+ $d0 = COPY %4(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -676,14 +676,14 @@ body: |
; CHECK: [[VFNMSS:%[0-9]+]]:spr = nofpexcept VFNMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
; CHECK: $s0 = COPY [[VFNMSS]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
- %1(s32) = COPY $s1
- %2(s32) = COPY $s2
+ %0(f32) = COPY $s0
+ %1(f32) = COPY $s1
+ %2(f32) = COPY $s2
- %3(s32) = G_FNEG %2
- %4(s32) = G_FMA %0, %1, %3
+ %3(f32) = G_FNEG %2
+ %4(f32) = G_FMA %0, %1, %3
- $s0 = COPY %4(s32)
+ $s0 = COPY %4(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -705,11 +705,11 @@ body: |
; CHECK: [[BFC:%[0-9]+]]:gpr = BFC [[COPY]], -65529, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[BFC]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007
- %2(s32) = G_AND %0, %1
+ %0(i32) = COPY $r0
+ %1(i32) = G_CONSTANT i32 -65529 ; 0xFFFF0007
+ %2(i32) = G_AND %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -731,11 +731,11 @@ body: |
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 6, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = G_CONSTANT i32 6 ; 0x00000006
- %2(s32) = G_AND %0, %1
+ %0(i32) = COPY $r0
+ %1(i32) = G_CONSTANT i32 6 ; 0x00000006
+ %2(i32) = G_AND %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index 935bbd34651f4..8ba8bdc7ed557 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -84,13 +84,13 @@ body: |
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s1) = G_TRUNC %0(s32)
+ %1(i1) = G_TRUNC %0(i32)
- %2(s32) = G_ZEXT %1(s1)
+ %2(i32) = G_ZEXT %1(i1)
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -113,13 +113,13 @@ body: |
; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[RSBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s1) = G_TRUNC %0(s32)
+ %1(i1) = G_TRUNC %0(i32)
- %2(s32) = G_SEXT %1(s1)
+ %2(i32) = G_SEXT %1(i1)
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -142,13 +142,13 @@ body: |
; CHECK: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[SXTB]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s8) = G_TRUNC %0(s32)
+ %1(i8) = G_TRUNC %0(i32)
- %2(s32) = G_SEXT %1(s8)
+ %2(i32) = G_SEXT %1(i8)
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -171,13 +171,13 @@ body: |
; CHECK: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[UXTH]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s16) = G_TRUNC %0(s32)
+ %1(i16) = G_TRUNC %0(i32)
- %2(s32) = G_ZEXT %1(s16)
+ %2(i32) = G_ZEXT %1(i16)
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -198,13 +198,13 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s8) = G_TRUNC %0(s32)
+ %1(i8) = G_TRUNC %0(i32)
- %2(s32) = G_ANYEXT %1(s8)
+ %2(i32) = G_ANYEXT %1(i8)
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -225,13 +225,13 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s16) = G_TRUNC %0(s32)
+ %1(i16) = G_TRUNC %0(i32)
- %2(s32) = G_ANYEXT %1(s16)
+ %2(i32) = G_ANYEXT %1(i16)
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -259,13 +259,13 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s1) = G_TRUNC %1(s32)
+ %2(i1) = G_TRUNC %1(i32)
- %3(s16) = G_ZEXT %2(s1)
+ %3(i16) = G_ZEXT %2(i1)
- G_STORE %3(s16), %0(p0) :: (store (s16))
+ G_STORE %3(i16), %0(p0) :: (store (s16))
BX_RET 14, $noreg
...
@@ -294,13 +294,13 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s1) = G_TRUNC %1(s32)
+ %2(i1) = G_TRUNC %1(i32)
- %3(s16) = G_SEXT %2(s1)
+ %3(i16) = G_SEXT %2(i1)
- G_STORE %3(s16), %0(p0) :: (store (s16))
+ G_STORE %3(i16), %0(p0) :: (store (s16))
BX_RET 14, $noreg
...
@@ -327,13 +327,13 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s1) = G_TRUNC %1(s32)
+ %2(i1) = G_TRUNC %1(i32)
- %3(s16) = G_ANYEXT %2(s1)
+ %3(i16) = G_ANYEXT %2(i1)
- G_STORE %3(s16), %0(p0) :: (store (s16))
+ G_STORE %3(i16), %0(p0) :: (store (s16))
BX_RET 14, $noreg
...
@@ -362,13 +362,13 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s8) = G_TRUNC %1(s32)
+ %2(i8) = G_TRUNC %1(i32)
- %3(s16) = G_ZEXT %2(s8)
+ %3(i16) = G_ZEXT %2(i8)
- G_STORE %3(s16), %0(p0) :: (store (s16))
+ G_STORE %3(i16), %0(p0) :: (store (s16))
BX_RET 14, $noreg
...
@@ -397,13 +397,13 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s8) = G_TRUNC %1(s32)
+ %2(i8) = G_TRUNC %1(i32)
- %3(s16) = G_SEXT %2(s8)
+ %3(i16) = G_SEXT %2(i8)
- G_STORE %3(s16), %0(p0) :: (store (s16))
+ G_STORE %3(i16), %0(p0) :: (store (s16))
BX_RET 14, $noreg
...
@@ -430,13 +430,13 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s8) = G_TRUNC %1(s32)
+ %2(i8) = G_TRUNC %1(i32)
- %3(s16) = G_ANYEXT %2(s8)
+ %3(i16) = G_ANYEXT %2(i8)
- G_STORE %3(s16), %0(p0) :: (store (s16))
+ G_STORE %3(i16), %0(p0) :: (store (s16))
BX_RET 14, $noreg
...
@@ -464,13 +464,13 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s1) = G_TRUNC %1(s32)
+ %2(i1) = G_TRUNC %1(i32)
- %3(s8) = G_ZEXT %2(s1)
+ %3(i8) = G_ZEXT %2(i1)
- G_STORE %3(s8), %0(p0) :: (store (s8))
+ G_STORE %3(i8), %0(p0) :: (store (s8))
BX_RET 14, $noreg
...
@@ -499,13 +499,13 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s1) = G_TRUNC %1(s32)
+ %2(i1) = G_TRUNC %1(i32)
- %3(s8) = G_SEXT %2(s1)
+ %3(i8) = G_SEXT %2(i1)
- G_STORE %3(s8), %0(p0) :: (store (s8))
+ G_STORE %3(i8), %0(p0) :: (store (s8))
BX_RET 14, $noreg
...
@@ -533,13 +533,13 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s1) = G_TRUNC %1(s32)
+ %2(i1) = G_TRUNC %1(i32)
- %3(s8) = G_ANYEXT %2(s1)
+ %3(i8) = G_ANYEXT %2(i1)
- G_STORE %3(s8), %0(p0) :: (store (s8))
+ G_STORE %3(i8), %0(p0) :: (store (s8))
BX_RET 14, $noreg
...
@@ -562,13 +562,13 @@ body: |
; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ADDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_ADD %0, %1
+ %2(i32) = G_ADD %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -590,12 +590,12 @@ body: |
; CHECK: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 255, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ADDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 255
- %2(s32) = G_ADD %0, %1
+ %1(i32) = G_CONSTANT i32 255
+ %2(i32) = G_ADD %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -618,13 +618,13 @@ body: |
; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[MOVi16_]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[ADDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 65535
+ %1(i32) = G_CONSTANT i32 65535
- %2(s32) = G_ADD %0, %1
+ %2(i32) = G_ADD %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -647,13 +647,13 @@ body: |
; CHECK: [[SUBrr:%[0-9]+]]:gpr = SUBrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[SUBrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_SUB %0, %1
+ %2(i32) = G_SUB %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -675,12 +675,12 @@ body: |
; CHECK: [[SUBri:%[0-9]+]]:gpr = SUBri [[COPY]], 17, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[SUBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 17
- %2(s32) = G_SUB %0, %1
+ %1(i32) = G_CONSTANT i32 17
+ %2(i32) = G_SUB %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -702,12 +702,12 @@ body: |
; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 17, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[RSBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 17
- %2(s32) = G_SUB %1, %0
+ %1(i32) = G_CONSTANT i32 17
+ %2(i32) = G_SUB %1, %0
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -730,13 +730,13 @@ body: |
; CHECK: [[MUL:%[0-9]+]]:gprnopc = MUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MUL]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_MUL %0, %1
+ %2(i32) = G_MUL %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -759,13 +759,13 @@ body: |
; CHECK: early-clobber %2:gprnopc = MULv5 [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY %2
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_MUL %0, %1
+ %2(i32) = G_MUL %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -788,13 +788,13 @@ body: |
; CHECK: [[SDIV:%[0-9]+]]:gpr = SDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[SDIV]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_SDIV %0, %1
+ %2(i32) = G_SDIV %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -817,13 +817,13 @@ body: |
; CHECK: [[UDIV:%[0-9]+]]:gpr = UDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[UDIV]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_UDIV %0, %1
+ %2(i32) = G_UDIV %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -846,13 +846,13 @@ body: |
; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVsr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_LSHR %0, %1
+ %2(i32) = G_LSHR %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -875,13 +875,13 @@ body: |
; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVsr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_ASHR %0, %1
+ %2(i32) = G_ASHR %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -904,13 +904,13 @@ body: |
; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVsr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_SHL %0, %1
+ %2(i32) = G_SHL %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -944,15 +944,15 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = G_FRAME_INDEX %fixed-stack.2
- %1(s32) = G_LOAD %0(p0) :: (load (s32))
+ %1(i32) = G_LOAD %0(p0) :: (load (s32))
$r0 = COPY %1
%2(p0) = G_FRAME_INDEX %fixed-stack.0
- %3(s8) = G_LOAD %2(p0) :: (load (s8))
+ %3(i8) = G_LOAD %2(p0) :: (load (s8))
- %4(s32) = G_ANYEXT %3(s8)
+ %4(i32) = G_ANYEXT %3(i8)
$r0 = COPY %4
@@ -983,17 +983,17 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %3(s32) = COPY $r1
+ %3(i32) = COPY $r1
- %1(s8) = G_TRUNC %3(s32)
+ %1(i8) = G_TRUNC %3(i32)
- %2(s16) = G_TRUNC %3(s32)
+ %2(i16) = G_TRUNC %3(i32)
- G_STORE %1(s8), %0(p0) :: (store (s8))
+ G_STORE %1(i8), %0(p0) :: (store (s8))
- G_STORE %2(s16), %0(p0) :: (store (s16))
+ G_STORE %2(i16), %0(p0) :: (store (s16))
- G_STORE %3(s32), %0(p0) :: (store (s32))
+ G_STORE %3(i32), %0(p0) :: (store (s32))
BX_RET 14, $noreg
...
@@ -1018,9 +1018,9 @@ body: |
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(p0) = G_PTR_ADD %0, %1(s32)
+ %2(p0) = G_PTR_ADD %0, %1(i32)
$r0 = COPY %2(p0)
BX_RET 14, $noreg, implicit $r0
@@ -1038,9 +1038,9 @@ body: |
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr = MOVi32imm 65537
; CHECK: $r0 = COPY [[MOVi32imm]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = G_CONSTANT i32 65537
+ %0(i32) = G_CONSTANT i32 65537
- $r0 = COPY %0(s32)
+ $r0 = COPY %0(i32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -1056,9 +1056,9 @@ body: |
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 42, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVi]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = G_CONSTANT i32 42
+ %0(i32) = G_CONSTANT i32 42
- $r0 = COPY %0(s32)
+ $r0 = COPY %0(i32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -1076,9 +1076,9 @@ body: |
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 42, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[MOVi]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = G_CONSTANT i32 42
+ %0(i32) = G_CONSTANT i32 42
- $r0 = COPY %0(s32)
+ $r0 = COPY %0(i32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -1133,8 +1133,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(p0) = G_INTTOPTR %0(s32)
+ %0(i32) = COPY $r0
+ %1(p0) = G_INTTOPTR %0(i32)
$r0 = COPY %1(p0)
@@ -1157,9 +1157,9 @@ body: |
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0
- %1(s32) = G_PTRTOINT %0(p0)
+ %1(i32) = G_PTRTOINT %0(p0)
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -1184,15 +1184,15 @@ body: |
; CHECK: [[MOVCCr:%[0-9]+]]:gpr = MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
; CHECK: $r0 = COPY [[MOVCCr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s1) = G_TRUNC %1(s32)
+ %2(i1) = G_TRUNC %1(i32)
- %3(s32) = G_SELECT %2(s1), %0, %1
+ %3(i32) = G_SELECT %2(i1), %0, %1
- $r0 = COPY %3(s32)
+ $r0 = COPY %3(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -1223,11 +1223,11 @@ body: |
%1(p0) = COPY $r1
- %2(s32) = COPY $r2
+ %2(i32) = COPY $r2
- %3(s1) = G_TRUNC %2(s32)
+ %3(i1) = G_TRUNC %2(i32)
- %4(p0) = G_SELECT %3(s1), %0, %1
+ %4(p0) = G_SELECT %3(i1), %0, %1
$r0 = COPY %4(p0)
@@ -1258,10 +1258,10 @@ body: |
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0
- %0(s32) = COPY $r0
- %1(s1) = G_TRUNC %0(s32)
+ %0(i32) = COPY $r0
+ %1(i1) = G_TRUNC %0(i32)
- G_BRCOND %1(s1), %bb.1
+ G_BRCOND %1(i1), %bb.1
G_BR %bb.2
bb.1:
@@ -1307,13 +1307,13 @@ body: |
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $r1, $r2
- %0(s32) = COPY $r0
- %1(s1) = G_TRUNC %0(s32)
+ %0(i32) = COPY $r0
+ %1(i1) = G_TRUNC %0(i32)
- %2(s32) = COPY $r1
- %3(s32) = COPY $r2
+ %2(i32) = COPY $r1
+ %3(i32) = COPY $r2
- G_BRCOND %1(s1), %bb.1
+ G_BRCOND %1(i1), %bb.1
G_BR %bb.2
bb.1:
@@ -1322,8 +1322,8 @@ body: |
G_BR %bb.2
bb.2:
- %4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1
+ %4(i32) = G_PHI %2(i32), %bb.0, %3(i32), %bb.1
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
index 7df230ccda67e..6c04261404b13 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
@@ -1,248 +1,310 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE
; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -enable-arm-gisel-bigendian -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG
define void @test_void_return() {
-; CHECK-LABEL: name: test_void_return
-; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-LABEL: name: test_void_return
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
entry:
ret void
}
define signext i1 @test_add_i1(i1 %x, i1 %y) {
-; CHECK-LABEL: name: test_add_i1
-; CHECK: liveins: $r0, $r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR1]]
-; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]]
-; CHECK: $r0 = COPY [[EXT]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_add_i1
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i1) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i1) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i1) = G_ADD [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[ADD]](i1)
+ ; CHECK-NEXT: $r0 = COPY [[SEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%sum = add i1 %x, %y
ret i1 %sum
}
define i8 @test_add_i8(i8 %x, i8 %y) {
-; CHECK-LABEL: name: test_add_i8
-; CHECK: liveins: $r0, $r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
-; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: $r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_add_i8
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i8) = G_ADD [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ADD]](i8)
+ ; CHECK-NEXT: $r0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%sum = add i8 %x, %y
ret i8 %sum
}
define i8 @test_sub_i8(i8 %x, i8 %y) {
-; CHECK-LABEL: name: test_sub_i8
-; CHECK: liveins: $r0, $r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
-; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]]
-; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
-; CHECK: $r0 = COPY [[RES_EXT]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_sub_i8
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i8) = G_SUB [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SUB]](i8)
+ ; CHECK-NEXT: $r0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%res = sub i8 %x, %y
ret i8 %res
}
define signext i8 @test_return_sext_i8(i8 %x) {
-; CHECK-LABEL: name: test_return_sext_i8
-; CHECK: liveins: $r0
-; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
-; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]
-; CHECK: $r0 = COPY [[VREGEXT]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_return_sext_i8
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i32) = G_SEXT [[TRUNC]](i8)
+ ; CHECK-NEXT: $r0 = COPY [[SEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
ret i8 %x
}
define i16 @test_add_i16(i16 %x, i16 %y) {
-; CHECK-LABEL: name: test_add_i16
-; CHECK: liveins: $r0, $r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
-; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: $r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_add_i16
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i16) = G_ADD [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ADD]](i16)
+ ; CHECK-NEXT: $r0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%sum = add i16 %x, %y
ret i16 %sum
}
define i16 @test_sub_i16(i16 %x, i16 %y) {
-; CHECK-LABEL: name: test_sub_i16
-; CHECK: liveins: $r0, $r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
-; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]]
-; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
-; CHECK: $r0 = COPY [[RES_EXT]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_sub_i16
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i16) = G_SUB [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SUB]](i16)
+ ; CHECK-NEXT: $r0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%res = sub i16 %x, %y
ret i16 %res
}
define zeroext i16 @test_return_zext_i16(i16 %x) {
-; CHECK-LABEL: name: test_return_zext_i16
-; CHECK: liveins: $r0
-; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
-; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]
-; CHECK: $r0 = COPY [[VREGEXT]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_return_zext_i16
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC]](i16)
+ ; CHECK-NEXT: $r0 = COPY [[ZEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
ret i16 %x
}
define i32 @test_add_i32(i32 %x, i32 %y) {
-; CHECK-LABEL: name: test_add_i32
-; CHECK: liveins: $r0, $r1
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: $r0 = COPY [[SUM]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_add_i32
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $r0 = COPY [[ADD]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%sum = add i32 %x, %y
ret i32 %sum
}
define i32 @test_sub_i32(i32 %x, i32 %y) {
-; CHECK-LABEL: name: test_sub_i32
-; CHECK: liveins: $r0, $r1
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]]
-; CHECK: $r0 = COPY [[RES]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_sub_i32
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $r0 = COPY [[SUB]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%res = sub i32 %x, %y
ret i32 %res
}
define i32 @test_stack_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
-; CHECK-LABEL: name: test_stack_args
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4
-; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: $r0, $r1, $r2, $r3
-; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY $r2
-; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
-; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load (s32)
-; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]]
-; CHECK: $r0 = COPY [[SUM]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_stack_args
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $r2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $r3
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i32) from %fixed-stack.1, align 8)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (i32) from %fixed-stack.0)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[COPY2]], [[LOAD1]]
+ ; CHECK-NEXT: $r0 = COPY [[ADD]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%sum = add i32 %p2, %p5
ret i32 %sum
}
define i16 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
+ ; CHECK-LABEL: name: test_stack_args_signext
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $r2
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[COPY2]](i32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $r3
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i1) = G_TRUNC [[COPY3]](i32)
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i32) from %fixed-stack.1, align 8)
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[LOAD]], 8
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (i32) from %fixed-stack.0)
+ ; CHECK-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[LOAD1]], 16
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_SEXT1]](i32)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i16) = G_ADD [[TRUNC]], [[TRUNC4]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ADD]](i16)
+ ; CHECK-NEXT: $r0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
i8 signext %p4, i16 signext %p5) {
-; CHECK-LABEL: name: test_stack_args_signext
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4
-; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: $r0, $r1, $r2, $r3
-; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK: [[VREGP1:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
-; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
-; CHECK: [[VREGP5EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load (s32)
-; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[VREGP5EXT]], 16
-; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]]
-; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]]
-; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: $r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%sum = add i16 %p1, %p5
ret i16 %sum
}
define i8 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
+ ; CHECK-LABEL: name: test_stack_args_zeroext
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $r2
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[COPY2]](i32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $r3
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i1) = G_TRUNC [[COPY3]](i32)
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i32) from %fixed-stack.1, align 8)
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[LOAD]], 8
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_ZEXT]](i32)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (i32) from %fixed-stack.0)
+ ; CHECK-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(i32) = G_ASSERT_ZEXT [[LOAD1]], 16
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_ZEXT1]](i32)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i8) = G_ADD [[TRUNC1]], [[TRUNC3]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ADD]](i8)
+ ; CHECK-NEXT: $r0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
i8 zeroext %p4, i16 zeroext %p5) {
-; CHECK-LABEL: name: test_stack_args_zeroext
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4
-; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: $r0, $r1, $r2, $r3
-; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2
-; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
-; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
-; CHECK: [[VREGP4EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load (s32)
-; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[VREGP4EXT]], 8
-; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]]
-; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
-; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: $r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%sum = add i8 %p2, %p4
ret i8 %sum
}
define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
+ ; CHECK-LABEL: name: test_stack_args_noext
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $r2
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[COPY2]](i32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $r3
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i1) = G_TRUNC [[COPY3]](i32)
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i32) from %fixed-stack.1, align 8)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[LOAD]](i32)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (i32) from %fixed-stack.0)
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[LOAD1]](i32)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i8) = G_ADD [[TRUNC1]], [[TRUNC3]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ADD]](i8)
+ ; CHECK-NEXT: $r0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
i8 %p4, i16 %p5) {
-; CHECK-LABEL: name: test_stack_args_noext
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0, size: 4, alignment: 8,
-; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4, size: 4, alignment: 4,
-; CHECK: liveins: $r0, $r1, $r2, $r3
-; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2
-; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
-; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
-; CHECK: [[VREGP4:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load (s32)
-; CHECK: [[TRUNC_VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[VREGP4]]
-; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[TRUNC_VREGP4]]
-; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: $r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%sum = add i8 %p2, %p4
ret i8 %sum
}
define zeroext i16 @test_stack_args_extend_the_extended(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
+ ; CHECK-LABEL: name: test_stack_args_extend_the_extended
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $r2
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i8) = G_TRUNC [[COPY2]](i32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $r3
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i1) = G_TRUNC [[COPY3]](i32)
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (i32) from %fixed-stack.1, align 8)
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[LOAD]], 8
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i8) = G_TRUNC [[ASSERT_SEXT]](i32)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (i32) from %fixed-stack.0)
+ ; CHECK-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[LOAD1]], 16
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[ASSERT_SEXT1]](i32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[TRUNC4]](i16)
+ ; CHECK-NEXT: $r0 = COPY [[ZEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
i8 signext %p4, i16 signext %p5) {
-; CHECK-LABEL: name: test_stack_args_extend_the_extended
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4, alignment: 8
-; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4, alignment: 4
-; CHECK: liveins: $r0, $r1, $r2, $r3
-; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
-; CHECK: [[VREGP5SEXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load (s32)
-; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[VREGP5SEXT]], 16
-; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]]
-; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]]
-; CHECK: $r0 = COPY [[VREGP5ZEXT]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
ret i16 %p5
}
define i16 @test_ptr_arg(ptr %p) {
-; CHECK-LABEL: name: test_ptr_arg
-; CHECK: liveins: $r0
-; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0
-; CHECK: [[VREGV:%[0-9]+]]:_(s16) = G_LOAD [[VREGP]](p0){{.*}}load (s16)
+ ; CHECK-LABEL: name: test_ptr_arg
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i16) = G_LOAD [[COPY]](p0) :: (load (i16) from %ir.p)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[LOAD]](i16)
+ ; CHECK-NEXT: $r0 = COPY [[ANYEXT]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%v = load i16, ptr %p
ret i16 %v
@@ -250,51 +312,94 @@ entry:
define ptr @test_ptr_ret(ptr %p) {
; Test pointer returns and pointer-to-pointer arguments
-; CHECK-LABEL: name: test_ptr_ret
-; CHECK: liveins: $r0
-; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0
-; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load (p0)
-; CHECK: $r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_ptr_ret
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load (p0) from %ir.p)
+ ; CHECK-NEXT: $r0 = COPY [[LOAD]](p0)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%v = load ptr, ptr %p
ret ptr %v
}
define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, ptr %p) {
-; CHECK-LABEL: name: test_ptr_arg_on_stack
-; CHECK: fixedStack:
-; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
-; CHECK: liveins: $r0, $r1, $r2, $r3
-; CHECK: [[FIP:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P]]
-; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load (p0)
-; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load (s32)
-; CHECK: $r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-LABEL: name: test_ptr_arg_on_stack
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $r2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $r3
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[LOAD]](p0) :: (load (i32) from %ir.p)
+ ; CHECK-NEXT: $r0 = COPY [[LOAD1]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%v = load i32, ptr %p
ret i32 %v
}
define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2,
+ ; CHECK-LABEL: name: test_float_aapcscc
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[COPY]](i32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[COPY1]](i32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $r2
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[COPY2]](i32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $r3
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[COPY3]](i32)
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (f32) from %fixed-stack.1, align 8)
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[LOAD]](i32)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (f32) from %fixed-stack.0)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[LOAD1]](i32)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[BITCAST5]]
+ ; CHECK-NEXT: $r0 = COPY [[FADD]](f32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
float %p3, float %p4, float %p5) {
-; CHECK-LABEL: name: test_float_aapcscc
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
-; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: $r0, $r1, $r2, $r3
-; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
-; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load (s32)
-; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]]
-; CHECK: $r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
entry:
%v = fadd float %p1, %p5
ret float %v
}
define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2,
+ ; CHECK-LABEL: name: test_float_vfpcc
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $s0, $s1, $s2, $s3, $s4, $s5, $s6, $s7, $s8, $s9, $s10, $s11, $s12, $s13, $s14, $s15
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $s2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $s3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY $s4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(f32) = COPY $s5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(f32) = COPY $s6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(f32) = COPY $s7
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $s8
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $s9
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $s10
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $s11
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $s12
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $s13
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(f32) = COPY $s14
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(f32) = COPY $s15
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (f32) from %fixed-stack.1, align 8)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (f32) from %fixed-stack.0)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY1]], [[LOAD1]]
+ ; CHECK-NEXT: $s0 = COPY [[FADD]](f32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
float %p3, float %p4, float %p5,
float %ridiculous,
float %number,
@@ -307,142 +412,215 @@ define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2,
float %in,
float %practice,
float %q0, float %q1) {
-; CHECK-LABEL: name: test_float_vfpcc
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
-; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: $s0, $s1, $s2, $s3, $s4, $s5, $s6, $s7, $s8, $s9, $s10, $s11, $s12, $s13, $s14, $s15
-; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
-; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load (s32)
-; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]]
-; CHECK: $s0 = COPY [[VREGV]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
entry:
%v = fadd float %p1, %q1
ret float %v
}
define arm_aapcs_vfpcc double @test_double_vfpcc(double %p0, double %p1, double %p2,
+ ; CHECK-LABEL: name: test_double_vfpcc
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f64) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f64) = COPY $d3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f64) = COPY $d4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(f64) = COPY $d5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(f64) = COPY $d6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(f64) = COPY $d7
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (f64) from %fixed-stack.1)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (f64) from %fixed-stack.0)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[COPY1]], [[LOAD1]]
+ ; CHECK-NEXT: $d0 = COPY [[FADD]](f64)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
double %p3, double %p4, double %p5,
double %reasonable,
double %parameters,
double %q0, double %q1) {
-; CHECK-LABEL: name: test_double_vfpcc
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
-; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
-; CHECK: liveins: $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7
-; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d1
-; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
-; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load (s64)
-; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
-; CHECK: $d0 = COPY [[VREGV]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
entry:
%v = fadd double %p1, %q1
ret double %v
}
define arm_aapcscc double @test_double_aapcscc(double %p0, double %p1, double %p2,
+ ; LITTLE-LABEL: name: test_double_aapcscc
+ ; LITTLE: bb.1.entry:
+ ; LITTLE-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; LITTLE-NEXT: {{ $}}
+ ; LITTLE-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r0
+ ; LITTLE-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r1
+ ; LITTLE-NEXT: [[MV:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; LITTLE-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r2
+ ; LITTLE-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r3
+ ; LITTLE-NEXT: [[MV1:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
+ ; LITTLE-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; LITTLE-NEXT: [[LOAD:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (f64) from %fixed-stack.3)
+ ; LITTLE-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; LITTLE-NEXT: [[LOAD1:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (f64) from %fixed-stack.2)
+ ; LITTLE-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; LITTLE-NEXT: [[LOAD2:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (f64) from %fixed-stack.1)
+ ; LITTLE-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; LITTLE-NEXT: [[LOAD3:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (f64) from %fixed-stack.0)
+ ; LITTLE-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[MV1]], [[LOAD3]]
+ ; LITTLE-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FADD]](f64)
+ ; LITTLE-NEXT: $r0 = COPY [[UV]](s32)
+ ; LITTLE-NEXT: $r1 = COPY [[UV1]](s32)
+ ; LITTLE-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
+ ;
+ ; BIG-LABEL: name: test_double_aapcscc
+ ; BIG: bb.1.entry:
+ ; BIG-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; BIG-NEXT: {{ $}}
+ ; BIG-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r0
+ ; BIG-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r1
+ ; BIG-NEXT: [[MV:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY]](s32)
+ ; BIG-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r2
+ ; BIG-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $r3
+ ; BIG-NEXT: [[MV1:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY2]](s32)
+ ; BIG-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; BIG-NEXT: [[LOAD:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (f64) from %fixed-stack.3)
+ ; BIG-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; BIG-NEXT: [[LOAD1:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (f64) from %fixed-stack.2)
+ ; BIG-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; BIG-NEXT: [[LOAD2:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (f64) from %fixed-stack.1)
+ ; BIG-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; BIG-NEXT: [[LOAD3:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (f64) from %fixed-stack.0)
+ ; BIG-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[MV1]], [[LOAD3]]
+ ; BIG-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FADD]](f64)
+ ; BIG-NEXT: $r0 = COPY [[UV1]](s32)
+ ; BIG-NEXT: $r1 = COPY [[UV]](s32)
+ ; BIG-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
double %p3, double %p4, double %p5) {
-; CHECK-LABEL: name: test_double_aapcscc
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[P2:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
-; CHECK-DAG: id: [[P3:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
-; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 16{{.*}}size: 8
-; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 24{{.*}}size: 8
-; CHECK: liveins: $r0, $r1, $r2, $r3
-; CHECK-DAG: [[VREGP1LO:%[0-9]+]]:_(s32) = COPY $r2
-; CHECK-DAG: [[VREGP1HI:%[0-9]+]]:_(s32) = COPY $r3
-; LITTLE: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1LO]](s32), [[VREGP1HI]](s32)
-; BIG: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32)
-; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
-; CHECK: [[VREGP5:%[0-9]+]]:_(s64) = G_LOAD [[FIP5]](p0){{.*}}load (s64)
-; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGP5]]
-; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; CHECK-DAG: $r0 = COPY [[VREGVLO]]
-; CHECK-DAG: $r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry:
%v = fadd double %p1, %p5
ret double %v
}
define arm_aapcs_vfpcc double @test_double_gap_vfpcc(double %p0, float %filler,
+ ; CHECK-LABEL: name: test_double_gap_vfpcc
+ ; CHECK: bb.1.entry:
+ ; CHECK-NEXT: liveins: $d0, $d2, $d3, $d4, $d5, $d6, $d7, $s2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $s2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f64) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(f64) = COPY $d3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(f64) = COPY $d4
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(f64) = COPY $d5
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(f64) = COPY $d6
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(f64) = COPY $d7
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (f64) from %fixed-stack.1)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (f64) from %fixed-stack.0)
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[COPY2]], [[LOAD1]]
+ ; CHECK-NEXT: $d0 = COPY [[FADD]](f64)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
double %p1, double %p2,
double %p3, double %p4,
double %reasonable,
double %parameters,
double %q0, double %q1) {
-; CHECK-LABEL: name: test_double_gap_vfpcc
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
-; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
-; CHECK: liveins: $d0, $d2, $d3, $d4, $d5, $d6, $d7, $s2
-; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d2
-; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
-; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load (s64)
-; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
-; CHECK: $d0 = COPY [[VREGV]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
entry:
%v = fadd double %p1, %q1
ret double %v
}
define arm_aapcscc double @test_double_gap_aapcscc(float %filler, double %p0,
+ ; LITTLE-LABEL: name: test_double_gap_aapcscc
+ ; LITTLE: bb.1.entry:
+ ; LITTLE-NEXT: liveins: $r0, $r2, $r3
+ ; LITTLE-NEXT: {{ $}}
+ ; LITTLE-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; LITTLE-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[COPY]](i32)
+ ; LITTLE-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
+ ; LITTLE-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
+ ; LITTLE-NEXT: [[MV:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
+ ; LITTLE-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; LITTLE-NEXT: [[LOAD:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (f64) from %fixed-stack.0)
+ ; LITTLE-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[MV]], [[LOAD]]
+ ; LITTLE-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FADD]](f64)
+ ; LITTLE-NEXT: $r0 = COPY [[UV]](s32)
+ ; LITTLE-NEXT: $r1 = COPY [[UV1]](s32)
+ ; LITTLE-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
+ ;
+ ; BIG-LABEL: name: test_double_gap_aapcscc
+ ; BIG: bb.1.entry:
+ ; BIG-NEXT: liveins: $r0, $r2, $r3
+ ; BIG-NEXT: {{ $}}
+ ; BIG-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; BIG-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[COPY]](i32)
+ ; BIG-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r2
+ ; BIG-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $r3
+ ; BIG-NEXT: [[MV:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY1]](s32)
+ ; BIG-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; BIG-NEXT: [[LOAD:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (f64) from %fixed-stack.0)
+ ; BIG-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[MV]], [[LOAD]]
+ ; BIG-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FADD]](f64)
+ ; BIG-NEXT: $r0 = COPY [[UV1]](s32)
+ ; BIG-NEXT: $r1 = COPY [[UV]](s32)
+ ; BIG-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
double %p1) {
-; CHECK-LABEL: name: test_double_gap_aapcscc
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
-; CHECK: liveins: $r0, $r2, $r3
-; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r2
-; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r3
-; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
-; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
-; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
-; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load (s64)
-; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
-; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; CHECK-DAG: $r0 = COPY [[VREGVLO]]
-; CHECK-DAG: $r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry:
%v = fadd double %p0, %p1
ret double %v
}
define arm_aapcscc double @test_double_gap2_aapcscc(double %p0, float %filler,
+ ; LITTLE-LABEL: name: test_double_gap2_aapcscc
+ ; LITTLE: bb.1.entry:
+ ; LITTLE-NEXT: liveins: $r0, $r1, $r2
+ ; LITTLE-NEXT: {{ $}}
+ ; LITTLE-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r0
+ ; LITTLE-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r1
+ ; LITTLE-NEXT: [[MV:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; LITTLE-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $r2
+ ; LITTLE-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[COPY2]](i32)
+ ; LITTLE-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; LITTLE-NEXT: [[LOAD:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (f64) from %fixed-stack.0)
+ ; LITTLE-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[MV]], [[LOAD]]
+ ; LITTLE-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FADD]](f64)
+ ; LITTLE-NEXT: $r0 = COPY [[UV]](s32)
+ ; LITTLE-NEXT: $r1 = COPY [[UV1]](s32)
+ ; LITTLE-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
+ ;
+ ; BIG-LABEL: name: test_double_gap2_aapcscc
+ ; BIG: bb.1.entry:
+ ; BIG-NEXT: liveins: $r0, $r1, $r2
+ ; BIG-NEXT: {{ $}}
+ ; BIG-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $r0
+ ; BIG-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $r1
+ ; BIG-NEXT: [[MV:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY]](s32)
+ ; BIG-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $r2
+ ; BIG-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[COPY2]](i32)
+ ; BIG-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; BIG-NEXT: [[LOAD:%[0-9]+]]:_(f64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (f64) from %fixed-stack.0)
+ ; BIG-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[MV]], [[LOAD]]
+ ; BIG-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FADD]](f64)
+ ; BIG-NEXT: $r0 = COPY [[UV1]](s32)
+ ; BIG-NEXT: $r1 = COPY [[UV]](s32)
+ ; BIG-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
double %p1) {
-; CHECK-LABEL: name: test_double_gap2_aapcscc
-; CHECK: fixedStack:
-; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
-; CHECK: liveins: $r0, $r1, $r2
-; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r1
-; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
-; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
-; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
-; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load (s64)
-; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
-; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; CHECK-DAG: $r0 = COPY [[VREGVLO]]
-; CHECK-DAG: $r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry:
%v = fadd double %p0, %p1
ret double %v
}
define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
-; CHECK-LABEL: name: test_shufflevector_s32_v2s32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ARG]](s32), [[ARG]](s32)
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)
+ ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY]](i32)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x i32>), [[C]](i32)
+ ; CHECK-NEXT: $r0 = COPY [[EVEC]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
%shuffle = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
%res = extractelement <2 x i32> %shuffle, i32 0
@@ -450,9 +628,13 @@ define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
}
define i32 @test_shufflevector_s32_s32_s32(i32 %arg) {
-; CHECK-LABEL: name: test_shufflevector_s32_s32_s32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: r0 = COPY [[ARG]](s32)
+ ; CHECK-LABEL: name: test_shufflevector_s32_s32_s32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: $r0 = COPY [[COPY]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
%shuffle = shufflevector <1 x i32> %vec, <1 x i32> undef, <1 x i32> zeroinitializer
%res = extractelement <1 x i32> %shuffle, i32 0
@@ -460,16 +642,21 @@ define i32 @test_shufflevector_s32_s32_s32(i32 %arg) {
}
define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[V1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
-; CHECK-DAG: [[V2:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
-; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], shufflemask(1, 0, 1)
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
+ ; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](i32), [[C]](i32)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x i32>) = G_INSERT_VECTOR_ELT [[IVEC]], [[COPY1]](i32), [[C1]](i32)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<3 x i32>) = G_SHUFFLE_VECTOR [[IVEC1]](<2 x i32>), [[DEF]], shufflemask(1, 0, 1)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<3 x i32>), [[C]](i32)
+ ; CHECK-NEXT: $r0 = COPY [[EVEC]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0
%v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1
%shuffle = shufflevector <2 x i32> %v2, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
@@ -479,16 +666,21 @@ define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) {
define i32 @test_shufflevector_v2s32_v4s32(i32 %arg1, i32 %arg2) {
-; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[V1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
-; CHECK-DAG: [[V2:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
-; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], shufflemask(0, 0, 0, 0)
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<4 x s32>)
+ ; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x i32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](i32), [[C]](i32)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x i32>) = G_INSERT_VECTOR_ELT [[IVEC]], [[COPY1]](i32), [[C1]](i32)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x i32>) = G_SHUFFLE_VECTOR [[IVEC1]](<2 x i32>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x i32>), [[C]](i32)
+ ; CHECK-NEXT: $r0 = COPY [[EVEC]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0
%v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1
%shuffle = shufflevector <2 x i32> %v2, <2 x i32> undef, <4 x i32> zeroinitializer
@@ -497,22 +689,27 @@ define i32 @test_shufflevector_v2s32_v4s32(i32 %arg1, i32 %arg2) {
}
define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
-; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK: [[ARG3:%[0-9]+]]:_(s32) = COPY $r2
-; CHECK: [[ARG4:%[0-9]+]]:_(s32) = COPY $r3
-; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK-DAG: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-; CHECK-DAG: [[V1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
-; CHECK-DAG: [[V2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
-; CHECK-DAG: [[V3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V2]], [[ARG3]](s32), [[C2]](s32)
-; CHECK-DAG: [[V4:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V3]], [[ARG4]](s32), [[C3]](s32)
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[V4]](<4 x s32>), [[UNDEF]], shufflemask(1, 3)
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)
+ ; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $r1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $r2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $r3
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](i32), [[C]](i32)
+ ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC]], [[COPY1]](i32), [[C1]](i32)
+ ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[COPY2]](i32), [[C2]](i32)
+ ; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x i32>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[COPY3]](i32), [[C3]](i32)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x i32>) = G_SHUFFLE_VECTOR [[IVEC3]](<4 x i32>), [[DEF]], shufflemask(1, 3)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<2 x i32>), [[C]](i32)
+ ; CHECK-NEXT: $r0 = COPY [[EVEC]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%v1 = insertelement <4 x i32> undef, i32 %arg1, i32 0
%v2 = insertelement <4 x i32> %v1, i32 %arg2, i32 1
%v3 = insertelement <4 x i32> %v2, i32 %arg3, i32 2
@@ -525,12 +722,15 @@ define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32
%struct.v2s32 = type { <2 x i32> }
define i32 @test_constantstruct_v2s32() {
-; CHECK-LABEL: name: test_constantstruct_v2s32
-; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32)
-; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[C3]]
+ ; CHECK-LABEL: name: test_constantstruct_v2s32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C1]](i32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x i32>), [[C2]](i32)
+ ; CHECK-NEXT: $r0 = COPY [[EVEC]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%vec = extractvalue %struct.v2s32 {<2 x i32><i32 1, i32 2>}, 0
%elt = extractelement <2 x i32> %vec, i32 0
ret i32 %elt
@@ -539,14 +739,17 @@ define i32 @test_constantstruct_v2s32() {
%struct.v2s32.s32.s32 = type { <2 x i32>, i32, i32 }
define i32 @test_constantstruct_v2s32_s32_s32() {
-; CHECK-LABEL: name: test_constantstruct_v2s32_s32_s32
-; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32)
-; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[C5]](s32)
+ ; CHECK-LABEL: name: test_constantstruct_v2s32_s32_s32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C1]](i32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x i32>), [[C4]](i32)
+ ; CHECK-NEXT: $r0 = COPY [[EVEC]](i32)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%vec = extractvalue %struct.v2s32.s32.s32 {<2 x i32><i32 1, i32 2>, i32 3, i32 4}, 0
%elt = extractelement <2 x i32> %vec, i32 0
ret i32 %elt
@@ -555,15 +758,19 @@ define i32 @test_constantstruct_v2s32_s32_s32() {
define void @test_load_store_struct(ptr %addr) {
; Make sure the IRTranslator doesn't use an unnecessarily large GEP index type
; when breaking up loads and stores of aggregates.
-; CHECK-LABEL: name: test_load_store_struct
-; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0
-; CHECK-DAG: [[VAL1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load (s32) from %ir.addr)
-; CHECK-DAG: [[OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-; CHECK-DAG: [[ADDR2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR1]], [[OFFSET]](s32)
-; CHECK-DAG: [[VAL2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load (s32) from %ir.addr + 4)
-; CHECK-DAG: G_STORE [[VAL1]](s32), [[ADDR1]](p0) :: (store (s32) into %ir.addr)
-; CHECK-DAG: [[ADDR3:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
-; CHECK-DAG: G_STORE [[VAL2]](s32), [[ADDR3]](p0) :: (store (s32) into %ir.addr + 4)
+ ; CHECK-LABEL: name: test_load_store_struct
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $r0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (load (i32) from %ir.addr)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i32)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p0) :: (load (i32) from %ir.addr + 4)
+ ; CHECK-NEXT: G_STORE [[LOAD]](i32), [[COPY]](p0) :: (store (i32) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](i32), [[COPY1]](p0) :: (store (i32) into %ir.addr + 4)
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%val = load {i32, i32}, ptr %addr, align 4
store {i32, i32} %val, ptr %addr, align 4
ret void
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
index a35f82722adaf..8797c387e032d 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
@@ -96,25 +96,28 @@ body: |
bb.0:
liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
; CHECK-NOT: G_FREM
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[Y2]]
; HARD-DAG: $s0 = COPY [[X]]
; HARD-DAG: $s1 = COPY [[Y]]
; SOFT: BL{{.*}} &fmodf, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; HARD: BL{{.*}} &fmodf, {{.*}}, implicit $s0, implicit $s1, implicit-def $s0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = COPY $s0
+ ; SOFT: [[R2:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R2]]
+ ; HARD: [[R:%[0-9]+]]:_(f32) = COPY $s0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FREM
- %2(s32) = G_FREM %0, %1
+ %2(f32) = G_FREM %0, %1
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -145,34 +148,38 @@ body: |
; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
; through R2-R3, ends up in R2-R3 or R3-R2, when passed to fmod.
; For hard float, the values need to end up in D0 and D1.
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
- %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]]
+ %4(f64) = G_MERGE_VALUES %0(f32), %1(f32)
+ %5(f64) = G_MERGE_VALUES %2(f32), %3(f32)
; CHECK-NOT: G_FREM
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X2]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X3]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y2]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y3]]
; HARD-DAG: $d0 = COPY [[X]]
; HARD-DAG: $d1 = COPY [[Y]]
; SOFT: BL{{.*}} &fmod, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; HARD: BL{{.*}} &fmod, {{.*}}, implicit $d0, implicit $d1, implicit-def $d0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FREM
- %6(s64) = G_FREM %4, %5
- %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
- $r0 = COPY %7(s32)
- $r1 = COPY %8(s32)
+ %6(f64) = G_FREM %4, %5
+ %7(f32), %8(f32) = G_UNMERGE_VALUES %6(f64)
+ $r0 = COPY %7(f32)
+ $r1 = COPY %8(f32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
@@ -191,25 +198,28 @@ body: |
bb.0:
liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
; CHECK-NOT: G_FPOW
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]]
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]]
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; HARD-DAG: $s0 = COPY [[X]]
; HARD-DAG: $s1 = COPY [[Y]]
; SOFT: BL{{.*}} &powf, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; HARD: BL{{.*}} &powf, {{.*}}, implicit $s0, implicit $s1, implicit-def $s0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = COPY $s0
+ ; SOFT: [[R2:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R2]]
+ ; HARD: [[R:%[0-9]+]]:_(f32) = COPY $s0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FPOW
- %2(s32) = G_FPOW %0, %1
+ %2(f32) = G_FPOW %0, %1
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -240,34 +250,38 @@ body: |
; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
; through R2-R3, ends up in R2-R3 or R3-R2, when passed to pow.
; For hard float, the values need to end up in D0 and D1.
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
- %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]]
+ %4(f64) = G_MERGE_VALUES %0(f32), %1(f32)
+ %5(f64) = G_MERGE_VALUES %2(f32), %3(f32)
; CHECK-NOT: G_FPOW
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X2]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X3]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y2]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y3]]
; HARD-DAG: $d0 = COPY [[X]]
; HARD-DAG: $d1 = COPY [[Y]]
; SOFT: BL{{.*}} &pow, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; HARD: BL{{.*}} &pow, {{.*}}, implicit $d0, implicit $d1, implicit-def $d0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FPOW
- %6(s64) = G_FPOW %4, %5
- %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
- $r0 = COPY %7(s32)
- $r1 = COPY %8(s32)
+ %6(f64) = G_FPOW %4, %5
+ %7(f32), %8(f32) = G_UNMERGE_VALUES %6(f64)
+ $r0 = COPY %7(f32)
+ $r1 = COPY %8(f32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
@@ -286,23 +300,26 @@ body: |
bb.0:
liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FADD [[X]], [[Y]]
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; HARD: [[R:%[0-9]+]]:_(f32) = G_FADD [[X]], [[Y]]
; SOFT-NOT: G_FADD
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]]
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]]
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fadd, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__addsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R1:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R1]]
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FADD
- %2(s32) = G_FADD %0, %1
+ %2(f32) = G_FADD %0, %1
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -327,34 +344,38 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
- %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- ; HARD: [[R:%[0-9]+]]:_(s64) = G_FADD [[X]], [[Y]]
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]]
+ %4(f64) = G_MERGE_VALUES %0(f32), %1(f32)
+ %5(f64) = G_MERGE_VALUES %2(f32), %3(f32)
+ ; HARD: [[R:%[0-9]+]]:_(f64) = G_FADD [[X]], [[Y]]
; SOFT-NOT: G_FADD
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X2]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X3]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y2]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dadd, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__adddf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FADD
- %6(s64) = G_FADD %4, %5
- ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
- %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- $r0 = COPY %7(s32)
- $r1 = COPY %8(s32)
+ %6(f64) = G_FADD %4, %5
+ ; HARD-DAG: G_UNMERGE_VALUES [[R]](f64)
+ %7(f32),%8(f32) = G_UNMERGE_VALUES %6(f64)
+ $r0 = COPY %7(f32)
+ $r1 = COPY %8(f32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
@@ -373,23 +394,26 @@ body: |
bb.0:
liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FSUB [[X]], [[Y]]
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; HARD: [[R:%[0-9]+]]:_(f32) = G_FSUB [[X]], [[Y]]
; SOFT-NOT: G_FSUB
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]]
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]]
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fsub, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__subsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R1:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R1]]
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FSUB
- %2(s32) = G_FSUB %0, %1
+ %2(f32) = G_FSUB %0, %1
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -414,34 +438,38 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
- %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- ; HARD: [[R:%[0-9]+]]:_(s64) = G_FSUB [[X]], [[Y]]
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]]
+ %4(f64) = G_MERGE_VALUES %0(f32), %1(f32)
+ %5(f64) = G_MERGE_VALUES %2(f32), %3(f32)
+ ; HARD: [[R:%[0-9]+]]:_(f64) = G_FSUB [[X]], [[Y]]
; SOFT-NOT: G_FSUB
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X2]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X3]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y2]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dsub, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__subdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FSUB
- %6(s64) = G_FSUB %4, %5
- ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
- %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- $r0 = COPY %7(s32)
- $r1 = COPY %8(s32)
+ %6(f64) = G_FSUB %4, %5
+ ; HARD-DAG: G_UNMERGE_VALUES [[R]](f64)
+ %7(f32),%8(f32) = G_UNMERGE_VALUES %6(f64)
+ $r0 = COPY %7(f32)
+ $r1 = COPY %8(f32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
@@ -460,23 +488,26 @@ body: |
bb.0:
liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FMUL [[X]], [[Y]]
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; HARD: [[R:%[0-9]+]]:_(f32) = G_FMUL [[X]], [[Y]]
; SOFT-NOT: G_FMUL
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]]
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]]
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fmul, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__mulsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R1:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R1]]
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMUL
- %2(s32) = G_FMUL %0, %1
+ %2(f32) = G_FMUL %0, %1
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -501,34 +532,38 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
- %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- ; HARD: [[R:%[0-9]+]]:_(s64) = G_FMUL [[X]], [[Y]]
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]]
+ %4(f64) = G_MERGE_VALUES %0(f32), %1(f32)
+ %5(f64) = G_MERGE_VALUES %2(f32), %3(f32)
+ ; HARD: [[R:%[0-9]+]]:_(f64) = G_FMUL [[X]], [[Y]]
; SOFT-NOT: G_FMUL
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X2]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X3]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y2]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dmul, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__muldf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMUL
- %6(s64) = G_FMUL %4, %5
- ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
- %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- $r0 = COPY %7(s32)
- $r1 = COPY %8(s32)
+ %6(f64) = G_FMUL %4, %5
+ ; HARD-DAG: G_UNMERGE_VALUES [[R]](f64)
+ %7(f32),%8(f32) = G_UNMERGE_VALUES %6(f64)
+ $r0 = COPY %7(f32)
+ $r1 = COPY %8(f32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
@@ -547,23 +582,26 @@ body: |
bb.0:
liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FDIV [[X]], [[Y]]
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; HARD: [[R:%[0-9]+]]:_(f32) = G_FDIV [[X]], [[Y]]
; SOFT-NOT: G_FDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]]
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]]
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fdiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__divsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R1:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R1]]
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FDIV
- %2(s32) = G_FDIV %0, %1
+ %2(f32) = G_FDIV %0, %1
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -588,34 +626,38 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
- %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
- ; HARD: [[R:%[0-9]+]]:_(s64) = G_FDIV [[X]], [[Y]]
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]]
+ %4(f64) = G_MERGE_VALUES %0(f32), %1(f32)
+ %5(f64) = G_MERGE_VALUES %2(f32), %3(f32)
+ ; HARD: [[R:%[0-9]+]]:_(f64) = G_FDIV [[X]], [[Y]]
; SOFT-NOT: G_FDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X2]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X3]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y2]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_ddiv, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__divdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FDIV
- %6(s64) = G_FDIV %4, %5
- ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
- %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- $r0 = COPY %7(s32)
- $r1 = COPY %8(s32)
+ %6(f64) = G_FDIV %4, %5
+ ; HARD-DAG: G_UNMERGE_VALUES [[R]](f64)
+ %7(f32),%8(f32) = G_UNMERGE_VALUES %6(f64)
+ $r0 = COPY %7(f32)
+ $r1 = COPY %8(f32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
@@ -632,13 +674,13 @@ body: |
bb.0:
liveins:
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.25
+ ; HARD: [[R:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.25
; SOFT-NOT: G_FCONSTANT
- ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1080033280
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_CONSTANT i32 -1080033280
; SOFT-NOT: G_FCONSTANT
- %0(s32) = G_FCONSTANT float -1.25
+ %0(f32) = G_FCONSTANT float -1.25
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %0(s32)
+ $r0 = COPY %0(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -663,22 +705,22 @@ body: |
; SOFT_POOL: id: 1
; SOFT_POOL: value: i32 858993459
- ; HARD: [[R:%[0-9]+]]:_(s64) = G_FCONSTANT double -2.4
+ ; HARD: [[R:%[0-9]+]]:_(f64) = G_FCONSTANT double -2.4
; SOFT-NOT: G_FCONSTANT
- ; SOFT_CONST-DAG: [[HI:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1073532109
- ; SOFT_CONST-DAG: [[LO:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459
+ ; SOFT_CONST-DAG: [[HI:%[0-9]+]]:_(f32) = G_CONSTANT i32 -1073532109
+ ; SOFT_CONST-DAG: [[LO:%[0-9]+]]:_(f32) = G_CONSTANT i32 858993459
; SOFT_POOL-DAG: [[HIPTR:%[0-9]+]]:_(p0) = G_CONSTANT_POOL %const.0
- ; SOFT_POOL-DAG: [[HI:%[0-9]+]]:_(s32) = G_LOAD [[HIPTR]]
+ ; SOFT_POOL-DAG: [[HI:%[0-9]+]]:_(f32) = G_LOAD [[HIPTR]]
; SOFT_POOL-DAG: [[LOPTR:%[0-9]+]]:_(p0) = G_CONSTANT_POOL %const.1
- ; SOFT_POOL-DAG: [[LO:%[0-9]+]]:_(s32) = G_LOAD [[LOPTR]]
+ ; SOFT_POOL-DAG: [[LO:%[0-9]+]]:_(f32) = G_LOAD [[LOPTR]]
; SOFT-NOT: G_FCONSTANT
- %0(s64) = G_FCONSTANT double -2.4
- ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
+ %0(f64) = G_FCONSTANT double -2.4
+ ; HARD-DAG: G_UNMERGE_VALUES [[R]](f64)
; SOFT-DAG: $r0 = COPY [[HI]]
; SOFT-DAG: $r1 = COPY [[LO]]
- %1(s32),%2(s32) = G_UNMERGE_VALUES %0(s64)
- $r0 = COPY %2(s32)
- $r1 = COPY %1(s32)
+ %1(f32),%2(f32) = G_UNMERGE_VALUES %0(f64)
+ $r0 = COPY %2(f32)
+ $r1 = COPY %1(f32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
@@ -696,14 +738,16 @@ body: |
bb.0:
liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- %0(s32) = COPY $r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FNEG [[X]]
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; SOFT: [[R:%[0-9]+]]:_(s32) = G_XOR [[X]], [[ZERO]]
- %1(s32) = G_FNEG %0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ %0(f32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(f32) = G_FNEG [[X]]
+ ; SOFT: [[BC:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; SOFT: [[R2:%[0-9]+]]:_(i32) = G_XOR [[BC]], [[ZERO]]
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R2]](i32)
+ %1(f32) = G_FNEG %0
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -725,24 +769,26 @@ body: |
bb.0:
liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- ; HARD: [[R:%[0-9]+]]:_(s64) = G_FNEG [[X]]
- ; HARD: G_UNMERGE_VALUES [[R]](s64)
- ; SOFT: [[POSITIVE_ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT: [[NEGATIVE_ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; SOFT: [[LOWR:%[0-9]+]]:_(s32) = G_XOR [[X0]], [[POSITIVE_ZERO]]
- ; SOFT: [[HIGHR:%[0-9]+]]:_(s32) = G_XOR [[X1]], [[NEGATIVE_ZERO]]
- ; SOFT: $r0 = COPY [[LOWR]]
- ; SOFT: $r1 = COPY [[HIGHR]]
- %3(s64) = G_FNEG %2
- %4(s32),%5(s32) = G_UNMERGE_VALUES %3(s64)
- $r0 = COPY %4(s32)
- $r1 = COPY %5(s32)
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]]
+ %2(f64) = G_MERGE_VALUES %0(f32), %1(f32)
+ ; HARD: [[R:%[0-9]+]]:_(f64) = G_FNEG [[X]]
+ ; HARD: G_UNMERGE_VALUES [[R]](f64)
+ ; SOFT: [[POSITIVE_ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT: [[NEGATIVE_ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
+ ; SOFT: [[X2:%[0-9]+]]:_(i32), [[X3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES
+ ; SOFT: [[LOWR:%[0-9]+]]:_(i32) = G_XOR [[X2]], [[POSITIVE_ZERO]]
+ ; SOFT: [[HIGHR:%[0-9]+]]:_(i32) = G_XOR [[X3]], [[NEGATIVE_ZERO]]
+ ; SOFT: [[LOWR1:%[0-9]+]]:_(f32), [[HIGHR1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES
+ ; SOFT: $r0 = COPY [[LOWR1]]
+ ; SOFT: $r1 = COPY [[HIGHR1]]
+ %3(f64) = G_FNEG %2
+ %4(f32),%5(f32) = G_UNMERGE_VALUES %3(f64)
+ $r0 = COPY %4(f32)
+ $r1 = COPY %5(f32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
@@ -762,25 +808,28 @@ body: |
bb.0:
liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- %0(s32) = COPY $r0
- ; HARD: [[R:%[0-9]+]]:_(s64) = G_FPEXT [[X]]
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ %0(f32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(f64) = G_FPEXT [[X]]
; SOFT-NOT: G_FPEXT
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_f2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__extendsfdf2, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
- ; SOFT: [[R0:%[0-9]+]]:_(s32) = COPY $r0
- ; SOFT: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT: [[R1:%[0-9]+]]:_(i32) = COPY $r1
; SOFT: ADJCALLSTACKUP
+ ; SOFT: [[R2:%[0-9]+]]:_(f32) = G_BITCAST [[R0]]
+ ; SOFT: [[R3:%[0-9]+]]:_(f32) = G_BITCAST [[R1]]
; SOFT-NOT: G_FPEXT
- %1(s64) = G_FPEXT %0(s32)
- ; HARD: G_UNMERGE_VALUES [[R]](s64)
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[R0]]
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[R1]]
- %2(s32), %3(s32) = G_UNMERGE_VALUES %1(s64)
- $r0 = COPY %2(s32)
- $r1 = COPY %3(s32)
+ %1(f64) = G_FPEXT %0(f32)
+ ; HARD: G_UNMERGE_VALUES [[R]](f64)
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[R2]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[R3]]
+ %2(f32), %3(f32) = G_UNMERGE_VALUES %1(f64)
+ $r0 = COPY %2(f32)
+ $r1 = COPY %3(f32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
@@ -800,25 +849,28 @@ body: |
bb.0:
liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; HARD: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTRUNC [[X]]
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; HARD: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f64) = G_MERGE_VALUES %0(f32), %1(f32)
+ ; HARD: [[R:%[0-9]+]]:_(f32) = G_FPTRUNC [[X]]
; SOFT-NOT: G_FPTRUNC
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_d2f, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__truncdfsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R1:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R1]]
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTRUNC
- %3(s32) = G_FPTRUNC %2(s64)
+ %3(f32) = G_FPTRUNC %2(f64)
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %3(s32)
+ $r0 = COPY %3(f32)
BX_RET 14, $noreg, implicit $r0
---
---
@@ -836,20 +888,21 @@ body: |
bb.0:
liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- %0(s32) = COPY $r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOSI [[X]]
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ %0(f32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(i32) = G_FPTOSI [[X]]
; SOFT-NOT: G_FPTOSI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_f2iz, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__fixsfsi, {{.*}}, implicit $r0, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOSI
- %1(s32) = G_FPTOSI %0(s32)
+ %1(i32) = G_FPTOSI %0(f32)
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(i32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -869,25 +922,27 @@ body: |
bb.0:
liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; HARD: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOSI [[X]]
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; HARD: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]]
+ %2(f64) = G_MERGE_VALUES %0(f32), %1(f32)
+ ; HARD: [[R:%[0-9]+]]:_(i32) = G_FPTOSI [[X]]
; SOFT-NOT: G_FPTOSI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X2]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_d2iz, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__fixdfsi, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOSI
- %3(s32) = G_FPTOSI %2(s64)
- ; CHECK: $r0 = COPY [[R]](s32)
- $r0 = COPY %3(s32)
+ %3(i32) = G_FPTOSI %2(f64)
+ ; CHECK: $r0 = COPY [[R]](i32)
+ $r0 = COPY %3(i32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -905,20 +960,21 @@ body: |
bb.0:
liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- %0(s32) = COPY $r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOUI [[X]]
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ %0(f32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(i32) = G_FPTOUI [[X]]
; SOFT-NOT: G_FPTOUI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_f2uiz, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__fixunssfsi, {{.*}}, implicit $r0, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOUI
- %1(s32) = G_FPTOUI %0(s32)
+ %1(i32) = G_FPTOUI %0(f32)
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(i32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -938,25 +994,27 @@ body: |
bb.0:
liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; HARD: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOUI [[X]]
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; HARD: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]]
+ %2(f64) = G_MERGE_VALUES %0(f32), %1(f32)
+ ; HARD: [[R:%[0-9]+]]:_(i32) = G_FPTOUI [[X]]
; SOFT-NOT: G_FPTOUI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X2]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_d2uiz, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__fixunsdfsi, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOUI
- %3(s32) = G_FPTOUI %2(s64)
- ; CHECK: $r0 = COPY [[R]](s32)
- $r0 = COPY %3(s32)
+ %3(i32) = G_FPTOUI %2(f64)
+ ; CHECK: $r0 = COPY [[R]](i32)
+ $r0 = COPY %3(i32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -974,20 +1032,21 @@ body: |
bb.0:
liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- %0(s32) = COPY $r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_SITOFP [[X]]
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(i32) = COPY $r0
+ %0(i32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(f32) = G_SITOFP [[X]]
; SOFT-NOT: G_SITOFP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-AEABI: BL{{.*}} &__aeabi_i2f, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__floatsisf, {{.*}}, implicit $r0, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R1:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R1]]
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SITOFP
- %1(s32) = G_SITOFP %0(s32)
+ %1(f32) = G_SITOFP %0(i32)
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -1007,25 +1066,25 @@ body: |
bb.0:
liveins: $r0
- ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $r0
- %0(s32) = COPY $r0
- ; HARD: [[R:%[0-9]+]]:_(s64) = G_SITOFP [[X]]
+ ; CHECK: [[X:%[0-9]+]]:_(i32) = COPY $r0
+ %0(i32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(f64) = G_SITOFP [[X]]
; SOFT-NOT: G_SITOFP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-AEABI: BL{{.*}} &__aeabi_i2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__floatsidf, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
- ; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
- ; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DAG: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT-DAG: [[R1:%[0-9]+]]:_(i32) = COPY $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SITOFP
- %1(s64) = G_SITOFP %0(s32)
- ; HARD: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]]
- %2(s32), %3(s32) = G_UNMERGE_VALUES %1(s64)
- ; CHECK-DAG: $r0 = COPY [[R0]](s32)
- ; CHECK-DAG: $r1 = COPY [[R1]](s32)
- $r0 = COPY %2(s32)
- $r1 = COPY %3(s32)
+ %1(f64) = G_SITOFP %0(i32)
+ ; HARD: [[R0:%[0-9]+]]:_(i32), [[R1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[R]]
+ %2(i32), %3(i32) = G_UNMERGE_VALUES %1(f64)
+ ; CHECK-DAG: $r0 = COPY [[R0]]
+ ; CHECK-DAG: $r1 = COPY [[R1]]
+ $r0 = COPY %2(i32)
+ $r1 = COPY %3(i32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
@@ -1043,20 +1102,21 @@ body: |
bb.0:
liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- %0(s32) = COPY $r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_UITOFP [[X]]
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(i32) = COPY $r0
+ %0(i32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(f32) = G_UITOFP [[X]]
; SOFT-NOT: G_UITOFP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-AEABI: BL{{.*}} &__aeabi_ui2f, {{.*}}, implicit $r0, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__floatunsisf, {{.*}}, implicit $r0, implicit-def $r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R1:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R1]]
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UITOFP
- %1(s32) = G_UITOFP %0(s32)
+ %1(f32) = G_UITOFP %0(i32)
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -1076,25 +1136,25 @@ body: |
bb.0:
liveins: $r0
- ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $r0
- %0(s32) = COPY $r0
- ; HARD: [[R:%[0-9]+]]:_(s64) = G_UITOFP [[X]]
+ ; CHECK: [[X:%[0-9]+]]:_(i32) = COPY $r0
+ %0(i32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(f64) = G_UITOFP [[X]]
; SOFT-NOT: G_UITOFP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-AEABI: BL{{.*}} &__aeabi_ui2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
; SOFT-DEFAULT: BL{{.*}} &__floatunsidf, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
- ; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
- ; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DAG: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT-DAG: [[R1:%[0-9]+]]:_(i32) = COPY $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UITOFP
- %1(s64) = G_UITOFP %0(s32)
- ; HARD: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]]
- %2(s32), %3(s32) = G_UNMERGE_VALUES %1(s64)
- ; CHECK-DAG: $r0 = COPY [[R0]](s32)
- ; CHECK-DAG: $r1 = COPY [[R1]](s32)
- $r0 = COPY %2(s32)
- $r1 = COPY %3(s32)
+ %1(f64) = G_UITOFP %0(i32)
+ ; HARD: [[R0:%[0-9]+]]:_(i32), [[R1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[R]]
+ %2(i32), %3(i32) = G_UNMERGE_VALUES %1(f64)
+ ; CHECK-DAG: $r0 = COPY [[R0]]
+ ; CHECK-DAG: $r1 = COPY [[R1]]
+ $r0 = COPY %2(i32)
+ $r1 = COPY %3(i32)
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
...
@@ -1114,20 +1174,20 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(true), %0(s32), %1
- %3(s32) = G_ZEXT %2(s1)
- $r0 = COPY %3(s32)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(true), %0(f32), %1
+ %3(i32) = G_ZEXT %2(i1)
+ $r0 = COPY %3(i32)
BX_RET 14, $noreg, implicit $r0
- ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(true), [[X]](f32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; For soft float we just need to return a '-1' constant, but the truncation
; to 1 bit is converted by the combiner to the following masking sequence.
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[REXT:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; SOFT-NOT: G_FCMP
; CHECK: $r0 = COPY [[REXT]]
...
@@ -1148,20 +1208,20 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(false), %0(s32), %1
- %3(s32) = G_ZEXT %2(s1)
- $r0 = COPY %3(s32)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(false), %0(f32), %1
+ %3(i32) = G_ZEXT %2(i1)
+ $r0 = COPY %3(i32)
BX_RET 14, $noreg, implicit $r0
- ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(false), [[X]](f32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; For soft float we just need to return a '0' constant, but the truncation
; to 1 bit is converted by the combiner to the following masking sequence.
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SOFT: [[REXT:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; SOFT-NOT: G_FCMP
; CHECK: $r0 = COPY [[REXT]]
...
@@ -1182,31 +1242,33 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(oeq), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(oeq), [[X]](f32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__eqsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- $r0 = COPY %3(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %3(i32) = G_ZEXT %2(i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1227,31 +1289,33 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(ogt), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ogt), [[X]](f32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- $r0 = COPY %3(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sgt), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %3(i32) = G_ZEXT %2(i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1272,31 +1336,33 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(oge), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(oge), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[X]](f32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpge, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- $r0 = COPY %3(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sge), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %3(i32) = G_ZEXT %2(i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1317,31 +1383,33 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(olt), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(olt), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(olt), [[X]](f32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- $r0 = COPY %3(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %3(i32) = G_ZEXT %2(i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1362,31 +1430,33 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(ole), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(ole), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ole), [[X]](f32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmple, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__lesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- $r0 = COPY %3(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sle), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %3(i32) = G_ZEXT %2(i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1407,26 +1477,28 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(ord), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s32), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(ord), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[X]](f32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %3(s32)
+ %3(i32) = G_ZEXT %2(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1447,27 +1519,29 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s32), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(ugt), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ugt), [[X]](f32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmple, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__lesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sgt), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %3(s32)
+ %3(i32) = G_ZEXT %2(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1488,27 +1562,29 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(uge), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s32), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(uge), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(uge), [[X]](f32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sge), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %3(s32)
+ %3(i32) = G_ZEXT %2(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1529,27 +1605,29 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(ult), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s32), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(ult), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ult), [[X]](f32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpge, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %3(s32)
+ %3(i32) = G_ZEXT %2(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1570,27 +1648,29 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(ule), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s32), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(ule), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ule), [[X]](f32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sle), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %3(s32)
+ %3(i32) = G_ZEXT %2(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1611,27 +1691,29 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(une), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s32), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(une), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(une), [[X]](f32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__nesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %3(s32)
+ %3(i32) = G_ZEXT %2(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1652,31 +1734,33 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(uno), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(uno), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(uno), [[X]](f32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- $r0 = COPY %3(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %3(i32) = G_ZEXT %2(i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1697,43 +1781,47 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(one), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(one), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(one), [[X]](f32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(i1) = G_ICMP intpred(sgt), [[RET1]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
- ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_OR [[RET1]], [[RET2]]
- ; SOFT-DEFAULT:[[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[RET2]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(i32) = G_ANYEXT [[R1]]
+ ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(i32) = G_ANYEXT [[R2]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i32) = G_OR [[RET1]], [[RET2]]
+ ; SOFT-DEFAULT:[[R:%[0-9]+]]:_(i32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence.
- ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[R]], [[MASK]]
+ ; SOFT: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT: [[REXT:%[0-9]+]]:_(i32) = G_AND [[R]], [[MASK]]
; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- $r0 = COPY %3(s32)
+ %3(i32) = G_ZEXT %2(i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1754,43 +1842,47 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ %2(i1) = G_FCMP floatpred(ueq), %0(f32), %1
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ueq), [[X]](f32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X1:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y1:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X1]]
+ ; SOFT-DAG: $r1 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__eqsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET1]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X]]
- ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X]](f32)
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y]](f32)
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[Y2]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
- ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_OR [[RET1]], [[RET2]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[RET2]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(i32) = G_ANYEXT [[R1]]
+ ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(i32) = G_ANYEXT [[R2]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i32) = G_OR [[RET1]], [[RET2]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence.
- ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[R]], [[MASK]]
+ ; SOFT: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT: [[REXT:%[0-9]+]]:_(i32) = G_AND [[R]], [[MASK]]
; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- $r0 = COPY %3(s32)
+ %3(i32) = G_ZEXT %2(i1)
+ $r0 = COPY %3(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1815,28 +1907,28 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; HARD-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; HARD-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; HARD-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; HARD-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(true), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; HARD-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; HARD-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; HARD-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; HARD-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(true), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(true), [[X]](f64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; The result needs to be truncated, and the combiner turns the truncation
; into the following masking sequence.
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[REXT:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- $r0 = COPY %7(s32)
+ %7(i32) = G_ZEXT %6(i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1861,28 +1953,28 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; HARD-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; HARD-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; HARD-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; HARD-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(false), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; HARD-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; HARD-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; HARD-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; HARD-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(false), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(false), [[X]](f64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ ; SOFT: [[REXT:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; The result needs to be truncated, and the combiner turns the truncation
; into the following masking sequence.
; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- $r0 = COPY %7(s32)
+ %7(i32) = G_ZEXT %6(i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1907,41 +1999,45 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(oeq), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s64), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(oeq), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(oeq), [[X]](f64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__eqdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- $r0 = COPY %7(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %7(i32) = G_ZEXT %6(i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -1966,41 +2062,45 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(ogt), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s64), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(ogt), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ogt), [[X]](f64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- $r0 = COPY %7(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sgt), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %7(i32) = G_ZEXT %6(i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2025,41 +2125,45 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(oge), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s64), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(oge), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[X]](f64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpge, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- $r0 = COPY %7(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sge), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %7(i32) = G_ZEXT %6(i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2084,41 +2188,45 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(olt), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s64), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(olt), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(olt), [[X]](f64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- $r0 = COPY %7(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %7(i32) = G_ZEXT %6(i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2143,41 +2251,45 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(ole), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s64), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(ole), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ole), [[X]](f64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmple, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ledf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- $r0 = COPY %7(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sle), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %7(i32) = G_ZEXT %6(i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2202,36 +2314,40 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(ord), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(ord), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[X]](f64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %7(s32)
+ %7(i32) = G_ZEXT %6(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2256,37 +2372,41 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(ugt), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(ugt), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ugt), [[X]](f64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmple, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ledf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sgt), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %7(s32)
+ %7(i32) = G_ZEXT %6(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2311,37 +2431,41 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(uge), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(uge), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(uge), [[X]](f64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sge), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %7(s32)
+ %7(i32) = G_ZEXT %6(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2366,37 +2490,41 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(ult), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(ult), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ult), [[X]](f64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpge, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %7(s32)
+ %7(i32) = G_ZEXT %6(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2421,37 +2549,41 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(ule), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(ule), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ule), [[X]](f64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(sle), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %7(s32)
+ %7(i32) = G_ZEXT %6(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2476,37 +2608,41 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(une), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]]
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(une), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(une), [[X]](f64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__nedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
+ ; SOFT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[RET]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- $r0 = COPY %7(s32)
+ %7(i32) = G_ZEXT %6(i1)
+ ; CHECK: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2531,41 +2667,45 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(uno), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s64), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(uno), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(uno), [[X]](f64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
- ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- ; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- $r0 = COPY %7(s32)
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(i32) = G_AND [[RET]], [[MASK]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[RET]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
+ ; SOFT-NOT: G_FCMP
+ %7(i32) = G_ZEXT %6(i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2590,55 +2730,63 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(one), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s64), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(one), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(one), [[X]](f64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(i1) = G_ICMP intpred(sgt), [[RET1]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X4:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X5:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y4:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y5:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X4]]
+ ; SOFT-DAG: $r1 = COPY [[X5]]
+ ; SOFT-DAG: $r2 = COPY [[Y4]]
+ ; SOFT-DAG: $r3 = COPY [[Y5]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
- ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_OR [[RET1]], [[RET2]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(i1) = G_ICMP intpred(slt), [[RET2]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(i32) = G_ANYEXT [[R1]]
+ ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(i32) = G_ANYEXT [[R2]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(i32) = G_OR [[RET1]], [[RET2]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence.
- ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[R]], [[MASK]]
+ ; SOFT: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT: [[REXT:%[0-9]+]]:_(i32) = G_AND [[R]], [[MASK]]
; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- $r0 = COPY %7(s32)
+ %7(i32) = G_ZEXT %6(i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
@@ -2663,55 +2811,63 @@ body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- %3(s32) = COPY $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
- %4(s64) = G_MERGE_VALUES %0(s32), %1
- %5(s64) = G_MERGE_VALUES %2(s32), %3
- ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
- %6(s1) = G_FCMP floatpred(ueq), %4(s64), %5
- ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s64), [[Y]]
- ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ %3(f32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(f32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(f32) = COPY $r3
+ %4(f64) = G_MERGE_VALUES %0(f32), %1
+ %5(f64) = G_MERGE_VALUES %2(f32), %3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[X0]](f32), [[X1]](f32)
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[Y0]](f32), [[Y1]](f32)
+ %6(i1) = G_FCMP floatpred(ueq), %4(f64), %5
+ ; HARD: [[R:%[0-9]+]]:_(i1) = G_FCMP floatpred(ueq), [[X]](f64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(i32) = G_ZEXT [[R]](i1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X3:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y3:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X2]]
+ ; SOFT-DAG: $r1 = COPY [[X3]]
+ ; SOFT-DAG: $r2 = COPY [[Y2]]
+ ; SOFT-DAG: $r3 = COPY [[Y3]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__eqdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(i1) = G_ICMP intpred(eq), [[RET1]](i32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: $r0 = COPY [[X0]]
- ; SOFT-DAG: $r1 = COPY [[X1]]
- ; SOFT-DAG: $r2 = COPY [[Y0]]
- ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT: [[X4:%[0-9]+]]:_(i32) = G_BITCAST [[X0]]
+ ; SOFT: [[X5:%[0-9]+]]:_(i32) = G_BITCAST [[X1]]
+ ; SOFT: [[Y4:%[0-9]+]]:_(i32) = G_BITCAST [[Y0]]
+ ; SOFT: [[Y5:%[0-9]+]]:_(i32) = G_BITCAST [[Y1]]
+ ; SOFT-DAG: $r0 = COPY [[X4]]
+ ; SOFT-DAG: $r1 = COPY [[X5]]
+ ; SOFT-DAG: $r2 = COPY [[Y4]]
+ ; SOFT-DAG: $r3 = COPY [[Y5]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(i32) = COPY $r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
- ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
- ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT-AEABI:[[R:%[0-9]+]]:_(s32) = G_OR [[RET1]], [[RET2]]
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(i1) = G_ICMP intpred(ne), [[RET2]](i32), [[ZERO]]
+ ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(i32) = G_ANYEXT [[R1]]
+ ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(i32) = G_ANYEXT [[R2]]
+ ; SOFT-AEABI:[[R:%[0-9]+]]:_(i32) = G_OR [[RET1]], [[RET2]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(i32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence.
- ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[R]], [[MASK]]
+ ; SOFT: [[MASK:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; SOFT: [[REXT:%[0-9]+]]:_(i32) = G_AND [[R]], [[MASK]]
; SOFT-NOT: G_FCMP
- %7(s32) = G_ZEXT %6(s1)
- $r0 = COPY %7(s32)
+ %7(i32) = G_ZEXT %6(i1)
+ $r0 = COPY %7(i32)
; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
index 3c900c2a54f24..b526e0ae3498d 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
@@ -67,14 +67,14 @@ body: |
; CHECK: [[LD:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8))
; CHECK: [[ASSERTZ:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LD]], 1
- ; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASSERTZ]]
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[EXT]], [[ONE]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[AND]]
- ; CHECK: G_STORE [[TRUNC]](s8), {{%[0-9]+}}(p0) :: (store (s8))
+ ; CHECK: [[ONE:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK: [[EXT:%[0-9]+]]:_(i32) = G_ANYEXT [[ASSERTZ]]
+ ; CHECK: [[AND:%[0-9]+]]:_(i32) = G_AND [[EXT]], [[ONE]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(i8) = G_TRUNC [[AND]]
+ ; CHECK: G_STORE [[TRUNC]](i8), {{%[0-9]+}}(p0) :: (store (i8))
%0:_(p0) = COPY $r0
- %5:_(s1) = G_LOAD %0(p0) :: (load (s1))
- G_STORE %5(s1), %0(p0) :: (store (s1))
+ %5:_(i1) = G_LOAD %0(p0) :: (load (s1))
+ G_STORE %5(i1), %0(p0) :: (store (s1))
BX_RET 14, $noreg
...
---
@@ -126,22 +126,22 @@ body: |
; Can't use the VFP support for unaligned operations, we need to use 32-bits
; operations instead.
; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0
- ; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load (s32), align 1)
- ; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[V1:%[0-9]+]]:_(i32) = G_LOAD [[ADDR1]](p0) :: (load (i32), align 1)
+ ; CHECK-NEXT: [[OFF:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR1]], [[OFF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
- ; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from unknown-address + 4, align 1)
- ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store (s32), align 1)
- ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store (s32) into unknown-address + 4, align 1)
+ ; CHECK-NEXT: [[V2:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p0) :: (load (i32) from unknown-address + 4, align 1)
+ ; CHECK-NEXT: G_STORE [[V1]](i32), [[ADDR1]](p0) :: (store (i32), align 1)
+ ; CHECK-NEXT: G_STORE [[V2]](i32), [[ADDR2]](p0) :: (store (i32) into unknown-address + 4, align 1)
%0(p0) = COPY $r0
- %1(s64) = G_LOAD %0(p0) :: (load (s64), align 1)
- G_STORE %1(s64), %0(p0) :: (store (s64), align 1)
+ %1(i64) = G_LOAD %0(p0) :: (load (s64), align 1)
+ G_STORE %1(i64), %0(p0) :: (store (s64), align 1)
; For word-aligned we can use VFP operations.
- ; CHECK: [[V:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load (s64), align 4)
- ; CHECK: G_STORE [[V]](s64), %0(p0) :: (store (s64), align 4)
- %2(s64) = G_LOAD %0(p0) :: (load (s64), align 4)
- G_STORE %2(s64), %0(p0) :: (store (s64), align 4)
+ ; CHECK: [[V:%[0-9]+]]:_(i64) = G_LOAD %0(p0) :: (load (s64), align 4)
+ ; CHECK: G_STORE [[V]](i64), %0(p0) :: (store (s64), align 4)
+ %2(i64) = G_LOAD %0(p0) :: (load (s64), align 4)
+ G_STORE %2(i64), %0(p0) :: (store (s64), align 4)
BX_RET 14, $noreg
...
@@ -164,7 +164,7 @@ body: |
; When we don't have VFP support, we need to use 32-bit operations.
; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0
; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load (s32), align 1)
- ; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[OFF:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR1]], [[OFF]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from unknown-address + 4, align 1)
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
index f721e7f3da128..dbc4aaec9b542 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
@@ -23,30 +23,34 @@ body: |
bb.0:
liveins: $r0, $r1, $r2
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
- ; CHECK-DAG: [[Z:%[0-9]+]]:_(s32) = COPY $r2
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s32) = COPY $r2
- ; HARD: [[R:%[0-9]+]]:_(s32) = G_FMA [[X]], [[Y]], [[Z]]
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(f32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(f32) = COPY $r1
+ ; CHECK-DAG: [[Z:%[0-9]+]]:_(f32) = COPY $r2
+ %0(f32) = COPY $r0
+ %1(f32) = COPY $r1
+ %2(f32) = COPY $r2
+ ; HARD: [[R:%[0-9]+]]:_(f32) = G_FMA [[X]], [[Y]], [[Z]]
; SOFT-NOT: G_FMA
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-ABI-DAG: $r0 = COPY [[X]]
- ; SOFT-ABI-DAG: $r1 = COPY [[Y]]
- ; SOFT-ABI-DAG: $r2 = COPY [[Z]]
+ ; SOFT-ABI-DAG: [[X2:%[0-9]+]]:_(i32) = G_BITCAST [[X]]
+ ; SOFT-ABI-DAG: [[Y2:%[0-9]+]]:_(i32) = G_BITCAST [[Y]]
+ ; SOFT-ABI-DAG: [[Z2:%[0-9]+]]:_(i32) = G_BITCAST [[Z]]
+ ; SOFT-ABI-DAG: $r0 = COPY [[X2]]
+ ; SOFT-ABI-DAG: $r1 = COPY [[Y2]]
+ ; SOFT-ABI-DAG: $r2 = COPY [[Z2]]
; SOFT-ABI: BL &fmaf, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit-def $r0
- ; SOFT-ABI: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-ABI: [[R2:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT-ABI-DAG: [[R:%[0-9]+]]:_(f32) = G_BITCAST [[R2]]
; HARD-ABI-DAG: $s0 = COPY [[X]]
; HARD-ABI-DAG: $s1 = COPY [[Y]]
; HARD-ABI-DAG: $s2 = COPY [[Z]]
; HARD-ABI: BL &fmaf, {{.*}}, implicit $s0, implicit $s1, implicit $s2, implicit-def $s0
- ; HARD-ABI: [[R:%[0-9]+]]:_(s32) = COPY $s0
+ ; HARD-ABI: [[R:%[0-9]+]]:_(f32) = COPY $s0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMA
- %3(s32) = G_FMA %0, %1, %2
+ %3(f32) = G_FMA %0, %1, %2
; CHECK: $r0 = COPY [[R]]
- $r0 = COPY %3(s32)
+ $r0 = COPY %3(f32)
BX_RET 14, $noreg, implicit $r0
...
---
@@ -91,21 +95,21 @@ body: |
; SOFT-ABI: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; SOFT-ABI: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-ABI: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
- ; SOFT-ABI: G_STORE [[Y0]](s32), [[FI1]](p0){{.*}}store (s32) into stack, align 1)
+ ; SOFT-ABI: G_STORE [[Y0]](s32), [[FI1]](p0){{.*}}store (i32) into stack, align 1)
; SOFT-ABI: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; FIXME: Should avoid multiple copies from $sp
; FIXME: This ought to be align 8 but ARM's call lowering hardcodes it to 1
; SOFT-ABI: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; SOFT-ABI: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32)
- ; SOFT-ABI: G_STORE [[Y1]](s32), [[FI2]](p0){{.*}}store (s32) into stack + 4, align 1)
+ ; SOFT-ABI: G_STORE [[Y1]](s32), [[FI2]](p0){{.*}}store (i32) into stack + 4, align 1)
; SOFT-ABI-DAG: $r{{[0-1]}} = COPY [[X0]]
; SOFT-ABI-DAG: $r{{[0-1]}} = COPY [[X1]]
; SOFT-ABI-DAG: $r{{[2-3]}} = COPY [[X0]]
; SOFT-ABI-DAG: $r{{[2-3]}} = COPY [[X1]]
; SOFT-ABI: BL &fma, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
- ; SOFT-ABI-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
- ; SOFT-ABI-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-ABI-DAG: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+ ; SOFT-ABI-DAG: [[R1:%[0-9]+]]:_(i32) = COPY $r1
; HARD-ABI-DAG: $d0 = COPY [[X]]
; HARD-ABI-DAG: $d1 = COPY [[X]]
; HARD-ABI-DAG: $d2 = COPY [[Y]]
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
index 65586f72c7c19..9faef9de1b807 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
@@ -7,7 +7,7 @@ declare arm_aapcscc ptr @simple_reg_params_target(i32, ptr)
define arm_aapcscc ptr @test_call_simple_reg_params(ptr %a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_reg_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(i32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $r0 = COPY [[BVREG]]
; CHECK-DAG: $r1 = COPY [[AVREG]]
@@ -28,12 +28,12 @@ declare arm_aapcscc ptr @simple_stack_params_target(i32, ptr, i32, ptr, i32, ptr
define arm_aapcscc ptr @test_call_simple_stack_params(ptr %a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_stack_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(i32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
-; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store (s32)
+; CHECK: G_STORE [[BVREG]](i32), [[FI1]](p0){{.*}}store (i32)
; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32)
@@ -58,53 +58,53 @@ declare arm_aapcscc signext i16 @ext_target(i8 signext, i8 zeroext, i16 signext,
define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
; CHECK-LABEL: name: test_call_ext_params
-; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s8) = G_TRUNC [[R0VREG]]
-; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]]
-; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY $r2
-; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]]
+; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(i8) = G_TRUNC [[R0VREG]]
+; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(i32) = COPY $r1
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(i16) = G_TRUNC [[R1VREG]]
+; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(i32) = COPY $r2
+; CHECK-DAG: [[CVREG:%[0-9]+]]:_(i1) = G_TRUNC [[R2VREG]]
; CHECK: ADJCALLSTACKDOWN 20, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8)
-; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8)
-; CHECK: [[SEXTB:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]](s16)
-; CHECK: [[ZEXTB:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]](s16)
-; CHECK: [[SEXTA2:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]]
+; CHECK: [[SEXTA:%[0-9]+]]:_(i32) = G_SEXT [[AVREG]](i8)
+; CHECK: [[ZEXTA:%[0-9]+]]:_(i32) = G_ZEXT [[AVREG]](i8)
+; CHECK: [[SEXTB:%[0-9]+]]:_(i32) = G_SEXT [[BVREG]](i16)
+; CHECK: [[ZEXTB:%[0-9]+]]:_(i32) = G_ZEXT [[BVREG]](i16)
+; CHECK: [[SEXTA2:%[0-9]+]]:_(i32) = G_SEXT [[AVREG]]
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
-; CHECK: G_STORE [[SEXTA2]](s32), [[FI1]](p0){{.*}}store (s32)
-; CHECK: [[ZEXTA2:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]]
+; CHECK: G_STORE [[SEXTA2]](i32), [[FI1]](p0){{.*}}store (i32)
+; CHECK: [[ZEXTA2:%[0-9]+]]:_(i32) = G_ZEXT [[AVREG]]
; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32)
-; CHECK: G_STORE [[ZEXTA2]](s32), [[FI2]](p0){{.*}}store (s32)
-; CHECK: [[SEXTB2:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]]
+; CHECK: G_STORE [[ZEXTA2]](i32), [[FI2]](p0){{.*}}store (i32)
+; CHECK: [[SEXTB2:%[0-9]+]]:_(i32) = G_SEXT [[BVREG]]
; CHECK: [[SP3:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[FI3:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP3]], [[OFF3]](s32)
-; CHECK: G_STORE [[SEXTB2]](s32), [[FI3]](p0){{.*}}store (s32)
-; CHECK: [[ZEXTB2:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]]
+; CHECK: G_STORE [[SEXTB2]](i32), [[FI3]](p0){{.*}}store (i32)
+; CHECK: [[ZEXTB2:%[0-9]+]]:_(i32) = G_ZEXT [[BVREG]]
; CHECK: [[SP4:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[FI4:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP4]], [[OFF4]](s32)
-; CHECK: G_STORE [[ZEXTB2]](s32), [[FI4]](p0){{.*}}store (s32)
-; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]]
+; CHECK: G_STORE [[ZEXTB2]](i32), [[FI4]](p0){{.*}}store (i32)
+; CHECK: [[ZEXTC:%[0-9]+]]:_(i32) = G_ZEXT [[CVREG]]
; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[FI5:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP5]], [[OFF5]](s32)
-; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store (s32)
+; CHECK: G_STORE [[ZEXTC]](i32), [[FI5]](p0){{.*}}store (i32)
; CHECK: $r0 = COPY [[SEXTA]]
; CHECK: $r1 = COPY [[ZEXTA]]
; CHECK: $r2 = COPY [[SEXTB]]
; CHECK: $r3 = COPY [[ZEXTB]]
; ARM: BL @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; THUMB: tBL 14 /* CC::al */, $noreg, @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
-; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[R0VREG_ASSERT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[R0VREG]], 16
-; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG_ASSERT]]
+; CHECK: [[R0VREG:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK: [[R0VREG_ASSERT:%[0-9]+]]:_(i32) = G_ASSERT_SEXT [[R0VREG]], 16
+; CHECK: [[RVREG:%[0-9]+]]:_(i16) = G_TRUNC [[R0VREG_ASSERT]]
; CHECK: ADJCALLSTACKUP 20, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]]
+; CHECK: [[RExtVREG:%[0-9]+]]:_(i32) = G_SEXT [[RVREG]]
; CHECK: $r0 = COPY [[RExtVREG]]
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
@@ -117,14 +117,14 @@ declare arm_aapcs_vfpcc double @vfpcc_fp_target(float, double)
define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) {
; CHECK-LABEL: name: test_call_vfpcc_fp_params
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY $d0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $s2
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(f64) = COPY $d0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(f32) = COPY $s2
; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $s0 = COPY [[BVREG]]
; CHECK-DAG: $d1 = COPY [[AVREG]]
; ARM: BL @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0
; THUMB: tBL 14 /* CC::al */, $noreg, @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0
-; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY $d0
+; CHECK: [[RVREG:%[0-9]+]]:_(f64) = COPY $d0
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $d0 = COPY [[RVREG]]
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $d0
@@ -140,20 +140,21 @@ define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
; CHECK-LABEL: name: test_call_aapcs_fp_params
; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY $r1
-; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
-; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r2
+; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
+; BIG-DAG: [[AVREG:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(i32) = COPY $r2
+; CHECK: [[BVREG2:%[0-9]+]]:_(f32) = G_BITCAST [[BVREG]]
; CHECK: ADJCALLSTACKDOWN 16, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64)
+; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](f64)
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
-; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store (s32)
+; CHECK: G_STORE [[BVREG2]](f32), [[FI1]](p0){{.*}}store (f32)
; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32)
-; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store (s64)
-; CHECK-DAG: $r0 = COPY [[BVREG]]
+; CHECK: G_STORE [[AVREG]](f64), [[FI2]](p0){{.*}}store (f64)
+; CHECK-DAG: $r0 = COPY [[BVREG2]]
; LITTLE-DAG: $r2 = COPY [[A1]]
; LITTLE-DAG: $r3 = COPY [[A2]]
; BIG-DAG: $r2 = COPY [[A2]]
@@ -162,10 +163,10 @@ define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
; THUMB: tBL 14 /* CC::al */, $noreg, @aapcscc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r1
-; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
-; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
+; LITTLE: [[RVREG:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
+; BIG: [[RVREG:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
; CHECK: ADJCALLSTACKUP 16, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64)
+; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](f64)
; LITTLE-DAG: $r0 = COPY [[R1]]
; LITTLE-DAG: $r1 = COPY [[R2]]
; BIG-DAG: $r0 = COPY [[R2]]
@@ -181,14 +182,15 @@ declare arm_aapcscc float @different_call_conv_target(float)
define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
; CHECK-LABEL: name: test_call_different_call_conv
-; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[X:%[0-9]+]]:_(f32) = COPY $s0
; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[X]]
; ARM: BL @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0
; THUMB: tBL 14 /* CC::al */, $noreg, @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0
-; CHECK: [[R:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK: [[S:%[0-9]+]]:_(f32) = G_BITCAST [[R]]
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK: $s0 = COPY [[R]]
+; CHECK: $s0 = COPY [[S]]
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0
entry:
@@ -201,16 +203,16 @@ declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32])
define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
; CHECK-LABEL: name: test_tiny_int_arrays
; CHECK: liveins: $r0, $r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(i32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]]
; ARM: BL @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; THUMB: tBL 14 /* CC::al */, $noreg, @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(i32) = COPY $r1
+; CHECK: [[R2:%[0-9]+]]:_(i32) = COPY $r2
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say
; that composite types larger than 4 bytes should be passed through memory),
@@ -230,10 +232,10 @@ declare arm_aapcscc void @multiple_int_arrays_target([2 x i32], [2 x i32])
define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) {
; CHECK-LABEL: name: test_multiple_int_arrays
; CHECK: liveins: $r0, $r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
-; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $r3
+; CHECK: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(i32) = COPY $r1
+; CHECK: [[R2:%[0-9]+]]:_(i32) = COPY $r2
+; CHECK: [[R3:%[0-9]+]]:_(i32) = COPY $r3
; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]]
@@ -259,25 +261,25 @@ define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) {
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4
; CHECK: liveins: $r0, $r1, $r2, $r3
-; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2
-; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3
+; CHECK-DAG: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK-DAG: [[R1:%[0-9]+]]:_(i32) = COPY $r1
+; CHECK-DAG: [[R2:%[0-9]+]]:_(i32) = COPY $r2
+; CHECK-DAG: [[R3:%[0-9]+]]:_(i32) = COPY $r3
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
-; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load (s32) from %fixed-stack.[[FIRST_STACK_ID]]
+; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(i32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load (i32) from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
-; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load (s32) from %fixed-stack.[[LAST_STACK_ID]]
+; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(i32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load (i32) from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: ADJCALLSTACKDOWN 64, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_FIRST_ELEMENT]](s32)
-; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store (s32)
+; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](i32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store (i32)
; Match the second-to-last offset, so we can get the correct SP for the last element
; CHECK: G_CONSTANT i32 56
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 60
; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_LAST_ELEMENT]](s32)
-; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store (s32)
+; CHECK: G_STORE [[LAST_STACK_ELEMENT]](i32), [[LAST_STACK_ARG_ADDR]]{{.*}}store (i32)
; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]]
; CHECK: $r2 = COPY [[R2]]
@@ -301,21 +303,21 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY $r1
-; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
-; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
+; LITTLE: [[ARR0:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
+; BIG: [[ARR0:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY $r3
-; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
-; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
+; LITTLE: [[ARR1:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
+; BIG: [[ARR1:%[0-9]+]]:_(f64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
-; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load (s64) from %fixed-stack.[[ARR2_ID]]
+; CHECK: [[ARR2:%[0-9]+]]:_(f64) = G_LOAD [[ARR2_FI]]{{.*}}load (f64) from %fixed-stack.[[ARR2_ID]]
; CHECK: ADJCALLSTACKDOWN 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
-; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64)
+; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](f64)
+; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](f64)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[ARR2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[ARR2_OFFSET]](s32)
-; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store (s64)
+; CHECK: G_STORE [[ARR2]](f64), [[ARR2_ADDR]](p0){{.*}}store (f64)
; LITTLE: $r0 = COPY [[ARR0_0]](s32)
; LITTLE: $r1 = COPY [[ARR0_1]](s32)
; BIG: $r0 = COPY [[ARR0_1]](s32)
@@ -326,11 +328,13 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
; BIG: $r3 = COPY [[ARR1_0]](s32)
; ARM: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; THUMB: tBL 14 /* CC::al */, $noreg, @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK: [[R0b:%[0-9]+]]:_(f32) = G_BITCAST [[R0]]
+; CHECK: [[R1:%[0-9]+]]:_(i32) = COPY $r1
+; CHECK: [[R1b:%[0-9]+]]:_(f32) = G_BITCAST [[R1]]
; CHECK: ADJCALLSTACKUP 8, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK: $r0 = COPY [[R0]]
-; CHECK: $r1 = COPY [[R1]]
+; CHECK: $r0 = COPY [[R0b]]
+; CHECK: $r1 = COPY [[R1b]]
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
entry:
@@ -348,49 +352,49 @@ define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3
; CHECK-DAG: id: [[Z2_ID:[0-9]+]], type: default, offset: 16, size: 8,
; CHECK-DAG: id: [[Z3_ID:[0-9]+]], type: default, offset: 24, size: 8,
; CHECK: liveins: $d0, $d1, $d2, $s6, $s7, $s8
-; CHECK: [[X0:%[0-9]+]]:_(s64) = COPY $d0
-; CHECK: [[X1:%[0-9]+]]:_(s64) = COPY $d1
-; CHECK: [[X2:%[0-9]+]]:_(s64) = COPY $d2
-; CHECK: [[Y0:%[0-9]+]]:_(s32) = COPY $s6
-; CHECK: [[Y1:%[0-9]+]]:_(s32) = COPY $s7
-; CHECK: [[Y2:%[0-9]+]]:_(s32) = COPY $s8
+; CHECK: [[X0:%[0-9]+]]:_(f64) = COPY $d0
+; CHECK: [[X1:%[0-9]+]]:_(f64) = COPY $d1
+; CHECK: [[X2:%[0-9]+]]:_(f64) = COPY $d2
+; CHECK: [[Y0:%[0-9]+]]:_(f32) = COPY $s6
+; CHECK: [[Y1:%[0-9]+]]:_(f32) = COPY $s7
+; CHECK: [[Y2:%[0-9]+]]:_(f32) = COPY $s8
; CHECK: [[Z0_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]]
-; CHECK: [[Z0:%[0-9]+]]:_(s64) = G_LOAD [[Z0_FI]]{{.*}}load (s64)
+; CHECK: [[Z0:%[0-9]+]]:_(f64) = G_LOAD [[Z0_FI]]{{.*}}load (f64)
; CHECK: [[Z1_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]]
-; CHECK: [[Z1:%[0-9]+]]:_(s64) = G_LOAD [[Z1_FI]]{{.*}}load (s64)
+; CHECK: [[Z1:%[0-9]+]]:_(f64) = G_LOAD [[Z1_FI]]{{.*}}load (f64)
; CHECK: [[Z2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]]
-; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load (s64)
+; CHECK: [[Z2:%[0-9]+]]:_(f64) = G_LOAD [[Z2_FI]]{{.*}}load (f64)
; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]]
-; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load (s64)
+; CHECK: [[Z3:%[0-9]+]]:_(f64) = G_LOAD [[Z3_FI]]{{.*}}load (f64)
; CHECK: ADJCALLSTACKDOWN 32, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z0_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[Z0_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z0_OFFSET]](s32)
-; CHECK: G_STORE [[Z0]](s64), [[Z0_ADDR]](p0){{.*}}store (s64)
+; CHECK: G_STORE [[Z0]](f64), [[Z0_ADDR]](p0){{.*}}store (f64)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z1_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[Z1_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z1_OFFSET]](s32)
-; CHECK: G_STORE [[Z1]](s64), [[Z1_ADDR]](p0){{.*}}store (s64)
+; CHECK: G_STORE [[Z1]](f64), [[Z1_ADDR]](p0){{.*}}store (f64)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[Z2_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z2_OFFSET]](s32)
-; CHECK: G_STORE [[Z2]](s64), [[Z2_ADDR]](p0){{.*}}store (s64)
+; CHECK: G_STORE [[Z2]](f64), [[Z2_ADDR]](p0){{.*}}store (f64)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z3_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z3_OFFSET]](s32)
-; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store (s64)
-; CHECK: $d0 = COPY [[X0]](s64)
-; CHECK: $d1 = COPY [[X1]](s64)
-; CHECK: $d2 = COPY [[X2]](s64)
-; CHECK: $s6 = COPY [[Y0]](s32)
-; CHECK: $s7 = COPY [[Y1]](s32)
-; CHECK: $s8 = COPY [[Y2]](s32)
+; CHECK: G_STORE [[Z3]](f64), [[Z3_ADDR]](p0){{.*}}store (f64)
+; CHECK: $d0 = COPY [[X0]](f64)
+; CHECK: $d1 = COPY [[X1]](f64)
+; CHECK: $d2 = COPY [[X2]](f64)
+; CHECK: $s6 = COPY [[Y0]](f32)
+; CHECK: $s7 = COPY [[Y1]](f32)
+; CHECK: $s8 = COPY [[Y2]](f32)
; ARM: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3
; THUMB: tBL 14 /* CC::al */, $noreg, @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $s1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $s2
-; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $s3
+; CHECK: [[R0:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK: [[R1:%[0-9]+]]:_(f32) = COPY $s1
+; CHECK: [[R2:%[0-9]+]]:_(f32) = COPY $s2
+; CHECK: [[R3:%[0-9]+]]:_(f32) = COPY $s3
; CHECK: ADJCALLSTACKUP 32, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[R0]]
; CHECK: $s1 = COPY [[R1]]
@@ -413,25 +417,25 @@ define arm_aapcscc [2 x ptr] @test_tough_arrays([6 x [4 x i32]] %arr) {
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4
; CHECK: liveins: $r0, $r1, $r2, $r3
-; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2
-; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3
+; CHECK-DAG: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK-DAG: [[R1:%[0-9]+]]:_(i32) = COPY $r1
+; CHECK-DAG: [[R2:%[0-9]+]]:_(i32) = COPY $r2
+; CHECK-DAG: [[R3:%[0-9]+]]:_(i32) = COPY $r3
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
-; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load (s32) from %fixed-stack.[[FIRST_STACK_ID]]
+; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(i32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load (i32) from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
-; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load (s32) from %fixed-stack.[[LAST_STACK_ID]]
+; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(i32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load (i32) from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: ADJCALLSTACKDOWN 80, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_FIRST_ELEMENT]](s32)
-; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store (s32)
+; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](i32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store (i32)
; Match the second-to-last offset, so we can get the correct SP for the last element
; CHECK: G_CONSTANT i32 72
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 76
; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_LAST_ELEMENT]](s32)
-; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store (s32)
+; CHECK: G_STORE [[LAST_STACK_ELEMENT]](i32), [[LAST_STACK_ARG_ADDR]]{{.*}}store (i32)
; CHECK: $r0 = COPY [[R0]]
; CHECK: $r1 = COPY [[R1]]
; CHECK: $r2 = COPY [[R2]]
@@ -455,18 +459,18 @@ declare arm_aapcscc {i32, i32} @structs_target({i32, i32})
define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
; CHECK-LABEL: test_structs
; CHECK: liveins: $r0, $r1
-; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK-DAG: [[X0:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK-DAG: [[X1:%[0-9]+]]:_(i32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK-DAG: $r0 = COPY [[X0]](s32)
-; CHECK-DAG: $r1 = COPY [[X1]](s32)
+; CHECK-DAG: $r0 = COPY [[X0]](i32)
+; CHECK-DAG: $r1 = COPY [[X1]](i32)
; ARM: BL @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
; THUMB: tBL 14 /* CC::al */, $noreg, @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: [[R0:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(i32) = COPY $r1
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK: $r0 = COPY [[R0]](s32)
-; CHECK: $r1 = COPY [[R1]](s32)
+; CHECK: $r0 = COPY [[R0]](i32)
+; CHECK: $r1 = COPY [[R1]](i32)
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
%r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x)
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
index 4cded131190f4..7ae3cda70998b 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
@@ -23,8 +23,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]
; CHECK: $r0 = COPY [[COPY1]]
; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
- %0:fprb(s32) = COPY $s0
- %1:gprb(s32) = G_FPTOSI %0(s32)
- $r0 = COPY %1(s32)
+ %0:fprb(f32) = COPY $s0
+ %1:gprb(i32) = G_FPTOSI %0(f32)
+ $r0 = COPY %1(i32)
MOVPCLR 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
index 0e989858d9c28..6cf631ac168a7 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll
@@ -49,7 +49,7 @@ define i17 @test_funny_ints(i17 %a, i17 %b) {
}
define half @test_half(half %a, half %b) {
-; CHECK: remark: {{.*}} unable to legalize instruction: %{{[0-9]+}}:_(s16) = G_FADD %{{[0-9]+}}:_, %{{[0-9]+}}:_ (in function: test_half)
+; CHECK: remark: {{.*}} unable to legalize instruction: %{{[0-9]+}}:_(f16) = G_FADD %{{[0-9]+}}:_, %{{[0-9]+}}:_ (in function: test_half)
; CHECK-LABEL: warning: Instruction selection used fallback path for test_half
%res = fadd half %a, %b
ret half %res
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
index daae1b7a094e7..2cbb64ef83737 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
@@ -6,12 +6,12 @@ declare arm_aapcscc i32 @int_varargs_target(i32, ...)
define arm_aapcscc i32 @test_call_to_varargs_with_ints(ptr %a, i32 %b) {
; CHECK-LABEL: name: test_call_to_varargs_with_ints
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(i32) = COPY $r1
; CHECK: ADJCALLSTACKDOWN 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
-; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store (s32)
+; CHECK: G_STORE [[BVREG]](i32), [[FI1]](p0){{.*}}store (i32)
; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32)
@@ -22,7 +22,7 @@ define arm_aapcscc i32 @test_call_to_varargs_with_ints(ptr %a, i32 %b) {
; CHECK-DAG: $r3 = COPY [[AVREG]]
; ARM: BL @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; THUMB: tBL 14 /* CC::al */, $noreg, @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
-; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[RVREG:%[0-9]+]]:_(i32) = COPY $r0
; CHECK: ADJCALLSTACKUP 8, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK: $r0 = COPY [[RVREG]]
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $r0
@@ -36,22 +36,23 @@ declare arm_aapcs_vfpcc float @float_varargs_target(float, double, ...)
define arm_aapcs_vfpcc float @test_call_to_varargs_with_floats(float %a, double %b) {
; CHECK-LABEL: name: test_call_to_varargs_with_floats
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(f64) = COPY $d1
; CHECK: ADJCALLSTACKDOWN 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64)
+; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](f64)
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
-; CHECK: G_STORE [[BVREG]](s64), [[FI1]](p0){{.*}}store (s64)
+; CHECK: G_STORE [[BVREG]](f64), [[FI1]](p0){{.*}}store (f64)
; CHECK-DAG: $r0 = COPY [[AVREG]]
; CHECK-DAG: $r2 = COPY [[B1]]
; CHECK-DAG: $r3 = COPY [[B2]]
; ARM: BL @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
; THUMB: tBL 14 /* CC::al */, $noreg, @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
-; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[RVREG:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK: [[RVREG2:%[0-9]+]]:_(f32) = G_BITCAST [[RVREG]]
; CHECK: ADJCALLSTACKUP 8, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK: $s0 = COPY [[RVREG]]
+; CHECK: $s0 = COPY [[RVREG2]]
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0
entry:
@@ -61,18 +62,19 @@ entry:
define arm_aapcs_vfpcc float @test_call_to_varargs_with_floats_fixed_args_only(float %a, double %b) {
; CHECK-LABEL: name: test_call_to_varargs_with_floats_fixed_args_only
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(f64) = COPY $d1
; CHECK: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
; CHECK-DAG: $r0 = COPY [[AVREG]]
-; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64)
+; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](f64)
; CHECK-DAG: $r2 = COPY [[B1]]
; CHECK-DAG: $r3 = COPY [[B2]]
; ARM: BL @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
; THUMB: tBL 14 /* CC::al */, $noreg, @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
-; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[RVREG:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK: [[RVREG2:%[0-9]+]]:_(f32) = G_BITCAST [[RVREG]]
; CHECK: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK: $s0 = COPY [[RVREG]]
+; CHECK: $s0 = COPY [[RVREG2]]
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0
entry:
@@ -83,22 +85,23 @@ entry:
define arm_aapcs_vfpcc float @test_indirect_call_to_varargs(ptr %fptr, float %a, double %b) {
; CHECK-LABEL: name: test_indirect_call_to_varargs
; CHECK-DAG: [[FPTRVREG:%[0-9]+]]:gpr(p0) = COPY $r0
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(f32) = COPY $s0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(f64) = COPY $d1
; CHECK: ADJCALLSTACKDOWN 8, 0, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64)
+; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](f64)
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32)
-; CHECK: G_STORE [[BVREG]](s64), [[FI1]](p0){{.*}}store (s64)
+; CHECK: G_STORE [[BVREG]](f64), [[FI1]](p0){{.*}}store (f64)
; CHECK-DAG: $r0 = COPY [[AVREG]]
; CHECK-DAG: $r2 = COPY [[B1]]
; CHECK-DAG: $r3 = COPY [[B2]]
; ARM: BLX [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
; THUMB: tBLXr 14 /* CC::al */, $noreg, [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
-; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[RVREG:%[0-9]+]]:_(i32) = COPY $r0
+; CHECK: [[RVREG2:%[0-9]+]]:_(f32) = G_BITCAST [[RVREG]]
; CHECK: ADJCALLSTACKUP 8, -1, 14 /* CC::al */, $noreg, implicit-def $sp, implicit $sp
-; CHECK: $s0 = COPY [[RVREG]]
+; CHECK: $s0 = COPY [[RVREG2]]
; ARM: BX_RET 14 /* CC::al */, $noreg, implicit $s0
; THUMB: tBX_RET 14 /* CC::al */, $noreg, implicit $s0
entry:
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir
index 5fa59ca787e72..c79cfca429537 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir
@@ -17,15 +17,15 @@ body: |
bb.0:
liveins: $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
- %1(s32) = G_CTLZ %0(s32)
+ %1(i32) = G_CTLZ %0(i32)
; ARM: [[VREGR:%[0-9]+]]:gpr = CLZ [[VREGX]], 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2CLZ [[VREGX]], 14 /* CC::al */, $noreg
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(i32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-dbg.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-dbg.mir
index 71dc0279595d9..37c15fee0d75f 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/select-dbg.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/select-dbg.mir
@@ -28,18 +28,18 @@ body: |
bb.0:
liveins: $r0, $s1
- %0(s32) = COPY $r0
- %1(s32) = COPY $s1
+ %0(i32) = COPY $r0
+ %1(f32) = COPY $s1
- %2(s32) = G_ADD %0, %0
+ %2(i32) = G_ADD %0, %0
; DBG_VALUE {{%[0-9]+}}:gpr, $noreg, !7, !DIExpression(), debug-location !9
- DBG_VALUE %2(s32), $noreg, !7, !DIExpression(), debug-location !9
+ DBG_VALUE %2(i32), $noreg, !7, !DIExpression(), debug-location !9
- %3(s32) = G_FADD %1, %1
+ %3(f32) = G_FADD %1, %1
; DBG_VALUE {{%[0-9]+}}:spr, $noreg, !7, !DIExpression(), debug-location !9
- DBG_VALUE %3(s32), $noreg, !7, !DIExpression(), debug-location !9
+ DBG_VALUE %3(f32), $noreg, !7, !DIExpression(), debug-location !9
; DBG_VALUE i32 42, 0, !7, !DIExpression(), debug-location !9
DBG_VALUE i32 42, 0, !7, !DIExpression(), debug-location !9
@@ -50,8 +50,8 @@ body: |
; DBG_VALUE $noreg, 0, !7, !DIExpression(), debug-location !9
DBG_VALUE $noreg, 0, !7, !DIExpression(), debug-location !9
- $r0 = COPY %2(s32)
- $s1 = COPY %3(s32)
+ $r0 = COPY %2(i32)
+ $s1 = COPY %3(f32)
BX_RET 14, $noreg, implicit $r0, implicit $s1
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
index 4517fe6dd4f13..0c5ac5ec7482a 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
@@ -66,10 +66,10 @@ body: |
%2(p0) = COPY $r0
; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = G_TRUNC %0(s64)
+ %1(i32) = G_TRUNC %0(s64)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
- G_STORE %1(s32), %2 :: (store (s32))
+ G_STORE %1(i32), %2 :: (store (s32))
; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14 /* CC::al */, $noreg
BX_RET 14, $noreg
@@ -96,13 +96,13 @@ body: |
; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VADDS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
+ %0(f32) = COPY $s0
- %1(s32) = COPY $s1
+ %1(f32) = COPY $s1
- %2(s32) = G_FADD %0, %1
+ %2(f32) = G_FADD %0, %1
- $s0 = COPY %2(s32)
+ $s0 = COPY %2(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -127,13 +127,13 @@ body: |
; CHECK-NEXT: [[VADDD:%[0-9]+]]:dpr = nofpexcept VADDD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VADDD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
+ %0(f64) = COPY $d0
- %1(s64) = COPY $d1
+ %1(f64) = COPY $d1
- %2(s64) = G_FADD %0, %1
+ %2(f64) = G_FADD %0, %1
- $d0 = COPY %2(s64)
+ $d0 = COPY %2(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -158,13 +158,13 @@ body: |
; CHECK-NEXT: [[VSUBS:%[0-9]+]]:spr = nofpexcept VSUBS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VSUBS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
+ %0(f32) = COPY $s0
- %1(s32) = COPY $s1
+ %1(f32) = COPY $s1
- %2(s32) = G_FSUB %0, %1
+ %2(f32) = G_FSUB %0, %1
- $s0 = COPY %2(s32)
+ $s0 = COPY %2(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -189,13 +189,13 @@ body: |
; CHECK-NEXT: [[VSUBD:%[0-9]+]]:dpr = nofpexcept VSUBD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VSUBD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
+ %0(f64) = COPY $d0
- %1(s64) = COPY $d1
+ %1(f64) = COPY $d1
- %2(s64) = G_FSUB %0, %1
+ %2(f64) = G_FSUB %0, %1
- $d0 = COPY %2(s64)
+ $d0 = COPY %2(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -220,13 +220,13 @@ body: |
; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nofpexcept VMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VMULS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
+ %0(f32) = COPY $s0
- %1(s32) = COPY $s1
+ %1(f32) = COPY $s1
- %2(s32) = G_FMUL %0, %1
+ %2(f32) = G_FMUL %0, %1
- $s0 = COPY %2(s32)
+ $s0 = COPY %2(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -251,13 +251,13 @@ body: |
; CHECK-NEXT: [[VMULD:%[0-9]+]]:dpr = nofpexcept VMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VMULD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
+ %0(f64) = COPY $d0
- %1(s64) = COPY $d1
+ %1(f64) = COPY $d1
- %2(s64) = G_FMUL %0, %1
+ %2(f64) = G_FMUL %0, %1
- $d0 = COPY %2(s64)
+ $d0 = COPY %2(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -282,13 +282,13 @@ body: |
; CHECK-NEXT: [[VDIVS:%[0-9]+]]:spr = nofpexcept VDIVS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VDIVS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
+ %0(f32) = COPY $s0
- %1(s32) = COPY $s1
+ %1(f32) = COPY $s1
- %2(s32) = G_FDIV %0, %1
+ %2(f32) = G_FDIV %0, %1
- $s0 = COPY %2(s32)
+ $s0 = COPY %2(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -313,13 +313,13 @@ body: |
; CHECK-NEXT: [[VDIVD:%[0-9]+]]:dpr = nofpexcept VDIVD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VDIVD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
+ %0(f64) = COPY $d0
- %1(s64) = COPY $d1
+ %1(f64) = COPY $d1
- %2(s64) = G_FDIV %0, %1
+ %2(f64) = G_FDIV %0, %1
- $d0 = COPY %2(s64)
+ $d0 = COPY %2(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -342,11 +342,11 @@ body: |
; CHECK-NEXT: [[VNEGS:%[0-9]+]]:spr = VNEGS [[COPY]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $s0 = COPY [[VNEGS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
+ %0(f32) = COPY $s0
- %1(s32) = G_FNEG %0
+ %1(f32) = G_FNEG %0
- $s0 = COPY %1(s32)
+ $s0 = COPY %1(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -370,11 +370,11 @@ body: |
; CHECK-NEXT: [[VNEGD:%[0-9]+]]:dpr = VNEGD [[COPY]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $d0 = COPY [[VNEGD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
+ %0(f64) = COPY $d0
- %1(s64) = G_FNEG %0
+ %1(f64) = G_FNEG %0
- $d0 = COPY %1(s64)
+ $d0 = COPY %1(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -401,15 +401,15 @@ body: |
; CHECK-NEXT: [[VFMAS:%[0-9]+]]:spr = nofpexcept VFMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VFMAS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $s0
+ %0(f32) = COPY $s0
- %1(s32) = COPY $s1
+ %1(f32) = COPY $s1
- %2(s32) = COPY $s2
+ %2(f32) = COPY $s2
- %3(s32) = G_FMA %0, %1, %2
+ %3(f32) = G_FMA %0, %1, %2
- $s0 = COPY %3(s32)
+ $s0 = COPY %3(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -436,15 +436,15 @@ body: |
; CHECK-NEXT: [[VFMAD:%[0-9]+]]:dpr = nofpexcept VFMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VFMAD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
+ %0(f64) = COPY $d0
- %1(s64) = COPY $d1
+ %1(f64) = COPY $d1
- %2(s64) = COPY $d2
+ %2(f64) = COPY $d2
- %3(s64) = G_FMA %0, %1, %2
+ %3(f64) = G_FMA %0, %1, %2
- $d0 = COPY %3(s64)
+ $d0 = COPY %3(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -467,11 +467,11 @@ body: |
; CHECK-NEXT: [[VCVTDS:%[0-9]+]]:dpr = nofpexcept VCVTDS [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VCVTDS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s32) = COPY $s0
+ %0(f32) = COPY $s0
- %1(s64) = G_FPEXT %0(s32)
+ %1(f64) = G_FPEXT %0(f32)
- $d0 = COPY %1(s64)
+ $d0 = COPY %1(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -494,11 +494,11 @@ body: |
; CHECK-NEXT: [[VCVTSD:%[0-9]+]]:spr = nofpexcept VCVTSD [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VCVTSD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s64) = COPY $d0
+ %0(f64) = COPY $d0
- %1(s32) = G_FPTRUNC %0(s64)
+ %1(f32) = G_FPTRUNC %0(f64)
- $s0 = COPY %1(s32)
+ $s0 = COPY %1(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -522,11 +522,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]
; CHECK-NEXT: $r0 = COPY [[COPY1]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $s0
+ %0(f32) = COPY $s0
- %1(s32) = G_FPTOSI %0(s32)
+ %1(i32) = G_FPTOSI %0(f32)
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -550,11 +550,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZD]]
; CHECK-NEXT: $r0 = COPY [[COPY1]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s64) = COPY $d0
+ %0(f64) = COPY $d0
- %1(s32) = G_FPTOSI %0(s64)
+ %1(i32) = G_FPTOSI %0(f64)
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -578,11 +578,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOUIZS]]
; CHECK-NEXT: $r0 = COPY [[COPY1]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $s0
+ %0(f32) = COPY $s0
- %1(s32) = G_FPTOUI %0(s32)
+ %1(i32) = G_FPTOUI %0(f32)
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -606,11 +606,11 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOUIZD]]
; CHECK-NEXT: $r0 = COPY [[COPY1]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s64) = COPY $d0
+ %0(f64) = COPY $d0
- %1(s32) = G_FPTOUI %0(s64)
+ %1(i32) = G_FPTOUI %0(f64)
- $r0 = COPY %1(s32)
+ $r0 = COPY %1(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -634,11 +634,11 @@ body: |
; CHECK-NEXT: [[VSITOS:%[0-9]+]]:spr = nofpexcept VSITOS [[COPY1]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $s0 = COPY [[VSITOS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_SITOFP %0(s32)
+ %1(f32) = G_SITOFP %0(i32)
- $s0 = COPY %1(s32)
+ $s0 = COPY %1(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -662,11 +662,11 @@ body: |
; CHECK-NEXT: [[VSITOD:%[0-9]+]]:dpr = nofpexcept VSITOD [[COPY1]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $d0 = COPY [[VSITOD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s64) = G_SITOFP %0(s32)
+ %1(f64) = G_SITOFP %0(i32)
- $d0 = COPY %1(s64)
+ $d0 = COPY %1(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -690,11 +690,11 @@ body: |
; CHECK-NEXT: [[VUITOS:%[0-9]+]]:spr = nofpexcept VUITOS [[COPY1]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $s0 = COPY [[VUITOS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_UITOFP %0(s32)
+ %1(f32) = G_UITOFP %0(i32)
- $s0 = COPY %1(s32)
+ $s0 = COPY %1(f32)
BX_RET 14, $noreg, implicit $s0
...
@@ -718,11 +718,11 @@ body: |
; CHECK-NEXT: [[VUITOD:%[0-9]+]]:dpr = nofpexcept VUITOD [[COPY1]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $d0 = COPY [[VUITOD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s64) = G_UITOFP %0(s32)
+ %1(f64) = G_UITOFP %0(i32)
- $d0 = COPY %1(s64)
+ $d0 = COPY %1(f64)
BX_RET 14, $noreg, implicit $d0
...
@@ -747,7 +747,7 @@ body: |
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(p0) = COPY $r0
- %1(s32) = G_LOAD %0(p0) :: (load (s32))
+ %1(i32) = G_LOAD %0(p0) :: (load (s32))
$s0 = COPY %1
@@ -803,10 +803,10 @@ body: |
; CHECK-NEXT: VSTRD [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s64))
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
- %1(s32) = COPY $s0
+ %1(i32) = COPY $s0
%2(s64) = COPY $d2
- G_STORE %1(s32), %0(p0) :: (store (s32))
+ G_STORE %1(i32), %0(p0) :: (store (s32))
G_STORE %2(s64), %0(p0) :: (store (s64))
@@ -832,8 +832,8 @@ body: |
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $d0, $d1
- %0(s32) = COPY $r0
- %1(s1) = G_TRUNC %0(s32)
+ %0(i32) = COPY $r0
+ %1(s1) = G_TRUNC %0(i32)
%2(s64) = COPY $d0
%3(s64) = COPY $d1
@@ -887,7 +887,7 @@ body: |
%1(s32) = COPY $r3
- %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %2(f64) = G_MERGE_VALUES %0(s32), %1(s32)
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-neon.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-neon.mir
index 954f22791c5ac..2a8f1ade61611 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/select-neon.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/select-neon.mir
@@ -24,13 +24,13 @@ body: |
; CHECK: [[VADDv1i64_:%[0-9]+]]:dpr = VADDv1i64 [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $d0 = COPY [[VADDv1i64_]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
+ %0(i64) = COPY $d0
- %1(s64) = COPY $d1
+ %1(i64) = COPY $d1
- %2(s64) = G_ADD %0, %1
+ %2(i64) = G_ADD %0, %1
- $d0 = COPY %2(s64)
+ $d0 = COPY %2(i64)
BX_RET 14, $noreg, implicit $d0
...
@@ -53,13 +53,13 @@ body: |
; CHECK: [[VSUBv1i64_:%[0-9]+]]:dpr = VSUBv1i64 [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $d0 = COPY [[VSUBv1i64_]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
- %0(s64) = COPY $d0
+ %0(i64) = COPY $d0
- %1(s64) = COPY $d1
+ %1(i64) = COPY $d1
- %2(s64) = G_SUB %0, %1
+ %2(i64) = G_SUB %0, %1
- $d0 = COPY %2(s64)
+ $d0 = COPY %2(i64)
BX_RET 14, $noreg, implicit $d0
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir
index 173494620e914..bdf7a2c6aebd4 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir
@@ -30,26 +30,26 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
- %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
- %3(s32) = G_AND %0, %2
+ %2(i32) = G_CONSTANT i32 65535 ; 0xFFFF
+ %3(i32) = G_AND %0, %2
- %4(s32) = G_CONSTANT i32 7
- %5(s32) = G_SHL %1, %4
- %6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
- %7(s32) = G_AND %5, %6
+ %4(i32) = G_CONSTANT i32 7
+ %5(i32) = G_SHL %1, %4
+ %6(i32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %7(i32) = G_AND %5, %6
- %8(s32) = G_OR %3, %7
+ %8(i32) = G_OR %3, %7
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
- $r0 = COPY %8(s32)
+ $r0 = COPY %8(i32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
@@ -76,26 +76,26 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
- %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
- %3(s32) = G_AND %0, %2
+ %2(i32) = G_CONSTANT i32 65535 ; 0xFFFF
+ %3(i32) = G_AND %0, %2
- %4(s32) = G_CONSTANT i32 7
- %5(s32) = G_SHL %1, %4
- %6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
- %7(s32) = G_AND %5, %6
+ %4(i32) = G_CONSTANT i32 7
+ %5(i32) = G_SHL %1, %4
+ %6(i32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %7(i32) = G_AND %5, %6
- %8(s32) = G_OR %7, %3
+ %8(i32) = G_OR %7, %3
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
- $r0 = COPY %8(s32)
+ $r0 = COPY %8(i32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
@@ -120,24 +120,24 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
- %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
- %3(s32) = G_AND %0, %2
+ %2(i32) = G_CONSTANT i32 65535 ; 0xFFFF
+ %3(i32) = G_AND %0, %2
- %4(s32) = G_CONSTANT i32 17
- %5(s32) = G_SHL %1, %4
+ %4(i32) = G_CONSTANT i32 17
+ %5(i32) = G_SHL %1, %4
- %6(s32) = G_OR %3, %5
+ %6(i32) = G_OR %3, %5
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 17, 14 /* CC::al */, $noreg
- $r0 = COPY %6(s32)
+ $r0 = COPY %6(i32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
@@ -162,24 +162,24 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
- %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
- %3(s32) = G_AND %0, %2
+ %2(i32) = G_CONSTANT i32 65535 ; 0xFFFF
+ %3(i32) = G_AND %0, %2
- %4(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
- %5(s32) = G_AND %1, %4
+ %4(i32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %5(i32) = G_AND %1, %4
- %6(s32) = G_OR %3, %5
+ %6(i32) = G_OR %3, %5
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 0, 14 /* CC::al */, $noreg
- $r0 = COPY %6(s32)
+ $r0 = COPY %6(i32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
@@ -204,24 +204,24 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
- %2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
- %3(s32) = G_AND %0, %2
+ %2(i32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %3(i32) = G_AND %0, %2
- %4(s32) = G_CONSTANT i32 16
- %5(s32) = G_LSHR %1, %4
+ %4(i32) = G_CONSTANT i32 16
+ %5(i32) = G_LSHR %1, %4
- %6(s32) = G_OR %3, %5
+ %6(i32) = G_OR %3, %5
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 16, 14 /* CC::al */, $noreg
- $r0 = COPY %6(s32)
+ $r0 = COPY %6(i32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
@@ -248,26 +248,26 @@ body: |
bb.0:
liveins: $r0, $r1
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
; ARM-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
; ARM-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
; THUMB-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
; THUMB-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
- %2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
- %3(s32) = G_AND %0, %2
+ %2(i32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
+ %3(i32) = G_AND %0, %2
- %4(s32) = G_CONSTANT i32 7
- %5(s32) = G_LSHR %1, %4
- %6(s32) = G_CONSTANT i32 65535 ; 0xFFFF
- %7(s32) = G_AND %5, %6
+ %4(i32) = G_CONSTANT i32 7
+ %5(i32) = G_LSHR %1, %4
+ %6(i32) = G_CONSTANT i32 65535 ; 0xFFFF
+ %7(i32) = G_AND %5, %6
- %8(s32) = G_OR %3, %7
+ %8(i32) = G_OR %3, %7
; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 7, 14 /* CC::al */, $noreg
- $r0 = COPY %8(s32)
+ $r0 = COPY %8(i32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
index fa982d8a60d75..c9e126b33340c 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
@@ -34,13 +34,13 @@ body: |
; CHECK: [[VFNMSD:%[0-9]+]]:dpr = nofpexcept VFNMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr
; CHECK: $d0 = COPY [[VFNMSD]]
; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $d0
- %0:fprb(s64) = COPY $d0
- %1:fprb(s64) = COPY $d1
- %2:fprb(s64) = COPY $d2
- %3:fprb(s64) = G_FNEG %1
- %4:fprb(s64) = G_FMA %0, %3, %2
- %5:fprb(s64) = G_FNEG %4
- $d0 = COPY %5(s64)
+ %0:fprb(f64) = COPY $d0
+ %1:fprb(f64) = COPY $d1
+ %2:fprb(f64) = COPY $d2
+ %3:fprb(f64) = G_FNEG %1
+ %4:fprb(f64) = G_FMA %0, %3, %2
+ %5:fprb(f64) = G_FNEG %4
+ $d0 = COPY %5(f64)
MOVPCLR 14, $noreg, implicit $d0
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir
index 51dfeccf57311..77fbdcc2a91a7 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir
@@ -27,27 +27,27 @@ body: |
bb.0:
liveins: $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
- %1(s32) = G_CONSTANT i32 24
- %2(s32) = G_SHL %0(s32), %1(s32)
+ %1(i32) = G_CONSTANT i32 24
+ %2(i32) = G_SHL %0(i32), %1(i32)
- %3(s32) = G_CONSTANT i32 16
- %4(s32) = G_ASHR %2(s32), %3(s32)
+ %3(i32) = G_CONSTANT i32 16
+ %4(i32) = G_ASHR %2(i32), %3(i32)
- %5(s32) = G_CONSTANT i32 8
- %6(s32) = G_LSHR %0(s32), %5(s32)
+ %5(i32) = G_CONSTANT i32 8
+ %6(i32) = G_LSHR %0(i32), %5(i32)
- %7(s32) = G_CONSTANT i32 255
- %8(s32) = G_AND %6(s32), %7(s32)
+ %7(i32) = G_CONSTANT i32 255
+ %8(i32) = G_AND %6(i32), %7(i32)
- %9(s32) = G_OR %4(s32), %8(s32)
+ %9(i32) = G_OR %4(i32), %8(i32)
; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]
- $r0 = COPY %9(s32)
+ $r0 = COPY %9(i32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
@@ -75,27 +75,27 @@ body: |
bb.0:
liveins: $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
- %1(s32) = G_CONSTANT i32 24
- %2(s32) = G_SHL %0(s32), %1(s32)
+ %1(i32) = G_CONSTANT i32 24
+ %2(i32) = G_SHL %0(i32), %1(i32)
- %3(s32) = G_CONSTANT i32 16
- %4(s32) = G_ASHR %2(s32), %3(s32)
+ %3(i32) = G_CONSTANT i32 16
+ %4(i32) = G_ASHR %2(i32), %3(i32)
- %5(s32) = G_CONSTANT i32 8
- %6(s32) = G_LSHR %0(s32), %5(s32)
+ %5(i32) = G_CONSTANT i32 8
+ %6(i32) = G_LSHR %0(i32), %5(i32)
- %7(s32) = G_CONSTANT i32 255
- %8(s32) = G_AND %6(s32), %7(s32)
+ %7(i32) = G_CONSTANT i32 255
+ %8(i32) = G_AND %6(i32), %7(i32)
- %9(s32) = G_OR %8(s32), %4(s32)
+ %9(i32) = G_OR %8(i32), %4(i32)
; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]
- $r0 = COPY %9(s32)
+ $r0 = COPY %9(i32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
@@ -123,25 +123,25 @@ body: |
bb.0:
liveins: $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 16 ; REVSH needs 24 here
- %2(s32) = G_SHL %0(s32), %1(s32)
+ %1(i32) = G_CONSTANT i32 16 ; REVSH needs 24 here
+ %2(i32) = G_SHL %0(i32), %1(i32)
- %3(s32) = G_CONSTANT i32 24 ; REVSH needs 16 here
- %4(s32) = G_ASHR %2(s32), %3(s32)
+ %3(i32) = G_CONSTANT i32 24 ; REVSH needs 16 here
+ %4(i32) = G_ASHR %2(i32), %3(i32)
- %5(s32) = G_CONSTANT i32 8
- %6(s32) = G_LSHR %0(s32), %5(s32)
+ %5(i32) = G_CONSTANT i32 8
+ %6(i32) = G_LSHR %0(i32), %5(i32)
- %7(s32) = G_CONSTANT i32 255
- %8(s32) = G_AND %6(s32), %7(s32)
+ %7(i32) = G_CONSTANT i32 255
+ %8(i32) = G_AND %6(i32), %7(i32)
- %9(s32) = G_OR %4(s32), %8(s32)
+ %9(i32) = G_OR %4(i32), %8(i32)
; We don't really care how this is folded as long as it's not into a REVSH.
; CHECK-NOT: REVSH
- $r0 = COPY %9(s32)
+ $r0 = COPY %9(i32)
BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
index 73251d4695d29..9dddaf01e691f 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
@@ -34,13 +34,13 @@ body: |
; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ADDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_ADD %0, %1
+ %2(i32) = G_ADD %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -62,12 +62,12 @@ body: |
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ADDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
- %2(s32) = G_ADD %0, %1
+ %1(i32) = G_CONSTANT i32 786444 ; 0x000c000c
+ %2(i32) = G_ADD %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -89,12 +89,12 @@ body: |
; CHECK: [[t2ADDri12_:%[0-9]+]]:rgpr = t2ADDri12 [[COPY]], 4093, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2ADDri12_]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 4093
- %2(s32) = G_ADD %0, %1
+ %1(i32) = G_CONSTANT i32 4093
+ %2(i32) = G_ADD %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -117,13 +117,13 @@ body: |
; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[t2MOVi32imm]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ADDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f
+ %1(i32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f
- %2(s32) = G_ADD %0, %1
+ %2(i32) = G_ADD %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -145,12 +145,12 @@ body: |
; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2RSBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
- %2(s32) = G_SUB %1, %0
+ %1(i32) = G_CONSTANT i32 786444 ; 0x000c000c
+ %2(i32) = G_SUB %1, %0
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -172,12 +172,12 @@ body: |
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2SUBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
- %2(s32) = G_SUB %0, %1
+ %1(i32) = G_CONSTANT i32 786444 ; 0x000c000c
+ %2(i32) = G_SUB %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -200,13 +200,13 @@ body: |
; CHECK: [[t2MUL:%[0-9]+]]:rgpr = t2MUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2MUL]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_MUL %0, %1
+ %2(i32) = G_MUL %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -232,16 +232,16 @@ body: |
; CHECK: [[t2MLA:%[0-9]+]]:rgpr = t2MLA [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2MLA]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = COPY $r2
+ %2(i32) = COPY $r2
- %3(s32) = G_MUL %0, %1
- %4(s32) = G_ADD %3, %2
+ %3(i32) = G_MUL %0, %1
+ %4(i32) = G_ADD %3, %2
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -264,13 +264,13 @@ body: |
; CHECK: [[t2SDIV:%[0-9]+]]:rgpr = t2SDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2SDIV]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_SDIV %0, %1
+ %2(i32) = G_SDIV %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -293,13 +293,13 @@ body: |
; CHECK: [[t2UDIV:%[0-9]+]]:rgpr = t2UDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2UDIV]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_UDIV %0, %1
+ %2(i32) = G_UDIV %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir
index bd2aa3f5fb152..3a37d1b8d11ad 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir
@@ -30,13 +30,13 @@ body: |
; CHECK: [[t2ANDrr:%[0-9]+]]:rgpr = t2ANDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = COPY $r1
+ %1(i32) = COPY $r1
- %2(s32) = G_AND %0, %1
+ %2(i32) = G_AND %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -58,12 +58,12 @@ body: |
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
- %2(s32) = G_AND %0, %1
+ %1(i32) = G_CONSTANT i32 786444 ; 0x000c000c
+ %2(i32) = G_AND %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -85,12 +85,12 @@ body: |
; CHECK: [[t2BFC:%[0-9]+]]:rgpr = t2BFC [[COPY]], -65529, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2BFC]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007
- %2(s32) = G_AND %0, %1
+ %1(i32) = G_CONSTANT i32 -65529 ; 0xFFFF0007
+ %2(i32) = G_AND %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -112,12 +112,12 @@ body: |
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
- %2(s32) = G_AND %0, %1
+ %1(i32) = G_CONSTANT i32 786444 ; 0x000c000c
+ %2(i32) = G_AND %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -139,12 +139,12 @@ body: |
; CHECK: [[t2MVNr:%[0-9]+]]:rgpr = t2MVNr [[COPY]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2MVNr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
+ %0(i32) = COPY $r0
- %1(s32) = G_CONSTANT i32 -1
- %2(s32) = G_XOR %0, %1
+ %1(i32) = G_CONSTANT i32 -1
+ %2(i32) = G_XOR %0, %1
- $r0 = COPY %2(s32)
+ $r0 = COPY %2(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -169,15 +169,15 @@ body: |
; CHECK: [[t2BICrr:%[0-9]+]]:rgpr = t2BICrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2BICrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
- %2(s32) = G_CONSTANT i32 -1
- %3(s32) = G_XOR %1, %2
+ %2(i32) = G_CONSTANT i32 -1
+ %3(i32) = G_XOR %1, %2
- %4(s32) = G_AND %0, %3
+ %4(i32) = G_AND %0, %3
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
@@ -202,15 +202,15 @@ body: |
; CHECK: [[t2ORNrr:%[0-9]+]]:rgpr = t2ORNrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ORNrr]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
+ %0(i32) = COPY $r0
+ %1(i32) = COPY $r1
- %2(s32) = G_CONSTANT i32 -1
- %3(s32) = G_XOR %1, %2
+ %2(i32) = G_CONSTANT i32 -1
+ %3(i32) = G_XOR %1, %2
- %4(s32) = G_OR %0, %3
+ %4(i32) = G_OR %0, %3
- $r0 = COPY %4(s32)
+ $r0 = COPY %4(i32)
BX_RET 14, $noreg, implicit $r0
...
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