[llvm] [AArch64][llvm] Add GICv5 ICH_PPI_HVIR{0,1}_EL2 system registers (PR #191818)

[Jonathan Thackray via llvm-commits]

https://github.com/jthackray created https://github.com/llvm/llvm-project/pull/191818

Add GICv5 `ICH_PPI_HVIR{0,1}_EL2` system registers (Interrupt
Controller PPI Hide Virtual Interrupt Registers). These registers
are added because a hypervisor may want to only expose a subset of the
PPIs to the virtual machine and hide the remaining PPIs.

The only way the hypervisor can do this is by trapping all the PPI ICV
registers which leads to additional code complexity and adds performance
overhead especially for nested virtualization.

These are documented here:
  https://developer.arm.com/documentation/111107/latest/AArch64-Registers/ICH-PPI-HVIR-n--EL2--Interrupt-Controller-PPI-Hide-Virtual-Interrupt-Registers

>From 9b645ae7c3ce795f7a1ca78a49765a85271a9f61 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Thu, 5 Mar 2026 22:26:57 +0000
Subject: [PATCH] [AArch64][llvm] Add GICv5 ICH_PPI_HVIR{0,1}_EL2 system
 registers

Add GICv5 `ICH_PPI_HVIR{0,1}_EL2` system registers (Interrupt
Controller PPI Hide Virtual Interrupt Registers). These registers
are added because a hypervisor may want to only expose a subset of the
PPIs to the virtual machine and hide the remaining PPIs.

The only way the hypervisor can do this is by trapping all the PPI ICV
registers which leads to additional code complexity and adds performance
overhead especially for nested virtualization.

These are documented here:
  https://developer.arm.com/documentation/111107/latest/AArch64-Registers/ICH-PPI-HVIR-n--EL2--Interrupt-Controller-PPI-Hide-Virtual-Interrupt-Registers
---
 .../Target/AArch64/AArch64SystemOperands.td   |  1 +
 llvm/test/MC/AArch64/armv9.7a-gcie.s          | 20 +++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index e5a8844f078f4..fb1f58d854135 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -2636,6 +2636,7 @@ foreach n=0-1 in {
 def : RWSysReg<"ICH_PPI_ACTIVER"#n#"_EL2",   0b11, 0b100, 0b1100, 0b1010, {0b11,nb}>;
 def : RWSysReg<"ICH_PPI_DVIR"#n#"_EL2",      0b11, 0b100, 0b1100, 0b1010, {0b00,nb}>;
 def : RWSysReg<"ICH_PPI_ENABLER"#n#"_EL2",   0b11, 0b100, 0b1100, 0b1010, {0b01,nb}>;
+def : RWSysReg<"ICH_PPI_HVIR"#n#"_EL2",      0b11, 0b100, 0b1100, 0b0111, {0b00,nb}>;
 def : RWSysReg<"ICH_PPI_PENDR"#n#"_EL2",     0b11, 0b100, 0b1100, 0b1010, {0b10,nb}>;
 }
 
diff --git a/llvm/test/MC/AArch64/armv9.7a-gcie.s b/llvm/test/MC/AArch64/armv9.7a-gcie.s
index 74e95015f6c86..053f7495080ba 100644
--- a/llvm/test/MC/AArch64/armv9.7a-gcie.s
+++ b/llvm/test/MC/AArch64/armv9.7a-gcie.s
@@ -554,6 +554,16 @@ MRS x3, ICH_PPI_ENABLER1_EL2
 // CHECK-ENCODING: [0x63,0xca,0x3c,0xd5]
 // CHECK-UNKNOWN: d53cca63
 
+MRS x3, ICH_PPI_HVIR0_EL2
+// CHECK-INST:    mrs x3, ICH_PPI_HVIR0_EL2
+// CHECK-ENCODING: [0x03,0xc7,0x3c,0xd5]
+// CHECK-UNKNOWN: d53cc703
+
+MRS x3, ICH_PPI_HVIR1_EL2
+// CHECK-INST:    mrs x3, ICH_PPI_HVIR1_EL2
+// CHECK-ENCODING: [0x23,0xc7,0x3c,0xd5]
+// CHECK-UNKNOWN: d53cc723
+
 MRS x3, ICH_PPI_PENDR0_EL2
 // CHECK-INST:    mrs x3, ICH_PPI_PENDR0_EL2
 // CHECK-ENCODING: [0x83,0xca,0x3c,0xd5]
@@ -706,6 +716,16 @@ MSR ICH_PPI_ENABLER1_EL2, x3
 // CHECK-ENCODING: [0x63,0xca,0x1c,0xd5]
 // CHECK-UNKNOWN: d51cca63
 
+MSR ICH_PPI_HVIR0_EL2, x3
+// CHECK-INST:    msr ICH_PPI_HVIR0_EL2, x3
+// CHECK-ENCODING: [0x03,0xc7,0x1c,0xd5]
+// CHECK-UNKNOWN: d51cc703
+
+MSR ICH_PPI_HVIR1_EL2, x3
+// CHECK-INST:    msr ICH_PPI_HVIR1_EL2, x3
+// CHECK-ENCODING: [0x23,0xc7,0x1c,0xd5]
+// CHECK-UNKNOWN: d51cc723
+
 MSR ICH_PPI_PENDR0_EL2, x3
 // CHECK-INST:    msr ICH_PPI_PENDR0_EL2, x3
 // CHECK-ENCODING: [0x83,0xca,0x1c,0xd5]