[llvm] [MachineLICM] Only mark live-ins as non-invariant if defined in loop (PR #191755)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 12 20:36:27 PDT 2026
https://github.com/yuyzhang512 created https://github.com/llvm/llvm-project/pull/191755
Previously, `HoistRegionPostRA` conservatively treated all live-in registers
as external defs, preventing hoisting of any instruction using them. This was
overly conservative for registers defined solely outside the loop, which are
truly loop-invariant.
This patch uses a two-pass approach:
1. First collect all register units defined within the loop
2. Then only mark live-in registers that overlap with loop defs as non-invariant
This allows hoisting instructions that use registers defined only outside the
loop (e.g. spill reloads).
- Added new lit test `machinelicm-livein-not-def-in-loop.mir` with positive and negative cases
- Updated 30 existing tests across AMDGPU, X86, AArch64, SystemZ, and RISCV to reflect improved
hoisting
>From f1fef7809b3298efc1f10ec375395a6e5c678a78 Mon Sep 17 00:00:00 2001
From: yuyzhang512 <yuyzhang at amd.com>
Date: Fri, 3 Apr 2026 03:58:07 +0000
Subject: [PATCH] [MachineLICM] Only mark live-ins as non-invariant if defined
in loop
Previously, HoistRegionPostRA conservatively treated all live-in
registers as external defs, preventing hoisting of any instruction
using them. This was overly conservative for registers defined solely
outside the loop, which are truly loop-invariant.
Use a two-pass approach: first collect all register units defined
within the loop, then only mark live-in registers that overlap with
loop defs as non-invariant. This allows hoisting instructions that
use registers defined only outside the loop (e.g. spill reloads).
---
llvm/lib/CodeGen/MachineLICM.cpp | 34 +++++-
.../AArch64/avoid-free-ext-promotion.ll | 2 +-
.../CodeGen/AArch64/mlicm-implicit-defs.mir | 6 +-
llvm/test/CodeGen/AArch64/peephole-and-tst.ll | 4 +-
.../CodeGen/AMDGPU/coalescer_distribute.ll | 3 +-
.../CodeGen/AMDGPU/indirect-addressing-si.ll | 16 +--
.../AMDGPU/infer-addrspace-flat-atomic.ll | 3 +-
.../CodeGen/AMDGPU/insert-delay-alu-bug.ll | 4 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll | 11 +-
.../machinelicm-livein-not-def-in-loop.mir | 114 ++++++++++++++++++
.../CodeGen/AMDGPU/no-dup-inst-prefetch.ll | 34 +++---
llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll | 3 +-
llvm/test/CodeGen/AMDGPU/select-undef.ll | 61 ++++++----
.../AMDGPU/undefined-subreg-liverange.ll | 3 +-
llvm/test/CodeGen/RISCV/rvv/pr95865.ll | 2 +-
.../DAGCombiner_illegal_BUILD_VECTOR.ll | 2 +-
llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll | 3 +-
.../CodeGen/X86/2007-01-13-StackPtrIndex.ll | 4 +-
.../CodeGen/X86/2009-04-25-CoalescerBug.ll | 2 +-
llvm/test/CodeGen/X86/apx/nf-regressions.ll | 24 ++--
llvm/test/CodeGen/X86/assertzext-demanded.ll | 2 +-
.../CodeGen/X86/combine-i64-trunc-srl-add.ll | 2 +-
llvm/test/CodeGen/X86/combine-pmuldq.ll | 4 +-
.../test/CodeGen/X86/constant-pool-sharing.ll | 8 +-
llvm/test/CodeGen/X86/postalloc-coalescing.ll | 1 -
llvm/test/CodeGen/X86/pr22338.ll | 4 +-
llvm/test/CodeGen/X86/pr63108.ll | 8 +-
.../test/CodeGen/X86/promote-sra-by-itself.ll | 2 +-
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 2 +-
.../CodeGen/X86/split-extend-vector-inreg.ll | 4 +-
llvm/test/CodeGen/X86/trunc-store.ll | 2 +-
llvm/test/CodeGen/X86/undef-label.ll | 11 +-
32 files changed, 272 insertions(+), 113 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/machinelicm-livein-not-def-in-loop.mir
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 53fbd3bec76cd..650d03f3b22f7 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -596,20 +596,42 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
SmallVector<CandidateInfo, 32> Candidates;
SmallDenseSet<int> StoredFIs;
- // Walk the entire region, count number of defs for each register, and
- // collect potential LICM candidates.
+ // First pass: collect all register units defined within the loop.
+ BitVector LoopRUDefs(NumRegUnits);
+ for (MachineBasicBlock *BB : CurLoop->getBlocks()) {
+ for (MachineInstr &MI : *BB) {
+ for (const MachineOperand &MO : MI.operands()) {
+ if (MO.isRegMask()) {
+ applyBitsNotInRegMaskToRegUnitsMask(*TRI, LoopRUDefs,
+ MO.getRegMask());
+ continue;
+ }
+ if (!MO.isReg() || !MO.isDef())
+ continue;
+ Register Reg = MO.getReg();
+ if (!Reg)
+ continue;
+ for (MCRegUnit Unit : TRI->regunits(Reg))
+ LoopRUDefs.set(static_cast<unsigned>(Unit));
+ }
+ }
+ }
+
+ // Second pass: walk the entire region, count number of defs for each
+ // register, and collect potential LICM candidates.
for (MachineBasicBlock *BB : CurLoop->getBlocks()) {
// If the header of the loop containing this basic block is a landing pad,
// then don't try to hoist instructions out of this loop.
const MachineLoop *ML = MLI->getLoopFor(BB);
if (ML && ML->getHeader()->isEHPad()) continue;
- // Conservatively treat live-in's as an external def.
- // FIXME: That means a reload that're reused in successor block(s) will not
- // be LICM'ed.
+ // Only treat live-in registers that are also defined within the loop as
+ // non-invariant. Live-ins that are solely defined outside the loop are
+ // loop-invariant and should not block hoisting.
for (const auto &LI : BB->liveins()) {
for (MCRegUnit Unit : TRI->regunits(LI.PhysReg))
- RUDefs.set(static_cast<unsigned>(Unit));
+ if (LoopRUDefs.test(static_cast<unsigned>(Unit)))
+ RUDefs.set(static_cast<unsigned>(Unit));
}
// Funclet entry blocks will clobber all registers
diff --git a/llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll b/llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll
index 634d1b90ff903..49090aa80b625 100644
--- a/llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll
+++ b/llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll
@@ -14,9 +14,9 @@ define void @avoid_promotion_1_and(ptr nocapture noundef %arg, ptr %p) {
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: ldr w8, [x0, #52]
; CHECK-NEXT: mov w9, #10 ; =0xa
+; CHECK-NEXT: cmp w8, #3
; CHECK-NEXT: LBB0_1: ; %bb8
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmp w8, #3
; CHECK-NEXT: b.lo LBB0_1
; CHECK-NEXT: ; %bb.2: ; %bb9
; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
diff --git a/llvm/test/CodeGen/AArch64/mlicm-implicit-defs.mir b/llvm/test/CodeGen/AArch64/mlicm-implicit-defs.mir
index 2c5a70288cfad..658755489ff44 100644
--- a/llvm/test/CodeGen/AArch64/mlicm-implicit-defs.mir
+++ b/llvm/test/CodeGen/AArch64/mlicm-implicit-defs.mir
@@ -62,15 +62,15 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x12 = COPY killed $x0
+ ; CHECK-NEXT: $x1 = COPY killed $x12
; CHECK-NEXT: $x2 = MOVi64imm 1024, implicit-def dead $x16
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK-NEXT: liveins: $x12, $x2
+ ; CHECK-NEXT: liveins: $x12, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $x1 = COPY killed $x12
- ; CHECK-NEXT: $x16 = LDRXroX killed $x1, $x2, 0, 0
+ ; CHECK-NEXT: $x16 = LDRXroX $x1, $x2, 0, 0
; CHECK-NEXT: $xzr = SUBSXri $x16, 0, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 1, %bb.1, implicit $nzcv
; CHECK-NEXT: B %bb.2
diff --git a/llvm/test/CodeGen/AArch64/peephole-and-tst.ll b/llvm/test/CodeGen/AArch64/peephole-and-tst.ll
index 74b0e69d1b05b..29db9febcb1b8 100644
--- a/llvm/test/CodeGen/AArch64/peephole-and-tst.ll
+++ b/llvm/test/CodeGen/AArch64/peephole-and-tst.ll
@@ -10,6 +10,7 @@ define i32 @test_func_i32_two_uses(i32 %in, i32 %bit, i32 %mask) {
; CHECK-SD-LABEL: test_func_i32_two_uses:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: adrp x8, :got:ptr_wrapper
+; CHECK-SD-NEXT: and w11, w2, w0
; CHECK-SD-NEXT: ldr x8, [x8, :got_lo12:ptr_wrapper]
; CHECK-SD-NEXT: ldr x9, [x8]
; CHECK-SD-NEXT: mov w8, wzr
@@ -22,7 +23,6 @@ define i32 @test_func_i32_two_uses(i32 %in, i32 %bit, i32 %mask) {
; CHECK-SD-NEXT: .LBB0_3: // %do.body
; CHECK-SD-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-SD-NEXT: ands w10, w1, w0
-; CHECK-SD-NEXT: and w11, w2, w0
; CHECK-SD-NEXT: cinc w8, w8, ne
; CHECK-SD-NEXT: cmp w10, w11
; CHECK-SD-NEXT: b.eq .LBB0_1
@@ -40,6 +40,7 @@ define i32 @test_func_i32_two_uses(i32 %in, i32 %bit, i32 %mask) {
; CHECK-GI-LABEL: test_func_i32_two_uses:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: adrp x8, :got:ptr_wrapper
+; CHECK-GI-NEXT: and w11, w2, w0
; CHECK-GI-NEXT: ldr x8, [x8, :got_lo12:ptr_wrapper]
; CHECK-GI-NEXT: ldr x9, [x8]
; CHECK-GI-NEXT: mov w8, wzr
@@ -53,7 +54,6 @@ define i32 @test_func_i32_two_uses(i32 %in, i32 %bit, i32 %mask) {
; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-GI-NEXT: and w10, w1, w0
; CHECK-GI-NEXT: tst w1, w0
-; CHECK-GI-NEXT: and w11, w2, w0
; CHECK-GI-NEXT: cinc w8, w8, ne
; CHECK-GI-NEXT: cmp w10, w11
; CHECK-GI-NEXT: b.eq .LBB0_1
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll b/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
index d07cc84865bea..20990488f3704 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
+++ b/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
@@ -20,9 +20,10 @@ define amdgpu_kernel void @hoge(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) {
; CHECK-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
; CHECK-NEXT: .LBB0_1: ; %bb25
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
+; CHECK-NEXT: s_mov_b64 vcc, vcc
; CHECK-NEXT: s_cbranch_vccnz .LBB0_1
; CHECK-NEXT: ; %bb.2: ; %bb30
; CHECK-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
index a9e67ff3fdcbb..91409c3daeb96 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
@@ -9595,6 +9595,8 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; SI-MOVREL-NEXT: v_mov_b32_e32 v0, 8
; SI-MOVREL-NEXT: s_mov_b32 s3, 0xf000
; SI-MOVREL-NEXT: s_mov_b32 s2, -1
+; SI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-MOVREL-NEXT: v_mov_b32_e32 v17, s1
; SI-MOVREL-NEXT: s_branch .LBB26_2
; SI-MOVREL-NEXT: .LBB26_1:
; SI-MOVREL-NEXT: ; implicit-def: $vgpr0
@@ -9602,14 +9604,12 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; SI-MOVREL-NEXT: .LBB26_2: ; %bb2
; SI-MOVREL-NEXT: ; =>This Loop Header: Depth=1
; SI-MOVREL-NEXT: ; Child Loop BB26_4 Depth 2
-; SI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
; SI-MOVREL-NEXT: v_cmp_le_i32_e32 vcc, s0, v0
; SI-MOVREL-NEXT: s_cbranch_vccnz .LBB26_1
; SI-MOVREL-NEXT: ; %bb.3: ; %bb4
; SI-MOVREL-NEXT: ; in Loop: Header=BB26_2 Depth=1
; SI-MOVREL-NEXT: buffer_load_dword v16, off, s[0:3], 0 glc
; SI-MOVREL-NEXT: s_waitcnt vmcnt(0)
-; SI-MOVREL-NEXT: v_mov_b32_e32 v17, s1
; SI-MOVREL-NEXT: s_mov_b64 s[4:5], exec
; SI-MOVREL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-MOVREL-NEXT: .LBB26_4: ; Parent Loop BB26_2 Depth=1
@@ -9631,6 +9631,8 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; VI-MOVREL: ; %bb.0: ; %bb
; VI-MOVREL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-MOVREL-NEXT: v_mov_b32_e32 v0, 8
+; VI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-MOVREL-NEXT: v_mov_b32_e32 v17, s1
; VI-MOVREL-NEXT: s_branch .LBB26_2
; VI-MOVREL-NEXT: .LBB26_1:
; VI-MOVREL-NEXT: ; implicit-def: $vgpr0
@@ -9638,14 +9640,12 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; VI-MOVREL-NEXT: .LBB26_2: ; %bb2
; VI-MOVREL-NEXT: ; =>This Loop Header: Depth=1
; VI-MOVREL-NEXT: ; Child Loop BB26_4 Depth 2
-; VI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
; VI-MOVREL-NEXT: v_cmp_le_i32_e32 vcc, s0, v0
; VI-MOVREL-NEXT: s_cbranch_vccnz .LBB26_1
; VI-MOVREL-NEXT: ; %bb.3: ; %bb4
; VI-MOVREL-NEXT: ; in Loop: Header=BB26_2 Depth=1
; VI-MOVREL-NEXT: flat_load_dword v16, v[0:1] glc
; VI-MOVREL-NEXT: s_waitcnt vmcnt(0)
-; VI-MOVREL-NEXT: v_mov_b32_e32 v17, s1
; VI-MOVREL-NEXT: s_mov_b64 s[2:3], exec
; VI-MOVREL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; VI-MOVREL-NEXT: .LBB26_4: ; Parent Loop BB26_2 Depth=1
@@ -9667,6 +9667,8 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; VI-IDXMODE: ; %bb.0: ; %bb
; VI-IDXMODE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, 8
+; VI-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
+; VI-IDXMODE-NEXT: v_mov_b32_e32 v17, s1
; VI-IDXMODE-NEXT: s_branch .LBB26_2
; VI-IDXMODE-NEXT: .LBB26_1:
; VI-IDXMODE-NEXT: ; implicit-def: $vgpr0
@@ -9674,14 +9676,12 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; VI-IDXMODE-NEXT: .LBB26_2: ; %bb2
; VI-IDXMODE-NEXT: ; =>This Loop Header: Depth=1
; VI-IDXMODE-NEXT: ; Child Loop BB26_4 Depth 2
-; VI-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
; VI-IDXMODE-NEXT: v_cmp_le_i32_e32 vcc, s0, v0
; VI-IDXMODE-NEXT: s_cbranch_vccnz .LBB26_1
; VI-IDXMODE-NEXT: ; %bb.3: ; %bb4
; VI-IDXMODE-NEXT: ; in Loop: Header=BB26_2 Depth=1
; VI-IDXMODE-NEXT: flat_load_dword v16, v[0:1] glc
; VI-IDXMODE-NEXT: s_waitcnt vmcnt(0)
-; VI-IDXMODE-NEXT: v_mov_b32_e32 v17, s1
; VI-IDXMODE-NEXT: s_mov_b64 s[2:3], exec
; VI-IDXMODE-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; VI-IDXMODE-NEXT: .LBB26_4: ; Parent Loop BB26_2 Depth=1
@@ -9704,6 +9704,8 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; GFX9-IDXMODE: ; %bb.0: ; %bb
; GFX9-IDXMODE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v0, 8
+; GFX9-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v17, s1
; GFX9-IDXMODE-NEXT: s_branch .LBB26_2
; GFX9-IDXMODE-NEXT: .LBB26_1:
; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr0
@@ -9711,14 +9713,12 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; GFX9-IDXMODE-NEXT: .LBB26_2: ; %bb2
; GFX9-IDXMODE-NEXT: ; =>This Loop Header: Depth=1
; GFX9-IDXMODE-NEXT: ; Child Loop BB26_4 Depth 2
-; GFX9-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-IDXMODE-NEXT: v_cmp_le_i32_e32 vcc, s0, v0
; GFX9-IDXMODE-NEXT: s_cbranch_vccnz .LBB26_1
; GFX9-IDXMODE-NEXT: ; %bb.3: ; %bb4
; GFX9-IDXMODE-NEXT: ; in Loop: Header=BB26_2 Depth=1
; GFX9-IDXMODE-NEXT: global_load_dword v16, v[0:1], off glc
; GFX9-IDXMODE-NEXT: s_waitcnt vmcnt(0)
-; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v17, s1
; GFX9-IDXMODE-NEXT: s_mov_b64 s[2:3], exec
; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-IDXMODE-NEXT: .LBB26_4: ; Parent Loop BB26_2 Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll b/llvm/test/CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll
index 36df710529599..338bea9668722 100644
--- a/llvm/test/CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll
+++ b/llvm/test/CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll
@@ -119,9 +119,10 @@ define protected amdgpu_kernel void @InferPHI(i32 %a, ptr addrspace(1) %b, doubl
; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
; CHECK-NEXT: .LBB3_1: ; %bb0
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
+; CHECK-NEXT: s_mov_b64 vcc, vcc
; CHECK-NEXT: s_cbranch_vccnz .LBB3_1
; CHECK-NEXT: ; %bb.2: ; %bb1
; CHECK-NEXT: s_mov_b64 s[0:1], src_shared_base
diff --git a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
index 7d8a0b70d5f55..39f1fee7ca8e8 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
@@ -172,10 +172,10 @@ define amdgpu_kernel void @f2(i32 %arg, i32 %arg1, i32 %arg2, i1 %arg3, i32 %arg
; GFX11-NEXT: s_cbranch_vccz .LBB2_12
; GFX11-NEXT: ; %bb.9:
; GFX11-NEXT: s_xor_b32 s0, s3, -1
-; GFX11-NEXT: .LBB2_10: ; %bb17
-; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s0
+; GFX11-NEXT: .LBB2_10: ; %bb17
+; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_cbranch_vccz .LBB2_10
; GFX11-NEXT: ; %bb.11: ; %Flow6
; GFX11-NEXT: s_mov_b32 s21, -1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
index af81d95973452..f646c40f9300e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
@@ -1529,13 +1529,14 @@ define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1,
; SI-NEXT: ; %bb.1: ; %.preheader1.preheader
; SI-NEXT: v_cmp_ngt_f32_e64 s[0:1], s6, 0
; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
+; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
; SI-NEXT: s_mov_b64 s[2:3], exec
; SI-NEXT: v_mov_b32_e32 v0, 0x3fc00000
-; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
+; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
; SI-NEXT: .LBB26_2: ; %bb
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
; SI-NEXT: v_add_f32_e32 v0, 0x3e800000, v0
+; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccnz .LBB26_2
; SI-NEXT: ; %bb.3: ; %bb33
; SI-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
@@ -1564,10 +1565,10 @@ define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1,
; GFX10-NEXT: s_mov_b64 s[2:3], exec
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX10-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
+; GFX10-NEXT: s_and_b64 vcc, exec, s[0:1]
; GFX10-NEXT: .LBB26_2: ; %bb
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_add_f32_e32 v0, 0x3e800000, v0
-; GFX10-NEXT: s_and_b64 vcc, exec, s[0:1]
; GFX10-NEXT: s_cbranch_vccnz .LBB26_2
; GFX10-NEXT: ; %bb.3: ; %bb33
; GFX10-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
@@ -1597,10 +1598,10 @@ define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1,
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX11-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_sdst(0)
+; GFX11-NEXT: s_and_b64 vcc, exec, s[0:1]
; GFX11-NEXT: .LBB26_2: ; %bb
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: v_add_f32_e32 v0, 0x3e800000, v0
-; GFX11-NEXT: s_and_b64 vcc, exec, s[0:1]
; GFX11-NEXT: s_cbranch_vccnz .LBB26_2
; GFX11-NEXT: ; %bb.3: ; %bb33
; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], exec
@@ -1632,10 +1633,10 @@ define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1,
; GFX12-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX12-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GFX12-NEXT: s_and_b64 vcc, exec, s[0:1]
; GFX12-NEXT: .LBB26_2: ; %bb
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_add_f32 s4, s4, 0x3e800000
-; GFX12-NEXT: s_and_b64 vcc, exec, s[0:1]
; GFX12-NEXT: s_cbranch_vccnz .LBB26_2
; GFX12-NEXT: ; %bb.3: ; %bb33
; GFX12-NEXT: s_and_not1_b64 s[2:3], s[2:3], exec
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-livein-not-def-in-loop.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-livein-not-def-in-loop.mir
new file mode 100644
index 0000000000000..255689463c2dc
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-livein-not-def-in-loop.mir
@@ -0,0 +1,114 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=machinelicm -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=machinelicm -o - %s | FileCheck %s
+
+# Test that post-RA MachineLICM can hoist an instruction using a live-in
+# register that is not defined within the loop. Previously, all live-in
+# registers were conservatively treated as non-invariant, which blocked
+# hoisting.
+
+---
+# $sgpr0 is defined in the preheader and is live-in to the loop body but
+# never redefined inside the loop. The S_MOV_B32 reading $sgpr0 should
+# be hoisted to the preheader.
+name: hoist_livein_not_def_in_loop
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: hoist_livein_not_def_in_loop
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sgpr0 = S_MOV_B32 0
+ ; CHECK-NEXT: $sgpr2 = S_MOV_B32 $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: S_NOP 0, implicit $sgpr2
+ ; CHECK-NEXT: $sgpr1 = S_ADD_I32 $sgpr1, 1, implicit-def $scc
+ ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: liveins: $sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: S_NOP 0, implicit $sgpr2
+ ; CHECK-NEXT: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1
+ liveins: $sgpr0, $sgpr1
+
+ $sgpr0 = S_MOV_B32 0
+
+ bb.1:
+ successors: %bb.1, %bb.2
+ liveins: $sgpr0, $sgpr1
+
+ $sgpr2 = S_MOV_B32 $sgpr0
+ S_NOP 0, implicit $sgpr2
+ $sgpr1 = S_ADD_I32 $sgpr1, 1, implicit-def $scc
+ S_CBRANCH_SCC1 %bb.1, implicit $scc
+ S_BRANCH %bb.2
+
+ bb.2:
+ liveins: $sgpr2
+
+ S_NOP 0, implicit $sgpr2
+ S_ENDPGM 0
+...
+
+---
+# $sgpr0 is live-in to the loop and also defined inside the loop. The
+# S_MOV_B32 reading $sgpr0 should NOT be hoisted since $sgpr0 is not
+# loop-invariant.
+name: no_hoist_livein_def_in_loop
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: no_hoist_livein_def_in_loop
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sgpr0 = S_MOV_B32 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sgpr2 = S_MOV_B32 $sgpr0
+ ; CHECK-NEXT: $sgpr0 = S_ADD_I32 $sgpr0, 1, implicit-def $scc
+ ; CHECK-NEXT: S_NOP 0, implicit $sgpr2
+ ; CHECK-NEXT: $sgpr1 = S_ADD_I32 $sgpr1, -1, implicit-def $scc
+ ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: liveins: $sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: S_NOP 0, implicit $sgpr2
+ ; CHECK-NEXT: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1
+ liveins: $sgpr0, $sgpr1
+
+ $sgpr0 = S_MOV_B32 0
+
+ bb.1:
+ successors: %bb.1, %bb.2
+ liveins: $sgpr0, $sgpr1
+
+ $sgpr2 = S_MOV_B32 $sgpr0
+ $sgpr0 = S_ADD_I32 $sgpr0, 1, implicit-def $scc
+ S_NOP 0, implicit $sgpr2
+ $sgpr1 = S_ADD_I32 $sgpr1, -1, implicit-def $scc
+ S_CBRANCH_SCC1 %bb.1, implicit $scc
+ S_BRANCH %bb.2
+
+ bb.2:
+ liveins: $sgpr2
+
+ S_NOP 0, implicit $sgpr2
+ S_ENDPGM 0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll b/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
index 306703bd61806..0ff552f90a0bc 100644
--- a/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
@@ -10,8 +10,15 @@ define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s1, 0
+; GFX10-NEXT: s_mov_b32 s8, s4
+; GFX10-NEXT: s_mov_b32 s9, s4
+; GFX10-NEXT: s_mov_b32 s10, s4
+; GFX10-NEXT: s_mov_b32 s11, s4
+; GFX10-NEXT: s_mov_b32 s12, s4
+; GFX10-NEXT: s_mov_b32 s13, s4
+; GFX10-NEXT: s_mov_b32 s14, s4
+; GFX10-NEXT: s_mov_b32 s15, s4
; GFX10-NEXT: ; implicit-def: $sgpr2
-; GFX10-NEXT: s_inst_prefetch 0x1
; GFX10-NEXT: s_branch .LBB0_2
; GFX10-NEXT: .p2align 6
; GFX10-NEXT: .LBB0_1: ; %Flow
@@ -32,14 +39,6 @@ define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX10-NEXT: s_mov_b32 s5, s4
; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s7, s4
-; GFX10-NEXT: s_mov_b32 s8, s4
-; GFX10-NEXT: s_mov_b32 s9, s4
-; GFX10-NEXT: s_mov_b32 s10, s4
-; GFX10-NEXT: s_mov_b32 s11, s4
-; GFX10-NEXT: s_mov_b32 s12, s4
-; GFX10-NEXT: s_mov_b32 s13, s4
-; GFX10-NEXT: s_mov_b32 s14, s4
-; GFX10-NEXT: s_mov_b32 s15, s4
; GFX10-NEXT: s_andn2_b32 s2, s2, exec_lo
; GFX10-NEXT: image_sample_lz v1, [v2, v2, v1], s[8:15], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_3D
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -49,7 +48,6 @@ define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX10-NEXT: s_or_b32 s2, s2, s0
; GFX10-NEXT: s_branch .LBB0_1
; GFX10-NEXT: .LBB0_4: ; %loop0_merge
-; GFX10-NEXT: s_inst_prefetch 0x2
; GFX10-NEXT: s_endpgm
;
; GFX12-LABEL: _amdgpu_cs_main:
@@ -59,6 +57,14 @@ define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX12-NEXT: v_mov_b32_e32 v1, 0
; GFX12-NEXT: s_mov_b32 s4, 0
; GFX12-NEXT: s_mov_b32 s1, 0
+; GFX12-NEXT: s_mov_b32 s8, s4
+; GFX12-NEXT: s_mov_b32 s9, s4
+; GFX12-NEXT: s_mov_b32 s10, s4
+; GFX12-NEXT: s_mov_b32 s11, s4
+; GFX12-NEXT: s_mov_b32 s12, s4
+; GFX12-NEXT: s_mov_b32 s13, s4
+; GFX12-NEXT: s_mov_b32 s14, s4
+; GFX12-NEXT: s_mov_b32 s15, s4
; GFX12-NEXT: ; implicit-def: $sgpr2
; GFX12-NEXT: s_branch .LBB0_2
; GFX12-NEXT: .LBB0_1: ; %Flow
@@ -80,14 +86,6 @@ define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX12-NEXT: s_mov_b32 s5, s4
; GFX12-NEXT: s_mov_b32 s6, s4
; GFX12-NEXT: s_mov_b32 s7, s4
-; GFX12-NEXT: s_mov_b32 s8, s4
-; GFX12-NEXT: s_mov_b32 s9, s4
-; GFX12-NEXT: s_mov_b32 s10, s4
-; GFX12-NEXT: s_mov_b32 s11, s4
-; GFX12-NEXT: s_mov_b32 s12, s4
-; GFX12-NEXT: s_mov_b32 s13, s4
-; GFX12-NEXT: s_mov_b32 s14, s4
-; GFX12-NEXT: s_mov_b32 s15, s4
; GFX12-NEXT: s_and_not1_b32 s2, s2, exec_lo
; GFX12-NEXT: image_sample_lz v1, [v2, v2, v1], s[8:15], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_3D
; GFX12-NEXT: s_wait_samplecnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll b/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
index 5155873afa8f6..ec127d1f70534 100644
--- a/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
@@ -401,14 +401,15 @@ define amdgpu_kernel void @clobbering_loop(ptr addrspace(1) %arg, ptr addrspace(
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: .LBB6_1: ; %while.cond
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: global_load_dword v1, v0, s[8:9] offset:4
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: v_add_u32_e32 v1, s2, v1
; GCN-NEXT: global_store_dword v0, v1, s[10:11] offset:4
; GCN-NEXT: ; wave barrier
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB6_1
; GCN-NEXT: ; %bb.2: ; %end
; GCN-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/select-undef.ll b/llvm/test/CodeGen/AMDGPU/select-undef.ll
index f497752994852..8737cc351d8a0 100644
--- a/llvm/test/CodeGen/AMDGPU/select-undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-undef.ll
@@ -62,12 +62,12 @@ define amdgpu_kernel void @undef_v6f32(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB4_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b128 v[6:9], v0
; GCN-NEXT: ds_read_b64 v[10:11], v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(1)
; GCN-NEXT: v_add_f32_e32 v3, v9, v3
; GCN-NEXT: s_waitcnt lgkmcnt(0)
@@ -76,6 +76,7 @@ define amdgpu_kernel void @undef_v6f32(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: v_add_f32_e32 v2, v8, v2
; GCN-NEXT: v_add_f32_e32 v1, v7, v1
; GCN-NEXT: v_add_f32_e32 v0, v6, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB4_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b64 v0, v[4:5]
@@ -106,12 +107,12 @@ define amdgpu_kernel void @undef_v6i32(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB5_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b128 v[6:9], v0
; GCN-NEXT: ds_read_b64 v[10:11], v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(1)
; GCN-NEXT: v_add_u32_e32 v3, v9, v3
; GCN-NEXT: s_waitcnt lgkmcnt(0)
@@ -120,6 +121,7 @@ define amdgpu_kernel void @undef_v6i32(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: v_add_u32_e32 v2, v8, v2
; GCN-NEXT: v_add_u32_e32 v1, v7, v1
; GCN-NEXT: v_add_u32_e32 v0, v6, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB5_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b64 v0, v[4:5]
@@ -151,12 +153,12 @@ define amdgpu_kernel void @undef_v5f32(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB6_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b128 v[5:8], v0
; GCN-NEXT: ds_read_b32 v9, v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(1)
; GCN-NEXT: v_add_f32_e32 v3, v8, v3
; GCN-NEXT: s_waitcnt lgkmcnt(0)
@@ -164,6 +166,7 @@ define amdgpu_kernel void @undef_v5f32(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: v_add_f32_e32 v2, v7, v2
; GCN-NEXT: v_add_f32_e32 v1, v6, v1
; GCN-NEXT: v_add_f32_e32 v0, v5, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB6_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b32 v0, v4
@@ -194,12 +197,12 @@ define amdgpu_kernel void @undef_v5i32(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB7_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b128 v[5:8], v0
; GCN-NEXT: ds_read_b32 v9, v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(1)
; GCN-NEXT: v_add_u32_e32 v3, v8, v3
; GCN-NEXT: s_waitcnt lgkmcnt(0)
@@ -207,6 +210,7 @@ define amdgpu_kernel void @undef_v5i32(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: v_add_u32_e32 v2, v7, v2
; GCN-NEXT: v_add_u32_e32 v1, v6, v1
; GCN-NEXT: v_add_u32_e32 v0, v5, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB7_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b32 v0, v4
@@ -237,19 +241,20 @@ define amdgpu_kernel void @undef_v3f64(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v6, s2
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: v_mov_b32_e32 v6, s2
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1
; GCN-NEXT: .LBB8_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b128 v[7:10], v6
; GCN-NEXT: ds_read_b64 v[11:12], v6 offset:16
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(1)
; GCN-NEXT: v_add_f64 v[2:3], v[9:10], v[2:3]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_add_f64 v[4:5], v[11:12], v[4:5]
; GCN-NEXT: v_add_f64 v[0:1], v[7:8], v[0:1]
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB8_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: v_mov_b32_e32 v6, s2
@@ -326,16 +331,17 @@ define amdgpu_kernel void @undef_v4f16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB10_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b64 v[3:4], v2
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_f16 v1, v4, v1
; GCN-NEXT: v_pk_add_f16 v0, v3, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB10_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: v_mov_b32_e32 v2, s2
@@ -364,16 +370,17 @@ define amdgpu_kernel void @undef_v4i16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB11_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b64 v[3:4], v2
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_u16 v1, v4, v1
; GCN-NEXT: v_pk_add_u16 v0, v3, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB11_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: v_mov_b32_e32 v2, s2
@@ -403,15 +410,16 @@ define amdgpu_kernel void @undef_v2f16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
+; GCN-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: .LBB12_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b32 v2, v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_f16 v1, v2, v1
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB12_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: v_mov_b32_e32 v0, s2
@@ -440,15 +448,16 @@ define amdgpu_kernel void @undef_v2i16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
+; GCN-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: .LBB13_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b32 v2, v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_u16 v1, v2, v1
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB13_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: v_mov_b32_e32 v0, s2
@@ -502,13 +511,14 @@ define amdgpu_kernel void @undef_bf16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB15_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_u16 v1, v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_add_u32_e32 v0, v1, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB15_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b16 v0, v0
@@ -540,13 +550,14 @@ define amdgpu_kernel void @undef_v2bf16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB16_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b32 v1, v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_u16 v0, v1, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB16_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b32 v0, v0
@@ -579,16 +590,17 @@ define amdgpu_kernel void @undef_v3bf16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB17_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b32 v2, v0
; GCN-NEXT: ds_read_u16 v3, v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(1)
; GCN-NEXT: v_pk_add_u16 v0, v2, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_u16 v1, v3, v1
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB17_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b16 v0, v1
@@ -621,14 +633,15 @@ define amdgpu_kernel void @undef_v4bf16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB18_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b64 v[2:3], v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_u16 v1, v3, v1
; GCN-NEXT: v_pk_add_u16 v0, v2, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB18_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b64 v0, v[0:1]
@@ -661,17 +674,18 @@ define amdgpu_kernel void @undef_v6bf16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB19_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b64 v[3:4], v0
; GCN-NEXT: ds_read_b32 v5, v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(1)
; GCN-NEXT: v_pk_add_u16 v1, v4, v1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_u16 v2, v5, v2
; GCN-NEXT: v_pk_add_u16 v0, v3, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB19_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b32 v0, v2
@@ -704,16 +718,17 @@ define amdgpu_kernel void @undef_v8bf16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB20_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b128 v[4:7], v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_u16 v3, v7, v3
; GCN-NEXT: v_pk_add_u16 v2, v6, v2
; GCN-NEXT: v_pk_add_u16 v1, v5, v1
; GCN-NEXT: v_pk_add_u16 v0, v4, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB20_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b128 v0, v[0:3]
@@ -746,11 +761,11 @@ define amdgpu_kernel void @undef_v16bf16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB21_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b128 v[8:11], v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_u16 v7, v11, v7
; GCN-NEXT: v_pk_add_u16 v6, v10, v6
@@ -760,6 +775,7 @@ define amdgpu_kernel void @undef_v16bf16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: v_pk_add_u16 v2, v10, v2
; GCN-NEXT: v_pk_add_u16 v1, v9, v1
; GCN-NEXT: v_pk_add_u16 v0, v8, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB21_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b128 v0, v[4:7]
@@ -795,11 +811,11 @@ define amdgpu_kernel void @undef_v32bf16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB22_1: ; %loop
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: ds_read_b128 v[16:19], v0
-; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_add_u16 v15, v19, v15
; GCN-NEXT: v_pk_add_u16 v14, v18, v14
@@ -817,6 +833,7 @@ define amdgpu_kernel void @undef_v32bf16(ptr addrspace(3) %ptr, i1 %cond) {
; GCN-NEXT: v_pk_add_u16 v2, v18, v2
; GCN-NEXT: v_pk_add_u16 v1, v17, v1
; GCN-NEXT: v_pk_add_u16 v0, v16, v0
+; GCN-NEXT: s_mov_b64 vcc, vcc
; GCN-NEXT: s_cbranch_vccnz .LBB22_1
; GCN-NEXT: ; %bb.2: ; %ret
; GCN-NEXT: ds_write_b128 v0, v[12:15]
diff --git a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
index 31708a9b738db..7e7fca3e5a29b 100644
--- a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
+++ b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
@@ -59,9 +59,10 @@ define amdgpu_ps float @valley_partially_undef_copy() #0 {
; CHECK-NEXT: s_waitcnt expcnt(1)
; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
+; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
; CHECK-NEXT: .LBB1_1: ; %bb9
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
+; CHECK-NEXT: s_mov_b64 vcc, vcc
; CHECK-NEXT: s_cbranch_vccnz .LBB1_1
; CHECK-NEXT: ; %bb.2: ; %bb11
; CHECK-NEXT: s_mov_b32 s3, 0xf000
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr95865.ll b/llvm/test/CodeGen/RISCV/rvv/pr95865.ll
index 01d66b344ec2e..98aa588db3220 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr95865.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr95865.ll
@@ -44,6 +44,7 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: andi t3, a4, 1
; CHECK-NEXT: li t2, 4
+; CHECK-NEXT: andi s10, a0, 1
; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader.i
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB0_2 Depth 2
@@ -103,7 +104,6 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
; CHECK-NEXT: addi s8, s8, 4
; CHECK-NEXT: addi ra, ra, 4
; CHECK-NEXT: addi a3, a3, 4
-; CHECK-NEXT: andi s10, a0, 1
; CHECK-NEXT: addi s11, s11, 4
; CHECK-NEXT: beqz s10, .LBB0_4
; CHECK-NEXT: # %bb.7: # %for.cond.cleanup11.i
diff --git a/llvm/test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll b/llvm/test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll
index 02bae826dcbc1..694013b82536e 100644
--- a/llvm/test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll
+++ b/llvm/test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll
@@ -8,9 +8,9 @@
define void @pr32422(double %a0) {
; CHECK-LABEL: pr32422:
; CHECK: # %bb.0: # %BB
+; CHECK-NEXT: cdbr %f0, %f0
; CHECK-NEXT: .LBB0_1: # %CF
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cdbr %f0, %f0
; CHECK-NEXT: jo .LBB0_1
; CHECK-NEXT: # %bb.2: # %CF353
; CHECK-NEXT: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll b/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
index 278f0bf2a30f6..84f865ee3cf72 100644
--- a/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
@@ -11,9 +11,10 @@ define void @pr32275(<4 x i8> %B15) {
; CHECK-NEXT: vrepif %v1, 1
; CHECK-NEXT: vn %v0, %v0, %v1
; CHECK-NEXT: vlgvf %r0, %v0, 3
+; CHECK-NEXT: chi %r0, 0
; CHECK-NEXT: .LBB0_1: # %CF34
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cijlh %r0, 0, .LBB0_1
+; CHECK-NEXT: jlh .LBB0_1
; CHECK-NEXT: # %bb.2: # %CF36
; CHECK-NEXT: br %r14
BB:
diff --git a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
index 1e5ee2f71d9b4..9e9688c7389bb 100644
--- a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
+++ b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
@@ -27,10 +27,10 @@ define dso_local void @foo(ptr %a0, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5)
; CHECK-NEXT: js .LBB0_14
; CHECK-NEXT: # %bb.12:
; CHECK-NEXT: xorl %r8d, %r8d
+; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_13: # %a25b
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: je .LBB0_13
; CHECK-NEXT: .LBB0_14: # %b85
; CHECK-NEXT: movb $1, %r8b
@@ -38,10 +38,10 @@ define dso_local void @foo(ptr %a0, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5)
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.15:
; CHECK-NEXT: xorl %r8d, %r8d
+; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_16: # %a25b140
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: je .LBB0_16
; CHECK-NEXT: .LBB0_1: # %a29b
; CHECK-NEXT: cmpl %esi, %edi
diff --git a/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll b/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
index 1dd30e8263099..a01ee300a08c5 100644
--- a/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
+++ b/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
@@ -8,10 +8,10 @@ define i64 @test(ptr %tmp13) nounwind {
; CHECK-NEXT: movl (%rdi), %ecx
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: shrl %eax
+; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %while.cond
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %while.end
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/apx/nf-regressions.ll b/llvm/test/CodeGen/X86/apx/nf-regressions.ll
index 68bd05a0737b6..fd20b3b422b44 100644
--- a/llvm/test/CodeGen/X86/apx/nf-regressions.ll
+++ b/llvm/test/CodeGen/X86/apx/nf-regressions.ll
@@ -9,12 +9,13 @@ define void @convertToThreeAddress(ptr %arg, ptr %arg1) {
; CHECK-NEXT: subq %rax, %rcx
; CHECK-NEXT: leaq 1(%rcx), %rax
; CHECK-NEXT: js .LBB0_1
+; CHECK-NEXT: # %bb.6: # %bb.preheader
+; CHECK-NEXT: cmpq $1, %rax
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB0_6: # %bb
+; CHECK-NEXT: .LBB0_7: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpq $1, %rax
-; CHECK-NEXT: jg .LBB0_6
-; CHECK-NEXT: .LBB0_5: # %bb16
+; CHECK-NEXT: jg .LBB0_7
+; CHECK-NEXT: .LBB0_9: # %bb16
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: xorl %edx, %edx
@@ -23,21 +24,22 @@ define void @convertToThreeAddress(ptr %arg, ptr %arg1) {
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %dl, %dl
; CHECK-NEXT: je .LBB0_3
-; CHECK-NEXT: # %bb.7: # %bb11
+; CHECK-NEXT: # %bb.8: # %bb11
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: testq %rcx, %rcx
; CHECK-NEXT: jns .LBB0_2
-; CHECK-NEXT: jmp .LBB0_5
+; CHECK-NEXT: jmp .LBB0_9
; CHECK-NEXT: .LBB0_3: # %bb10
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testb %cl, %cl
-; CHECK-NEXT: jne .LBB0_5
+; CHECK-NEXT: jne .LBB0_9
+; CHECK-NEXT: # %bb.4:
+; CHECK-NEXT: cmpq $1, %rax
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB0_4: # %bb12
+; CHECK-NEXT: .LBB0_5: # %bb12
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpq $1, %rax
-; CHECK-NEXT: jg .LBB0_4
-; CHECK-NEXT: jmp .LBB0_5
+; CHECK-NEXT: jg .LBB0_5
+; CHECK-NEXT: jmp .LBB0_9
entry:
%i = load i32, ptr %arg, align 4
%i2 = sext i32 %i to i64
diff --git a/llvm/test/CodeGen/X86/assertzext-demanded.ll b/llvm/test/CodeGen/X86/assertzext-demanded.ll
index 33a8c543ed9ab..fd314d8a2d3b9 100644
--- a/llvm/test/CodeGen/X86/assertzext-demanded.ll
+++ b/llvm/test/CodeGen/X86/assertzext-demanded.ll
@@ -7,10 +7,10 @@ define void @simplify_assertzext(ptr %0) {
; CHECK: # %bb.0: # %BB
; CHECK-NEXT: movl $275047, %eax # imm = 0x43267
; CHECK-NEXT: movb $1, %cl
+; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %CF246
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %CF260
; CHECK-NEXT: orl $278403, %eax # imm = 0x43F83
diff --git a/llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll b/llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll
index f7906e5a009ae..84c2b7946e1fb 100644
--- a/llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll
+++ b/llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll
@@ -233,10 +233,10 @@ define i32 @pr128158(i64 %x) {
; X64-NEXT: movabsq $-4294967296, %rax # imm = 0xFFFFFFFF00000000
; X64-NEXT: addq %rdi, %rax
; X64-NEXT: shrq $32, %rax
+; X64-NEXT: cmpl $9, %eax
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB16_1: # %for.body
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: cmpl $9, %eax
; X64-NEXT: jb .LBB16_1
; X64-NEXT: # %bb.2: # %exit
; X64-NEXT: xorl %eax, %eax
diff --git a/llvm/test/CodeGen/X86/combine-pmuldq.ll b/llvm/test/CodeGen/X86/combine-pmuldq.ll
index 5b279e5953629..0189e1589241c 100644
--- a/llvm/test/CodeGen/X86/combine-pmuldq.ll
+++ b/llvm/test/CodeGen/X86/combine-pmuldq.ll
@@ -208,20 +208,20 @@ define <8 x i64> @combine_zext_pmuludq_256(<8 x i32> %a) {
define void @PR39398(i32 %a0) {
; SSE-LABEL: PR39398:
; SSE: # %bb.0: # %bb
+; SSE-NEXT: cmpl $232, %edi
; SSE-NEXT: .p2align 4
; SSE-NEXT: .LBB5_1: # %bb10
; SSE-NEXT: # =>This Inner Loop Header: Depth=1
-; SSE-NEXT: cmpl $232, %edi
; SSE-NEXT: jne .LBB5_1
; SSE-NEXT: # %bb.2: # %bb34
; SSE-NEXT: retq
;
; AVX-LABEL: PR39398:
; AVX: # %bb.0: # %bb
+; AVX-NEXT: cmpl $232, %edi
; AVX-NEXT: .p2align 4
; AVX-NEXT: .LBB5_1: # %bb10
; AVX-NEXT: # =>This Inner Loop Header: Depth=1
-; AVX-NEXT: cmpl $232, %edi
; AVX-NEXT: jne .LBB5_1
; AVX-NEXT: # %bb.2: # %bb34
; AVX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/constant-pool-sharing.ll b/llvm/test/CodeGen/X86/constant-pool-sharing.ll
index be835f78292e5..647fa4a6e6d9d 100644
--- a/llvm/test/CodeGen/X86/constant-pool-sharing.ll
+++ b/llvm/test/CodeGen/X86/constant-pool-sharing.ll
@@ -12,12 +12,12 @@ define void @share_v4i32_v4f32(ptr %p, ptr %q, i1 %t) nounwind {
; SSE-LINUX-LABEL: share_v4i32_v4f32:
; SSE-LINUX: # %bb.0: # %entry
; SSE-LINUX-NEXT: movaps {{.*#+}} xmm0 = [1073741824,1073741824,1073741824,1073741824]
+; SSE-LINUX-NEXT: testb $1, %dl
; SSE-LINUX-NEXT: .p2align 4
; SSE-LINUX-NEXT: .LBB0_1: # %loop
; SSE-LINUX-NEXT: # =>This Inner Loop Header: Depth=1
; SSE-LINUX-NEXT: movaps %xmm0, (%rdi)
; SSE-LINUX-NEXT: movaps %xmm0, (%rsi)
-; SSE-LINUX-NEXT: testb $1, %dl
; SSE-LINUX-NEXT: jne .LBB0_1
; SSE-LINUX-NEXT: # %bb.2: # %ret
; SSE-LINUX-NEXT: retq
@@ -25,12 +25,12 @@ define void @share_v4i32_v4f32(ptr %p, ptr %q, i1 %t) nounwind {
; SSE-MSVC-LABEL: share_v4i32_v4f32:
; SSE-MSVC: # %bb.0: # %entry
; SSE-MSVC-NEXT: movaps {{.*#+}} xmm0 = [1073741824,1073741824,1073741824,1073741824]
+; SSE-MSVC-NEXT: testb $1, %r8b
; SSE-MSVC-NEXT: .p2align 4
; SSE-MSVC-NEXT: .LBB0_1: # %loop
; SSE-MSVC-NEXT: # =>This Inner Loop Header: Depth=1
; SSE-MSVC-NEXT: movaps %xmm0, (%rcx)
; SSE-MSVC-NEXT: movaps %xmm0, (%rdx)
-; SSE-MSVC-NEXT: testb $1, %r8b
; SSE-MSVC-NEXT: jne .LBB0_1
; SSE-MSVC-NEXT: # %bb.2: # %ret
; SSE-MSVC-NEXT: retq
@@ -39,12 +39,12 @@ define void @share_v4i32_v4f32(ptr %p, ptr %q, i1 %t) nounwind {
; AVX-LINUX: # %bb.0: # %entry
; AVX-LINUX-NEXT: vbroadcastss {{.*#+}} xmm0 = [1073741824,1073741824,1073741824,1073741824]
; AVX-LINUX-NEXT: vbroadcastss {{.*#+}} xmm1 = [1073741824,1073741824,1073741824,1073741824]
+; AVX-LINUX-NEXT: testb $1, %dl
; AVX-LINUX-NEXT: .p2align 4
; AVX-LINUX-NEXT: .LBB0_1: # %loop
; AVX-LINUX-NEXT: # =>This Inner Loop Header: Depth=1
; AVX-LINUX-NEXT: vmovaps %xmm0, (%rdi)
; AVX-LINUX-NEXT: vmovaps %xmm1, (%rsi)
-; AVX-LINUX-NEXT: testb $1, %dl
; AVX-LINUX-NEXT: jne .LBB0_1
; AVX-LINUX-NEXT: # %bb.2: # %ret
; AVX-LINUX-NEXT: retq
@@ -53,12 +53,12 @@ define void @share_v4i32_v4f32(ptr %p, ptr %q, i1 %t) nounwind {
; AVX-MSVC: # %bb.0: # %entry
; AVX-MSVC-NEXT: vbroadcastss {{.*#+}} xmm0 = [1073741824,1073741824,1073741824,1073741824]
; AVX-MSVC-NEXT: vbroadcastss {{.*#+}} xmm1 = [1073741824,1073741824,1073741824,1073741824]
+; AVX-MSVC-NEXT: testb $1, %r8b
; AVX-MSVC-NEXT: .p2align 4
; AVX-MSVC-NEXT: .LBB0_1: # %loop
; AVX-MSVC-NEXT: # =>This Inner Loop Header: Depth=1
; AVX-MSVC-NEXT: vmovaps %xmm0, (%rcx)
; AVX-MSVC-NEXT: vmovaps %xmm1, (%rdx)
-; AVX-MSVC-NEXT: testb $1, %r8b
; AVX-MSVC-NEXT: jne .LBB0_1
; AVX-MSVC-NEXT: # %bb.2: # %ret
; AVX-MSVC-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/postalloc-coalescing.ll b/llvm/test/CodeGen/X86/postalloc-coalescing.ll
index 7430d7a9baf26..ca9cc71ba078e 100644
--- a/llvm/test/CodeGen/X86/postalloc-coalescing.ll
+++ b/llvm/test/CodeGen/X86/postalloc-coalescing.ll
@@ -11,7 +11,6 @@ define fastcc i32 @_Z18yy_get_next_bufferv() nounwind {
; CHECK-NEXT: .LBB0_1: # %bb116
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movb %al, 0
-; CHECK-NEXT: cmpl $-1, %eax
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: .LBB0_3: # %bb158
; CHECK-NEXT: movb %al, 0
diff --git a/llvm/test/CodeGen/X86/pr22338.ll b/llvm/test/CodeGen/X86/pr22338.ll
index bf3967ca8fede..fd8c23c245793 100644
--- a/llvm/test/CodeGen/X86/pr22338.ll
+++ b/llvm/test/CodeGen/X86/pr22338.ll
@@ -21,10 +21,10 @@ define i32 @fn(i32 %a0, i32 %a1) {
; X86-NEXT: addb %dl, %dl
; X86-NEXT: movl %edx, %ecx
; X86-NEXT: shll %cl, %eax
+; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB0_1: # %bb1
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: je .LBB0_1
; X86-NEXT: # %bb.2: # %bb2
; X86-NEXT: popl %ebx
@@ -46,10 +46,10 @@ define i32 @fn(i32 %a0, i32 %a1) {
; X64-NEXT: addb %dl, %dl
; X64-NEXT: movl %edx, %ecx
; X64-NEXT: shll %cl, %eax
+; X64-NEXT: testl %esi, %esi
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB0_1: # %bb1
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: testl %esi, %esi
; X64-NEXT: je .LBB0_1
; X64-NEXT: # %bb.2: # %bb2
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr63108.ll b/llvm/test/CodeGen/X86/pr63108.ll
index b5b80515fc6d9..7f0844c8af65d 100644
--- a/llvm/test/CodeGen/X86/pr63108.ll
+++ b/llvm/test/CodeGen/X86/pr63108.ll
@@ -16,11 +16,11 @@ define i32 @PR63108() {
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: movd {{.*#+}} xmm1 = [57339,0,0,0]
; SSE-NEXT: xorl %eax, %eax
+; SSE-NEXT: testb %al, %al
; SSE-NEXT: .p2align 4
; SSE-NEXT: .LBB0_3: # %vector.body
; SSE-NEXT: # =>This Inner Loop Header: Depth=1
; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: testb %al, %al
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: jne .LBB0_3
; SSE-NEXT: # %bb.4: # %middle.block
@@ -50,12 +50,12 @@ define i32 @PR63108() {
; AVX1-NEXT: .LBB0_2: # %vector.body.preheader
; AVX1-NEXT: vmovss {{.*#+}} xmm0 = [57339,0,0,0]
; AVX1-NEXT: xorl %eax, %eax
+; AVX1-NEXT: testb %al, %al
; AVX1-NEXT: .p2align 4
; AVX1-NEXT: .LBB0_3: # %vector.body
; AVX1-NEXT: # =>This Inner Loop Header: Depth=1
; AVX1-NEXT: vmovaps %ymm0, %ymm1
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: testb %al, %al
; AVX1-NEXT: jne .LBB0_3
; AVX1-NEXT: # %bb.4: # %middle.block
; AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
@@ -86,12 +86,12 @@ define i32 @PR63108() {
; AVX2-NEXT: .LBB0_2: # %vector.body.preheader
; AVX2-NEXT: vmovd {{.*#+}} xmm0 = [57339,0,0,0]
; AVX2-NEXT: xorl %eax, %eax
+; AVX2-NEXT: testb %al, %al
; AVX2-NEXT: .p2align 4
; AVX2-NEXT: .LBB0_3: # %vector.body
; AVX2-NEXT: # =>This Inner Loop Header: Depth=1
; AVX2-NEXT: vmovdqa %ymm0, %ymm1
; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
-; AVX2-NEXT: testb %al, %al
; AVX2-NEXT: jne .LBB0_3
; AVX2-NEXT: # %bb.4: # %middle.block
; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
@@ -122,12 +122,12 @@ define i32 @PR63108() {
; AVX512-NEXT: .LBB0_2: # %vector.body.preheader
; AVX512-NEXT: vmovd {{.*#+}} xmm0 = [57339,0,0,0]
; AVX512-NEXT: xorl %eax, %eax
+; AVX512-NEXT: testb %al, %al
; AVX512-NEXT: .p2align 4
; AVX512-NEXT: .LBB0_3: # %vector.body
; AVX512-NEXT: # =>This Inner Loop Header: Depth=1
; AVX512-NEXT: vmovdqa %ymm0, %ymm1
; AVX512-NEXT: vpxor %xmm0, %xmm0, %xmm0
-; AVX512-NEXT: testb %al, %al
; AVX512-NEXT: jne .LBB0_3
; AVX512-NEXT: # %bb.4: # %middle.block
; AVX512-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
diff --git a/llvm/test/CodeGen/X86/promote-sra-by-itself.ll b/llvm/test/CodeGen/X86/promote-sra-by-itself.ll
index d57411f495b69..001e6bbc5909a 100644
--- a/llvm/test/CodeGen/X86/promote-sra-by-itself.ll
+++ b/llvm/test/CodeGen/X86/promote-sra-by-itself.ll
@@ -19,10 +19,10 @@ define i16 @basic(ptr %p) {
define void @crash(i1 %cond, ptr %p) {
; CHECK-LABEL: crash:
; CHECK: # %bb.0:
+; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB1_1: # %loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne .LBB1_1
; CHECK-NEXT: # %bb.2: # %exit
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
index 69a6cdb7081eb..a13255f8c55d4 100644
--- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
+++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
@@ -82,11 +82,11 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: movq _syCTRO at GOTPCREL(%rip), %rax
; CHECK-NEXT: movl $1, %r13d
; CHECK-NEXT: movb $1, %cl
+; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: LBB0_9: ## %do.body
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl $0, (%rax)
-; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: jne LBB0_9
; CHECK-NEXT: ## %bb.10: ## %do.end
; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
diff --git a/llvm/test/CodeGen/X86/split-extend-vector-inreg.ll b/llvm/test/CodeGen/X86/split-extend-vector-inreg.ll
index c8e31f7088a45..fdde231ded80f 100644
--- a/llvm/test/CodeGen/X86/split-extend-vector-inreg.ll
+++ b/llvm/test/CodeGen/X86/split-extend-vector-inreg.ll
@@ -9,10 +9,10 @@ define <4 x i64> @autogen_SD88863() {
; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X86-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[3],ymm1[3]
; X86-NEXT: movb $1, %al
+; X86-NEXT: testb %al, %al
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB0_1: # %CF
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: testb %al, %al
; X86-NEXT: jne .LBB0_1
; X86-NEXT: # %bb.2: # %CF240
; X86-NEXT: retl
@@ -23,10 +23,10 @@ define <4 x i64> @autogen_SD88863() {
; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[3],ymm1[3]
; X64-NEXT: movb $1, %al
+; X64-NEXT: testb %al, %al
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB0_1: # %CF
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: testb %al, %al
; X64-NEXT: jne .LBB0_1
; X64-NEXT: # %bb.2: # %CF240
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/trunc-store.ll b/llvm/test/CodeGen/X86/trunc-store.ll
index 3ce06f7caa28e..925e6c93d8ed2 100644
--- a/llvm/test/CodeGen/X86/trunc-store.ll
+++ b/llvm/test/CodeGen/X86/trunc-store.ll
@@ -29,10 +29,10 @@
define void @fn1(i64 %a0) {
; CHECK-LABEL: fn1:
; CHECK: # %bb.0: # %for.cond
+; CHECK-NEXT: cmpq $8, %rdi
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpq $8, %rdi
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %middle.block
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/undef-label.ll b/llvm/test/CodeGen/X86/undef-label.ll
index a2d9bc571f582..a13b10e4f0495 100644
--- a/llvm/test/CodeGen/X86/undef-label.ll
+++ b/llvm/test/CodeGen/X86/undef-label.ll
@@ -14,13 +14,14 @@ define dso_local void @xyz() {
; CHECK-NEXT: xorpd %xmm1, %xmm1
; CHECK-NEXT: ucomisd %xmm1, %xmm0
; CHECK-NEXT: jne .LBB0_1
-; CHECK-NEXT: jnp .LBB0_2
+; CHECK-NEXT: jnp .LBB0_3
+; CHECK-NEXT: .LBB0_1: # %foo.preheader
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB0_1: # %foo
+; CHECK-NEXT: .LBB0_2: # %foo
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: ja .LBB0_1
-; CHECK-NEXT: .LBB0_2: # %bar
+; CHECK-NEXT: ja .LBB0_2
+; CHECK-NEXT: .LBB0_3: # %bar
; CHECK-NEXT: retq
entry:
%cmp1 = fcmp oeq double bitcast (i64 ptrtoint (ptr @g to i64) to double), 0.000000e+00
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